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--                                                                            --
--  Abstract : Encoder Wrapper Layer for 6280/7280/8270/8290 without interrupts
--
------------------------------------------------------------------------------*/

/*------------------------------------------------------------------------------
    1. Include headers
------------------------------------------------------------------------------*/

#include "basetype.h"
#include "ewl.h"
#include "ewl_linux_lock.h"
#include "ewl_x280_common.h"
#include "encswhwregisters.h"

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>

#include <errno.h>

#include <sys/types.h>
#include <unistd.h>
#include <pthread.h>

#ifndef EWL_NO_HW_TIMEOUT
#define EWL_WAIT_HW_TIMEOUT 2   /* HW IRQ timeout in seconds */
#endif

extern volatile u32 asic_status;

/*******************************************************************************
 Function name   : EWLWaitHwRdy
 Description     : Poll the encoder interrupt register to notice IRQ
 Return type     : i32 
 Argument        : void
*******************************************************************************/
i32 EWLWaitHwRdy(const void *inst, u32 *slicesReady)
{
    hx280ewl_t *enc = (hx280ewl_t *) inst;
    volatile u32 irq_stats;
    u32 prevSlicesReady = 0;
    i32 ret = EWL_HW_WAIT_TIMEOUT;
    struct timespec t;
    u32 timeout = 1000;     /* Polling interval in microseconds */
    int loop = 100;         /* How many times to poll before timeout */
    u32 clrByWrite1 = (EWLReadReg(inst, BASE_HWFuse2) & HWCFGIrqClearSupport);

    assert(enc != NULL);

    PTRACE("EWLWaitHwRdy\n");
    (void) enc;

    /* The function should return when a slice is ready */
    if (slicesReady)
        prevSlicesReady = *slicesReady;

    if(timeout == (u32) (-1) )
    {
        loop = -1;   /* wait forever (almost) */
        timeout = 1000; /* 1ms polling interval */
    }

    t.tv_sec = 0;
    t.tv_nsec = timeout - t.tv_sec * 1000;
    t.tv_nsec = 100 * 1000 * 1000;

    do
    {
        /* Get the number of completed slices from ASIC registers. */
        if (slicesReady)
            *slicesReady = (EWLReadReg(enc, 21 * 4) >> 16) & 0xFF;

#ifdef PCIE_FPGA_VERIFICATION
        /* Only for verification purpose, to test input line buffer in hw-handshake mode or sw-irq is disabled. */
        if (pollInputLineBufTestFunc) pollInputLineBufTestFunc();
       #endif

        irq_stats = EWLReadReg(enc, 1 * 4);

        PTRACE("EWLWaitHw: IRQ stat = %08x\n", irq_stats);

        /* ignore the irq status of input line buffer in hw handshake mode */
        if ((irq_stats == ASIC_STATUS_LINE_BUFFER_DONE) && (EWLReadReg(enc, BASE_HEncInstantInput) & (1<<29)))
            continue;

        if((irq_stats & ASIC_STATUS_ALL))
        {
            u32 i;
            u32 irq_status, clr_stats;
            for(i = 0; i < enc->regSize; i += 4) 
            {
              enc->regMirror[i/4] = EWLReadReg(enc, i);
            }
            
            /* clear the status bits */
            irq_status = enc->regMirror[1];
            if (clrByWrite1)
                clr_stats = irq_status;
            else
                clr_stats = irq_status & (~0xf7d);
                
            EWLWriteReg(inst, 0x04, clr_stats);

            ret = EWL_OK;
            loop = 0;
        }

        if (slicesReady)
        {
            if (*slicesReady > prevSlicesReady)
            {
                ret = EWL_OK;
                loop = 0;
            }
        }

        if (loop)
        {
            if(nanosleep(&t, NULL) != 0) 
            {
                PTRACE("EWLWaitHw: Sleep interrupted!\n");
            }
        }
    }
    while(loop--);

    asic_status = irq_stats; /* update the buffered asic status */

    if (slicesReady) 
    {
        PTRACE("EWLWaitHw: slicesReady = %d\n", *slicesReady);
    }
    PTRACE("EWLWaitHw: asic_status = %x\n", asic_status);
    PTRACE("EWLWaitHw: OK!\n");

    return ret;
}
