/*
** ###################################################################
**     Processor:           MIMX8QM6AVUFF
**     Compilers:           Keil ARM C/C++ Compiler
**                          GNU C Compiler
**                          IAR ANSI C/C++ Compiler for ARM
**
**     Reference manual:    IMX8QMRM, Rev. E, Jun. 2018
**     Version:             rev. 4.0, 2018-08-30
**     Build:               b190927
**
**     Abstract:
**         CMSIS Peripheral Access Layer for MIMX8QM6_cm4_core1
**
**     Copyright 1997-2016 Freescale Semiconductor, Inc.
**     Copyright 2016-2018 NXP
**     All rights reserved.
**
**     SPDX-License-Identifier: BSD-3-Clause
**
**     http:                 www.nxp.com
**     mail:                 support@nxp.com
**
**     Revisions:
**     - rev. 1.0 (2016-06-02)
**         Initial version.
**     - rev. 2.0 (2017-05-04)
**         RevA Header ER
**     - rev. 3.0 (2018-01-29)
**         RevB Header ER
**     - rev. 4.0 (2018-08-30)
**         RevC Header EAR
**
** ###################################################################
*/

/*!
 * @file MIMX8QM6_cm4_core1.h
 * @version 4.0
 * @date 2018-08-30
 * @brief CMSIS Peripheral Access Layer for MIMX8QM6_cm4_core1
 *
 * CMSIS Peripheral Access Layer for MIMX8QM6_cm4_core1
 */

#ifndef _MIMX8QM6_CM4_CORE1_H_
#define _MIMX8QM6_CM4_CORE1_H_                   /**< Symbol preventing repeated inclusion */

/** Memory map major version (memory maps with equal major version number are
 * compatible) */
#define MCU_MEM_MAP_VERSION 0x0400U
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0000U


/* ----------------------------------------------------------------------------
   -- Interrupt vector numbers
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
 * @{
 */

/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 611                /**< Number of interrupts in the Vector table */

typedef enum IRQn {
  /* Auxiliary constants */
  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */

  /* Core interrupts */
  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */

  /* Device specific interrupts */
  Reserved16_IRQn              = 0,                /**< Reserved */
  Reserved17_IRQn              = 1,                /**< Reserved */
  Reserved18_IRQn              = 2,                /**< Reserved */
  Reserved19_IRQn              = 3,                /**< Reserved */
  Reserved20_IRQn              = 4,                /**< Reserved */
  M4_1_MCM_IRQn                = 5,                /**< MCM IRQ */
  Reserved22_IRQn              = 6,                /**< Reserved */
  Reserved23_IRQn              = 7,                /**< Reserved */
  Reserved24_IRQn              = 8,                /**< Reserved */
  Reserved25_IRQn              = 9,                /**< Reserved */
  Reserved26_IRQn              = 10,               /**< Reserved */
  Reserved27_IRQn              = 11,               /**< Reserved */
  Reserved28_IRQn              = 12,               /**< Reserved */
  Reserved29_IRQn              = 13,               /**< Reserved */
  Reserved30_IRQn              = 14,               /**< Reserved */
  Reserved31_IRQn              = 15,               /**< Reserved */
  Reserved32_IRQn              = 16,               /**< Reserved */
  Reserved33_IRQn              = 17,               /**< Reserved */
  Reserved34_IRQn              = 18,               /**< Reserved */
  M4_1_TPM_IRQn                = 19,               /**< Timer PWM Module */
  Reserved36_IRQn              = 20,               /**< Reserved */
  Reserved37_IRQn              = 21,               /**< Reserved */
  M4_1_LPIT_IRQn               = 22,               /**< Low-Power Periodic Interrupt Timer */
  Reserved39_IRQn              = 23,               /**< Reserved */
  Reserved40_IRQn              = 24,               /**< Reserved */
  M4_1_LPUART_IRQn             = 25,               /**< Low Power UART */
  Reserved42_IRQn              = 26,               /**< Reserved */
  M4_1_LPI2C_IRQn              = 27,               /**< Low-Power I2C - Logical OR of master and slave interrupts */
  Reserved44_IRQn              = 28,               /**< Reserved */
  M4_1_MU0_B0_IRQn             = 29,               /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 0, Logical OR of all general-purpose, TX, and RX interrupts */
  Reserved46_IRQn              = 30,               /**< Reserved */
  Reserved47_IRQn              = 31,               /**< Reserved */
  IRQSTEER_0_IRQn              = 32,               /**< External interrupt 0 */
  IRQSTEER_1_IRQn              = 33,               /**< External interrupt 1 */
  IRQSTEER_2_IRQn              = 34,               /**< External interrupt 2 */
  IRQSTEER_3_IRQn              = 35,               /**< External interrupt 3 */
  IRQSTEER_4_IRQn              = 36,               /**< External interrupt 4 */
  IRQSTEER_5_IRQn              = 37,               /**< External interrupt 5 */
  IRQSTEER_6_IRQn              = 38,               /**< External interrupt 6 */
  IRQSTEER_7_IRQn              = 39,               /**< External interrupt 7 */
  Reserved56_IRQn              = 40,               /**< Reserved */
  Reserved57_IRQn              = 41,               /**< Reserved */
  Reserved58_IRQn              = 42,               /**< Reserved */
  Reserved59_IRQn              = 43,               /**< Reserved */
  M4_1_MU0_B1_IRQn             = 44,               /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 1, Logical OR of all general-purpose, TX, and RX interrupts */
  M4_1_MU0_B2_IRQn             = 45,               /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 2, Logical OR of all general-purpose, TX, and RX interrupts */
  M4_1_MU0_B3_IRQn             = 46,               /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 3, Logical OR of all general-purpose, TX, and RX interrupts */
  Reserved63_IRQn              = 47,               /**< Reserved */
  Reserved64_IRQn              = 48,               /**< Reserved */
  M4_1_MU1_A_IRQn              = 49,               /**< Messaging Unit 1 (IPC with System Controller) - Side A (MCU), Logical OR of all general-purpose, TX, and RX interrupts */
  M4_1_SW_IRQn                 = 50,               /**< Software interrupt (asserted/cleared via NVIC registers, INTISR[50] input tied low) */
  A53_NEXTERRIRQ_IRQn          = 83,               /**< Shared Int Source nEXTERRIRQ from A53 Sub-System */
  A53_NINTERRIRQ_IRQn          = 84,               /**< Shared Int Source nINTERRIRQ from A53 Sub-System */
  A72_NEXTERRIRQ_IRQn          = 85,               /**< Shared Int Source nEXTERRIRQ from A72 Sub-System */
  A72_NINTERRIRQ_IRQn          = 86,               /**< Shared Int Source nINTERRIRQ from A72 Sub-System */
  VPU_NEXTERRIRQ_IRQn          = 87,               /**< Shared Int Source nEXTERRIRQ from VPU Sub-System */
  CCI_NERRORIRQ_IRQn           = 91,               /**< Shared Int Source nERRORIRQ from CCI Sub-System */
  CCI_NEVNTCNTOVERFLOW0_IRQn   = 92,               /**< Shared Int Source nEVNTCNTOVERFLOW[0] from CCI Sub-System */
  CCI_NEVNTCNTOVERFLOW1_IRQn   = 93,               /**< Shared Int Source nEVNTCNTOVERFLOW[1] from CCI Sub-System */
  CCI_NEVNTCNTOVERFLOW2_IRQn   = 94,               /**< Shared Int Source nEVNTCNTOVERFLOW[2] from CCI Sub-System */
  CCI_NEVNTCNTOVERFLOW3_IRQn   = 95,               /**< Shared Int Source nEVNTCNTOVERFLOW[3] from CCI Sub-System */
  CCI_NEVNTCNTOVERFLOW4_IRQn   = 96,               /**< Shared Int Source nEVNTCNTOVERFLOW[4] from CCI Sub-System */
  M4_0_INT_OUT0_IRQn           = 99,               /**< Shared Int Source INT_OUT[0] from M4_0 Sub-System */
  M4_0_INT_OUT1_IRQn           = 100,              /**< Shared Int Source INT_OUT[1] from M4_0 Sub-System */
  M4_0_INT_OUT2_IRQn           = 101,              /**< Shared Int Source INT_OUT[2] from M4_0 Sub-System */
  M4_0_INT_OUT3_IRQn           = 102,              /**< Shared Int Source INT_OUT[3] from M4_0 Sub-System */
  M4_0_INT_OUT4_IRQn           = 103,              /**< Shared Int Source INT_OUT[4] from M4_0 Sub-System */
  M4_0_INT_OUT5_IRQn           = 104,              /**< Shared Int Source INT_OUT[5] from M4_0 Sub-System */
  M4_0_INT_OUT6_IRQn           = 105,              /**< Shared Int Source INT_OUT[6] from M4_0 Sub-System */
  M4_0_INT_OUT7_IRQn           = 106,              /**< Shared Int Source INT_OUT[7] from M4_0 Sub-System */
  M4_1_INT_OUT0_IRQn           = 107,              /**< Shared Int Source INT_OUT[0] from M4_1 Sub-System */
  M4_1_INT_OUT1_IRQn           = 108,              /**< Shared Int Source INT_OUT[1] from M4_1 Sub-System */
  M4_1_INT_OUT2_IRQn           = 109,              /**< Shared Int Source INT_OUT[2] from M4_1 Sub-System */
  M4_1_INT_OUT3_IRQn           = 110,              /**< Shared Int Source INT_OUT[3] from M4_1 Sub-System */
  M4_1_INT_OUT4_IRQn           = 111,              /**< Shared Int Source INT_OUT[4] from M4_1 Sub-System */
  M4_1_INT_OUT5_IRQn           = 112,              /**< Shared Int Source INT_OUT[5] from M4_1 Sub-System */
  M4_1_INT_OUT6_IRQn           = 113,              /**< Shared Int Source INT_OUT[6] from M4_1 Sub-System */
  M4_1_INT_OUT7_IRQn           = 114,              /**< Shared Int Source INT_OUT[7] from M4_1 Sub-System */
  DBLOG_COMB_IRPT_NS_IRQn      = 115,              /**< Shared Int Source comb_irpt_ns from DBLog Sub-System */
  DBLOG_COMB_IRPT_S_IRQn       = 116,              /**< Shared Int Source comb_irpt_s from DBLog Sub-System */
  DBLOG_GBL_FLT_IRPT_NS_IRQn   = 117,              /**< Shared Int Source gbl_flt_irpt_ns from DBLog Sub-System */
  DBLOG_GBL_FLT_IRPT_S_IRQn    = 118,              /**< Shared Int Source gbl_flt_irpt_s from DBLog Sub-System */
  DBLOG_PERF_IRPT_IMX8_0_IRQn  = 119,              /**< Shared Int Source perf_irpt_imx8_0 from DBLog Sub-System */
  DBLOG_PERF_IRPT_IMX8_1_IRQn  = 120,              /**< Shared Int Source perf_irpt_imx8_1 from DBLog Sub-System */
  DBLOG_PERF_IRPT_IMX8_2_IRQn  = 121,              /**< Shared Int Source perf_irpt_imx8_2 from DBLog Sub-System */
  DBLOG_PERF_IRPT_IMX8_3_IRQn  = 122,              /**< Shared Int Source perf_irpt_imx8_3 from DBLog Sub-System */
  DISPLAY0_INT_OUT0_IRQn       = 123,              /**< Shared Int Source INT_OUT[0] from Display0 Sub-System */
  DISPLAY0_INT_OUT1_IRQn       = 124,              /**< Shared Int Source INT_OUT[1] from Display0 Sub-System */
  DISPLAY0_INT_OUT2_IRQn       = 125,              /**< Shared Int Source INT_OUT[2] from Display0 Sub-System */
  DISPLAY0_INT_OUT3_IRQn       = 126,              /**< Shared Int Source INT_OUT[3] from Display0 Sub-System */
  DISPLAY0_INT_OUT4_IRQn       = 127,              /**< Shared Int Source INT_OUT[4] from Display0 Sub-System */
  DISPLAY0_INT_OUT5_IRQn       = 128,              /**< Shared Int Source INT_OUT[5] from Display0 Sub-System */
  DISPLAY0_INT_OUT6_IRQn       = 129,              /**< Shared Int Source INT_OUT[6] from Display0 Sub-System */
  DISPLAY0_INT_OUT7_IRQn       = 130,              /**< Shared Int Source INT_OUT[7] from Display0 Sub-System */
  DISPLAY0_RESERVED_IRQn       = 131,              /**< Shared Int Source Reserved from Display0 Sub-System */
  DISPLAY0_INT_OUT9_IRQn       = 132,              /**< Shared Int Source INT_OUT[9] from Display0 Sub-System */
  DISPLAY0_INT_OUT10_IRQn      = 133,              /**< Shared Int Source INT_OUT[10] from Display0 Sub-System */
  DISPLAY0_INT_OUT11_IRQn      = 134,              /**< Shared Int Source INT_OUT[11] from Display0 Sub-System */
  DISPLAY0_INT_OUT12_IRQn      = 135,              /**< Shared Int Source INT_OUT[12] from Display0 Sub-System */
  LVDS0_INT_OUT_IRQn           = 140,              /**< Shared Int Source INT_OUT from LVDS0 Sub-System */
  LVDS1_INT_OUT_IRQn           = 141,              /**< Shared Int Source INT_OUT from LVDS1 Sub-System */
  MIPI_DSI0_INT_OUT_IRQn       = 142,              /**< Shared Int Source INT_OUT from MIPI_DSI0 Sub-System */
  MIPI_DSI1_INT_OUT_IRQn       = 143,              /**< Shared Int Source INT_OUT from MIPI_DSI1 Sub-System */
  HDMI_TX_INT_OUT_IRQn         = 144,              /**< Shared Int Source INT_OUT from HDMI_TX Sub-System */
  GPU0_XAQ2_INTR_IRQn          = 147,              /**< Shared Int Source xaq2_intr from GPU0 Sub-System */
  GPU1_XAQ2_INTR_IRQn          = 148,              /**< Shared Int Source xaq2_intr from GPU1 Sub-System */
  DMA_EDMA0_INT_IRQn           = 149,              /**< Shared Int Source eDMA0_INT from DMA Sub-System */
  DMA_EDMA0_ERR_INT_IRQn       = 150,              /**< Shared Int Source eDMA0_ERR_INT from DMA Sub-System */
  DMA_EDMA1_INT_IRQn           = 151,              /**< Shared Int Source eDMA1_INT from DMA Sub-System */
  DMA_EDMA1_ERR_INT_IRQn       = 152,              /**< Shared Int Source eDMA1_ERR_INT from DMA Sub-System */
  HSIO_PCIEA_MSI_CTRL_INT_IRQn = 153,              /**< Shared Int Source PCIeA_MSI_CTRL_INT from HSIO Sub-System */
  HSIO_PCIEA_CLK_REQ_INT_IRQn  = 154,              /**< Shared Int Source PCIeA_CLK_REQ_INT from HSIO Sub-System */
  HSIO_PCIEA_DMA_INT_IRQn      = 155,              /**< Shared Int Source PCIeA_DMA_INT from HSIO Sub-System */
  HSIO_PCIEA_INT_D_IRQn        = 156,              /**< Shared Int Source PCIeA_INT_D from HSIO Sub-System */
  HSIO_PCIEA_INT_C_IRQn        = 157,              /**< Shared Int Source PCIeA_INT_C from HSIO Sub-System */
  HSIO_PCIEA_INT_B_IRQn        = 158,              /**< Shared Int Source PCIeA_INT_B from HSIO Sub-System */
  HSIO_PCIEA_INT_A_IRQn        = 159,              /**< Shared Int Source PCIeA_INT_A from HSIO Sub-System */
  HSIO_PCIEA_SMLH_REQ_RST_IRQn = 160,              /**< Shared Int Source PCIeA_SMLH_REQ_RST from HSIO Sub-System */
  HSIO_PCIEA_GPIO_WAKEUP0_IRQn = 161,              /**< Shared Int Source PCIeA_GPIO_WAKEUP[0] from HSIO Sub-System */
  HSIO_PCIEA_GPIO_WAKEUP1_IRQn = 162,              /**< Shared Int Source PCIeA_GPIO_WAKEUP[1] from HSIO Sub-System */
  LSIO_GPT0_INT_IRQn           = 163,              /**< Shared Int Source GPT0_INT from LSIO Sub-System */
  LSIO_GPT1_INT_IRQn           = 164,              /**< Shared Int Source GPT1_INT from LSIO Sub-System */
  LSIO_GPT2_INT_IRQn           = 165,              /**< Shared Int Source GPT2_INT from LSIO Sub-System */
  LSIO_GPT3_INT_IRQn           = 166,              /**< Shared Int Source GPT3_INT from LSIO Sub-System */
  LSIO_GPT4_INT_IRQn           = 167,              /**< Shared Int Source GPT4_INT from LSIO Sub-System */
  LSIO_KPP_INT_IRQn            = 168,              /**< Shared Int Source KPP_INT from LSIO Sub-System */
  HSIO_SATA_INT0_IRQn          = 171,              /**< Shared Int Source SATA_INT[0] from HSIO Sub-System */
  HSIO_SATA_INT2_IRQn          = 172,              /**< Shared Int Source SATA_INT[2] from HSIO Sub-System */
  LSIO_OCTASPI0_INT_IRQn       = 175,              /**< Shared Int Source OctaSPI0_INT from LSIO Sub-System */
  LSIO_OCTASPI1_INT_IRQn       = 176,              /**< Shared Int Source OctaSPI1_INT from LSIO Sub-System */
  LSIO_PWM0_INT_IRQn           = 177,              /**< Shared Int Source PWM0_INT from LSIO Sub-System */
  LSIO_PWM1_INT_IRQn           = 178,              /**< Shared Int Source PWM1_INT from LSIO Sub-System */
  LSIO_PWM2_INT_IRQn           = 179,              /**< Shared Int Source PWM2_INT from LSIO Sub-System */
  LSIO_PWM3_INT_IRQn           = 180,              /**< Shared Int Source PWM3_INT from LSIO Sub-System */
  LSIO_PWM4_INT_IRQn           = 181,              /**< Shared Int Source PWM4_INT from LSIO Sub-System */
  LSIO_PWM5_INT_IRQn           = 182,              /**< Shared Int Source PWM5_INT from LSIO Sub-System */
  LSIO_PWM6_INT_IRQn           = 183,              /**< Shared Int Source PWM6_INT from LSIO Sub-System */
  LSIO_PWM7_INT_IRQn           = 184,              /**< Shared Int Source PWM7_INT from LSIO Sub-System */
  HSIO_PCIEB_MSI_CTRL_INT_IRQn = 185,              /**< Shared Int Source PCIeB_MSI_CTRL_INT from HSIO Sub-System */
  HSIO_PCIEB_CLK_REQ_INT_IRQn  = 186,              /**< Shared Int Source PCIeB_CLK_REQ_INT from HSIO Sub-System */
  HSIO_PCIEB_DMA_INT_IRQn      = 187,              /**< Shared Int Source PCIeB_DMA_INT from HSIO Sub-System */
  HSIO_PCIEB_INT_D_IRQn        = 188,              /**< Shared Int Source PCIeB_INT_D from HSIO Sub-System */
  HSIO_PCIEB_INT_C_IRQn        = 189,              /**< Shared Int Source PCIeB_INT_C from HSIO Sub-System */
  HSIO_PCIEB_INT_B_IRQn        = 190,              /**< Shared Int Source PCIeB_INT_B from HSIO Sub-System */
  HSIO_PCIEB_INT_A_IRQn        = 191,              /**< Shared Int Source PCIeB_INT_A from HSIO Sub-System */
  HSIO_PCIEB_SMLH_REQ_RST_IRQn = 192,              /**< Shared Int Source PCIeB_SMLH_REQ_RST from HSIO Sub-System */
  HSIO_PCIEB_GPIO_WAKEUP0_IRQn = 193,              /**< Shared Int Source PCIeB_GPIO_WAKEUP[0] from HSIO Sub-System */
  HSIO_PCIEB_GPIO_WAKEUP1_IRQn = 194,              /**< Shared Int Source PCIeB_GPIO_WAKEUP[1] from HSIO Sub-System */
  SCU_INT_OUT0_IRQn            = 195,              /**< Shared Int Source INT_OUT[0] from SCU Sub-System */
  SCU_INT_OUT1_IRQn            = 196,              /**< Shared Int Source INT_OUT[1] from SCU Sub-System */
  SCU_INT_OUT2_IRQn            = 197,              /**< Shared Int Source INT_OUT[2] from SCU Sub-System */
  SCU_INT_OUT3_IRQn            = 198,              /**< Shared Int Source INT_OUT[3] from SCU Sub-System */
  SCU_INT_OUT4_IRQn            = 199,              /**< Shared Int Source INT_OUT[4] from SCU Sub-System */
  SCU_INT_OUT5_IRQn            = 200,              /**< Shared Int Source INT_OUT[5] from SCU Sub-System */
  SCU_INT_OUT6_IRQn            = 201,              /**< Shared Int Source INT_OUT[6] from SCU Sub-System */
  SCU_INT_OUT7_IRQn            = 202,              /**< Shared Int Source INT_OUT[7] from SCU Sub-System */
  SCU_SYS_COUNT_INT0_IRQn      = 203,              /**< Shared Int Source SYS_COUNT_INT[0] from SCU Sub-System */
  SCU_SYS_COUNT_INT1_IRQn      = 204,              /**< Shared Int Source SYS_COUNT_INT[1] from SCU Sub-System */
  SCU_SYS_COUNT_INT2_IRQn      = 205,              /**< Shared Int Source SYS_COUNT_INT[2] from SCU Sub-System */
  SCU_SYS_COUNT_INT3_IRQn      = 206,              /**< Shared Int Source SYS_COUNT_INT[3] from SCU Sub-System */
  DRC0_DFI_ALERT_ERR_IRQn      = 211,              /**< Shared Int Source DFI_ALERT_ERR from DRC0 Sub-System */
  DRC1_DFI_ALERT_ERR_IRQn      = 212,              /**< Shared Int Source DFI_ALERT_ERR from DRC1 Sub-System */
  DRC0_PERF_CNT_FULL_IRQn      = 213,              /**< Shared Int Source PERF_CNT_FULL from DRC0 Sub-System */
  DRC1_PERF_CNT_FULL_IRQn      = 214,              /**< Shared Int Source PERF_CNT_FULL from DRC1 Sub-System */
  LSIO_GPIO_INT0_IRQn          = 219,              /**< Shared Int Source GPIO_INT[0] from LSIO Sub-System */
  LSIO_GPIO_INT1_IRQn          = 220,              /**< Shared Int Source GPIO_INT[1] from LSIO Sub-System */
  LSIO_GPIO_INT2_IRQn          = 221,              /**< Shared Int Source GPIO_INT[2] from LSIO Sub-System */
  LSIO_GPIO_INT3_IRQn          = 222,              /**< Shared Int Source GPIO_INT[3] from LSIO Sub-System */
  LSIO_GPIO_INT4_IRQn          = 223,              /**< Shared Int Source GPIO_INT[4] from LSIO Sub-System */
  LSIO_GPIO_INT5_IRQn          = 224,              /**< Shared Int Source GPIO_INT[5] from LSIO Sub-System */
  LSIO_GPIO_INT6_IRQn          = 225,              /**< Shared Int Source GPIO_INT[6] from LSIO Sub-System */
  LSIO_GPIO_INT7_IRQn          = 226,              /**< Shared Int Source GPIO_INT[7] from LSIO Sub-System */
  DISPLAY1_INT_OUT0_IRQn       = 235,              /**< Shared Int Source INT_OUT[0] from Display1 Sub-System */
  DISPLAY1_INT_OUT1_IRQn       = 236,              /**< Shared Int Source INT_OUT[1] from Display1 Sub-System */
  DISPLAY1_INT_OUT2_IRQn       = 237,              /**< Shared Int Source INT_OUT[2] from Display1 Sub-System */
  DISPLAY1_INT_OUT3_IRQn       = 238,              /**< Shared Int Source INT_OUT[3] from Display1 Sub-System */
  DISPLAY1_INT_OUT4_IRQn       = 239,              /**< Shared Int Source INT_OUT[4] from Display1 Sub-System */
  DISPLAY1_INT_OUT5_IRQn       = 240,              /**< Shared Int Source INT_OUT[5] from Display1 Sub-System */
  DISPLAY1_INT_OUT6_IRQn       = 241,              /**< Shared Int Source INT_OUT[6] from Display1 Sub-System */
  DISPLAY1_INT_OUT7_IRQn       = 242,              /**< Shared Int Source INT_OUT[7] from Display1 Sub-System */
  DISPLAY1_RESERVED_IRQn       = 243,              /**< Shared Int Source Reserved from Display1 Sub-System */
  DISPLAY1_INT_OUT9_IRQn       = 244,              /**< Shared Int Source INT_OUT[9] from Display1 Sub-System */
  DISPLAY1_INT_OUT10_IRQn      = 245,              /**< Shared Int Source INT_OUT[10] from Display1 Sub-System */
  DISPLAY1_INT_OUT11_IRQn      = 246,              /**< Shared Int Source INT_OUT[11] from Display1 Sub-System */
  DISPLAY1_INT_OUT12_IRQn      = 247,              /**< Shared Int Source INT_OUT[12] from Display1 Sub-System */
  VPU_SYS_INT0_IRQn            = 251,              /**< Shared Int Source SYS_INT[0] from VPU Sub-System */
  VPU_SYS_INT1_IRQn            = 252,              /**< Shared Int Source SYS_INT[1] from VPU Sub-System */
  LSIO_MU0_INT_IRQn            = 259,              /**< Shared Int Source MU0_INT from LSIO Sub-System */
  LSIO_MU1_INT_IRQn            = 260,              /**< Shared Int Source MU1_INT from LSIO Sub-System */
  LSIO_MU2_INT_IRQn            = 261,              /**< Shared Int Source MU2_INT from LSIO Sub-System */
  LSIO_MU3_INT_IRQn            = 262,              /**< Shared Int Source MU3_INT from LSIO Sub-System */
  LSIO_MU4_INT_IRQn            = 263,              /**< Shared Int Source MU4_INT from LSIO Sub-System */
  LSIO_MU5_INT_A_IRQn          = 267,              /**< Shared Int Source MU5_INT_A from LSIO Sub-System */
  LSIO_MU6_INT_A_IRQn          = 268,              /**< Shared Int Source MU6_INT_A from LSIO Sub-System */
  LSIO_MU7_INT_A_IRQn          = 269,              /**< Shared Int Source MU7_INT_A from LSIO Sub-System */
  LSIO_MU8_INT_A_IRQn          = 270,              /**< Shared Int Source MU8_INT_A from LSIO Sub-System */
  LSIO_MU9_INT_A_IRQn          = 271,              /**< Shared Int Source MU9_INT_A from LSIO Sub-System */
  LSIO_MU10_INT_A_IRQn         = 272,              /**< Shared Int Source MU10_INT_A from LSIO Sub-System */
  LSIO_MU11_INT_A_IRQn         = 273,              /**< Shared Int Source MU11_INT_A from LSIO Sub-System */
  LSIO_MU12_INT_A_IRQn         = 274,              /**< Shared Int Source MU12_INT_A from LSIO Sub-System */
  LSIO_MU13_INT_A_IRQn         = 275,              /**< Shared Int Source MU13_INT_A from LSIO Sub-System */
  LSIO_MU5_INT_B_IRQn          = 283,              /**< Shared Int Source MU5_INT_B from LSIO Sub-System */
  LSIO_MU6_INT_B_IRQn          = 284,              /**< Shared Int Source MU6_INT_B from LSIO Sub-System */
  LSIO_MU7_INT_B_IRQn          = 285,              /**< Shared Int Source MU7_INT_B from LSIO Sub-System */
  LSIO_MU8_INT_B_IRQn          = 286,              /**< Shared Int Source MU8_INT_B from LSIO Sub-System */
  LSIO_MU9_INT_B_IRQn          = 287,              /**< Shared Int Source MU9_INT_B from LSIO Sub-System */
  LSIO_MU10_INT_B_IRQn         = 288,              /**< Shared Int Source MU10_INT_B from LSIO Sub-System */
  LSIO_MU11_INT_B_IRQn         = 289,              /**< Shared Int Source MU11_INT_B from LSIO Sub-System */
  LSIO_MU12_INT_B_IRQn         = 290,              /**< Shared Int Source MU12_INT_B from LSIO Sub-System */
  LSIO_MU13_INT_B_IRQn         = 291,              /**< Shared Int Source MU13_INT_B from LSIO Sub-System */
  DMA_SPI0_INT_IRQn            = 299,              /**< Shared Int Source SPI0_INT from DMA Sub-System */
  DMA_SPI1_INT_IRQn            = 300,              /**< Shared Int Source SPI1_INT from DMA Sub-System */
  DMA_SPI2_INT_IRQn            = 301,              /**< Shared Int Source SPI2_INT from DMA Sub-System */
  DMA_SPI3_INT_IRQn            = 302,              /**< Shared Int Source SPI3_INT from DMA Sub-System */
  DMA_I2C0_INT_IRQn            = 303,              /**< Shared Int Source I2C0_INT from DMA Sub-System */
  DMA_I2C1_INT_IRQn            = 304,              /**< Shared Int Source I2C1_INT from DMA Sub-System */
  DMA_I2C2_INT_IRQn            = 305,              /**< Shared Int Source I2C2_INT from DMA Sub-System */
  DMA_I2C3_INT_IRQn            = 306,              /**< Shared Int Source I2C3_INT from DMA Sub-System */
  DMA_I2C4_INT_IRQn            = 307,              /**< Shared Int Source I2C4_INT from DMA Sub-System */
  DMA_UART0_INT_IRQn           = 308,              /**< Shared Int Source UART0_INT from DMA Sub-System */
  DMA_UART1_INT_IRQn           = 309,              /**< Shared Int Source UART1_INT from DMA Sub-System */
  DMA_UART2_INT_IRQn           = 310,              /**< Shared Int Source UART2_INT from DMA Sub-System */
  DMA_UART3_INT_IRQn           = 311,              /**< Shared Int Source UART3_INT from DMA Sub-System */
  DMA_UART4_INT_IRQn           = 312,              /**< Shared Int Source UART4_INT from DMA Sub-System */
  DMA_SIM0_INT_IRQn            = 313,              /**< Shared Int Source SIM0_INT from DMA Sub-System */
  DMA_SIM1_INT_IRQn            = 314,              /**< Shared Int Source SIM1_INT from DMA Sub-System */
  CONNECTIVITY_USDHC0_INT_IRQn = 315,              /**< Shared Int Source uSDHC0_INT from Connectivity Sub-System */
  CONNECTIVITY_USDHC1_INT_IRQn = 316,              /**< Shared Int Source uSDHC1_INT from Connectivity Sub-System */
  CONNECTIVITY_USDHC2_INT_IRQn = 317,              /**< Shared Int Source uSDHC2_INT from Connectivity Sub-System */
  DMA_FLEXCAN0_INT_IRQn        = 318,              /**< Shared Int Source FlexCAN0_INT from DMA Sub-System */
  DMA_FLEXCAN1_INT_IRQn        = 319,              /**< Shared Int Source FlexCAN1_INT from DMA Sub-System */
  DMA_FLEXCAN2_INT_IRQn        = 320,              /**< Shared Int Source FlexCAN2_INT from DMA Sub-System */
  DMA_FTM0_INT_IRQn            = 321,              /**< Shared Int Source FTM0_INT from DMA Sub-System */
  DMA_FTM1_INT_IRQn            = 322,              /**< Shared Int Source FTM1_INT from DMA Sub-System */
  DMA_ADC0_INT_IRQn            = 323,              /**< Shared Int Source ADC0_INT from DMA Sub-System */
  DMA_ADC1_INT_IRQn            = 324,              /**< Shared Int Source ADC1_INT from DMA Sub-System */
  DMA_EXTERNAL_DMA_INT_0_IRQn  = 325,              /**< Shared Int Source EXTERNAL_DMA_INT_0 from DMA Sub-System */
  DMA_EXTERNAL_DMA_INT_1_IRQn  = 326,              /**< Shared Int Source EXTERNAL_DMA_INT_1 from DMA Sub-System */
  DMA_EXTERNAL_DMA_INT_2_IRQn  = 327,              /**< Shared Int Source EXTERNAL_DMA_INT_2 from DMA Sub-System */
  DMA_EXTERNAL_DMA_INT_3_IRQn  = 328,              /**< Shared Int Source EXTERNAL_DMA_INT_3 from DMA Sub-System */
  DMA_EXTERNAL_DMA_INT_4_IRQn  = 329,              /**< Shared Int Source EXTERNAL_DMA_INT_4 from DMA Sub-System */
  DMA_EXTERNAL_DMA_INT_5_IRQn  = 330,              /**< Shared Int Source EXTERNAL_DMA_INT_5 from DMA Sub-System */
  CONNECTIVITY_ENET0_FRAME1_INT_IRQn = 339,        /**< Shared Int Source ENET0_FRAME1_INT from Connectivity Sub-System */
  CONNECTIVITY_ENET0_FRAME2_INT_IRQn = 340,        /**< Shared Int Source ENET0_FRAME2_INT from Connectivity Sub-System */
  CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQn = 341,  /**< Shared Int Source ENET0_FRAME0_EVENT_INT from Connectivity Sub-System */
  CONNECTIVITY_ENET0_TIMER_INT_IRQn = 342,         /**< Shared Int Source ENET0_TIMER_INT from Connectivity Sub-System */
  CONNECTIVITY_ENET1_FRAME1_INT_IRQn = 343,        /**< Shared Int Source ENET1_FRAME1_INT from Connectivity Sub-System */
  CONNECTIVITY_ENET1_FRAME2_INT_IRQn = 344,        /**< Shared Int Source ENET1_FRAME2_INT from Connectivity Sub-System */
  CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQn = 345,  /**< Shared Int Source ENET1_FRAME0_EVENT_INT from Connectivity Sub-System */
  CONNECTIVITY_ENET1_TIMER_INT_IRQn = 346,         /**< Shared Int Source ENET1_TIMER_INT from Connectivity Sub-System */
  CONNECTIVITY_DTCP_INT_IRQn   = 347,              /**< Shared Int Source DTCP_INT from Connectivity Sub-System */
  CONNECTIVITY_MLB_INT_IRQn    = 348,              /**< Shared Int Source MLB_INT from Connectivity Sub-System */
  CONNECTIVITY_MLB_AHB_INT_IRQn = 349,             /**< Shared Int Source MLB_AHB_INT from Connectivity Sub-System */
  CONNECTIVITY_USB_OTG_INT_IRQn = 350,             /**< Shared Int Source USB_OTG_INT from Connectivity Sub-System */
  CONNECTIVITY_USB_HOST_INT_IRQn = 351,            /**< Shared Int Source USB_HOST_INT from Connectivity Sub-System */
  CONNECTIVITY_UTMI_INT_IRQn   = 352,              /**< Shared Int Source UTMI_INT from Connectivity Sub-System */
  CONNECTIVITY_WAKEUP_INT_IRQn = 353,              /**< Shared Int Source WAKEUP_INT from Connectivity Sub-System */
  CONNECTIVITY_USB3_INT_IRQn   = 354,              /**< Shared Int Source USB3_INT from Connectivity Sub-System */
  CONNECTIVITY_ND_FLASH_BCH_INT_IRQn = 355,        /**< Shared Int Source ND_FLASH_BCH_INT from Connectivity Sub-System */
  CONNECTIVITY_ND_FLASH_GPMI_INT_IRQn = 356,       /**< Shared Int Source ND_FLASH_GPMI_INT from Connectivity Sub-System */
  CONNECTIVITY_APBHDMA_IRQn    = 357,              /**< Shared Int Source APBHDMA from Connectivity Sub-System */
  CONNECTIVITY_DMA_INT_IRQn    = 358,              /**< Shared Int Source DMA_INT from Connectivity Sub-System */
  CONNECTIVITY_DMA_ERR_INT_IRQn = 359,             /**< Shared Int Source DMA_ERR_INT from Connectivity Sub-System */
  IMAGING_MSI_INT_IRQn         = 371,              /**< Shared Int Source MSI_INT from Imaging Sub-System */
  IMAGING_PDMA_STREAM0_INT_IRQn = 380,             /**< Shared Int Source PDMA_STREAM0_INT from Imaging Sub-System */
  IMAGING_PDMA_STREAM1_INT_IRQn = 381,             /**< Shared Int Source PDMA_STREAM1_INT from Imaging Sub-System */
  IMAGING_PDMA_STREAM2_INT_IRQn = 382,             /**< Shared Int Source PDMA_STREAM2_INT from Imaging Sub-System */
  IMAGING_PDMA_STREAM3_INT_IRQn = 383,             /**< Shared Int Source PDMA_STREAM3_INT from Imaging Sub-System */
  IMAGING_PDMA_STREAM4_INT_IRQn = 384,             /**< Shared Int Source PDMA_STREAM4_INT from Imaging Sub-System */
  IMAGING_PDMA_STREAM5_INT_IRQn = 385,             /**< Shared Int Source PDMA_STREAM5_INT from Imaging Sub-System */
  IMAGING_PDMA_STREAM6_INT_IRQn = 386,             /**< Shared Int Source PDMA_STREAM6_INT from Imaging Sub-System */
  IMAGING_PDMA_STREAM7_INT_IRQn = 387,             /**< Shared Int Source PDMA_STREAM7_INT from Imaging Sub-System */
  IMAGING_MJPEG_ENC0_INT_IRQn  = 388,              /**< Shared Int Source MJPEG_ENC0_INT from Imaging Sub-System */
  IMAGING_MJPEG_ENC1_INT_IRQn  = 389,              /**< Shared Int Source MJPEG_ENC1_INT from Imaging Sub-System */
  IMAGING_MJPEG_ENC2_INT_IRQn  = 390,              /**< Shared Int Source MJPEG_ENC2_INT from Imaging Sub-System */
  IMAGING_MJPEG_ENC3_INT_IRQn  = 391,              /**< Shared Int Source MJPEG_ENC3_INT from Imaging Sub-System */
  IMAGING_MJPEG_DEC0_INT_IRQn  = 392,              /**< Shared Int Source MJPEG_DEC0_INT from Imaging Sub-System */
  IMAGING_MJPEG_DEC1_INT_IRQn  = 393,              /**< Shared Int Source MJPEG_DEC1_INT from Imaging Sub-System */
  IMAGING_MJPEG_DEC2_INT_IRQn  = 394,              /**< Shared Int Source MJPEG_DEC2_INT from Imaging Sub-System */
  IMAGING_MJPEG_DEC3_INT_IRQn  = 395,              /**< Shared Int Source MJPEG_DEC3_INT from Imaging Sub-System */
  AUDIO_SAI0_MOD_INT_IRQn      = 397,              /**< Shared Int Source SAI0_MOD_INT from Audio Sub-System */
  AUDIO_SAI0_DMA_INT_IRQn      = 398,              /**< Shared Int Source SAI0_DMA_INT from Audio Sub-System */
  AUDIO_SAI1_MOD_INT_IRQn      = 399,              /**< Shared Int Source SAI1_MOD_INT from Audio Sub-System */
  AUDIO_SAI1_DMA_INT_IRQn      = 400,              /**< Shared Int Source SAI1_DMA_INT from Audio Sub-System */
  AUDIO_SAI2_MOD_INT_IRQn      = 401,              /**< Shared Int Source SAI2_MOD_INT from Audio Sub-System */
  AUDIO_SAI2_DMA_INT_IRQn      = 402,              /**< Shared Int Source SAI2_DMA_INT from Audio Sub-System */
  MIPI_CSI0_OUT_INT_IRQn       = 403,              /**< Shared Int Source OUT_INT from MIPI_CSI0 Sub-System */
  MIPI_CSI1_OUT_INT_IRQn       = 404,              /**< Shared Int Source OUT_INT from MIPI_CSI1 Sub-System */
  HDMI_RX_OUT_INT_IRQn         = 405,              /**< Shared Int Source OUT_INT from HDMI_RX Sub-System */
  AUDIO_SAI3_MOD_INT_IRQn      = 406,              /**< Shared Int Source SAI3_MOD_INT from Audio Sub-System */
  AUDIO_SAI3_DMA_INT_IRQn      = 407,              /**< Shared Int Source SAI3_DMA_INT from Audio Sub-System */
  AUDIO_SAI_HDMI_RX_MOD_INT_IRQn = 408,            /**< Shared Int Source SAI_HDMI_RX_MOD_INT from Audio Sub-System */
  AUDIO_SAI_HDMI_RX_DMA_INT_IRQn = 409,            /**< Shared Int Source SAI_HDMI_RX_DMA_INT from Audio Sub-System */
  AUDIO_SAI_HDMI_TX_MOD_INT_IRQn = 410,            /**< Shared Int Source SAI_HDMI_TX_MOD_INT from Audio Sub-System */
  AUDIO_SAI_HDMI_TX_DMA_INT_IRQn = 411,            /**< Shared Int Source SAI_HDMI_TX_DMA_INT from Audio Sub-System */
  AUDIO_SAI6_MOD_INT_IRQn      = 412,              /**< Shared Int Source SAI6_MOD_INT from Audio Sub-System */
  AUDIO_SAI6_DMA_INT_IRQn      = 413,              /**< Shared Int Source SAI6_DMA_INT from Audio Sub-System */
  AUDIO_SAI7_MOD_INT_IRQn      = 414,              /**< Shared Int Source SAI7_MOD_INT from Audio Sub-System */
  AUDIO_SAI7_DMA_INT_IRQn      = 415,              /**< Shared Int Source SAI7_DMA_INT from Audio Sub-System */
  DMA_SPI0_MOD_INT_IRQn        = 419,              /**< Shared Int Source SPI0_MOD_INT from DMA Sub-System */
  DMA_SPI1_MOD_INT_IRQn        = 420,              /**< Shared Int Source SPI1_MOD_INT from DMA Sub-System */
  DMA_SPI2_MOD_INT_IRQn        = 421,              /**< Shared Int Source SPI2_MOD_INT from DMA Sub-System */
  DMA_SPI3_MOD_INT_IRQn        = 422,              /**< Shared Int Source SPI3_MOD_INT from DMA Sub-System */
  DMA_I2C0_MOD_INT_IRQn        = 423,              /**< Shared Int Source I2C0_MOD_INT from DMA Sub-System */
  DMA_I2C1_MOD_INT_IRQn        = 424,              /**< Shared Int Source I2C1_MOD_INT from DMA Sub-System */
  DMA_I2C2_MOD_INT_IRQn        = 425,              /**< Shared Int Source I2C2_MOD_INT from DMA Sub-System */
  DMA_I2C3_MOD_INT_IRQn        = 426,              /**< Shared Int Source I2C3_MOD_INT from DMA Sub-System */
  DMA_I2C4_MOD_INT_IRQn        = 427,              /**< Shared Int Source I2C4_MOD_INT from DMA Sub-System */
  DMA_UART0_MOD_INT_IRQn       = 428,              /**< Shared Int Source UART0_MOD_INT from DMA Sub-System */
  DMA_UART1_MOD_INT_IRQn       = 429,              /**< Shared Int Source UART1_MOD_INT from DMA Sub-System */
  DMA_UART2_MOD_INT_IRQn       = 430,              /**< Shared Int Source UART2_MOD_INT from DMA Sub-System */
  DMA_UART3_MOD_INT_IRQn       = 431,              /**< Shared Int Source UART3_MOD_INT from DMA Sub-System */
  DMA_UART4_MOD_INT_IRQn       = 432,              /**< Shared Int Source UART4_MOD_INT from DMA Sub-System */
  DMA_SIM0_MOD_INT_IRQn        = 433,              /**< Shared Int Source SIM0_MOD_INT from DMA Sub-System */
  DMA_SIM1_MOD_INT_IRQn        = 434,              /**< Shared Int Source SIM1_MOD_INT from DMA Sub-System */
  DMA_FLEXCAN0_MOD_INT_IRQn    = 435,              /**< Shared Int Source FLEXCAN0_MOD_INT from DMA Sub-System */
  DMA_FLEXCAN1_MOD_INT_IRQn    = 436,              /**< Shared Int Source FLEXCAN1_MOD_INT from DMA Sub-System */
  DMA_FLEXCAN2_MOD_INT_IRQn    = 437,              /**< Shared Int Source FLEXCAN2_MOD_INT from DMA Sub-System */
  DMA_FTM0_MOD_INT_IRQn        = 438,              /**< Shared Int Source FTM0_MOD_INT from DMA Sub-System */
  DMA_FTM1_MOD_INT_IRQn        = 439,              /**< Shared Int Source FTM1_MOD_INT from DMA Sub-System */
  DMA_ADC0_MOD_INT_IRQn        = 440,              /**< Shared Int Source ADC0_MOD_INT from DMA Sub-System */
  DMA_ADC1_MOD_INT_IRQn        = 441,              /**< Shared Int Source ADC1_MOD_INT from DMA Sub-System */
  DMA_FLEXCAN0_DMA_INT_IRQn    = 442,              /**< Shared Int Source FLEXCAN0_DMA_INT from DMA Sub-System */
  DMA_FLEXCAN1_DMA_INT_IRQn    = 443,              /**< Shared Int Source FLEXCAN1_DMA_INT from DMA Sub-System */
  DMA_FLEXCAN2_DMA_INT_IRQn    = 444,              /**< Shared Int Source FLEXCAN2_DMA_INT from DMA Sub-System */
  DMA_FTM0_DMA_INT_IRQn        = 445,              /**< Shared Int Source FTM0_DMA_INT from DMA Sub-System */
  DMA_FTM1_DMA_INT_IRQn        = 446,              /**< Shared Int Source FTM1_DMA_INT from DMA Sub-System */
  DMA_ADC0_DMA_INT_IRQn        = 447,              /**< Shared Int Source ADC0_DMA_INT from DMA Sub-System */
  DMA_ADC1_DMA_INT_IRQn        = 448,              /**< Shared Int Source ADC1_DMA_INT from DMA Sub-System */
  AUDIO_EDMA0_INT_IRQn         = 451,              /**< Shared Int Source eDMA0_INT from Audio Sub-System */
  AUDIO_EDMA0_ERR_INT_IRQn     = 452,              /**< Shared Int Source eDMA0_ERR_INT from Audio Sub-System */
  AUDIO_EDMA1_INT_IRQn         = 453,              /**< Shared Int Source eDMA1_INT from Audio Sub-System */
  AUDIO_EDMA1_ERR_INT_IRQn     = 454,              /**< Shared Int Source eDMA1_ERR_INT from Audio Sub-System */
  AUDIO_ASRC0_INT1_IRQn        = 455,              /**< Shared Int Source ASRC0_INT1 from Audio Sub-System */
  AUDIO_ASRC0_INT2_IRQn        = 456,              /**< Shared Int Source ASRC0_INT2 from Audio Sub-System */
  AUDIO_DMA0_CH0_INT_IRQn      = 457,              /**< Shared Int Source DMA0_CH0_INT from Audio Sub-System */
  AUDIO_DMA0_CH1_INT_IRQn      = 458,              /**< Shared Int Source DMA0_CH1_INT from Audio Sub-System */
  AUDIO_DMA0_CH2_INT_IRQn      = 459,              /**< Shared Int Source DMA0_CH2_INT from Audio Sub-System */
  AUDIO_DMA0_CH3_INT_IRQn      = 460,              /**< Shared Int Source DMA0_CH3_INT from Audio Sub-System */
  AUDIO_DMA0_CH4_INT_IRQn      = 461,              /**< Shared Int Source DMA0_CH4_INT from Audio Sub-System */
  AUDIO_DMA0_CH5_INT_IRQn      = 462,              /**< Shared Int Source DMA0_CH5_INT from Audio Sub-System */
  AUDIO_ASRC1_INT1_IRQn        = 463,              /**< Shared Int Source ASRC1_INT1 from Audio Sub-System */
  AUDIO_ASRC1_INT2_IRQn        = 464,              /**< Shared Int Source ASRC1_INT2 from Audio Sub-System */
  AUDIO_DMA1_CH0_INT_IRQn      = 465,              /**< Shared Int Source DMA1_CH0_INT from Audio Sub-System */
  AUDIO_DMA1_CH1_INT_IRQn      = 466,              /**< Shared Int Source DMA1_CH1_INT from Audio Sub-System */
  AUDIO_DMA1_CH2_INT_IRQn      = 467,              /**< Shared Int Source DMA1_CH2_INT from Audio Sub-System */
  AUDIO_DMA1_CH3_INT_IRQn      = 468,              /**< Shared Int Source DMA1_CH3_INT from Audio Sub-System */
  AUDIO_DMA1_CH4_INT_IRQn      = 469,              /**< Shared Int Source DMA1_CH4_INT from Audio Sub-System */
  AUDIO_DMA1_CH5_INT_IRQn      = 470,              /**< Shared Int Source DMA1_CH5_INT from Audio Sub-System */
  AUDIO_ESAI0_INT_IRQn         = 471,              /**< Shared Int Source ESAI0_INT from Audio Sub-System */
  AUDIO_ESAI1_INT_IRQn         = 472,              /**< Shared Int Source ESAI1_INT  from Audio Sub-System */
  AUDIO_UNUSED_IRQn            = 473,              /**< Shared Int Source Unused from Audio Sub-System */
  AUDIO_GPT0_INT_IRQn          = 474,              /**< Shared Int Source GPT0_INT from Audio Sub-System */
  AUDIO_GPT1_INT_IRQn          = 475,              /**< Shared Int Source GPT1_INT from Audio Sub-System */
  AUDIO_GPT2_INT_IRQn          = 476,              /**< Shared Int Source GPT2_INT from Audio Sub-System */
  AUDIO_GPT3_INT_IRQn          = 477,              /**< Shared Int Source GPT3_INT from Audio Sub-System */
  AUDIO_GPT4_INT_IRQn          = 478,              /**< Shared Int Source GPT4_INT from Audio Sub-System */
  AUDIO_GPT5_INT_IRQn          = 479,              /**< Shared Int Source GPT5_INT from Audio Sub-System */
  AUDIO_SAI0_INT_IRQn          = 480,              /**< Shared Int Source SAI0_INT from Audio Sub-System */
  AUDIO_SAI1_INT_IRQn          = 481,              /**< Shared Int Source SAI1_INT from Audio Sub-System */
  AUDIO_SAI2_INT_IRQn          = 482,              /**< Shared Int Source SAI2_INT from Audio Sub-System */
  AUDIO_SAI3_INT_IRQn          = 483,              /**< Shared Int Source SAI3_INT from Audio Sub-System */
  AUDIO_SAI_HDMI_RX_INT_IRQn   = 484,              /**< Shared Int Source SAI_HDMI_RX_INT from Audio Sub-System */
  AUDIO_SAI_HDMI_TX_INT_IRQn   = 485,              /**< Shared Int Source SAI_HDMI_TX_INT from Audio Sub-System */
  AUDIO_SAI6_INT_IRQn          = 486,              /**< Shared Int Source SAI6_INT from Audio Sub-System */
  AUDIO_SAI7_INT_IRQn          = 487,              /**< Shared Int Source SAI7_INT from Audio Sub-System */
  AUDIO_SPDIF0_RX_INT_IRQn     = 488,              /**< Shared Int Source SPDIF0_RX_INT from Audio Sub-System */
  AUDIO_SPDIF0_TX_INT_IRQn     = 489,              /**< Shared Int Source SPDIF0_TX_INT from Audio Sub-System */
  AUDIO_SPDIF1_RX_INT_IRQn     = 490,              /**< Shared Int Source SPDIF1_RX_INT from Audio Sub-System */
  AUDIO_SPDIF1_TX_INT_IRQn     = 491,              /**< Shared Int Source SPDIF1_TX_INT from Audio Sub-System */
  AUDIO_ESAI0_MOD_INT_IRQn     = 492,              /**< Shared Int Source ESAI0_MOD_INT from Audio Sub-System */
  AUDIO_ESAI0_DMA_INT_IRQn     = 493,              /**< Shared Int Source ESAI0_DMA_INT from Audio Sub-System */
  AUDIO_ESAI1_MOD_INT_IRQn     = 494,              /**< Shared Int Source ESAI1_MOD_INT from Audio Sub-System */
  AUDIO_ESAI1_DMA_INT_IRQn     = 495,              /**< Shared Int Source ESAI1_DMA_INT from Audio Sub-System */
  DMA_SPI0_DMA_RX_INT_IRQn     = 499,              /**< Shared Int Source SPI0_DMA_RX_INT from DMA Sub-System */
  DMA_SPI0_DMA_TX_INT_IRQn     = 500,              /**< Shared Int Source SPI0_DMA_TX_INT from DMA Sub-System */
  DMA_SPI1_DMA_RX_INT_IRQn     = 501,              /**< Shared Int Source SPI1_DMA_RX_INT from DMA Sub-System */
  DMA_SPI1_DMA_TX_INT_IRQn     = 502,              /**< Shared Int Source SPI1_DMA_TX_INT from DMA Sub-System */
  DMA_SPI2_DMA_RX_INT_IRQn     = 503,              /**< Shared Int Source SPI2_DMA_RX_INT from DMA Sub-System */
  DMA_SPI2_DMA_TX_INT_IRQn     = 504,              /**< Shared Int Source SPI2_DMA_TX_INT from DMA Sub-System */
  DMA_SPI3_DMA_RX_INT_IRQn     = 505,              /**< Shared Int Source SPI3_DMA_RX_INT from DMA Sub-System */
  DMA_SPI3_DMA_TX_INT_IRQn     = 506,              /**< Shared Int Source SPI3_DMA_TX_INT from DMA Sub-System */
  DMA_I2C0_DMA_RX_INT_IRQn     = 507,              /**< Shared Int Source I2C0_DMA_RX_INT from DMA Sub-System */
  DMA_I2C0_DMA_TX_INT_IRQn     = 508,              /**< Shared Int Source I2C0_DMA_TX_INT from DMA Sub-System */
  DMA_I2C1_DMA_RX_INT_IRQn     = 509,              /**< Shared Int Source I2C1_DMA_RX_INT from DMA Sub-System */
  DMA_I2C1_DMA_TX_INT_IRQn     = 510,              /**< Shared Int Source I2C1_DMA_TX_INT from DMA Sub-System */
  DMA_I2C2_DMA_RX_INT_IRQn     = 511,              /**< Shared Int Source I2C2_DMA_RX_INT from DMA Sub-System */
  DMA_I2C2_DMA_TX_INT_IRQn     = 512,              /**< Shared Int Source I2C2_DMA_TX_INT from DMA Sub-System */
  DMA_I2C3_DMA_RX_INT_IRQn     = 513,              /**< Shared Int Source I2C3_DMA_RX_INT from DMA Sub-System */
  DMA_I2C3_DMA_TX_INT_IRQn     = 514,              /**< Shared Int Source I2C3_DMA_TX_INT from DMA Sub-System */
  DMA_I2C4_DMA_RX_INT_IRQn     = 515,              /**< Shared Int Source I2C4_DMA_RX_INT from DMA Sub-System */
  DMA_I2C4_DMA_TX_INT_IRQn     = 516,              /**< Shared Int Source I2C4_DMA_TX_INT from DMA Sub-System */
  DMA_UART0_DMA_RX_INT_IRQn    = 517,              /**< Shared Int Source UART0_DMA_RX_INT from DMA Sub-System */
  DMA_UART0_DMA_TX_INT_IRQn    = 518,              /**< Shared Int Source UART0_DMA_TX_INT from DMA Sub-System */
  DMA_UART1_DMA_RX_INT_IRQn    = 519,              /**< Shared Int Source UART1_DMA_RX_INT from DMA Sub-System */
  DMA_UART1_DMA_TX_INT_IRQn    = 520,              /**< Shared Int Source UART1_DMA_TX_INT from DMA Sub-System */
  DMA_UART2_DMA_RX_INT_IRQn    = 521,              /**< Shared Int Source UART2_DMA_RX_INT from DMA Sub-System */
  DMA_UART2_DMA_TX_INT_IRQn    = 522,              /**< Shared Int Source UART2_DMA_TX_INT from DMA Sub-System */
  DMA_UART3_DMA_RX_INT_IRQn    = 523,              /**< Shared Int Source UART3_DMA_RX_INT from DMA Sub-System */
  DMA_UART3_DMA_TX_INT_IRQn    = 524,              /**< Shared Int Source UART3_DMA_TX_INT from DMA Sub-System */
  DMA_UART4_DMA_RX_INT_IRQn    = 525,              /**< Shared Int Source UART4_DMA_RX_INT from DMA Sub-System */
  DMA_UART4_DMA_TX_INT_IRQn    = 526,              /**< Shared Int Source UART4_DMA_TX_INT from DMA Sub-System */
  DMA_SIM0_DMA_RX_INT_IRQn     = 527,              /**< Shared Int Source SIM0_DMA_RX_INT from DMA Sub-System */
  DMA_SIM0_DMA_TX_INT_IRQn     = 528,              /**< Shared Int Source SIM0_DMA_TX_INT from DMA Sub-System */
  DMA_SIM1_DMA_RX_INT_IRQn     = 529,              /**< Shared Int Source SIM1_DMA_RX_INT from DMA Sub-System */
  DMA_SIM1_DMA_TX_INT_IRQn     = 530,              /**< Shared Int Source SIM1_DMA_TX_INT from DMA Sub-System */
  SECURITY_MU1_A_INT_IRQn      = 531,              /**< Shared Int Source MU1_A_INT from Security Sub-System */
  SECURITY_MU2_A_INT_IRQn      = 532,              /**< Shared Int Source MU2_A_INT from Security Sub-System */
  SECURITY_MU3_A_INT_IRQn      = 533,              /**< Shared Int Source MU3_A_INT from Security Sub-System */
  SECURITY_CAAM_INT0_IRQn      = 534,              /**< Shared Int Source CAAM_INT0 from Security Sub-System */
  SECURITY_CAAM_INT1_IRQn      = 535,              /**< Shared Int Source CAAM_INT1 from Security Sub-System */
  SECURITY_CAAM_INT2_IRQn      = 536,              /**< Shared Int Source CAAM_INT2 from Security Sub-System */
  SECURITY_CAAM_INT3_IRQn      = 537,              /**< Shared Int Source CAAM_INT3 from Security Sub-System */
  SECURITY_CAAM_RTIC_INT_IRQn  = 538,              /**< Shared Int Source CAAM_RTIC_INT from Security Sub-System */
  AUDIO_SPDIF0_RX_MOD_INT_IRQn = 539,              /**< Shared Int Source SPDIF0_RX_MOD_INT from Audio Sub-System */
  AUDIO_SPDIF0_RX_DMA_INT_IRQn = 540,              /**< Shared Int Source SPDIF0_RX_DMA_INT from Audio Sub-System */
  AUDIO_SPDIF0_TX_MOD_INT_IRQn = 541,              /**< Shared Int Source SPDIF0_TX_MOD_INT from Audio Sub-System */
  AUDIO_SPDIF0_TX_DMA_INT_IRQn = 542,              /**< Shared Int Source SPDIF0_TX_DMA_INT from Audio Sub-System */
  AUDIO_SPDIF1_RX_MOD_INT_IRQn = 543,              /**< Shared Int Source SPDIF1_RX_MOD_INT from Audio Sub-System */
  AUDIO_SPDIF1_RX_DMA_INT_IRQn = 544,              /**< Shared Int Source SPDIF1_RX_DMA_INT from Audio Sub-System */
  AUDIO_SPDIF1_TX_MOD_INT_IRQn = 545,              /**< Shared Int Source SPDIF1_TX_MOD_INT from Audio Sub-System */
  AUDIO_SPDIF1_TX_DMA_INT_IRQn = 546,              /**< Shared Int Source SPDIF1_TX_DMA_INT from Audio Sub-System */
  VPU_VPU_INT_0_IRQn           = 547,              /**< Shared Int Source VPU_INT_0 from VPU Sub-System */
  VPU_VPU_INT_1_IRQn           = 548,              /**< Shared Int Source VPU_INT_1 from VPU Sub-System */
  VPU_VPU_INT_2_IRQn           = 549,              /**< Shared Int Source VPU_INT_2 from VPU Sub-System */
  VPU_VPU_INT_3_IRQn           = 550,              /**< Shared Int Source VPU_INT_3 from VPU Sub-System */
  VPU_VPU_INT_4_IRQn           = 551,              /**< Shared Int Source VPU_INT_4 from VPU Sub-System */
  VPU_VPU_INT_5_IRQn           = 552,              /**< Shared Int Source VPU_INT_5 from VPU Sub-System */
  VPU_VPU_INT_6_IRQn           = 553,              /**< Shared Int Source VPU_INT_6 from VPU Sub-System */
  VPU_VPU_INT_7_IRQn           = 554,              /**< Shared Int Source VPU_INT_7 from VPU Sub-System */
  M4_1_INTMUX_SOURCE_TPM_IRQn  = 564,              /**< INTMUX Input source: TPM Interrupt */
  M4_1_INTMUX_SOURCE_LPIT_IRQn = 567,              /**< INTMUX Input source: LPIT Interrupt */
  M4_1_INTMUX_SOURCE_LPUART_IRQn = 570,            /**< INTMUX Input source: LPUART Interrupt */
  M4_1_INTMUX_SOURCE_LPI2C_IRQn = 572,             /**< INTMUX Input source: LPI2C Interrupt */
  M4_1_INTMUX_SOURCE_MU0_A3_IRQn = 591,            /**< INTMUX Input source: MU0_A3 Interrupt */
  M4_1_INTMUX_SOURCE_MU0_A2_IRQn = 592,            /**< INTMUX Input source: MU0_A2 Interrupt */
  M4_1_INTMUX_SOURCE_MU0_A1_IRQn = 593,            /**< INTMUX Input source: MU0_A1 Interrupt */
  M4_1_INTMUX_SOURCE_MU0_A0_IRQn = 594             /**< INTMUX Input source: MU0_A0 Interrupt */
} IRQn_Type;

/*!
 * @}
 */ /* end of group Interrupt_vector_numbers */


/* ----------------------------------------------------------------------------
   -- Configuration of the Cortex-M4 Processor and Core Peripherals
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals
 * @{
 */

#define __CM4_REV                      0x0001    /**< Core revision r0p1 */
#define __MPU_PRESENT                  1         /**< MPU present or not */
#define __NVIC_PRIO_BITS               4         /**< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig         0         /**< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT                  1         /**< FPU present or not */

#include "core_cm4.h"                  /* Core Peripheral Access Layer */
#include "system_MIMX8QM6_cm4_core1.h" /* Device specific configuration file */

/*!
 * @}
 */ /* end of group Cortex_Core_Configuration */


/* ----------------------------------------------------------------------------
   -- Device Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
 * @{
 */


/*
** Start of section using anonymous unions
*/

#if defined(__ARMCC_VERSION)
  #if (__ARMCC_VERSION >= 6010050)
    #pragma clang diagnostic push
  #else
    #pragma push
    #pragma anon_unions
  #endif
#elif defined(__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma language=extended
#else
  #error Not supported compiler type
#endif

/* ----------------------------------------------------------------------------
   -- ACM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ACM_Peripheral_Access_Layer ACM Peripheral Access Layer
 * @{
 */

/** ACM - Register Layout Typedef */
typedef struct {
  __IO uint32_t AUD_CLK0_SEL;                      /**< Audio Clock Multiplexer #0 selector, offset: 0x0 */
       uint8_t RESERVED_0[65532];
  __IO uint32_t AUD_CLK1_SEL;                      /**< Audio Clock Multiplexer #1 selector, offset: 0x10000 */
       uint8_t RESERVED_1[65532];
  __IO uint32_t MCLKOUT0_SEL;                      /**< Master Clock Output #0 selector, offset: 0x20000 */
       uint8_t RESERVED_2[65532];
  __IO uint32_t MCLKOUT1_SEL;                      /**< Master Clock Output #1 selector, offset: 0x30000 */
       uint8_t RESERVED_3[65532];
  __IO uint32_t ASRC0_CLK_SEL;                     /**< ASRC #0 clock selector, offset: 0x40000 */
       uint8_t RESERVED_4[131068];
  __IO uint32_t ESAI0_CLK_SEL;                     /**< ESAI #0 clock selector, offset: 0x60000 */
       uint8_t RESERVED_5[65532];
  __IO uint32_t ESAI1_CLK_SEL;                     /**< ESAI #1 clock selector, offset: 0x70000 */
       uint8_t RESERVED_6[65532];
  __IO uint32_t GPT0_CLK_SEL;                      /**< GP Timer #0 clock selector, offset: 0x80000 */
  __IO uint32_t GPT0_CAPIN1_SEL;                   /**< GP Timer #0 event capture input #1 selector, offset: 0x80004 */
  __IO uint32_t GPT0_CAPIN2_SEL;                   /**< GP Timer #0 event capture input #2 selector, offset: 0x80008 */
       uint8_t RESERVED_7[65524];
  __IO uint32_t GPT1_CLK_SEL;                      /**< GP Timer #1 clock selector, offset: 0x90000 */
  __IO uint32_t GPT1_CAPIN1_SEL;                   /**< GP Timer #1 event capture input #1 selector, offset: 0x90004 */
  __IO uint32_t GPT1_CAPIN2_SEL;                   /**< GP Timer #1 event capture input #2 selector, offset: 0x90008 */
       uint8_t RESERVED_8[65524];
  __IO uint32_t GPT2_CLK_SEL;                      /**< GP Timer #2 clock selector, offset: 0xA0000 */
  __IO uint32_t GPT2_CAPIN1_SEL;                   /**< GP Timer #2 event capture input #1 selector, offset: 0xA0004 */
  __IO uint32_t GPT2_CAPIN2_SEL;                   /**< GP Timer #2 event capture input #2 selector, offset: 0xA0008 */
       uint8_t RESERVED_9[65524];
  __IO uint32_t GPT3_CLK_SEL;                      /**< GP Timer #3 clock selector, offset: 0xB0000 */
  __IO uint32_t GPT3_CAPIN1_SEL;                   /**< GP Timer #3 event capture input #1 selector, offset: 0xB0004 */
  __IO uint32_t GPT3_CAPIN2_SEL;                   /**< GP Timer #3 event capture input #2 selector, offset: 0xB0008 */
       uint8_t RESERVED_10[65524];
  __IO uint32_t GPT4_CLK_SEL;                      /**< GP Timer #4 clock selector, offset: 0xC0000 */
  __IO uint32_t GPT4_CAPIN1_SEL;                   /**< GP Timer #4 event capture input #1 selector, offset: 0xC0004 */
  __IO uint32_t GPT4_CAPIN2_SEL;                   /**< GP Timer #4 event capture input #2 selector, offset: 0xC0008 */
       uint8_t RESERVED_11[65524];
  __IO uint32_t GPT5_CLK_SEL;                      /**< GP Timer #5 clock selector, offset: 0xD0000 */
  __IO uint32_t GPT5_CAPIN1_SEL;                   /**< GP Timer #5 event capture input #1 selector, offset: 0xD0004 */
  __IO uint32_t GPT5_CAPIN2_SEL;                   /**< GP Timer #5 event capture input #2 selector, offset: 0xD0008 */
       uint8_t RESERVED_12[65524];
  __IO uint32_t SAI0_MCLK_SEL;                     /**< SAI #0 clock selector, offset: 0xE0000 */
       uint8_t RESERVED_13[65532];
  __IO uint32_t SAI1_MCLK_SEL;                     /**< SAI #1 clock selector, offset: 0xF0000 */
       uint8_t RESERVED_14[65532];
  __IO uint32_t SAI2_MCLK_SEL;                     /**< SAI #2 clock selector, offset: 0x100000 */
       uint8_t RESERVED_15[65532];
  __IO uint32_t SAI3_MCLK_SEL;                     /**< SAI #3 clock selector, offset: 0x110000 */
       uint8_t RESERVED_16[65532];
  __IO uint32_t SAI_HDMIRX0_MCLK_SEL;              /**< SAI HDMI RX #0 clock selector, offset: 0x120000 */
       uint8_t RESERVED_17[65532];
  __IO uint32_t SAI_HDMITX0_MCLK_SEL;              /**< SAI HDMI TX #0 clock selector, offset: 0x130000 */
  __IO uint32_t SAI_HDMITX1_MCLK_SEL;              /**< SAI HDMI TX #1 clock selector, offset: 0x130004 */
       uint8_t RESERVED_18[65528];
  __IO uint32_t SAI6_MCLK_SEL;                     /**< SAI #6 clock selector, offset: 0x140000 */
       uint8_t RESERVED_19[65532];
  __IO uint32_t SAI7_MCLK_SEL;                     /**< SAI #7 clock selector, offset: 0x150000 */
       uint8_t RESERVED_20[65532];
  __IO uint32_t TSAI0_MCLK_SEL;                    /**< TSAI #0 clock selector, offset: 0x160000 */
       uint8_t RESERVED_21[65532];
  __IO uint32_t TSAI1_MCLK_SEL;                    /**< TSAI #1 clock selector, offset: 0x170000 */
       uint8_t RESERVED_22[65532];
  __IO uint32_t TSAI2_MCLK_SEL;                    /**< TSAI #2 clock selector, offset: 0x180000 */
       uint8_t RESERVED_23[65532];
  __IO uint32_t TSAI3_MCLK_SEL;                    /**< TSAI #3 clock selector, offset: 0x190000 */
       uint8_t RESERVED_24[65532];
  __IO uint32_t SPDIF0_TX_CLK_SEL;                 /**< SPDI/F #0 clock selector, offset: 0x1A0000 */
       uint8_t RESERVED_25[65532];
  __IO uint32_t SPDIF1_TX_CLK_SEL;                 /**< SPDI/F #1 clock selector, offset: 0x1B0000 */
       uint8_t RESERVED_26[65532];
  __IO uint32_t MQS_HMCLK_SEL;                     /**< MQS HM clock selector, offset: 0x1C0000 */
} ACM_Type;

/* ----------------------------------------------------------------------------
   -- ACM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ACM_Register_Masks ACM Register Masks
 * @{
 */

/*! @name AUD_CLK0_SEL - Audio Clock Multiplexer #0 selector */
/*! @{ */
#define ACM_AUD_CLK0_SEL_SEL_MASK                (0x1FU)
#define ACM_AUD_CLK0_SEL_SEL_SHIFT               (0U)
#define ACM_AUD_CLK0_SEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK0_SEL_SEL_SHIFT)) & ACM_AUD_CLK0_SEL_SEL_MASK)
/*! @} */

/*! @name AUD_CLK1_SEL - Audio Clock Multiplexer #1 selector */
/*! @{ */
#define ACM_AUD_CLK1_SEL_SEL_MASK                (0x1FU)
#define ACM_AUD_CLK1_SEL_SEL_SHIFT               (0U)
#define ACM_AUD_CLK1_SEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK1_SEL_SEL_SHIFT)) & ACM_AUD_CLK1_SEL_SEL_MASK)
/*! @} */

/*! @name MCLKOUT0_SEL - Master Clock Output #0 selector */
/*! @{ */
#define ACM_MCLKOUT0_SEL_SEL_MASK                (0x7U)
#define ACM_MCLKOUT0_SEL_SEL_SHIFT               (0U)
#define ACM_MCLKOUT0_SEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT0_SEL_SEL_SHIFT)) & ACM_MCLKOUT0_SEL_SEL_MASK)
/*! @} */

/*! @name MCLKOUT1_SEL - Master Clock Output #1 selector */
/*! @{ */
#define ACM_MCLKOUT1_SEL_SEL_MASK                (0x7U)
#define ACM_MCLKOUT1_SEL_SEL_SHIFT               (0U)
#define ACM_MCLKOUT1_SEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT1_SEL_SEL_SHIFT)) & ACM_MCLKOUT1_SEL_SEL_MASK)
/*! @} */

/*! @name ASRC0_CLK_SEL - ASRC #0 clock selector */
/*! @{ */
#define ACM_ASRC0_CLK_SEL_SEL_MASK               (0x7U)
#define ACM_ASRC0_CLK_SEL_SEL_SHIFT              (0U)
#define ACM_ASRC0_CLK_SEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACM_ASRC0_CLK_SEL_SEL_SHIFT)) & ACM_ASRC0_CLK_SEL_SEL_MASK)
/*! @} */

/*! @name ESAI0_CLK_SEL - ESAI #0 clock selector */
/*! @{ */
#define ACM_ESAI0_CLK_SEL_SEL_MASK               (0x3U)
#define ACM_ESAI0_CLK_SEL_SEL_SHIFT              (0U)
#define ACM_ESAI0_CLK_SEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACM_ESAI0_CLK_SEL_SEL_SHIFT)) & ACM_ESAI0_CLK_SEL_SEL_MASK)
/*! @} */

/*! @name ESAI1_CLK_SEL - ESAI #1 clock selector */
/*! @{ */
#define ACM_ESAI1_CLK_SEL_SEL_MASK               (0x3U)
#define ACM_ESAI1_CLK_SEL_SEL_SHIFT              (0U)
#define ACM_ESAI1_CLK_SEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACM_ESAI1_CLK_SEL_SEL_SHIFT)) & ACM_ESAI1_CLK_SEL_SEL_MASK)
/*! @} */

/*! @name GPT0_CLK_SEL - GP Timer #0 clock selector */
/*! @{ */
#define ACM_GPT0_CLK_SEL_SEL_MASK                (0x7U)
#define ACM_GPT0_CLK_SEL_SEL_SHIFT               (0U)
#define ACM_GPT0_CLK_SEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << ACM_GPT0_CLK_SEL_SEL_SHIFT)) & ACM_GPT0_CLK_SEL_SEL_MASK)
/*! @} */

/*! @name GPT0_CAPIN1_SEL - GP Timer #0 event capture input #1 selector */
/*! @{ */
#define ACM_GPT0_CAPIN1_SEL_SEL_MASK             (0x1FU)
#define ACM_GPT0_CAPIN1_SEL_SEL_SHIFT            (0U)
#define ACM_GPT0_CAPIN1_SEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << ACM_GPT0_CAPIN1_SEL_SEL_SHIFT)) & ACM_GPT0_CAPIN1_SEL_SEL_MASK)
/*! @} */

/*! @name GPT0_CAPIN2_SEL - GP Timer #0 event capture input #2 selector */
/*! @{ */
#define ACM_GPT0_CAPIN2_SEL_SEL_MASK             (0x1FU)
#define ACM_GPT0_CAPIN2_SEL_SEL_SHIFT            (0U)
#define ACM_GPT0_CAPIN2_SEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << ACM_GPT0_CAPIN2_SEL_SEL_SHIFT)) & ACM_GPT0_CAPIN2_SEL_SEL_MASK)
/*! @} */

/*! @name GPT1_CLK_SEL - GP Timer #1 clock selector */
/*! @{ */
#define ACM_GPT1_CLK_SEL_SEL_MASK                (0x7U)
#define ACM_GPT1_CLK_SEL_SEL_SHIFT               (0U)
#define ACM_GPT1_CLK_SEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << ACM_GPT1_CLK_SEL_SEL_SHIFT)) & ACM_GPT1_CLK_SEL_SEL_MASK)
/*! @} */

/*! @name GPT1_CAPIN1_SEL - GP Timer #1 event capture input #1 selector */
/*! @{ */
#define ACM_GPT1_CAPIN1_SEL_SEL_MASK             (0x1FU)
#define ACM_GPT1_CAPIN1_SEL_SEL_SHIFT            (0U)
#define ACM_GPT1_CAPIN1_SEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << ACM_GPT1_CAPIN1_SEL_SEL_SHIFT)) & ACM_GPT1_CAPIN1_SEL_SEL_MASK)
/*! @} */

/*! @name GPT1_CAPIN2_SEL - GP Timer #1 event capture input #2 selector */
/*! @{ */
#define ACM_GPT1_CAPIN2_SEL_SEL_MASK             (0x1FU)
#define ACM_GPT1_CAPIN2_SEL_SEL_SHIFT            (0U)
#define ACM_GPT1_CAPIN2_SEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << ACM_GPT1_CAPIN2_SEL_SEL_SHIFT)) & ACM_GPT1_CAPIN2_SEL_SEL_MASK)
/*! @} */

/*! @name GPT2_CLK_SEL - GP Timer #2 clock selector */
/*! @{ */
#define ACM_GPT2_CLK_SEL_SEL_MASK                (0x7U)
#define ACM_GPT2_CLK_SEL_SEL_SHIFT               (0U)
#define ACM_GPT2_CLK_SEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << ACM_GPT2_CLK_SEL_SEL_SHIFT)) & ACM_GPT2_CLK_SEL_SEL_MASK)
/*! @} */

/*! @name GPT2_CAPIN1_SEL - GP Timer #2 event capture input #1 selector */
/*! @{ */
#define ACM_GPT2_CAPIN1_SEL_SEL_MASK             (0x1FU)
#define ACM_GPT2_CAPIN1_SEL_SEL_SHIFT            (0U)
#define ACM_GPT2_CAPIN1_SEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << ACM_GPT2_CAPIN1_SEL_SEL_SHIFT)) & ACM_GPT2_CAPIN1_SEL_SEL_MASK)
/*! @} */

/*! @name GPT2_CAPIN2_SEL - GP Timer #2 event capture input #2 selector */
/*! @{ */
#define ACM_GPT2_CAPIN2_SEL_SEL_MASK             (0x1FU)
#define ACM_GPT2_CAPIN2_SEL_SEL_SHIFT            (0U)
#define ACM_GPT2_CAPIN2_SEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << ACM_GPT2_CAPIN2_SEL_SEL_SHIFT)) & ACM_GPT2_CAPIN2_SEL_SEL_MASK)
/*! @} */

/*! @name GPT3_CLK_SEL - GP Timer #3 clock selector */
/*! @{ */
#define ACM_GPT3_CLK_SEL_SEL_MASK                (0x7U)
#define ACM_GPT3_CLK_SEL_SEL_SHIFT               (0U)
#define ACM_GPT3_CLK_SEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << ACM_GPT3_CLK_SEL_SEL_SHIFT)) & ACM_GPT3_CLK_SEL_SEL_MASK)
/*! @} */

/*! @name GPT3_CAPIN1_SEL - GP Timer #3 event capture input #1 selector */
/*! @{ */
#define ACM_GPT3_CAPIN1_SEL_SEL_MASK             (0x1FU)
#define ACM_GPT3_CAPIN1_SEL_SEL_SHIFT            (0U)
#define ACM_GPT3_CAPIN1_SEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << ACM_GPT3_CAPIN1_SEL_SEL_SHIFT)) & ACM_GPT3_CAPIN1_SEL_SEL_MASK)
/*! @} */

/*! @name GPT3_CAPIN2_SEL - GP Timer #3 event capture input #2 selector */
/*! @{ */
#define ACM_GPT3_CAPIN2_SEL_SEL_MASK             (0x1FU)
#define ACM_GPT3_CAPIN2_SEL_SEL_SHIFT            (0U)
#define ACM_GPT3_CAPIN2_SEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << ACM_GPT3_CAPIN2_SEL_SEL_SHIFT)) & ACM_GPT3_CAPIN2_SEL_SEL_MASK)
/*! @} */

/*! @name GPT4_CLK_SEL - GP Timer #4 clock selector */
/*! @{ */
#define ACM_GPT4_CLK_SEL_SEL_MASK                (0x7U)
#define ACM_GPT4_CLK_SEL_SEL_SHIFT               (0U)
#define ACM_GPT4_CLK_SEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << ACM_GPT4_CLK_SEL_SEL_SHIFT)) & ACM_GPT4_CLK_SEL_SEL_MASK)
/*! @} */

/*! @name GPT4_CAPIN1_SEL - GP Timer #4 event capture input #1 selector */
/*! @{ */
#define ACM_GPT4_CAPIN1_SEL_SEL_MASK             (0x1FU)
#define ACM_GPT4_CAPIN1_SEL_SEL_SHIFT            (0U)
#define ACM_GPT4_CAPIN1_SEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << ACM_GPT4_CAPIN1_SEL_SEL_SHIFT)) & ACM_GPT4_CAPIN1_SEL_SEL_MASK)
/*! @} */

/*! @name GPT4_CAPIN2_SEL - GP Timer #4 event capture input #2 selector */
/*! @{ */
#define ACM_GPT4_CAPIN2_SEL_SEL_MASK             (0x1FU)
#define ACM_GPT4_CAPIN2_SEL_SEL_SHIFT            (0U)
#define ACM_GPT4_CAPIN2_SEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << ACM_GPT4_CAPIN2_SEL_SEL_SHIFT)) & ACM_GPT4_CAPIN2_SEL_SEL_MASK)
/*! @} */

/*! @name GPT5_CLK_SEL - GP Timer #5 clock selector */
/*! @{ */
#define ACM_GPT5_CLK_SEL_SEL_MASK                (0x7U)
#define ACM_GPT5_CLK_SEL_SEL_SHIFT               (0U)
#define ACM_GPT5_CLK_SEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << ACM_GPT5_CLK_SEL_SEL_SHIFT)) & ACM_GPT5_CLK_SEL_SEL_MASK)
/*! @} */

/*! @name GPT5_CAPIN1_SEL - GP Timer #5 event capture input #1 selector */
/*! @{ */
#define ACM_GPT5_CAPIN1_SEL_SEL_MASK             (0x1FU)
#define ACM_GPT5_CAPIN1_SEL_SEL_SHIFT            (0U)
#define ACM_GPT5_CAPIN1_SEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << ACM_GPT5_CAPIN1_SEL_SEL_SHIFT)) & ACM_GPT5_CAPIN1_SEL_SEL_MASK)
/*! @} */

/*! @name GPT5_CAPIN2_SEL - GP Timer #5 event capture input #2 selector */
/*! @{ */
#define ACM_GPT5_CAPIN2_SEL_SEL_MASK             (0x1FU)
#define ACM_GPT5_CAPIN2_SEL_SEL_SHIFT            (0U)
#define ACM_GPT5_CAPIN2_SEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << ACM_GPT5_CAPIN2_SEL_SEL_SHIFT)) & ACM_GPT5_CAPIN2_SEL_SEL_MASK)
/*! @} */

/*! @name SAI0_MCLK_SEL - SAI #0 clock selector */
/*! @{ */
#define ACM_SAI0_MCLK_SEL_SEL_MASK               (0x3U)
#define ACM_SAI0_MCLK_SEL_SEL_SHIFT              (0U)
#define ACM_SAI0_MCLK_SEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACM_SAI0_MCLK_SEL_SEL_SHIFT)) & ACM_SAI0_MCLK_SEL_SEL_MASK)
/*! @} */

/*! @name SAI1_MCLK_SEL - SAI #1 clock selector */
/*! @{ */
#define ACM_SAI1_MCLK_SEL_SEL_MASK               (0x3U)
#define ACM_SAI1_MCLK_SEL_SEL_SHIFT              (0U)
#define ACM_SAI1_MCLK_SEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACM_SAI1_MCLK_SEL_SEL_SHIFT)) & ACM_SAI1_MCLK_SEL_SEL_MASK)
/*! @} */

/*! @name SAI2_MCLK_SEL - SAI #2 clock selector */
/*! @{ */
#define ACM_SAI2_MCLK_SEL_SEL_MASK               (0x3U)
#define ACM_SAI2_MCLK_SEL_SEL_SHIFT              (0U)
#define ACM_SAI2_MCLK_SEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACM_SAI2_MCLK_SEL_SEL_SHIFT)) & ACM_SAI2_MCLK_SEL_SEL_MASK)
/*! @} */

/*! @name SAI3_MCLK_SEL - SAI #3 clock selector */
/*! @{ */
#define ACM_SAI3_MCLK_SEL_SEL_MASK               (0x3U)
#define ACM_SAI3_MCLK_SEL_SEL_SHIFT              (0U)
#define ACM_SAI3_MCLK_SEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACM_SAI3_MCLK_SEL_SEL_SHIFT)) & ACM_SAI3_MCLK_SEL_SEL_MASK)
/*! @} */

/*! @name SAI_HDMIRX0_MCLK_SEL - SAI HDMI RX #0 clock selector */
/*! @{ */
#define ACM_SAI_HDMIRX0_MCLK_SEL_SEL_MASK        (0x3U)
#define ACM_SAI_HDMIRX0_MCLK_SEL_SEL_SHIFT       (0U)
#define ACM_SAI_HDMIRX0_MCLK_SEL_SEL(x)          (((uint32_t)(((uint32_t)(x)) << ACM_SAI_HDMIRX0_MCLK_SEL_SEL_SHIFT)) & ACM_SAI_HDMIRX0_MCLK_SEL_SEL_MASK)
/*! @} */

/*! @name SAI_HDMITX0_MCLK_SEL - SAI HDMI TX #0 clock selector */
/*! @{ */
#define ACM_SAI_HDMITX0_MCLK_SEL_SEL_MASK        (0x3U)
#define ACM_SAI_HDMITX0_MCLK_SEL_SEL_SHIFT       (0U)
#define ACM_SAI_HDMITX0_MCLK_SEL_SEL(x)          (((uint32_t)(((uint32_t)(x)) << ACM_SAI_HDMITX0_MCLK_SEL_SEL_SHIFT)) & ACM_SAI_HDMITX0_MCLK_SEL_SEL_MASK)
/*! @} */

/*! @name SAI_HDMITX1_MCLK_SEL - SAI HDMI TX #1 clock selector */
/*! @{ */
#define ACM_SAI_HDMITX1_MCLK_SEL_SEL_MASK        (0x3U)
#define ACM_SAI_HDMITX1_MCLK_SEL_SEL_SHIFT       (0U)
#define ACM_SAI_HDMITX1_MCLK_SEL_SEL(x)          (((uint32_t)(((uint32_t)(x)) << ACM_SAI_HDMITX1_MCLK_SEL_SEL_SHIFT)) & ACM_SAI_HDMITX1_MCLK_SEL_SEL_MASK)
/*! @} */

/*! @name SAI6_MCLK_SEL - SAI #6 clock selector */
/*! @{ */
#define ACM_SAI6_MCLK_SEL_SEL_MASK               (0x3U)
#define ACM_SAI6_MCLK_SEL_SEL_SHIFT              (0U)
#define ACM_SAI6_MCLK_SEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACM_SAI6_MCLK_SEL_SEL_SHIFT)) & ACM_SAI6_MCLK_SEL_SEL_MASK)
/*! @} */

/*! @name SAI7_MCLK_SEL - SAI #7 clock selector */
/*! @{ */
#define ACM_SAI7_MCLK_SEL_SEL_MASK               (0x3U)
#define ACM_SAI7_MCLK_SEL_SEL_SHIFT              (0U)
#define ACM_SAI7_MCLK_SEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACM_SAI7_MCLK_SEL_SEL_SHIFT)) & ACM_SAI7_MCLK_SEL_SEL_MASK)
/*! @} */

/*! @name TSAI0_MCLK_SEL - TSAI #0 clock selector */
/*! @{ */
#define ACM_TSAI0_MCLK_SEL_SEL_MASK              (0x3U)
#define ACM_TSAI0_MCLK_SEL_SEL_SHIFT             (0U)
#define ACM_TSAI0_MCLK_SEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << ACM_TSAI0_MCLK_SEL_SEL_SHIFT)) & ACM_TSAI0_MCLK_SEL_SEL_MASK)
/*! @} */

/*! @name TSAI1_MCLK_SEL - TSAI #1 clock selector */
/*! @{ */
#define ACM_TSAI1_MCLK_SEL_SEL_MASK              (0x3U)
#define ACM_TSAI1_MCLK_SEL_SEL_SHIFT             (0U)
#define ACM_TSAI1_MCLK_SEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << ACM_TSAI1_MCLK_SEL_SEL_SHIFT)) & ACM_TSAI1_MCLK_SEL_SEL_MASK)
/*! @} */

/*! @name TSAI2_MCLK_SEL - TSAI #2 clock selector */
/*! @{ */
#define ACM_TSAI2_MCLK_SEL_SEL_MASK              (0x3U)
#define ACM_TSAI2_MCLK_SEL_SEL_SHIFT             (0U)
#define ACM_TSAI2_MCLK_SEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << ACM_TSAI2_MCLK_SEL_SEL_SHIFT)) & ACM_TSAI2_MCLK_SEL_SEL_MASK)
/*! @} */

/*! @name TSAI3_MCLK_SEL - TSAI #3 clock selector */
/*! @{ */
#define ACM_TSAI3_MCLK_SEL_SEL_MASK              (0x3U)
#define ACM_TSAI3_MCLK_SEL_SEL_SHIFT             (0U)
#define ACM_TSAI3_MCLK_SEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << ACM_TSAI3_MCLK_SEL_SEL_SHIFT)) & ACM_TSAI3_MCLK_SEL_SEL_MASK)
/*! @} */

/*! @name SPDIF0_TX_CLK_SEL - SPDI/F #0 clock selector */
/*! @{ */
#define ACM_SPDIF0_TX_CLK_SEL_SEL_MASK           (0x3U)
#define ACM_SPDIF0_TX_CLK_SEL_SEL_SHIFT          (0U)
#define ACM_SPDIF0_TX_CLK_SEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << ACM_SPDIF0_TX_CLK_SEL_SEL_SHIFT)) & ACM_SPDIF0_TX_CLK_SEL_SEL_MASK)
/*! @} */

/*! @name SPDIF1_TX_CLK_SEL - SPDI/F #1 clock selector */
/*! @{ */
#define ACM_SPDIF1_TX_CLK_SEL_SEL_MASK           (0x3U)
#define ACM_SPDIF1_TX_CLK_SEL_SEL_SHIFT          (0U)
#define ACM_SPDIF1_TX_CLK_SEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << ACM_SPDIF1_TX_CLK_SEL_SEL_SHIFT)) & ACM_SPDIF1_TX_CLK_SEL_SEL_MASK)
/*! @} */

/*! @name MQS_HMCLK_SEL - MQS HM clock selector */
/*! @{ */
#define ACM_MQS_HMCLK_SEL_SEL_MASK               (0x3U)
#define ACM_MQS_HMCLK_SEL_SEL_SHIFT              (0U)
#define ACM_MQS_HMCLK_SEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACM_MQS_HMCLK_SEL_SEL_SHIFT)) & ACM_MQS_HMCLK_SEL_SEL_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ACM_Register_Masks */


/* ACM - Peripheral instance base addresses */
/** Peripheral AUDIO__ACM base address */
#define AUDIO__ACM_BASE                          (0x59E00000u)
/** Peripheral AUDIO__ACM base pointer */
#define AUDIO__ACM                               ((ACM_Type *)AUDIO__ACM_BASE)
/** Array initializer of ACM peripheral base addresses */
#define ACM_BASE_ADDRS                           { AUDIO__ACM_BASE }
/** Array initializer of ACM peripheral base pointers */
#define ACM_BASE_PTRS                            { AUDIO__ACM }

/*!
 * @}
 */ /* end of group ACM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ADC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
 * @{
 */

/** ADC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t CTRL;                              /**< ADC Control Register, offset: 0x10 */
  __IO uint32_t STAT;                              /**< ADC Status Register, offset: 0x14 */
  __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
  __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
  __IO uint32_t CFG;                               /**< ADC Configuration Register, offset: 0x20 */
  __IO uint32_t PAUSE;                             /**< ADC Pause Register, offset: 0x24 */
       uint8_t RESERVED_1[8];
  __IO uint32_t FCTRL;                             /**< ADC FIFO Control Register, offset: 0x30 */
  __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
       uint8_t RESERVED_2[136];
  __IO uint32_t TCTRL[8];                          /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
       uint8_t RESERVED_3[32];
  struct {                                         /* offset: 0x100, array step: 0x8 */
    __IO uint32_t CMDL;                              /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
    __IO uint32_t CMDH;                              /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
  } CMD[15];
       uint8_t RESERVED_4[136];
  __IO uint32_t CV[4];                             /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_5[240];
  __I  uint32_t RESFIFO;                           /**< ADC Data Result FIFO Register, offset: 0x300 */
       uint8_t RESERVED_6[3320];
  __IO uint32_t TST;                               /**< ADC Test Register, offset: 0xFFC */
} ADC_Type;

/* ----------------------------------------------------------------------------
   -- ADC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ADC_Register_Masks ADC Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */
#define ADC_VERID_RES_MASK                       (0x1U)
#define ADC_VERID_RES_SHIFT                      (0U)
/*! RES - Resolution
 *  0b0..Up to 13-bit differential/12-bit single ended resolution supported.
 *  0b1..Up to 16-bit differential/15-bit single ended resolution supported.
 */
#define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
#define ADC_VERID_DIFFEN_MASK                    (0x2U)
#define ADC_VERID_DIFFEN_SHIFT                   (1U)
/*! DIFFEN - Differential Supported
 *  0b0..Differential operation not supported.
 *  0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
 */
#define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
#define ADC_VERID_MVI_MASK                       (0x8U)
#define ADC_VERID_MVI_SHIFT                      (3U)
/*! MVI - Multi Vref Implemented
 *  0b0..Single voltage reference high (VREFH) input supported.
 *  0b1..Multiple voltage reference high (VREFH) inputs supported.
 */
#define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
#define ADC_VERID_CSW_MASK                       (0x70U)
#define ADC_VERID_CSW_SHIFT                      (4U)
/*! CSW - Channel Scale Width
 *  0b000..Channel scaling not supported.
 *  0b001..Channel scaling supported. 1-bit CSCALE control field.
 *  0b110..Channel scaling supported. 6-bit CSCALE control field.
 */
#define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
#define ADC_VERID_VR1RNGI_MASK                   (0x100U)
#define ADC_VERID_VR1RNGI_SHIFT                  (8U)
/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
 *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
 *  0b1..Range control required. CFG[VREF1RNG] is implemented.
 */
#define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
#define ADC_VERID_IADCKI_MASK                    (0x200U)
#define ADC_VERID_IADCKI_SHIFT                   (9U)
/*! IADCKI - Internal ADC Clock implemented
 *  0b0..Internal clock source not implemented.
 *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
 */
#define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
#define ADC_VERID_CALOFSI_MASK                   (0x400U)
#define ADC_VERID_CALOFSI_SHIFT                  (10U)
/*! CALOFSI - Calibration Offset Function Implemented
 *  0b0..Offset calibration and offset trimming not implemented.
 *  0b1..Offset calibration and offset trimming implemented.
 */
#define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
#define ADC_VERID_MINOR_MASK                     (0xFF0000U)
#define ADC_VERID_MINOR_SHIFT                    (16U)
#define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
#define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
#define ADC_VERID_MAJOR_SHIFT                    (24U)
#define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */
#define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
#define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
#define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
#define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
#define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
/*! FIFOSIZE - Result FIFO Depth
 *  0b00000001..Result FIFO depth = 1 dataword.
 *  0b00000100..Result FIFO depth = 4 datawords.
 *  0b00001000..Result FIFO depth = 8 datawords.
 *  0b00010000..Result FIFO depth = 16 datawords.
 *  0b00100000..Result FIFO depth = 32 datawords.
 *  0b01000000..Result FIFO depth = 64 datawords.
 */
#define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
#define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
#define ADC_PARAM_CV_NUM_SHIFT                   (16U)
#define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
#define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
#define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
#define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
/*! @} */

/*! @name CTRL - ADC Control Register */
/*! @{ */
#define ADC_CTRL_ADCEN_MASK                      (0x1U)
#define ADC_CTRL_ADCEN_SHIFT                     (0U)
/*! ADCEN - ADC Enable
 *  0b0..ADC is disabled.
 *  0b1..ADC is enabled.
 */
#define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
#define ADC_CTRL_RST_MASK                        (0x2U)
#define ADC_CTRL_RST_SHIFT                       (1U)
/*! RST - Software Reset
 *  0b0..ADC logic is not reset.
 *  0b1..ADC logic is reset.
 */
#define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
#define ADC_CTRL_DOZEN_MASK                      (0x4U)
#define ADC_CTRL_DOZEN_SHIFT                     (2U)
/*! DOZEN - Doze Enable
 *  0b0..ADC is enabled in Doze mode.
 *  0b1..ADC is disabled in Doze mode.
 */
#define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
#define ADC_CTRL_RSTFIFO_MASK                    (0x100U)
#define ADC_CTRL_RSTFIFO_SHIFT                   (8U)
/*! RSTFIFO - Reset FIFO
 *  0b0..No effect.
 *  0b1..FIFO is reset.
 */
#define ADC_CTRL_RSTFIFO(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
/*! @} */

/*! @name STAT - ADC Status Register */
/*! @{ */
#define ADC_STAT_RDY_MASK                        (0x1U)
#define ADC_STAT_RDY_SHIFT                       (0U)
/*! RDY - Result FIFO Ready Flag
 *  0b0..Result FIFO data level not above watermark level.
 *  0b1..Result FIFO holding data above watermark level.
 */
#define ADC_STAT_RDY(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
#define ADC_STAT_FOF_MASK                        (0x2U)
#define ADC_STAT_FOF_SHIFT                       (1U)
/*! FOF - Result FIFO Overflow Flag
 *  0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
 */
#define ADC_STAT_FOF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
#define ADC_STAT_TRGACT_MASK                     (0x70000U)
#define ADC_STAT_TRGACT_SHIFT                    (16U)
/*! TRGACT - Trigger Active
 *  0b000..Command (sequence) associated with Trigger 0 currently being executed.
 *  0b001..Command (sequence) associated with Trigger 1 currently being executed.
 *  0b010..Command (sequence) associated with Trigger 2 currently being executed.
 *  0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.
 */
#define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
#define ADC_STAT_CMDACT_MASK                     (0xF000000U)
#define ADC_STAT_CMDACT_SHIFT                    (24U)
/*! CMDACT - Command Active
 *  0b0000..No command is currently in progress.
 *  0b0001..Command 1 currently being executed.
 *  0b0010..Command 2 currently being executed.
 *  0b0011-0b1111..Associated command number is currently being executed.
 */
#define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
/*! @} */

/*! @name IE - Interrupt Enable Register */
/*! @{ */
#define ADC_IE_FWMIE_MASK                        (0x1U)
#define ADC_IE_FWMIE_SHIFT                       (0U)
/*! FWMIE - FIFO Watermark Interrupt Enable
 *  0b0..FIFO watermark interrupts are not enabled.
 *  0b1..FIFO watermark interrupts are enabled.
 */
#define ADC_IE_FWMIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
#define ADC_IE_FOFIE_MASK                        (0x2U)
#define ADC_IE_FOFIE_SHIFT                       (1U)
/*! FOFIE - Result FIFO Overflow Interrupt Enable
 *  0b0..FIFO overflow interrupts are not enabled.
 *  0b1..FIFO overflow interrupts are enabled.
 */
#define ADC_IE_FOFIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
/*! @} */

/*! @name DE - DMA Enable Register */
/*! @{ */
#define ADC_DE_FWMDE_MASK                        (0x1U)
#define ADC_DE_FWMDE_SHIFT                       (0U)
/*! FWMDE - FIFO Watermark DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define ADC_DE_FWMDE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
/*! @} */

/*! @name CFG - ADC Configuration Register */
/*! @{ */
#define ADC_CFG_TPRICTRL_MASK                    (0x1U)
#define ADC_CFG_TPRICTRL_SHIFT                   (0U)
/*! TPRICTRL - ADC trigger priority control
 *  0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started.
 *  0b1..If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true conversion.
 */
#define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
#define ADC_CFG_PWRSEL_MASK                      (0x30U)
#define ADC_CFG_PWRSEL_SHIFT                     (4U)
/*! PWRSEL - Power Configuration Select
 *  0b00..Level 1 (Lowest power setting)
 *  0b01..Level 2
 *  0b10..Level 3
 *  0b11..Level 4 (Highest power setting)
 */
#define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
#define ADC_CFG_REFSEL_MASK                      (0xC0U)
#define ADC_CFG_REFSEL_SHIFT                     (6U)
/*! REFSEL - Voltage Reference Selection
 *  0b00..(Default) Option 1 setting.
 *  0b01..Option 2 setting.
 *  0b10..Option 3 setting.
 *  0b11..Reserved
 */
#define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
#define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
#define ADC_CFG_PUDLY_SHIFT                      (16U)
#define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
#define ADC_CFG_PWREN_MASK                       (0x10000000U)
#define ADC_CFG_PWREN_SHIFT                      (28U)
/*! PWREN - ADC Analog Pre-Enable
 *  0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
 *  0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any detected trigger does not begin ADC operation until the power up delay time has passed.
 */
#define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
/*! @} */

/*! @name PAUSE - ADC Pause Register */
/*! @{ */
#define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
#define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
#define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
#define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
#define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
/*! PAUSEEN - PAUSE Option Enable
 *  0b0..Pause operation disabled
 *  0b1..Pause operation enabled
 */
#define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
/*! @} */

/*! @name FCTRL - ADC FIFO Control Register */
/*! @{ */
#define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
#define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
#define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
#define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
#define ADC_FCTRL_FWMARK_SHIFT                   (16U)
#define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
/*! @} */

/*! @name SWTRIG - Software Trigger Register */
/*! @{ */
#define ADC_SWTRIG_SWT0_MASK                     (0x1U)
#define ADC_SWTRIG_SWT0_SHIFT                    (0U)
/*! SWT0 - Software trigger 0 event
 *  0b0..No trigger 0 event generated.
 *  0b1..Trigger 0 event generated.
 */
#define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
#define ADC_SWTRIG_SWT1_MASK                     (0x2U)
#define ADC_SWTRIG_SWT1_SHIFT                    (1U)
/*! SWT1 - Software trigger 1 event
 *  0b0..No trigger 1 event generated.
 *  0b1..Trigger 1 event generated.
 */
#define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
#define ADC_SWTRIG_SWT2_MASK                     (0x4U)
#define ADC_SWTRIG_SWT2_SHIFT                    (2U)
/*! SWT2 - Software trigger 2 event
 *  0b0..No trigger 2 event generated.
 *  0b1..Trigger 2 event generated.
 */
#define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
#define ADC_SWTRIG_SWT3_MASK                     (0x8U)
#define ADC_SWTRIG_SWT3_SHIFT                    (3U)
/*! SWT3 - Software trigger 3 event
 *  0b0..No trigger 3 event generated.
 *  0b1..Trigger 3 event generated.
 */
#define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
#define ADC_SWTRIG_SWT4_MASK                     (0x10U)
#define ADC_SWTRIG_SWT4_SHIFT                    (4U)
/*! SWT4 - Software trigger 4 event
 *  0b0..No trigger 4 event generated.
 *  0b1..Trigger 4 event generated.
 */
#define ADC_SWTRIG_SWT4(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
#define ADC_SWTRIG_SWT5_MASK                     (0x20U)
#define ADC_SWTRIG_SWT5_SHIFT                    (5U)
/*! SWT5 - Software trigger 5 event
 *  0b0..No trigger 5 event generated.
 *  0b1..Trigger 5 event generated.
 */
#define ADC_SWTRIG_SWT5(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
#define ADC_SWTRIG_SWT6_MASK                     (0x40U)
#define ADC_SWTRIG_SWT6_SHIFT                    (6U)
/*! SWT6 - Software trigger 6 event
 *  0b0..No trigger 6 event generated.
 *  0b1..Trigger 6 event generated.
 */
#define ADC_SWTRIG_SWT6(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
#define ADC_SWTRIG_SWT7_MASK                     (0x80U)
#define ADC_SWTRIG_SWT7_SHIFT                    (7U)
/*! SWT7 - Software trigger 7 event
 *  0b0..No trigger 7 event generated.
 *  0b1..Trigger 7 event generated.
 */
#define ADC_SWTRIG_SWT7(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
/*! @} */

/*! @name TCTRL - Trigger Control Register */
/*! @{ */
#define ADC_TCTRL_HTEN_MASK                      (0x1U)
#define ADC_TCTRL_HTEN_SHIFT                     (0U)
/*! HTEN - Trigger enable
 *  0b0..Hardware trigger source disabled
 *  0b1..Hardware trigger source enabled
 */
#define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
#define ADC_TCTRL_TPRI_MASK                      (0x700U)
#define ADC_TCTRL_TPRI_SHIFT                     (8U)
/*! TPRI - Trigger priority setting
 *  0b000..Set to highest priority, Level 1
 *  0b001-0b110..Set to corresponding priority level
 *  0b111..Set to lowest priority, Level 8
 */
#define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
#define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
#define ADC_TCTRL_TDLY_SHIFT                     (16U)
#define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
#define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
#define ADC_TCTRL_TCMD_SHIFT                     (24U)
/*! TCMD - Trigger command select
 *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
 *  0b0001..CMD1 is executed
 *  0b0010-0b1110..Corresponding CMD is executed
 *  0b1111..CMD15 is executed
 */
#define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
/*! @} */

/* The count of ADC_TCTRL */
#define ADC_TCTRL_COUNT                          (8U)

/*! @name CMDL - ADC Command Low Buffer Register */
/*! @{ */
#define ADC_CMDL_ADCH_MASK                       (0x1FU)
#define ADC_CMDL_ADCH_SHIFT                      (0U)
/*! ADCH - Input channel select
 *  0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
 *  0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
 *  0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
 *  0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
 *  0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
 *  0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
 *  0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
 */
#define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
#define ADC_CMDL_ABSEL_MASK                      (0x20U)
#define ADC_CMDL_ABSEL_SHIFT                     (5U)
/*! ABSEL - A-side vs. B-side Select
 *  0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
 *  0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
 */
#define ADC_CMDL_ABSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
#define ADC_CMDL_DIFF_MASK                       (0x40U)
#define ADC_CMDL_DIFF_SHIFT                      (6U)
/*! DIFF - Differential Mode Enable
 *  0b0..Single-ended mode.
 *  0b1..Differential mode.
 */
#define ADC_CMDL_DIFF(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
#define ADC_CMDL_CSCALE_MASK                     (0x2000U)
#define ADC_CMDL_CSCALE_SHIFT                    (13U)
/*! CSCALE - Channel Scale
 *  0b0..Scale selected analog channel (Factor of 30/64)
 *  0b1..(Default) Full scale (Factor of 1)
 */
#define ADC_CMDL_CSCALE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
/*! @} */

/* The count of ADC_CMDL */
#define ADC_CMDL_COUNT                           (15U)

/*! @name CMDH - ADC Command High Buffer Register */
/*! @{ */
#define ADC_CMDH_CMPEN_MASK                      (0x3U)
#define ADC_CMDH_CMPEN_SHIFT                     (0U)
/*! CMPEN - Compare Function Enable
 *  0b00..Compare disabled.
 *  0b01..Reserved
 *  0b10..Compare enabled. Store on true.
 *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
 */
#define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
#define ADC_CMDH_LWI_MASK                        (0x80U)
#define ADC_CMDH_LWI_SHIFT                       (7U)
/*! LWI - Loop with Increment
 *  0b0..Auto channel increment disabled
 *  0b1..Auto channel increment enabled
 */
#define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
#define ADC_CMDH_STS_MASK                        (0x700U)
#define ADC_CMDH_STS_SHIFT                       (8U)
#define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
#define ADC_CMDH_AVGS_MASK                       (0x7000U)
#define ADC_CMDH_AVGS_SHIFT                      (12U)
/*! AVGS - Hardware Average Select
 *  0b000..Single conversion.
 *  0b001..2 conversions averaged.
 *  0b010..4 conversions averaged.
 *  0b011..8 conversions averaged.
 *  0b100..16 conversions averaged.
 *  0b101..32 conversions averaged.
 *  0b110..64 conversions averaged.
 *  0b111..128 conversions averaged.
 */
#define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
#define ADC_CMDH_LOOP_MASK                       (0xF0000U)
#define ADC_CMDH_LOOP_SHIFT                      (16U)
/*! LOOP - Loop Count Select
 *  0b0000..Looping not enabled. Command executes 1 time.
 *  0b0001..Loop 1 time. Command executes 2 times.
 *  0b0010..Loop 2 times. Command executes 3 times.
 *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
 *  0b1111..Loop 15 times. Command executes 16 times.
 */
#define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
#define ADC_CMDH_NEXT_MASK                       (0xF000000U)
#define ADC_CMDH_NEXT_SHIFT                      (24U)
/*! NEXT - Next Command Select
 *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
 *  0b0001..Select CMD1 command buffer register as next command.
 *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
 *  0b1111..Select CMD15 command buffer register as next command.
 */
#define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
/*! @} */

/* The count of ADC_CMDH */
#define ADC_CMDH_COUNT                           (15U)

/*! @name CV - Compare Value Register */
/*! @{ */
#define ADC_CV_CVL_MASK                          (0xFFFFU)
#define ADC_CV_CVL_SHIFT                         (0U)
#define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
#define ADC_CV_CVH_MASK                          (0xFFFF0000U)
#define ADC_CV_CVH_SHIFT                         (16U)
#define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
/*! @} */

/* The count of ADC_CV */
#define ADC_CV_COUNT                             (4U)

/*! @name RESFIFO - ADC Data Result FIFO Register */
/*! @{ */
#define ADC_RESFIFO_D_MASK                       (0xFFFFU)
#define ADC_RESFIFO_D_SHIFT                      (0U)
#define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
#define ADC_RESFIFO_TSRC_MASK                    (0x70000U)
#define ADC_RESFIFO_TSRC_SHIFT                   (16U)
/*! TSRC - Trigger Source
 *  0b000..Trigger source 0 initiated this conversion.
 *  0b001..Trigger source 1 initiated this conversion.
 *  0b010-0b110..Corresponding trigger source initiated this conversion.
 *  0b111..Trigger source 7 initiated this conversion.
 */
#define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
#define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
#define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
/*! LOOPCNT - Loop count value
 *  0b0000..Result is from initial conversion in command.
 *  0b0001..Result is from second conversion in command.
 */
#define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
#define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
#define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
/*! CMDSRC - Command Buffer Source
 *  0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
 *  0b0001..CMD1 buffer used as control settings for this conversion.
 *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
 *  0b1111..CMD15 buffer used as control settings for this conversion.
 */
#define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
#define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
#define ADC_RESFIFO_VALID_SHIFT                  (31U)
/*! VALID - FIFO entry is valid
 *  0b0..FIFO is empty. Discard any read from RESFIFO.
 *  0b1..FIFO record read from RESFIFO is valid.
 */
#define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
/*! @} */

/*! @name TST - ADC Test Register */
/*! @{ */
#define ADC_TST_FOFFM_MASK                       (0x100U)
#define ADC_TST_FOFFM_SHIFT                      (8U)
/*! FOFFM - Force M-side offset
 *  0b0..Normal operation. No forced offset.
 *  0b1..Test configuration. Forced offset on MDAC.
 */
#define ADC_TST_FOFFM(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK)
#define ADC_TST_FOFFP_MASK                       (0x200U)
#define ADC_TST_FOFFP_SHIFT                      (9U)
/*! FOFFP - Force P-side offset
 *  0b0..Normal operation. No forced offset.
 *  0b1..Test configuration. Forced offset on PDAC.
 */
#define ADC_TST_FOFFP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK)
#define ADC_TST_TMODE_MASK                       (0x1F0000U)
#define ADC_TST_TMODE_SHIFT                      (16U)
/*! TMODE - Test Mode Select
 *  0b00000..P-side redundancy check. Measure LSB offset cap.
 *  0b00001-0b00011..Reserved
 *  0b00100..P-side test. Bist_offset vs. lower order caps (bits 5-0)
 *  0b00101..P-side test. MSB_offset vs. lower order caps (bits 5-0)
 *  0b00110..P-side test. Bit 6 vs. lower order caps (bits 5-0)
 *  0b00111..P-side test. Bit 7 vs. lower order caps (bits 6-0)
 *  0b01000..P-side test. Bit 8 vs. lower order caps (bits 7-0)
 *  0b01001..P-side test. Bit 9 vs. lower order caps (bits 8-0)
 *  0b01010..P-side test. Bit 10 vs. lower order caps (bits 9-0)
 *  0b01011..P-side test. Bit 11 vs. lower order caps (bits 10-0)
 *  0b01100-0b01111..Reserved
 *  0b10000..M-side redundancy check. Measure LSB offset cap.
 *  0b10001-0b10011..Reserved
 *  0b10100..M-side test. Bist_offset vs. lower order caps (bits 5-0)
 *  0b10101..M-side test. MSB_offset vs. lower order caps (bits 5-0)
 *  0b10110..M-side test. Bit 6 vs. lower order caps (bits 5-0)
 *  0b10111..M-side test. Bit 7 vs. lower order caps (bits 6-0)
 *  0b11000..M-side test. Bit 8 vs. lower order caps (bits 7-0)
 *  0b11001..M-side test. Bit 9 vs. lower order caps (bits 8-0)
 *  0b11010..M-side test. Bit 10 vs. lower order caps (bits 9-0)
 *  0b11011..M-side test. Bit 11 vs. lower order caps (bits 10-0)
 *  0b11100..Transfer raw CMPOUT[15:13] value. No ADC conversion. Result is from most recent conversion.
 *  0b11101..Transfer raw CMPOUT[12:0] value. No ADC conversion. Result is from most recent conversion.
 *  0b11110..Transfer raw CM_CMPOUT[15:13] value. No ADC conversion. Result is from most recent conversion.
 *  0b11111..Transfer raw CM_CMPOUT[12:0] value. No ADC conversion. Result is from most recent conversion.
 */
#define ADC_TST_TMODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_TST_TMODE_SHIFT)) & ADC_TST_TMODE_MASK)
#define ADC_TST_TESTEN_MASK                      (0x800000U)
#define ADC_TST_TESTEN_SHIFT                     (23U)
/*! TESTEN - Enable test configuration
 *  0b0..Normal operation. Test configuration not enabled.
 *  0b1..Test configuration. TMODE select test operation to perform when ADC conversions are triggered.
 */
#define ADC_TST_TESTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ADC_Register_Masks */


/* ADC - Peripheral instance base addresses */
/** Peripheral DMA__ADC0 base address */
#define DMA__ADC0_BASE                           (0x5A880000u)
/** Peripheral DMA__ADC0 base pointer */
#define DMA__ADC0                                ((ADC_Type *)DMA__ADC0_BASE)
/** Peripheral DMA__ADC1 base address */
#define DMA__ADC1_BASE                           (0x5A890000u)
/** Peripheral DMA__ADC1 base pointer */
#define DMA__ADC1                                ((ADC_Type *)DMA__ADC1_BASE)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS                           { DMA__ADC0_BASE, DMA__ADC1_BASE }
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASE_PTRS                            { DMA__ADC0, DMA__ADC1 }
/** Interrupt vectors for the ADC peripheral type */
#define ADC_IRQS                                 { DMA_ADC0_INT_IRQn, DMA_ADC1_INT_IRQn }

/*!
 * @}
 */ /* end of group ADC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- APBH Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
 * @{
 */

/** APBH - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0 */
    __IO uint32_t RW;                                /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
    __IO uint32_t SET;                               /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
    __IO uint32_t CLR;                               /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
    __IO uint32_t TOG;                               /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
  } CTRL0;
  struct {                                         /* offset: 0x10 */
    __IO uint32_t RW;                                /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
    __IO uint32_t SET;                               /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
    __IO uint32_t CLR;                               /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
    __IO uint32_t TOG;                               /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
  } CTRL1;
  struct {                                         /* offset: 0x20 */
    __IO uint32_t RW;                                /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
    __IO uint32_t SET;                               /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
    __IO uint32_t CLR;                               /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
    __IO uint32_t TOG;                               /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
  } CTRL2;
  struct {                                         /* offset: 0x30 */
    __IO uint32_t RW;                                /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
    __IO uint32_t SET;                               /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
    __IO uint32_t CLR;                               /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
    __IO uint32_t TOG;                               /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
  } CHANNEL_CTRL;
       uint32_t DEVSEL;                            /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
       uint8_t RESERVED_0[12];
  __IO uint32_t DMA_BURST_SIZE;                    /**< AHB to APBH DMA burst size, offset: 0x50 */
       uint8_t RESERVED_1[12];
  __IO uint32_t DEBUGr;                            /**< AHB to APBH DMA Debug Register, offset: 0x60 */
       uint8_t RESERVED_2[156];
  __I  uint32_t CH0_CURCMDAR;                      /**< APBH DMA Channel n Current Command Address Register, offset: 0x100 */
       uint8_t RESERVED_3[12];
  __IO uint32_t CH0_NXTCMDAR;                      /**< APBH DMA Channel n Next Command Address Register, offset: 0x110 */
       uint8_t RESERVED_4[12];
  __I  uint32_t CH0_CMD;                           /**< APBH DMA Channel n Command Register, offset: 0x120 */
       uint8_t RESERVED_5[12];
  __I  uint32_t CH0_BAR;                           /**< APBH DMA Channel n Buffer Address Register, offset: 0x130 */
       uint8_t RESERVED_6[12];
  __IO uint32_t CH0_SEMA;                          /**< APBH DMA Channel n Semaphore Register, offset: 0x140 */
       uint8_t RESERVED_7[12];
  __I  uint32_t CH0_DEBUG1;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x150 */
       uint8_t RESERVED_8[12];
  __I  uint32_t CH0_DEBUG2;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x160 */
       uint8_t RESERVED_9[12];
  __I  uint32_t CH1_CURCMDAR;                      /**< APBH DMA Channel n Current Command Address Register, offset: 0x170 */
       uint8_t RESERVED_10[12];
  __IO uint32_t CH1_NXTCMDAR;                      /**< APBH DMA Channel n Next Command Address Register, offset: 0x180 */
       uint8_t RESERVED_11[12];
  __I  uint32_t CH1_CMD;                           /**< APBH DMA Channel n Command Register, offset: 0x190 */
       uint8_t RESERVED_12[12];
  __I  uint32_t CH1_BAR;                           /**< APBH DMA Channel n Buffer Address Register, offset: 0x1A0 */
       uint8_t RESERVED_13[12];
  __IO uint32_t CH1_SEMA;                          /**< APBH DMA Channel n Semaphore Register, offset: 0x1B0 */
       uint8_t RESERVED_14[12];
  __I  uint32_t CH1_DEBUG1;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1C0 */
       uint8_t RESERVED_15[12];
  __I  uint32_t CH1_DEBUG2;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1D0 */
       uint8_t RESERVED_16[12];
  __I  uint32_t CH2_CURCMDAR;                      /**< APBH DMA Channel n Current Command Address Register, offset: 0x1E0 */
       uint8_t RESERVED_17[12];
  __IO uint32_t CH2_NXTCMDAR;                      /**< APBH DMA Channel n Next Command Address Register, offset: 0x1F0 */
       uint8_t RESERVED_18[12];
  __I  uint32_t CH2_CMD;                           /**< APBH DMA Channel n Command Register, offset: 0x200 */
       uint8_t RESERVED_19[12];
  __I  uint32_t CH2_BAR;                           /**< APBH DMA Channel n Buffer Address Register, offset: 0x210 */
       uint8_t RESERVED_20[12];
  __IO uint32_t CH2_SEMA;                          /**< APBH DMA Channel n Semaphore Register, offset: 0x220 */
       uint8_t RESERVED_21[12];
  __I  uint32_t CH2_DEBUG1;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x230 */
       uint8_t RESERVED_22[12];
  __I  uint32_t CH2_DEBUG2;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x240 */
       uint8_t RESERVED_23[12];
  __I  uint32_t CH3_CURCMDAR;                      /**< APBH DMA Channel n Current Command Address Register, offset: 0x250 */
       uint8_t RESERVED_24[12];
  __IO uint32_t CH3_NXTCMDAR;                      /**< APBH DMA Channel n Next Command Address Register, offset: 0x260 */
       uint8_t RESERVED_25[12];
  __I  uint32_t CH3_CMD;                           /**< APBH DMA Channel n Command Register, offset: 0x270 */
       uint8_t RESERVED_26[12];
  __I  uint32_t CH3_BAR;                           /**< APBH DMA Channel n Buffer Address Register, offset: 0x280 */
       uint8_t RESERVED_27[12];
  __IO uint32_t CH3_SEMA;                          /**< APBH DMA Channel n Semaphore Register, offset: 0x290 */
       uint8_t RESERVED_28[12];
  __I  uint32_t CH3_DEBUG1;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2A0 */
       uint8_t RESERVED_29[12];
  __I  uint32_t CH3_DEBUG2;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2B0 */
       uint8_t RESERVED_30[12];
  __I  uint32_t CH4_CURCMDAR;                      /**< APBH DMA Channel n Current Command Address Register, offset: 0x2C0 */
       uint8_t RESERVED_31[12];
  __IO uint32_t CH4_NXTCMDAR;                      /**< APBH DMA Channel n Next Command Address Register, offset: 0x2D0 */
       uint8_t RESERVED_32[12];
  __I  uint32_t CH4_CMD;                           /**< APBH DMA Channel n Command Register, offset: 0x2E0 */
       uint8_t RESERVED_33[12];
  __I  uint32_t CH4_BAR;                           /**< APBH DMA Channel n Buffer Address Register, offset: 0x2F0 */
       uint8_t RESERVED_34[12];
  __IO uint32_t CH4_SEMA;                          /**< APBH DMA Channel n Semaphore Register, offset: 0x300 */
       uint8_t RESERVED_35[12];
  __I  uint32_t CH4_DEBUG1;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x310 */
       uint8_t RESERVED_36[12];
  __I  uint32_t CH4_DEBUG2;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x320 */
       uint8_t RESERVED_37[12];
  __I  uint32_t CH5_CURCMDAR;                      /**< APBH DMA Channel n Current Command Address Register, offset: 0x330 */
       uint8_t RESERVED_38[12];
  __IO uint32_t CH5_NXTCMDAR;                      /**< APBH DMA Channel n Next Command Address Register, offset: 0x340 */
       uint8_t RESERVED_39[12];
  __I  uint32_t CH5_CMD;                           /**< APBH DMA Channel n Command Register, offset: 0x350 */
       uint8_t RESERVED_40[12];
  __I  uint32_t CH5_BAR;                           /**< APBH DMA Channel n Buffer Address Register, offset: 0x360 */
       uint8_t RESERVED_41[12];
  __IO uint32_t CH5_SEMA;                          /**< APBH DMA Channel n Semaphore Register, offset: 0x370 */
       uint8_t RESERVED_42[12];
  __I  uint32_t CH5_DEBUG1;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x380 */
       uint8_t RESERVED_43[12];
  __I  uint32_t CH5_DEBUG2;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x390 */
       uint8_t RESERVED_44[12];
  __I  uint32_t CH6_CURCMDAR;                      /**< APBH DMA Channel n Current Command Address Register, offset: 0x3A0 */
       uint8_t RESERVED_45[12];
  __IO uint32_t CH6_NXTCMDAR;                      /**< APBH DMA Channel n Next Command Address Register, offset: 0x3B0 */
       uint8_t RESERVED_46[12];
  __I  uint32_t CH6_CMD;                           /**< APBH DMA Channel n Command Register, offset: 0x3C0 */
       uint8_t RESERVED_47[12];
  __I  uint32_t CH6_BAR;                           /**< APBH DMA Channel n Buffer Address Register, offset: 0x3D0 */
       uint8_t RESERVED_48[12];
  __IO uint32_t CH6_SEMA;                          /**< APBH DMA Channel n Semaphore Register, offset: 0x3E0 */
       uint8_t RESERVED_49[12];
  __I  uint32_t CH6_DEBUG1;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x3F0 */
       uint8_t RESERVED_50[12];
  __I  uint32_t CH6_DEBUG2;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x400 */
       uint8_t RESERVED_51[12];
  __I  uint32_t CH7_CURCMDAR;                      /**< APBH DMA Channel n Current Command Address Register, offset: 0x410 */
       uint8_t RESERVED_52[12];
  __IO uint32_t CH7_NXTCMDAR;                      /**< APBH DMA Channel n Next Command Address Register, offset: 0x420 */
       uint8_t RESERVED_53[12];
  __I  uint32_t CH7_CMD;                           /**< APBH DMA Channel n Command Register, offset: 0x430 */
       uint8_t RESERVED_54[12];
  __I  uint32_t CH7_BAR;                           /**< APBH DMA Channel n Buffer Address Register, offset: 0x440 */
       uint8_t RESERVED_55[12];
  __IO uint32_t CH7_SEMA;                          /**< APBH DMA Channel n Semaphore Register, offset: 0x450 */
       uint8_t RESERVED_56[12];
  __I  uint32_t CH7_DEBUG1;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x460 */
       uint8_t RESERVED_57[12];
  __I  uint32_t CH7_DEBUG2;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x470 */
       uint8_t RESERVED_58[12];
  __I  uint32_t CH8_CURCMDAR;                      /**< APBH DMA Channel n Current Command Address Register, offset: 0x480 */
       uint8_t RESERVED_59[12];
  __IO uint32_t CH8_NXTCMDAR;                      /**< APBH DMA Channel n Next Command Address Register, offset: 0x490 */
       uint8_t RESERVED_60[12];
  __I  uint32_t CH8_CMD;                           /**< APBH DMA Channel n Command Register, offset: 0x4A0 */
       uint8_t RESERVED_61[12];
  __I  uint32_t CH8_BAR;                           /**< APBH DMA Channel n Buffer Address Register, offset: 0x4B0 */
       uint8_t RESERVED_62[12];
  __IO uint32_t CH8_SEMA;                          /**< APBH DMA Channel n Semaphore Register, offset: 0x4C0 */
       uint8_t RESERVED_63[12];
  __I  uint32_t CH8_DEBUG1;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4D0 */
       uint8_t RESERVED_64[12];
  __I  uint32_t CH8_DEBUG2;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4E0 */
       uint8_t RESERVED_65[12];
  __I  uint32_t CH9_CURCMDAR;                      /**< APBH DMA Channel n Current Command Address Register, offset: 0x4F0 */
       uint8_t RESERVED_66[12];
  __IO uint32_t CH9_NXTCMDAR;                      /**< APBH DMA Channel n Next Command Address Register, offset: 0x500 */
       uint8_t RESERVED_67[12];
  __I  uint32_t CH9_CMD;                           /**< APBH DMA Channel n Command Register, offset: 0x510 */
       uint8_t RESERVED_68[12];
  __I  uint32_t CH9_BAR;                           /**< APBH DMA Channel n Buffer Address Register, offset: 0x520 */
       uint8_t RESERVED_69[12];
  __IO uint32_t CH9_SEMA;                          /**< APBH DMA Channel n Semaphore Register, offset: 0x530 */
       uint8_t RESERVED_70[12];
  __I  uint32_t CH9_DEBUG1;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x540 */
       uint8_t RESERVED_71[12];
  __I  uint32_t CH9_DEBUG2;                        /**< AHB to APBH DMA Channel n Debug Information, offset: 0x550 */
       uint8_t RESERVED_72[12];
  __I  uint32_t CH10_CURCMDAR;                     /**< APBH DMA Channel n Current Command Address Register, offset: 0x560 */
       uint8_t RESERVED_73[12];
  __IO uint32_t CH10_NXTCMDAR;                     /**< APBH DMA Channel n Next Command Address Register, offset: 0x570 */
       uint8_t RESERVED_74[12];
  __I  uint32_t CH10_CMD;                          /**< APBH DMA Channel n Command Register, offset: 0x580 */
       uint8_t RESERVED_75[12];
  __I  uint32_t CH10_BAR;                          /**< APBH DMA Channel n Buffer Address Register, offset: 0x590 */
       uint8_t RESERVED_76[12];
  __IO uint32_t CH10_SEMA;                         /**< APBH DMA Channel n Semaphore Register, offset: 0x5A0 */
       uint8_t RESERVED_77[12];
  __I  uint32_t CH10_DEBUG1;                       /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5B0 */
       uint8_t RESERVED_78[12];
  __I  uint32_t CH10_DEBUG2;                       /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5C0 */
       uint8_t RESERVED_79[12];
  __I  uint32_t CH11_CURCMDAR;                     /**< APBH DMA Channel n Current Command Address Register, offset: 0x5D0 */
       uint8_t RESERVED_80[12];
  __IO uint32_t CH11_NXTCMDAR;                     /**< APBH DMA Channel n Next Command Address Register, offset: 0x5E0 */
       uint8_t RESERVED_81[12];
  __I  uint32_t CH11_CMD;                          /**< APBH DMA Channel n Command Register, offset: 0x5F0 */
       uint8_t RESERVED_82[12];
  __I  uint32_t CH11_BAR;                          /**< APBH DMA Channel n Buffer Address Register, offset: 0x600 */
       uint8_t RESERVED_83[12];
  __IO uint32_t CH11_SEMA;                         /**< APBH DMA Channel n Semaphore Register, offset: 0x610 */
       uint8_t RESERVED_84[12];
  __I  uint32_t CH11_DEBUG1;                       /**< AHB to APBH DMA Channel n Debug Information, offset: 0x620 */
       uint8_t RESERVED_85[12];
  __I  uint32_t CH11_DEBUG2;                       /**< AHB to APBH DMA Channel n Debug Information, offset: 0x630 */
       uint8_t RESERVED_86[12];
  __I  uint32_t CH12_CURCMDAR;                     /**< APBH DMA Channel n Current Command Address Register, offset: 0x640 */
       uint8_t RESERVED_87[12];
  __IO uint32_t CH12_NXTCMDAR;                     /**< APBH DMA Channel n Next Command Address Register, offset: 0x650 */
       uint8_t RESERVED_88[12];
  __I  uint32_t CH12_CMD;                          /**< APBH DMA Channel n Command Register, offset: 0x660 */
       uint8_t RESERVED_89[12];
  __I  uint32_t CH12_BAR;                          /**< APBH DMA Channel n Buffer Address Register, offset: 0x670 */
       uint8_t RESERVED_90[12];
  __IO uint32_t CH12_SEMA;                         /**< APBH DMA Channel n Semaphore Register, offset: 0x680 */
       uint8_t RESERVED_91[12];
  __I  uint32_t CH12_DEBUG1;                       /**< AHB to APBH DMA Channel n Debug Information, offset: 0x690 */
       uint8_t RESERVED_92[12];
  __I  uint32_t CH12_DEBUG2;                       /**< AHB to APBH DMA Channel n Debug Information, offset: 0x6A0 */
       uint8_t RESERVED_93[12];
  __I  uint32_t CH13_CURCMDAR;                     /**< APBH DMA Channel n Current Command Address Register, offset: 0x6B0 */
       uint8_t RESERVED_94[12];
  __IO uint32_t CH13_NXTCMDAR;                     /**< APBH DMA Channel n Next Command Address Register, offset: 0x6C0 */
       uint8_t RESERVED_95[12];
  __I  uint32_t CH13_CMD;                          /**< APBH DMA Channel n Command Register, offset: 0x6D0 */
       uint8_t RESERVED_96[12];
  __I  uint32_t CH13_BAR;                          /**< APBH DMA Channel n Buffer Address Register, offset: 0x6E0 */
       uint8_t RESERVED_97[12];
  __IO uint32_t CH13_SEMA;                         /**< APBH DMA Channel n Semaphore Register, offset: 0x6F0 */
       uint8_t RESERVED_98[12];
  __I  uint32_t CH13_DEBUG1;                       /**< AHB to APBH DMA Channel n Debug Information, offset: 0x700 */
       uint8_t RESERVED_99[12];
  __I  uint32_t CH13_DEBUG2;                       /**< AHB to APBH DMA Channel n Debug Information, offset: 0x710 */
       uint8_t RESERVED_100[12];
  __I  uint32_t CH14_CURCMDAR;                     /**< APBH DMA Channel n Current Command Address Register, offset: 0x720 */
       uint8_t RESERVED_101[12];
  __IO uint32_t CH14_NXTCMDAR;                     /**< APBH DMA Channel n Next Command Address Register, offset: 0x730 */
       uint8_t RESERVED_102[12];
  __I  uint32_t CH14_CMD;                          /**< APBH DMA Channel n Command Register, offset: 0x740 */
       uint8_t RESERVED_103[12];
  __I  uint32_t CH14_BAR;                          /**< APBH DMA Channel n Buffer Address Register, offset: 0x750 */
       uint8_t RESERVED_104[12];
  __IO uint32_t CH14_SEMA;                         /**< APBH DMA Channel n Semaphore Register, offset: 0x760 */
       uint8_t RESERVED_105[12];
  __I  uint32_t CH14_DEBUG1;                       /**< AHB to APBH DMA Channel n Debug Information, offset: 0x770 */
       uint8_t RESERVED_106[12];
  __I  uint32_t CH14_DEBUG2;                       /**< AHB to APBH DMA Channel n Debug Information, offset: 0x780 */
       uint8_t RESERVED_107[12];
  __I  uint32_t CH15_CURCMDAR;                     /**< APBH DMA Channel n Current Command Address Register, offset: 0x790 */
       uint8_t RESERVED_108[12];
  __IO uint32_t CH15_NXTCMDAR;                     /**< APBH DMA Channel n Next Command Address Register, offset: 0x7A0 */
       uint8_t RESERVED_109[12];
  __I  uint32_t CH15_CMD;                          /**< APBH DMA Channel n Command Register, offset: 0x7B0 */
       uint8_t RESERVED_110[12];
  __I  uint32_t CH15_BAR;                          /**< APBH DMA Channel n Buffer Address Register, offset: 0x7C0 */
       uint8_t RESERVED_111[12];
  __IO uint32_t CH15_SEMA;                         /**< APBH DMA Channel n Semaphore Register, offset: 0x7D0 */
       uint8_t RESERVED_112[12];
  __I  uint32_t CH15_DEBUG1;                       /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7E0 */
       uint8_t RESERVED_113[12];
  __I  uint32_t CH15_DEBUG2;                       /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7F0 */
       uint8_t RESERVED_114[12];
  __I  uint32_t VERSION;                           /**< APBH Bridge Version Register, offset: 0x800 */
} APBH_Type;

/* ----------------------------------------------------------------------------
   -- APBH Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup APBH_Register_Masks APBH Register Masks
 * @{
 */

/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
/*! @{ */
#define APBH_CTRL0_CLKGATE_CHANNEL_MASK          (0xFFFFU)
#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT         (0U)
#define APBH_CTRL0_CLKGATE_CHANNEL(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
#define APBH_CTRL0_APB_BURST_EN_MASK             (0x10000000U)
#define APBH_CTRL0_APB_BURST_EN_SHIFT            (28U)
#define APBH_CTRL0_APB_BURST_EN(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
#define APBH_CTRL0_AHB_BURST8_EN_MASK            (0x20000000U)
#define APBH_CTRL0_AHB_BURST8_EN_SHIFT           (29U)
#define APBH_CTRL0_AHB_BURST8_EN(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
#define APBH_CTRL0_CLKGATE_MASK                  (0x40000000U)
#define APBH_CTRL0_CLKGATE_SHIFT                 (30U)
#define APBH_CTRL0_CLKGATE(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
#define APBH_CTRL0_SFTRST_MASK                   (0x80000000U)
#define APBH_CTRL0_SFTRST_SHIFT                  (31U)
#define APBH_CTRL0_SFTRST(x)                     (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
/*! @} */

/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
/*! @{ */
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK         (0x1U)
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT        (0U)
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK         (0x2U)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT        (1U)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK         (0x4U)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT        (2U)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK         (0x8U)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT        (3U)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK         (0x10U)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT        (4U)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK         (0x20U)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT        (5U)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK         (0x40U)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT        (6U)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK         (0x80U)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT        (7U)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK         (0x100U)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT        (8U)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK         (0x200U)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT        (9U)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK        (0x400U)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT       (10U)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK        (0x800U)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT       (11U)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK        (0x1000U)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT       (12U)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK        (0x2000U)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT       (13U)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK        (0x4000U)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT       (14U)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK        (0x8000U)
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT       (15U)
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK      (0x10000U)
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT     (16U)
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK      (0x20000U)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT     (17U)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK      (0x40000U)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT     (18U)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK      (0x80000U)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT     (19U)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK      (0x100000U)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT     (20U)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK      (0x200000U)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT     (21U)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK      (0x400000U)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT     (22U)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK      (0x800000U)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT     (23U)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK      (0x1000000U)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT     (24U)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK      (0x2000000U)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT     (25U)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK     (0x4000000U)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT    (26U)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK     (0x8000000U)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT    (27U)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK     (0x10000000U)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT    (28U)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK     (0x20000000U)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT    (29U)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK     (0x40000000U)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT    (30U)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK     (0x80000000U)
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT    (31U)
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
/*! @} */

/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
/*! @{ */
#define APBH_CTRL2_CH0_ERROR_IRQ_MASK            (0x1U)
#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT           (0U)
#define APBH_CTRL2_CH0_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH1_ERROR_IRQ_MASK            (0x2U)
#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT           (1U)
#define APBH_CTRL2_CH1_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH2_ERROR_IRQ_MASK            (0x4U)
#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT           (2U)
#define APBH_CTRL2_CH2_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH3_ERROR_IRQ_MASK            (0x8U)
#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT           (3U)
#define APBH_CTRL2_CH3_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH4_ERROR_IRQ_MASK            (0x10U)
#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT           (4U)
#define APBH_CTRL2_CH4_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH5_ERROR_IRQ_MASK            (0x20U)
#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT           (5U)
#define APBH_CTRL2_CH5_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH6_ERROR_IRQ_MASK            (0x40U)
#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT           (6U)
#define APBH_CTRL2_CH6_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH7_ERROR_IRQ_MASK            (0x80U)
#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT           (7U)
#define APBH_CTRL2_CH7_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH8_ERROR_IRQ_MASK            (0x100U)
#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT           (8U)
#define APBH_CTRL2_CH8_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH9_ERROR_IRQ_MASK            (0x200U)
#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT           (9U)
#define APBH_CTRL2_CH9_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH10_ERROR_IRQ_MASK           (0x400U)
#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT          (10U)
#define APBH_CTRL2_CH10_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH11_ERROR_IRQ_MASK           (0x800U)
#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT          (11U)
#define APBH_CTRL2_CH11_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH12_ERROR_IRQ_MASK           (0x1000U)
#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT          (12U)
#define APBH_CTRL2_CH12_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH13_ERROR_IRQ_MASK           (0x2000U)
#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT          (13U)
#define APBH_CTRL2_CH13_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH14_ERROR_IRQ_MASK           (0x4000U)
#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT          (14U)
#define APBH_CTRL2_CH14_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH15_ERROR_IRQ_MASK           (0x8000U)
#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT          (15U)
#define APBH_CTRL2_CH15_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH0_ERROR_STATUS_MASK         (0x10000U)
#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT        (16U)
/*! CH0_ERROR_STATUS - CH0_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH0_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH1_ERROR_STATUS_MASK         (0x20000U)
#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT        (17U)
/*! CH1_ERROR_STATUS - CH1_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH1_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH2_ERROR_STATUS_MASK         (0x40000U)
#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT        (18U)
/*! CH2_ERROR_STATUS - CH2_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH2_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH3_ERROR_STATUS_MASK         (0x80000U)
#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT        (19U)
/*! CH3_ERROR_STATUS - CH3_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH3_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH4_ERROR_STATUS_MASK         (0x100000U)
#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT        (20U)
/*! CH4_ERROR_STATUS - CH4_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH4_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH5_ERROR_STATUS_MASK         (0x200000U)
#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT        (21U)
/*! CH5_ERROR_STATUS - CH5_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH5_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH6_ERROR_STATUS_MASK         (0x400000U)
#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT        (22U)
/*! CH6_ERROR_STATUS - CH6_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH6_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH7_ERROR_STATUS_MASK         (0x800000U)
#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT        (23U)
/*! CH7_ERROR_STATUS - CH7_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH7_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH8_ERROR_STATUS_MASK         (0x1000000U)
#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT        (24U)
/*! CH8_ERROR_STATUS - CH8_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH8_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH9_ERROR_STATUS_MASK         (0x2000000U)
#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT        (25U)
/*! CH9_ERROR_STATUS - CH9_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH9_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH10_ERROR_STATUS_MASK        (0x4000000U)
#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT       (26U)
/*! CH10_ERROR_STATUS - CH10_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH10_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH11_ERROR_STATUS_MASK        (0x8000000U)
#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT       (27U)
/*! CH11_ERROR_STATUS - CH11_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH11_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH12_ERROR_STATUS_MASK        (0x10000000U)
#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT       (28U)
/*! CH12_ERROR_STATUS - CH12_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH12_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH13_ERROR_STATUS_MASK        (0x20000000U)
#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT       (29U)
/*! CH13_ERROR_STATUS - CH13_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH13_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH14_ERROR_STATUS_MASK        (0x40000000U)
#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT       (30U)
/*! CH14_ERROR_STATUS - CH14_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH14_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH15_ERROR_STATUS_MASK        (0x80000000U)
#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT       (31U)
/*! CH15_ERROR_STATUS - CH15_ERROR_STATUS
 *  0b0..An early termination from the device causes error IRQ.
 *  0b1..An AHB bus error causes error IRQ.
 */
#define APBH_CTRL2_CH15_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
/*! @} */

/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
/*! @{ */
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK    (0xFFFFU)
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT   (0U)
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK     (0xFFFF0000U)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT    (16U)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
/*! @} */

/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
/*! @{ */
#define APBH_DMA_BURST_SIZE_CH0_MASK             (0x3U)
#define APBH_DMA_BURST_SIZE_CH0_SHIFT            (0U)
#define APBH_DMA_BURST_SIZE_CH0(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
#define APBH_DMA_BURST_SIZE_CH1_MASK             (0xCU)
#define APBH_DMA_BURST_SIZE_CH1_SHIFT            (2U)
#define APBH_DMA_BURST_SIZE_CH1(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
#define APBH_DMA_BURST_SIZE_CH2_MASK             (0x30U)
#define APBH_DMA_BURST_SIZE_CH2_SHIFT            (4U)
#define APBH_DMA_BURST_SIZE_CH2(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
#define APBH_DMA_BURST_SIZE_CH3_MASK             (0xC0U)
#define APBH_DMA_BURST_SIZE_CH3_SHIFT            (6U)
#define APBH_DMA_BURST_SIZE_CH3(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
#define APBH_DMA_BURST_SIZE_CH4_MASK             (0x300U)
#define APBH_DMA_BURST_SIZE_CH4_SHIFT            (8U)
#define APBH_DMA_BURST_SIZE_CH4(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
#define APBH_DMA_BURST_SIZE_CH5_MASK             (0xC00U)
#define APBH_DMA_BURST_SIZE_CH5_SHIFT            (10U)
#define APBH_DMA_BURST_SIZE_CH5(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
#define APBH_DMA_BURST_SIZE_CH6_MASK             (0x3000U)
#define APBH_DMA_BURST_SIZE_CH6_SHIFT            (12U)
#define APBH_DMA_BURST_SIZE_CH6(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
#define APBH_DMA_BURST_SIZE_CH7_MASK             (0xC000U)
#define APBH_DMA_BURST_SIZE_CH7_SHIFT            (14U)
#define APBH_DMA_BURST_SIZE_CH7(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
#define APBH_DMA_BURST_SIZE_CH8_MASK             (0x30000U)
#define APBH_DMA_BURST_SIZE_CH8_SHIFT            (16U)
#define APBH_DMA_BURST_SIZE_CH8(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
/*! @} */

/*! @name DEBUG - AHB to APBH DMA Debug Register */
/*! @{ */
#define APBH_DEBUG_GPMI_ONE_FIFO_MASK            (0x1U)
#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT           (0U)
#define APBH_DEBUG_GPMI_ONE_FIFO(x)              (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
/*! @} */

/*! @name CH0_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH0_CURCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH0_CURCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH0_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH0_NXTCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH0_NXTCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH0_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH0_CMD_COMMAND_MASK                (0x3U)
#define APBH_CH0_CMD_COMMAND_SHIFT               (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH0_CMD_COMMAND(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_COMMAND_SHIFT)) & APBH_CH0_CMD_COMMAND_MASK)
#define APBH_CH0_CMD_CHAIN_MASK                  (0x4U)
#define APBH_CH0_CMD_CHAIN_SHIFT                 (2U)
#define APBH_CH0_CMD_CHAIN(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CHAIN_SHIFT)) & APBH_CH0_CMD_CHAIN_MASK)
#define APBH_CH0_CMD_IRQONCMPLT_MASK             (0x8U)
#define APBH_CH0_CMD_IRQONCMPLT_SHIFT            (3U)
#define APBH_CH0_CMD_IRQONCMPLT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_IRQONCMPLT_SHIFT)) & APBH_CH0_CMD_IRQONCMPLT_MASK)
#define APBH_CH0_CMD_NANDLOCK_MASK               (0x10U)
#define APBH_CH0_CMD_NANDLOCK_SHIFT              (4U)
#define APBH_CH0_CMD_NANDLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDLOCK_SHIFT)) & APBH_CH0_CMD_NANDLOCK_MASK)
#define APBH_CH0_CMD_NANDWAIT4READY_MASK         (0x20U)
#define APBH_CH0_CMD_NANDWAIT4READY_SHIFT        (5U)
#define APBH_CH0_CMD_NANDWAIT4READY(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH0_CMD_NANDWAIT4READY_MASK)
#define APBH_CH0_CMD_SEMAPHORE_MASK              (0x40U)
#define APBH_CH0_CMD_SEMAPHORE_SHIFT             (6U)
#define APBH_CH0_CMD_SEMAPHORE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_SEMAPHORE_SHIFT)) & APBH_CH0_CMD_SEMAPHORE_MASK)
#define APBH_CH0_CMD_WAIT4ENDCMD_MASK            (0x80U)
#define APBH_CH0_CMD_WAIT4ENDCMD_SHIFT           (7U)
#define APBH_CH0_CMD_WAIT4ENDCMD(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH0_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH0_CMD_HALTONTERMINATE_MASK        (0x100U)
#define APBH_CH0_CMD_HALTONTERMINATE_SHIFT       (8U)
#define APBH_CH0_CMD_HALTONTERMINATE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH0_CMD_HALTONTERMINATE_MASK)
#define APBH_CH0_CMD_CMDWORDS_MASK               (0xF000U)
#define APBH_CH0_CMD_CMDWORDS_SHIFT              (12U)
#define APBH_CH0_CMD_CMDWORDS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CMDWORDS_SHIFT)) & APBH_CH0_CMD_CMDWORDS_MASK)
#define APBH_CH0_CMD_XFER_COUNT_MASK             (0xFFFF0000U)
#define APBH_CH0_CMD_XFER_COUNT_SHIFT            (16U)
#define APBH_CH0_CMD_XFER_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_XFER_COUNT_SHIFT)) & APBH_CH0_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH0_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH0_BAR_ADDRESS_MASK                (0xFFFFFFFFU)
#define APBH_CH0_BAR_ADDRESS_SHIFT               (0U)
#define APBH_CH0_BAR_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH0_BAR_ADDRESS_SHIFT)) & APBH_CH0_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH0_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH0_SEMA_INCREMENT_SEMA_MASK        (0xFFU)
#define APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT       (0U)
#define APBH_CH0_SEMA_INCREMENT_SEMA(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH0_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH0_SEMA_PHORE_MASK                 (0xFF0000U)
#define APBH_CH0_SEMA_PHORE_SHIFT                (16U)
#define APBH_CH0_SEMA_PHORE(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_PHORE_SHIFT)) & APBH_CH0_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH0_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH0_DEBUG1_STATEMACHINE_MASK        (0x1FU)
#define APBH_CH0_DEBUG1_STATEMACHINE_SHIFT       (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH0_DEBUG1_STATEMACHINE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH0_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK        (0x100000U)
#define APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT       (20U)
#define APBH_CH0_DEBUG1_WR_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK       (0x200000U)
#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT      (21U)
#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK        (0x400000U)
#define APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT       (22U)
#define APBH_CH0_DEBUG1_RD_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK       (0x800000U)
#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT      (23U)
#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK    (0x1000000U)
#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT   (24U)
#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH0_DEBUG1_READY_MASK               (0x4000000U)
#define APBH_CH0_DEBUG1_READY_SHIFT              (26U)
#define APBH_CH0_DEBUG1_READY(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_READY_SHIFT)) & APBH_CH0_DEBUG1_READY_MASK)
#define APBH_CH0_DEBUG1_END_MASK                 (0x10000000U)
#define APBH_CH0_DEBUG1_END_SHIFT                (28U)
#define APBH_CH0_DEBUG1_END(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_END_SHIFT)) & APBH_CH0_DEBUG1_END_MASK)
#define APBH_CH0_DEBUG1_KICK_MASK                (0x20000000U)
#define APBH_CH0_DEBUG1_KICK_SHIFT               (29U)
#define APBH_CH0_DEBUG1_KICK(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_KICK_SHIFT)) & APBH_CH0_DEBUG1_KICK_MASK)
#define APBH_CH0_DEBUG1_BURST_MASK               (0x40000000U)
#define APBH_CH0_DEBUG1_BURST_SHIFT              (30U)
#define APBH_CH0_DEBUG1_BURST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_BURST_SHIFT)) & APBH_CH0_DEBUG1_BURST_MASK)
#define APBH_CH0_DEBUG1_REQ_MASK                 (0x80000000U)
#define APBH_CH0_DEBUG1_REQ_SHIFT                (31U)
#define APBH_CH0_DEBUG1_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_REQ_SHIFT)) & APBH_CH0_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH0_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH0_DEBUG2_AHB_BYTES_MASK           (0xFFFFU)
#define APBH_CH0_DEBUG2_AHB_BYTES_SHIFT          (0U)
#define APBH_CH0_DEBUG2_AHB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH0_DEBUG2_APB_BYTES_MASK           (0xFFFF0000U)
#define APBH_CH0_DEBUG2_APB_BYTES_SHIFT          (16U)
#define APBH_CH0_DEBUG2_APB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH1_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH1_CURCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH1_CURCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH1_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH1_NXTCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH1_NXTCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH1_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH1_CMD_COMMAND_MASK                (0x3U)
#define APBH_CH1_CMD_COMMAND_SHIFT               (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH1_CMD_COMMAND(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_COMMAND_SHIFT)) & APBH_CH1_CMD_COMMAND_MASK)
#define APBH_CH1_CMD_CHAIN_MASK                  (0x4U)
#define APBH_CH1_CMD_CHAIN_SHIFT                 (2U)
#define APBH_CH1_CMD_CHAIN(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CHAIN_SHIFT)) & APBH_CH1_CMD_CHAIN_MASK)
#define APBH_CH1_CMD_IRQONCMPLT_MASK             (0x8U)
#define APBH_CH1_CMD_IRQONCMPLT_SHIFT            (3U)
#define APBH_CH1_CMD_IRQONCMPLT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_IRQONCMPLT_SHIFT)) & APBH_CH1_CMD_IRQONCMPLT_MASK)
#define APBH_CH1_CMD_NANDLOCK_MASK               (0x10U)
#define APBH_CH1_CMD_NANDLOCK_SHIFT              (4U)
#define APBH_CH1_CMD_NANDLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDLOCK_SHIFT)) & APBH_CH1_CMD_NANDLOCK_MASK)
#define APBH_CH1_CMD_NANDWAIT4READY_MASK         (0x20U)
#define APBH_CH1_CMD_NANDWAIT4READY_SHIFT        (5U)
#define APBH_CH1_CMD_NANDWAIT4READY(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH1_CMD_NANDWAIT4READY_MASK)
#define APBH_CH1_CMD_SEMAPHORE_MASK              (0x40U)
#define APBH_CH1_CMD_SEMAPHORE_SHIFT             (6U)
#define APBH_CH1_CMD_SEMAPHORE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_SEMAPHORE_SHIFT)) & APBH_CH1_CMD_SEMAPHORE_MASK)
#define APBH_CH1_CMD_WAIT4ENDCMD_MASK            (0x80U)
#define APBH_CH1_CMD_WAIT4ENDCMD_SHIFT           (7U)
#define APBH_CH1_CMD_WAIT4ENDCMD(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH1_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH1_CMD_HALTONTERMINATE_MASK        (0x100U)
#define APBH_CH1_CMD_HALTONTERMINATE_SHIFT       (8U)
#define APBH_CH1_CMD_HALTONTERMINATE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH1_CMD_HALTONTERMINATE_MASK)
#define APBH_CH1_CMD_CMDWORDS_MASK               (0xF000U)
#define APBH_CH1_CMD_CMDWORDS_SHIFT              (12U)
#define APBH_CH1_CMD_CMDWORDS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CMDWORDS_SHIFT)) & APBH_CH1_CMD_CMDWORDS_MASK)
#define APBH_CH1_CMD_XFER_COUNT_MASK             (0xFFFF0000U)
#define APBH_CH1_CMD_XFER_COUNT_SHIFT            (16U)
#define APBH_CH1_CMD_XFER_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_XFER_COUNT_SHIFT)) & APBH_CH1_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH1_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH1_BAR_ADDRESS_MASK                (0xFFFFFFFFU)
#define APBH_CH1_BAR_ADDRESS_SHIFT               (0U)
#define APBH_CH1_BAR_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH1_BAR_ADDRESS_SHIFT)) & APBH_CH1_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH1_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH1_SEMA_INCREMENT_SEMA_MASK        (0xFFU)
#define APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT       (0U)
#define APBH_CH1_SEMA_INCREMENT_SEMA(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH1_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH1_SEMA_PHORE_MASK                 (0xFF0000U)
#define APBH_CH1_SEMA_PHORE_SHIFT                (16U)
#define APBH_CH1_SEMA_PHORE(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_PHORE_SHIFT)) & APBH_CH1_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH1_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH1_DEBUG1_STATEMACHINE_MASK        (0x1FU)
#define APBH_CH1_DEBUG1_STATEMACHINE_SHIFT       (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH1_DEBUG1_STATEMACHINE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH1_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK        (0x100000U)
#define APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT       (20U)
#define APBH_CH1_DEBUG1_WR_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK       (0x200000U)
#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT      (21U)
#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK        (0x400000U)
#define APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT       (22U)
#define APBH_CH1_DEBUG1_RD_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK       (0x800000U)
#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT      (23U)
#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK    (0x1000000U)
#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT   (24U)
#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH1_DEBUG1_READY_MASK               (0x4000000U)
#define APBH_CH1_DEBUG1_READY_SHIFT              (26U)
#define APBH_CH1_DEBUG1_READY(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_READY_SHIFT)) & APBH_CH1_DEBUG1_READY_MASK)
#define APBH_CH1_DEBUG1_END_MASK                 (0x10000000U)
#define APBH_CH1_DEBUG1_END_SHIFT                (28U)
#define APBH_CH1_DEBUG1_END(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_END_SHIFT)) & APBH_CH1_DEBUG1_END_MASK)
#define APBH_CH1_DEBUG1_KICK_MASK                (0x20000000U)
#define APBH_CH1_DEBUG1_KICK_SHIFT               (29U)
#define APBH_CH1_DEBUG1_KICK(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_KICK_SHIFT)) & APBH_CH1_DEBUG1_KICK_MASK)
#define APBH_CH1_DEBUG1_BURST_MASK               (0x40000000U)
#define APBH_CH1_DEBUG1_BURST_SHIFT              (30U)
#define APBH_CH1_DEBUG1_BURST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_BURST_SHIFT)) & APBH_CH1_DEBUG1_BURST_MASK)
#define APBH_CH1_DEBUG1_REQ_MASK                 (0x80000000U)
#define APBH_CH1_DEBUG1_REQ_SHIFT                (31U)
#define APBH_CH1_DEBUG1_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_REQ_SHIFT)) & APBH_CH1_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH1_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH1_DEBUG2_AHB_BYTES_MASK           (0xFFFFU)
#define APBH_CH1_DEBUG2_AHB_BYTES_SHIFT          (0U)
#define APBH_CH1_DEBUG2_AHB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH1_DEBUG2_APB_BYTES_MASK           (0xFFFF0000U)
#define APBH_CH1_DEBUG2_APB_BYTES_SHIFT          (16U)
#define APBH_CH1_DEBUG2_APB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH2_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH2_CURCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH2_CURCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH2_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH2_NXTCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH2_NXTCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH2_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH2_CMD_COMMAND_MASK                (0x3U)
#define APBH_CH2_CMD_COMMAND_SHIFT               (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH2_CMD_COMMAND(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_COMMAND_SHIFT)) & APBH_CH2_CMD_COMMAND_MASK)
#define APBH_CH2_CMD_CHAIN_MASK                  (0x4U)
#define APBH_CH2_CMD_CHAIN_SHIFT                 (2U)
#define APBH_CH2_CMD_CHAIN(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CHAIN_SHIFT)) & APBH_CH2_CMD_CHAIN_MASK)
#define APBH_CH2_CMD_IRQONCMPLT_MASK             (0x8U)
#define APBH_CH2_CMD_IRQONCMPLT_SHIFT            (3U)
#define APBH_CH2_CMD_IRQONCMPLT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_IRQONCMPLT_SHIFT)) & APBH_CH2_CMD_IRQONCMPLT_MASK)
#define APBH_CH2_CMD_NANDLOCK_MASK               (0x10U)
#define APBH_CH2_CMD_NANDLOCK_SHIFT              (4U)
#define APBH_CH2_CMD_NANDLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDLOCK_SHIFT)) & APBH_CH2_CMD_NANDLOCK_MASK)
#define APBH_CH2_CMD_NANDWAIT4READY_MASK         (0x20U)
#define APBH_CH2_CMD_NANDWAIT4READY_SHIFT        (5U)
#define APBH_CH2_CMD_NANDWAIT4READY(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH2_CMD_NANDWAIT4READY_MASK)
#define APBH_CH2_CMD_SEMAPHORE_MASK              (0x40U)
#define APBH_CH2_CMD_SEMAPHORE_SHIFT             (6U)
#define APBH_CH2_CMD_SEMAPHORE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_SEMAPHORE_SHIFT)) & APBH_CH2_CMD_SEMAPHORE_MASK)
#define APBH_CH2_CMD_WAIT4ENDCMD_MASK            (0x80U)
#define APBH_CH2_CMD_WAIT4ENDCMD_SHIFT           (7U)
#define APBH_CH2_CMD_WAIT4ENDCMD(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH2_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH2_CMD_HALTONTERMINATE_MASK        (0x100U)
#define APBH_CH2_CMD_HALTONTERMINATE_SHIFT       (8U)
#define APBH_CH2_CMD_HALTONTERMINATE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH2_CMD_HALTONTERMINATE_MASK)
#define APBH_CH2_CMD_CMDWORDS_MASK               (0xF000U)
#define APBH_CH2_CMD_CMDWORDS_SHIFT              (12U)
#define APBH_CH2_CMD_CMDWORDS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CMDWORDS_SHIFT)) & APBH_CH2_CMD_CMDWORDS_MASK)
#define APBH_CH2_CMD_XFER_COUNT_MASK             (0xFFFF0000U)
#define APBH_CH2_CMD_XFER_COUNT_SHIFT            (16U)
#define APBH_CH2_CMD_XFER_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_XFER_COUNT_SHIFT)) & APBH_CH2_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH2_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH2_BAR_ADDRESS_MASK                (0xFFFFFFFFU)
#define APBH_CH2_BAR_ADDRESS_SHIFT               (0U)
#define APBH_CH2_BAR_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH2_BAR_ADDRESS_SHIFT)) & APBH_CH2_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH2_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH2_SEMA_INCREMENT_SEMA_MASK        (0xFFU)
#define APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT       (0U)
#define APBH_CH2_SEMA_INCREMENT_SEMA(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH2_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH2_SEMA_PHORE_MASK                 (0xFF0000U)
#define APBH_CH2_SEMA_PHORE_SHIFT                (16U)
#define APBH_CH2_SEMA_PHORE(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_PHORE_SHIFT)) & APBH_CH2_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH2_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH2_DEBUG1_STATEMACHINE_MASK        (0x1FU)
#define APBH_CH2_DEBUG1_STATEMACHINE_SHIFT       (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH2_DEBUG1_STATEMACHINE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH2_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK        (0x100000U)
#define APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT       (20U)
#define APBH_CH2_DEBUG1_WR_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK       (0x200000U)
#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT      (21U)
#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK        (0x400000U)
#define APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT       (22U)
#define APBH_CH2_DEBUG1_RD_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK       (0x800000U)
#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT      (23U)
#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK    (0x1000000U)
#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT   (24U)
#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH2_DEBUG1_READY_MASK               (0x4000000U)
#define APBH_CH2_DEBUG1_READY_SHIFT              (26U)
#define APBH_CH2_DEBUG1_READY(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_READY_SHIFT)) & APBH_CH2_DEBUG1_READY_MASK)
#define APBH_CH2_DEBUG1_END_MASK                 (0x10000000U)
#define APBH_CH2_DEBUG1_END_SHIFT                (28U)
#define APBH_CH2_DEBUG1_END(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_END_SHIFT)) & APBH_CH2_DEBUG1_END_MASK)
#define APBH_CH2_DEBUG1_KICK_MASK                (0x20000000U)
#define APBH_CH2_DEBUG1_KICK_SHIFT               (29U)
#define APBH_CH2_DEBUG1_KICK(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_KICK_SHIFT)) & APBH_CH2_DEBUG1_KICK_MASK)
#define APBH_CH2_DEBUG1_BURST_MASK               (0x40000000U)
#define APBH_CH2_DEBUG1_BURST_SHIFT              (30U)
#define APBH_CH2_DEBUG1_BURST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_BURST_SHIFT)) & APBH_CH2_DEBUG1_BURST_MASK)
#define APBH_CH2_DEBUG1_REQ_MASK                 (0x80000000U)
#define APBH_CH2_DEBUG1_REQ_SHIFT                (31U)
#define APBH_CH2_DEBUG1_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_REQ_SHIFT)) & APBH_CH2_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH2_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH2_DEBUG2_AHB_BYTES_MASK           (0xFFFFU)
#define APBH_CH2_DEBUG2_AHB_BYTES_SHIFT          (0U)
#define APBH_CH2_DEBUG2_AHB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH2_DEBUG2_APB_BYTES_MASK           (0xFFFF0000U)
#define APBH_CH2_DEBUG2_APB_BYTES_SHIFT          (16U)
#define APBH_CH2_DEBUG2_APB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH3_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH3_CURCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH3_CURCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH3_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH3_NXTCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH3_NXTCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH3_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH3_CMD_COMMAND_MASK                (0x3U)
#define APBH_CH3_CMD_COMMAND_SHIFT               (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH3_CMD_COMMAND(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_COMMAND_SHIFT)) & APBH_CH3_CMD_COMMAND_MASK)
#define APBH_CH3_CMD_CHAIN_MASK                  (0x4U)
#define APBH_CH3_CMD_CHAIN_SHIFT                 (2U)
#define APBH_CH3_CMD_CHAIN(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CHAIN_SHIFT)) & APBH_CH3_CMD_CHAIN_MASK)
#define APBH_CH3_CMD_IRQONCMPLT_MASK             (0x8U)
#define APBH_CH3_CMD_IRQONCMPLT_SHIFT            (3U)
#define APBH_CH3_CMD_IRQONCMPLT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_IRQONCMPLT_SHIFT)) & APBH_CH3_CMD_IRQONCMPLT_MASK)
#define APBH_CH3_CMD_NANDLOCK_MASK               (0x10U)
#define APBH_CH3_CMD_NANDLOCK_SHIFT              (4U)
#define APBH_CH3_CMD_NANDLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDLOCK_SHIFT)) & APBH_CH3_CMD_NANDLOCK_MASK)
#define APBH_CH3_CMD_NANDWAIT4READY_MASK         (0x20U)
#define APBH_CH3_CMD_NANDWAIT4READY_SHIFT        (5U)
#define APBH_CH3_CMD_NANDWAIT4READY(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH3_CMD_NANDWAIT4READY_MASK)
#define APBH_CH3_CMD_SEMAPHORE_MASK              (0x40U)
#define APBH_CH3_CMD_SEMAPHORE_SHIFT             (6U)
#define APBH_CH3_CMD_SEMAPHORE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_SEMAPHORE_SHIFT)) & APBH_CH3_CMD_SEMAPHORE_MASK)
#define APBH_CH3_CMD_WAIT4ENDCMD_MASK            (0x80U)
#define APBH_CH3_CMD_WAIT4ENDCMD_SHIFT           (7U)
#define APBH_CH3_CMD_WAIT4ENDCMD(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH3_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH3_CMD_HALTONTERMINATE_MASK        (0x100U)
#define APBH_CH3_CMD_HALTONTERMINATE_SHIFT       (8U)
#define APBH_CH3_CMD_HALTONTERMINATE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH3_CMD_HALTONTERMINATE_MASK)
#define APBH_CH3_CMD_CMDWORDS_MASK               (0xF000U)
#define APBH_CH3_CMD_CMDWORDS_SHIFT              (12U)
#define APBH_CH3_CMD_CMDWORDS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CMDWORDS_SHIFT)) & APBH_CH3_CMD_CMDWORDS_MASK)
#define APBH_CH3_CMD_XFER_COUNT_MASK             (0xFFFF0000U)
#define APBH_CH3_CMD_XFER_COUNT_SHIFT            (16U)
#define APBH_CH3_CMD_XFER_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_XFER_COUNT_SHIFT)) & APBH_CH3_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH3_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH3_BAR_ADDRESS_MASK                (0xFFFFFFFFU)
#define APBH_CH3_BAR_ADDRESS_SHIFT               (0U)
#define APBH_CH3_BAR_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH3_BAR_ADDRESS_SHIFT)) & APBH_CH3_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH3_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH3_SEMA_INCREMENT_SEMA_MASK        (0xFFU)
#define APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT       (0U)
#define APBH_CH3_SEMA_INCREMENT_SEMA(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH3_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH3_SEMA_PHORE_MASK                 (0xFF0000U)
#define APBH_CH3_SEMA_PHORE_SHIFT                (16U)
#define APBH_CH3_SEMA_PHORE(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_PHORE_SHIFT)) & APBH_CH3_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH3_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH3_DEBUG1_STATEMACHINE_MASK        (0x1FU)
#define APBH_CH3_DEBUG1_STATEMACHINE_SHIFT       (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH3_DEBUG1_STATEMACHINE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH3_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK        (0x100000U)
#define APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT       (20U)
#define APBH_CH3_DEBUG1_WR_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK       (0x200000U)
#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT      (21U)
#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK        (0x400000U)
#define APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT       (22U)
#define APBH_CH3_DEBUG1_RD_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK       (0x800000U)
#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT      (23U)
#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK    (0x1000000U)
#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT   (24U)
#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH3_DEBUG1_READY_MASK               (0x4000000U)
#define APBH_CH3_DEBUG1_READY_SHIFT              (26U)
#define APBH_CH3_DEBUG1_READY(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_READY_SHIFT)) & APBH_CH3_DEBUG1_READY_MASK)
#define APBH_CH3_DEBUG1_END_MASK                 (0x10000000U)
#define APBH_CH3_DEBUG1_END_SHIFT                (28U)
#define APBH_CH3_DEBUG1_END(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_END_SHIFT)) & APBH_CH3_DEBUG1_END_MASK)
#define APBH_CH3_DEBUG1_KICK_MASK                (0x20000000U)
#define APBH_CH3_DEBUG1_KICK_SHIFT               (29U)
#define APBH_CH3_DEBUG1_KICK(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_KICK_SHIFT)) & APBH_CH3_DEBUG1_KICK_MASK)
#define APBH_CH3_DEBUG1_BURST_MASK               (0x40000000U)
#define APBH_CH3_DEBUG1_BURST_SHIFT              (30U)
#define APBH_CH3_DEBUG1_BURST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_BURST_SHIFT)) & APBH_CH3_DEBUG1_BURST_MASK)
#define APBH_CH3_DEBUG1_REQ_MASK                 (0x80000000U)
#define APBH_CH3_DEBUG1_REQ_SHIFT                (31U)
#define APBH_CH3_DEBUG1_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_REQ_SHIFT)) & APBH_CH3_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH3_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH3_DEBUG2_AHB_BYTES_MASK           (0xFFFFU)
#define APBH_CH3_DEBUG2_AHB_BYTES_SHIFT          (0U)
#define APBH_CH3_DEBUG2_AHB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH3_DEBUG2_APB_BYTES_MASK           (0xFFFF0000U)
#define APBH_CH3_DEBUG2_APB_BYTES_SHIFT          (16U)
#define APBH_CH3_DEBUG2_APB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH4_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH4_CURCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH4_CURCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH4_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH4_NXTCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH4_NXTCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH4_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH4_CMD_COMMAND_MASK                (0x3U)
#define APBH_CH4_CMD_COMMAND_SHIFT               (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH4_CMD_COMMAND(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_COMMAND_SHIFT)) & APBH_CH4_CMD_COMMAND_MASK)
#define APBH_CH4_CMD_CHAIN_MASK                  (0x4U)
#define APBH_CH4_CMD_CHAIN_SHIFT                 (2U)
#define APBH_CH4_CMD_CHAIN(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CHAIN_SHIFT)) & APBH_CH4_CMD_CHAIN_MASK)
#define APBH_CH4_CMD_IRQONCMPLT_MASK             (0x8U)
#define APBH_CH4_CMD_IRQONCMPLT_SHIFT            (3U)
#define APBH_CH4_CMD_IRQONCMPLT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_IRQONCMPLT_SHIFT)) & APBH_CH4_CMD_IRQONCMPLT_MASK)
#define APBH_CH4_CMD_NANDLOCK_MASK               (0x10U)
#define APBH_CH4_CMD_NANDLOCK_SHIFT              (4U)
#define APBH_CH4_CMD_NANDLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDLOCK_SHIFT)) & APBH_CH4_CMD_NANDLOCK_MASK)
#define APBH_CH4_CMD_NANDWAIT4READY_MASK         (0x20U)
#define APBH_CH4_CMD_NANDWAIT4READY_SHIFT        (5U)
#define APBH_CH4_CMD_NANDWAIT4READY(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH4_CMD_NANDWAIT4READY_MASK)
#define APBH_CH4_CMD_SEMAPHORE_MASK              (0x40U)
#define APBH_CH4_CMD_SEMAPHORE_SHIFT             (6U)
#define APBH_CH4_CMD_SEMAPHORE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_SEMAPHORE_SHIFT)) & APBH_CH4_CMD_SEMAPHORE_MASK)
#define APBH_CH4_CMD_WAIT4ENDCMD_MASK            (0x80U)
#define APBH_CH4_CMD_WAIT4ENDCMD_SHIFT           (7U)
#define APBH_CH4_CMD_WAIT4ENDCMD(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH4_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH4_CMD_HALTONTERMINATE_MASK        (0x100U)
#define APBH_CH4_CMD_HALTONTERMINATE_SHIFT       (8U)
#define APBH_CH4_CMD_HALTONTERMINATE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH4_CMD_HALTONTERMINATE_MASK)
#define APBH_CH4_CMD_CMDWORDS_MASK               (0xF000U)
#define APBH_CH4_CMD_CMDWORDS_SHIFT              (12U)
#define APBH_CH4_CMD_CMDWORDS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CMDWORDS_SHIFT)) & APBH_CH4_CMD_CMDWORDS_MASK)
#define APBH_CH4_CMD_XFER_COUNT_MASK             (0xFFFF0000U)
#define APBH_CH4_CMD_XFER_COUNT_SHIFT            (16U)
#define APBH_CH4_CMD_XFER_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_XFER_COUNT_SHIFT)) & APBH_CH4_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH4_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH4_BAR_ADDRESS_MASK                (0xFFFFFFFFU)
#define APBH_CH4_BAR_ADDRESS_SHIFT               (0U)
#define APBH_CH4_BAR_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH4_BAR_ADDRESS_SHIFT)) & APBH_CH4_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH4_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH4_SEMA_INCREMENT_SEMA_MASK        (0xFFU)
#define APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT       (0U)
#define APBH_CH4_SEMA_INCREMENT_SEMA(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH4_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH4_SEMA_PHORE_MASK                 (0xFF0000U)
#define APBH_CH4_SEMA_PHORE_SHIFT                (16U)
#define APBH_CH4_SEMA_PHORE(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_PHORE_SHIFT)) & APBH_CH4_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH4_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH4_DEBUG1_STATEMACHINE_MASK        (0x1FU)
#define APBH_CH4_DEBUG1_STATEMACHINE_SHIFT       (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH4_DEBUG1_STATEMACHINE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH4_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK        (0x100000U)
#define APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT       (20U)
#define APBH_CH4_DEBUG1_WR_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK       (0x200000U)
#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT      (21U)
#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK        (0x400000U)
#define APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT       (22U)
#define APBH_CH4_DEBUG1_RD_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK       (0x800000U)
#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT      (23U)
#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK    (0x1000000U)
#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT   (24U)
#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH4_DEBUG1_READY_MASK               (0x4000000U)
#define APBH_CH4_DEBUG1_READY_SHIFT              (26U)
#define APBH_CH4_DEBUG1_READY(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_READY_SHIFT)) & APBH_CH4_DEBUG1_READY_MASK)
#define APBH_CH4_DEBUG1_END_MASK                 (0x10000000U)
#define APBH_CH4_DEBUG1_END_SHIFT                (28U)
#define APBH_CH4_DEBUG1_END(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_END_SHIFT)) & APBH_CH4_DEBUG1_END_MASK)
#define APBH_CH4_DEBUG1_KICK_MASK                (0x20000000U)
#define APBH_CH4_DEBUG1_KICK_SHIFT               (29U)
#define APBH_CH4_DEBUG1_KICK(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_KICK_SHIFT)) & APBH_CH4_DEBUG1_KICK_MASK)
#define APBH_CH4_DEBUG1_BURST_MASK               (0x40000000U)
#define APBH_CH4_DEBUG1_BURST_SHIFT              (30U)
#define APBH_CH4_DEBUG1_BURST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_BURST_SHIFT)) & APBH_CH4_DEBUG1_BURST_MASK)
#define APBH_CH4_DEBUG1_REQ_MASK                 (0x80000000U)
#define APBH_CH4_DEBUG1_REQ_SHIFT                (31U)
#define APBH_CH4_DEBUG1_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_REQ_SHIFT)) & APBH_CH4_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH4_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH4_DEBUG2_AHB_BYTES_MASK           (0xFFFFU)
#define APBH_CH4_DEBUG2_AHB_BYTES_SHIFT          (0U)
#define APBH_CH4_DEBUG2_AHB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH4_DEBUG2_APB_BYTES_MASK           (0xFFFF0000U)
#define APBH_CH4_DEBUG2_APB_BYTES_SHIFT          (16U)
#define APBH_CH4_DEBUG2_APB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH5_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH5_CURCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH5_CURCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH5_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH5_NXTCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH5_NXTCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH5_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH5_CMD_COMMAND_MASK                (0x3U)
#define APBH_CH5_CMD_COMMAND_SHIFT               (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH5_CMD_COMMAND(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_COMMAND_SHIFT)) & APBH_CH5_CMD_COMMAND_MASK)
#define APBH_CH5_CMD_CHAIN_MASK                  (0x4U)
#define APBH_CH5_CMD_CHAIN_SHIFT                 (2U)
#define APBH_CH5_CMD_CHAIN(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CHAIN_SHIFT)) & APBH_CH5_CMD_CHAIN_MASK)
#define APBH_CH5_CMD_IRQONCMPLT_MASK             (0x8U)
#define APBH_CH5_CMD_IRQONCMPLT_SHIFT            (3U)
#define APBH_CH5_CMD_IRQONCMPLT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_IRQONCMPLT_SHIFT)) & APBH_CH5_CMD_IRQONCMPLT_MASK)
#define APBH_CH5_CMD_NANDLOCK_MASK               (0x10U)
#define APBH_CH5_CMD_NANDLOCK_SHIFT              (4U)
#define APBH_CH5_CMD_NANDLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK)
#define APBH_CH5_CMD_NANDWAIT4READY_MASK         (0x20U)
#define APBH_CH5_CMD_NANDWAIT4READY_SHIFT        (5U)
#define APBH_CH5_CMD_NANDWAIT4READY(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH5_CMD_NANDWAIT4READY_MASK)
#define APBH_CH5_CMD_SEMAPHORE_MASK              (0x40U)
#define APBH_CH5_CMD_SEMAPHORE_SHIFT             (6U)
#define APBH_CH5_CMD_SEMAPHORE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_SEMAPHORE_SHIFT)) & APBH_CH5_CMD_SEMAPHORE_MASK)
#define APBH_CH5_CMD_WAIT4ENDCMD_MASK            (0x80U)
#define APBH_CH5_CMD_WAIT4ENDCMD_SHIFT           (7U)
#define APBH_CH5_CMD_WAIT4ENDCMD(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH5_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH5_CMD_HALTONTERMINATE_MASK        (0x100U)
#define APBH_CH5_CMD_HALTONTERMINATE_SHIFT       (8U)
#define APBH_CH5_CMD_HALTONTERMINATE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH5_CMD_HALTONTERMINATE_MASK)
#define APBH_CH5_CMD_CMDWORDS_MASK               (0xF000U)
#define APBH_CH5_CMD_CMDWORDS_SHIFT              (12U)
#define APBH_CH5_CMD_CMDWORDS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CMDWORDS_SHIFT)) & APBH_CH5_CMD_CMDWORDS_MASK)
#define APBH_CH5_CMD_XFER_COUNT_MASK             (0xFFFF0000U)
#define APBH_CH5_CMD_XFER_COUNT_SHIFT            (16U)
#define APBH_CH5_CMD_XFER_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_XFER_COUNT_SHIFT)) & APBH_CH5_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH5_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH5_BAR_ADDRESS_MASK                (0xFFFFFFFFU)
#define APBH_CH5_BAR_ADDRESS_SHIFT               (0U)
#define APBH_CH5_BAR_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH5_BAR_ADDRESS_SHIFT)) & APBH_CH5_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH5_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH5_SEMA_INCREMENT_SEMA_MASK        (0xFFU)
#define APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT       (0U)
#define APBH_CH5_SEMA_INCREMENT_SEMA(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH5_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH5_SEMA_PHORE_MASK                 (0xFF0000U)
#define APBH_CH5_SEMA_PHORE_SHIFT                (16U)
#define APBH_CH5_SEMA_PHORE(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_PHORE_SHIFT)) & APBH_CH5_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH5_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH5_DEBUG1_STATEMACHINE_MASK        (0x1FU)
#define APBH_CH5_DEBUG1_STATEMACHINE_SHIFT       (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH5_DEBUG1_STATEMACHINE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH5_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK        (0x100000U)
#define APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT       (20U)
#define APBH_CH5_DEBUG1_WR_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK       (0x200000U)
#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT      (21U)
#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK        (0x400000U)
#define APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT       (22U)
#define APBH_CH5_DEBUG1_RD_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK       (0x800000U)
#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT      (23U)
#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK    (0x1000000U)
#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT   (24U)
#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH5_DEBUG1_READY_MASK               (0x4000000U)
#define APBH_CH5_DEBUG1_READY_SHIFT              (26U)
#define APBH_CH5_DEBUG1_READY(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_READY_SHIFT)) & APBH_CH5_DEBUG1_READY_MASK)
#define APBH_CH5_DEBUG1_END_MASK                 (0x10000000U)
#define APBH_CH5_DEBUG1_END_SHIFT                (28U)
#define APBH_CH5_DEBUG1_END(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_END_SHIFT)) & APBH_CH5_DEBUG1_END_MASK)
#define APBH_CH5_DEBUG1_KICK_MASK                (0x20000000U)
#define APBH_CH5_DEBUG1_KICK_SHIFT               (29U)
#define APBH_CH5_DEBUG1_KICK(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_KICK_SHIFT)) & APBH_CH5_DEBUG1_KICK_MASK)
#define APBH_CH5_DEBUG1_BURST_MASK               (0x40000000U)
#define APBH_CH5_DEBUG1_BURST_SHIFT              (30U)
#define APBH_CH5_DEBUG1_BURST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_BURST_SHIFT)) & APBH_CH5_DEBUG1_BURST_MASK)
#define APBH_CH5_DEBUG1_REQ_MASK                 (0x80000000U)
#define APBH_CH5_DEBUG1_REQ_SHIFT                (31U)
#define APBH_CH5_DEBUG1_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_REQ_SHIFT)) & APBH_CH5_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH5_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH5_DEBUG2_AHB_BYTES_MASK           (0xFFFFU)
#define APBH_CH5_DEBUG2_AHB_BYTES_SHIFT          (0U)
#define APBH_CH5_DEBUG2_AHB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH5_DEBUG2_APB_BYTES_MASK           (0xFFFF0000U)
#define APBH_CH5_DEBUG2_APB_BYTES_SHIFT          (16U)
#define APBH_CH5_DEBUG2_APB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH6_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH6_CURCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH6_CURCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH6_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH6_NXTCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH6_NXTCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH6_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH6_CMD_COMMAND_MASK                (0x3U)
#define APBH_CH6_CMD_COMMAND_SHIFT               (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH6_CMD_COMMAND(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_COMMAND_SHIFT)) & APBH_CH6_CMD_COMMAND_MASK)
#define APBH_CH6_CMD_CHAIN_MASK                  (0x4U)
#define APBH_CH6_CMD_CHAIN_SHIFT                 (2U)
#define APBH_CH6_CMD_CHAIN(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CHAIN_SHIFT)) & APBH_CH6_CMD_CHAIN_MASK)
#define APBH_CH6_CMD_IRQONCMPLT_MASK             (0x8U)
#define APBH_CH6_CMD_IRQONCMPLT_SHIFT            (3U)
#define APBH_CH6_CMD_IRQONCMPLT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_IRQONCMPLT_SHIFT)) & APBH_CH6_CMD_IRQONCMPLT_MASK)
#define APBH_CH6_CMD_NANDLOCK_MASK               (0x10U)
#define APBH_CH6_CMD_NANDLOCK_SHIFT              (4U)
#define APBH_CH6_CMD_NANDLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDLOCK_SHIFT)) & APBH_CH6_CMD_NANDLOCK_MASK)
#define APBH_CH6_CMD_NANDWAIT4READY_MASK         (0x20U)
#define APBH_CH6_CMD_NANDWAIT4READY_SHIFT        (5U)
#define APBH_CH6_CMD_NANDWAIT4READY(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH6_CMD_NANDWAIT4READY_MASK)
#define APBH_CH6_CMD_SEMAPHORE_MASK              (0x40U)
#define APBH_CH6_CMD_SEMAPHORE_SHIFT             (6U)
#define APBH_CH6_CMD_SEMAPHORE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_SEMAPHORE_SHIFT)) & APBH_CH6_CMD_SEMAPHORE_MASK)
#define APBH_CH6_CMD_WAIT4ENDCMD_MASK            (0x80U)
#define APBH_CH6_CMD_WAIT4ENDCMD_SHIFT           (7U)
#define APBH_CH6_CMD_WAIT4ENDCMD(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH6_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH6_CMD_HALTONTERMINATE_MASK        (0x100U)
#define APBH_CH6_CMD_HALTONTERMINATE_SHIFT       (8U)
#define APBH_CH6_CMD_HALTONTERMINATE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH6_CMD_HALTONTERMINATE_MASK)
#define APBH_CH6_CMD_CMDWORDS_MASK               (0xF000U)
#define APBH_CH6_CMD_CMDWORDS_SHIFT              (12U)
#define APBH_CH6_CMD_CMDWORDS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CMDWORDS_SHIFT)) & APBH_CH6_CMD_CMDWORDS_MASK)
#define APBH_CH6_CMD_XFER_COUNT_MASK             (0xFFFF0000U)
#define APBH_CH6_CMD_XFER_COUNT_SHIFT            (16U)
#define APBH_CH6_CMD_XFER_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_XFER_COUNT_SHIFT)) & APBH_CH6_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH6_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH6_BAR_ADDRESS_MASK                (0xFFFFFFFFU)
#define APBH_CH6_BAR_ADDRESS_SHIFT               (0U)
#define APBH_CH6_BAR_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH6_BAR_ADDRESS_SHIFT)) & APBH_CH6_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH6_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH6_SEMA_INCREMENT_SEMA_MASK        (0xFFU)
#define APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT       (0U)
#define APBH_CH6_SEMA_INCREMENT_SEMA(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH6_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH6_SEMA_PHORE_MASK                 (0xFF0000U)
#define APBH_CH6_SEMA_PHORE_SHIFT                (16U)
#define APBH_CH6_SEMA_PHORE(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_PHORE_SHIFT)) & APBH_CH6_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH6_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH6_DEBUG1_STATEMACHINE_MASK        (0x1FU)
#define APBH_CH6_DEBUG1_STATEMACHINE_SHIFT       (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH6_DEBUG1_STATEMACHINE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH6_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK        (0x100000U)
#define APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT       (20U)
#define APBH_CH6_DEBUG1_WR_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK       (0x200000U)
#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT      (21U)
#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK        (0x400000U)
#define APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT       (22U)
#define APBH_CH6_DEBUG1_RD_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK       (0x800000U)
#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT      (23U)
#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK    (0x1000000U)
#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT   (24U)
#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH6_DEBUG1_READY_MASK               (0x4000000U)
#define APBH_CH6_DEBUG1_READY_SHIFT              (26U)
#define APBH_CH6_DEBUG1_READY(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_READY_SHIFT)) & APBH_CH6_DEBUG1_READY_MASK)
#define APBH_CH6_DEBUG1_END_MASK                 (0x10000000U)
#define APBH_CH6_DEBUG1_END_SHIFT                (28U)
#define APBH_CH6_DEBUG1_END(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_END_SHIFT)) & APBH_CH6_DEBUG1_END_MASK)
#define APBH_CH6_DEBUG1_KICK_MASK                (0x20000000U)
#define APBH_CH6_DEBUG1_KICK_SHIFT               (29U)
#define APBH_CH6_DEBUG1_KICK(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_KICK_SHIFT)) & APBH_CH6_DEBUG1_KICK_MASK)
#define APBH_CH6_DEBUG1_BURST_MASK               (0x40000000U)
#define APBH_CH6_DEBUG1_BURST_SHIFT              (30U)
#define APBH_CH6_DEBUG1_BURST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_BURST_SHIFT)) & APBH_CH6_DEBUG1_BURST_MASK)
#define APBH_CH6_DEBUG1_REQ_MASK                 (0x80000000U)
#define APBH_CH6_DEBUG1_REQ_SHIFT                (31U)
#define APBH_CH6_DEBUG1_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_REQ_SHIFT)) & APBH_CH6_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH6_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH6_DEBUG2_AHB_BYTES_MASK           (0xFFFFU)
#define APBH_CH6_DEBUG2_AHB_BYTES_SHIFT          (0U)
#define APBH_CH6_DEBUG2_AHB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH6_DEBUG2_APB_BYTES_MASK           (0xFFFF0000U)
#define APBH_CH6_DEBUG2_APB_BYTES_SHIFT          (16U)
#define APBH_CH6_DEBUG2_APB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH7_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH7_CURCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH7_CURCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH7_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH7_NXTCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH7_NXTCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH7_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH7_CMD_COMMAND_MASK                (0x3U)
#define APBH_CH7_CMD_COMMAND_SHIFT               (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH7_CMD_COMMAND(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_COMMAND_SHIFT)) & APBH_CH7_CMD_COMMAND_MASK)
#define APBH_CH7_CMD_CHAIN_MASK                  (0x4U)
#define APBH_CH7_CMD_CHAIN_SHIFT                 (2U)
#define APBH_CH7_CMD_CHAIN(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CHAIN_SHIFT)) & APBH_CH7_CMD_CHAIN_MASK)
#define APBH_CH7_CMD_IRQONCMPLT_MASK             (0x8U)
#define APBH_CH7_CMD_IRQONCMPLT_SHIFT            (3U)
#define APBH_CH7_CMD_IRQONCMPLT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_IRQONCMPLT_SHIFT)) & APBH_CH7_CMD_IRQONCMPLT_MASK)
#define APBH_CH7_CMD_NANDLOCK_MASK               (0x10U)
#define APBH_CH7_CMD_NANDLOCK_SHIFT              (4U)
#define APBH_CH7_CMD_NANDLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDLOCK_SHIFT)) & APBH_CH7_CMD_NANDLOCK_MASK)
#define APBH_CH7_CMD_NANDWAIT4READY_MASK         (0x20U)
#define APBH_CH7_CMD_NANDWAIT4READY_SHIFT        (5U)
#define APBH_CH7_CMD_NANDWAIT4READY(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH7_CMD_NANDWAIT4READY_MASK)
#define APBH_CH7_CMD_SEMAPHORE_MASK              (0x40U)
#define APBH_CH7_CMD_SEMAPHORE_SHIFT             (6U)
#define APBH_CH7_CMD_SEMAPHORE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_SEMAPHORE_SHIFT)) & APBH_CH7_CMD_SEMAPHORE_MASK)
#define APBH_CH7_CMD_WAIT4ENDCMD_MASK            (0x80U)
#define APBH_CH7_CMD_WAIT4ENDCMD_SHIFT           (7U)
#define APBH_CH7_CMD_WAIT4ENDCMD(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH7_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH7_CMD_HALTONTERMINATE_MASK        (0x100U)
#define APBH_CH7_CMD_HALTONTERMINATE_SHIFT       (8U)
#define APBH_CH7_CMD_HALTONTERMINATE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH7_CMD_HALTONTERMINATE_MASK)
#define APBH_CH7_CMD_CMDWORDS_MASK               (0xF000U)
#define APBH_CH7_CMD_CMDWORDS_SHIFT              (12U)
#define APBH_CH7_CMD_CMDWORDS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CMDWORDS_SHIFT)) & APBH_CH7_CMD_CMDWORDS_MASK)
#define APBH_CH7_CMD_XFER_COUNT_MASK             (0xFFFF0000U)
#define APBH_CH7_CMD_XFER_COUNT_SHIFT            (16U)
#define APBH_CH7_CMD_XFER_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_XFER_COUNT_SHIFT)) & APBH_CH7_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH7_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH7_BAR_ADDRESS_MASK                (0xFFFFFFFFU)
#define APBH_CH7_BAR_ADDRESS_SHIFT               (0U)
#define APBH_CH7_BAR_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH7_BAR_ADDRESS_SHIFT)) & APBH_CH7_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH7_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH7_SEMA_INCREMENT_SEMA_MASK        (0xFFU)
#define APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT       (0U)
#define APBH_CH7_SEMA_INCREMENT_SEMA(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH7_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH7_SEMA_PHORE_MASK                 (0xFF0000U)
#define APBH_CH7_SEMA_PHORE_SHIFT                (16U)
#define APBH_CH7_SEMA_PHORE(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_PHORE_SHIFT)) & APBH_CH7_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH7_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH7_DEBUG1_STATEMACHINE_MASK        (0x1FU)
#define APBH_CH7_DEBUG1_STATEMACHINE_SHIFT       (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH7_DEBUG1_STATEMACHINE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH7_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK        (0x100000U)
#define APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT       (20U)
#define APBH_CH7_DEBUG1_WR_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK       (0x200000U)
#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT      (21U)
#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK        (0x400000U)
#define APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT       (22U)
#define APBH_CH7_DEBUG1_RD_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK       (0x800000U)
#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT      (23U)
#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK    (0x1000000U)
#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT   (24U)
#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH7_DEBUG1_READY_MASK               (0x4000000U)
#define APBH_CH7_DEBUG1_READY_SHIFT              (26U)
#define APBH_CH7_DEBUG1_READY(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_READY_SHIFT)) & APBH_CH7_DEBUG1_READY_MASK)
#define APBH_CH7_DEBUG1_END_MASK                 (0x10000000U)
#define APBH_CH7_DEBUG1_END_SHIFT                (28U)
#define APBH_CH7_DEBUG1_END(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_END_SHIFT)) & APBH_CH7_DEBUG1_END_MASK)
#define APBH_CH7_DEBUG1_KICK_MASK                (0x20000000U)
#define APBH_CH7_DEBUG1_KICK_SHIFT               (29U)
#define APBH_CH7_DEBUG1_KICK(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_KICK_SHIFT)) & APBH_CH7_DEBUG1_KICK_MASK)
#define APBH_CH7_DEBUG1_BURST_MASK               (0x40000000U)
#define APBH_CH7_DEBUG1_BURST_SHIFT              (30U)
#define APBH_CH7_DEBUG1_BURST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_BURST_SHIFT)) & APBH_CH7_DEBUG1_BURST_MASK)
#define APBH_CH7_DEBUG1_REQ_MASK                 (0x80000000U)
#define APBH_CH7_DEBUG1_REQ_SHIFT                (31U)
#define APBH_CH7_DEBUG1_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_REQ_SHIFT)) & APBH_CH7_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH7_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH7_DEBUG2_AHB_BYTES_MASK           (0xFFFFU)
#define APBH_CH7_DEBUG2_AHB_BYTES_SHIFT          (0U)
#define APBH_CH7_DEBUG2_AHB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH7_DEBUG2_APB_BYTES_MASK           (0xFFFF0000U)
#define APBH_CH7_DEBUG2_APB_BYTES_SHIFT          (16U)
#define APBH_CH7_DEBUG2_APB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH8_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH8_CURCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH8_CURCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH8_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH8_NXTCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH8_NXTCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH8_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH8_CMD_COMMAND_MASK                (0x3U)
#define APBH_CH8_CMD_COMMAND_SHIFT               (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH8_CMD_COMMAND(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_COMMAND_SHIFT)) & APBH_CH8_CMD_COMMAND_MASK)
#define APBH_CH8_CMD_CHAIN_MASK                  (0x4U)
#define APBH_CH8_CMD_CHAIN_SHIFT                 (2U)
#define APBH_CH8_CMD_CHAIN(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CHAIN_SHIFT)) & APBH_CH8_CMD_CHAIN_MASK)
#define APBH_CH8_CMD_IRQONCMPLT_MASK             (0x8U)
#define APBH_CH8_CMD_IRQONCMPLT_SHIFT            (3U)
#define APBH_CH8_CMD_IRQONCMPLT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_IRQONCMPLT_SHIFT)) & APBH_CH8_CMD_IRQONCMPLT_MASK)
#define APBH_CH8_CMD_NANDLOCK_MASK               (0x10U)
#define APBH_CH8_CMD_NANDLOCK_SHIFT              (4U)
#define APBH_CH8_CMD_NANDLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDLOCK_SHIFT)) & APBH_CH8_CMD_NANDLOCK_MASK)
#define APBH_CH8_CMD_NANDWAIT4READY_MASK         (0x20U)
#define APBH_CH8_CMD_NANDWAIT4READY_SHIFT        (5U)
#define APBH_CH8_CMD_NANDWAIT4READY(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH8_CMD_NANDWAIT4READY_MASK)
#define APBH_CH8_CMD_SEMAPHORE_MASK              (0x40U)
#define APBH_CH8_CMD_SEMAPHORE_SHIFT             (6U)
#define APBH_CH8_CMD_SEMAPHORE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_SEMAPHORE_SHIFT)) & APBH_CH8_CMD_SEMAPHORE_MASK)
#define APBH_CH8_CMD_WAIT4ENDCMD_MASK            (0x80U)
#define APBH_CH8_CMD_WAIT4ENDCMD_SHIFT           (7U)
#define APBH_CH8_CMD_WAIT4ENDCMD(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH8_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH8_CMD_HALTONTERMINATE_MASK        (0x100U)
#define APBH_CH8_CMD_HALTONTERMINATE_SHIFT       (8U)
#define APBH_CH8_CMD_HALTONTERMINATE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH8_CMD_HALTONTERMINATE_MASK)
#define APBH_CH8_CMD_CMDWORDS_MASK               (0xF000U)
#define APBH_CH8_CMD_CMDWORDS_SHIFT              (12U)
#define APBH_CH8_CMD_CMDWORDS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CMDWORDS_SHIFT)) & APBH_CH8_CMD_CMDWORDS_MASK)
#define APBH_CH8_CMD_XFER_COUNT_MASK             (0xFFFF0000U)
#define APBH_CH8_CMD_XFER_COUNT_SHIFT            (16U)
#define APBH_CH8_CMD_XFER_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_XFER_COUNT_SHIFT)) & APBH_CH8_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH8_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH8_BAR_ADDRESS_MASK                (0xFFFFFFFFU)
#define APBH_CH8_BAR_ADDRESS_SHIFT               (0U)
#define APBH_CH8_BAR_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH8_BAR_ADDRESS_SHIFT)) & APBH_CH8_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH8_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH8_SEMA_INCREMENT_SEMA_MASK        (0xFFU)
#define APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT       (0U)
#define APBH_CH8_SEMA_INCREMENT_SEMA(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH8_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH8_SEMA_PHORE_MASK                 (0xFF0000U)
#define APBH_CH8_SEMA_PHORE_SHIFT                (16U)
#define APBH_CH8_SEMA_PHORE(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_PHORE_SHIFT)) & APBH_CH8_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH8_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH8_DEBUG1_STATEMACHINE_MASK        (0x1FU)
#define APBH_CH8_DEBUG1_STATEMACHINE_SHIFT       (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH8_DEBUG1_STATEMACHINE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH8_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK        (0x100000U)
#define APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT       (20U)
#define APBH_CH8_DEBUG1_WR_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK       (0x200000U)
#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT      (21U)
#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK        (0x400000U)
#define APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT       (22U)
#define APBH_CH8_DEBUG1_RD_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK       (0x800000U)
#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT      (23U)
#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK    (0x1000000U)
#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT   (24U)
#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH8_DEBUG1_READY_MASK               (0x4000000U)
#define APBH_CH8_DEBUG1_READY_SHIFT              (26U)
#define APBH_CH8_DEBUG1_READY(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_READY_SHIFT)) & APBH_CH8_DEBUG1_READY_MASK)
#define APBH_CH8_DEBUG1_END_MASK                 (0x10000000U)
#define APBH_CH8_DEBUG1_END_SHIFT                (28U)
#define APBH_CH8_DEBUG1_END(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_END_SHIFT)) & APBH_CH8_DEBUG1_END_MASK)
#define APBH_CH8_DEBUG1_KICK_MASK                (0x20000000U)
#define APBH_CH8_DEBUG1_KICK_SHIFT               (29U)
#define APBH_CH8_DEBUG1_KICK(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_KICK_SHIFT)) & APBH_CH8_DEBUG1_KICK_MASK)
#define APBH_CH8_DEBUG1_BURST_MASK               (0x40000000U)
#define APBH_CH8_DEBUG1_BURST_SHIFT              (30U)
#define APBH_CH8_DEBUG1_BURST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_BURST_SHIFT)) & APBH_CH8_DEBUG1_BURST_MASK)
#define APBH_CH8_DEBUG1_REQ_MASK                 (0x80000000U)
#define APBH_CH8_DEBUG1_REQ_SHIFT                (31U)
#define APBH_CH8_DEBUG1_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_REQ_SHIFT)) & APBH_CH8_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH8_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH8_DEBUG2_AHB_BYTES_MASK           (0xFFFFU)
#define APBH_CH8_DEBUG2_AHB_BYTES_SHIFT          (0U)
#define APBH_CH8_DEBUG2_AHB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH8_DEBUG2_APB_BYTES_MASK           (0xFFFF0000U)
#define APBH_CH8_DEBUG2_APB_BYTES_SHIFT          (16U)
#define APBH_CH8_DEBUG2_APB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH9_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH9_CURCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH9_CURCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH9_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH9_NXTCMDAR_CMD_ADDR_MASK          (0xFFFFFFFFU)
#define APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT         (0U)
#define APBH_CH9_NXTCMDAR_CMD_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH9_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH9_CMD_COMMAND_MASK                (0x3U)
#define APBH_CH9_CMD_COMMAND_SHIFT               (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH9_CMD_COMMAND(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_COMMAND_SHIFT)) & APBH_CH9_CMD_COMMAND_MASK)
#define APBH_CH9_CMD_CHAIN_MASK                  (0x4U)
#define APBH_CH9_CMD_CHAIN_SHIFT                 (2U)
#define APBH_CH9_CMD_CHAIN(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CHAIN_SHIFT)) & APBH_CH9_CMD_CHAIN_MASK)
#define APBH_CH9_CMD_IRQONCMPLT_MASK             (0x8U)
#define APBH_CH9_CMD_IRQONCMPLT_SHIFT            (3U)
#define APBH_CH9_CMD_IRQONCMPLT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_IRQONCMPLT_SHIFT)) & APBH_CH9_CMD_IRQONCMPLT_MASK)
#define APBH_CH9_CMD_NANDLOCK_MASK               (0x10U)
#define APBH_CH9_CMD_NANDLOCK_SHIFT              (4U)
#define APBH_CH9_CMD_NANDLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDLOCK_SHIFT)) & APBH_CH9_CMD_NANDLOCK_MASK)
#define APBH_CH9_CMD_NANDWAIT4READY_MASK         (0x20U)
#define APBH_CH9_CMD_NANDWAIT4READY_SHIFT        (5U)
#define APBH_CH9_CMD_NANDWAIT4READY(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH9_CMD_NANDWAIT4READY_MASK)
#define APBH_CH9_CMD_SEMAPHORE_MASK              (0x40U)
#define APBH_CH9_CMD_SEMAPHORE_SHIFT             (6U)
#define APBH_CH9_CMD_SEMAPHORE(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_SEMAPHORE_SHIFT)) & APBH_CH9_CMD_SEMAPHORE_MASK)
#define APBH_CH9_CMD_WAIT4ENDCMD_MASK            (0x80U)
#define APBH_CH9_CMD_WAIT4ENDCMD_SHIFT           (7U)
#define APBH_CH9_CMD_WAIT4ENDCMD(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH9_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH9_CMD_HALTONTERMINATE_MASK        (0x100U)
#define APBH_CH9_CMD_HALTONTERMINATE_SHIFT       (8U)
#define APBH_CH9_CMD_HALTONTERMINATE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH9_CMD_HALTONTERMINATE_MASK)
#define APBH_CH9_CMD_CMDWORDS_MASK               (0xF000U)
#define APBH_CH9_CMD_CMDWORDS_SHIFT              (12U)
#define APBH_CH9_CMD_CMDWORDS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CMDWORDS_SHIFT)) & APBH_CH9_CMD_CMDWORDS_MASK)
#define APBH_CH9_CMD_XFER_COUNT_MASK             (0xFFFF0000U)
#define APBH_CH9_CMD_XFER_COUNT_SHIFT            (16U)
#define APBH_CH9_CMD_XFER_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_XFER_COUNT_SHIFT)) & APBH_CH9_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH9_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH9_BAR_ADDRESS_MASK                (0xFFFFFFFFU)
#define APBH_CH9_BAR_ADDRESS_SHIFT               (0U)
#define APBH_CH9_BAR_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH9_BAR_ADDRESS_SHIFT)) & APBH_CH9_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH9_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH9_SEMA_INCREMENT_SEMA_MASK        (0xFFU)
#define APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT       (0U)
#define APBH_CH9_SEMA_INCREMENT_SEMA(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH9_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH9_SEMA_PHORE_MASK                 (0xFF0000U)
#define APBH_CH9_SEMA_PHORE_SHIFT                (16U)
#define APBH_CH9_SEMA_PHORE(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_PHORE_SHIFT)) & APBH_CH9_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH9_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH9_DEBUG1_STATEMACHINE_MASK        (0x1FU)
#define APBH_CH9_DEBUG1_STATEMACHINE_SHIFT       (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH9_DEBUG1_STATEMACHINE(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH9_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK        (0x100000U)
#define APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT       (20U)
#define APBH_CH9_DEBUG1_WR_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK       (0x200000U)
#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT      (21U)
#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK        (0x400000U)
#define APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT       (22U)
#define APBH_CH9_DEBUG1_RD_FIFO_FULL(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK       (0x800000U)
#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT      (23U)
#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK    (0x1000000U)
#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT   (24U)
#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH9_DEBUG1_READY_MASK               (0x4000000U)
#define APBH_CH9_DEBUG1_READY_SHIFT              (26U)
#define APBH_CH9_DEBUG1_READY(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_READY_SHIFT)) & APBH_CH9_DEBUG1_READY_MASK)
#define APBH_CH9_DEBUG1_END_MASK                 (0x10000000U)
#define APBH_CH9_DEBUG1_END_SHIFT                (28U)
#define APBH_CH9_DEBUG1_END(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_END_SHIFT)) & APBH_CH9_DEBUG1_END_MASK)
#define APBH_CH9_DEBUG1_KICK_MASK                (0x20000000U)
#define APBH_CH9_DEBUG1_KICK_SHIFT               (29U)
#define APBH_CH9_DEBUG1_KICK(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_KICK_SHIFT)) & APBH_CH9_DEBUG1_KICK_MASK)
#define APBH_CH9_DEBUG1_BURST_MASK               (0x40000000U)
#define APBH_CH9_DEBUG1_BURST_SHIFT              (30U)
#define APBH_CH9_DEBUG1_BURST(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_BURST_SHIFT)) & APBH_CH9_DEBUG1_BURST_MASK)
#define APBH_CH9_DEBUG1_REQ_MASK                 (0x80000000U)
#define APBH_CH9_DEBUG1_REQ_SHIFT                (31U)
#define APBH_CH9_DEBUG1_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_REQ_SHIFT)) & APBH_CH9_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH9_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH9_DEBUG2_AHB_BYTES_MASK           (0xFFFFU)
#define APBH_CH9_DEBUG2_AHB_BYTES_SHIFT          (0U)
#define APBH_CH9_DEBUG2_AHB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH9_DEBUG2_APB_BYTES_MASK           (0xFFFF0000U)
#define APBH_CH9_DEBUG2_APB_BYTES_SHIFT          (16U)
#define APBH_CH9_DEBUG2_APB_BYTES(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH10_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH10_CURCMDAR_CMD_ADDR_MASK         (0xFFFFFFFFU)
#define APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT        (0U)
#define APBH_CH10_CURCMDAR_CMD_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH10_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH10_NXTCMDAR_CMD_ADDR_MASK         (0xFFFFFFFFU)
#define APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT        (0U)
#define APBH_CH10_NXTCMDAR_CMD_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH10_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH10_CMD_COMMAND_MASK               (0x3U)
#define APBH_CH10_CMD_COMMAND_SHIFT              (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH10_CMD_COMMAND(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_COMMAND_SHIFT)) & APBH_CH10_CMD_COMMAND_MASK)
#define APBH_CH10_CMD_CHAIN_MASK                 (0x4U)
#define APBH_CH10_CMD_CHAIN_SHIFT                (2U)
#define APBH_CH10_CMD_CHAIN(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CHAIN_SHIFT)) & APBH_CH10_CMD_CHAIN_MASK)
#define APBH_CH10_CMD_IRQONCMPLT_MASK            (0x8U)
#define APBH_CH10_CMD_IRQONCMPLT_SHIFT           (3U)
#define APBH_CH10_CMD_IRQONCMPLT(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_IRQONCMPLT_SHIFT)) & APBH_CH10_CMD_IRQONCMPLT_MASK)
#define APBH_CH10_CMD_NANDLOCK_MASK              (0x10U)
#define APBH_CH10_CMD_NANDLOCK_SHIFT             (4U)
#define APBH_CH10_CMD_NANDLOCK(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDLOCK_SHIFT)) & APBH_CH10_CMD_NANDLOCK_MASK)
#define APBH_CH10_CMD_NANDWAIT4READY_MASK        (0x20U)
#define APBH_CH10_CMD_NANDWAIT4READY_SHIFT       (5U)
#define APBH_CH10_CMD_NANDWAIT4READY(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH10_CMD_NANDWAIT4READY_MASK)
#define APBH_CH10_CMD_SEMAPHORE_MASK             (0x40U)
#define APBH_CH10_CMD_SEMAPHORE_SHIFT            (6U)
#define APBH_CH10_CMD_SEMAPHORE(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_SEMAPHORE_SHIFT)) & APBH_CH10_CMD_SEMAPHORE_MASK)
#define APBH_CH10_CMD_WAIT4ENDCMD_MASK           (0x80U)
#define APBH_CH10_CMD_WAIT4ENDCMD_SHIFT          (7U)
#define APBH_CH10_CMD_WAIT4ENDCMD(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH10_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH10_CMD_HALTONTERMINATE_MASK       (0x100U)
#define APBH_CH10_CMD_HALTONTERMINATE_SHIFT      (8U)
#define APBH_CH10_CMD_HALTONTERMINATE(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH10_CMD_HALTONTERMINATE_MASK)
#define APBH_CH10_CMD_CMDWORDS_MASK              (0xF000U)
#define APBH_CH10_CMD_CMDWORDS_SHIFT             (12U)
#define APBH_CH10_CMD_CMDWORDS(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CMDWORDS_SHIFT)) & APBH_CH10_CMD_CMDWORDS_MASK)
#define APBH_CH10_CMD_XFER_COUNT_MASK            (0xFFFF0000U)
#define APBH_CH10_CMD_XFER_COUNT_SHIFT           (16U)
#define APBH_CH10_CMD_XFER_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_XFER_COUNT_SHIFT)) & APBH_CH10_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH10_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH10_BAR_ADDRESS_MASK               (0xFFFFFFFFU)
#define APBH_CH10_BAR_ADDRESS_SHIFT              (0U)
#define APBH_CH10_BAR_ADDRESS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH10_BAR_ADDRESS_SHIFT)) & APBH_CH10_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH10_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH10_SEMA_INCREMENT_SEMA_MASK       (0xFFU)
#define APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT      (0U)
#define APBH_CH10_SEMA_INCREMENT_SEMA(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH10_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH10_SEMA_PHORE_MASK                (0xFF0000U)
#define APBH_CH10_SEMA_PHORE_SHIFT               (16U)
#define APBH_CH10_SEMA_PHORE(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_PHORE_SHIFT)) & APBH_CH10_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH10_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH10_DEBUG1_STATEMACHINE_MASK       (0x1FU)
#define APBH_CH10_DEBUG1_STATEMACHINE_SHIFT      (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH10_DEBUG1_STATEMACHINE(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH10_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK       (0x100000U)
#define APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT      (20U)
#define APBH_CH10_DEBUG1_WR_FIFO_FULL(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK      (0x200000U)
#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT     (21U)
#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK       (0x400000U)
#define APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT      (22U)
#define APBH_CH10_DEBUG1_RD_FIFO_FULL(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK      (0x800000U)
#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT     (23U)
#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK   (0x1000000U)
#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT  (24U)
#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID(x)     (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH10_DEBUG1_READY_MASK              (0x4000000U)
#define APBH_CH10_DEBUG1_READY_SHIFT             (26U)
#define APBH_CH10_DEBUG1_READY(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_READY_SHIFT)) & APBH_CH10_DEBUG1_READY_MASK)
#define APBH_CH10_DEBUG1_END_MASK                (0x10000000U)
#define APBH_CH10_DEBUG1_END_SHIFT               (28U)
#define APBH_CH10_DEBUG1_END(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_END_SHIFT)) & APBH_CH10_DEBUG1_END_MASK)
#define APBH_CH10_DEBUG1_KICK_MASK               (0x20000000U)
#define APBH_CH10_DEBUG1_KICK_SHIFT              (29U)
#define APBH_CH10_DEBUG1_KICK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_KICK_SHIFT)) & APBH_CH10_DEBUG1_KICK_MASK)
#define APBH_CH10_DEBUG1_BURST_MASK              (0x40000000U)
#define APBH_CH10_DEBUG1_BURST_SHIFT             (30U)
#define APBH_CH10_DEBUG1_BURST(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_BURST_SHIFT)) & APBH_CH10_DEBUG1_BURST_MASK)
#define APBH_CH10_DEBUG1_REQ_MASK                (0x80000000U)
#define APBH_CH10_DEBUG1_REQ_SHIFT               (31U)
#define APBH_CH10_DEBUG1_REQ(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_REQ_SHIFT)) & APBH_CH10_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH10_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH10_DEBUG2_AHB_BYTES_MASK          (0xFFFFU)
#define APBH_CH10_DEBUG2_AHB_BYTES_SHIFT         (0U)
#define APBH_CH10_DEBUG2_AHB_BYTES(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH10_DEBUG2_APB_BYTES_MASK          (0xFFFF0000U)
#define APBH_CH10_DEBUG2_APB_BYTES_SHIFT         (16U)
#define APBH_CH10_DEBUG2_APB_BYTES(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH11_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH11_CURCMDAR_CMD_ADDR_MASK         (0xFFFFFFFFU)
#define APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT        (0U)
#define APBH_CH11_CURCMDAR_CMD_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH11_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH11_NXTCMDAR_CMD_ADDR_MASK         (0xFFFFFFFFU)
#define APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT        (0U)
#define APBH_CH11_NXTCMDAR_CMD_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH11_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH11_CMD_COMMAND_MASK               (0x3U)
#define APBH_CH11_CMD_COMMAND_SHIFT              (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH11_CMD_COMMAND(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_COMMAND_SHIFT)) & APBH_CH11_CMD_COMMAND_MASK)
#define APBH_CH11_CMD_CHAIN_MASK                 (0x4U)
#define APBH_CH11_CMD_CHAIN_SHIFT                (2U)
#define APBH_CH11_CMD_CHAIN(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CHAIN_SHIFT)) & APBH_CH11_CMD_CHAIN_MASK)
#define APBH_CH11_CMD_IRQONCMPLT_MASK            (0x8U)
#define APBH_CH11_CMD_IRQONCMPLT_SHIFT           (3U)
#define APBH_CH11_CMD_IRQONCMPLT(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_IRQONCMPLT_SHIFT)) & APBH_CH11_CMD_IRQONCMPLT_MASK)
#define APBH_CH11_CMD_NANDLOCK_MASK              (0x10U)
#define APBH_CH11_CMD_NANDLOCK_SHIFT             (4U)
#define APBH_CH11_CMD_NANDLOCK(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDLOCK_SHIFT)) & APBH_CH11_CMD_NANDLOCK_MASK)
#define APBH_CH11_CMD_NANDWAIT4READY_MASK        (0x20U)
#define APBH_CH11_CMD_NANDWAIT4READY_SHIFT       (5U)
#define APBH_CH11_CMD_NANDWAIT4READY(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH11_CMD_NANDWAIT4READY_MASK)
#define APBH_CH11_CMD_SEMAPHORE_MASK             (0x40U)
#define APBH_CH11_CMD_SEMAPHORE_SHIFT            (6U)
#define APBH_CH11_CMD_SEMAPHORE(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_SEMAPHORE_SHIFT)) & APBH_CH11_CMD_SEMAPHORE_MASK)
#define APBH_CH11_CMD_WAIT4ENDCMD_MASK           (0x80U)
#define APBH_CH11_CMD_WAIT4ENDCMD_SHIFT          (7U)
#define APBH_CH11_CMD_WAIT4ENDCMD(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH11_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH11_CMD_HALTONTERMINATE_MASK       (0x100U)
#define APBH_CH11_CMD_HALTONTERMINATE_SHIFT      (8U)
#define APBH_CH11_CMD_HALTONTERMINATE(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH11_CMD_HALTONTERMINATE_MASK)
#define APBH_CH11_CMD_CMDWORDS_MASK              (0xF000U)
#define APBH_CH11_CMD_CMDWORDS_SHIFT             (12U)
#define APBH_CH11_CMD_CMDWORDS(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CMDWORDS_SHIFT)) & APBH_CH11_CMD_CMDWORDS_MASK)
#define APBH_CH11_CMD_XFER_COUNT_MASK            (0xFFFF0000U)
#define APBH_CH11_CMD_XFER_COUNT_SHIFT           (16U)
#define APBH_CH11_CMD_XFER_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_XFER_COUNT_SHIFT)) & APBH_CH11_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH11_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH11_BAR_ADDRESS_MASK               (0xFFFFFFFFU)
#define APBH_CH11_BAR_ADDRESS_SHIFT              (0U)
#define APBH_CH11_BAR_ADDRESS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH11_BAR_ADDRESS_SHIFT)) & APBH_CH11_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH11_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH11_SEMA_INCREMENT_SEMA_MASK       (0xFFU)
#define APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT      (0U)
#define APBH_CH11_SEMA_INCREMENT_SEMA(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH11_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH11_SEMA_PHORE_MASK                (0xFF0000U)
#define APBH_CH11_SEMA_PHORE_SHIFT               (16U)
#define APBH_CH11_SEMA_PHORE(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_PHORE_SHIFT)) & APBH_CH11_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH11_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH11_DEBUG1_STATEMACHINE_MASK       (0x1FU)
#define APBH_CH11_DEBUG1_STATEMACHINE_SHIFT      (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH11_DEBUG1_STATEMACHINE(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH11_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK       (0x100000U)
#define APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT      (20U)
#define APBH_CH11_DEBUG1_WR_FIFO_FULL(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK      (0x200000U)
#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT     (21U)
#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK       (0x400000U)
#define APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT      (22U)
#define APBH_CH11_DEBUG1_RD_FIFO_FULL(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK      (0x800000U)
#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT     (23U)
#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK   (0x1000000U)
#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT  (24U)
#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID(x)     (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH11_DEBUG1_READY_MASK              (0x4000000U)
#define APBH_CH11_DEBUG1_READY_SHIFT             (26U)
#define APBH_CH11_DEBUG1_READY(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_READY_SHIFT)) & APBH_CH11_DEBUG1_READY_MASK)
#define APBH_CH11_DEBUG1_END_MASK                (0x10000000U)
#define APBH_CH11_DEBUG1_END_SHIFT               (28U)
#define APBH_CH11_DEBUG1_END(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_END_SHIFT)) & APBH_CH11_DEBUG1_END_MASK)
#define APBH_CH11_DEBUG1_KICK_MASK               (0x20000000U)
#define APBH_CH11_DEBUG1_KICK_SHIFT              (29U)
#define APBH_CH11_DEBUG1_KICK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_KICK_SHIFT)) & APBH_CH11_DEBUG1_KICK_MASK)
#define APBH_CH11_DEBUG1_BURST_MASK              (0x40000000U)
#define APBH_CH11_DEBUG1_BURST_SHIFT             (30U)
#define APBH_CH11_DEBUG1_BURST(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_BURST_SHIFT)) & APBH_CH11_DEBUG1_BURST_MASK)
#define APBH_CH11_DEBUG1_REQ_MASK                (0x80000000U)
#define APBH_CH11_DEBUG1_REQ_SHIFT               (31U)
#define APBH_CH11_DEBUG1_REQ(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_REQ_SHIFT)) & APBH_CH11_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH11_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH11_DEBUG2_AHB_BYTES_MASK          (0xFFFFU)
#define APBH_CH11_DEBUG2_AHB_BYTES_SHIFT         (0U)
#define APBH_CH11_DEBUG2_AHB_BYTES(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH11_DEBUG2_APB_BYTES_MASK          (0xFFFF0000U)
#define APBH_CH11_DEBUG2_APB_BYTES_SHIFT         (16U)
#define APBH_CH11_DEBUG2_APB_BYTES(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH12_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH12_CURCMDAR_CMD_ADDR_MASK         (0xFFFFFFFFU)
#define APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT        (0U)
#define APBH_CH12_CURCMDAR_CMD_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH12_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH12_NXTCMDAR_CMD_ADDR_MASK         (0xFFFFFFFFU)
#define APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT        (0U)
#define APBH_CH12_NXTCMDAR_CMD_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH12_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH12_CMD_COMMAND_MASK               (0x3U)
#define APBH_CH12_CMD_COMMAND_SHIFT              (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH12_CMD_COMMAND(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_COMMAND_SHIFT)) & APBH_CH12_CMD_COMMAND_MASK)
#define APBH_CH12_CMD_CHAIN_MASK                 (0x4U)
#define APBH_CH12_CMD_CHAIN_SHIFT                (2U)
#define APBH_CH12_CMD_CHAIN(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CHAIN_SHIFT)) & APBH_CH12_CMD_CHAIN_MASK)
#define APBH_CH12_CMD_IRQONCMPLT_MASK            (0x8U)
#define APBH_CH12_CMD_IRQONCMPLT_SHIFT           (3U)
#define APBH_CH12_CMD_IRQONCMPLT(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_IRQONCMPLT_SHIFT)) & APBH_CH12_CMD_IRQONCMPLT_MASK)
#define APBH_CH12_CMD_NANDLOCK_MASK              (0x10U)
#define APBH_CH12_CMD_NANDLOCK_SHIFT             (4U)
#define APBH_CH12_CMD_NANDLOCK(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDLOCK_SHIFT)) & APBH_CH12_CMD_NANDLOCK_MASK)
#define APBH_CH12_CMD_NANDWAIT4READY_MASK        (0x20U)
#define APBH_CH12_CMD_NANDWAIT4READY_SHIFT       (5U)
#define APBH_CH12_CMD_NANDWAIT4READY(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH12_CMD_NANDWAIT4READY_MASK)
#define APBH_CH12_CMD_SEMAPHORE_MASK             (0x40U)
#define APBH_CH12_CMD_SEMAPHORE_SHIFT            (6U)
#define APBH_CH12_CMD_SEMAPHORE(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_SEMAPHORE_SHIFT)) & APBH_CH12_CMD_SEMAPHORE_MASK)
#define APBH_CH12_CMD_WAIT4ENDCMD_MASK           (0x80U)
#define APBH_CH12_CMD_WAIT4ENDCMD_SHIFT          (7U)
#define APBH_CH12_CMD_WAIT4ENDCMD(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH12_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH12_CMD_HALTONTERMINATE_MASK       (0x100U)
#define APBH_CH12_CMD_HALTONTERMINATE_SHIFT      (8U)
#define APBH_CH12_CMD_HALTONTERMINATE(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH12_CMD_HALTONTERMINATE_MASK)
#define APBH_CH12_CMD_CMDWORDS_MASK              (0xF000U)
#define APBH_CH12_CMD_CMDWORDS_SHIFT             (12U)
#define APBH_CH12_CMD_CMDWORDS(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CMDWORDS_SHIFT)) & APBH_CH12_CMD_CMDWORDS_MASK)
#define APBH_CH12_CMD_XFER_COUNT_MASK            (0xFFFF0000U)
#define APBH_CH12_CMD_XFER_COUNT_SHIFT           (16U)
#define APBH_CH12_CMD_XFER_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_XFER_COUNT_SHIFT)) & APBH_CH12_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH12_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH12_BAR_ADDRESS_MASK               (0xFFFFFFFFU)
#define APBH_CH12_BAR_ADDRESS_SHIFT              (0U)
#define APBH_CH12_BAR_ADDRESS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH12_BAR_ADDRESS_SHIFT)) & APBH_CH12_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH12_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH12_SEMA_INCREMENT_SEMA_MASK       (0xFFU)
#define APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT      (0U)
#define APBH_CH12_SEMA_INCREMENT_SEMA(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH12_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH12_SEMA_PHORE_MASK                (0xFF0000U)
#define APBH_CH12_SEMA_PHORE_SHIFT               (16U)
#define APBH_CH12_SEMA_PHORE(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_PHORE_SHIFT)) & APBH_CH12_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH12_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH12_DEBUG1_STATEMACHINE_MASK       (0x1FU)
#define APBH_CH12_DEBUG1_STATEMACHINE_SHIFT      (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH12_DEBUG1_STATEMACHINE(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH12_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK       (0x100000U)
#define APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT      (20U)
#define APBH_CH12_DEBUG1_WR_FIFO_FULL(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK      (0x200000U)
#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT     (21U)
#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK       (0x400000U)
#define APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT      (22U)
#define APBH_CH12_DEBUG1_RD_FIFO_FULL(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK      (0x800000U)
#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT     (23U)
#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK   (0x1000000U)
#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT  (24U)
#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID(x)     (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH12_DEBUG1_READY_MASK              (0x4000000U)
#define APBH_CH12_DEBUG1_READY_SHIFT             (26U)
#define APBH_CH12_DEBUG1_READY(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_READY_SHIFT)) & APBH_CH12_DEBUG1_READY_MASK)
#define APBH_CH12_DEBUG1_END_MASK                (0x10000000U)
#define APBH_CH12_DEBUG1_END_SHIFT               (28U)
#define APBH_CH12_DEBUG1_END(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_END_SHIFT)) & APBH_CH12_DEBUG1_END_MASK)
#define APBH_CH12_DEBUG1_KICK_MASK               (0x20000000U)
#define APBH_CH12_DEBUG1_KICK_SHIFT              (29U)
#define APBH_CH12_DEBUG1_KICK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_KICK_SHIFT)) & APBH_CH12_DEBUG1_KICK_MASK)
#define APBH_CH12_DEBUG1_BURST_MASK              (0x40000000U)
#define APBH_CH12_DEBUG1_BURST_SHIFT             (30U)
#define APBH_CH12_DEBUG1_BURST(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_BURST_SHIFT)) & APBH_CH12_DEBUG1_BURST_MASK)
#define APBH_CH12_DEBUG1_REQ_MASK                (0x80000000U)
#define APBH_CH12_DEBUG1_REQ_SHIFT               (31U)
#define APBH_CH12_DEBUG1_REQ(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_REQ_SHIFT)) & APBH_CH12_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH12_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH12_DEBUG2_AHB_BYTES_MASK          (0xFFFFU)
#define APBH_CH12_DEBUG2_AHB_BYTES_SHIFT         (0U)
#define APBH_CH12_DEBUG2_AHB_BYTES(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH12_DEBUG2_APB_BYTES_MASK          (0xFFFF0000U)
#define APBH_CH12_DEBUG2_APB_BYTES_SHIFT         (16U)
#define APBH_CH12_DEBUG2_APB_BYTES(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH13_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH13_CURCMDAR_CMD_ADDR_MASK         (0xFFFFFFFFU)
#define APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT        (0U)
#define APBH_CH13_CURCMDAR_CMD_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH13_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH13_NXTCMDAR_CMD_ADDR_MASK         (0xFFFFFFFFU)
#define APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT        (0U)
#define APBH_CH13_NXTCMDAR_CMD_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH13_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH13_CMD_COMMAND_MASK               (0x3U)
#define APBH_CH13_CMD_COMMAND_SHIFT              (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH13_CMD_COMMAND(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_COMMAND_SHIFT)) & APBH_CH13_CMD_COMMAND_MASK)
#define APBH_CH13_CMD_CHAIN_MASK                 (0x4U)
#define APBH_CH13_CMD_CHAIN_SHIFT                (2U)
#define APBH_CH13_CMD_CHAIN(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CHAIN_SHIFT)) & APBH_CH13_CMD_CHAIN_MASK)
#define APBH_CH13_CMD_IRQONCMPLT_MASK            (0x8U)
#define APBH_CH13_CMD_IRQONCMPLT_SHIFT           (3U)
#define APBH_CH13_CMD_IRQONCMPLT(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_IRQONCMPLT_SHIFT)) & APBH_CH13_CMD_IRQONCMPLT_MASK)
#define APBH_CH13_CMD_NANDLOCK_MASK              (0x10U)
#define APBH_CH13_CMD_NANDLOCK_SHIFT             (4U)
#define APBH_CH13_CMD_NANDLOCK(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDLOCK_SHIFT)) & APBH_CH13_CMD_NANDLOCK_MASK)
#define APBH_CH13_CMD_NANDWAIT4READY_MASK        (0x20U)
#define APBH_CH13_CMD_NANDWAIT4READY_SHIFT       (5U)
#define APBH_CH13_CMD_NANDWAIT4READY(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH13_CMD_NANDWAIT4READY_MASK)
#define APBH_CH13_CMD_SEMAPHORE_MASK             (0x40U)
#define APBH_CH13_CMD_SEMAPHORE_SHIFT            (6U)
#define APBH_CH13_CMD_SEMAPHORE(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_SEMAPHORE_SHIFT)) & APBH_CH13_CMD_SEMAPHORE_MASK)
#define APBH_CH13_CMD_WAIT4ENDCMD_MASK           (0x80U)
#define APBH_CH13_CMD_WAIT4ENDCMD_SHIFT          (7U)
#define APBH_CH13_CMD_WAIT4ENDCMD(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH13_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH13_CMD_HALTONTERMINATE_MASK       (0x100U)
#define APBH_CH13_CMD_HALTONTERMINATE_SHIFT      (8U)
#define APBH_CH13_CMD_HALTONTERMINATE(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH13_CMD_HALTONTERMINATE_MASK)
#define APBH_CH13_CMD_CMDWORDS_MASK              (0xF000U)
#define APBH_CH13_CMD_CMDWORDS_SHIFT             (12U)
#define APBH_CH13_CMD_CMDWORDS(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CMDWORDS_SHIFT)) & APBH_CH13_CMD_CMDWORDS_MASK)
#define APBH_CH13_CMD_XFER_COUNT_MASK            (0xFFFF0000U)
#define APBH_CH13_CMD_XFER_COUNT_SHIFT           (16U)
#define APBH_CH13_CMD_XFER_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_XFER_COUNT_SHIFT)) & APBH_CH13_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH13_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH13_BAR_ADDRESS_MASK               (0xFFFFFFFFU)
#define APBH_CH13_BAR_ADDRESS_SHIFT              (0U)
#define APBH_CH13_BAR_ADDRESS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH13_BAR_ADDRESS_SHIFT)) & APBH_CH13_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH13_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH13_SEMA_INCREMENT_SEMA_MASK       (0xFFU)
#define APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT      (0U)
#define APBH_CH13_SEMA_INCREMENT_SEMA(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH13_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH13_SEMA_PHORE_MASK                (0xFF0000U)
#define APBH_CH13_SEMA_PHORE_SHIFT               (16U)
#define APBH_CH13_SEMA_PHORE(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_PHORE_SHIFT)) & APBH_CH13_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH13_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH13_DEBUG1_STATEMACHINE_MASK       (0x1FU)
#define APBH_CH13_DEBUG1_STATEMACHINE_SHIFT      (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH13_DEBUG1_STATEMACHINE(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH13_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK       (0x100000U)
#define APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT      (20U)
#define APBH_CH13_DEBUG1_WR_FIFO_FULL(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK      (0x200000U)
#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT     (21U)
#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK       (0x400000U)
#define APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT      (22U)
#define APBH_CH13_DEBUG1_RD_FIFO_FULL(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK      (0x800000U)
#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT     (23U)
#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK   (0x1000000U)
#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT  (24U)
#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID(x)     (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH13_DEBUG1_READY_MASK              (0x4000000U)
#define APBH_CH13_DEBUG1_READY_SHIFT             (26U)
#define APBH_CH13_DEBUG1_READY(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_READY_SHIFT)) & APBH_CH13_DEBUG1_READY_MASK)
#define APBH_CH13_DEBUG1_END_MASK                (0x10000000U)
#define APBH_CH13_DEBUG1_END_SHIFT               (28U)
#define APBH_CH13_DEBUG1_END(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_END_SHIFT)) & APBH_CH13_DEBUG1_END_MASK)
#define APBH_CH13_DEBUG1_KICK_MASK               (0x20000000U)
#define APBH_CH13_DEBUG1_KICK_SHIFT              (29U)
#define APBH_CH13_DEBUG1_KICK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_KICK_SHIFT)) & APBH_CH13_DEBUG1_KICK_MASK)
#define APBH_CH13_DEBUG1_BURST_MASK              (0x40000000U)
#define APBH_CH13_DEBUG1_BURST_SHIFT             (30U)
#define APBH_CH13_DEBUG1_BURST(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_BURST_SHIFT)) & APBH_CH13_DEBUG1_BURST_MASK)
#define APBH_CH13_DEBUG1_REQ_MASK                (0x80000000U)
#define APBH_CH13_DEBUG1_REQ_SHIFT               (31U)
#define APBH_CH13_DEBUG1_REQ(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_REQ_SHIFT)) & APBH_CH13_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH13_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH13_DEBUG2_AHB_BYTES_MASK          (0xFFFFU)
#define APBH_CH13_DEBUG2_AHB_BYTES_SHIFT         (0U)
#define APBH_CH13_DEBUG2_AHB_BYTES(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH13_DEBUG2_APB_BYTES_MASK          (0xFFFF0000U)
#define APBH_CH13_DEBUG2_APB_BYTES_SHIFT         (16U)
#define APBH_CH13_DEBUG2_APB_BYTES(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH14_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH14_CURCMDAR_CMD_ADDR_MASK         (0xFFFFFFFFU)
#define APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT        (0U)
#define APBH_CH14_CURCMDAR_CMD_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH14_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH14_NXTCMDAR_CMD_ADDR_MASK         (0xFFFFFFFFU)
#define APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT        (0U)
#define APBH_CH14_NXTCMDAR_CMD_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH14_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH14_CMD_COMMAND_MASK               (0x3U)
#define APBH_CH14_CMD_COMMAND_SHIFT              (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH14_CMD_COMMAND(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_COMMAND_SHIFT)) & APBH_CH14_CMD_COMMAND_MASK)
#define APBH_CH14_CMD_CHAIN_MASK                 (0x4U)
#define APBH_CH14_CMD_CHAIN_SHIFT                (2U)
#define APBH_CH14_CMD_CHAIN(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CHAIN_SHIFT)) & APBH_CH14_CMD_CHAIN_MASK)
#define APBH_CH14_CMD_IRQONCMPLT_MASK            (0x8U)
#define APBH_CH14_CMD_IRQONCMPLT_SHIFT           (3U)
#define APBH_CH14_CMD_IRQONCMPLT(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_IRQONCMPLT_SHIFT)) & APBH_CH14_CMD_IRQONCMPLT_MASK)
#define APBH_CH14_CMD_NANDLOCK_MASK              (0x10U)
#define APBH_CH14_CMD_NANDLOCK_SHIFT             (4U)
#define APBH_CH14_CMD_NANDLOCK(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDLOCK_SHIFT)) & APBH_CH14_CMD_NANDLOCK_MASK)
#define APBH_CH14_CMD_NANDWAIT4READY_MASK        (0x20U)
#define APBH_CH14_CMD_NANDWAIT4READY_SHIFT       (5U)
#define APBH_CH14_CMD_NANDWAIT4READY(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH14_CMD_NANDWAIT4READY_MASK)
#define APBH_CH14_CMD_SEMAPHORE_MASK             (0x40U)
#define APBH_CH14_CMD_SEMAPHORE_SHIFT            (6U)
#define APBH_CH14_CMD_SEMAPHORE(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_SEMAPHORE_SHIFT)) & APBH_CH14_CMD_SEMAPHORE_MASK)
#define APBH_CH14_CMD_WAIT4ENDCMD_MASK           (0x80U)
#define APBH_CH14_CMD_WAIT4ENDCMD_SHIFT          (7U)
#define APBH_CH14_CMD_WAIT4ENDCMD(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH14_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH14_CMD_HALTONTERMINATE_MASK       (0x100U)
#define APBH_CH14_CMD_HALTONTERMINATE_SHIFT      (8U)
#define APBH_CH14_CMD_HALTONTERMINATE(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH14_CMD_HALTONTERMINATE_MASK)
#define APBH_CH14_CMD_CMDWORDS_MASK              (0xF000U)
#define APBH_CH14_CMD_CMDWORDS_SHIFT             (12U)
#define APBH_CH14_CMD_CMDWORDS(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CMDWORDS_SHIFT)) & APBH_CH14_CMD_CMDWORDS_MASK)
#define APBH_CH14_CMD_XFER_COUNT_MASK            (0xFFFF0000U)
#define APBH_CH14_CMD_XFER_COUNT_SHIFT           (16U)
#define APBH_CH14_CMD_XFER_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_XFER_COUNT_SHIFT)) & APBH_CH14_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH14_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH14_BAR_ADDRESS_MASK               (0xFFFFFFFFU)
#define APBH_CH14_BAR_ADDRESS_SHIFT              (0U)
#define APBH_CH14_BAR_ADDRESS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH14_BAR_ADDRESS_SHIFT)) & APBH_CH14_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH14_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH14_SEMA_INCREMENT_SEMA_MASK       (0xFFU)
#define APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT      (0U)
#define APBH_CH14_SEMA_INCREMENT_SEMA(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH14_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH14_SEMA_PHORE_MASK                (0xFF0000U)
#define APBH_CH14_SEMA_PHORE_SHIFT               (16U)
#define APBH_CH14_SEMA_PHORE(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_PHORE_SHIFT)) & APBH_CH14_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH14_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH14_DEBUG1_STATEMACHINE_MASK       (0x1FU)
#define APBH_CH14_DEBUG1_STATEMACHINE_SHIFT      (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH14_DEBUG1_STATEMACHINE(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH14_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK       (0x100000U)
#define APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT      (20U)
#define APBH_CH14_DEBUG1_WR_FIFO_FULL(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK      (0x200000U)
#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT     (21U)
#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK       (0x400000U)
#define APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT      (22U)
#define APBH_CH14_DEBUG1_RD_FIFO_FULL(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK      (0x800000U)
#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT     (23U)
#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK   (0x1000000U)
#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT  (24U)
#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID(x)     (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH14_DEBUG1_READY_MASK              (0x4000000U)
#define APBH_CH14_DEBUG1_READY_SHIFT             (26U)
#define APBH_CH14_DEBUG1_READY(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_READY_SHIFT)) & APBH_CH14_DEBUG1_READY_MASK)
#define APBH_CH14_DEBUG1_END_MASK                (0x10000000U)
#define APBH_CH14_DEBUG1_END_SHIFT               (28U)
#define APBH_CH14_DEBUG1_END(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_END_SHIFT)) & APBH_CH14_DEBUG1_END_MASK)
#define APBH_CH14_DEBUG1_KICK_MASK               (0x20000000U)
#define APBH_CH14_DEBUG1_KICK_SHIFT              (29U)
#define APBH_CH14_DEBUG1_KICK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_KICK_SHIFT)) & APBH_CH14_DEBUG1_KICK_MASK)
#define APBH_CH14_DEBUG1_BURST_MASK              (0x40000000U)
#define APBH_CH14_DEBUG1_BURST_SHIFT             (30U)
#define APBH_CH14_DEBUG1_BURST(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_BURST_SHIFT)) & APBH_CH14_DEBUG1_BURST_MASK)
#define APBH_CH14_DEBUG1_REQ_MASK                (0x80000000U)
#define APBH_CH14_DEBUG1_REQ_SHIFT               (31U)
#define APBH_CH14_DEBUG1_REQ(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_REQ_SHIFT)) & APBH_CH14_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH14_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH14_DEBUG2_AHB_BYTES_MASK          (0xFFFFU)
#define APBH_CH14_DEBUG2_AHB_BYTES_SHIFT         (0U)
#define APBH_CH14_DEBUG2_AHB_BYTES(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH14_DEBUG2_APB_BYTES_MASK          (0xFFFF0000U)
#define APBH_CH14_DEBUG2_APB_BYTES_SHIFT         (16U)
#define APBH_CH14_DEBUG2_APB_BYTES(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name CH15_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH15_CURCMDAR_CMD_ADDR_MASK         (0xFFFFFFFFU)
#define APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT        (0U)
#define APBH_CH15_CURCMDAR_CMD_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_CURCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH15_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH15_NXTCMDAR_CMD_ADDR_MASK         (0xFFFFFFFFU)
#define APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT        (0U)
#define APBH_CH15_NXTCMDAR_CMD_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */

/*! @name CH15_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH15_CMD_COMMAND_MASK               (0x3U)
#define APBH_CH15_CMD_COMMAND_SHIFT              (0U)
/*! COMMAND - COMMAND
 *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
 *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
 *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
 *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
 */
#define APBH_CH15_CMD_COMMAND(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_COMMAND_SHIFT)) & APBH_CH15_CMD_COMMAND_MASK)
#define APBH_CH15_CMD_CHAIN_MASK                 (0x4U)
#define APBH_CH15_CMD_CHAIN_SHIFT                (2U)
#define APBH_CH15_CMD_CHAIN(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CHAIN_SHIFT)) & APBH_CH15_CMD_CHAIN_MASK)
#define APBH_CH15_CMD_IRQONCMPLT_MASK            (0x8U)
#define APBH_CH15_CMD_IRQONCMPLT_SHIFT           (3U)
#define APBH_CH15_CMD_IRQONCMPLT(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_IRQONCMPLT_SHIFT)) & APBH_CH15_CMD_IRQONCMPLT_MASK)
#define APBH_CH15_CMD_NANDLOCK_MASK              (0x10U)
#define APBH_CH15_CMD_NANDLOCK_SHIFT             (4U)
#define APBH_CH15_CMD_NANDLOCK(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDLOCK_SHIFT)) & APBH_CH15_CMD_NANDLOCK_MASK)
#define APBH_CH15_CMD_NANDWAIT4READY_MASK        (0x20U)
#define APBH_CH15_CMD_NANDWAIT4READY_SHIFT       (5U)
#define APBH_CH15_CMD_NANDWAIT4READY(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH15_CMD_NANDWAIT4READY_MASK)
#define APBH_CH15_CMD_SEMAPHORE_MASK             (0x40U)
#define APBH_CH15_CMD_SEMAPHORE_SHIFT            (6U)
#define APBH_CH15_CMD_SEMAPHORE(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_SEMAPHORE_SHIFT)) & APBH_CH15_CMD_SEMAPHORE_MASK)
#define APBH_CH15_CMD_WAIT4ENDCMD_MASK           (0x80U)
#define APBH_CH15_CMD_WAIT4ENDCMD_SHIFT          (7U)
#define APBH_CH15_CMD_WAIT4ENDCMD(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH15_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH15_CMD_HALTONTERMINATE_MASK       (0x100U)
#define APBH_CH15_CMD_HALTONTERMINATE_SHIFT      (8U)
#define APBH_CH15_CMD_HALTONTERMINATE(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH15_CMD_HALTONTERMINATE_MASK)
#define APBH_CH15_CMD_CMDWORDS_MASK              (0xF000U)
#define APBH_CH15_CMD_CMDWORDS_SHIFT             (12U)
#define APBH_CH15_CMD_CMDWORDS(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CMDWORDS_SHIFT)) & APBH_CH15_CMD_CMDWORDS_MASK)
#define APBH_CH15_CMD_XFER_COUNT_MASK            (0xFFFF0000U)
#define APBH_CH15_CMD_XFER_COUNT_SHIFT           (16U)
#define APBH_CH15_CMD_XFER_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_XFER_COUNT_SHIFT)) & APBH_CH15_CMD_XFER_COUNT_MASK)
/*! @} */

/*! @name CH15_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH15_BAR_ADDRESS_MASK               (0xFFFFFFFFU)
#define APBH_CH15_BAR_ADDRESS_SHIFT              (0U)
#define APBH_CH15_BAR_ADDRESS(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH15_BAR_ADDRESS_SHIFT)) & APBH_CH15_BAR_ADDRESS_MASK)
/*! @} */

/*! @name CH15_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH15_SEMA_INCREMENT_SEMA_MASK       (0xFFU)
#define APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT      (0U)
#define APBH_CH15_SEMA_INCREMENT_SEMA(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH15_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH15_SEMA_PHORE_MASK                (0xFF0000U)
#define APBH_CH15_SEMA_PHORE_SHIFT               (16U)
#define APBH_CH15_SEMA_PHORE(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_PHORE_SHIFT)) & APBH_CH15_SEMA_PHORE_MASK)
/*! @} */

/*! @name CH15_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH15_DEBUG1_STATEMACHINE_MASK       (0x1FU)
#define APBH_CH15_DEBUG1_STATEMACHINE_SHIFT      (0U)
/*! STATEMACHINE - STATEMACHINE
 *  0b00000..This is the idle state of the DMA state machine.
 *  0b00001..State in which the DMA is waiting to receive the first word of a command.
 *  0b00010..State in which the DMA is waiting to receive the third word of a command.
 *  0b00011..State in which the DMA is waiting to receive the second word of a command.
 *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
 *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
 *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
 *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
 *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
 *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
 *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
 *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
 *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
 *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
 *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
 *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
 *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
 *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
 *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
 */
#define APBH_CH15_DEBUG1_STATEMACHINE(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH15_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK       (0x100000U)
#define APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT      (20U)
#define APBH_CH15_DEBUG1_WR_FIFO_FULL(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK      (0x200000U)
#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT     (21U)
#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK       (0x400000U)
#define APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT      (22U)
#define APBH_CH15_DEBUG1_RD_FIFO_FULL(x)         (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK      (0x800000U)
#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT     (23U)
#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK   (0x1000000U)
#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT  (24U)
#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID(x)     (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH15_DEBUG1_READY_MASK              (0x4000000U)
#define APBH_CH15_DEBUG1_READY_SHIFT             (26U)
#define APBH_CH15_DEBUG1_READY(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_READY_SHIFT)) & APBH_CH15_DEBUG1_READY_MASK)
#define APBH_CH15_DEBUG1_END_MASK                (0x10000000U)
#define APBH_CH15_DEBUG1_END_SHIFT               (28U)
#define APBH_CH15_DEBUG1_END(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_END_SHIFT)) & APBH_CH15_DEBUG1_END_MASK)
#define APBH_CH15_DEBUG1_KICK_MASK               (0x20000000U)
#define APBH_CH15_DEBUG1_KICK_SHIFT              (29U)
#define APBH_CH15_DEBUG1_KICK(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_KICK_SHIFT)) & APBH_CH15_DEBUG1_KICK_MASK)
#define APBH_CH15_DEBUG1_BURST_MASK              (0x40000000U)
#define APBH_CH15_DEBUG1_BURST_SHIFT             (30U)
#define APBH_CH15_DEBUG1_BURST(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_BURST_SHIFT)) & APBH_CH15_DEBUG1_BURST_MASK)
#define APBH_CH15_DEBUG1_REQ_MASK                (0x80000000U)
#define APBH_CH15_DEBUG1_REQ_SHIFT               (31U)
#define APBH_CH15_DEBUG1_REQ(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_REQ_SHIFT)) & APBH_CH15_DEBUG1_REQ_MASK)
/*! @} */

/*! @name CH15_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH15_DEBUG2_AHB_BYTES_MASK          (0xFFFFU)
#define APBH_CH15_DEBUG2_AHB_BYTES_SHIFT         (0U)
#define APBH_CH15_DEBUG2_AHB_BYTES(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH15_DEBUG2_APB_BYTES_MASK          (0xFFFF0000U)
#define APBH_CH15_DEBUG2_APB_BYTES_SHIFT         (16U)
#define APBH_CH15_DEBUG2_APB_BYTES(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_APB_BYTES_MASK)
/*! @} */

/*! @name VERSION - APBH Bridge Version Register */
/*! @{ */
#define APBH_VERSION_STEP_MASK                   (0xFFFFU)
#define APBH_VERSION_STEP_SHIFT                  (0U)
#define APBH_VERSION_STEP(x)                     (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
#define APBH_VERSION_MINOR_MASK                  (0xFF0000U)
#define APBH_VERSION_MINOR_SHIFT                 (16U)
#define APBH_VERSION_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
#define APBH_VERSION_MAJOR_MASK                  (0xFF000000U)
#define APBH_VERSION_MAJOR_SHIFT                 (24U)
#define APBH_VERSION_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group APBH_Register_Masks */


/* APBH - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__APBH base address */
#define CONNECTIVITY__APBH_BASE                  (0x5B810000u)
/** Peripheral CONNECTIVITY__APBH base pointer */
#define CONNECTIVITY__APBH                       ((APBH_Type *)CONNECTIVITY__APBH_BASE)
/** Array initializer of APBH peripheral base addresses */
#define APBH_BASE_ADDRS                          { CONNECTIVITY__APBH_BASE }
/** Array initializer of APBH peripheral base pointers */
#define APBH_BASE_PTRS                           { CONNECTIVITY__APBH }
/** Interrupt vectors for the APBH peripheral type */
#define APBH_IRQS                                { CONNECTIVITY_APBHDMA_IRQn }

/*!
 * @}
 */ /* end of group APBH_Peripheral_Access_Layer */
 
 
/* ----------------------------------------------------------------------------
   -- ASMC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ASMC_Peripheral_Access_Layer ASMC Peripheral Access Layer
 * @{
 */

/** ASMC - Register Layout Typedef */
typedef struct {
  __I  uint32_t SRS;                               /**< System Reset Status Register, offset: 0x0 */
       uint8_t RESERVED_0[4];
  __IO uint32_t PMPROT;                            /**< Power Mode Protection register, offset: 0x8 */
  __IO uint32_t PMCTRL;                            /**< Power Mode Control register, offset: 0xC */
  __IO uint32_t STOPCTRL;                          /**< Stop Control Register, offset: 0x10 */
  __I  uint32_t PMSTAT;                            /**< Power Mode Status register, offset: 0x14 */
} ASMC_Type;

/* ----------------------------------------------------------------------------
   -- ASMC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ASMC_Register_Masks ASMC Register Masks
 * @{
 */

/*! @name SRS - System Reset Status Register */
#define ASMC_SRS_WAKEUP_MASK                     (0x1U)
#define ASMC_SRS_WAKEUP_SHIFT                    (0U)
#define ASMC_SRS_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WAKEUP_SHIFT)) & ASMC_SRS_WAKEUP_MASK)
#define ASMC_SRS_WDOG1_MASK                      (0x20U)
#define ASMC_SRS_WDOG1_SHIFT                     (5U)
#define ASMC_SRS_WDOG1(x)                        (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WDOG1_SHIFT)) & ASMC_SRS_WDOG1_MASK)
#define ASMC_SRS_RES_MASK                        (0x40U)
#define ASMC_SRS_RES_SHIFT                       (6U)
#define ASMC_SRS_RES(x)                          (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_RES_SHIFT)) & ASMC_SRS_RES_MASK)
#define ASMC_SRS_POR_MASK                        (0x80U)
#define ASMC_SRS_POR_SHIFT                       (7U)
#define ASMC_SRS_POR(x)                          (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_POR_SHIFT)) & ASMC_SRS_POR_MASK)
#define ASMC_SRS_LOCKUP_MASK                     (0x200U)
#define ASMC_SRS_LOCKUP_SHIFT                    (9U)
#define ASMC_SRS_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_LOCKUP_SHIFT)) & ASMC_SRS_LOCKUP_MASK)
#define ASMC_SRS_SW_MASK                         (0x400U)
#define ASMC_SRS_SW_SHIFT                        (10U)
#define ASMC_SRS_SW(x)                           (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SW_SHIFT)) & ASMC_SRS_SW_MASK)
#define ASMC_SRS_SACKERR_MASK                    (0x1000U)
#define ASMC_SRS_SACKERR_SHIFT                   (12U)
#define ASMC_SRS_SACKERR(x)                      (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SACKERR_SHIFT)) & ASMC_SRS_SACKERR_MASK)

/*! @name PMPROT - Power Mode Protection register */
#define ASMC_PMPROT_AVLLS_MASK                   (0x2U)
#define ASMC_PMPROT_AVLLS_SHIFT                  (1U)
#define ASMC_PMPROT_AVLLS(x)                     (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLLS_SHIFT)) & ASMC_PMPROT_AVLLS_MASK)
#define ASMC_PMPROT_ALLS_MASK                    (0x8U)
#define ASMC_PMPROT_ALLS_SHIFT                   (3U)
#define ASMC_PMPROT_ALLS(x)                      (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_ALLS_SHIFT)) & ASMC_PMPROT_ALLS_MASK)
#define ASMC_PMPROT_AVLP_MASK                    (0x20U)
#define ASMC_PMPROT_AVLP_SHIFT                   (5U)
#define ASMC_PMPROT_AVLP(x)                      (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLP_SHIFT)) & ASMC_PMPROT_AVLP_MASK)

/*! @name PMCTRL - Power Mode Control register */
#define ASMC_PMCTRL_STOPM_MASK                   (0x7U)
#define ASMC_PMCTRL_STOPM_SHIFT                  (0U)
#define ASMC_PMCTRL_STOPM(x)                     (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_STOPM_SHIFT)) & ASMC_PMCTRL_STOPM_MASK)
#define ASMC_PMCTRL_RUNM_MASK                    (0x60U)
#define ASMC_PMCTRL_RUNM_SHIFT                   (5U)
#define ASMC_PMCTRL_RUNM(x)                      (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_RUNM_SHIFT)) & ASMC_PMCTRL_RUNM_MASK)

/*! @name STOPCTRL - Stop Control Register */
#define ASMC_STOPCTRL_PSTOPO_MASK                (0xC0U)
#define ASMC_STOPCTRL_PSTOPO_SHIFT               (6U)
#define ASMC_STOPCTRL_PSTOPO(x)                  (((uint32_t)(((uint32_t)(x)) << ASMC_STOPCTRL_PSTOPO_SHIFT)) & ASMC_STOPCTRL_PSTOPO_MASK)

/*! @name PMSTAT - Power Mode Status register */
#define ASMC_PMSTAT_PMSTAT_MASK                  (0xFFU)
#define ASMC_PMSTAT_PMSTAT_SHIFT                 (0U)
#define ASMC_PMSTAT_PMSTAT(x)                    (((uint32_t)(((uint32_t)(x)) << ASMC_PMSTAT_PMSTAT_SHIFT)) & ASMC_PMSTAT_PMSTAT_MASK)


/*!
 * @}
 */ /* end of group ASMC_Register_Masks */


/* ASMC - Peripheral instance base addresses */
/** Peripheral ASMC base address */
#define BBS_SIM_BASE                              (0x41410000)
/** Peripheral BBS_SIM base pointer */
#define BBS_SIM                                   ((ASMC_Type *)BBS_SIM_BASE)
/** Array initializer of BBS_SIM peripheral base addresses */
#define BBS_SIM_BASE_ADDRS                        {BBS_SIM_BASE}
/** Array initializer of BBS_SIM peripheral base pointers */
#define BBS_SIM_BASE_PTRS                         {BBS_SIM}

/*!
 * @}
 */ /* end of group ASMC_Peripheral_Access_Layer */
 

/* ----------------------------------------------------------------------------
   -- ASRC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
 * @{
 */

/** ASRC - Register Layout Typedef */
typedef struct {
  __IO uint32_t ASRCTR;                            /**< ASRC Control Register, offset: 0x0 */
  __IO uint32_t ASRIER;                            /**< ASRC Interrupt Enable Register, offset: 0x4 */
       uint8_t RESERVED_0[4];
  __IO uint32_t ASRCNCR;                           /**< ASRC Channel Number Configuration Register, offset: 0xC */
  __IO uint32_t ASRCFG;                            /**< ASRC Filter Configuration Status Register, offset: 0x10 */
  __IO uint32_t ASRCSR;                            /**< ASRC Clock Source Register, offset: 0x14 */
  __IO uint32_t ASRCDR1;                           /**< ASRC Clock Divider Register 1, offset: 0x18 */
  __IO uint32_t ASRCDR2;                           /**< ASRC Clock Divider Register 2, offset: 0x1C */
  __I  uint32_t ASRSTR;                            /**< ASRC Status Register, offset: 0x20 */
  union {                                          /* offset: 0x24 */
    __IO uint32_t ASRDCMD;                           /**< ASRC Debug Command Register, offset: 0x24 */
    __I  uint32_t ASRRA;                             /**< Ratio Register Part A, offset: 0x24 */
  };
  union {                                          /* offset: 0x28 */
    __IO uint32_t ASRDINSTH;                         /**< ASRC Debug Instruction Register High, offset: 0x28 */
    __I  uint32_t ASRRB;                             /**< Ratio Register Part B, offset: 0x28 */
  };
  union {                                          /* offset: 0x2C */
    __IO uint32_t ASRDINSTL;                         /**< ASRC Debug Instruction Register Low, offset: 0x2C */
    __I  uint32_t ASRRC;                             /**< Ratio Register Part C, offset: 0x2C */
  };
  __IO uint32_t ASRMAA;                            /**< ASRC Memory Access Address Register, offset: 0x30 */
  __IO uint32_t ASRMAD;                            /**< ASRC Memory Access Data Register, offset: 0x34 */
  __IO uint32_t ASRDCR;                            /**< ASRC Debug Control Register, offset: 0x38 */
  __IO uint32_t ASRDCR1;                           /**< ASRC Debug Control Register -1, offset: 0x3C */
  __IO uint32_t ASRPM[5];                          /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */
  __IO uint32_t ASRTFR1;                           /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */
  __I  uint32_t ASRTFR2;                           /**< ASRC Task queue FIFO Register 2, offset: 0x58 */
  __IO uint32_t ASRCCR;                            /**< ASRC Channel Counter Register, offset: 0x5C */
  __O  uint32_t ASRDIA;                            /**< ASRC Data Input Register for Pair x, offset: 0x60 */
  __I  uint32_t ASRDOA;                            /**< ASRC Data Output Register for Pair x, offset: 0x64 */
  __O  uint32_t ASRDIB;                            /**< ASRC Data Input Register for Pair x, offset: 0x68 */
  __I  uint32_t ASRDOB;                            /**< ASRC Data Output Register for Pair x, offset: 0x6C */
  __O  uint32_t ASRDIC;                            /**< ASRC Data Input Register for Pair x, offset: 0x70 */
  __I  uint32_t ASRDOC;                            /**< ASRC Data Output Register for Pair x, offset: 0x74 */
       uint8_t RESERVED_1[8];
  __IO uint32_t ASRIDRHA;                          /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
  __IO uint32_t ASRIDRLA;                          /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
  __IO uint32_t ASRIDRHB;                          /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
  __IO uint32_t ASRIDRLB;                          /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
  __IO uint32_t ASRIDRHC;                          /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
  __IO uint32_t ASRIDRLC;                          /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
  __IO uint32_t ASR76K;                            /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */
  __IO uint32_t ASR56K;                            /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */
  __IO uint32_t ASRMCRA;                           /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */
  __I  uint32_t ASRFSTA;                           /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */
  __IO uint32_t ASRMCRB;                           /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */
  __I  uint32_t ASRFSTB;                           /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */
  __IO uint32_t ASRMCRC;                           /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */
  __I  uint32_t ASRFSTC;                           /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */
       uint8_t RESERVED_2[8];
  __IO uint32_t ASRMCR1[3];                        /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */
} ASRC_Type;

/* ----------------------------------------------------------------------------
   -- ASRC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ASRC_Register_Masks ASRC Register Masks
 * @{
 */

/*! @name ASRCTR - ASRC Control Register */
/*! @{ */
#define ASRC_ASRCTR_ASRCEN_MASK                  (0x1U)
#define ASRC_ASRCTR_ASRCEN_SHIFT                 (0U)
#define ASRC_ASRCTR_ASRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK)
#define ASRC_ASRCTR_ASREA_MASK                   (0x2U)
#define ASRC_ASRCTR_ASREA_SHIFT                  (1U)
#define ASRC_ASRCTR_ASREA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK)
#define ASRC_ASRCTR_ASREB_MASK                   (0x4U)
#define ASRC_ASRCTR_ASREB_SHIFT                  (2U)
#define ASRC_ASRCTR_ASREB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK)
#define ASRC_ASRCTR_ASREC_MASK                   (0x8U)
#define ASRC_ASRCTR_ASREC_SHIFT                  (3U)
#define ASRC_ASRCTR_ASREC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK)
#define ASRC_ASRCTR_SRST_MASK                    (0x10U)
#define ASRC_ASRCTR_SRST_SHIFT                   (4U)
#define ASRC_ASRCTR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK)
#define ASRC_ASRCTR_WINDA_MASK                   (0x80U)
#define ASRC_ASRCTR_WINDA_SHIFT                  (7U)
#define ASRC_ASRCTR_WINDA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_WINDA_SHIFT)) & ASRC_ASRCTR_WINDA_MASK)
#define ASRC_ASRCTR_WINDB_MASK                   (0x100U)
#define ASRC_ASRCTR_WINDB_SHIFT                  (8U)
#define ASRC_ASRCTR_WINDB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_WINDB_SHIFT)) & ASRC_ASRCTR_WINDB_MASK)
#define ASRC_ASRCTR_WINDC_MASK                   (0x200U)
#define ASRC_ASRCTR_WINDC_SHIFT                  (9U)
#define ASRC_ASRCTR_WINDC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_WINDC_SHIFT)) & ASRC_ASRCTR_WINDC_MASK)
#define ASRC_ASRCTR_SHIRA_MASK                   (0x400U)
#define ASRC_ASRCTR_SHIRA_SHIFT                  (10U)
#define ASRC_ASRCTR_SHIRA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SHIRA_SHIFT)) & ASRC_ASRCTR_SHIRA_MASK)
#define ASRC_ASRCTR_SHIRB_MASK                   (0x800U)
#define ASRC_ASRCTR_SHIRB_SHIFT                  (11U)
#define ASRC_ASRCTR_SHIRB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SHIRB_SHIFT)) & ASRC_ASRCTR_SHIRB_MASK)
#define ASRC_ASRCTR_SHIRC_MASK                   (0x1000U)
#define ASRC_ASRCTR_SHIRC_SHIFT                  (12U)
#define ASRC_ASRCTR_SHIRC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SHIRC_SHIFT)) & ASRC_ASRCTR_SHIRC_MASK)
#define ASRC_ASRCTR_IDRA_MASK                    (0x2000U)
#define ASRC_ASRCTR_IDRA_SHIFT                   (13U)
#define ASRC_ASRCTR_IDRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK)
#define ASRC_ASRCTR_USRA_MASK                    (0x4000U)
#define ASRC_ASRCTR_USRA_SHIFT                   (14U)
#define ASRC_ASRCTR_USRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK)
#define ASRC_ASRCTR_IDRB_MASK                    (0x8000U)
#define ASRC_ASRCTR_IDRB_SHIFT                   (15U)
#define ASRC_ASRCTR_IDRB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK)
#define ASRC_ASRCTR_USRB_MASK                    (0x10000U)
#define ASRC_ASRCTR_USRB_SHIFT                   (16U)
#define ASRC_ASRCTR_USRB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK)
#define ASRC_ASRCTR_IDRC_MASK                    (0x20000U)
#define ASRC_ASRCTR_IDRC_SHIFT                   (17U)
#define ASRC_ASRCTR_IDRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK)
#define ASRC_ASRCTR_USRC_MASK                    (0x40000U)
#define ASRC_ASRCTR_USRC_SHIFT                   (18U)
#define ASRC_ASRCTR_USRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK)
#define ASRC_ASRCTR_SD1R0_MASK                   (0x80000U)
#define ASRC_ASRCTR_SD1R0_SHIFT                  (19U)
#define ASRC_ASRCTR_SD1R0(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SD1R0_SHIFT)) & ASRC_ASRCTR_SD1R0_MASK)
#define ASRC_ASRCTR_ATSA_MASK                    (0x100000U)
#define ASRC_ASRCTR_ATSA_SHIFT                   (20U)
#define ASRC_ASRCTR_ATSA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK)
#define ASRC_ASRCTR_ATSB_MASK                    (0x200000U)
#define ASRC_ASRCTR_ATSB_SHIFT                   (21U)
#define ASRC_ASRCTR_ATSB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK)
#define ASRC_ASRCTR_ATSC_MASK                    (0x400000U)
#define ASRC_ASRCTR_ATSC_SHIFT                   (22U)
#define ASRC_ASRCTR_ATSC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK)
#define ASRC_ASRCTR_ASDBG_MASK                   (0x800000U)
#define ASRC_ASRCTR_ASDBG_SHIFT                  (23U)
#define ASRC_ASRCTR_ASDBG(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASDBG_SHIFT)) & ASRC_ASRCTR_ASDBG_MASK)
/*! @} */

/*! @name ASRIER - ASRC Interrupt Enable Register */
/*! @{ */
#define ASRC_ASRIER_ADIEA_MASK                   (0x1U)
#define ASRC_ASRIER_ADIEA_SHIFT                  (0U)
/*! ADIEA - ADIEA
 *  0b1..interrupt enabled
 *  0b0..interrupt disabled
 */
#define ASRC_ASRIER_ADIEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK)
#define ASRC_ASRIER_ADIEB_MASK                   (0x2U)
#define ASRC_ASRIER_ADIEB_SHIFT                  (1U)
/*! ADIEB - ADIEB
 *  0b1..interrupt enabled
 *  0b0..interrupt disabled
 */
#define ASRC_ASRIER_ADIEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK)
#define ASRC_ASRIER_ADIEC_MASK                   (0x4U)
#define ASRC_ASRIER_ADIEC_SHIFT                  (2U)
/*! ADIEC - ADIEC
 *  0b1..interrupt enabled
 *  0b0..interrupt disabled
 */
#define ASRC_ASRIER_ADIEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK)
#define ASRC_ASRIER_ADOEA_MASK                   (0x8U)
#define ASRC_ASRIER_ADOEA_SHIFT                  (3U)
/*! ADOEA - ADOEA
 *  0b1..interrupt enabled
 *  0b0..interrupt disabled
 */
#define ASRC_ASRIER_ADOEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK)
#define ASRC_ASRIER_ADOEB_MASK                   (0x10U)
#define ASRC_ASRIER_ADOEB_SHIFT                  (4U)
/*! ADOEB - ADOEB
 *  0b1..interrupt enabled
 *  0b0..interrupt disabled
 */
#define ASRC_ASRIER_ADOEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK)
#define ASRC_ASRIER_ADOEC_MASK                   (0x20U)
#define ASRC_ASRIER_ADOEC_SHIFT                  (5U)
/*! ADOEC - ADOEC
 *  0b1..interrupt enabled
 *  0b0..interrupt disabled
 */
#define ASRC_ASRIER_ADOEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK)
#define ASRC_ASRIER_AOLIE_MASK                   (0x40U)
#define ASRC_ASRIER_AOLIE_SHIFT                  (6U)
/*! AOLIE - AOLIE
 *  0b1..interrupt enabled
 *  0b0..interrupt disabled
 */
#define ASRC_ASRIER_AOLIE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK)
#define ASRC_ASRIER_AFPWE_MASK                   (0x80U)
#define ASRC_ASRIER_AFPWE_SHIFT                  (7U)
/*! AFPWE - AFPWE
 *  0b1..interrupt enabled
 *  0b0..interrupt disabled
 */
#define ASRC_ASRIER_AFPWE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK)
/*! @} */

/*! @name ASRCNCR - ASRC Channel Number Configuration Register */
/*! @{ */
#define ASRC_ASRCNCR_ANCA_MASK                   (0xFU)
#define ASRC_ASRCNCR_ANCA_SHIFT                  (0U)
/*! ANCA - ANCA
 *  0b0000..0 channels in A (Pair A is disabled)
 *  0b0001..1 channel in A
 *  0b0010..2 channels in A
 *  0b0011..3 channels in A
 *  0b0100..4 channels in A
 *  0b0101..5 channels in A
 *  0b0110..6 channels in A
 *  0b0111..7 channels in A
 *  0b1000..8 channels in A
 *  0b1001..9 channels in A
 *  0b1010..10 channels in A
 *  0b1011-0b1111..Should not be used.
 */
#define ASRC_ASRCNCR_ANCA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK)
#define ASRC_ASRCNCR_ANCB_MASK                   (0xF0U)
#define ASRC_ASRCNCR_ANCB_SHIFT                  (4U)
/*! ANCB - ANCB
 *  0b0000..0 channels in B (Pair B is disabled)
 *  0b0001..1 channel in B
 *  0b0010..2 channels in B
 *  0b0011..3 channels in B
 *  0b0100..4 channels in B
 *  0b0101..5 channels in B
 *  0b0110..6 channels in B
 *  0b0111..7 channels in B
 *  0b1000..8 channels in B
 *  0b1001..9 channels in B
 *  0b1010..10 channels in B
 *  0b1011-0b1111..Should not be used.
 */
#define ASRC_ASRCNCR_ANCB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK)
#define ASRC_ASRCNCR_ANCC_MASK                   (0xF00U)
#define ASRC_ASRCNCR_ANCC_SHIFT                  (8U)
/*! ANCC - ANCC
 *  0b0000..0 channels in C (Pair C is disabled)
 *  0b0001..1 channel in C
 *  0b0010..2 channels in C
 *  0b0011..3 channels in C
 *  0b0100..4 channels in C
 *  0b0101..5 channels in C
 *  0b0110..6 channels in C
 *  0b0111..7 channels in C
 *  0b1000..8 channels in C
 *  0b1001..9 channels in C
 *  0b1010..10 channels in C
 *  0b1011-0b1111..Should not be used.
 */
#define ASRC_ASRCNCR_ANCC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK)
/*! @} */

/*! @name ASRCFG - ASRC Filter Configuration Status Register */
/*! @{ */
#define ASRC_ASRCFG_HFA_MASK                     (0x3U)
#define ASRC_ASRCFG_HFA_SHIFT                    (0U)
/*! HFA - HFA
 *  0b00..Select half-band pre-filter. This mode can have less MIPS but at the cost of about -50dB THD+N near Nyquist frequency (the range covers from 20/24*Nyquist frequency to the Nyquist frequency).
 *  0b01..Select a general type pre-filter with normalized bandwidth chosen as 0.468
 *  0b10..Select a general type pre-filter with normalized bandwidth chosen as 0.416
 *  0b11..Select a general type pre-filter with normalized bandwidth chosen as 0.292
 */
#define ASRC_ASRCFG_HFA(x)                       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_HFA_SHIFT)) & ASRC_ASRCFG_HFA_MASK)
#define ASRC_ASRCFG_HFB_MASK                     (0xCU)
#define ASRC_ASRCFG_HFB_SHIFT                    (2U)
/*! HFB - HFB
 *  0b00..Select half-band pre-filter. This mode can have less MIPS but at the cost of about -50dB THD+N near Nyquist frequency (the range covers from 20/24*Nyquist frequency to the Nyquist frequency).
 *  0b01..Select a general type pre-filter with normalized bandwidth chosen as 0.468
 *  0b10..Select a general type pre-filter with normalized bandwidth chosen as 0.416
 *  0b11..Select a general type pre-filter with normalized bandwidth chosen as 0.292
 */
#define ASRC_ASRCFG_HFB(x)                       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_HFB_SHIFT)) & ASRC_ASRCFG_HFB_MASK)
#define ASRC_ASRCFG_HFC_MASK                     (0x30U)
#define ASRC_ASRCFG_HFC_SHIFT                    (4U)
/*! HFC - HFC
 *  0b00..Select half-band pre-filter. This mode can have less MIPS but at the cost of about -50dB THD+N near Nyquist frequency (the range covers from 20/24*Nyquist frequency to the Nyquist frequency).
 *  0b01..Select a general type pre-filter with normalized bandwidth chosen as 0.468
 *  0b10..Select a general type pre-filter with normalized bandwidth chosen as 0.416
 *  0b11..Select a general type pre-filter with normalized bandwidth chosen as 0.292
 */
#define ASRC_ASRCFG_HFC(x)                       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_HFC_SHIFT)) & ASRC_ASRCFG_HFC_MASK)
#define ASRC_ASRCFG_PREMODA_MASK                 (0xC0U)
#define ASRC_ASRCFG_PREMODA_SHIFT                (6U)
#define ASRC_ASRCFG_PREMODA(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK)
#define ASRC_ASRCFG_POSTMODA_MASK                (0x300U)
#define ASRC_ASRCFG_POSTMODA_SHIFT               (8U)
#define ASRC_ASRCFG_POSTMODA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK)
#define ASRC_ASRCFG_PREMODB_MASK                 (0xC00U)
#define ASRC_ASRCFG_PREMODB_SHIFT                (10U)
#define ASRC_ASRCFG_PREMODB(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK)
#define ASRC_ASRCFG_POSTMODB_MASK                (0x3000U)
#define ASRC_ASRCFG_POSTMODB_SHIFT               (12U)
#define ASRC_ASRCFG_POSTMODB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK)
#define ASRC_ASRCFG_PREMODC_MASK                 (0xC000U)
#define ASRC_ASRCFG_PREMODC_SHIFT                (14U)
#define ASRC_ASRCFG_PREMODC(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK)
#define ASRC_ASRCFG_POSTMODC_MASK                (0x30000U)
#define ASRC_ASRCFG_POSTMODC_SHIFT               (16U)
/*! POSTMODC - POSTMODC
 *  0b00..Select Upsampling-by-2 as defined in Signal Processing Flow.
 *  0b01..Select Direct-Connection as defined in Signal Processing Flow.
 *  0b10..Select Downsampling-by-2 as defined in Signal Processing Flow.
 */
#define ASRC_ASRCFG_POSTMODC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK)
#define ASRC_ASRCFG_NDPRA_MASK                   (0x40000U)
#define ASRC_ASRCFG_NDPRA_SHIFT                  (18U)
/*! NDPRA - NDPRA
 *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
 *  0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
 */
#define ASRC_ASRCFG_NDPRA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK)
#define ASRC_ASRCFG_NDPRB_MASK                   (0x80000U)
#define ASRC_ASRCFG_NDPRB_SHIFT                  (19U)
/*! NDPRB - NDPRB
 *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
 *  0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
 */
#define ASRC_ASRCFG_NDPRB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK)
#define ASRC_ASRCFG_NDPRC_MASK                   (0x100000U)
#define ASRC_ASRCFG_NDPRC_SHIFT                  (20U)
/*! NDPRC - NDPRC
 *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
 *  0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
 */
#define ASRC_ASRCFG_NDPRC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK)
#define ASRC_ASRCFG_INIRQA_MASK                  (0x200000U)
#define ASRC_ASRCFG_INIRQA_SHIFT                 (21U)
#define ASRC_ASRCFG_INIRQA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK)
#define ASRC_ASRCFG_INIRQB_MASK                  (0x400000U)
#define ASRC_ASRCFG_INIRQB_SHIFT                 (22U)
#define ASRC_ASRCFG_INIRQB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK)
#define ASRC_ASRCFG_INIRQC_MASK                  (0x800000U)
#define ASRC_ASRCFG_INIRQC_SHIFT                 (23U)
#define ASRC_ASRCFG_INIRQC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK)
/*! @} */

/*! @name ASRCSR - ASRC Clock Source Register */
/*! @{ */
#define ASRC_ASRCSR_AICSA_MASK                   (0xFU)
#define ASRC_ASRCSR_AICSA_SHIFT                  (0U)
/*! AICSA - AICSA
 *  0b0000..bit clock 0
 *  0b0001..bit clock 1
 *  0b0010..bit clock 2
 *  0b0011..bit clock 3
 *  0b0100..bit clock 4
 *  0b0101..bit clock 5
 *  0b0110..bit clock 6
 *  0b0111..bit clock 7
 *  0b1000..bit clock 8
 *  0b1001..bit clock 9
 *  0b1010..bit clock A
 *  0b1011..bit clock B
 *  0b1100..bit clock C
 *  0b1101..bit clock D
 *  0b1110..bit clock E
 *  0b1111..clock disabled, connected to zero
 */
#define ASRC_ASRCSR_AICSA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK)
#define ASRC_ASRCSR_AICSB_MASK                   (0xF0U)
#define ASRC_ASRCSR_AICSB_SHIFT                  (4U)
/*! AICSB - AICSB
 *  0b0000..bit clock 0
 *  0b0001..bit clock 1
 *  0b0010..bit clock 2
 *  0b0011..bit clock 3
 *  0b0100..bit clock 4
 *  0b0101..bit clock 5
 *  0b0110..bit clock 6
 *  0b0111..bit clock 7
 *  0b1000..bit clock 8
 *  0b1001..bit clock 9
 *  0b1010..bit clock A
 *  0b1011..bit clock B
 *  0b1100..bit clock C
 *  0b1101..bit clock D
 *  0b1110..bit clock E
 *  0b1111..clock disabled, connected to zero
 */
#define ASRC_ASRCSR_AICSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK)
#define ASRC_ASRCSR_AICSC_MASK                   (0xF00U)
#define ASRC_ASRCSR_AICSC_SHIFT                  (8U)
/*! AICSC - AICSC
 *  0b0000..bit clock 0
 *  0b0001..bit clock 1
 *  0b0010..bit clock 2
 *  0b0011..bit clock 3
 *  0b0100..bit clock 4
 *  0b0101..bit clock 5
 *  0b0110..bit clock 6
 *  0b0111..bit clock 7
 *  0b1000..bit clock 8
 *  0b1001..bit clock 9
 *  0b1010..bit clock A
 *  0b1011..bit clock B
 *  0b1100..bit clock C
 *  0b1101..bit clock D
 *  0b1110..bit clock E
 *  0b1111..clock disabled, connected to zero
 */
#define ASRC_ASRCSR_AICSC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK)
#define ASRC_ASRCSR_AOCSA_MASK                   (0xF000U)
#define ASRC_ASRCSR_AOCSA_SHIFT                  (12U)
/*! AOCSA - AOCSA
 *  0b0000..bit clock 0
 *  0b0001..bit clock 1
 *  0b0010..bit clock 2
 *  0b0011..bit clock 3
 *  0b0100..bit clock 4
 *  0b0101..bit clock 5
 *  0b0110..bit clock 6
 *  0b0111..bit clock 7
 *  0b1000..bit clock 8
 *  0b1001..bit clock 9
 *  0b1010..bit clock A
 *  0b1011..bit clock B
 *  0b1100..bit clock C
 *  0b1101..bit clock D
 *  0b1110..bit clock E
 *  0b1111..clock disabled, connected to zero
 */
#define ASRC_ASRCSR_AOCSA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK)
#define ASRC_ASRCSR_AOCSB_MASK                   (0xF0000U)
#define ASRC_ASRCSR_AOCSB_SHIFT                  (16U)
/*! AOCSB - AOCSB
 *  0b0000..bit clock 0
 *  0b0001..bit clock 1
 *  0b0010..bit clock 2
 *  0b0011..bit clock 3
 *  0b0100..bit clock 4
 *  0b0101..bit clock 5
 *  0b0110..bit clock 6
 *  0b0111..bit clock 7
 *  0b1000..bit clock 8
 *  0b1001..bit clock 9
 *  0b1010..bit clock A
 *  0b1011..bit clock B
 *  0b1100..bit clock C
 *  0b1101..bit clock D
 *  0b1110..bit clock E
 *  0b1111..clock disabled, connected to zero
 */
#define ASRC_ASRCSR_AOCSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK)
#define ASRC_ASRCSR_AOCSC_MASK                   (0xF00000U)
#define ASRC_ASRCSR_AOCSC_SHIFT                  (20U)
/*! AOCSC - AOCSC
 *  0b0000..bit clock 0
 *  0b0001..bit clock 1
 *  0b0010..bit clock 2
 *  0b0011..bit clock 3
 *  0b0100..bit clock 4
 *  0b0101..bit clock 5
 *  0b0110..bit clock 6
 *  0b0111..bit clock 7
 *  0b1000..bit clock 8
 *  0b1001..bit clock 9
 *  0b1010..bit clock A
 *  0b1011..bit clock B
 *  0b1100..bit clock C
 *  0b1101..bit clock D
 *  0b1110..bit clock E
 *  0b1111..clock disabled, connected to zero
 */
#define ASRC_ASRCSR_AOCSC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK)
/*! @} */

/*! @name ASRCDR1 - ASRC Clock Divider Register 1 */
/*! @{ */
#define ASRC_ASRCDR1_AICPA_MASK                  (0x7U)
#define ASRC_ASRCDR1_AICPA_SHIFT                 (0U)
#define ASRC_ASRCDR1_AICPA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK)
#define ASRC_ASRCDR1_AICDA_MASK                  (0x38U)
#define ASRC_ASRCDR1_AICDA_SHIFT                 (3U)
#define ASRC_ASRCDR1_AICDA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK)
#define ASRC_ASRCDR1_AICPB_MASK                  (0x1C0U)
#define ASRC_ASRCDR1_AICPB_SHIFT                 (6U)
#define ASRC_ASRCDR1_AICPB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK)
#define ASRC_ASRCDR1_AICDB_MASK                  (0xE00U)
#define ASRC_ASRCDR1_AICDB_SHIFT                 (9U)
#define ASRC_ASRCDR1_AICDB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK)
#define ASRC_ASRCDR1_AOCPA_MASK                  (0x7000U)
#define ASRC_ASRCDR1_AOCPA_SHIFT                 (12U)
#define ASRC_ASRCDR1_AOCPA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK)
#define ASRC_ASRCDR1_AOCDA_MASK                  (0x38000U)
#define ASRC_ASRCDR1_AOCDA_SHIFT                 (15U)
#define ASRC_ASRCDR1_AOCDA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK)
#define ASRC_ASRCDR1_AOCPB_MASK                  (0x1C0000U)
#define ASRC_ASRCDR1_AOCPB_SHIFT                 (18U)
#define ASRC_ASRCDR1_AOCPB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK)
#define ASRC_ASRCDR1_AOCDB_MASK                  (0xE00000U)
#define ASRC_ASRCDR1_AOCDB_SHIFT                 (21U)
#define ASRC_ASRCDR1_AOCDB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK)
/*! @} */

/*! @name ASRCDR2 - ASRC Clock Divider Register 2 */
/*! @{ */
#define ASRC_ASRCDR2_AICPC_MASK                  (0x7U)
#define ASRC_ASRCDR2_AICPC_SHIFT                 (0U)
#define ASRC_ASRCDR2_AICPC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK)
#define ASRC_ASRCDR2_AICDC_MASK                  (0x38U)
#define ASRC_ASRCDR2_AICDC_SHIFT                 (3U)
#define ASRC_ASRCDR2_AICDC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK)
#define ASRC_ASRCDR2_AOCPC_MASK                  (0x1C0U)
#define ASRC_ASRCDR2_AOCPC_SHIFT                 (6U)
#define ASRC_ASRCDR2_AOCPC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK)
#define ASRC_ASRCDR2_AOCDC_MASK                  (0xE00U)
#define ASRC_ASRCDR2_AOCDC_SHIFT                 (9U)
#define ASRC_ASRCDR2_AOCDC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK)
/*! @} */

/*! @name ASRSTR - ASRC Status Register */
/*! @{ */
#define ASRC_ASRSTR_AIDEA_MASK                   (0x1U)
#define ASRC_ASRSTR_AIDEA_SHIFT                  (0U)
#define ASRC_ASRSTR_AIDEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK)
#define ASRC_ASRSTR_AIDEB_MASK                   (0x2U)
#define ASRC_ASRSTR_AIDEB_SHIFT                  (1U)
#define ASRC_ASRSTR_AIDEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK)
#define ASRC_ASRSTR_AIDEC_MASK                   (0x4U)
#define ASRC_ASRSTR_AIDEC_SHIFT                  (2U)
#define ASRC_ASRSTR_AIDEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK)
#define ASRC_ASRSTR_AODFA_MASK                   (0x8U)
#define ASRC_ASRSTR_AODFA_SHIFT                  (3U)
#define ASRC_ASRSTR_AODFA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK)
#define ASRC_ASRSTR_AODFB_MASK                   (0x10U)
#define ASRC_ASRSTR_AODFB_SHIFT                  (4U)
#define ASRC_ASRSTR_AODFB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK)
#define ASRC_ASRSTR_AODFC_MASK                   (0x20U)
#define ASRC_ASRSTR_AODFC_SHIFT                  (5U)
#define ASRC_ASRSTR_AODFC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK)
#define ASRC_ASRSTR_AOLE_MASK                    (0x40U)
#define ASRC_ASRSTR_AOLE_SHIFT                   (6U)
#define ASRC_ASRSTR_AOLE(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK)
#define ASRC_ASRSTR_FPWT_MASK                    (0x80U)
#define ASRC_ASRSTR_FPWT_SHIFT                   (7U)
#define ASRC_ASRSTR_FPWT(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK)
#define ASRC_ASRSTR_AIDUA_MASK                   (0x100U)
#define ASRC_ASRSTR_AIDUA_SHIFT                  (8U)
#define ASRC_ASRSTR_AIDUA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK)
#define ASRC_ASRSTR_AIDUB_MASK                   (0x200U)
#define ASRC_ASRSTR_AIDUB_SHIFT                  (9U)
#define ASRC_ASRSTR_AIDUB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK)
#define ASRC_ASRSTR_AIDUC_MASK                   (0x400U)
#define ASRC_ASRSTR_AIDUC_SHIFT                  (10U)
#define ASRC_ASRSTR_AIDUC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK)
#define ASRC_ASRSTR_AODOA_MASK                   (0x800U)
#define ASRC_ASRSTR_AODOA_SHIFT                  (11U)
#define ASRC_ASRSTR_AODOA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK)
#define ASRC_ASRSTR_AODOB_MASK                   (0x1000U)
#define ASRC_ASRSTR_AODOB_SHIFT                  (12U)
#define ASRC_ASRSTR_AODOB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK)
#define ASRC_ASRSTR_AODOC_MASK                   (0x2000U)
#define ASRC_ASRSTR_AODOC_SHIFT                  (13U)
#define ASRC_ASRSTR_AODOC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK)
#define ASRC_ASRSTR_AIOLA_MASK                   (0x4000U)
#define ASRC_ASRSTR_AIOLA_SHIFT                  (14U)
#define ASRC_ASRSTR_AIOLA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK)
#define ASRC_ASRSTR_AIOLB_MASK                   (0x8000U)
#define ASRC_ASRSTR_AIOLB_SHIFT                  (15U)
#define ASRC_ASRSTR_AIOLB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK)
#define ASRC_ASRSTR_AIOLC_MASK                   (0x10000U)
#define ASRC_ASRSTR_AIOLC_SHIFT                  (16U)
#define ASRC_ASRSTR_AIOLC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK)
#define ASRC_ASRSTR_AOOLA_MASK                   (0x20000U)
#define ASRC_ASRSTR_AOOLA_SHIFT                  (17U)
#define ASRC_ASRSTR_AOOLA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK)
#define ASRC_ASRSTR_AOOLB_MASK                   (0x40000U)
#define ASRC_ASRSTR_AOOLB_SHIFT                  (18U)
#define ASRC_ASRSTR_AOOLB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK)
#define ASRC_ASRSTR_AOOLC_MASK                   (0x80000U)
#define ASRC_ASRSTR_AOOLC_SHIFT                  (19U)
#define ASRC_ASRSTR_AOOLC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK)
#define ASRC_ASRSTR_ATQOL_MASK                   (0x100000U)
#define ASRC_ASRSTR_ATQOL_SHIFT                  (20U)
#define ASRC_ASRSTR_ATQOL(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK)
#define ASRC_ASRSTR_DSLCNT_MASK                  (0x200000U)
#define ASRC_ASRSTR_DSLCNT_SHIFT                 (21U)
#define ASRC_ASRSTR_DSLCNT(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK)
/*! @} */

/*! @name ASRDCMD - ASRC Debug Command Register */
/*! @{ */
#define ASRC_ASRDCMD_PMAB_OR_BKPTAB_MASK         (0x1FFU)
#define ASRC_ASRDCMD_PMAB_OR_BKPTAB_SHIFT        (0U)
#define ASRC_ASRDCMD_PMAB_OR_BKPTAB(x)           (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCMD_PMAB_OR_BKPTAB_SHIFT)) & ASRC_ASRDCMD_PMAB_OR_BKPTAB_MASK)
#define ASRC_ASRDCMD_BKPACT_MASK                 (0x40000U)
#define ASRC_ASRDCMD_BKPACT_SHIFT                (18U)
#define ASRC_ASRDCMD_BKPACT(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCMD_BKPACT_SHIFT)) & ASRC_ASRDCMD_BKPACT_MASK)
#define ASRC_ASRDCMD_DBGCMD_MASK                 (0x380000U)
#define ASRC_ASRDCMD_DBGCMD_SHIFT                (19U)
/*! DBGCMD - DBGCMD
 *  0b000..NOP. No debug operation.
 *  0b001..GO. This command changes the FP mode from interactive debug mode to normal execution mode. This command is only active when FP is in interactive debug mode.
 *  0b010..STEP. This command advances the FP mode one instruction further. This command is only active when FP is in interactive debug mode.
 *  0b011..SET_BREAKPOINT. Set the breakpoint.
 *  0b100..MANUAL INSTRUCTION. This command forces the FP to put the manual instruction into pipeline for execution in the next running cycle. This command is only active when FP is in interactive debug mode.
 *  0b101..FORCE_BREAKPOINT. Force the FP into the interactive debug mode.
 *  0b111..REMOVE_BREAKPOINT. Remove the breakpoint.
 */
#define ASRC_ASRDCMD_DBGCMD(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCMD_DBGCMD_SHIFT)) & ASRC_ASRDCMD_DBGCMD_MASK)
#define ASRC_ASRDCMD_SDCMD_MASK                  (0x400000U)
#define ASRC_ASRDCMD_SDCMD_SHIFT                 (22U)
#define ASRC_ASRDCMD_SDCMD(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCMD_SDCMD_SHIFT)) & ASRC_ASRDCMD_SDCMD_MASK)
#define ASRC_ASRDCMD_INTACT_MASK                 (0x800000U)
#define ASRC_ASRDCMD_INTACT_SHIFT                (23U)
#define ASRC_ASRDCMD_INTACT(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCMD_INTACT_SHIFT)) & ASRC_ASRDCMD_INTACT_MASK)
/*! @} */

/*! @name ASRRA - Ratio Register Part A */
/*! @{ */
#define ASRC_ASRRA_ASRRA_MASK                    (0xFFFFFFU)
#define ASRC_ASRRA_ASRRA_SHIFT                   (0U)
#define ASRC_ASRRA_ASRRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRRA_ASRRA_SHIFT)) & ASRC_ASRRA_ASRRA_MASK)
/*! @} */

/*! @name ASRDINSTH - ASRC Debug Instruction Register High */
/*! @{ */
#define ASRC_ASRDINSTH_ASRDINSTH_MASK            (0xFFFFFFU)
#define ASRC_ASRDINSTH_ASRDINSTH_SHIFT           (0U)
#define ASRC_ASRDINSTH_ASRDINSTH(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDINSTH_ASRDINSTH_SHIFT)) & ASRC_ASRDINSTH_ASRDINSTH_MASK)
/*! @} */

/*! @name ASRRB - Ratio Register Part B */
/*! @{ */
#define ASRC_ASRRB_ASRRC_H_MASK                  (0x3FU)
#define ASRC_ASRRB_ASRRC_H_SHIFT                 (0U)
#define ASRC_ASRRB_ASRRC_H(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRRB_ASRRC_H_SHIFT)) & ASRC_ASRRB_ASRRC_H_MASK)
#define ASRC_ASRRB_IPSFT_MASK                    (0x3F00U)
#define ASRC_ASRRB_IPSFT_SHIFT                   (8U)
#define ASRC_ASRRB_IPSFT(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRRB_IPSFT_SHIFT)) & ASRC_ASRRB_IPSFT_MASK)
#define ASRC_ASRRB_ASRRA_H_MASK                  (0x3F0000U)
#define ASRC_ASRRB_ASRRA_H_SHIFT                 (16U)
#define ASRC_ASRRB_ASRRA_H(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRRB_ASRRA_H_SHIFT)) & ASRC_ASRRB_ASRRA_H_MASK)
/*! @} */

/*! @name ASRDINSTL - ASRC Debug Instruction Register Low */
/*! @{ */
#define ASRC_ASRDINSTL_ASRDINSTL_MASK            (0xFFFFFFU)
#define ASRC_ASRDINSTL_ASRDINSTL_SHIFT           (0U)
#define ASRC_ASRDINSTL_ASRDINSTL(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDINSTL_ASRDINSTL_SHIFT)) & ASRC_ASRDINSTL_ASRDINSTL_MASK)
/*! @} */

/*! @name ASRRC - Ratio Register Part C */
/*! @{ */
#define ASRC_ASRRC_ASRRC_MASK                    (0xFFFFFFU)
#define ASRC_ASRRC_ASRRC_SHIFT                   (0U)
#define ASRC_ASRRC_ASRRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRRC_ASRRC_SHIFT)) & ASRC_ASRRC_ASRRC_MASK)
/*! @} */

/*! @name ASRMAA - ASRC Memory Access Address Register */
/*! @{ */
#define ASRC_ASRMAA_ADDR_MASK                    (0x1FFFU)
#define ASRC_ASRMAA_ADDR_SHIFT                   (0U)
#define ASRC_ASRMAA_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMAA_ADDR_SHIFT)) & ASRC_ASRMAA_ADDR_MASK)
#define ASRC_ASRMAA_MEMOPT_MASK                  (0xC00000U)
#define ASRC_ASRMAA_MEMOPT_SHIFT                 (22U)
#define ASRC_ASRMAA_MEMOPT(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMAA_MEMOPT_SHIFT)) & ASRC_ASRMAA_MEMOPT_MASK)
/*! @} */

/*! @name ASRMAD - ASRC Memory Access Data Register */
/*! @{ */
#define ASRC_ASRMAD_DATA_MASK                    (0xFFFFFFU)
#define ASRC_ASRMAD_DATA_SHIFT                   (0U)
#define ASRC_ASRMAD_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMAD_DATA_SHIFT)) & ASRC_ASRMAD_DATA_MASK)
/*! @} */

/*! @name ASRDCR - ASRC Debug Control Register */
/*! @{ */
#define ASRC_ASRDCR_DSL_TKO_H_MASK               (0x3FU)
#define ASRC_ASRDCR_DSL_TKO_H_SHIFT              (0U)
#define ASRC_ASRDCR_DSL_TKO_H(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_DSL_TKO_H_SHIFT)) & ASRC_ASRDCR_DSL_TKO_H_MASK)
#define ASRC_ASRDCR_OUTCLK_MASK                  (0x100U)
#define ASRC_ASRDCR_OUTCLK_SHIFT                 (8U)
#define ASRC_ASRDCR_OUTCLK(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_OUTCLK_SHIFT)) & ASRC_ASRDCR_OUTCLK_MASK)
#define ASRC_ASRDCR_INCLK_MASK                   (0x200U)
#define ASRC_ASRDCR_INCLK_SHIFT                  (9U)
#define ASRC_ASRDCR_INCLK(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_INCLK_SHIFT)) & ASRC_ASRDCR_INCLK_MASK)
#define ASRC_ASRDCR_CPAIR_MASK                   (0xC00U)
#define ASRC_ASRDCR_CPAIR_SHIFT                  (10U)
#define ASRC_ASRDCR_CPAIR(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_CPAIR_SHIFT)) & ASRC_ASRDCR_CPAIR_MASK)
#define ASRC_ASRDCR_PFWPT_MASK                   (0x1F000U)
#define ASRC_ASRDCR_PFWPT_SHIFT                  (12U)
#define ASRC_ASRDCR_PFWPT(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_PFWPT_SHIFT)) & ASRC_ASRDCR_PFWPT_MASK)
#define ASRC_ASRDCR_TSKQE_MASK                   (0x20000U)
#define ASRC_ASRDCR_TSKQE_SHIFT                  (17U)
#define ASRC_ASRDCR_TSKQE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_TSKQE_SHIFT)) & ASRC_ASRDCR_TSKQE_MASK)
#define ASRC_ASRDCR_SFFOA_MASK                   (0x40000U)
#define ASRC_ASRDCR_SFFOA_SHIFT                  (18U)
#define ASRC_ASRDCR_SFFOA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_SFFOA_SHIFT)) & ASRC_ASRDCR_SFFOA_MASK)
#define ASRC_ASRDCR_SFFOB_MASK                   (0x80000U)
#define ASRC_ASRDCR_SFFOB_SHIFT                  (19U)
#define ASRC_ASRDCR_SFFOB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_SFFOB_SHIFT)) & ASRC_ASRDCR_SFFOB_MASK)
#define ASRC_ASRDCR_SFFOC_MASK                   (0x100000U)
#define ASRC_ASRDCR_SFFOC_SHIFT                  (20U)
#define ASRC_ASRDCR_SFFOC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_SFFOC_SHIFT)) & ASRC_ASRDCR_SFFOC_MASK)
#define ASRC_ASRDCR_CNTCLRA_MASK                 (0x200000U)
#define ASRC_ASRDCR_CNTCLRA_SHIFT                (21U)
#define ASRC_ASRDCR_CNTCLRA(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_CNTCLRA_SHIFT)) & ASRC_ASRDCR_CNTCLRA_MASK)
#define ASRC_ASRDCR_CNTCLRB_MASK                 (0x400000U)
#define ASRC_ASRDCR_CNTCLRB_SHIFT                (22U)
#define ASRC_ASRDCR_CNTCLRB(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_CNTCLRB_SHIFT)) & ASRC_ASRDCR_CNTCLRB_MASK)
#define ASRC_ASRDCR_CNTCLRC_MASK                 (0x800000U)
#define ASRC_ASRDCR_CNTCLRC_SHIFT                (23U)
#define ASRC_ASRDCR_CNTCLRC(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR_CNTCLRC_SHIFT)) & ASRC_ASRDCR_CNTCLRC_MASK)
/*! @} */

/*! @name ASRDCR1 - ASRC Debug Control Register -1 */
/*! @{ */
#define ASRC_ASRDCR1_DSL_TKO_L_MASK              (0xFFFFFFU)
#define ASRC_ASRDCR1_DSL_TKO_L_SHIFT             (0U)
#define ASRC_ASRDCR1_DSL_TKO_L(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDCR1_DSL_TKO_L_SHIFT)) & ASRC_ASRDCR1_DSL_TKO_L_MASK)
/*! @} */

/*! @name ASRPM - ASRC Parameter Register n */
/*! @{ */
#define ASRC_ASRPM_PARAMETER_VALUE_MASK          (0xFFFFFFU)
#define ASRC_ASRPM_PARAMETER_VALUE_SHIFT         (0U)
#define ASRC_ASRPM_PARAMETER_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK)
/*! @} */

/* The count of ASRC_ASRPM */
#define ASRC_ASRPM_COUNT                         (5U)

/*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */
/*! @{ */
#define ASRC_ASRTFR1_TF_BASE_MASK                (0x1FC0U)
#define ASRC_ASRTFR1_TF_BASE_SHIFT               (6U)
#define ASRC_ASRTFR1_TF_BASE(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK)
#define ASRC_ASRTFR1_TF_FILL_MASK                (0xFE000U)
#define ASRC_ASRTFR1_TF_FILL_SHIFT               (13U)
#define ASRC_ASRTFR1_TF_FILL(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK)
/*! @} */

/*! @name ASRTFR2 - ASRC Task queue FIFO Register 2 */
/*! @{ */
#define ASRC_ASRTFR2_TF_WR_PTR_MASK              (0x3FU)
#define ASRC_ASRTFR2_TF_WR_PTR_SHIFT             (0U)
#define ASRC_ASRTFR2_TF_WR_PTR(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR2_TF_WR_PTR_SHIFT)) & ASRC_ASRTFR2_TF_WR_PTR_MASK)
#define ASRC_ASRTFR2_TF_RD_PTR_MASK              (0xFC0U)
#define ASRC_ASRTFR2_TF_RD_PTR_SHIFT             (6U)
#define ASRC_ASRTFR2_TF_RD_PTR(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR2_TF_RD_PTR_SHIFT)) & ASRC_ASRTFR2_TF_RD_PTR_MASK)
#define ASRC_ASRTFR2_DSLA_FIFO_PT_MASK           (0xF000U)
#define ASRC_ASRTFR2_DSLA_FIFO_PT_SHIFT          (12U)
#define ASRC_ASRTFR2_DSLA_FIFO_PT(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR2_DSLA_FIFO_PT_SHIFT)) & ASRC_ASRTFR2_DSLA_FIFO_PT_MASK)
#define ASRC_ASRTFR2_DSLB_FIFO_PT_MASK           (0xF0000U)
#define ASRC_ASRTFR2_DSLB_FIFO_PT_SHIFT          (16U)
#define ASRC_ASRTFR2_DSLB_FIFO_PT(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR2_DSLB_FIFO_PT_SHIFT)) & ASRC_ASRTFR2_DSLB_FIFO_PT_MASK)
#define ASRC_ASRTFR2_DSLC_FIFO_PT_MASK           (0xF00000U)
#define ASRC_ASRTFR2_DSLC_FIFO_PT_SHIFT          (20U)
#define ASRC_ASRTFR2_DSLC_FIFO_PT(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR2_DSLC_FIFO_PT_SHIFT)) & ASRC_ASRTFR2_DSLC_FIFO_PT_MASK)
/*! @} */

/*! @name ASRCCR - ASRC Channel Counter Register */
/*! @{ */
#define ASRC_ASRCCR_ACIA_MASK                    (0xFU)
#define ASRC_ASRCCR_ACIA_SHIFT                   (0U)
#define ASRC_ASRCCR_ACIA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK)
#define ASRC_ASRCCR_ACIB_MASK                    (0xF0U)
#define ASRC_ASRCCR_ACIB_SHIFT                   (4U)
#define ASRC_ASRCCR_ACIB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK)
#define ASRC_ASRCCR_ACIC_MASK                    (0xF00U)
#define ASRC_ASRCCR_ACIC_SHIFT                   (8U)
#define ASRC_ASRCCR_ACIC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK)
#define ASRC_ASRCCR_ACOA_MASK                    (0xF000U)
#define ASRC_ASRCCR_ACOA_SHIFT                   (12U)
#define ASRC_ASRCCR_ACOA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK)
#define ASRC_ASRCCR_ACOB_MASK                    (0xF0000U)
#define ASRC_ASRCCR_ACOB_SHIFT                   (16U)
#define ASRC_ASRCCR_ACOB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK)
#define ASRC_ASRCCR_ACOC_MASK                    (0xF00000U)
#define ASRC_ASRCCR_ACOC_SHIFT                   (20U)
#define ASRC_ASRCCR_ACOC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK)
/*! @} */

/*! @name ASRDIA - ASRC Data Input Register for Pair x */
/*! @{ */
#define ASRC_ASRDIA_DATA_MASK                    (0xFFFFFFU)
#define ASRC_ASRDIA_DATA_SHIFT                   (0U)
#define ASRC_ASRDIA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK)
/*! @} */

/*! @name ASRDOA - ASRC Data Output Register for Pair x */
/*! @{ */
#define ASRC_ASRDOA_DATA_MASK                    (0xFFFFFFU)
#define ASRC_ASRDOA_DATA_SHIFT                   (0U)
#define ASRC_ASRDOA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK)
/*! @} */

/*! @name ASRDIB - ASRC Data Input Register for Pair x */
/*! @{ */
#define ASRC_ASRDIB_DATA_MASK                    (0xFFFFFFU)
#define ASRC_ASRDIB_DATA_SHIFT                   (0U)
#define ASRC_ASRDIB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK)
/*! @} */

/*! @name ASRDOB - ASRC Data Output Register for Pair x */
/*! @{ */
#define ASRC_ASRDOB_DATA_MASK                    (0xFFFFFFU)
#define ASRC_ASRDOB_DATA_SHIFT                   (0U)
#define ASRC_ASRDOB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK)
/*! @} */

/*! @name ASRDIC - ASRC Data Input Register for Pair x */
/*! @{ */
#define ASRC_ASRDIC_DATA_MASK                    (0xFFFFFFU)
#define ASRC_ASRDIC_DATA_SHIFT                   (0U)
#define ASRC_ASRDIC_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK)
/*! @} */

/*! @name ASRDOC - ASRC Data Output Register for Pair x */
/*! @{ */
#define ASRC_ASRDOC_DATA_MASK                    (0xFFFFFFU)
#define ASRC_ASRDOC_DATA_SHIFT                   (0U)
#define ASRC_ASRDOC_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK)
/*! @} */

/*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */
/*! @{ */
#define ASRC_ASRIDRHA_IDRATIOA_H_MASK            (0xFFU)
#define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT           (0U)
#define ASRC_ASRIDRHA_IDRATIOA_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK)
/*! @} */

/*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */
/*! @{ */
#define ASRC_ASRIDRLA_IDRATIOA_L_MASK            (0xFFFFFFU)
#define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT           (0U)
#define ASRC_ASRIDRLA_IDRATIOA_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK)
/*! @} */

/*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */
/*! @{ */
#define ASRC_ASRIDRHB_IDRATIOB_H_MASK            (0xFFU)
#define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT           (0U)
#define ASRC_ASRIDRHB_IDRATIOB_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK)
/*! @} */

/*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */
/*! @{ */
#define ASRC_ASRIDRLB_IDRATIOB_L_MASK            (0xFFFFFFU)
#define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT           (0U)
#define ASRC_ASRIDRLB_IDRATIOB_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK)
/*! @} */

/*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */
/*! @{ */
#define ASRC_ASRIDRHC_IDRATIOC_H_MASK            (0xFFU)
#define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT           (0U)
#define ASRC_ASRIDRHC_IDRATIOC_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK)
/*! @} */

/*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */
/*! @{ */
#define ASRC_ASRIDRLC_IDRATIOC_L_MASK            (0xFFFFFFU)
#define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT           (0U)
#define ASRC_ASRIDRLC_IDRATIOC_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK)
/*! @} */

/*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */
/*! @{ */
#define ASRC_ASR76K_ASR76K_MASK                  (0x1FFFFU)
#define ASRC_ASR76K_ASR76K_SHIFT                 (0U)
#define ASRC_ASR76K_ASR76K(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK)
/*! @} */

/*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */
/*! @{ */
#define ASRC_ASR56K_ASR56K_MASK                  (0x1FFFFU)
#define ASRC_ASR56K_ASR56K_SHIFT                 (0U)
#define ASRC_ASR56K_ASR56K(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK)
/*! @} */

/*! @name ASRMCRA - ASRC Misc Control Register for Pair A */
/*! @{ */
#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK      (0x3FU)
#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT     (0U)
#define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
#define ASRC_ASRMCRA_RSYNOFA_MASK                (0x400U)
#define ASRC_ASRMCRA_RSYNOFA_SHIFT               (10U)
#define ASRC_ASRMCRA_RSYNOFA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK)
#define ASRC_ASRMCRA_RSYNIFA_MASK                (0x800U)
#define ASRC_ASRMCRA_RSYNIFA_SHIFT               (11U)
#define ASRC_ASRMCRA_RSYNIFA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK)
#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK     (0x3F000U)
#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT    (12U)
#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
#define ASRC_ASRMCRA_BYPASSPOLYA_MASK            (0x100000U)
#define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT           (20U)
/*! BYPASSPOLYA - BYPASSPOLYA
 *  0b1..Bypass polyphase filtering.
 *  0b0..Don't bypass polyphase filtering.
 */
#define ASRC_ASRMCRA_BYPASSPOLYA(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK)
#define ASRC_ASRMCRA_BUFSTALLA_MASK              (0x200000U)
#define ASRC_ASRMCRA_BUFSTALLA_SHIFT             (21U)
/*! BUFSTALLA - BUFSTALLA
 *  0b1..Stall Pair A conversion in case of near empty/full FIFO conditions.
 *  0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
 */
#define ASRC_ASRMCRA_BUFSTALLA(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK)
#define ASRC_ASRMCRA_EXTTHRSHA_MASK              (0x400000U)
#define ASRC_ASRMCRA_EXTTHRSHA_SHIFT             (22U)
/*! EXTTHRSHA - EXTTHRSHA
 *  0b1..Use external defined thresholds.
 *  0b0..Use default thresholds.
 */
#define ASRC_ASRMCRA_EXTTHRSHA(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK)
#define ASRC_ASRMCRA_ZEROBUFA_MASK               (0x800000U)
#define ASRC_ASRMCRA_ZEROBUFA_SHIFT              (23U)
/*! ZEROBUFA - ZEROBUFA
 *  0b1..Don't zeroize the buffer
 *  0b0..Zeroize the buffer
 */
#define ASRC_ASRMCRA_ZEROBUFA(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK)
/*! @} */

/*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */
/*! @{ */
#define ASRC_ASRFSTA_INFIFO_FILLA_MASK           (0x7FU)
#define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT          (0U)
#define ASRC_ASRFSTA_INFIFO_FILLA(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK)
#define ASRC_ASRFSTA_IAEA_MASK                   (0x800U)
#define ASRC_ASRFSTA_IAEA_SHIFT                  (11U)
#define ASRC_ASRFSTA_IAEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK)
#define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK          (0x7F000U)
#define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT         (12U)
#define ASRC_ASRFSTA_OUTFIFO_FILLA(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
#define ASRC_ASRFSTA_OAFA_MASK                   (0x800000U)
#define ASRC_ASRFSTA_OAFA_SHIFT                  (23U)
#define ASRC_ASRFSTA_OAFA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK)
/*! @} */

/*! @name ASRMCRB - ASRC Misc Control Register for Pair B */
/*! @{ */
#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK      (0x3FU)
#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT     (0U)
#define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
#define ASRC_ASRMCRB_RSYNOFB_MASK                (0x400U)
#define ASRC_ASRMCRB_RSYNOFB_SHIFT               (10U)
#define ASRC_ASRMCRB_RSYNOFB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK)
#define ASRC_ASRMCRB_RSYNIFB_MASK                (0x800U)
#define ASRC_ASRMCRB_RSYNIFB_SHIFT               (11U)
#define ASRC_ASRMCRB_RSYNIFB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK)
#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK     (0x3F000U)
#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT    (12U)
#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
#define ASRC_ASRMCRB_BYPASSPOLYB_MASK            (0x100000U)
#define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT           (20U)
/*! BYPASSPOLYB - BYPASSPOLYB
 *  0b1..Bypass polyphase filtering.
 *  0b0..Don't bypass polyphase filtering.
 */
#define ASRC_ASRMCRB_BYPASSPOLYB(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK)
#define ASRC_ASRMCRB_BUFSTALLB_MASK              (0x200000U)
#define ASRC_ASRMCRB_BUFSTALLB_SHIFT             (21U)
/*! BUFSTALLB - BUFSTALLB
 *  0b1..Stall Pair B conversion in case of near empty/full FIFO conditions.
 *  0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
 */
#define ASRC_ASRMCRB_BUFSTALLB(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK)
#define ASRC_ASRMCRB_EXTTHRSHB_MASK              (0x400000U)
#define ASRC_ASRMCRB_EXTTHRSHB_SHIFT             (22U)
/*! EXTTHRSHB - EXTTHRSHB
 *  0b1..Use external defined thresholds.
 *  0b0..Use default thresholds.
 */
#define ASRC_ASRMCRB_EXTTHRSHB(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK)
#define ASRC_ASRMCRB_ZEROBUFB_MASK               (0x800000U)
#define ASRC_ASRMCRB_ZEROBUFB_SHIFT              (23U)
/*! ZEROBUFB - ZEROBUFB
 *  0b1..Don't zeroize the buffer
 *  0b0..Zeroize the buffer
 */
#define ASRC_ASRMCRB_ZEROBUFB(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK)
/*! @} */

/*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */
/*! @{ */
#define ASRC_ASRFSTB_INFIFO_FILLB_MASK           (0x7FU)
#define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT          (0U)
#define ASRC_ASRFSTB_INFIFO_FILLB(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK)
#define ASRC_ASRFSTB_IAEB_MASK                   (0x800U)
#define ASRC_ASRFSTB_IAEB_SHIFT                  (11U)
#define ASRC_ASRFSTB_IAEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK)
#define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK          (0x7F000U)
#define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT         (12U)
#define ASRC_ASRFSTB_OUTFIFO_FILLB(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
#define ASRC_ASRFSTB_OAFB_MASK                   (0x800000U)
#define ASRC_ASRFSTB_OAFB_SHIFT                  (23U)
#define ASRC_ASRFSTB_OAFB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK)
/*! @} */

/*! @name ASRMCRC - ASRC Misc Control Register for Pair C */
/*! @{ */
#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK      (0x3FU)
#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT     (0U)
#define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
#define ASRC_ASRMCRC_RSYNOFC_MASK                (0x400U)
#define ASRC_ASRMCRC_RSYNOFC_SHIFT               (10U)
#define ASRC_ASRMCRC_RSYNOFC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK)
#define ASRC_ASRMCRC_RSYNIFC_MASK                (0x800U)
#define ASRC_ASRMCRC_RSYNIFC_SHIFT               (11U)
#define ASRC_ASRMCRC_RSYNIFC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK)
#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK     (0x3F000U)
#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT    (12U)
#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
#define ASRC_ASRMCRC_BYPASSPOLYC_MASK            (0x100000U)
#define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT           (20U)
/*! BYPASSPOLYC - BYPASSPOLYC
 *  0b1..Bypass polyphase filtering.
 *  0b0..Don't bypass polyphase filtering.
 */
#define ASRC_ASRMCRC_BYPASSPOLYC(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK)
#define ASRC_ASRMCRC_BUFSTALLC_MASK              (0x200000U)
#define ASRC_ASRMCRC_BUFSTALLC_SHIFT             (21U)
/*! BUFSTALLC - BUFSTALLC
 *  0b1..Stall Pair C conversion in case of near empty/full FIFO conditions.
 *  0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
 */
#define ASRC_ASRMCRC_BUFSTALLC(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK)
#define ASRC_ASRMCRC_EXTTHRSHC_MASK              (0x400000U)
#define ASRC_ASRMCRC_EXTTHRSHC_SHIFT             (22U)
/*! EXTTHRSHC - EXTTHRSHC
 *  0b1..Use external defined thresholds.
 *  0b0..Use default thresholds.
 */
#define ASRC_ASRMCRC_EXTTHRSHC(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK)
#define ASRC_ASRMCRC_ZEROBUFC_MASK               (0x800000U)
#define ASRC_ASRMCRC_ZEROBUFC_SHIFT              (23U)
/*! ZEROBUFC - ZEROBUFC
 *  0b1..Don't zeroize the buffer
 *  0b0..Zeroize the buffer
 */
#define ASRC_ASRMCRC_ZEROBUFC(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK)
/*! @} */

/*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */
/*! @{ */
#define ASRC_ASRFSTC_INFIFO_FILLC_MASK           (0x7FU)
#define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT          (0U)
#define ASRC_ASRFSTC_INFIFO_FILLC(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK)
#define ASRC_ASRFSTC_IAEC_MASK                   (0x800U)
#define ASRC_ASRFSTC_IAEC_SHIFT                  (11U)
#define ASRC_ASRFSTC_IAEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK)
#define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK          (0x7F000U)
#define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT         (12U)
#define ASRC_ASRFSTC_OUTFIFO_FILLC(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
#define ASRC_ASRFSTC_OAFC_MASK                   (0x800000U)
#define ASRC_ASRFSTC_OAFC_SHIFT                  (23U)
#define ASRC_ASRFSTC_OAFC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK)
/*! @} */

/*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */
/*! @{ */
#define ASRC_ASRMCR1_OW16_MASK                   (0x1U)
#define ASRC_ASRMCR1_OW16_SHIFT                  (0U)
/*! OW16 - OW16
 *  0b1..16-bit output data
 *  0b0..24-bit output data.
 */
#define ASRC_ASRMCR1_OW16(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK)
#define ASRC_ASRMCR1_OSGN_MASK                   (0x2U)
#define ASRC_ASRMCR1_OSGN_SHIFT                  (1U)
/*! OSGN - OSGN
 *  0b1..Sign extension.
 *  0b0..No sign extension.
 */
#define ASRC_ASRMCR1_OSGN(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK)
#define ASRC_ASRMCR1_OMSB_MASK                   (0x4U)
#define ASRC_ASRMCR1_OMSB_SHIFT                  (2U)
/*! OMSB - OMSB
 *  0b1..MSB aligned.
 *  0b0..LSB aligned.
 */
#define ASRC_ASRMCR1_OMSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK)
#define ASRC_ASRMCR1_IMSB_MASK                   (0x100U)
#define ASRC_ASRMCR1_IMSB_SHIFT                  (8U)
/*! IMSB - IMSB
 *  0b1..MSB aligned.
 *  0b0..LSB aligned.
 */
#define ASRC_ASRMCR1_IMSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK)
#define ASRC_ASRMCR1_IWD_MASK                    (0xE00U)
#define ASRC_ASRMCR1_IWD_SHIFT                   (9U)
#define ASRC_ASRMCR1_IWD(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK)
/*! @} */

/* The count of ASRC_ASRMCR1 */
#define ASRC_ASRMCR1_COUNT                       (3U)


/*!
 * @}
 */ /* end of group ASRC_Register_Masks */


/* ASRC - Peripheral instance base addresses */
/** Peripheral AUDIO__ASRC0 base address */
#define AUDIO__ASRC0_BASE                        (0x59000000u)
/** Peripheral AUDIO__ASRC0 base pointer */
#define AUDIO__ASRC0                             ((ASRC_Type *)AUDIO__ASRC0_BASE)
/** Peripheral AUDIO__ASRC1 base address */
#define AUDIO__ASRC1_BASE                        (0x59800000u)
/** Peripheral AUDIO__ASRC1 base pointer */
#define AUDIO__ASRC1                             ((ASRC_Type *)AUDIO__ASRC1_BASE)
/** Array initializer of ASRC peripheral base addresses */
#define ASRC_BASE_ADDRS                          { AUDIO__ASRC0_BASE, AUDIO__ASRC1_BASE }
/** Array initializer of ASRC peripheral base pointers */
#define ASRC_BASE_PTRS                           { AUDIO__ASRC0, AUDIO__ASRC1 }

/*!
 * @}
 */ /* end of group ASRC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_ACM_REGS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_ACM_REGS_Peripheral_Access_Layer AUDIO_LPCG_ACM_REGS Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_ACM_REGS - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_ACM_REGS_0;              /**< na, offset: 0x0 */
} AUDIO_LPCG_ACM_REGS_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_ACM_REGS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_ACM_REGS_Register_Masks AUDIO_LPCG_ACM_REGS Register Masks
 * @{
 */

/*! @name LPCG_LPCG_ACM_REGS_0 - na */
/*! @{ */
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_MASK (0x1U)
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_SHIFT (0U)
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_SHIFT)) & AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_HWEN_MASK)
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_2_2_MASK)
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_acm_regs_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_4_31_SHIFT (4U)
#define AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_ACM_REGS_LPCG_LPCG_ACM_REGS_0_LPCG_lpcg_acm_regs_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_ACM_REGS_Register_Masks */


/* AUDIO_LPCG_ACM_REGS - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_ACM_REGS base address */
#define AUDIO__LPCG_ACM_REGS_BASE                (0x59C60000u)
/** Peripheral AUDIO__LPCG_ACM_REGS base pointer */
#define AUDIO__LPCG_ACM_REGS                     ((AUDIO_LPCG_ACM_REGS_Type *)AUDIO__LPCG_ACM_REGS_BASE)
/** Array initializer of AUDIO_LPCG_ACM_REGS peripheral base addresses */
#define AUDIO_LPCG_ACM_REGS_BASE_ADDRS           { AUDIO__LPCG_ACM_REGS_BASE }
/** Array initializer of AUDIO_LPCG_ACM_REGS peripheral base pointers */
#define AUDIO_LPCG_ACM_REGS_BASE_PTRS            { AUDIO__LPCG_ACM_REGS }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_ACM_REGS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_AMIX Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_AMIX_Peripheral_Access_Layer AUDIO_LPCG_AMIX Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_AMIX - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_AMIX_0;                  /**< na, offset: 0x0 */
} AUDIO_LPCG_AMIX_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_AMIX Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_AMIX_Register_Masks AUDIO_LPCG_AMIX Register Masks
 * @{
 */

/*! @name LPCG_LPCG_AMIX_0 - na */
/*! @{ */
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_0_0_MASK)
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_2_2_MASK)
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_amix_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_SHIFT (4U)
#define AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_AMIX_LPCG_LPCG_AMIX_0_LPCG_lpcg_amix_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_AMIX_Register_Masks */


/* AUDIO_LPCG_AMIX - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_AMIX base address */
#define AUDIO__LPCG_AMIX_BASE                    (0x59C40000u)
/** Peripheral AUDIO__LPCG_AMIX base pointer */
#define AUDIO__LPCG_AMIX                         ((AUDIO_LPCG_AMIX_Type *)AUDIO__LPCG_AMIX_BASE)
/** Array initializer of AUDIO_LPCG_AMIX peripheral base addresses */
#define AUDIO_LPCG_AMIX_BASE_ADDRS               { AUDIO__LPCG_AMIX_BASE }
/** Array initializer of AUDIO_LPCG_AMIX peripheral base pointers */
#define AUDIO_LPCG_AMIX_BASE_PTRS                { AUDIO__LPCG_AMIX }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_AMIX_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_ASRC0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_ASRC0_Peripheral_Access_Layer AUDIO_LPCG_ASRC0 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_ASRC0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_ASRC0_0;                 /**< na, offset: 0x0 */
} AUDIO_LPCG_ASRC0_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_ASRC0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_ASRC0_Register_Masks AUDIO_LPCG_ASRC0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_ASRC0_0 - na */
/*! @{ */
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_0_0_MASK)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_2_2_MASK)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_4_8_MASK (0x1F0U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_4_8_SHIFT (4U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_4_8(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_4_8_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_4_8_MASK)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_SWEN_MASK (0x200U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_SWEN_SHIFT (9U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_10_10_MASK (0x400U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_10_10_SHIFT (10U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_10_10_MASK)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_STOP_MASK (0x800U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_STOP_SHIFT (11U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_asrc0_mem_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_12_31_MASK (0xFFFFF000U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_12_31_SHIFT (12U)
#define AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_12_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_12_31_SHIFT)) & AUDIO_LPCG_ASRC0_LPCG_LPCG_ASRC0_0_LPCG_lpcg_asrc0_0_reserved_12_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_ASRC0_Register_Masks */


/* AUDIO_LPCG_ASRC0 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_ASRC0 base address */
#define AUDIO__LPCG_ASRC0_BASE                   (0x59400000u)
/** Peripheral AUDIO__LPCG_ASRC0 base pointer */
#define AUDIO__LPCG_ASRC0                        ((AUDIO_LPCG_ASRC0_Type *)AUDIO__LPCG_ASRC0_BASE)
/** Array initializer of AUDIO_LPCG_ASRC0 peripheral base addresses */
#define AUDIO_LPCG_ASRC0_BASE_ADDRS              { AUDIO__LPCG_ASRC0_BASE }
/** Array initializer of AUDIO_LPCG_ASRC0 peripheral base pointers */
#define AUDIO_LPCG_ASRC0_BASE_PTRS               { AUDIO__LPCG_ASRC0 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_ASRC0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_ASRC1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_ASRC1_Peripheral_Access_Layer AUDIO_LPCG_ASRC1 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_ASRC1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_ASRC1_0;                 /**< na, offset: 0x0 */
} AUDIO_LPCG_ASRC1_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_ASRC1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_ASRC1_Register_Masks AUDIO_LPCG_ASRC1 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_ASRC1_0 - na */
/*! @{ */
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_0_0_MASK)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_2_2_MASK)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_4_8_MASK (0x1F0U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_4_8_SHIFT (4U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_4_8(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_4_8_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_4_8_MASK)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_SWEN_MASK (0x200U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_SWEN_SHIFT (9U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_10_10_MASK (0x400U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_10_10_SHIFT (10U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_10_10_MASK)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_STOP_MASK (0x800U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_STOP_SHIFT (11U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_asrc1_mem_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_12_31_MASK (0xFFFFF000U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_12_31_SHIFT (12U)
#define AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_12_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_12_31_SHIFT)) & AUDIO_LPCG_ASRC1_LPCG_LPCG_ASRC1_0_LPCG_lpcg_asrc1_0_reserved_12_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_ASRC1_Register_Masks */


/* AUDIO_LPCG_ASRC1 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_ASRC1 base address */
#define AUDIO__LPCG_ASRC1_BASE                   (0x59C00000u)
/** Peripheral AUDIO__LPCG_ASRC1 base pointer */
#define AUDIO__LPCG_ASRC1                        ((AUDIO_LPCG_ASRC1_Type *)AUDIO__LPCG_ASRC1_BASE)
/** Array initializer of AUDIO_LPCG_ASRC1 peripheral base addresses */
#define AUDIO_LPCG_ASRC1_BASE_ADDRS              { AUDIO__LPCG_ASRC1_BASE }
/** Array initializer of AUDIO_LPCG_ASRC1 peripheral base pointers */
#define AUDIO_LPCG_ASRC1_BASE_PTRS               { AUDIO__LPCG_ASRC1 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_ASRC1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_AUD_PLL_DIV_CLK0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_AUD_PLL_DIV_CLK0_Peripheral_Access_Layer AUDIO_LPCG_AUD_PLL_DIV_CLK0 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_AUD_PLL_DIV_CLK0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_AUD_PLL_DIV_CLK0_0;      /**< na, offset: 0x0 */
} AUDIO_LPCG_AUD_PLL_DIV_CLK0_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_AUD_PLL_DIV_CLK0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_AUD_PLL_DIV_CLK0_Register_Masks AUDIO_LPCG_AUD_PLL_DIV_CLK0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_AUD_PLL_DIV_CLK0_0 - na */
/*! @{ */
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_0_0_MASK)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_MASK (0x2U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_SHIFT (1U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_SWEN_MASK)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_2_2_MASK)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_MASK (0x8U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_SHIFT (3U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_acm_aud_pll_div_clk0_STOP_MASK)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_SHIFT (4U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK0_LPCG_LPCG_AUD_PLL_DIV_CLK0_0_LPCG_lpcg_aud_pll_div_clk0_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_AUD_PLL_DIV_CLK0_Register_Masks */


/* AUDIO_LPCG_AUD_PLL_DIV_CLK0 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0 base address */
#define AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0_BASE    (0x59D20000u)
/** Peripheral AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0 base pointer */
#define AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0         ((AUDIO_LPCG_AUD_PLL_DIV_CLK0_Type *)AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0_BASE)
/** Array initializer of AUDIO_LPCG_AUD_PLL_DIV_CLK0 peripheral base addresses */
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_BASE_ADDRS   { AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0_BASE }
/** Array initializer of AUDIO_LPCG_AUD_PLL_DIV_CLK0 peripheral base pointers */
#define AUDIO_LPCG_AUD_PLL_DIV_CLK0_BASE_PTRS    { AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_AUD_PLL_DIV_CLK0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_AUD_PLL_DIV_CLK1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_AUD_PLL_DIV_CLK1_Peripheral_Access_Layer AUDIO_LPCG_AUD_PLL_DIV_CLK1 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_AUD_PLL_DIV_CLK1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_AUD_PLL_DIV_CLK1_0;      /**< na, offset: 0x0 */
} AUDIO_LPCG_AUD_PLL_DIV_CLK1_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_AUD_PLL_DIV_CLK1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_AUD_PLL_DIV_CLK1_Register_Masks AUDIO_LPCG_AUD_PLL_DIV_CLK1 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_AUD_PLL_DIV_CLK1_0 - na */
/*! @{ */
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_0_0_MASK)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_MASK (0x2U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_SHIFT (1U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_SWEN_MASK)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_2_2_MASK)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_MASK (0x8U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_SHIFT (3U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_acm_aud_pll_div_clk1_STOP_MASK)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_SHIFT (4U)
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_AUD_PLL_DIV_CLK1_LPCG_LPCG_AUD_PLL_DIV_CLK1_0_LPCG_lpcg_aud_pll_div_clk1_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_AUD_PLL_DIV_CLK1_Register_Masks */


/* AUDIO_LPCG_AUD_PLL_DIV_CLK1 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1 base address */
#define AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1_BASE    (0x59D30000u)
/** Peripheral AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1 base pointer */
#define AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1         ((AUDIO_LPCG_AUD_PLL_DIV_CLK1_Type *)AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1_BASE)
/** Array initializer of AUDIO_LPCG_AUD_PLL_DIV_CLK1 peripheral base addresses */
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_BASE_ADDRS   { AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1_BASE }
/** Array initializer of AUDIO_LPCG_AUD_PLL_DIV_CLK1 peripheral base pointers */
#define AUDIO_LPCG_AUD_PLL_DIV_CLK1_BASE_PTRS    { AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_AUD_PLL_DIV_CLK1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_AUD_REC_CLK0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_AUD_REC_CLK0_Peripheral_Access_Layer AUDIO_LPCG_AUD_REC_CLK0 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_AUD_REC_CLK0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_AUD_REC_CLK0_0;          /**< na, offset: 0x0 */
} AUDIO_LPCG_AUD_REC_CLK0_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_AUD_REC_CLK0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_AUD_REC_CLK0_Register_Masks AUDIO_LPCG_AUD_REC_CLK0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_AUD_REC_CLK0_0 - na */
/*! @{ */
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_0_0_MASK)
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_MASK (0x2U)
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_SHIFT (1U)
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_SWEN_MASK)
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_2_2_MASK)
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_MASK (0x8U)
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_SHIFT (3U)
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_acm_aud_rec_clk0_STOP_MASK)
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_SHIFT (4U)
#define AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK0_LPCG_LPCG_AUD_REC_CLK0_0_LPCG_lpcg_aud_rec_clk0_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_AUD_REC_CLK0_Register_Masks */


/* AUDIO_LPCG_AUD_REC_CLK0 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_ACM_AUD_REC_CLK0 base address */
#define AUDIO__LPCG_ACM_AUD_REC_CLK0_BASE        (0x59D00000u)
/** Peripheral AUDIO__LPCG_ACM_AUD_REC_CLK0 base pointer */
#define AUDIO__LPCG_ACM_AUD_REC_CLK0             ((AUDIO_LPCG_AUD_REC_CLK0_Type *)AUDIO__LPCG_ACM_AUD_REC_CLK0_BASE)
/** Array initializer of AUDIO_LPCG_AUD_REC_CLK0 peripheral base addresses */
#define AUDIO_LPCG_AUD_REC_CLK0_BASE_ADDRS       { AUDIO__LPCG_ACM_AUD_REC_CLK0_BASE }
/** Array initializer of AUDIO_LPCG_AUD_REC_CLK0 peripheral base pointers */
#define AUDIO_LPCG_AUD_REC_CLK0_BASE_PTRS        { AUDIO__LPCG_ACM_AUD_REC_CLK0 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_AUD_REC_CLK0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_AUD_REC_CLK1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_AUD_REC_CLK1_Peripheral_Access_Layer AUDIO_LPCG_AUD_REC_CLK1 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_AUD_REC_CLK1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_AUD_REC_CLK1_0;          /**< na, offset: 0x0 */
} AUDIO_LPCG_AUD_REC_CLK1_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_AUD_REC_CLK1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_AUD_REC_CLK1_Register_Masks AUDIO_LPCG_AUD_REC_CLK1 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_AUD_REC_CLK1_0 - na */
/*! @{ */
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_0_0_MASK)
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_MASK (0x2U)
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_SHIFT (1U)
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_SWEN_MASK)
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_2_2_MASK)
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_MASK (0x8U)
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_SHIFT (3U)
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_acm_aud_rec_clk1_STOP_MASK)
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_SHIFT (4U)
#define AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_AUD_REC_CLK1_LPCG_LPCG_AUD_REC_CLK1_0_LPCG_lpcg_aud_rec_clk1_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_AUD_REC_CLK1_Register_Masks */


/* AUDIO_LPCG_AUD_REC_CLK1 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_ACM_AUD_REC_CLK1 base address */
#define AUDIO__LPCG_ACM_AUD_REC_CLK1_BASE        (0x59D10000u)
/** Peripheral AUDIO__LPCG_ACM_AUD_REC_CLK1 base pointer */
#define AUDIO__LPCG_ACM_AUD_REC_CLK1             ((AUDIO_LPCG_AUD_REC_CLK1_Type *)AUDIO__LPCG_ACM_AUD_REC_CLK1_BASE)
/** Array initializer of AUDIO_LPCG_AUD_REC_CLK1 peripheral base addresses */
#define AUDIO_LPCG_AUD_REC_CLK1_BASE_ADDRS       { AUDIO__LPCG_ACM_AUD_REC_CLK1_BASE }
/** Array initializer of AUDIO_LPCG_AUD_REC_CLK1 peripheral base pointers */
#define AUDIO_LPCG_AUD_REC_CLK1_BASE_PTRS        { AUDIO__LPCG_ACM_AUD_REC_CLK1 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_AUD_REC_CLK1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_EDMA0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_EDMA0_Peripheral_Access_Layer AUDIO_LPCG_EDMA0 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_EDMA0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_EDMA0_0;                 /**< na, offset: 0x0 */
} AUDIO_LPCG_EDMA0_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_EDMA0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_EDMA0_Register_Masks AUDIO_LPCG_EDMA0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_EDMA0_0 - na */
/*! @{ */
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_0_0_MASK)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_2_2_MASK)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_MASK (0x1FFF0U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_SHIFT (4U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_4_16_MASK)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_SHIFT (17U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_SWEN_MASK)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_18_18_MASK)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_MASK (0x80000U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_SHIFT (19U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_hclk_STOP_MASK)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_24_MASK (0x1F00000U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_24_SHIFT (20U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_24(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_24_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_20_24_MASK)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_SWEN_MASK (0x2000000U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_SWEN_SHIFT (25U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_SWEN_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_SWEN_MASK)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_26_26_MASK (0x4000000U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_26_26_SHIFT (26U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_26_26_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_26_26_MASK)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_STOP_MASK (0x8000000U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_STOP_SHIFT (27U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_STOP_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_edma0_mem_hclk_STOP_MASK)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_28_31_MASK (0xF0000000U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_28_31_SHIFT (28U)
#define AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_28_31_SHIFT)) & AUDIO_LPCG_EDMA0_LPCG_LPCG_EDMA0_0_LPCG_lpcg_edma0_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_EDMA0_Register_Masks */


/* AUDIO_LPCG_EDMA0 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_EDMA0 base address */
#define AUDIO__LPCG_EDMA0_BASE                   (0x595F0000u)
/** Peripheral AUDIO__LPCG_EDMA0 base pointer */
#define AUDIO__LPCG_EDMA0                        ((AUDIO_LPCG_EDMA0_Type *)AUDIO__LPCG_EDMA0_BASE)
/** Array initializer of AUDIO_LPCG_EDMA0 peripheral base addresses */
#define AUDIO_LPCG_EDMA0_BASE_ADDRS              { AUDIO__LPCG_EDMA0_BASE }
/** Array initializer of AUDIO_LPCG_EDMA0 peripheral base pointers */
#define AUDIO_LPCG_EDMA0_BASE_PTRS               { AUDIO__LPCG_EDMA0 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_EDMA0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_EDMA1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_EDMA1_Peripheral_Access_Layer AUDIO_LPCG_EDMA1 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_EDMA1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_EDMA1_0;                 /**< na, offset: 0x0 */
} AUDIO_LPCG_EDMA1_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_EDMA1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_EDMA1_Register_Masks AUDIO_LPCG_EDMA1 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_EDMA1_0 - na */
/*! @{ */
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_0_0_MASK)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_2_2_MASK)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_MASK (0x1FFF0U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_SHIFT (4U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_4_16_MASK)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_SHIFT (17U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_SWEN_MASK)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_18_18_MASK)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_MASK (0x80000U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_SHIFT (19U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_hclk_STOP_MASK)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_24_MASK (0x1F00000U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_24_SHIFT (20U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_24(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_24_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_20_24_MASK)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_SWEN_MASK (0x2000000U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_SWEN_SHIFT (25U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_SWEN_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_SWEN_MASK)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_26_26_MASK (0x4000000U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_26_26_SHIFT (26U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_26_26_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_26_26_MASK)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_STOP_MASK (0x8000000U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_STOP_SHIFT (27U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_STOP_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_edma1_mem_hclk_STOP_MASK)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_28_31_MASK (0xF0000000U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_28_31_SHIFT (28U)
#define AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_28_31_SHIFT)) & AUDIO_LPCG_EDMA1_LPCG_LPCG_EDMA1_0_LPCG_lpcg_edma1_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_EDMA1_Register_Masks */


/* AUDIO_LPCG_EDMA1 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_EDMA1 base address */
#define AUDIO__LPCG_EDMA1_BASE                   (0x59DF0000u)
/** Peripheral AUDIO__LPCG_EDMA1 base pointer */
#define AUDIO__LPCG_EDMA1                        ((AUDIO_LPCG_EDMA1_Type *)AUDIO__LPCG_EDMA1_BASE)
/** Array initializer of AUDIO_LPCG_EDMA1 peripheral base addresses */
#define AUDIO_LPCG_EDMA1_BASE_ADDRS              { AUDIO__LPCG_EDMA1_BASE }
/** Array initializer of AUDIO_LPCG_EDMA1 peripheral base pointers */
#define AUDIO_LPCG_EDMA1_BASE_PTRS               { AUDIO__LPCG_EDMA1 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_EDMA1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_ESAI0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_ESAI0_Peripheral_Access_Layer AUDIO_LPCG_ESAI0 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_ESAI0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_ESAI0_0;                 /**< na, offset: 0x0 */
} AUDIO_LPCG_ESAI0_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_ESAI0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_ESAI0_Register_Masks AUDIO_LPCG_ESAI0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_ESAI0_0 - na */
/*! @{ */
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_MASK (0x1U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_SHIFT (0U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_MASK (0x2U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_SHIFT (1U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_2_2_MASK)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_MASK (0x8U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_SHIFT (3U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_16_MASK (0x1FFF0U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_16_SHIFT (4U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_4_16_MASK)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_SHIFT (17U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_SWEN_MASK)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_18_18_MASK)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_MASK (0x80000U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_SHIFT (19U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_esai0_extal_clk_STOP_MASK)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_MASK (0xFFF00000U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_SHIFT (20U)
#define AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_ESAI0_LPCG_LPCG_ESAI0_0_LPCG_lpcg_esai0_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_ESAI0_Register_Masks */


/* AUDIO_LPCG_ESAI0 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_ESAI0 base address */
#define AUDIO__LPCG_ESAI0_BASE                   (0x59410000u)
/** Peripheral AUDIO__LPCG_ESAI0 base pointer */
#define AUDIO__LPCG_ESAI0                        ((AUDIO_LPCG_ESAI0_Type *)AUDIO__LPCG_ESAI0_BASE)
/** Array initializer of AUDIO_LPCG_ESAI0 peripheral base addresses */
#define AUDIO_LPCG_ESAI0_BASE_ADDRS              { AUDIO__LPCG_ESAI0_BASE }
/** Array initializer of AUDIO_LPCG_ESAI0 peripheral base pointers */
#define AUDIO_LPCG_ESAI0_BASE_PTRS               { AUDIO__LPCG_ESAI0 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_ESAI0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_ESAI1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_ESAI1_Peripheral_Access_Layer AUDIO_LPCG_ESAI1 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_ESAI1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_ESAI1_0;                 /**< na, offset: 0x0 */
} AUDIO_LPCG_ESAI1_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_ESAI1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_ESAI1_Register_Masks AUDIO_LPCG_ESAI1 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_ESAI1_0 - na */
/*! @{ */
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_HWEN_MASK (0x1U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_HWEN_SHIFT (0U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_SWEN_MASK (0x2U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_SWEN_SHIFT (1U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_2_2_MASK)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_STOP_MASK (0x8U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_STOP_SHIFT (3U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_4_16_MASK (0x1FFF0U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_4_16_SHIFT (4U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_4_16_MASK)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_SWEN_SHIFT (17U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_SWEN_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_SWEN_MASK)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_18_18_MASK)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_STOP_MASK (0x80000U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_STOP_SHIFT (19U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_STOP_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_esai1_extal_clk_STOP_MASK)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_20_31_MASK (0xFFF00000U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_20_31_SHIFT (20U)
#define AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_ESAI1_LPCG_LPCG_ESAI1_0_LPCG_lpcg_esai1_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_ESAI1_Register_Masks */


/* AUDIO_LPCG_ESAI1 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_ESAI1 base address */
#define AUDIO__LPCG_ESAI1_BASE                   (0x59C10000u)
/** Peripheral AUDIO__LPCG_ESAI1 base pointer */
#define AUDIO__LPCG_ESAI1                        ((AUDIO_LPCG_ESAI1_Type *)AUDIO__LPCG_ESAI1_BASE)
/** Array initializer of AUDIO_LPCG_ESAI1 peripheral base addresses */
#define AUDIO_LPCG_ESAI1_BASE_ADDRS              { AUDIO__LPCG_ESAI1_BASE }
/** Array initializer of AUDIO_LPCG_ESAI1 peripheral base pointers */
#define AUDIO_LPCG_ESAI1_BASE_PTRS               { AUDIO__LPCG_ESAI1 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_ESAI1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_GPT0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_GPT0_Peripheral_Access_Layer AUDIO_LPCG_GPT0 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_GPT0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_GPT0_0;                  /**< na, offset: 0x0 */
} AUDIO_LPCG_GPT0_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_GPT0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_GPT0_Register_Masks AUDIO_LPCG_GPT0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_GPT0_0 - na */
/*! @{ */
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_HWEN_MASK (0x1U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_HWEN_SHIFT (0U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_SWEN_MASK (0x2U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_SWEN_SHIFT (1U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_2_2_MASK)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_STOP_MASK (0x8U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_STOP_SHIFT (3U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_16_MASK (0x1FFF0U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_16_SHIFT (4U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_4_16_MASK)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_SHIFT (17U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_SWEN_MASK)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_18_18_MASK)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_MASK (0x80000U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_SHIFT (19U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipp_ind_clkin_STOP_MASK)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_20_MASK (0x100000U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_20_SHIFT (20U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_20_20_MASK)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_SWEN_MASK (0x200000U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_SWEN_SHIFT (21U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_SWEN_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_SWEN_MASK)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_22_22_MASK (0x400000U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_22_22_SHIFT (22U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_22_22_MASK)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_STOP_MASK (0x800000U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_STOP_SHIFT (23U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_STOP_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_gpt0_ipg_clk_24m_STOP_MASK)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_24_31_MASK (0xFF000000U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_24_31_SHIFT (24U)
#define AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_GPT0_LPCG_LPCG_GPT0_0_LPCG_lpcg_gpt0_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_GPT0_Register_Masks */


/* AUDIO_LPCG_GPT0 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_GPT0 base address */
#define AUDIO__LPCG_GPT0_BASE                    (0x594B0000u)
/** Peripheral AUDIO__LPCG_GPT0 base pointer */
#define AUDIO__LPCG_GPT0                         ((AUDIO_LPCG_GPT0_Type *)AUDIO__LPCG_GPT0_BASE)
/** Array initializer of AUDIO_LPCG_GPT0 peripheral base addresses */
#define AUDIO_LPCG_GPT0_BASE_ADDRS               { AUDIO__LPCG_GPT0_BASE }
/** Array initializer of AUDIO_LPCG_GPT0 peripheral base pointers */
#define AUDIO_LPCG_GPT0_BASE_PTRS                { AUDIO__LPCG_GPT0 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_GPT0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_GPT1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_GPT1_Peripheral_Access_Layer AUDIO_LPCG_GPT1 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_GPT1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_GPT1_0;                  /**< na, offset: 0x0 */
} AUDIO_LPCG_GPT1_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_GPT1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_GPT1_Register_Masks AUDIO_LPCG_GPT1 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_GPT1_0 - na */
/*! @{ */
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_HWEN_MASK (0x1U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_HWEN_SHIFT (0U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_SWEN_MASK (0x2U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_SWEN_SHIFT (1U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_2_2_MASK)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_STOP_MASK (0x8U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_STOP_SHIFT (3U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_16_MASK (0x1FFF0U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_16_SHIFT (4U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_4_16_MASK)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_SHIFT (17U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_SWEN_MASK)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_18_18_MASK)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_MASK (0x80000U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_SHIFT (19U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipp_ind_clkin_STOP_MASK)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_20_MASK (0x100000U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_20_SHIFT (20U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_20_20_MASK)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_SWEN_MASK (0x200000U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_SWEN_SHIFT (21U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_SWEN_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_SWEN_MASK)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_22_22_MASK (0x400000U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_22_22_SHIFT (22U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_22_22_MASK)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_STOP_MASK (0x800000U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_STOP_SHIFT (23U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_STOP_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_gpt1_ipg_clk_24m_STOP_MASK)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_24_31_MASK (0xFF000000U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_24_31_SHIFT (24U)
#define AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_GPT1_LPCG_LPCG_GPT1_0_LPCG_lpcg_gpt1_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_GPT1_Register_Masks */


/* AUDIO_LPCG_GPT1 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_GPT1 base address */
#define AUDIO__LPCG_GPT1_BASE                    (0x594C0000u)
/** Peripheral AUDIO__LPCG_GPT1 base pointer */
#define AUDIO__LPCG_GPT1                         ((AUDIO_LPCG_GPT1_Type *)AUDIO__LPCG_GPT1_BASE)
/** Array initializer of AUDIO_LPCG_GPT1 peripheral base addresses */
#define AUDIO_LPCG_GPT1_BASE_ADDRS               { AUDIO__LPCG_GPT1_BASE }
/** Array initializer of AUDIO_LPCG_GPT1 peripheral base pointers */
#define AUDIO_LPCG_GPT1_BASE_PTRS                { AUDIO__LPCG_GPT1 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_GPT1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_GPT2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_GPT2_Peripheral_Access_Layer AUDIO_LPCG_GPT2 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_GPT2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_GPT2_0;                  /**< na, offset: 0x0 */
} AUDIO_LPCG_GPT2_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_GPT2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_GPT2_Register_Masks AUDIO_LPCG_GPT2 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_GPT2_0 - na */
/*! @{ */
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_HWEN_MASK (0x1U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_HWEN_SHIFT (0U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_SWEN_MASK (0x2U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_SWEN_SHIFT (1U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_2_2_MASK)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_STOP_MASK (0x8U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_STOP_SHIFT (3U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_16_MASK (0x1FFF0U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_16_SHIFT (4U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_4_16_MASK)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_SHIFT (17U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_SWEN_MASK)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_18_18_MASK)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_MASK (0x80000U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_SHIFT (19U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipp_ind_clkin_STOP_MASK)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_20_MASK (0x100000U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_20_SHIFT (20U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_20_20_MASK)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_SWEN_MASK (0x200000U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_SWEN_SHIFT (21U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_SWEN_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_SWEN_MASK)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_22_22_MASK (0x400000U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_22_22_SHIFT (22U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_22_22_MASK)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_STOP_MASK (0x800000U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_STOP_SHIFT (23U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_STOP_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_gpt2_ipg_clk_24m_STOP_MASK)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_24_31_MASK (0xFF000000U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_24_31_SHIFT (24U)
#define AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_GPT2_LPCG_LPCG_GPT2_0_LPCG_lpcg_gpt2_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_GPT2_Register_Masks */


/* AUDIO_LPCG_GPT2 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_GPT2 base address */
#define AUDIO__LPCG_GPT2_BASE                    (0x594D0000u)
/** Peripheral AUDIO__LPCG_GPT2 base pointer */
#define AUDIO__LPCG_GPT2                         ((AUDIO_LPCG_GPT2_Type *)AUDIO__LPCG_GPT2_BASE)
/** Array initializer of AUDIO_LPCG_GPT2 peripheral base addresses */
#define AUDIO_LPCG_GPT2_BASE_ADDRS               { AUDIO__LPCG_GPT2_BASE }
/** Array initializer of AUDIO_LPCG_GPT2 peripheral base pointers */
#define AUDIO_LPCG_GPT2_BASE_PTRS                { AUDIO__LPCG_GPT2 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_GPT2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_GPT3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_GPT3_Peripheral_Access_Layer AUDIO_LPCG_GPT3 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_GPT3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_GPT3_0;                  /**< na, offset: 0x0 */
} AUDIO_LPCG_GPT3_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_GPT3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_GPT3_Register_Masks AUDIO_LPCG_GPT3 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_GPT3_0 - na */
/*! @{ */
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_HWEN_MASK (0x1U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_HWEN_SHIFT (0U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_SWEN_MASK (0x2U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_SWEN_SHIFT (1U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_2_2_MASK)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_STOP_MASK (0x8U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_STOP_SHIFT (3U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_16_MASK (0x1FFF0U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_16_SHIFT (4U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_4_16_MASK)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_SHIFT (17U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_SWEN_MASK)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_18_18_MASK)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_MASK (0x80000U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_SHIFT (19U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipp_ind_clkin_STOP_MASK)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_20_MASK (0x100000U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_20_SHIFT (20U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_20_20_MASK)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_SWEN_MASK (0x200000U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_SWEN_SHIFT (21U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_SWEN_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_SWEN_MASK)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_22_22_MASK (0x400000U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_22_22_SHIFT (22U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_22_22_MASK)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_STOP_MASK (0x800000U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_STOP_SHIFT (23U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_STOP_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_gpt3_ipg_clk_24m_STOP_MASK)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_24_31_MASK (0xFF000000U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_24_31_SHIFT (24U)
#define AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_GPT3_LPCG_LPCG_GPT3_0_LPCG_lpcg_gpt3_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_GPT3_Register_Masks */


/* AUDIO_LPCG_GPT3 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_GPT3 base address */
#define AUDIO__LPCG_GPT3_BASE                    (0x594E0000u)
/** Peripheral AUDIO__LPCG_GPT3 base pointer */
#define AUDIO__LPCG_GPT3                         ((AUDIO_LPCG_GPT3_Type *)AUDIO__LPCG_GPT3_BASE)
/** Array initializer of AUDIO_LPCG_GPT3 peripheral base addresses */
#define AUDIO_LPCG_GPT3_BASE_ADDRS               { AUDIO__LPCG_GPT3_BASE }
/** Array initializer of AUDIO_LPCG_GPT3 peripheral base pointers */
#define AUDIO_LPCG_GPT3_BASE_PTRS                { AUDIO__LPCG_GPT3 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_GPT3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_GPT4 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_GPT4_Peripheral_Access_Layer AUDIO_LPCG_GPT4 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_GPT4 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_GPT4_0;                  /**< na, offset: 0x0 */
} AUDIO_LPCG_GPT4_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_GPT4 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_GPT4_Register_Masks AUDIO_LPCG_GPT4 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_GPT4_0 - na */
/*! @{ */
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_HWEN_MASK (0x1U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_HWEN_SHIFT (0U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_SWEN_MASK (0x2U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_SWEN_SHIFT (1U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_2_2_MASK)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_STOP_MASK (0x8U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_STOP_SHIFT (3U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_16_MASK (0x1FFF0U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_16_SHIFT (4U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_4_16_MASK)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_SHIFT (17U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_SWEN_MASK)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_18_18_MASK)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_MASK (0x80000U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_SHIFT (19U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipp_ind_clkin_STOP_MASK)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_20_MASK (0x100000U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_20_SHIFT (20U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_20_20_MASK)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_SWEN_MASK (0x200000U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_SWEN_SHIFT (21U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_SWEN_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_SWEN_MASK)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_22_22_MASK (0x400000U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_22_22_SHIFT (22U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_22_22_MASK)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_STOP_MASK (0x800000U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_STOP_SHIFT (23U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_STOP_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_gpt4_ipg_clk_24m_STOP_MASK)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_24_31_MASK (0xFF000000U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_24_31_SHIFT (24U)
#define AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_GPT4_LPCG_LPCG_GPT4_0_LPCG_lpcg_gpt4_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_GPT4_Register_Masks */


/* AUDIO_LPCG_GPT4 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_GPT4 base address */
#define AUDIO__LPCG_GPT4_BASE                    (0x594F0000u)
/** Peripheral AUDIO__LPCG_GPT4 base pointer */
#define AUDIO__LPCG_GPT4                         ((AUDIO_LPCG_GPT4_Type *)AUDIO__LPCG_GPT4_BASE)
/** Array initializer of AUDIO_LPCG_GPT4 peripheral base addresses */
#define AUDIO_LPCG_GPT4_BASE_ADDRS               { AUDIO__LPCG_GPT4_BASE }
/** Array initializer of AUDIO_LPCG_GPT4 peripheral base pointers */
#define AUDIO_LPCG_GPT4_BASE_PTRS                { AUDIO__LPCG_GPT4 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_GPT4_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_GPT5 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_GPT5_Peripheral_Access_Layer AUDIO_LPCG_GPT5 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_GPT5 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_GPT5_0;                  /**< na, offset: 0x0 */
} AUDIO_LPCG_GPT5_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_GPT5 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_GPT5_Register_Masks AUDIO_LPCG_GPT5 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_GPT5_0 - na */
/*! @{ */
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_HWEN_MASK (0x1U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_HWEN_SHIFT (0U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_SWEN_MASK (0x2U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_SWEN_SHIFT (1U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_2_2_MASK)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_STOP_MASK (0x8U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_STOP_SHIFT (3U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_16_MASK (0x1FFF0U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_16_SHIFT (4U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_4_16_MASK)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_SHIFT (17U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_SWEN_MASK)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_18_18_MASK)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_MASK (0x80000U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_SHIFT (19U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipp_ind_clkin_STOP_MASK)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_20_MASK (0x100000U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_20_SHIFT (20U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_20_20_MASK)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_SWEN_MASK (0x200000U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_SWEN_SHIFT (21U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_SWEN_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_SWEN_MASK)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_22_22_MASK (0x400000U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_22_22_SHIFT (22U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_22_22_MASK)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_STOP_MASK (0x800000U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_STOP_SHIFT (23U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_STOP_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_gpt5_ipg_clk_24m_STOP_MASK)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_24_31_MASK (0xFF000000U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_24_31_SHIFT (24U)
#define AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_GPT5_LPCG_LPCG_GPT5_0_LPCG_lpcg_gpt5_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_GPT5_Register_Masks */


/* AUDIO_LPCG_GPT5 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_GPT5 base address */
#define AUDIO__LPCG_GPT5_BASE                    (0x59500000u)
/** Peripheral AUDIO__LPCG_GPT5 base pointer */
#define AUDIO__LPCG_GPT5                         ((AUDIO_LPCG_GPT5_Type *)AUDIO__LPCG_GPT5_BASE)
/** Array initializer of AUDIO_LPCG_GPT5 peripheral base addresses */
#define AUDIO_LPCG_GPT5_BASE_ADDRS               { AUDIO__LPCG_GPT5_BASE }
/** Array initializer of AUDIO_LPCG_GPT5 peripheral base pointers */
#define AUDIO_LPCG_GPT5_BASE_PTRS                { AUDIO__LPCG_GPT5 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_GPT5_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_MCLKOUT0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_MCLKOUT0_Peripheral_Access_Layer AUDIO_LPCG_MCLKOUT0 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_MCLKOUT0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_MCLKOUT0_0;              /**< na, offset: 0x0 */
} AUDIO_LPCG_MCLKOUT0_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_MCLKOUT0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_MCLKOUT0_Register_Masks AUDIO_LPCG_MCLKOUT0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_MCLKOUT0_0 - na */
/*! @{ */
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_0_0_MASK)
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_MASK (0x2U)
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_SHIFT (1U)
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_SHIFT)) & AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_SWEN_MASK)
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_2_2_MASK)
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_MASK (0x8U)
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_SHIFT (3U)
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_SHIFT)) & AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_mclkout0_STOP_MASK)
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_SHIFT (4U)
#define AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_MCLKOUT0_LPCG_LPCG_MCLKOUT0_0_LPCG_lpcg_mclkout0_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_MCLKOUT0_Register_Masks */


/* AUDIO_LPCG_MCLKOUT0 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_MCLKOUT0 base address */
#define AUDIO__LPCG_MCLKOUT0_BASE                (0x59D50000u)
/** Peripheral AUDIO__LPCG_MCLKOUT0 base pointer */
#define AUDIO__LPCG_MCLKOUT0                     ((AUDIO_LPCG_MCLKOUT0_Type *)AUDIO__LPCG_MCLKOUT0_BASE)
/** Array initializer of AUDIO_LPCG_MCLKOUT0 peripheral base addresses */
#define AUDIO_LPCG_MCLKOUT0_BASE_ADDRS           { AUDIO__LPCG_MCLKOUT0_BASE }
/** Array initializer of AUDIO_LPCG_MCLKOUT0 peripheral base pointers */
#define AUDIO_LPCG_MCLKOUT0_BASE_PTRS            { AUDIO__LPCG_MCLKOUT0 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_MCLKOUT0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_MCLKOUT1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_MCLKOUT1_Peripheral_Access_Layer AUDIO_LPCG_MCLKOUT1 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_MCLKOUT1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_MCLKOUT1_0;              /**< na, offset: 0x0 */
} AUDIO_LPCG_MCLKOUT1_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_MCLKOUT1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_MCLKOUT1_Register_Masks AUDIO_LPCG_MCLKOUT1 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_MCLKOUT1_0 - na */
/*! @{ */
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_0_0_MASK)
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_MASK (0x2U)
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_SHIFT (1U)
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_SHIFT)) & AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_SWEN_MASK)
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_2_2_MASK)
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_MASK (0x8U)
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_SHIFT (3U)
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_SHIFT)) & AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_mclkout1_STOP_MASK)
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_SHIFT (4U)
#define AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_SHIFT)) & AUDIO_LPCG_MCLKOUT1_LPCG_LPCG_MCLKOUT1_0_LPCG_lpcg_mclkout1_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_MCLKOUT1_Register_Masks */


/* AUDIO_LPCG_MCLKOUT1 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_MCLKOUT1 base address */
#define AUDIO__LPCG_MCLKOUT1_BASE                (0x59D60000u)
/** Peripheral AUDIO__LPCG_MCLKOUT1 base pointer */
#define AUDIO__LPCG_MCLKOUT1                     ((AUDIO_LPCG_MCLKOUT1_Type *)AUDIO__LPCG_MCLKOUT1_BASE)
/** Array initializer of AUDIO_LPCG_MCLKOUT1 peripheral base addresses */
#define AUDIO_LPCG_MCLKOUT1_BASE_ADDRS           { AUDIO__LPCG_MCLKOUT1_BASE }
/** Array initializer of AUDIO_LPCG_MCLKOUT1 peripheral base pointers */
#define AUDIO_LPCG_MCLKOUT1_BASE_PTRS            { AUDIO__LPCG_MCLKOUT1 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_MCLKOUT1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_MQS_REGS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_MQS_REGS_Peripheral_Access_Layer AUDIO_LPCG_MQS_REGS Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_MQS_REGS - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_MQS_REGS_0;              /**< na, offset: 0x0 */
} AUDIO_LPCG_MQS_REGS_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_MQS_REGS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_MQS_REGS_Register_Masks AUDIO_LPCG_MQS_REGS Register Masks
 * @{
 */

/*! @name LPCG_LPCG_MQS_REGS_0 - na */
/*! @{ */
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_MASK (0x1U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_SHIFT (0U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_HWEN_MASK)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_2_2_MASK)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_regs_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_16_MASK (0x1FFF0U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_16_SHIFT (4U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_4_16_MASK)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_SHIFT (17U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_SWEN_MASK)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_18_18_MASK)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_MASK (0x80000U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_SHIFT (19U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_mqs_hmclk_STOP_MASK)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_MASK (0xFFF00000U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_SHIFT (20U)
#define AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_MQS_REGS_LPCG_LPCG_MQS_REGS_0_LPCG_lpcg_mqs_regs_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_MQS_REGS_Register_Masks */


/* AUDIO_LPCG_MQS_REGS - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_MQS_REGS base address */
#define AUDIO__LPCG_MQS_REGS_BASE                (0x59C50000u)
/** Peripheral AUDIO__LPCG_MQS_REGS base pointer */
#define AUDIO__LPCG_MQS_REGS                     ((AUDIO_LPCG_MQS_REGS_Type *)AUDIO__LPCG_MQS_REGS_BASE)
/** Array initializer of AUDIO_LPCG_MQS_REGS peripheral base addresses */
#define AUDIO_LPCG_MQS_REGS_BASE_ADDRS           { AUDIO__LPCG_MQS_REGS_BASE }
/** Array initializer of AUDIO_LPCG_MQS_REGS peripheral base pointers */
#define AUDIO_LPCG_MQS_REGS_BASE_PTRS            { AUDIO__LPCG_MQS_REGS }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_MQS_REGS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI0_Peripheral_Access_Layer AUDIO_LPCG_SAI0 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_SAI0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_SAI0_0;                  /**< na, offset: 0x0 */
} AUDIO_LPCG_SAI0_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI0_Register_Masks AUDIO_LPCG_SAI0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_SAI0_0 - na */
/*! @{ */
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_0_0_MASK)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_2_2_MASK)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_7_MASK (0xF0U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_7_SHIFT (4U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_4_7_MASK)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_MASK (0x100U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_SHIFT (8U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_SWEN_MASK (0x200U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_SWEN_SHIFT (9U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_10_10_MASK (0x400U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_10_10_SHIFT (10U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_10_10_MASK)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_STOP_MASK (0x800U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_STOP_SHIFT (11U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_12_16_MASK (0x1F000U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_12_16_SHIFT (12U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_12_16_MASK)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_SWEN_MASK)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_18_18_MASK)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_SHIFT (19U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_sai0_ipg_clk_sai_mclk_1_STOP_MASK)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_MASK (0xFFF00000U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_SHIFT (20U)
#define AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI0_LPCG_LPCG_SAI0_0_LPCG_lpcg_sai0_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI0_Register_Masks */


/* AUDIO_LPCG_SAI0 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_SAI0 base address */
#define AUDIO__LPCG_SAI0_BASE                    (0x59440000u)
/** Peripheral AUDIO__LPCG_SAI0 base pointer */
#define AUDIO__LPCG_SAI0                         ((AUDIO_LPCG_SAI0_Type *)AUDIO__LPCG_SAI0_BASE)
/** Array initializer of AUDIO_LPCG_SAI0 peripheral base addresses */
#define AUDIO_LPCG_SAI0_BASE_ADDRS               { AUDIO__LPCG_SAI0_BASE }
/** Array initializer of AUDIO_LPCG_SAI0 peripheral base pointers */
#define AUDIO_LPCG_SAI0_BASE_PTRS                { AUDIO__LPCG_SAI0 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI1_Peripheral_Access_Layer AUDIO_LPCG_SAI1 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_SAI1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_SAI1_0;                  /**< na, offset: 0x0 */
} AUDIO_LPCG_SAI1_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI1_Register_Masks AUDIO_LPCG_SAI1 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_SAI1_0 - na */
/*! @{ */
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_0_0_MASK)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_2_2_MASK)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_7_MASK (0xF0U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_7_SHIFT (4U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_4_7_MASK)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_MASK (0x100U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_SHIFT (8U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_SWEN_MASK (0x200U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_SWEN_SHIFT (9U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_10_10_MASK (0x400U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_10_10_SHIFT (10U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_10_10_MASK)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_STOP_MASK (0x800U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_STOP_SHIFT (11U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_12_16_MASK (0x1F000U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_12_16_SHIFT (12U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_12_16_MASK)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_SWEN_MASK)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_18_18_MASK)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_SHIFT (19U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_sai1_ipg_clk_sai_mclk_1_STOP_MASK)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_MASK (0xFFF00000U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_SHIFT (20U)
#define AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI1_LPCG_LPCG_SAI1_0_LPCG_lpcg_sai1_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI1_Register_Masks */


/* AUDIO_LPCG_SAI1 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_SAI1 base address */
#define AUDIO__LPCG_SAI1_BASE                    (0x59450000u)
/** Peripheral AUDIO__LPCG_SAI1 base pointer */
#define AUDIO__LPCG_SAI1                         ((AUDIO_LPCG_SAI1_Type *)AUDIO__LPCG_SAI1_BASE)
/** Array initializer of AUDIO_LPCG_SAI1 peripheral base addresses */
#define AUDIO_LPCG_SAI1_BASE_ADDRS               { AUDIO__LPCG_SAI1_BASE }
/** Array initializer of AUDIO_LPCG_SAI1 peripheral base pointers */
#define AUDIO_LPCG_SAI1_BASE_PTRS                { AUDIO__LPCG_SAI1 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI2_Peripheral_Access_Layer AUDIO_LPCG_SAI2 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_SAI2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_SAI2_0;                  /**< na, offset: 0x0 */
} AUDIO_LPCG_SAI2_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI2_Register_Masks AUDIO_LPCG_SAI2 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_SAI2_0 - na */
/*! @{ */
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_0_0_MASK)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_2_2_MASK)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_7_MASK (0xF0U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_7_SHIFT (4U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_4_7_MASK)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_MASK (0x100U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_SHIFT (8U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_SWEN_MASK (0x200U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_SWEN_SHIFT (9U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_10_10_MASK (0x400U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_10_10_SHIFT (10U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_10_10_MASK)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_STOP_MASK (0x800U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_STOP_SHIFT (11U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_12_16_MASK (0x1F000U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_12_16_SHIFT (12U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_12_16_MASK)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_SWEN_MASK)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_18_18_MASK)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_SHIFT (19U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_sai2_ipg_clk_sai_mclk_1_STOP_MASK)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_MASK (0xFFF00000U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_SHIFT (20U)
#define AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI2_LPCG_LPCG_SAI2_0_LPCG_lpcg_sai2_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI2_Register_Masks */


/* AUDIO_LPCG_SAI2 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_SAI2 base address */
#define AUDIO__LPCG_SAI2_BASE                    (0x59460000u)
/** Peripheral AUDIO__LPCG_SAI2 base pointer */
#define AUDIO__LPCG_SAI2                         ((AUDIO_LPCG_SAI2_Type *)AUDIO__LPCG_SAI2_BASE)
/** Array initializer of AUDIO_LPCG_SAI2 peripheral base addresses */
#define AUDIO_LPCG_SAI2_BASE_ADDRS               { AUDIO__LPCG_SAI2_BASE }
/** Array initializer of AUDIO_LPCG_SAI2 peripheral base pointers */
#define AUDIO_LPCG_SAI2_BASE_PTRS                { AUDIO__LPCG_SAI2 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI3_Peripheral_Access_Layer AUDIO_LPCG_SAI3 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_SAI3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_SAI3_0;                  /**< na, offset: 0x0 */
} AUDIO_LPCG_SAI3_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI3_Register_Masks AUDIO_LPCG_SAI3 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_SAI3_0 - na */
/*! @{ */
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_0_0_MASK)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_2_2_MASK)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_7_MASK (0xF0U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_7_SHIFT (4U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_4_7_MASK)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_MASK (0x100U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_SHIFT (8U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_SWEN_MASK (0x200U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_SWEN_SHIFT (9U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_10_10_MASK (0x400U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_10_10_SHIFT (10U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_10_10_MASK)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_STOP_MASK (0x800U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_STOP_SHIFT (11U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_12_16_MASK (0x1F000U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_12_16_SHIFT (12U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_12_16_MASK)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_SWEN_MASK)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_18_18_MASK)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_SHIFT (19U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_sai3_ipg_clk_sai_mclk_1_STOP_MASK)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_MASK (0xFFF00000U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_SHIFT (20U)
#define AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI3_LPCG_LPCG_SAI3_0_LPCG_lpcg_sai3_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI3_Register_Masks */


/* AUDIO_LPCG_SAI3 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_SAI3 base address */
#define AUDIO__LPCG_SAI3_BASE                    (0x59470000u)
/** Peripheral AUDIO__LPCG_SAI3 base pointer */
#define AUDIO__LPCG_SAI3                         ((AUDIO_LPCG_SAI3_Type *)AUDIO__LPCG_SAI3_BASE)
/** Array initializer of AUDIO_LPCG_SAI3 peripheral base addresses */
#define AUDIO_LPCG_SAI3_BASE_ADDRS               { AUDIO__LPCG_SAI3_BASE }
/** Array initializer of AUDIO_LPCG_SAI3 peripheral base pointers */
#define AUDIO_LPCG_SAI3_BASE_PTRS                { AUDIO__LPCG_SAI3 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI6 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI6_Peripheral_Access_Layer AUDIO_LPCG_SAI6 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_SAI6 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_SAI6_0;                  /**< na, offset: 0x0 */
} AUDIO_LPCG_SAI6_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI6 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI6_Register_Masks AUDIO_LPCG_SAI6 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_SAI6_0 - na */
/*! @{ */
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_0_0_MASK)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_2_2_MASK)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_4_7_MASK (0xF0U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_4_7_SHIFT (4U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_4_7_MASK)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_HWEN_MASK (0x100U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_HWEN_SHIFT (8U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_SWEN_MASK (0x200U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_SWEN_SHIFT (9U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_10_10_MASK (0x400U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_10_10_SHIFT (10U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_10_10_MASK)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_STOP_MASK (0x800U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_STOP_SHIFT (11U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_12_16_MASK (0x1F000U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_12_16_SHIFT (12U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_12_16_MASK)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_SWEN_MASK)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_18_18_MASK)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_STOP_SHIFT (19U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_sai6_ipg_clk_sai_mclk_1_STOP_MASK)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_20_31_MASK (0xFFF00000U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_20_31_SHIFT (20U)
#define AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI6_LPCG_LPCG_SAI6_0_LPCG_lpcg_sai6_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI6_Register_Masks */


/* AUDIO_LPCG_SAI6 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_SAI6 base address */
#define AUDIO__LPCG_SAI6_BASE                    (0x59C20000u)
/** Peripheral AUDIO__LPCG_SAI6 base pointer */
#define AUDIO__LPCG_SAI6                         ((AUDIO_LPCG_SAI6_Type *)AUDIO__LPCG_SAI6_BASE)
/** Array initializer of AUDIO_LPCG_SAI6 peripheral base addresses */
#define AUDIO_LPCG_SAI6_BASE_ADDRS               { AUDIO__LPCG_SAI6_BASE }
/** Array initializer of AUDIO_LPCG_SAI6 peripheral base pointers */
#define AUDIO_LPCG_SAI6_BASE_PTRS                { AUDIO__LPCG_SAI6 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI6_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI7 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI7_Peripheral_Access_Layer AUDIO_LPCG_SAI7 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_SAI7 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_SAI7_0;                  /**< na, offset: 0x0 */
} AUDIO_LPCG_SAI7_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI7 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI7_Register_Masks AUDIO_LPCG_SAI7 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_SAI7_0 - na */
/*! @{ */
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_0_0_MASK)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_2_2_MASK)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_4_7_MASK (0xF0U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_4_7_SHIFT (4U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_4_7_MASK)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_HWEN_MASK (0x100U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_HWEN_SHIFT (8U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_SWEN_MASK (0x200U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_SWEN_SHIFT (9U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_10_10_MASK (0x400U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_10_10_SHIFT (10U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_10_10_MASK)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_STOP_MASK (0x800U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_STOP_SHIFT (11U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_12_16_MASK (0x1F000U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_12_16_SHIFT (12U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_12_16_MASK)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_SWEN_MASK)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_18_18_MASK)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_STOP_SHIFT (19U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_sai7_ipg_clk_sai_mclk_1_STOP_MASK)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_20_31_MASK (0xFFF00000U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_20_31_SHIFT (20U)
#define AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI7_LPCG_LPCG_SAI7_0_LPCG_lpcg_sai7_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI7_Register_Masks */


/* AUDIO_LPCG_SAI7 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_SAI7 base address */
#define AUDIO__LPCG_SAI7_BASE                    (0x59C30000u)
/** Peripheral AUDIO__LPCG_SAI7 base pointer */
#define AUDIO__LPCG_SAI7                         ((AUDIO_LPCG_SAI7_Type *)AUDIO__LPCG_SAI7_BASE)
/** Array initializer of AUDIO_LPCG_SAI7 peripheral base addresses */
#define AUDIO_LPCG_SAI7_BASE_ADDRS               { AUDIO__LPCG_SAI7_BASE }
/** Array initializer of AUDIO_LPCG_SAI7 peripheral base pointers */
#define AUDIO_LPCG_SAI7_BASE_PTRS                { AUDIO__LPCG_SAI7 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI7_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI_HDMIRX0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI_HDMIRX0_Peripheral_Access_Layer AUDIO_LPCG_SAI_HDMIRX0 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_SAI_HDMIRX0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_SAI_HDMIRX0_0;           /**< na, offset: 0x0 */
} AUDIO_LPCG_SAI_HDMIRX0_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI_HDMIRX0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI_HDMIRX0_Register_Masks AUDIO_LPCG_SAI_HDMIRX0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_SAI_HDMIRX0_0 - na */
/*! @{ */
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_0_0_MASK)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_2_2_MASK)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_4_7_MASK (0xF0U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_4_7_SHIFT (4U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_4_7_MASK)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_HWEN_MASK (0x100U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_HWEN_SHIFT (8U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_SWEN_MASK (0x200U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_SWEN_SHIFT (9U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_10_10_MASK (0x400U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_10_10_SHIFT (10U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_10_10_MASK)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_STOP_MASK (0x800U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_STOP_SHIFT (11U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_12_16_MASK (0x1F000U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_12_16_SHIFT (12U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_12_16_MASK)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_SWEN_MASK)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_18_18_MASK)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_STOP_SHIFT (19U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_sai_hdmirx0_ipg_clk_sai_mclk_1_STOP_MASK)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_20_31_MASK (0xFFF00000U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_20_31_SHIFT (20U)
#define AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI_HDMIRX0_LPCG_LPCG_SAI_HDMIRX0_0_LPCG_lpcg_sai_hdmirx0_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI_HDMIRX0_Register_Masks */


/* AUDIO_LPCG_SAI_HDMIRX0 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_SAI_HDMIRX0 base address */
#define AUDIO__LPCG_SAI_HDMIRX0_BASE             (0x59480000u)
/** Peripheral AUDIO__LPCG_SAI_HDMIRX0 base pointer */
#define AUDIO__LPCG_SAI_HDMIRX0                  ((AUDIO_LPCG_SAI_HDMIRX0_Type *)AUDIO__LPCG_SAI_HDMIRX0_BASE)
/** Array initializer of AUDIO_LPCG_SAI_HDMIRX0 peripheral base addresses */
#define AUDIO_LPCG_SAI_HDMIRX0_BASE_ADDRS        { AUDIO__LPCG_SAI_HDMIRX0_BASE }
/** Array initializer of AUDIO_LPCG_SAI_HDMIRX0 peripheral base pointers */
#define AUDIO_LPCG_SAI_HDMIRX0_BASE_PTRS         { AUDIO__LPCG_SAI_HDMIRX0 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI_HDMIRX0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI_HDMITX0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI_HDMITX0_Peripheral_Access_Layer AUDIO_LPCG_SAI_HDMITX0 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_SAI_HDMITX0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_SAI_HDMITX0_0;           /**< na, offset: 0x0 */
} AUDIO_LPCG_SAI_HDMITX0_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SAI_HDMITX0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SAI_HDMITX0_Register_Masks AUDIO_LPCG_SAI_HDMITX0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_SAI_HDMITX0_0 - na */
/*! @{ */
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_0_0_MASK (0x1U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_0_0_SHIFT (0U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_0_0_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_0_0_MASK)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_SWEN_MASK (0x2U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_SWEN_SHIFT (1U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_SWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_SWEN_MASK)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_2_2_MASK)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_STOP_MASK (0x8U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_STOP_SHIFT (3U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_STOP_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_STOP_MASK)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_4_7_MASK (0xF0U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_4_7_SHIFT (4U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_4_7(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_4_7_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_4_7_MASK)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_HWEN_MASK (0x100U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_HWEN_SHIFT (8U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_SWEN_MASK (0x200U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_SWEN_SHIFT (9U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_10_10_MASK (0x400U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_10_10_SHIFT (10U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_10_10_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_10_10_MASK)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_STOP_MASK (0x800U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_STOP_SHIFT (11U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_12_16_MASK (0x1F000U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_12_16_SHIFT (12U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_12_16_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_12_16_MASK)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_SWEN_SHIFT (17U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_SWEN_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_SWEN_MASK)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_18_18_MASK)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_STOP_MASK (0x80000U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_STOP_SHIFT (19U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_STOP_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_sai_hdmitx0_ipg_clk_sai_mclk_1_STOP_MASK)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_20_31_MASK (0xFFF00000U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_20_31_SHIFT (20U)
#define AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_20_31_SHIFT)) & AUDIO_LPCG_SAI_HDMITX0_LPCG_LPCG_SAI_HDMITX0_0_LPCG_lpcg_sai_hdmitx0_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI_HDMITX0_Register_Masks */


/* AUDIO_LPCG_SAI_HDMITX0 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_SAI_HDMITX0 base address */
#define AUDIO__LPCG_SAI_HDMITX0_BASE             (0x59490000u)
/** Peripheral AUDIO__LPCG_SAI_HDMITX0 base pointer */
#define AUDIO__LPCG_SAI_HDMITX0                  ((AUDIO_LPCG_SAI_HDMITX0_Type *)AUDIO__LPCG_SAI_HDMITX0_BASE)
/** Array initializer of AUDIO_LPCG_SAI_HDMITX0 peripheral base addresses */
#define AUDIO_LPCG_SAI_HDMITX0_BASE_ADDRS        { AUDIO__LPCG_SAI_HDMITX0_BASE }
/** Array initializer of AUDIO_LPCG_SAI_HDMITX0 peripheral base pointers */
#define AUDIO_LPCG_SAI_HDMITX0_BASE_PTRS         { AUDIO__LPCG_SAI_HDMITX0 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_SAI_HDMITX0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SPDIF0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SPDIF0_Peripheral_Access_Layer AUDIO_LPCG_SPDIF0 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_SPDIF0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_SPDIF0_0;                /**< na, offset: 0x0 */
} AUDIO_LPCG_SPDIF0_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SPDIF0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SPDIF0_Register_Masks AUDIO_LPCG_SPDIF0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_SPDIF0_0 - na */
/*! @{ */
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_MASK (0x1U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_SHIFT (0U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_MASK (0x2U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_SHIFT (1U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_2_2_MASK)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_MASK (0x8U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_SHIFT (3U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_16_MASK (0x1FFF0U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_16_SHIFT (4U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_4_16_MASK)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_SWEN_SHIFT (17U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_SWEN_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_SWEN_MASK)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_18_18_MASK)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_STOP_MASK (0x80000U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_STOP_SHIFT (19U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_STOP_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_gclkw_t0_STOP_MASK)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_20_MASK (0x100000U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_20_SHIFT (20U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_20_20_MASK)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_MASK (0x200000U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_SHIFT (21U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_SWEN_MASK)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_22_22_MASK (0x400000U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_22_22_SHIFT (22U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_22_22_MASK)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_MASK (0x800000U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_SHIFT (23U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_spdif0_tx_clk_STOP_MASK)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_24_31_MASK (0xFF000000U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_24_31_SHIFT (24U)
#define AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_SPDIF0_LPCG_LPCG_SPDIF0_0_LPCG_lpcg_spdif0_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_SPDIF0_Register_Masks */


/* AUDIO_LPCG_SPDIF0 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_SPDIF0 base address */
#define AUDIO__LPCG_SPDIF0_BASE                  (0x59420000u)
/** Peripheral AUDIO__LPCG_SPDIF0 base pointer */
#define AUDIO__LPCG_SPDIF0                       ((AUDIO_LPCG_SPDIF0_Type *)AUDIO__LPCG_SPDIF0_BASE)
/** Array initializer of AUDIO_LPCG_SPDIF0 peripheral base addresses */
#define AUDIO_LPCG_SPDIF0_BASE_ADDRS             { AUDIO__LPCG_SPDIF0_BASE }
/** Array initializer of AUDIO_LPCG_SPDIF0 peripheral base pointers */
#define AUDIO_LPCG_SPDIF0_BASE_PTRS              { AUDIO__LPCG_SPDIF0 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_SPDIF0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SPDIF1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SPDIF1_Peripheral_Access_Layer AUDIO_LPCG_SPDIF1 Peripheral Access Layer
 * @{
 */

/** AUDIO_LPCG_SPDIF1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_SPDIF1_0;                /**< na, offset: 0x0 */
} AUDIO_LPCG_SPDIF1_Type;

/* ----------------------------------------------------------------------------
   -- AUDIO_LPCG_SPDIF1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AUDIO_LPCG_SPDIF1_Register_Masks AUDIO_LPCG_SPDIF1 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_SPDIF1_0 - na */
/*! @{ */
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_HWEN_MASK (0x1U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_HWEN_SHIFT (0U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_HWEN_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_HWEN_MASK)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_SWEN_MASK (0x2U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_SWEN_SHIFT (1U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_SWEN_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_SWEN_MASK)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_2_2_MASK (0x4U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_2_2_SHIFT (2U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_2_2_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_2_2_MASK)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_STOP_MASK (0x8U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_STOP_SHIFT (3U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_STOP_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_ipg_clk_s_STOP_MASK)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_4_16_MASK (0x1FFF0U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_4_16_SHIFT (4U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_4_16_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_4_16_MASK)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_SWEN_MASK (0x20000U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_SWEN_SHIFT (17U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_SWEN_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_SWEN_MASK)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_18_18_MASK (0x40000U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_18_18_SHIFT (18U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_18_18_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_18_18_MASK)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_STOP_MASK (0x80000U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_STOP_SHIFT (19U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_STOP_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_gclkw_t0_STOP_MASK)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_20_20_MASK (0x100000U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_20_20_SHIFT (20U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_20_20_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_20_20_MASK)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_SWEN_MASK (0x200000U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_SWEN_SHIFT (21U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_SWEN_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_SWEN_MASK)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_22_22_MASK (0x400000U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_22_22_SHIFT (22U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_22_22_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_22_22_MASK)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_STOP_MASK (0x800000U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_STOP_SHIFT (23U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_STOP_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_spdif1_tx_clk_STOP_MASK)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_24_31_MASK (0xFF000000U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_24_31_SHIFT (24U)
#define AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_24_31_SHIFT)) & AUDIO_LPCG_SPDIF1_LPCG_LPCG_SPDIF1_0_LPCG_lpcg_spdif1_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AUDIO_LPCG_SPDIF1_Register_Masks */


/* AUDIO_LPCG_SPDIF1 - Peripheral instance base addresses */
/** Peripheral AUDIO__LPCG_SPDIF1 base address */
#define AUDIO__LPCG_SPDIF1_BASE                  (0x59430000u)
/** Peripheral AUDIO__LPCG_SPDIF1 base pointer */
#define AUDIO__LPCG_SPDIF1                       ((AUDIO_LPCG_SPDIF1_Type *)AUDIO__LPCG_SPDIF1_BASE)
/** Array initializer of AUDIO_LPCG_SPDIF1 peripheral base addresses */
#define AUDIO_LPCG_SPDIF1_BASE_ADDRS             { AUDIO__LPCG_SPDIF1_BASE }
/** Array initializer of AUDIO_LPCG_SPDIF1 peripheral base pointers */
#define AUDIO_LPCG_SPDIF1_BASE_PTRS              { AUDIO__LPCG_SPDIF1 }

/*!
 * @}
 */ /* end of group AUDIO_LPCG_SPDIF1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- BCH Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
 * @{
 */

/** BCH - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0 */
    __IO uint32_t RW;                                /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
    __IO uint32_t SET;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
    __IO uint32_t CLR;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
    __IO uint32_t TOG;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
  } CTRL;
  struct {                                         /* offset: 0x10 */
    __I  uint32_t RW;                                /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
    __I  uint32_t SET;                               /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */
    __I  uint32_t CLR;                               /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */
    __I  uint32_t TOG;                               /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */
  } STATUS0;
  struct {                                         /* offset: 0x20 */
    __IO uint32_t RW;                                /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
    __IO uint32_t SET;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */
    __IO uint32_t CLR;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */
    __IO uint32_t TOG;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */
  } MODE;
  struct {                                         /* offset: 0x30 */
    __IO uint32_t RW;                                /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
    __IO uint32_t SET;                               /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */
    __IO uint32_t CLR;                               /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */
    __IO uint32_t TOG;                               /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */
  } ENCODEPTR;
  struct {                                         /* offset: 0x40 */
    __IO uint32_t RW;                                /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
    __IO uint32_t SET;                               /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */
    __IO uint32_t CLR;                               /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */
    __IO uint32_t TOG;                               /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */
  } DATAPTR;
  struct {                                         /* offset: 0x50 */
    __IO uint32_t RW;                                /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
    __IO uint32_t SET;                               /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */
    __IO uint32_t CLR;                               /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */
    __IO uint32_t TOG;                               /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */
  } METAPTR;
       uint8_t RESERVED_0[16];
  struct {                                         /* offset: 0x70 */
    __IO uint32_t RW;                                /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
    __IO uint32_t SET;                               /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */
    __IO uint32_t CLR;                               /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */
    __IO uint32_t TOG;                               /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */
  } LAYOUTSELECT;
  struct {                                         /* offset: 0x80 */
    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */
    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */
    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */
  } FLASH0LAYOUT0;
  struct {                                         /* offset: 0x90 */
    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */
    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */
    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */
  } FLASH0LAYOUT1;
  struct {                                         /* offset: 0xA0 */
    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */
    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */
    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */
  } FLASH1LAYOUT0;
  struct {                                         /* offset: 0xB0 */
    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */
    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */
    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */
  } FLASH1LAYOUT1;
  struct {                                         /* offset: 0xC0 */
    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */
    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */
    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */
  } FLASH2LAYOUT0;
  struct {                                         /* offset: 0xD0 */
    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */
    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */
    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */
  } FLASH2LAYOUT1;
  struct {                                         /* offset: 0xE0 */
    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */
    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */
    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */
  } FLASH3LAYOUT0;
  struct {                                         /* offset: 0xF0 */
    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */
    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */
    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */
  } FLASH3LAYOUT1;
  struct {                                         /* offset: 0x100 */
    __IO uint32_t RW;                                /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
    __IO uint32_t SET;                               /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
    __IO uint32_t CLR;                               /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
    __IO uint32_t TOG;                               /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
  } DEBUG0;
  struct {                                         /* offset: 0x110 */
    __I  uint32_t RW;                                /**< KES Debug Read Register, offset: 0x110 */
    __I  uint32_t SET;                               /**< KES Debug Read Register, offset: 0x114 */
    __I  uint32_t CLR;                               /**< KES Debug Read Register, offset: 0x118 */
    __I  uint32_t TOG;                               /**< KES Debug Read Register, offset: 0x11C */
  } DBGKESREAD;
  struct {                                         /* offset: 0x120 */
    __I  uint32_t RW;                                /**< Chien Search Debug Read Register, offset: 0x120 */
    __I  uint32_t SET;                               /**< Chien Search Debug Read Register, offset: 0x124 */
    __I  uint32_t CLR;                               /**< Chien Search Debug Read Register, offset: 0x128 */
    __I  uint32_t TOG;                               /**< Chien Search Debug Read Register, offset: 0x12C */
  } DBGCSFEREAD;
  struct {                                         /* offset: 0x130 */
    __I  uint32_t RW;                                /**< Syndrome Generator Debug Read Register, offset: 0x130 */
    __I  uint32_t SET;                               /**< Syndrome Generator Debug Read Register, offset: 0x134 */
    __I  uint32_t CLR;                               /**< Syndrome Generator Debug Read Register, offset: 0x138 */
    __I  uint32_t TOG;                               /**< Syndrome Generator Debug Read Register, offset: 0x13C */
  } DBGSYNDGENREAD;
  struct {                                         /* offset: 0x140 */
    __I  uint32_t RW;                                /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
    __I  uint32_t SET;                               /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */
    __I  uint32_t CLR;                               /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */
    __I  uint32_t TOG;                               /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */
  } DBGAHBMREAD;
  struct {                                         /* offset: 0x150 */
    __I  uint32_t RW;                                /**< Block Name Register, offset: 0x150 */
    __I  uint32_t SET;                               /**< Block Name Register, offset: 0x154 */
    __I  uint32_t CLR;                               /**< Block Name Register, offset: 0x158 */
    __I  uint32_t TOG;                               /**< Block Name Register, offset: 0x15C */
  } BLOCKNAME;
  struct {                                         /* offset: 0x160 */
    __I  uint32_t RW;                                /**< BCH Version Register, offset: 0x160 */
    __I  uint32_t SET;                               /**< BCH Version Register, offset: 0x164 */
    __I  uint32_t CLR;                               /**< BCH Version Register, offset: 0x168 */
    __I  uint32_t TOG;                               /**< BCH Version Register, offset: 0x16C */
  } VERSION;
  struct {                                         /* offset: 0x170 */
    __IO uint32_t RW;                                /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
    __IO uint32_t SET;                               /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */
    __IO uint32_t CLR;                               /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */
    __IO uint32_t TOG;                               /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */
  } DEBUG1;
} BCH_Type;

/* ----------------------------------------------------------------------------
   -- BCH Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup BCH_Register_Masks BCH Register Masks
 * @{
 */

/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
/*! @{ */
#define BCH_CTRL_COMPLETE_IRQ_MASK               (0x1U)
#define BCH_CTRL_COMPLETE_IRQ_SHIFT              (0U)
#define BCH_CTRL_COMPLETE_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
#define BCH_CTRL_RSVD0_MASK                      (0x2U)
#define BCH_CTRL_RSVD0_SHIFT                     (1U)
#define BCH_CTRL_RSVD0(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
#define BCH_CTRL_DEBUG_STALL_IRQ_MASK            (0x4U)
#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT           (2U)
#define BCH_CTRL_DEBUG_STALL_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
#define BCH_CTRL_BM_ERROR_IRQ_MASK               (0x8U)
#define BCH_CTRL_BM_ERROR_IRQ_SHIFT              (3U)
#define BCH_CTRL_BM_ERROR_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
#define BCH_CTRL_RSVD1_MASK                      (0xF0U)
#define BCH_CTRL_RSVD1_SHIFT                     (4U)
#define BCH_CTRL_RSVD1(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
#define BCH_CTRL_COMPLETE_IRQ_EN_MASK            (0x100U)
#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT           (8U)
#define BCH_CTRL_COMPLETE_IRQ_EN(x)              (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
#define BCH_CTRL_RSVD2_MASK                      (0x200U)
#define BCH_CTRL_RSVD2_SHIFT                     (9U)
#define BCH_CTRL_RSVD2(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK         (0x400U)
#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT        (10U)
#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
#define BCH_CTRL_RSVD3_MASK                      (0xF800U)
#define BCH_CTRL_RSVD3_SHIFT                     (11U)
#define BCH_CTRL_RSVD3(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
#define BCH_CTRL_M2M_ENABLE_MASK                 (0x10000U)
#define BCH_CTRL_M2M_ENABLE_SHIFT                (16U)
#define BCH_CTRL_M2M_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
#define BCH_CTRL_M2M_ENCODE_MASK                 (0x20000U)
#define BCH_CTRL_M2M_ENCODE_SHIFT                (17U)
#define BCH_CTRL_M2M_ENCODE(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
#define BCH_CTRL_M2M_LAYOUT_MASK                 (0xC0000U)
#define BCH_CTRL_M2M_LAYOUT_SHIFT                (18U)
#define BCH_CTRL_M2M_LAYOUT(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
#define BCH_CTRL_RSVD4_MASK                      (0x300000U)
#define BCH_CTRL_RSVD4_SHIFT                     (20U)
#define BCH_CTRL_RSVD4(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
#define BCH_CTRL_DEBUGSYNDROME_MASK              (0x400000U)
#define BCH_CTRL_DEBUGSYNDROME_SHIFT             (22U)
#define BCH_CTRL_DEBUGSYNDROME(x)                (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
#define BCH_CTRL_RSVD5_MASK                      (0x3F800000U)
#define BCH_CTRL_RSVD5_SHIFT                     (23U)
#define BCH_CTRL_RSVD5(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
#define BCH_CTRL_CLKGATE_MASK                    (0x40000000U)
#define BCH_CTRL_CLKGATE_SHIFT                   (30U)
/*! CLKGATE - CLKGATE
 *  0b0..Allow BCH to operate normally.
 *  0b1..Do not clock BCH gates in order to minimize power consumption.
 */
#define BCH_CTRL_CLKGATE(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
#define BCH_CTRL_SFTRST_MASK                     (0x80000000U)
#define BCH_CTRL_SFTRST_SHIFT                    (31U)
/*! SFTRST - SFTRST
 *  0b0..Allow BCH to operate normally.
 *  0b1..Hold BCH in reset.
 */
#define BCH_CTRL_SFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
/*! @} */

/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
/*! @{ */
#define BCH_STATUS0_RSVD0_MASK                   (0x3U)
#define BCH_STATUS0_RSVD0_SHIFT                  (0U)
#define BCH_STATUS0_RSVD0(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
#define BCH_STATUS0_UNCORRECTABLE_MASK           (0x4U)
#define BCH_STATUS0_UNCORRECTABLE_SHIFT          (2U)
#define BCH_STATUS0_UNCORRECTABLE(x)             (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
#define BCH_STATUS0_CORRECTED_MASK               (0x8U)
#define BCH_STATUS0_CORRECTED_SHIFT              (3U)
#define BCH_STATUS0_CORRECTED(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
#define BCH_STATUS0_ALLONES_MASK                 (0x10U)
#define BCH_STATUS0_ALLONES_SHIFT                (4U)
#define BCH_STATUS0_ALLONES(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
#define BCH_STATUS0_RSVD1_MASK                   (0xE0U)
#define BCH_STATUS0_RSVD1_SHIFT                  (5U)
#define BCH_STATUS0_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
#define BCH_STATUS0_STATUS_BLK0_MASK             (0xFF00U)
#define BCH_STATUS0_STATUS_BLK0_SHIFT            (8U)
/*! STATUS_BLK0 - STATUS_BLK0
 *  0b00000000..No errors found on block.
 *  0b00000001..One error found on block.
 *  0b00000010..One errors found on block.
 *  0b00000011..One errors found on block.
 *  0b00000100..One errors found on block.
 *  0b11111110..Block exhibited uncorrectable errors.
 *  0b11111111..Page is erased.
 */
#define BCH_STATUS0_STATUS_BLK0(x)               (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
#define BCH_STATUS0_COMPLETED_CE_MASK            (0xF0000U)
#define BCH_STATUS0_COMPLETED_CE_SHIFT           (16U)
#define BCH_STATUS0_COMPLETED_CE(x)              (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
#define BCH_STATUS0_HANDLE_MASK                  (0xFFF00000U)
#define BCH_STATUS0_HANDLE_SHIFT                 (20U)
#define BCH_STATUS0_HANDLE(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
/*! @} */

/*! @name MODE - Hardware ECC Accelerator Mode Register */
/*! @{ */
#define BCH_MODE_ERASE_THRESHOLD_MASK            (0xFFU)
#define BCH_MODE_ERASE_THRESHOLD_SHIFT           (0U)
#define BCH_MODE_ERASE_THRESHOLD(x)              (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
#define BCH_MODE_RSVD_MASK                       (0xFFFFFF00U)
#define BCH_MODE_RSVD_SHIFT                      (8U)
#define BCH_MODE_RSVD(x)                         (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
/*! @} */

/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
/*! @{ */
#define BCH_ENCODEPTR_ADDR_MASK                  (0xFFFFFFFFU)
#define BCH_ENCODEPTR_ADDR_SHIFT                 (0U)
#define BCH_ENCODEPTR_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
/*! @} */

/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
/*! @{ */
#define BCH_DATAPTR_ADDR_MASK                    (0xFFFFFFFFU)
#define BCH_DATAPTR_ADDR_SHIFT                   (0U)
#define BCH_DATAPTR_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
/*! @} */

/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
/*! @{ */
#define BCH_METAPTR_ADDR_MASK                    (0xFFFFFFFFU)
#define BCH_METAPTR_ADDR_SHIFT                   (0U)
#define BCH_METAPTR_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
/*! @} */

/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
/*! @{ */
#define BCH_LAYOUTSELECT_CS0_SELECT_MASK         (0x3U)
#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT        (0U)
#define BCH_LAYOUTSELECT_CS0_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS1_SELECT_MASK         (0xCU)
#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT        (2U)
#define BCH_LAYOUTSELECT_CS1_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS2_SELECT_MASK         (0x30U)
#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT        (4U)
#define BCH_LAYOUTSELECT_CS2_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS3_SELECT_MASK         (0xC0U)
#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT        (6U)
#define BCH_LAYOUTSELECT_CS3_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS4_SELECT_MASK         (0x300U)
#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT        (8U)
#define BCH_LAYOUTSELECT_CS4_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS5_SELECT_MASK         (0xC00U)
#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT        (10U)
#define BCH_LAYOUTSELECT_CS5_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS6_SELECT_MASK         (0x3000U)
#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT        (12U)
#define BCH_LAYOUTSELECT_CS6_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS7_SELECT_MASK         (0xC000U)
#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT        (14U)
#define BCH_LAYOUTSELECT_CS7_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS8_SELECT_MASK         (0x30000U)
#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT        (16U)
#define BCH_LAYOUTSELECT_CS8_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS9_SELECT_MASK         (0xC0000U)
#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT        (18U)
#define BCH_LAYOUTSELECT_CS9_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS10_SELECT_MASK        (0x300000U)
#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT       (20U)
#define BCH_LAYOUTSELECT_CS10_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS11_SELECT_MASK        (0xC00000U)
#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT       (22U)
#define BCH_LAYOUTSELECT_CS11_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS12_SELECT_MASK        (0x3000000U)
#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT       (24U)
#define BCH_LAYOUTSELECT_CS12_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS13_SELECT_MASK        (0xC000000U)
#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT       (26U)
#define BCH_LAYOUTSELECT_CS13_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS14_SELECT_MASK        (0x30000000U)
#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT       (28U)
#define BCH_LAYOUTSELECT_CS14_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS15_SELECT_MASK        (0xC0000000U)
#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT       (30U)
#define BCH_LAYOUTSELECT_CS15_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
/*! @} */

/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
/*! @{ */
#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK        (0xFFFU)
#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT       (0U)
#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
#define BCH_FLASH0LAYOUT0_ECC0_MASK              (0xF000U)
#define BCH_FLASH0LAYOUT0_ECC0_SHIFT             (12U)
/*! ECC0 - ECC0
 *  0b0000..No ECC to be performed
 *  0b0001..ECC 2 to be performed
 *  0b0010..ECC 4 to be performed
 *  0b0011..ECC 6 to be performed
 *  0b0100..ECC 8 to be performed
 *  0b0101..ECC 10 to be performed
 *  0b0110..ECC 12 to be performed
 *  0b0111..ECC 14 to be performed
 *  0b1000..ECC 16 to be performed
 *  0b1001..ECC 18 to be performed
 *  0b1010..ECC 20 to be performed
 */
#define BCH_FLASH0LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
#define BCH_FLASH0LAYOUT0_META_SIZE_MASK         (0xFF0000U)
#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT        (16U)
#define BCH_FLASH0LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT          (24U)
#define BCH_FLASH0LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
/*! @} */

/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
/*! @{ */
#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK        (0xFFFU)
#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT       (0U)
#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
#define BCH_FLASH0LAYOUT1_ECCN_MASK              (0xF000U)
#define BCH_FLASH0LAYOUT1_ECCN_SHIFT             (12U)
/*! ECCN - ECCN
 *  0b0000..No ECC to be performed
 *  0b0001..ECC 2 to be performed
 *  0b0010..ECC 4 to be performed
 *  0b0011..ECC 6 to be performed
 *  0b0100..ECC 8 to be performed
 *  0b0101..ECC 10 to be performed
 *  0b0110..ECC 12 to be performed
 *  0b0111..ECC 14 to be performed
 *  0b1000..ECC 16 to be performed
 *  0b1001..ECC 18 to be performed
 *  0b1010..ECC 20 to be performed
 */
#define BCH_FLASH0LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT        (16U)
#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
/*! @} */

/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
/*! @{ */
#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK        (0xFFFU)
#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT       (0U)
#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
#define BCH_FLASH1LAYOUT0_ECC0_MASK              (0xF000U)
#define BCH_FLASH1LAYOUT0_ECC0_SHIFT             (12U)
/*! ECC0 - ECC0
 *  0b0000..No ECC to be performed
 *  0b0001..ECC 2 to be performed
 *  0b0010..ECC 4 to be performed
 *  0b0011..ECC 6 to be performed
 *  0b0100..ECC 8 to be performed
 *  0b0101..ECC 10 to be performed
 *  0b0110..ECC 12 to be performed
 *  0b0111..ECC 14 to be performed
 *  0b1000..ECC 16 to be performed
 *  0b1001..ECC 18 to be performed
 *  0b1010..ECC 20 to be performed
 */
#define BCH_FLASH1LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
#define BCH_FLASH1LAYOUT0_META_SIZE_MASK         (0xFF0000U)
#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT        (16U)
#define BCH_FLASH1LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT          (24U)
#define BCH_FLASH1LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
/*! @} */

/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
/*! @{ */
#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK        (0xFFFU)
#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT       (0U)
#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
#define BCH_FLASH1LAYOUT1_ECCN_MASK              (0xF000U)
#define BCH_FLASH1LAYOUT1_ECCN_SHIFT             (12U)
/*! ECCN - ECCN
 *  0b0000..No ECC to be performed
 *  0b0001..ECC 2 to be performed
 *  0b0010..ECC 4 to be performed
 *  0b0011..ECC 6 to be performed
 *  0b0100..ECC 8 to be performed
 *  0b0101..ECC 10 to be performed
 *  0b0110..ECC 12 to be performed
 *  0b0111..ECC 14 to be performed
 *  0b1000..ECC 16 to be performed
 *  0b1001..ECC 18 to be performed
 *  0b1010..ECC 20 to be performed
 */
#define BCH_FLASH1LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT        (16U)
#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
/*! @} */

/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
/*! @{ */
#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK        (0xFFFU)
#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT       (0U)
#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
#define BCH_FLASH2LAYOUT0_ECC0_MASK              (0xF000U)
#define BCH_FLASH2LAYOUT0_ECC0_SHIFT             (12U)
/*! ECC0 - ECC0
 *  0b0000..No ECC to be performed
 *  0b0001..ECC 2 to be performed
 *  0b0010..ECC 4 to be performed
 *  0b0011..ECC 6 to be performed
 *  0b0100..ECC 8 to be performed
 *  0b0101..ECC 10 to be performed
 *  0b0110..ECC 12 to be performed
 *  0b0111..ECC 14 to be performed
 *  0b1000..ECC 16 to be performed
 *  0b1001..ECC 18 to be performed
 *  0b1010..ECC 20 to be performed
 */
#define BCH_FLASH2LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
#define BCH_FLASH2LAYOUT0_META_SIZE_MASK         (0xFF0000U)
#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT        (16U)
#define BCH_FLASH2LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT          (24U)
#define BCH_FLASH2LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
/*! @} */

/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
/*! @{ */
#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK        (0xFFFU)
#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT       (0U)
#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
#define BCH_FLASH2LAYOUT1_ECCN_MASK              (0xF000U)
#define BCH_FLASH2LAYOUT1_ECCN_SHIFT             (12U)
/*! ECCN - ECCN
 *  0b0000..No ECC to be performed
 *  0b0001..ECC 2 to be performed
 *  0b0010..ECC 4 to be performed
 *  0b0011..ECC 6 to be performed
 *  0b0100..ECC 8 to be performed
 *  0b0101..ECC 10 to be performed
 *  0b0110..ECC 12 to be performed
 *  0b0111..ECC 14 to be performed
 *  0b1000..ECC 16 to be performed
 *  0b1001..ECC 18 to be performed
 *  0b1010..ECC 20 to be performed
 */
#define BCH_FLASH2LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT        (16U)
#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
/*! @} */

/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
/*! @{ */
#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK        (0xFFFU)
#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT       (0U)
#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
#define BCH_FLASH3LAYOUT0_ECC0_MASK              (0xF000U)
#define BCH_FLASH3LAYOUT0_ECC0_SHIFT             (12U)
/*! ECC0 - ECC0
 *  0b0000..No ECC to be performed
 *  0b0001..ECC 2 to be performed
 *  0b0010..ECC 4 to be performed
 *  0b0011..ECC 6 to be performed
 *  0b0100..ECC 8 to be performed
 *  0b0101..ECC 10 to be performed
 *  0b0110..ECC 12 to be performed
 *  0b0111..ECC 14 to be performed
 *  0b1000..ECC 16 to be performed
 *  0b1001..ECC 18 to be performed
 *  0b1010..ECC 20 to be performed
 */
#define BCH_FLASH3LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
#define BCH_FLASH3LAYOUT0_META_SIZE_MASK         (0xFF0000U)
#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT        (16U)
#define BCH_FLASH3LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT          (24U)
#define BCH_FLASH3LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
/*! @} */

/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
/*! @{ */
#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK        (0xFFFU)
#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT       (0U)
#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
#define BCH_FLASH3LAYOUT1_ECCN_MASK              (0xF000U)
#define BCH_FLASH3LAYOUT1_ECCN_SHIFT             (12U)
/*! ECCN - ECCN
 *  0b0000..No ECC to be performed
 *  0b0001..ECC 2 to be performed
 *  0b0010..ECC 4 to be performed
 *  0b0011..ECC 6 to be performed
 *  0b0100..ECC 8 to be performed
 *  0b0101..ECC 10 to be performed
 *  0b0110..ECC 12 to be performed
 *  0b0111..ECC 14 to be performed
 *  0b1000..ECC 16 to be performed
 *  0b1001..ECC 18 to be performed
 *  0b1010..ECC 20 to be performed
 */
#define BCH_FLASH3LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT        (16U)
#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
/*! @} */

/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
/*! @{ */
#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK         (0x3FU)
#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT        (0U)
#define BCH_DEBUG0_DEBUG_REG_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
#define BCH_DEBUG0_RSVD0_MASK                    (0xC0U)
#define BCH_DEBUG0_RSVD0_SHIFT                   (6U)
#define BCH_DEBUG0_RSVD0(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK)
#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK       (0x100U)
#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT      (8U)
/*! BM_KES_TEST_BYPASS - BM_KES_TEST_BYPASS
 *  0b0..Bus master address generator for SYND_GEN writes operates normally.
 *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
 */
#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK)
#define BCH_DEBUG0_KES_DEBUG_STALL_MASK          (0x200U)
#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT         (9U)
/*! KES_DEBUG_STALL - KES_DEBUG_STALL
 *  0b0..KES FSM proceeds to next block supplied by bus master.
 *  0b1..KES FSM waits after current equations are solved and the search engine is started.
 */
#define BCH_DEBUG0_KES_DEBUG_STALL(x)            (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK)
#define BCH_DEBUG0_KES_DEBUG_STEP_MASK           (0x400U)
#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT          (10U)
#define BCH_DEBUG0_KES_DEBUG_STEP(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK)
#define BCH_DEBUG0_KES_STANDALONE_MASK           (0x800U)
#define BCH_DEBUG0_KES_STANDALONE_SHIFT          (11U)
/*! KES_STANDALONE - KES_STANDALONE
 *  0b0..Bus master address generator for SYND_GEN writes operates normally.
 *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
 */
#define BCH_DEBUG0_KES_STANDALONE(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK)
#define BCH_DEBUG0_KES_DEBUG_KICK_MASK           (0x1000U)
#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT          (12U)
#define BCH_DEBUG0_KES_DEBUG_KICK(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK)
#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK         (0x2000U)
#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT        (13U)
/*! KES_DEBUG_MODE4K - KES_DEBUG_MODE4K
 *  0b1..Mode is set for 4K NAND pages.
 *  0b1..Mode is set for 2K NAND pages.
 */
#define BCH_DEBUG0_KES_DEBUG_MODE4K(x)           (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK)
#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK   (0x4000U)
#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT  (14U)
/*! KES_DEBUG_PAYLOAD_FLAG - KES_DEBUG_PAYLOAD_FLAG
 *  0b1..Payload is set for 512 bytes data block.
 *  0b1..Payload is set for 65 or 19 bytes auxiliary block.
 */
#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x)     (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK)
#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK     (0x8000U)
#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT    (15U)
#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK)
#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
/*! KES_DEBUG_SYNDROME_SYMBOL - KES_DEBUG_SYNDROME_SYMBOL
 *  0b000000000..Bus master address generator for SYND_GEN writes operates normally.
 *  0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
 */
#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x)  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
#define BCH_DEBUG0_ROM_BIST_COMPLETE_MASK        (0x2000000U)
#define BCH_DEBUG0_ROM_BIST_COMPLETE_SHIFT       (25U)
#define BCH_DEBUG0_ROM_BIST_COMPLETE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_ROM_BIST_COMPLETE_SHIFT)) & BCH_DEBUG0_ROM_BIST_COMPLETE_MASK)
#define BCH_DEBUG0_ROM_BIST_ENABLE_MASK          (0x4000000U)
#define BCH_DEBUG0_ROM_BIST_ENABLE_SHIFT         (26U)
#define BCH_DEBUG0_ROM_BIST_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_ROM_BIST_ENABLE_SHIFT)) & BCH_DEBUG0_ROM_BIST_ENABLE_MASK)
#define BCH_DEBUG0_RSVD1_MASK                    (0xF8000000U)
#define BCH_DEBUG0_RSVD1_SHIFT                   (27U)
#define BCH_DEBUG0_RSVD1(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK)
/*! @} */

/*! @name DBGKESREAD - KES Debug Read Register */
/*! @{ */
#define BCH_DBGKESREAD_VALUES_MASK               (0xFFFFFFFFU)
#define BCH_DBGKESREAD_VALUES_SHIFT              (0U)
#define BCH_DBGKESREAD_VALUES(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK)
/*! @} */

/*! @name DBGCSFEREAD - Chien Search Debug Read Register */
/*! @{ */
#define BCH_DBGCSFEREAD_VALUES_MASK              (0xFFFFFFFFU)
#define BCH_DBGCSFEREAD_VALUES_SHIFT             (0U)
#define BCH_DBGCSFEREAD_VALUES(x)                (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK)
/*! @} */

/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */
/*! @{ */
#define BCH_DBGSYNDGENREAD_VALUES_MASK           (0xFFFFFFFFU)
#define BCH_DBGSYNDGENREAD_VALUES_SHIFT          (0U)
#define BCH_DBGSYNDGENREAD_VALUES(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK)
/*! @} */

/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */
/*! @{ */
#define BCH_DBGAHBMREAD_VALUES_MASK              (0xFFFFFFFFU)
#define BCH_DBGAHBMREAD_VALUES_SHIFT             (0U)
#define BCH_DBGAHBMREAD_VALUES(x)                (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK)
/*! @} */

/*! @name BLOCKNAME - Block Name Register */
/*! @{ */
#define BCH_BLOCKNAME_NAME_MASK                  (0xFFFFFFFFU)
#define BCH_BLOCKNAME_NAME_SHIFT                 (0U)
#define BCH_BLOCKNAME_NAME(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK)
/*! @} */

/*! @name VERSION - BCH Version Register */
/*! @{ */
#define BCH_VERSION_STEP_MASK                    (0xFFFFU)
#define BCH_VERSION_STEP_SHIFT                   (0U)
#define BCH_VERSION_STEP(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK)
#define BCH_VERSION_MINOR_MASK                   (0xFF0000U)
#define BCH_VERSION_MINOR_SHIFT                  (16U)
#define BCH_VERSION_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK)
#define BCH_VERSION_MAJOR_MASK                   (0xFF000000U)
#define BCH_VERSION_MAJOR_SHIFT                  (24U)
#define BCH_VERSION_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK)
/*! @} */

/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */
/*! @{ */
#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK        (0x1FFU)
#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT       (0U)
#define BCH_DEBUG1_ERASED_ZERO_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
#define BCH_DEBUG1_RSVD_MASK                     (0x7FFFFE00U)
#define BCH_DEBUG1_RSVD_SHIFT                    (9U)
#define BCH_DEBUG1_RSVD(x)                       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK)
#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK       (0x80000000U)
#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT      (31U)
/*! DEBUG1_PREERASECHK - DEBUG1_PREERASECHK
 *  0b0..Turn off pre-erase check
 *  0b1..Turn on pre-erase check
 */
#define BCH_DEBUG1_DEBUG1_PREERASECHK(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group BCH_Register_Masks */


/* BCH - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__BCH base address */
#define CONNECTIVITY__BCH_BASE                   (0x5B814000u)
/** Peripheral CONNECTIVITY__BCH base pointer */
#define CONNECTIVITY__BCH                        ((BCH_Type *)CONNECTIVITY__BCH_BASE)
/** Array initializer of BCH peripheral base addresses */
#define BCH_BASE_ADDRS                           { CONNECTIVITY__BCH_BASE }
/** Array initializer of BCH peripheral base pointers */
#define BCH_BASE_PTRS                            { CONNECTIVITY__BCH }

/*!
 * @}
 */ /* end of group BCH_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CAN Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
 * @{
 */

/** CAN - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
  __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
  __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
  __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
  __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
  __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
  __IO uint32_t IMASK2;                            /**< Interrupt Masks 2 register, offset: 0x24 */
  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
  __IO uint32_t IFLAG2;                            /**< Interrupt Flags 2 register, offset: 0x2C */
  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
  __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
  __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
       uint8_t RESERVED_1[8];
  __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
  __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
  __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
  __IO uint32_t CBT;                               /**< CAN Bit Timing Register, offset: 0x50 */
       uint8_t RESERVED_2[4];
  __I  uint32_t DBG1;                              /**< Debug 1 register, offset: 0x58 */
  __I  uint32_t DBG2;                              /**< Debug 2 register, offset: 0x5C */
       uint8_t RESERVED_3[32];
  struct {                                         /* offset: 0x80, array step: 0x10 */
    __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
    __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
    __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
    __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
  } MB[64];
       uint8_t RESERVED_4[1024];
  __IO uint32_t RXIMR[64];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
       uint8_t RESERVED_5[640];
  __IO uint32_t FDCTRL;                            /**< CAN FD Control Register, offset: 0xC00 */
  __IO uint32_t FDCBT;                             /**< CAN FD Bit Timing Register, offset: 0xC04 */
  __I  uint32_t FDCRC;                             /**< CAN FD CRC Register, offset: 0xC08 */
} CAN_Type;

/* ----------------------------------------------------------------------------
   -- CAN Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CAN_Register_Masks CAN Register Masks
 * @{
 */

/*! @name MCR - Module Configuration Register */
/*! @{ */
#define CAN_MCR_MAXMB_MASK                       (0x7FU)
#define CAN_MCR_MAXMB_SHIFT                      (0U)
#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
#define CAN_MCR_IDAM_MASK                        (0x300U)
#define CAN_MCR_IDAM_SHIFT                       (8U)
/*! IDAM - ID Acceptance Mode
 *  0b00..Format A: One full ID (standard and extended) per ID Filter Table element.
 *  0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element.
 *  0b10..Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
 *  0b11..Format D: All frames rejected.
 */
#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
#define CAN_MCR_FDEN_MASK                        (0x800U)
#define CAN_MCR_FDEN_SHIFT                       (11U)
/*! FDEN - CAN FD operation enable
 *  0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
 *  0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
 */
#define CAN_MCR_FDEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
#define CAN_MCR_AEN_MASK                         (0x1000U)
#define CAN_MCR_AEN_SHIFT                        (12U)
/*! AEN - Abort Enable
 *  0b0..Abort disabled.
 *  0b1..Abort enabled.
 */
#define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
#define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
#define CAN_MCR_LPRIOEN_SHIFT                    (13U)
/*! LPRIOEN - Local Priority Enable
 *  0b0..Local Priority disabled.
 *  0b1..Local Priority enabled.
 */
#define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
#define CAN_MCR_DMA_MASK                         (0x8000U)
#define CAN_MCR_DMA_SHIFT                        (15U)
/*! DMA - DMA Enable
 *  0b0..DMA feature for RX FIFO disabled.
 *  0b1..DMA feature for RX FIFO enabled.
 */
#define CAN_MCR_DMA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
#define CAN_MCR_IRMQ_MASK                        (0x10000U)
#define CAN_MCR_IRMQ_SHIFT                       (16U)
/*! IRMQ - Individual Rx Masking And Queue Enable
 *  0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY.
 *  0b1..Individual Rx masking and queue feature are enabled.
 */
#define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
#define CAN_MCR_SRXDIS_MASK                      (0x20000U)
#define CAN_MCR_SRXDIS_SHIFT                     (17U)
/*! SRXDIS - Self Reception Disable
 *  0b0..Self reception enabled.
 *  0b1..Self reception disabled.
 */
#define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
#define CAN_MCR_DOZE_MASK                        (0x40000U)
#define CAN_MCR_DOZE_SHIFT                       (18U)
/*! DOZE - Doze Mode Enable
 *  0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
 *  0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
 */
#define CAN_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
#define CAN_MCR_WAKSRC_MASK                      (0x80000U)
#define CAN_MCR_WAKSRC_SHIFT                     (19U)
/*! WAKSRC - Wake Up Source
 *  0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
 *  0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
 */
#define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
#define CAN_MCR_LPMACK_MASK                      (0x100000U)
#define CAN_MCR_LPMACK_SHIFT                     (20U)
/*! LPMACK - Low-Power Mode Acknowledge
 *  0b0..FlexCAN is not in a low-power mode.
 *  0b1..FlexCAN is in a low-power mode.
 */
#define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
#define CAN_MCR_WRNEN_MASK                       (0x200000U)
#define CAN_MCR_WRNEN_SHIFT                      (21U)
/*! WRNEN - Warning Interrupt Enable
 *  0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
 *  0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
 */
#define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
#define CAN_MCR_SLFWAK_MASK                      (0x400000U)
#define CAN_MCR_SLFWAK_SHIFT                     (22U)
/*! SLFWAK - Self Wake Up
 *  0b0..FlexCAN Self Wake Up feature is disabled.
 *  0b1..FlexCAN Self Wake Up feature is enabled.
 */
#define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
#define CAN_MCR_FRZACK_MASK                      (0x1000000U)
#define CAN_MCR_FRZACK_SHIFT                     (24U)
/*! FRZACK - Freeze Mode Acknowledge
 *  0b0..FlexCAN not in Freeze mode, prescaler running.
 *  0b1..FlexCAN in Freeze mode, prescaler stopped.
 */
#define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
#define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
#define CAN_MCR_SOFTRST_SHIFT                    (25U)
/*! SOFTRST - Soft Reset
 *  0b0..No reset request.
 *  0b1..Resets the registers affected by soft reset.
 */
#define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
#define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
#define CAN_MCR_WAKMSK_SHIFT                     (26U)
/*! WAKMSK - Wake Up Interrupt Mask
 *  0b0..Wake Up Interrupt is disabled.
 *  0b1..Wake Up Interrupt is enabled.
 */
#define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
#define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
#define CAN_MCR_NOTRDY_SHIFT                     (27U)
/*! NOTRDY - FlexCAN Not Ready
 *  0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode.
 */
#define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
#define CAN_MCR_HALT_MASK                        (0x10000000U)
#define CAN_MCR_HALT_SHIFT                       (28U)
/*! HALT - Halt FlexCAN
 *  0b0..No Freeze mode request.
 *  0b1..Enters Freeze mode if the FRZ bit is asserted.
 */
#define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
#define CAN_MCR_RFEN_MASK                        (0x20000000U)
#define CAN_MCR_RFEN_SHIFT                       (29U)
/*! RFEN - Rx FIFO Enable
 *  0b0..Rx FIFO not enabled.
 *  0b1..Rx FIFO enabled.
 */
#define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
#define CAN_MCR_FRZ_MASK                         (0x40000000U)
#define CAN_MCR_FRZ_SHIFT                        (30U)
/*! FRZ - Freeze Enable
 *  0b0..Not enabled to enter Freeze mode.
 *  0b1..Enabled to enter Freeze mode.
 */
#define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
#define CAN_MCR_MDIS_MASK                        (0x80000000U)
#define CAN_MCR_MDIS_SHIFT                       (31U)
/*! MDIS - Module Disable
 *  0b0..Enable the FlexCAN module.
 *  0b1..Disable the FlexCAN module.
 */
#define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
/*! @} */

/*! @name CTRL1 - Control 1 register */
/*! @{ */
#define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
#define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
#define CAN_CTRL1_LOM_MASK                       (0x8U)
#define CAN_CTRL1_LOM_SHIFT                      (3U)
/*! LOM - Listen-Only Mode
 *  0b0..Listen-Only mode is deactivated.
 *  0b1..FlexCAN module operates in Listen-Only mode.
 */
#define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
#define CAN_CTRL1_LBUF_MASK                      (0x10U)
#define CAN_CTRL1_LBUF_SHIFT                     (4U)
/*! LBUF - Lowest Buffer Transmitted First
 *  0b0..Buffer with highest priority is transmitted first.
 *  0b1..Lowest number buffer is transmitted first.
 */
#define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
#define CAN_CTRL1_TSYN_MASK                      (0x20U)
#define CAN_CTRL1_TSYN_SHIFT                     (5U)
/*! TSYN - Timer Sync
 *  0b0..Timer Sync feature disabled
 *  0b1..Timer Sync feature enabled
 */
#define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
#define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
#define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
/*! BOFFREC - Bus Off Recovery
 *  0b0..Automatic recovering from Bus Off state enabled.
 *  0b1..Automatic recovering from Bus Off state disabled.
 */
#define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
#define CAN_CTRL1_SMP_MASK                       (0x80U)
#define CAN_CTRL1_SMP_SHIFT                      (7U)
/*! SMP - CAN Bit Sampling
 *  0b0..Just one sample is used to determine the bit value.
 *  0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used.
 */
#define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
#define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
#define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
/*! RWRNMSK - Rx Warning Interrupt Mask
 *  0b0..Rx Warning Interrupt disabled.
 *  0b1..Rx Warning Interrupt enabled.
 */
#define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
#define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
#define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
/*! TWRNMSK - Tx Warning Interrupt Mask
 *  0b0..Tx Warning Interrupt disabled.
 *  0b1..Tx Warning Interrupt enabled.
 */
#define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
#define CAN_CTRL1_LPB_MASK                       (0x1000U)
#define CAN_CTRL1_LPB_SHIFT                      (12U)
/*! LPB - Loop Back Mode
 *  0b0..Loop Back disabled.
 *  0b1..Loop Back enabled.
 */
#define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
#define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
#define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
/*! ERRMSK - Error Interrupt Mask
 *  0b0..Error interrupt disabled.
 *  0b1..Error interrupt enabled.
 */
#define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
#define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
#define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
/*! BOFFMSK - Bus Off Interrupt Mask
 *  0b0..Bus Off interrupt disabled.
 *  0b1..Bus Off interrupt enabled.
 */
#define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
#define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
#define CAN_CTRL1_PSEG2_SHIFT                    (16U)
#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
#define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
#define CAN_CTRL1_PSEG1_SHIFT                    (19U)
#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
#define CAN_CTRL1_RJW_MASK                       (0xC00000U)
#define CAN_CTRL1_RJW_SHIFT                      (22U)
#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
#define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
#define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
/*! @} */

/*! @name TIMER - Free Running Timer */
/*! @{ */
#define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
#define CAN_TIMER_TIMER_SHIFT                    (0U)
#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
/*! @} */

/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
/*! @{ */
#define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
#define CAN_RXMGMASK_MG_SHIFT                    (0U)
#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
/*! @} */

/*! @name RX14MASK - Rx 14 Mask register */
/*! @{ */
#define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
#define CAN_RX14MASK_RX14M_SHIFT                 (0U)
#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
/*! @} */

/*! @name RX15MASK - Rx 15 Mask register */
/*! @{ */
#define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
#define CAN_RX15MASK_RX15M_SHIFT                 (0U)
#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
/*! @} */

/*! @name ECR - Error Counter */
/*! @{ */
#define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
#define CAN_ECR_TXERRCNT_SHIFT                   (0U)
#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
#define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
#define CAN_ECR_RXERRCNT_SHIFT                   (8U)
#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
#define CAN_ECR_TXERRCNT_FAST_MASK               (0xFF0000U)
#define CAN_ECR_TXERRCNT_FAST_SHIFT              (16U)
#define CAN_ECR_TXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
#define CAN_ECR_RXERRCNT_FAST_MASK               (0xFF000000U)
#define CAN_ECR_RXERRCNT_FAST_SHIFT              (24U)
#define CAN_ECR_RXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
/*! @} */

/*! @name ESR1 - Error and Status 1 register */
/*! @{ */
#define CAN_ESR1_WAKINT_MASK                     (0x1U)
#define CAN_ESR1_WAKINT_SHIFT                    (0U)
/*! WAKINT - Wake-Up Interrupt
 *  0b0..No such occurrence.
 *  0b1..Indicates a recessive to dominant transition was received on the CAN bus.
 */
#define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
#define CAN_ESR1_ERRINT_MASK                     (0x2U)
#define CAN_ESR1_ERRINT_SHIFT                    (1U)
/*! ERRINT - Error Interrupt
 *  0b0..No such occurrence.
 *  0b1..Indicates setting of any Error Bit in the Error and Status Register.
 */
#define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
#define CAN_ESR1_BOFFINT_MASK                    (0x4U)
#define CAN_ESR1_BOFFINT_SHIFT                   (2U)
/*! BOFFINT - Bus Off Interrupt
 *  0b0..No such occurrence.
 *  0b1..FlexCAN module entered Bus Off state.
 */
#define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
#define CAN_ESR1_RX_MASK                         (0x8U)
#define CAN_ESR1_RX_SHIFT                        (3U)
/*! RX - FlexCAN In Reception
 *  0b0..FlexCAN is not receiving a message.
 *  0b1..FlexCAN is receiving a message.
 */
#define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
#define CAN_ESR1_FLTCONF_MASK                    (0x30U)
#define CAN_ESR1_FLTCONF_SHIFT                   (4U)
/*! FLTCONF - Fault Confinement State
 *  0b00..Error Active
 *  0b01..Error Passive
 *  0b1x..Bus Off
 */
#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
#define CAN_ESR1_TX_MASK                         (0x40U)
#define CAN_ESR1_TX_SHIFT                        (6U)
/*! TX - FlexCAN In Transmission
 *  0b0..FlexCAN is not transmitting a message.
 *  0b1..FlexCAN is transmitting a message.
 */
#define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
#define CAN_ESR1_IDLE_MASK                       (0x80U)
#define CAN_ESR1_IDLE_SHIFT                      (7U)
/*! IDLE - IDLE
 *  0b0..No such occurrence.
 *  0b1..CAN bus is now IDLE.
 */
#define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
#define CAN_ESR1_RXWRN_MASK                      (0x100U)
#define CAN_ESR1_RXWRN_SHIFT                     (8U)
/*! RXWRN - Rx Error Warning
 *  0b0..No such occurrence.
 *  0b1..RXERRCNT is greater than or equal to 96.
 */
#define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
#define CAN_ESR1_TXWRN_MASK                      (0x200U)
#define CAN_ESR1_TXWRN_SHIFT                     (9U)
/*! TXWRN - TX Error Warning
 *  0b0..No such occurrence.
 *  0b1..TXERRCNT is greater than or equal to 96.
 */
#define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
#define CAN_ESR1_STFERR_MASK                     (0x400U)
#define CAN_ESR1_STFERR_SHIFT                    (10U)
/*! STFERR - Stuffing Error
 *  0b0..No such occurrence.
 *  0b1..A Stuffing Error occurred since last read of this register.
 */
#define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
#define CAN_ESR1_FRMERR_MASK                     (0x800U)
#define CAN_ESR1_FRMERR_SHIFT                    (11U)
/*! FRMERR - Form Error
 *  0b0..No such occurrence.
 *  0b1..A Form Error occurred since last read of this register.
 */
#define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
#define CAN_ESR1_CRCERR_MASK                     (0x1000U)
#define CAN_ESR1_CRCERR_SHIFT                    (12U)
/*! CRCERR - Cyclic Redundancy Check Error
 *  0b0..No such occurrence.
 *  0b1..A CRC error occurred since last read of this register.
 */
#define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
#define CAN_ESR1_ACKERR_MASK                     (0x2000U)
#define CAN_ESR1_ACKERR_SHIFT                    (13U)
/*! ACKERR - Acknowledge Error
 *  0b0..No such occurrence.
 *  0b1..An ACK error occurred since last read of this register.
 */
#define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
#define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
#define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
/*! BIT0ERR - Bit0 Error
 *  0b0..No such occurrence.
 *  0b1..At least one bit sent as dominant is received as recessive.
 */
#define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
#define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
#define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
/*! BIT1ERR - Bit1 Error
 *  0b0..No such occurrence.
 *  0b1..At least one bit sent as recessive is received as dominant.
 */
#define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
#define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
#define CAN_ESR1_RWRNINT_SHIFT                   (16U)
/*! RWRNINT - Rx Warning Interrupt Flag
 *  0b0..No such occurrence.
 *  0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
 */
#define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
#define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
#define CAN_ESR1_TWRNINT_SHIFT                   (17U)
/*! TWRNINT - Tx Warning Interrupt Flag
 *  0b0..No such occurrence.
 *  0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
 */
#define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
#define CAN_ESR1_SYNCH_MASK                      (0x40000U)
#define CAN_ESR1_SYNCH_SHIFT                     (18U)
/*! SYNCH - CAN Synchronization Status
 *  0b0..FlexCAN is not synchronized to the CAN bus.
 *  0b1..FlexCAN is synchronized to the CAN bus.
 */
#define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
#define CAN_ESR1_BOFFDONEINT_MASK                (0x80000U)
#define CAN_ESR1_BOFFDONEINT_SHIFT               (19U)
/*! BOFFDONEINT - Bus Off Done Interrupt
 *  0b0..No such occurrence.
 *  0b1..FlexCAN module has completed Bus Off process.
 */
#define CAN_ESR1_BOFFDONEINT(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
#define CAN_ESR1_ERRINT_FAST_MASK                (0x100000U)
#define CAN_ESR1_ERRINT_FAST_SHIFT               (20U)
/*! ERRINT_FAST - Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set.
 */
#define CAN_ESR1_ERRINT_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
#define CAN_ESR1_ERROVR_MASK                     (0x200000U)
#define CAN_ESR1_ERROVR_SHIFT                    (21U)
/*! ERROVR - Error Overrun bit
 *  0b0..Overrun has not occurred.
 *  0b1..Overrun has occurred.
 */
#define CAN_ESR1_ERROVR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
#define CAN_ESR1_STFERR_FAST_MASK                (0x4000000U)
#define CAN_ESR1_STFERR_FAST_SHIFT               (26U)
/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..A Stuffing Error occurred since last read of this register.
 */
#define CAN_ESR1_STFERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
#define CAN_ESR1_FRMERR_FAST_MASK                (0x8000000U)
#define CAN_ESR1_FRMERR_FAST_SHIFT               (27U)
/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..A Form Error occurred since last read of this register.
 */
#define CAN_ESR1_FRMERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
#define CAN_ESR1_CRCERR_FAST_MASK                (0x10000000U)
#define CAN_ESR1_CRCERR_FAST_SHIFT               (28U)
/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..A CRC error occurred since last read of this register.
 */
#define CAN_ESR1_CRCERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
#define CAN_ESR1_BIT0ERR_FAST_MASK               (0x40000000U)
#define CAN_ESR1_BIT0ERR_FAST_SHIFT              (30U)
/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..At least one bit sent as dominant is received as recessive.
 */
#define CAN_ESR1_BIT0ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
#define CAN_ESR1_BIT1ERR_FAST_MASK               (0x80000000U)
#define CAN_ESR1_BIT1ERR_FAST_SHIFT              (31U)
/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..At least one bit sent as recessive is received as dominant.
 */
#define CAN_ESR1_BIT1ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
/*! @} */

/*! @name IMASK2 - Interrupt Masks 2 register */
/*! @{ */
#define CAN_IMASK2_BUF63TO32M_MASK               (0xFFFFFFFFU)
#define CAN_IMASK2_BUF63TO32M_SHIFT              (0U)
#define CAN_IMASK2_BUF63TO32M(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
/*! @} */

/*! @name IMASK1 - Interrupt Masks 1 register */
/*! @{ */
#define CAN_IMASK1_BUF31TO0M_MASK                (0xFFFFFFFFU)
#define CAN_IMASK1_BUF31TO0M_SHIFT               (0U)
#define CAN_IMASK1_BUF31TO0M(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
/*! @} */

/*! @name IFLAG2 - Interrupt Flags 2 register */
/*! @{ */
#define CAN_IFLAG2_BUF63TO32I_MASK               (0xFFFFFFFFU)
#define CAN_IFLAG2_BUF63TO32I_SHIFT              (0U)
#define CAN_IFLAG2_BUF63TO32I(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
/*! @} */

/*! @name IFLAG1 - Interrupt Flags 1 register */
/*! @{ */
#define CAN_IFLAG1_BUF0I_MASK                    (0x1U)
#define CAN_IFLAG1_BUF0I_SHIFT                   (0U)
/*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit
 *  0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when CAN_MCR[RFEN]=0.
 *  0b1..The corresponding buffer has successfully completed transmission or reception when CAN_MCR[RFEN]=0.
 */
#define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
#define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
#define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
#define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
#define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
/*! BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO"
 *  0b0..No occurrence of MB5 completing transmission/reception when CAN_MCR[RFEN]=0, or of frame(s) available in the FIFO, when CAN_MCR[RFEN]=1
 *  0b1..MB5 completed transmission/reception when CAN_MCR[RFEN]=0, or frame(s) available in the Rx FIFO when CAN_MCR[RFEN]=1. It generates a DMA request in case of CAN_MCR[RFEN] and CAN_MCR[DMA] are enabled.
 */
#define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
#define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
#define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
/*! BUF6I - Buffer MB6 Interrupt Or "Rx FIFO Warning"
 *  0b0..No occurrence of MB6 completing transmission/reception when CAN_MCR[RFEN]=0, or of Rx FIFO almost full when CAN_MCR[RFEN]=1
 *  0b1..MB6 completed transmission/reception when CAN_MCR[RFEN]=0, or Rx FIFO almost full when CAN_MCR[RFEN]=1
 */
#define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
#define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
#define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
/*! BUF7I - Buffer MB7 Interrupt Or "Rx FIFO Overflow"
 *  0b0..No occurrence of MB7 completing transmission/reception when CAN_MCR[RFEN]=0, or of Rx FIFO overflow when CAN_MCR[RFEN]=1
 *  0b1..MB7 completed transmission/reception when CAN_MCR[RFEN]=0, or Rx FIFO overflow when CAN_MCR[RFEN]=1
 */
#define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
#define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
#define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
/*! @} */

/*! @name CTRL2 - Control 2 register */
/*! @{ */
#define CAN_CTRL2_EACEN_MASK                     (0x10000U)
#define CAN_CTRL2_EACEN_SHIFT                    (16U)
/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
 *  0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
 *  0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply.
 */
#define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
#define CAN_CTRL2_RRS_MASK                       (0x20000U)
#define CAN_CTRL2_RRS_SHIFT                      (17U)
/*! RRS - Remote Request Storing
 *  0b0..Remote Response Frame is generated.
 *  0b1..Remote Request Frame is stored.
 */
#define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
#define CAN_CTRL2_MRP_MASK                       (0x40000U)
#define CAN_CTRL2_MRP_SHIFT                      (18U)
/*! MRP - Mailboxes Reception Priority
 *  0b0..Matching starts from Rx FIFO and continues on Mailboxes.
 *  0b1..Matching starts from Mailboxes and continues on Rx FIFO.
 */
#define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
#define CAN_CTRL2_TASD_MASK                      (0xF80000U)
#define CAN_CTRL2_TASD_SHIFT                     (19U)
#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
#define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
#define CAN_CTRL2_RFFN_SHIFT                     (24U)
#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
#define CAN_CTRL2_BOFFDONEMSK_MASK               (0x40000000U)
#define CAN_CTRL2_BOFFDONEMSK_SHIFT              (30U)
/*! BOFFDONEMSK - Bus Off Done Interrupt Mask
 *  0b0..Bus Off Done interrupt disabled.
 *  0b1..Bus Off Done interrupt enabled.
 */
#define CAN_CTRL2_BOFFDONEMSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
#define CAN_CTRL2_ERRMSK_FAST_MASK               (0x80000000U)
#define CAN_CTRL2_ERRMSK_FAST_SHIFT              (31U)
/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames
 *  0b0..ERRINT_FAST Error interrupt disabled.
 *  0b1..ERRINT_FAST Error interrupt enabled.
 */
#define CAN_CTRL2_ERRMSK_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
/*! @} */

/*! @name ESR2 - Error and Status 2 register */
/*! @{ */
#define CAN_ESR2_IMB_MASK                        (0x2000U)
#define CAN_ESR2_IMB_SHIFT                       (13U)
/*! IMB - Inactive Mailbox
 *  0b0..If CAN_ESR2[VPS] is asserted, the CAN_ESR2[LPTM] is not an inactive Mailbox.
 *  0b1..If CAN_ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.
 */
#define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
#define CAN_ESR2_VPS_MASK                        (0x4000U)
#define CAN_ESR2_VPS_SHIFT                       (14U)
/*! VPS - Valid Priority Status
 *  0b0..Contents of IMB and LPTM are invalid.
 *  0b1..Contents of IMB and LPTM are valid.
 */
#define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
#define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
#define CAN_ESR2_LPTM_SHIFT                      (16U)
#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
/*! @} */

/*! @name CRCR - CRC Register */
/*! @{ */
#define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
#define CAN_CRCR_TXCRC_SHIFT                     (0U)
#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
#define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
#define CAN_CRCR_MBCRC_SHIFT                     (16U)
#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
/*! @} */

/*! @name RXFGMASK - Rx FIFO Global Mask register */
/*! @{ */
#define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
#define CAN_RXFGMASK_FGM_SHIFT                   (0U)
#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
/*! @} */

/*! @name RXFIR - Rx FIFO Information Register */
/*! @{ */
#define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
#define CAN_RXFIR_IDHIT_SHIFT                    (0U)
#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
/*! @} */

/*! @name CBT - CAN Bit Timing Register */
/*! @{ */
#define CAN_CBT_EPSEG2_MASK                      (0x1FU)
#define CAN_CBT_EPSEG2_SHIFT                     (0U)
#define CAN_CBT_EPSEG2(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
#define CAN_CBT_EPSEG1_MASK                      (0x3E0U)
#define CAN_CBT_EPSEG1_SHIFT                     (5U)
#define CAN_CBT_EPSEG1(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
#define CAN_CBT_EPROPSEG_MASK                    (0xFC00U)
#define CAN_CBT_EPROPSEG_SHIFT                   (10U)
#define CAN_CBT_EPROPSEG(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
#define CAN_CBT_ERJW_MASK                        (0xF0000U)
#define CAN_CBT_ERJW_SHIFT                       (16U)
#define CAN_CBT_ERJW(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
#define CAN_CBT_EPRESDIV_MASK                    (0x7FE00000U)
#define CAN_CBT_EPRESDIV_SHIFT                   (21U)
#define CAN_CBT_EPRESDIV(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
#define CAN_CBT_BTF_MASK                         (0x80000000U)
#define CAN_CBT_BTF_SHIFT                        (31U)
/*! BTF - Bit Timing Format Enable
 *  0b0..Extended bit time definitions disabled.
 *  0b1..Extended bit time definitions enabled.
 */
#define CAN_CBT_BTF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
/*! @} */

/*! @name DBG1 - Debug 1 register */
/*! @{ */
#define CAN_DBG1_CFSM_MASK                       (0x7FU)
#define CAN_DBG1_CFSM_SHIFT                      (0U)
#define CAN_DBG1_CFSM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
#define CAN_DBG1_CBN_MASK                        (0x3FF0000U)
#define CAN_DBG1_CBN_SHIFT                       (16U)
#define CAN_DBG1_CBN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
/*! @} */

/*! @name DBG2 - Debug 2 register */
/*! @{ */
#define CAN_DBG2_RMP_MASK                        (0x7FU)
#define CAN_DBG2_RMP_SHIFT                       (0U)
#define CAN_DBG2_RMP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
#define CAN_DBG2_MPP_MASK                        (0x80U)
#define CAN_DBG2_MPP_SHIFT                       (7U)
/*! MPP - Matching Process in Progress
 *  0b0..No matching process ongoing
 *  0b1..Matching process is in progress.
 */
#define CAN_DBG2_MPP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
#define CAN_DBG2_TAP_MASK                        (0x7F00U)
#define CAN_DBG2_TAP_SHIFT                       (8U)
#define CAN_DBG2_TAP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
#define CAN_DBG2_APP_MASK                        (0x8000U)
#define CAN_DBG2_APP_SHIFT                       (15U)
/*! APP - Arbitration Process in Progress
 *  0b0..No arbitration process ongoing
 *  0b1..Arbitration process is in progress.
 */
#define CAN_DBG2_APP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
/*! @} */

/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
/*! @{ */
#define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
#define CAN_CS_TIME_STAMP_SHIFT                  (0U)
#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
#define CAN_CS_DLC_MASK                          (0xF0000U)
#define CAN_CS_DLC_SHIFT                         (16U)
#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
#define CAN_CS_RTR_MASK                          (0x100000U)
#define CAN_CS_RTR_SHIFT                         (20U)
#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
#define CAN_CS_IDE_MASK                          (0x200000U)
#define CAN_CS_IDE_SHIFT                         (21U)
#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
#define CAN_CS_SRR_MASK                          (0x400000U)
#define CAN_CS_SRR_SHIFT                         (22U)
#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
#define CAN_CS_CODE_MASK                         (0xF000000U)
#define CAN_CS_CODE_SHIFT                        (24U)
#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
#define CAN_CS_ESI_MASK                          (0x20000000U)
#define CAN_CS_ESI_SHIFT                         (29U)
#define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
#define CAN_CS_BRS_MASK                          (0x40000000U)
#define CAN_CS_BRS_SHIFT                         (30U)
#define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
#define CAN_CS_EDL_MASK                          (0x80000000U)
#define CAN_CS_EDL_SHIFT                         (31U)
#define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
/*! @} */

/* The count of CAN_CS */
#define CAN_CS_COUNT                             (64U)

/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */
/*! @{ */
#define CAN_ID_EXT_MASK                          (0x3FFFFU)
#define CAN_ID_EXT_SHIFT                         (0U)
#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
#define CAN_ID_STD_MASK                          (0x1FFC0000U)
#define CAN_ID_STD_SHIFT                         (18U)
#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
#define CAN_ID_PRIO_MASK                         (0xE0000000U)
#define CAN_ID_PRIO_SHIFT                        (29U)
#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
/*! @} */

/* The count of CAN_ID */
#define CAN_ID_COUNT                             (64U)

/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
/*! @{ */
#define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
#define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
#define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
#define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
#define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
#define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
#define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
#define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
/*! @} */

/* The count of CAN_WORD0 */
#define CAN_WORD0_COUNT                          (64U)

/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
/*! @{ */
#define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
#define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
#define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
#define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
#define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
#define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
#define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
#define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
/*! @} */

/* The count of CAN_WORD1 */
#define CAN_WORD1_COUNT                          (64U)

/*! @name RXIMR - Rx Individual Mask Registers */
/*! @{ */
#define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
#define CAN_RXIMR_MI_SHIFT                       (0U)
#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
/*! @} */

/* The count of CAN_RXIMR */
#define CAN_RXIMR_COUNT                          (64U)

/*! @name FDCTRL - CAN FD Control Register */
/*! @{ */
#define CAN_FDCTRL_TDCVAL_MASK                   (0x3FU)
#define CAN_FDCTRL_TDCVAL_SHIFT                  (0U)
#define CAN_FDCTRL_TDCVAL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
#define CAN_FDCTRL_TDCOFF_MASK                   (0x1F00U)
#define CAN_FDCTRL_TDCOFF_SHIFT                  (8U)
#define CAN_FDCTRL_TDCOFF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
#define CAN_FDCTRL_TDCFAIL_MASK                  (0x4000U)
#define CAN_FDCTRL_TDCFAIL_SHIFT                 (14U)
/*! TDCFAIL - Transceiver Delay Compensation Fail
 *  0b0..Measured loop delay is in range.
 *  0b1..Measured loop delay is out of range.
 */
#define CAN_FDCTRL_TDCFAIL(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
#define CAN_FDCTRL_TDCEN_MASK                    (0x8000U)
#define CAN_FDCTRL_TDCEN_SHIFT                   (15U)
/*! TDCEN - Transceiver Delay Compensation Enable
 *  0b0..TDC is disabled
 *  0b1..TDC is enabled
 */
#define CAN_FDCTRL_TDCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
#define CAN_FDCTRL_MBDSR0_MASK                   (0x30000U)
#define CAN_FDCTRL_MBDSR0_SHIFT                  (16U)
/*! MBDSR0 - Message Buffer Data Size for Region 0
 *  0b00..Selects 8 bytes per Message Buffer.
 *  0b01..Selects 16 bytes per Message Buffer.
 *  0b10..Selects 32 bytes per Message Buffer.
 *  0b11..Selects 64 bytes per Message Buffer.
 */
#define CAN_FDCTRL_MBDSR0(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
#define CAN_FDCTRL_MBDSR1_MASK                   (0x180000U)
#define CAN_FDCTRL_MBDSR1_SHIFT                  (19U)
/*! MBDSR1 - Message Buffer Data Size for Region 1
 *  0b00..Selects 8 bytes per Message Buffer.
 *  0b01..Selects 16 bytes per Message Buffer.
 *  0b10..Selects 32 bytes per Message Buffer.
 *  0b11..Selects 64 bytes per Message Buffer.
 */
#define CAN_FDCTRL_MBDSR1(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
#define CAN_FDCTRL_FDRATE_MASK                   (0x80000000U)
#define CAN_FDCTRL_FDRATE_SHIFT                  (31U)
/*! FDRATE - Bit Rate Switch Enable
 *  0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
 *  0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
 */
#define CAN_FDCTRL_FDRATE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
/*! @} */

/*! @name FDCBT - CAN FD Bit Timing Register */
/*! @{ */
#define CAN_FDCBT_FPSEG2_MASK                    (0x7U)
#define CAN_FDCBT_FPSEG2_SHIFT                   (0U)
#define CAN_FDCBT_FPSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
#define CAN_FDCBT_FPSEG1_MASK                    (0xE0U)
#define CAN_FDCBT_FPSEG1_SHIFT                   (5U)
#define CAN_FDCBT_FPSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
#define CAN_FDCBT_FPROPSEG_MASK                  (0x7C00U)
#define CAN_FDCBT_FPROPSEG_SHIFT                 (10U)
#define CAN_FDCBT_FPROPSEG(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
#define CAN_FDCBT_FRJW_MASK                      (0x30000U)
#define CAN_FDCBT_FRJW_SHIFT                     (16U)
#define CAN_FDCBT_FRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
#define CAN_FDCBT_FPRESDIV_MASK                  (0x3FF00000U)
#define CAN_FDCBT_FPRESDIV_SHIFT                 (20U)
#define CAN_FDCBT_FPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
/*! @} */

/*! @name FDCRC - CAN FD CRC Register */
/*! @{ */
#define CAN_FDCRC_FD_TXCRC_MASK                  (0x1FFFFFU)
#define CAN_FDCRC_FD_TXCRC_SHIFT                 (0U)
#define CAN_FDCRC_FD_TXCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
#define CAN_FDCRC_FD_MBCRC_MASK                  (0x7F000000U)
#define CAN_FDCRC_FD_MBCRC_SHIFT                 (24U)
#define CAN_FDCRC_FD_MBCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CAN_Register_Masks */


/* CAN - Peripheral instance base addresses */
/** Peripheral DMA__CAN0 base address */
#define DMA__CAN0_BASE                           (0x5A8D0000u)
/** Peripheral DMA__CAN0 base pointer */
#define DMA__CAN0                                ((CAN_Type *)DMA__CAN0_BASE)
/** Peripheral DMA__CAN1 base address */
#define DMA__CAN1_BASE                           (0x5A8E0000u)
/** Peripheral DMA__CAN1 base pointer */
#define DMA__CAN1                                ((CAN_Type *)DMA__CAN1_BASE)
/** Peripheral DMA__CAN2 base address */
#define DMA__CAN2_BASE                           (0x5A8F0000u)
/** Peripheral DMA__CAN2 base pointer */
#define DMA__CAN2                                ((CAN_Type *)DMA__CAN2_BASE)
/** Array initializer of CAN peripheral base addresses */
#define CAN_BASE_ADDRS                           { DMA__CAN0_BASE, DMA__CAN1_BASE, DMA__CAN2_BASE }
/** Array initializer of CAN peripheral base pointers */
#define CAN_BASE_PTRS                            { DMA__CAN0, DMA__CAN1, DMA__CAN2 }
/** Interrupt vectors for the CAN peripheral type */
#define CAN_Rx_Warning_IRQS                      { DMA_FLEXCAN0_INT_IRQn, DMA_FLEXCAN1_INT_IRQn, DMA_FLEXCAN2_INT_IRQn }
#define CAN_Tx_Warning_IRQS                      { DMA_FLEXCAN0_INT_IRQn, DMA_FLEXCAN1_INT_IRQn, DMA_FLEXCAN2_INT_IRQn }
#define CAN_Wake_Up_IRQS                         { DMA_FLEXCAN0_INT_IRQn, DMA_FLEXCAN1_INT_IRQn, DMA_FLEXCAN2_INT_IRQn }
#define CAN_Error_IRQS                           { DMA_FLEXCAN0_INT_IRQn, DMA_FLEXCAN1_INT_IRQn, DMA_FLEXCAN2_INT_IRQn }
#define CAN_Bus_Off_IRQS                         { DMA_FLEXCAN0_INT_IRQn, DMA_FLEXCAN1_INT_IRQn, DMA_FLEXCAN2_INT_IRQn }
#define CAN_ORed_Message_buffer_IRQS             { DMA_FLEXCAN0_INT_IRQn, DMA_FLEXCAN1_INT_IRQn, DMA_FLEXCAN2_INT_IRQn }

/*!
 * @}
 */ /* end of group CAN_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CM4_LPCG_LPI2C Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CM4_LPCG_LPI2C_Peripheral_Access_Layer CM4_LPCG_LPI2C Peripheral Access Layer
 * @{
 */

/** CM4_LPCG_LPI2C - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPI2C_0;                      /**< na, offset: 0x0 */
} CM4_LPCG_LPI2C_Type;

/* ----------------------------------------------------------------------------
   -- CM4_LPCG_LPI2C Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CM4_LPCG_LPI2C_Register_Masks CM4_LPCG_LPI2C Register Masks
 * @{
 */

/*! @name LPCG_LPI2C_0 - na */
/*! @{ */
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK (0x4U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT (2U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK (0x10U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT (4U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK (0x20U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT (5U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK (0x40U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT (6U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK (0x80U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT (7U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK (0xFFFFFF00U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT (8U)
#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CM4_LPCG_LPI2C_Register_Masks */


/* CM4_LPCG_LPI2C - Peripheral instance base addresses */
/** Peripheral CM4_0__LPCG_LPI2C base address */
#define CM4_0__LPCG_LPI2C_BASE                   (0x37630000u)
/** Peripheral CM4_0__LPCG_LPI2C base pointer */
#define CM4_0__LPCG_LPI2C                        ((CM4_LPCG_LPI2C_Type *)CM4_0__LPCG_LPI2C_BASE)
/** Peripheral CM4_1__LPCG_LPI2C base address */
#define CM4_1__LPCG_LPI2C_BASE                   (0x41630000u)
/** Peripheral CM4_1__LPCG_LPI2C base pointer */
#define CM4_1__LPCG_LPI2C                        ((CM4_LPCG_LPI2C_Type *)CM4_1__LPCG_LPI2C_BASE)
/** Array initializer of CM4_LPCG_LPI2C peripheral base addresses */
#define CM4_LPCG_LPI2C_BASE_ADDRS                { CM4_0__LPCG_LPI2C_BASE, CM4_1__LPCG_LPI2C_BASE }
/** Array initializer of CM4_LPCG_LPI2C peripheral base pointers */
#define CM4_LPCG_LPI2C_BASE_PTRS                 { CM4_0__LPCG_LPI2C, CM4_1__LPCG_LPI2C }

/*!
 * @}
 */ /* end of group CM4_LPCG_LPI2C_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CM4_LPCG_LPIT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CM4_LPCG_LPIT_Peripheral_Access_Layer CM4_LPCG_LPIT Peripheral Access Layer
 * @{
 */

/** CM4_LPCG_LPIT - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPIT_0;                       /**< na, offset: 0x0 */
} CM4_LPCG_LPIT_Type;

/* ----------------------------------------------------------------------------
   -- CM4_LPCG_LPIT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CM4_LPCG_LPIT_Register_Masks CM4_LPCG_LPIT Register Masks
 * @{
 */

/*! @name LPCG_LPIT_0 - na */
/*! @{ */
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK (0x1U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT (0U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK (0x2U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT (1U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK (0x4U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT (2U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK (0x8U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT (3U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK (0x10U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT (4U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK (0x20U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT (5U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK (0x40U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT (6U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK (0x80U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT (7U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK (0xFFFFFF00U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT (8U)
#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CM4_LPCG_LPIT_Register_Masks */


/* CM4_LPCG_LPIT - Peripheral instance base addresses */
/** Peripheral CM4_0__LPCG_LPIT base address */
#define CM4_0__LPCG_LPIT_BASE                    (0x37610000u)
/** Peripheral CM4_0__LPCG_LPIT base pointer */
#define CM4_0__LPCG_LPIT                         ((CM4_LPCG_LPIT_Type *)CM4_0__LPCG_LPIT_BASE)
/** Peripheral CM4_1__LPCG_LPIT base address */
#define CM4_1__LPCG_LPIT_BASE                    (0x41610000u)
/** Peripheral CM4_1__LPCG_LPIT base pointer */
#define CM4_1__LPCG_LPIT                         ((CM4_LPCG_LPIT_Type *)CM4_1__LPCG_LPIT_BASE)
/** Array initializer of CM4_LPCG_LPIT peripheral base addresses */
#define CM4_LPCG_LPIT_BASE_ADDRS                 { CM4_0__LPCG_LPIT_BASE, CM4_1__LPCG_LPIT_BASE }
/** Array initializer of CM4_LPCG_LPIT peripheral base pointers */
#define CM4_LPCG_LPIT_BASE_PTRS                  { CM4_0__LPCG_LPIT, CM4_1__LPCG_LPIT }

/*!
 * @}
 */ /* end of group CM4_LPCG_LPIT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CM4_LPCG_LPUART Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CM4_LPCG_LPUART_Peripheral_Access_Layer CM4_LPCG_LPUART Peripheral Access Layer
 * @{
 */

/** CM4_LPCG_LPUART - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPUART_0;                     /**< na, offset: 0x0 */
} CM4_LPCG_LPUART_Type;

/* ----------------------------------------------------------------------------
   -- CM4_LPCG_LPUART Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CM4_LPCG_LPUART_Register_Masks CM4_LPCG_LPUART Register Masks
 * @{
 */

/*! @name LPCG_LPUART_0 - na */
/*! @{ */
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK (0x4U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT (2U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK (0x8U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT (3U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK (0x10U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT (4U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK (0x20U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT (5U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK (0x40U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT (6U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK (0x80U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT (7U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK (0xFFFFFF00U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT (8U)
#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CM4_LPCG_LPUART_Register_Masks */


/* CM4_LPCG_LPUART - Peripheral instance base addresses */
/** Peripheral CM4_0__LPCG_LPUART base address */
#define CM4_0__LPCG_LPUART_BASE                  (0x37620000u)
/** Peripheral CM4_0__LPCG_LPUART base pointer */
#define CM4_0__LPCG_LPUART                       ((CM4_LPCG_LPUART_Type *)CM4_0__LPCG_LPUART_BASE)
/** Peripheral CM4_1__LPCG_LPUART base address */
#define CM4_1__LPCG_LPUART_BASE                  (0x41620000u)
/** Peripheral CM4_1__LPCG_LPUART base pointer */
#define CM4_1__LPCG_LPUART                       ((CM4_LPCG_LPUART_Type *)CM4_1__LPCG_LPUART_BASE)
/** Array initializer of CM4_LPCG_LPUART peripheral base addresses */
#define CM4_LPCG_LPUART_BASE_ADDRS               { CM4_0__LPCG_LPUART_BASE, CM4_1__LPCG_LPUART_BASE }
/** Array initializer of CM4_LPCG_LPUART peripheral base pointers */
#define CM4_LPCG_LPUART_BASE_PTRS                { CM4_0__LPCG_LPUART, CM4_1__LPCG_LPUART }

/*!
 * @}
 */ /* end of group CM4_LPCG_LPUART_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CM4_LPCG_MMCAU_HCLK Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer CM4_LPCG_MMCAU_HCLK Peripheral Access Layer
 * @{
 */

/** CM4_LPCG_MMCAU_HCLK - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MMCAU_HCLK_0;                 /**< na, offset: 0x0 */
} CM4_LPCG_MMCAU_HCLK_Type;

/* ----------------------------------------------------------------------------
   -- CM4_LPCG_MMCAU_HCLK Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CM4_LPCG_MMCAU_HCLK_Register_Masks CM4_LPCG_MMCAU_HCLK Register Masks
 * @{
 */

/*! @name LPCG_MMCAU_HCLK_0 - na */
/*! @{ */
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK (0x1U)
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT (0U)
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK)
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK (0x2U)
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT (1U)
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK)
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK (0x4U)
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT (2U)
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK)
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK (0x8U)
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT (3U)
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK)
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT (4U)
#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CM4_LPCG_MMCAU_HCLK_Register_Masks */


/* CM4_LPCG_MMCAU_HCLK - Peripheral instance base addresses */
/** Peripheral CM4_0__LPCG_MMCAU_HCLK base address */
#define CM4_0__LPCG_MMCAU_HCLK_BASE              (0x375F0000u)
/** Peripheral CM4_0__LPCG_MMCAU_HCLK base pointer */
#define CM4_0__LPCG_MMCAU_HCLK                   ((CM4_LPCG_MMCAU_HCLK_Type *)CM4_0__LPCG_MMCAU_HCLK_BASE)
/** Peripheral CM4_1__LPCG_MMCAU_HCLK base address */
#define CM4_1__LPCG_MMCAU_HCLK_BASE              (0x415F0000u)
/** Peripheral CM4_1__LPCG_MMCAU_HCLK base pointer */
#define CM4_1__LPCG_MMCAU_HCLK                   ((CM4_LPCG_MMCAU_HCLK_Type *)CM4_1__LPCG_MMCAU_HCLK_BASE)
/** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base addresses */
#define CM4_LPCG_MMCAU_HCLK_BASE_ADDRS           { CM4_0__LPCG_MMCAU_HCLK_BASE, CM4_1__LPCG_MMCAU_HCLK_BASE }
/** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base pointers */
#define CM4_LPCG_MMCAU_HCLK_BASE_PTRS            { CM4_0__LPCG_MMCAU_HCLK, CM4_1__LPCG_MMCAU_HCLK }

/*!
 * @}
 */ /* end of group CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CM4_LPCG_TCMC_HCLK Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer CM4_LPCG_TCMC_HCLK Peripheral Access Layer
 * @{
 */

/** CM4_LPCG_TCMC_HCLK - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_TCMC_HCLK_0;                  /**< na, offset: 0x0 */
} CM4_LPCG_TCMC_HCLK_Type;

/* ----------------------------------------------------------------------------
   -- CM4_LPCG_TCMC_HCLK Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CM4_LPCG_TCMC_HCLK_Register_Masks CM4_LPCG_TCMC_HCLK Register Masks
 * @{
 */

/*! @name LPCG_TCMC_HCLK_0 - na */
/*! @{ */
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK (0x1U)
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT (0U)
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK)
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK (0x2U)
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT (1U)
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK)
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK (0x4U)
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT (2U)
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK)
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK (0x8U)
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT (3U)
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK)
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT (4U)
#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CM4_LPCG_TCMC_HCLK_Register_Masks */


/* CM4_LPCG_TCMC_HCLK - Peripheral instance base addresses */
/** Peripheral CM4_0__LPCG_TCMC_HCLK base address */
#define CM4_0__LPCG_TCMC_HCLK_BASE               (0x375E0000u)
/** Peripheral CM4_0__LPCG_TCMC_HCLK base pointer */
#define CM4_0__LPCG_TCMC_HCLK                    ((CM4_LPCG_TCMC_HCLK_Type *)CM4_0__LPCG_TCMC_HCLK_BASE)
/** Peripheral CM4_1__LPCG_TCMC_HCLK base address */
#define CM4_1__LPCG_TCMC_HCLK_BASE               (0x415E0000u)
/** Peripheral CM4_1__LPCG_TCMC_HCLK base pointer */
#define CM4_1__LPCG_TCMC_HCLK                    ((CM4_LPCG_TCMC_HCLK_Type *)CM4_1__LPCG_TCMC_HCLK_BASE)
/** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base addresses */
#define CM4_LPCG_TCMC_HCLK_BASE_ADDRS            { CM4_0__LPCG_TCMC_HCLK_BASE, CM4_1__LPCG_TCMC_HCLK_BASE }
/** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base pointers */
#define CM4_LPCG_TCMC_HCLK_BASE_PTRS             { CM4_0__LPCG_TCMC_HCLK, CM4_1__LPCG_TCMC_HCLK }

/*!
 * @}
 */ /* end of group CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CM4_LPCG_TPM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CM4_LPCG_TPM_Peripheral_Access_Layer CM4_LPCG_TPM Peripheral Access Layer
 * @{
 */

/** CM4_LPCG_TPM - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_TPM_0;                        /**< na, offset: 0x0 */
} CM4_LPCG_TPM_Type;

/* ----------------------------------------------------------------------------
   -- CM4_LPCG_TPM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CM4_LPCG_TPM_Register_Masks CM4_LPCG_TPM Register Masks
 * @{
 */

/*! @name LPCG_TPM_0 - na */
/*! @{ */
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK (0x1U)
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT (0U)
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK)
#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK (0x2U)
#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT (1U)
#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK)
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK (0x4U)
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT (2U)
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK)
#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK (0x8U)
#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT (3U)
#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK)
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK (0x10U)
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT (4U)
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK)
#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK (0x20U)
#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT (5U)
#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK)
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK (0x40U)
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT (6U)
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK)
#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK (0x80U)
#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT (7U)
#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK)
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK (0xFFFFFF00U)
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT (8U)
#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CM4_LPCG_TPM_Register_Masks */


/* CM4_LPCG_TPM - Peripheral instance base addresses */
/** Peripheral CM4_0__LPCG_TPM base address */
#define CM4_0__LPCG_TPM_BASE                     (0x37600000u)
/** Peripheral CM4_0__LPCG_TPM base pointer */
#define CM4_0__LPCG_TPM                          ((CM4_LPCG_TPM_Type *)CM4_0__LPCG_TPM_BASE)
/** Peripheral CM4_1__LPCG_TPM base address */
#define CM4_1__LPCG_TPM_BASE                     (0x41600000u)
/** Peripheral CM4_1__LPCG_TPM base pointer */
#define CM4_1__LPCG_TPM                          ((CM4_LPCG_TPM_Type *)CM4_1__LPCG_TPM_BASE)
/** Array initializer of CM4_LPCG_TPM peripheral base addresses */
#define CM4_LPCG_TPM_BASE_ADDRS                  { CM4_0__LPCG_TPM_BASE, CM4_1__LPCG_TPM_BASE }
/** Array initializer of CM4_LPCG_TPM peripheral base pointers */
#define CM4_LPCG_TPM_BASE_PTRS                   { CM4_0__LPCG_TPM, CM4_1__LPCG_TPM }

/*!
 * @}
 */ /* end of group CM4_LPCG_TPM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_DTC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_DTC_Peripheral_Access_Layer CONNECTIVITY_LPCG_DTC Peripheral Access Layer
 * @{
 */

/** CONNECTIVITY_LPCG_DTC - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_DTCP_0;                  /**< na, offset: 0x0 */
} CONNECTIVITY_LPCG_DTC_Type;

/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_DTC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_DTC_Register_Masks CONNECTIVITY_LPCG_DTC Register Masks
 * @{
 */

/*! @name LPCG_LPCG_DTCP_0 - na */
/*! @{ */
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_0_0_MASK (0x1U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_0_0_SHIFT (0U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_0_0_MASK)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_SWEN_AND_dtcp_mem_dtcp_mem_rom_clk_SWEN_MASK (0x2U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_SWEN_AND_dtcp_mem_dtcp_mem_rom_clk_SWEN_SHIFT (1U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_SWEN_AND_dtcp_mem_dtcp_mem_rom_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_SWEN_AND_dtcp_mem_dtcp_mem_rom_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_SWEN_AND_dtcp_mem_dtcp_mem_rom_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_2_2_MASK (0x4U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_2_2_SHIFT (2U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_2_2_MASK)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_STOP_AND_dtcp_mem_dtcp_mem_rom_clk_STOP_MASK (0x8U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_STOP_AND_dtcp_mem_dtcp_mem_rom_clk_STOP_SHIFT (3U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_STOP_AND_dtcp_mem_dtcp_mem_rom_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_STOP_AND_dtcp_mem_dtcp_mem_rom_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_mem_dtcp_mem_ram_clk_STOP_AND_dtcp_mem_dtcp_mem_rom_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_4_16_MASK (0x1FFF0U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_4_16_SHIFT (4U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_4_16_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_4_16_MASK)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_SWEN_MASK (0x20000U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_SWEN_SHIFT (17U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_18_18_MASK (0x40000U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_18_18_SHIFT (18U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_18_18_MASK)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_STOP_MASK (0x80000U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_STOP_SHIFT (19U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_dtcp_dtcp_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_20_31_MASK (0xFFF00000U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_20_31_SHIFT (20U)
#define CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_DTC_LPCG_LPCG_DTCP_0_LPCG_lpcg_dtcp_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_DTC_Register_Masks */


/* CONNECTIVITY_LPCG_DTC - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__LPCG_DTCP base address */
#define CONNECTIVITY__LPCG_DTCP_BASE             (0x5B250000u)
/** Peripheral CONNECTIVITY__LPCG_DTCP base pointer */
#define CONNECTIVITY__LPCG_DTCP                  ((CONNECTIVITY_LPCG_DTC_Type *)CONNECTIVITY__LPCG_DTCP_BASE)
/** Array initializer of CONNECTIVITY_LPCG_DTC peripheral base addresses */
#define CONNECTIVITY_LPCG_DTC_BASE_ADDRS         { CONNECTIVITY__LPCG_DTCP_BASE }
/** Array initializer of CONNECTIVITY_LPCG_DTC peripheral base pointers */
#define CONNECTIVITY_LPCG_DTC_BASE_PTRS          { CONNECTIVITY__LPCG_DTCP }

/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_DTC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_EDMA Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer CONNECTIVITY_LPCG_EDMA Peripheral Access Layer
 * @{
 */

/** CONNECTIVITY_LPCG_EDMA - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_EDMA_0;                  /**< na, offset: 0x0 */
} CONNECTIVITY_LPCG_EDMA_Type;

/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_EDMA Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_EDMA_Register_Masks CONNECTIVITY_LPCG_EDMA Register Masks
 * @{
 */

/*! @name LPCG_LPCG_EDMA_0 - na */
/*! @{ */
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK (0x1U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT (0U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK (0x2U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT (1U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK (0x4U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT (2U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK (0x8U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT (3U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK (0x1FFF0U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT (4U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK (0x20000U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT (17U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK (0x40000U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT (18U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK (0x80000U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT (19U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK (0xFFF00000U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT (20U)
#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_EDMA_Register_Masks */


/* CONNECTIVITY_LPCG_EDMA - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__LPCG_EDMA base address */
#define CONNECTIVITY__LPCG_EDMA_BASE             (0x5B2A0000u)
/** Peripheral CONNECTIVITY__LPCG_EDMA base pointer */
#define CONNECTIVITY__LPCG_EDMA                  ((CONNECTIVITY_LPCG_EDMA_Type *)CONNECTIVITY__LPCG_EDMA_BASE)
/** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base addresses */
#define CONNECTIVITY_LPCG_EDMA_BASE_ADDRS        { CONNECTIVITY__LPCG_EDMA_BASE }
/** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base pointers */
#define CONNECTIVITY_LPCG_EDMA_BASE_PTRS         { CONNECTIVITY__LPCG_EDMA }

/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer
 * @{
 */

/** CONNECTIVITY_LPCG_ENET0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_ENET1_0;                 /**< na, offset: 0x0 */
  __IO uint32_t LPCG_LPCG_ENET1_4;                 /**< na, offset: 0x4 */
} CONNECTIVITY_LPCG_ENET0_Type;

/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_ENET0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_ENET0_Register_Masks CONNECTIVITY_LPCG_ENET0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_ENET1_0 - na */
/*! @{ */
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK (0x1U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT (0U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK (0x2U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT (1U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK (0x4U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT (2U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK (0x8U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT (3U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK (0x10U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT (4U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK (0x20U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT (5U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK (0x40U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT (6U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK (0x80U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT (7U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK (0x100U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT (8U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK (0x200U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT (9U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK (0x400U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT (10U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK (0x800U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT (11U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK (0x1000U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT (12U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK (0x2000U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT (13U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK (0x4000U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT (14U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK (0x8000U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT (15U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK (0x10000U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT (16U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK (0x20000U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT (17U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK (0x40000U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT (18U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK (0x80000U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT (19U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK (0x100000U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT (20U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK (0x200000U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT (21U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK (0x400000U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT (22U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK (0x800000U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT (23U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK (0xFF000000U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT (24U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK)
/*! @} */

/*! @name LPCG_LPCG_ENET1_4 - na */
/*! @{ */
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK (0x1U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT (0U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK (0x2U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT (1U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK (0x4U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT (2U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK (0x8U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT (3U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK (0xFFFFFFF0U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT (4U)
#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_ENET0_Register_Masks */


/* CONNECTIVITY_LPCG_ENET0 - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__LPCG_ENET0 base address */
#define CONNECTIVITY__LPCG_ENET0_BASE            (0x5B230000u)
/** Peripheral CONNECTIVITY__LPCG_ENET0 base pointer */
#define CONNECTIVITY__LPCG_ENET0                 ((CONNECTIVITY_LPCG_ENET0_Type *)CONNECTIVITY__LPCG_ENET0_BASE)
/** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base addresses */
#define CONNECTIVITY_LPCG_ENET0_BASE_ADDRS       { CONNECTIVITY__LPCG_ENET0_BASE }
/** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base pointers */
#define CONNECTIVITY_LPCG_ENET0_BASE_PTRS        { CONNECTIVITY__LPCG_ENET0 }

/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer
 * @{
 */

/** CONNECTIVITY_LPCG_ENET1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_ENET2_0;                 /**< na, offset: 0x0 */
  __IO uint32_t LPCG_LPCG_ENET2_4;                 /**< na, offset: 0x4 */
} CONNECTIVITY_LPCG_ENET1_Type;

/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_ENET1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_ENET1_Register_Masks CONNECTIVITY_LPCG_ENET1 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_ENET2_0 - na */
/*! @{ */
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK (0x1U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT (0U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK (0x2U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT (1U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK (0x4U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT (2U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK (0x8U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT (3U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK (0x10U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT (4U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK (0x20U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT (5U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK (0x40U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT (6U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK (0x80U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT (7U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK (0x100U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT (8U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK (0x200U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT (9U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK (0x400U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT (10U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK (0x800U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT (11U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK (0x1000U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT (12U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK (0x2000U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT (13U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK (0x4000U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT (14U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK (0x8000U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT (15U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK (0x10000U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT (16U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK (0x20000U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT (17U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK (0x40000U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT (18U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK (0x80000U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT (19U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK (0x100000U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT (20U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK (0x200000U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT (21U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK (0x400000U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT (22U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK (0x800000U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT (23U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK (0xFF000000U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT (24U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK)
/*! @} */

/*! @name LPCG_LPCG_ENET2_4 - na */
/*! @{ */
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK (0x1U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT (0U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK (0x2U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT (1U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK (0x4U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT (2U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK (0x8U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT (3U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK (0xFFFFFFF0U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT (4U)
#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_ENET1_Register_Masks */


/* CONNECTIVITY_LPCG_ENET1 - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__LPCG_ENET1 base address */
#define CONNECTIVITY__LPCG_ENET1_BASE            (0x5B240000u)
/** Peripheral CONNECTIVITY__LPCG_ENET1 base pointer */
#define CONNECTIVITY__LPCG_ENET1                 ((CONNECTIVITY_LPCG_ENET1_Type *)CONNECTIVITY__LPCG_ENET1_BASE)
/** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base addresses */
#define CONNECTIVITY_LPCG_ENET1_BASE_ADDRS       { CONNECTIVITY__LPCG_ENET1_BASE }
/** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base pointers */
#define CONNECTIVITY_LPCG_ENET1_BASE_PTRS        { CONNECTIVITY__LPCG_ENET1 }

/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_MLB Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer CONNECTIVITY_LPCG_MLB Peripheral Access Layer
 * @{
 */

/** CONNECTIVITY_LPCG_MLB - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_MLB_0;                   /**< na, offset: 0x0 */
} CONNECTIVITY_LPCG_MLB_Type;

/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_MLB Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_MLB_Register_Masks CONNECTIVITY_LPCG_MLB Register Masks
 * @{
 */

/*! @name LPCG_LPCG_MLB_0 - na */
/*! @{ */
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK (0x1U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT (0U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK (0x2U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT (1U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK (0x4U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT (2U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK (0x8U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT (3U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK (0xFFF0U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT (4U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK (0x10000U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT (16U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK (0x20000U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT (17U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK (0x40000U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT (18U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK (0x80000U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT (19U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK (0x100000U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT (20U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK (0x200000U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT (21U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK (0x400000U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT (22U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK (0x800000U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT (23U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK (0xFF000000U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT (24U)
#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_MLB_Register_Masks */


/* CONNECTIVITY_LPCG_MLB - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__LPCG_MLB base address */
#define CONNECTIVITY__LPCG_MLB_BASE              (0x5B260000u)
/** Peripheral CONNECTIVITY__LPCG_MLB base pointer */
#define CONNECTIVITY__LPCG_MLB                   ((CONNECTIVITY_LPCG_MLB_Type *)CONNECTIVITY__LPCG_MLB_BASE)
/** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base addresses */
#define CONNECTIVITY_LPCG_MLB_BASE_ADDRS         { CONNECTIVITY__LPCG_MLB_BASE }
/** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base pointers */
#define CONNECTIVITY_LPCG_MLB_BASE_PTRS          { CONNECTIVITY__LPCG_MLB }

/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer
 * @{
 */

/** CONNECTIVITY_LPCG_RAWNAND - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_RAWNAND_0;               /**< na, offset: 0x0 */
  __IO uint32_t LPCG_LPCG_RAWNAND_4;               /**< na, offset: 0x4 */
} CONNECTIVITY_LPCG_RAWNAND_Type;

/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_RAWNAND Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Register_Masks CONNECTIVITY_LPCG_RAWNAND Register Masks
 * @{
 */

/*! @name LPCG_LPCG_RAWNAND_0 - na */
/*! @{ */
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK (0x1U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT (0U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK (0x2U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT (1U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK (0x4U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT (2U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK (0x8U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT (3U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK (0x10U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT (4U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK (0x20U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT (5U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK (0x40U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT (6U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK (0x80U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT (7U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK (0x1FF00U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT (8U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK (0x20000U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT (17U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK (0x40000U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT (18U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK (0x80000U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT (19U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK (0x100000U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT (20U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK (0x200000U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT (21U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK (0x400000U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT (22U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK (0x800000U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT (23U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK (0xFF000000U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT (24U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK)
/*! @} */

/*! @name LPCG_LPCG_RAWNAND_4 - na */
/*! @{ */
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK (0x1FFFFU)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT (0U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK (0x20000U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT (17U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK (0x40000U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT (18U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK (0x80000U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT (19U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK (0xFFF00000U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT (20U)
#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Register_Masks */


/* CONNECTIVITY_LPCG_RAWNAND - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__LPCG_RAWNAND base address */
#define CONNECTIVITY__LPCG_RAWNAND_BASE          (0x5B290000u)
/** Peripheral CONNECTIVITY__LPCG_RAWNAND base pointer */
#define CONNECTIVITY__LPCG_RAWNAND               ((CONNECTIVITY_LPCG_RAWNAND_Type *)CONNECTIVITY__LPCG_RAWNAND_BASE)
/** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base addresses */
#define CONNECTIVITY_LPCG_RAWNAND_BASE_ADDRS     { CONNECTIVITY__LPCG_RAWNAND_BASE }
/** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base pointers */
#define CONNECTIVITY_LPCG_RAWNAND_BASE_PTRS      { CONNECTIVITY__LPCG_RAWNAND }

/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_USB2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB2 Peripheral Access Layer
 * @{
 */

/** CONNECTIVITY_LPCG_USB2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_USB2_0;                  /**< na, offset: 0x0 */
} CONNECTIVITY_LPCG_USB2_Type;

/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_USB2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_USB2_Register_Masks CONNECTIVITY_LPCG_USB2 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_USB2_0 - na */
/*! @{ */
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK (0x1FFFFU)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT (0U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK (0x20000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT (17U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK (0x40000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT (18U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK (0x80000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT (19U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK (0x100000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT (20U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK (0x200000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT (21U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK (0x400000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT (22U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK (0x800000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT (23U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK (0x1000000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT (24U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK (0x2000000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT (25U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK (0x4000000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT (26U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK (0x8000000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT (27U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK (0x10000000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT (28U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK (0x20000000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT (29U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK (0x40000000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT (30U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK (0x80000000U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT (31U)
#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_USB2_Register_Masks */


/* CONNECTIVITY_LPCG_USB2 - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__LPCG_USB2 base address */
#define CONNECTIVITY__LPCG_USB2_BASE             (0x5B270000u)
/** Peripheral CONNECTIVITY__LPCG_USB2 base pointer */
#define CONNECTIVITY__LPCG_USB2                  ((CONNECTIVITY_LPCG_USB2_Type *)CONNECTIVITY__LPCG_USB2_BASE)
/** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base addresses */
#define CONNECTIVITY_LPCG_USB2_BASE_ADDRS        { CONNECTIVITY__LPCG_USB2_BASE }
/** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base pointers */
#define CONNECTIVITY_LPCG_USB2_BASE_PTRS         { CONNECTIVITY__LPCG_USB2 }

/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_USB3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB3 Peripheral Access Layer
 * @{
 */

/** CONNECTIVITY_LPCG_USB3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_USB3_0;                  /**< na, offset: 0x0 */
} CONNECTIVITY_LPCG_USB3_Type;

/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_USB3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_USB3_Register_Masks CONNECTIVITY_LPCG_USB3 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_USB3_0 - na */
/*! @{ */
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK (0x1U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT (0U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK (0x2U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT (1U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK (0x4U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT (2U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK (0x8U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT (3U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK (0x10U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT (4U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK (0x20U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT (5U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK (0x40U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT (6U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK (0x80U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT (7U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK (0x1FF00U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT (8U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK (0x20000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT (17U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK (0x40000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT (18U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK (0x80000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT (19U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK (0x100000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT (20U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK (0x200000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT (21U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK (0x400000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT (22U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK (0x800000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT (23U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK (0x1000000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT (24U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK (0x2000000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT (25U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK (0x4000000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT (26U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK (0x8000000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT (27U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK (0x10000000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT (28U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK (0x20000000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT (29U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK (0x40000000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT (30U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK (0x80000000U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT (31U)
#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_USB3_Register_Masks */


/* CONNECTIVITY_LPCG_USB3 - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__LPCG_USB3 base address */
#define CONNECTIVITY__LPCG_USB3_BASE             (0x5B280000u)
/** Peripheral CONNECTIVITY__LPCG_USB3 base pointer */
#define CONNECTIVITY__LPCG_USB3                  ((CONNECTIVITY_LPCG_USB3_Type *)CONNECTIVITY__LPCG_USB3_BASE)
/** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base addresses */
#define CONNECTIVITY_LPCG_USB3_BASE_ADDRS        { CONNECTIVITY__LPCG_USB3_BASE }
/** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base pointers */
#define CONNECTIVITY_LPCG_USB3_BASE_PTRS         { CONNECTIVITY__LPCG_USB3 }

/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer
 * @{
 */

/** CONNECTIVITY_LPCG_USDHC0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_USDHC1_0;                /**< na, offset: 0x0 */
} CONNECTIVITY_LPCG_USDHC0_Type;

/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_USDHC0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_USDHC0_Register_Masks CONNECTIVITY_LPCG_USDHC0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_USDHC1_0 - na */
/*! @{ */
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK (0x1U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT (0U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK (0x2U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT (1U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK (0x4U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT (2U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK (0x8U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT (3U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK (0xFFF0U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT (4U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK (0x10000U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT (16U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK (0x20000U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT (17U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK (0x40000U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT (18U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK (0x80000U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT (19U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK (0x100000U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT (20U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK (0x200000U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT (21U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK (0x400000U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT (22U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK (0x800000U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT (23U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK (0xFF000000U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT (24U)
#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_USDHC0_Register_Masks */


/* CONNECTIVITY_LPCG_USDHC0 - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__LPCG_USDHC0 base address */
#define CONNECTIVITY__LPCG_USDHC0_BASE           (0x5B200000u)
/** Peripheral CONNECTIVITY__LPCG_USDHC0 base pointer */
#define CONNECTIVITY__LPCG_USDHC0                ((CONNECTIVITY_LPCG_USDHC0_Type *)CONNECTIVITY__LPCG_USDHC0_BASE)
/** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base addresses */
#define CONNECTIVITY_LPCG_USDHC0_BASE_ADDRS      { CONNECTIVITY__LPCG_USDHC0_BASE }
/** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base pointers */
#define CONNECTIVITY_LPCG_USDHC0_BASE_PTRS       { CONNECTIVITY__LPCG_USDHC0 }

/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer
 * @{
 */

/** CONNECTIVITY_LPCG_USDHC1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_USDHC2_0;                /**< na, offset: 0x0 */
} CONNECTIVITY_LPCG_USDHC1_Type;

/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_USDHC1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_USDHC1_Register_Masks CONNECTIVITY_LPCG_USDHC1 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_USDHC2_0 - na */
/*! @{ */
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK (0x1U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT (0U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK (0x2U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT (1U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK (0x4U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT (2U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK (0x8U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT (3U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK (0xFFF0U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT (4U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK (0x10000U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT (16U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK (0x20000U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT (17U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK (0x40000U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT (18U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK (0x80000U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT (19U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK (0x100000U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT (20U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK (0x200000U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT (21U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK (0x400000U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT (22U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK (0x800000U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT (23U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK (0xFF000000U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT (24U)
#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_USDHC1_Register_Masks */


/* CONNECTIVITY_LPCG_USDHC1 - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__LPCG_USDHC1 base address */
#define CONNECTIVITY__LPCG_USDHC1_BASE           (0x5B210000u)
/** Peripheral CONNECTIVITY__LPCG_USDHC1 base pointer */
#define CONNECTIVITY__LPCG_USDHC1                ((CONNECTIVITY_LPCG_USDHC1_Type *)CONNECTIVITY__LPCG_USDHC1_BASE)
/** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base addresses */
#define CONNECTIVITY_LPCG_USDHC1_BASE_ADDRS      { CONNECTIVITY__LPCG_USDHC1_BASE }
/** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base pointers */
#define CONNECTIVITY_LPCG_USDHC1_BASE_PTRS       { CONNECTIVITY__LPCG_USDHC1 }

/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_USDHC2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_USDHC2_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC2 Peripheral Access Layer
 * @{
 */

/** CONNECTIVITY_LPCG_USDHC2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_USDHC3_0;                /**< na, offset: 0x0 */
} CONNECTIVITY_LPCG_USDHC2_Type;

/* ----------------------------------------------------------------------------
   -- CONNECTIVITY_LPCG_USDHC2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CONNECTIVITY_LPCG_USDHC2_Register_Masks CONNECTIVITY_LPCG_USDHC2 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_USDHC3_0 - na */
/*! @{ */
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_0_0_MASK (0x1U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_0_0_SHIFT (0U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_0_0_MASK)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_SWEN_MASK (0x2U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_SWEN_SHIFT (1U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_2_2_MASK (0x4U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_2_2_SHIFT (2U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_2_2_MASK)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_STOP_MASK (0x8U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_STOP_SHIFT (3U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_perclk_STOP_MASK)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_4_15_MASK (0xFFF0U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_4_15_SHIFT (4U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_4_15_MASK)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_HWEN_MASK (0x10000U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_HWEN_SHIFT (16U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_HWEN_MASK)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_SWEN_AND_usdhc3_ipg_clk_SWEN_MASK (0x20000U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_SWEN_AND_usdhc3_ipg_clk_SWEN_SHIFT (17U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_SWEN_AND_usdhc3_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_SWEN_AND_usdhc3_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_SWEN_AND_usdhc3_ipg_clk_SWEN_MASK)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_18_18_MASK (0x40000U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_18_18_SHIFT (18U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_18_18_MASK)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_STOP_AND_usdhc3_ipg_clk_STOP_MASK (0x80000U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_STOP_AND_usdhc3_ipg_clk_STOP_SHIFT (19U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_STOP_AND_usdhc3_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_STOP_AND_usdhc3_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_ipg_clk_s_STOP_AND_usdhc3_ipg_clk_STOP_MASK)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_20_20_MASK (0x100000U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_20_20_SHIFT (20U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_20_20_MASK)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_SWEN_MASK (0x200000U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_SWEN_SHIFT (21U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_SWEN_MASK)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_22_22_MASK (0x400000U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_22_22_SHIFT (22U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_22_22_MASK)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_STOP_MASK (0x800000U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_STOP_SHIFT (23U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_usdhc3_hclk_STOP_MASK)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_24_31_MASK (0xFF000000U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_24_31_SHIFT (24U)
#define CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC2_LPCG_LPCG_USDHC3_0_LPCG_lpcg_usdhc3_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_USDHC2_Register_Masks */


/* CONNECTIVITY_LPCG_USDHC2 - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__LPCG_USDHC2 base address */
#define CONNECTIVITY__LPCG_USDHC2_BASE           (0x5B220000u)
/** Peripheral CONNECTIVITY__LPCG_USDHC2 base pointer */
#define CONNECTIVITY__LPCG_USDHC2                ((CONNECTIVITY_LPCG_USDHC2_Type *)CONNECTIVITY__LPCG_USDHC2_BASE)
/** Array initializer of CONNECTIVITY_LPCG_USDHC2 peripheral base addresses */
#define CONNECTIVITY_LPCG_USDHC2_BASE_ADDRS      { CONNECTIVITY__LPCG_USDHC2_BASE }
/** Array initializer of CONNECTIVITY_LPCG_USDHC2 peripheral base pointers */
#define CONNECTIVITY_LPCG_USDHC2_BASE_PTRS       { CONNECTIVITY__LPCG_USDHC2 }

/*!
 * @}
 */ /* end of group CONNECTIVITY_LPCG_USDHC2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DBLOG_LPCG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DBLOG_LPCG_Peripheral_Access_Layer DBLOG_LPCG Peripheral Access Layer
 * @{
 */

/** DBLOG_LPCG - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_DBLOG_IDLE_0;            /**< na, offset: 0x0 */
  __IO uint32_t LPCG_LPCG_DBLOG_IDLE_4;            /**< na, offset: 0x4 */
} DBLOG_LPCG_Type;

/* ----------------------------------------------------------------------------
   -- DBLOG_LPCG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DBLOG_LPCG_Register_Masks DBLOG_LPCG Register Masks
 * @{
 */

/*! @name LPCG_LPCG_DBLOG_IDLE_0 - na */
/*! @{ */
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_0_0_MASK (0x1U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_0_0_SHIFT (0U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_0_0_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_0_0_MASK)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_SWEN_MASK (0x2U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_SWEN_SHIFT (1U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_SWEN_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_SWEN_MASK)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_2_2_MASK (0x4U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_2_2_SHIFT (2U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_2_2_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_2_2_MASK)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_STOP_MASK (0x8U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_STOP_SHIFT (3U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_STOP_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_lpcg_swhw_gated_STOP_MASK)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_4_31_SHIFT (4U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_4_31_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_0_LPCG_lpcg_dblog_idle_0_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_LPCG_DBLOG_IDLE_4 - na */
/*! @{ */
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_0_4_MASK (0x1FU)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_0_4_SHIFT (0U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_0_4(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_0_4_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_0_4_MASK)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_SWEN_MASK (0x20U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_SWEN_SHIFT (5U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_SWEN_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_SWEN_MASK)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_6_6_MASK (0x40U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_6_6_SHIFT (6U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_6_6_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_6_6_MASK)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_STOP_MASK (0x80U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_STOP_SHIFT (7U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_STOP_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_lpcg_hw_gated_STOP_MASK)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_8_31_MASK (0xFFFFFF00U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_8_31_SHIFT (8U)
#define DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_8_31_SHIFT)) & DBLOG_LPCG_LPCG_LPCG_DBLOG_IDLE_4_LPCG_lpcg_dblog_idle_4_reserved_8_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DBLOG_LPCG_Register_Masks */


/* DBLOG_LPCG - Peripheral instance base addresses */
/** Peripheral DBLOG__LPCG_CLK base address */
#define DBLOG__LPCG_CLK_BASE                     (0x510F0000u)
/** Peripheral DBLOG__LPCG_CLK base pointer */
#define DBLOG__LPCG_CLK                          ((DBLOG_LPCG_Type *)DBLOG__LPCG_CLK_BASE)
/** Array initializer of DBLOG_LPCG peripheral base addresses */
#define DBLOG_LPCG_BASE_ADDRS                    { DBLOG__LPCG_CLK_BASE }
/** Array initializer of DBLOG_LPCG peripheral base pointers */
#define DBLOG_LPCG_BASE_PTRS                     { DBLOG__LPCG_CLK }

/*!
 * @}
 */ /* end of group DBLOG_LPCG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DB_LPCG_BN Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DB_LPCG_BN_Peripheral_Access_Layer DB_LPCG_BN Peripheral Access Layer
 * @{
 */

/** DB_LPCG_BN - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_BN_0;                    /**< na, offset: 0x0 */
} DB_LPCG_BN_Type;

/* ----------------------------------------------------------------------------
   -- DB_LPCG_BN Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DB_LPCG_BN_Register_Masks DB_LPCG_BN Register Masks
 * @{
 */

/*! @name LPCG_LPCG_BN_0 - na */
/*! @{ */
#define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_0_0_MASK (0x1U)
#define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_0_0_SHIFT (0U)
#define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_0_0_SHIFT)) & DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_0_0_MASK)
#define DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_SWEN_MASK (0x2U)
#define DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_SWEN_SHIFT (1U)
#define DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_SWEN_SHIFT)) & DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_SWEN_MASK)
#define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_2_2_MASK (0x4U)
#define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_2_2_SHIFT (2U)
#define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_2_2_SHIFT)) & DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_2_2_MASK)
#define DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_STOP_MASK (0x8U)
#define DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_STOP_SHIFT (3U)
#define DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_STOP_SHIFT)) & DB_LPCG_BN_LPCG_LPCG_BN_0_bn_gated_STOP_MASK)
#define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_4_31_SHIFT (4U)
#define DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_4_31_SHIFT)) & DB_LPCG_BN_LPCG_LPCG_BN_0_LPCG_lpcg_bn_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DB_LPCG_BN_Register_Masks */


/* DB_LPCG_BN - Peripheral instance base addresses */
/** Peripheral DB__LPCG_BN_GATED base address */
#define DB__LPCG_BN_GATED_BASE                   (0x5CEF0000u)
/** Peripheral DB__LPCG_BN_GATED base pointer */
#define DB__LPCG_BN_GATED                        ((DB_LPCG_BN_Type *)DB__LPCG_BN_GATED_BASE)
/** Array initializer of DB_LPCG_BN peripheral base addresses */
#define DB_LPCG_BN_BASE_ADDRS                    { DB__LPCG_BN_GATED_BASE }
/** Array initializer of DB_LPCG_BN peripheral base pointers */
#define DB_LPCG_BN_BASE_PTRS                     { DB__LPCG_BN_GATED }

/*!
 * @}
 */ /* end of group DB_LPCG_BN_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DB_LPCG_PG0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DB_LPCG_PG0_Peripheral_Access_Layer DB_LPCG_PG0 Peripheral Access Layer
 * @{
 */

/** DB_LPCG_PG0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_PG0_0;                   /**< na, offset: 0x0 */
} DB_LPCG_PG0_Type;

/* ----------------------------------------------------------------------------
   -- DB_LPCG_PG0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DB_LPCG_PG0_Register_Masks DB_LPCG_PG0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_PG0_0 - na */
/*! @{ */
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_0_0_MASK (0x1U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_0_0_SHIFT (0U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_0_0_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_0_0_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_SWEN_MASK (0x2U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_SWEN_SHIFT (1U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_SWEN_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_SWEN_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_2_2_MASK (0x4U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_2_2_SHIFT (2U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_2_2_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_2_2_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_STOP_MASK (0x8U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_STOP_SHIFT (3U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_STOP_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_A_gated_STOP_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_4_4_MASK (0x10U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_4_4_SHIFT (4U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_4_4_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_4_4_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_SWEN_MASK (0x20U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_SWEN_SHIFT (5U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_SWEN_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_SWEN_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_6_6_MASK (0x40U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_6_6_SHIFT (6U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_6_6_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_6_6_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_STOP_MASK (0x80U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_STOP_SHIFT (7U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_STOP_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_B_gated_STOP_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_8_8_MASK (0x100U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_8_8_SHIFT (8U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_8_8_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_8_8_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_SWEN_MASK (0x200U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_SWEN_SHIFT (9U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_SWEN_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_SWEN_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_10_10_MASK (0x400U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_10_10_SHIFT (10U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_10_10_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_10_10_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_STOP_MASK (0x800U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_STOP_SHIFT (11U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_STOP_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_C_gated_STOP_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_12_12_MASK (0x1000U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_12_12_SHIFT (12U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_12_12_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_12_12_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_SWEN_MASK (0x2000U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_SWEN_SHIFT (13U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_SWEN_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_SWEN_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_14_14_MASK (0x4000U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_14_14_SHIFT (14U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_14_14_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_14_14_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_STOP_MASK (0x8000U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_STOP_SHIFT (15U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_STOP_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_D_gated_STOP_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_16_16_MASK (0x10000U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_16_16_SHIFT (16U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_16_16(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_16_16_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_16_16_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_SWEN_MASK (0x20000U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_SWEN_SHIFT (17U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_SWEN_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_SWEN_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_18_18_MASK (0x40000U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_18_18_SHIFT (18U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_18_18_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_18_18_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_STOP_MASK (0x80000U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_STOP_SHIFT (19U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_STOP_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_E_gated_STOP_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_20_20_MASK (0x100000U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_20_20_SHIFT (20U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_20_20_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_20_20_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_SWEN_MASK (0x200000U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_SWEN_SHIFT (21U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_SWEN_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_SWEN_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_22_22_MASK (0x400000U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_22_22_SHIFT (22U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_22_22_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_22_22_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_STOP_MASK (0x800000U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_STOP_SHIFT (23U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_STOP_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_pg0_F_gated_STOP_MASK)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_24_31_MASK (0xFF000000U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_24_31_SHIFT (24U)
#define DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_24_31_SHIFT)) & DB_LPCG_PG0_LPCG_LPCG_PG0_0_LPCG_lpcg_pg0_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DB_LPCG_PG0_Register_Masks */


/* DB_LPCG_PG0 - Peripheral instance base addresses */
/** Peripheral DB__LPCG_PG0 base address */
#define DB__LPCG_PG0_BASE                        (0x5C8F0000u)
/** Peripheral DB__LPCG_PG0 base pointer */
#define DB__LPCG_PG0                             ((DB_LPCG_PG0_Type *)DB__LPCG_PG0_BASE)
/** Array initializer of DB_LPCG_PG0 peripheral base addresses */
#define DB_LPCG_PG0_BASE_ADDRS                   { DB__LPCG_PG0_BASE }
/** Array initializer of DB_LPCG_PG0 peripheral base pointers */
#define DB_LPCG_PG0_BASE_PTRS                    { DB__LPCG_PG0 }

/*!
 * @}
 */ /* end of group DB_LPCG_PG0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DB_LPCG_PG1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DB_LPCG_PG1_Peripheral_Access_Layer DB_LPCG_PG1 Peripheral Access Layer
 * @{
 */

/** DB_LPCG_PG1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_PG1_0;                   /**< na, offset: 0x0 */
} DB_LPCG_PG1_Type;

/* ----------------------------------------------------------------------------
   -- DB_LPCG_PG1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DB_LPCG_PG1_Register_Masks DB_LPCG_PG1 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_PG1_0 - na */
/*! @{ */
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_0_0_MASK (0x1U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_0_0_SHIFT (0U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_0_0_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_0_0_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_SWEN_MASK (0x2U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_SWEN_SHIFT (1U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_SWEN_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_SWEN_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_2_2_MASK (0x4U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_2_2_SHIFT (2U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_2_2_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_2_2_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_STOP_MASK (0x8U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_STOP_SHIFT (3U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_STOP_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_A_gated_STOP_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_4_4_MASK (0x10U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_4_4_SHIFT (4U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_4_4_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_4_4_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_SWEN_MASK (0x20U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_SWEN_SHIFT (5U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_SWEN_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_SWEN_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_6_6_MASK (0x40U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_6_6_SHIFT (6U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_6_6_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_6_6_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_STOP_MASK (0x80U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_STOP_SHIFT (7U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_STOP_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_B_gated_STOP_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_8_8_MASK (0x100U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_8_8_SHIFT (8U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_8_8_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_8_8_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_SWEN_MASK (0x200U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_SWEN_SHIFT (9U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_SWEN_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_SWEN_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_10_10_MASK (0x400U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_10_10_SHIFT (10U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_10_10_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_10_10_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_STOP_MASK (0x800U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_STOP_SHIFT (11U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_STOP_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_C_gated_STOP_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_12_12_MASK (0x1000U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_12_12_SHIFT (12U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_12_12_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_12_12_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_SWEN_MASK (0x2000U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_SWEN_SHIFT (13U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_SWEN_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_SWEN_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_14_14_MASK (0x4000U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_14_14_SHIFT (14U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_14_14_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_14_14_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_STOP_MASK (0x8000U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_STOP_SHIFT (15U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_STOP_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_D_gated_STOP_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_16_16_MASK (0x10000U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_16_16_SHIFT (16U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_16_16(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_16_16_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_16_16_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_SWEN_MASK (0x20000U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_SWEN_SHIFT (17U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_SWEN_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_SWEN_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_18_18_MASK (0x40000U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_18_18_SHIFT (18U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_18_18_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_18_18_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_STOP_MASK (0x80000U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_STOP_SHIFT (19U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_STOP_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_E_gated_STOP_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_20_20_MASK (0x100000U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_20_20_SHIFT (20U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_20_20_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_20_20_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_SWEN_MASK (0x200000U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_SWEN_SHIFT (21U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_SWEN_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_SWEN_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_22_22_MASK (0x400000U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_22_22_SHIFT (22U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_22_22_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_22_22_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_STOP_MASK (0x800000U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_STOP_SHIFT (23U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_STOP_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_pg1_F_gated_STOP_MASK)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_24_31_MASK (0xFF000000U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_24_31_SHIFT (24U)
#define DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_24_31_SHIFT)) & DB_LPCG_PG1_LPCG_LPCG_PG1_0_LPCG_lpcg_pg1_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DB_LPCG_PG1_Register_Masks */


/* DB_LPCG_PG1 - Peripheral instance base addresses */
/** Peripheral DB__LPCG_PG1 base address */
#define DB__LPCG_PG1_BASE                        (0x5C9F0000u)
/** Peripheral DB__LPCG_PG1 base pointer */
#define DB__LPCG_PG1                             ((DB_LPCG_PG1_Type *)DB__LPCG_PG1_BASE)
/** Array initializer of DB_LPCG_PG1 peripheral base addresses */
#define DB_LPCG_PG1_BASE_ADDRS                   { DB__LPCG_PG1_BASE }
/** Array initializer of DB_LPCG_PG1 peripheral base pointers */
#define DB_LPCG_PG1_BASE_PTRS                    { DB__LPCG_PG1 }

/*!
 * @}
 */ /* end of group DB_LPCG_PG1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DB_LPCG_PG2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DB_LPCG_PG2_Peripheral_Access_Layer DB_LPCG_PG2 Peripheral Access Layer
 * @{
 */

/** DB_LPCG_PG2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_PG2_0;                   /**< na, offset: 0x0 */
} DB_LPCG_PG2_Type;

/* ----------------------------------------------------------------------------
   -- DB_LPCG_PG2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DB_LPCG_PG2_Register_Masks DB_LPCG_PG2 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_PG2_0 - na */
/*! @{ */
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_0_0_MASK (0x1U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_0_0_SHIFT (0U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_0_0_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_0_0_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_SWEN_MASK (0x2U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_SWEN_SHIFT (1U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_SWEN_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_SWEN_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_2_2_MASK (0x4U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_2_2_SHIFT (2U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_2_2_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_2_2_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_STOP_MASK (0x8U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_STOP_SHIFT (3U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_STOP_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_A_gated_STOP_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_4_4_MASK (0x10U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_4_4_SHIFT (4U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_4_4_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_4_4_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_SWEN_MASK (0x20U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_SWEN_SHIFT (5U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_SWEN_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_SWEN_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_6_6_MASK (0x40U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_6_6_SHIFT (6U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_6_6_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_6_6_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_STOP_MASK (0x80U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_STOP_SHIFT (7U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_STOP_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_B_gated_STOP_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_8_8_MASK (0x100U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_8_8_SHIFT (8U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_8_8_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_8_8_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_SWEN_MASK (0x200U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_SWEN_SHIFT (9U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_SWEN_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_SWEN_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_10_10_MASK (0x400U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_10_10_SHIFT (10U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_10_10_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_10_10_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_STOP_MASK (0x800U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_STOP_SHIFT (11U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_STOP_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_C_gated_STOP_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_12_12_MASK (0x1000U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_12_12_SHIFT (12U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_12_12_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_12_12_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_SWEN_MASK (0x2000U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_SWEN_SHIFT (13U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_SWEN_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_SWEN_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_14_14_MASK (0x4000U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_14_14_SHIFT (14U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_14_14_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_14_14_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_STOP_MASK (0x8000U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_STOP_SHIFT (15U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_STOP_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_D_gated_STOP_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_16_16_MASK (0x10000U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_16_16_SHIFT (16U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_16_16(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_16_16_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_16_16_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_SWEN_MASK (0x20000U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_SWEN_SHIFT (17U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_SWEN_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_SWEN_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_18_18_MASK (0x40000U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_18_18_SHIFT (18U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_18_18_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_18_18_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_STOP_MASK (0x80000U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_STOP_SHIFT (19U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_STOP_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_E_gated_STOP_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_20_20_MASK (0x100000U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_20_20_SHIFT (20U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_20_20_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_20_20_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_SWEN_MASK (0x200000U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_SWEN_SHIFT (21U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_SWEN_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_SWEN_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_22_22_MASK (0x400000U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_22_22_SHIFT (22U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_22_22_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_22_22_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_STOP_MASK (0x800000U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_STOP_SHIFT (23U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_STOP_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_pg2_F_gated_STOP_MASK)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_24_31_MASK (0xFF000000U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_24_31_SHIFT (24U)
#define DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_24_31_SHIFT)) & DB_LPCG_PG2_LPCG_LPCG_PG2_0_LPCG_lpcg_pg2_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DB_LPCG_PG2_Register_Masks */


/* DB_LPCG_PG2 - Peripheral instance base addresses */
/** Peripheral DB__LPCG_PG2 base address */
#define DB__LPCG_PG2_BASE                        (0x5CAF0000u)
/** Peripheral DB__LPCG_PG2 base pointer */
#define DB__LPCG_PG2                             ((DB_LPCG_PG2_Type *)DB__LPCG_PG2_BASE)
/** Array initializer of DB_LPCG_PG2 peripheral base addresses */
#define DB_LPCG_PG2_BASE_ADDRS                   { DB__LPCG_PG2_BASE }
/** Array initializer of DB_LPCG_PG2 peripheral base pointers */
#define DB_LPCG_PG2_BASE_PTRS                    { DB__LPCG_PG2 }

/*!
 * @}
 */ /* end of group DB_LPCG_PG2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DB_LPCG_PG3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DB_LPCG_PG3_Peripheral_Access_Layer DB_LPCG_PG3 Peripheral Access Layer
 * @{
 */

/** DB_LPCG_PG3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_PG3_0;                   /**< na, offset: 0x0 */
} DB_LPCG_PG3_Type;

/* ----------------------------------------------------------------------------
   -- DB_LPCG_PG3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DB_LPCG_PG3_Register_Masks DB_LPCG_PG3 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_PG3_0 - na */
/*! @{ */
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_0_0_MASK (0x1U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_0_0_SHIFT (0U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_0_0_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_0_0_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_SWEN_MASK (0x2U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_SWEN_SHIFT (1U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_SWEN_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_SWEN_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_2_2_MASK (0x4U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_2_2_SHIFT (2U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_2_2_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_2_2_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_STOP_MASK (0x8U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_STOP_SHIFT (3U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_STOP_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_A_gated_STOP_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_4_4_MASK (0x10U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_4_4_SHIFT (4U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_4_4_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_4_4_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_SWEN_MASK (0x20U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_SWEN_SHIFT (5U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_SWEN_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_SWEN_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_6_6_MASK (0x40U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_6_6_SHIFT (6U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_6_6_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_6_6_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_STOP_MASK (0x80U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_STOP_SHIFT (7U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_STOP_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_B_gated_STOP_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_8_8_MASK (0x100U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_8_8_SHIFT (8U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_8_8_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_8_8_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_SWEN_MASK (0x200U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_SWEN_SHIFT (9U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_SWEN_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_SWEN_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_10_10_MASK (0x400U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_10_10_SHIFT (10U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_10_10_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_10_10_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_STOP_MASK (0x800U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_STOP_SHIFT (11U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_STOP_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_C_gated_STOP_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_12_12_MASK (0x1000U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_12_12_SHIFT (12U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_12_12_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_12_12_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_SWEN_MASK (0x2000U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_SWEN_SHIFT (13U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_SWEN_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_SWEN_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_14_14_MASK (0x4000U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_14_14_SHIFT (14U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_14_14_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_14_14_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_STOP_MASK (0x8000U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_STOP_SHIFT (15U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_STOP_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_D_gated_STOP_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_16_16_MASK (0x10000U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_16_16_SHIFT (16U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_16_16(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_16_16_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_16_16_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_SWEN_MASK (0x20000U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_SWEN_SHIFT (17U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_SWEN_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_SWEN_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_18_18_MASK (0x40000U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_18_18_SHIFT (18U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_18_18_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_18_18_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_STOP_MASK (0x80000U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_STOP_SHIFT (19U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_STOP_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_E_gated_STOP_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_20_20_MASK (0x100000U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_20_20_SHIFT (20U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_20_20_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_20_20_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_SWEN_MASK (0x200000U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_SWEN_SHIFT (21U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_SWEN_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_SWEN_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_22_22_MASK (0x400000U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_22_22_SHIFT (22U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_22_22_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_22_22_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_STOP_MASK (0x800000U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_STOP_SHIFT (23U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_STOP_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_pg3_F_gated_STOP_MASK)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_24_31_MASK (0xFF000000U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_24_31_SHIFT (24U)
#define DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_24_31_SHIFT)) & DB_LPCG_PG3_LPCG_LPCG_PG3_0_LPCG_lpcg_pg3_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DB_LPCG_PG3_Register_Masks */


/* DB_LPCG_PG3 - Peripheral instance base addresses */
/** Peripheral DB__LPCG_PG3 base address */
#define DB__LPCG_PG3_BASE                        (0x5CBF0000u)
/** Peripheral DB__LPCG_PG3 base pointer */
#define DB__LPCG_PG3                             ((DB_LPCG_PG3_Type *)DB__LPCG_PG3_BASE)
/** Array initializer of DB_LPCG_PG3 peripheral base addresses */
#define DB_LPCG_PG3_BASE_ADDRS                   { DB__LPCG_PG3_BASE }
/** Array initializer of DB_LPCG_PG3 peripheral base pointers */
#define DB_LPCG_PG3_BASE_PTRS                    { DB__LPCG_PG3 }

/*!
 * @}
 */ /* end of group DB_LPCG_PG3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DC_LPCG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DC_LPCG_Peripheral_Access_Layer DC_LPCG Peripheral Access Layer
 * @{
 */

/** DC_LPCG - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_DC_LPCG_0;                    /**< na, offset: 0x0 */
  __IO uint32_t LPCG_DC_LPCG_4;                    /**< na, offset: 0x4 */
  __IO uint32_t LPCG_DC_LPCG_8;                    /**< na, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t LPCG_DC_LPCG_16;                   /**< na, offset: 0x10 */
  __IO uint32_t LPCG_DC_LPCG_20;                   /**< na, offset: 0x14 */
  __IO uint32_t LPCG_DC_LPCG_24;                   /**< na, offset: 0x18 */
  __IO uint32_t LPCG_DC_LPCG_28;                   /**< na, offset: 0x1C */
  __IO uint32_t LPCG_DC_LPCG_32;                   /**< na, offset: 0x20 */
  __IO uint32_t LPCG_DC_LPCG_36;                   /**< na, offset: 0x24 */
  __IO uint32_t LPCG_DC_LPCG_40;                   /**< na, offset: 0x28 */
  __IO uint32_t LPCG_DC_LPCG_44;                   /**< na, offset: 0x2C */
  __IO uint32_t LPCG_DC_LPCG_48;                   /**< na, offset: 0x30 */
  __IO uint32_t LPCG_DC_LPCG_52;                   /**< na, offset: 0x34 */
  __IO uint32_t LPCG_DC_LPCG_56;                   /**< na, offset: 0x38 */
  __IO uint32_t LPCG_DC_LPCG_60;                   /**< na, offset: 0x3C */
  __IO uint32_t LPCG_DC_LPCG_64;                   /**< na, offset: 0x40 */
  __IO uint32_t LPCG_DC_LPCG_68;                   /**< na, offset: 0x44 */
  __IO uint32_t LPCG_DC_LPCG_72;                   /**< na, offset: 0x48 */
} DC_LPCG_Type;

/* ----------------------------------------------------------------------------
   -- DC_LPCG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DC_LPCG_Register_Masks DC_LPCG Register Masks
 * @{
 */

/*! @name LPCG_DC_LPCG_0 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK (0x1U)
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK)
#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK (0x2U)
#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT (1U)
#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN(x)  (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK (0x4U)
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT (2U)
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK)
#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK (0x8U)
#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT (3U)
#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP(x)  (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK (0x10U)
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT (4U)
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK)
#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK (0x20U)
#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT (5U)
#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN(x)  (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK (0x40U)
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT (6U)
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK)
#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK (0x80U)
#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT (7U)
#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP(x)  (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK (0xFFFFFF00U)
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT (8U)
#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_4 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK (0xFFFFU)
#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK (0xFFF00000U)
#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_8 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK (0xFFFFU)
#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK (0xFFF00000U)
#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_16 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK (0xFFFFU)
#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK (0xFFF00000U)
#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_20 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK (0xFFFFU)
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK (0x100000U)
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK (0x200000U)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT (21U)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK (0x400000U)
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT (22U)
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK (0x800000U)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT (23U)
#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK (0xFF000000U)
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT (24U)
#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_24 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK (0xFFFFU)
#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_MASK (0x100000U)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_MASK (0x200000U)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_SHIFT (21U)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_MASK (0x400000U)
#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_SHIFT (22U)
#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_MASK)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_MASK (0x800000U)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_SHIFT (23U)
#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_MASK (0xFF000000U)
#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_SHIFT (24U)
#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_28 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_MASK (0x1U)
#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_MASK)
#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_MASK (0x2U)
#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_SHIFT (1U)
#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_MASK (0x4U)
#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_SHIFT (2U)
#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_MASK)
#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_MASK (0x8U)
#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_SHIFT (3U)
#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_MASK (0xFFFFFFF0U)
#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_SHIFT (4U)
#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_32 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_MASK (0x1U)
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_MASK)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_MASK (0x2U)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_SHIFT (1U)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_MASK (0x4U)
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_SHIFT (2U)
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_MASK)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_MASK (0x8U)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_SHIFT (3U)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_MASK (0xFFF0U)
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_SHIFT (4U)
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_MASK (0xFFF00000U)
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_36 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_MASK (0x1U)
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_MASK)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_MASK (0x2U)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_SHIFT (1U)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_MASK (0x4U)
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_SHIFT (2U)
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_MASK)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_MASK (0x8U)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_SHIFT (3U)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_MASK (0xFFF0U)
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_SHIFT (4U)
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_MASK (0xFFF00000U)
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_40 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_MASK (0x1U)
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_MASK)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_MASK (0x2U)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_SHIFT (1U)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_MASK (0x4U)
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_SHIFT (2U)
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_MASK)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_MASK (0x8U)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_SHIFT (3U)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_MASK (0xFFF0U)
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_SHIFT (4U)
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_MASK (0xFFF00000U)
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_44 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_MASK (0xFFFFU)
#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_MASK (0x100000U)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_MASK (0x200000U)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_SHIFT (21U)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_MASK (0x400000U)
#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_SHIFT (22U)
#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_MASK)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_MASK (0x800000U)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_SHIFT (23U)
#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_MASK (0xFF000000U)
#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_SHIFT (24U)
#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_48 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_MASK (0x1U)
#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_MASK)
#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_MASK (0x2U)
#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_SHIFT (1U)
#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_MASK (0x4U)
#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_SHIFT (2U)
#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_MASK)
#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_MASK (0x8U)
#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_SHIFT (3U)
#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_MASK (0xFFFFFFF0U)
#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_SHIFT (4U)
#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_52 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_MASK (0x1U)
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_MASK)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_MASK (0x2U)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_SHIFT (1U)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_MASK (0x4U)
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_SHIFT (2U)
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_MASK)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_MASK (0x8U)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_SHIFT (3U)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_MASK (0xFFF0U)
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_SHIFT (4U)
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_MASK (0xFFF00000U)
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_56 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_MASK (0x1U)
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_MASK)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_MASK (0x2U)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_SHIFT (1U)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_MASK (0x4U)
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_SHIFT (2U)
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_MASK)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_MASK (0x8U)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_SHIFT (3U)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_MASK (0xFFF0U)
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_SHIFT (4U)
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_MASK (0xFFF00000U)
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_60 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_MASK (0x1U)
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_MASK)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_MASK (0x2U)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_SHIFT (1U)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_MASK (0x4U)
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_SHIFT (2U)
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_MASK)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_MASK (0x8U)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_SHIFT (3U)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_MASK (0xFFF0U)
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_SHIFT (4U)
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_MASK (0xFFF00000U)
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_64 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_MASK (0x1U)
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_MASK)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_MASK (0x2U)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_SHIFT (1U)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_MASK (0x4U)
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_SHIFT (2U)
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_MASK)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_MASK (0x8U)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_SHIFT (3U)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_MASK (0xFFF0U)
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_SHIFT (4U)
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_MASK (0xFFF00000U)
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_68 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_MASK (0x1U)
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_MASK)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_MASK (0x2U)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_SHIFT (1U)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_MASK (0x4U)
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_SHIFT (2U)
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_MASK)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_MASK (0x8U)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_SHIFT (3U)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_MASK (0xFFF0U)
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_SHIFT (4U)
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_MASK (0xFFF00000U)
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DC_LPCG_72 - na */
/*! @{ */
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_MASK (0x1U)
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_SHIFT (0U)
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_MASK)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_MASK (0x2U)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_SHIFT (1U)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_MASK (0x4U)
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_SHIFT (2U)
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_MASK)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_MASK (0x8U)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_SHIFT (3U)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_MASK (0xFFF0U)
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_SHIFT (4U)
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_MASK)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_MASK (0x10000U)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_SHIFT (16U)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_MASK (0x20000U)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_SHIFT (17U)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_MASK)
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_MASK (0x40000U)
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_SHIFT (18U)
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_MASK)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_MASK (0x80000U)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_SHIFT (19U)
#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_MASK)
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_MASK (0xFFF00000U)
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_SHIFT (20U)
#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DC_LPCG_Register_Masks */


/* DC_LPCG - Peripheral instance base addresses */
/** Peripheral DC_0__LPCG_DSP0_CLK base address */
#define DC_0__LPCG_DSP0_CLK_BASE                 (0x56010000u)
/** Peripheral DC_0__LPCG_DSP0_CLK base pointer */
#define DC_0__LPCG_DSP0_CLK                      ((DC_LPCG_Type *)DC_0__LPCG_DSP0_CLK_BASE)
/** Peripheral DC_1__LPCG_DSP0_CLK base address */
#define DC_1__LPCG_DSP0_CLK_BASE                 (0x57010000u)
/** Peripheral DC_1__LPCG_DSP0_CLK base pointer */
#define DC_1__LPCG_DSP0_CLK                      ((DC_LPCG_Type *)DC_1__LPCG_DSP0_CLK_BASE)
/** Array initializer of DC_LPCG peripheral base addresses */
#define DC_LPCG_BASE_ADDRS                       { DC_0__LPCG_DSP0_CLK_BASE, DC_1__LPCG_DSP0_CLK_BASE }
/** Array initializer of DC_LPCG peripheral base pointers */
#define DC_LPCG_BASE_PTRS                        { DC_0__LPCG_DSP0_CLK, DC_1__LPCG_DSP0_CLK }

/*!
 * @}
 */ /* end of group DC_LPCG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DI_HDMI_LPCG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DI_HDMI_LPCG_Peripheral_Access_Layer DI_HDMI_LPCG Peripheral Access Layer
 * @{
 */

/** DI_HDMI_LPCG - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_DI_HDMI_LPCG_0;               /**< na, offset: 0x0 */
  __IO uint32_t LPCG_DI_HDMI_LPCG_4;               /**< na, offset: 0x4 */
  __IO uint32_t LPCG_DI_HDMI_LPCG_8;               /**< na, offset: 0x8 */
  __IO uint32_t LPCG_DI_HDMI_LPCG_12;              /**< na, offset: 0xC */
  __IO uint32_t LPCG_DI_HDMI_LPCG_16;              /**< na, offset: 0x10 */
  __IO uint32_t LPCG_DI_HDMI_LPCG_20;              /**< na, offset: 0x14 */
  __IO uint32_t LPCG_DI_HDMI_LPCG_24;              /**< na, offset: 0x18 */
  __IO uint32_t LPCG_DI_HDMI_LPCG_28;              /**< na, offset: 0x1C */
  __IO uint32_t LPCG_DI_HDMI_LPCG_32;              /**< na, offset: 0x20 */
  __IO uint32_t LPCG_DI_HDMI_LPCG_36;              /**< na, offset: 0x24 */
  __IO uint32_t LPCG_DI_HDMI_LPCG_40;              /**< na, offset: 0x28 */
  __IO uint32_t LPCG_DI_HDMI_LPCG_44;              /**< na, offset: 0x2C */
} DI_HDMI_LPCG_Type;

/* ----------------------------------------------------------------------------
   -- DI_HDMI_LPCG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DI_HDMI_LPCG_Register_Masks DI_HDMI_LPCG Register Masks
 * @{
 */

/*! @name LPCG_DI_HDMI_LPCG_0 - na */
/*! @{ */
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_div_clk_HWEN_MASK (0x1U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_div_clk_HWEN_SHIFT (0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_div_clk_HWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_div_clk_HWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_SWEN_AND_hdp_i2c_lpi2c_div_clk_SWEN_MASK (0x2U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_SWEN_AND_hdp_i2c_lpi2c_div_clk_SWEN_SHIFT (1U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_SWEN_AND_hdp_i2c_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_SWEN_AND_hdp_i2c_lpi2c_div_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_SWEN_AND_hdp_i2c_lpi2c_div_clk_SWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_2_2_MASK (0x4U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_2_2_SHIFT (2U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_2_2_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_2_2_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_STOP_AND_hdp_i2c_lpi2c_div_clk_STOP_MASK (0x8U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_STOP_AND_hdp_i2c_lpi2c_div_clk_STOP_SHIFT (3U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_STOP_AND_hdp_i2c_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_STOP_AND_hdp_i2c_lpi2c_div_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_lpi2c_clk_STOP_AND_hdp_i2c_lpi2c_div_clk_STOP_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_4_15_MASK (0xFFF0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_4_15_SHIFT (4U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_4_15_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_4_15_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_s_HWEN_MASK (0x10000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_s_HWEN_SHIFT (16U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_s_HWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_s_HWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_SWEN_AND_hdp_i2c_ipg_clk_s_SWEN_MASK (0x20000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_SWEN_AND_hdp_i2c_ipg_clk_s_SWEN_SHIFT (17U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_SWEN_AND_hdp_i2c_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_SWEN_AND_hdp_i2c_ipg_clk_s_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_SWEN_AND_hdp_i2c_ipg_clk_s_SWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_18_18_MASK (0x40000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_18_18_SHIFT (18U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_18_18_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_STOP_AND_hdp_i2c_ipg_clk_s_STOP_MASK (0x80000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_STOP_AND_hdp_i2c_ipg_clk_s_STOP_SHIFT (19U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_STOP_AND_hdp_i2c_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_STOP_AND_hdp_i2c_ipg_clk_s_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_hdp_i2c_ipg_clk_STOP_AND_hdp_i2c_ipg_clk_s_STOP_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_20_31_MASK (0xFFF00000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_20_31_SHIFT (20U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_0_LPCG_di_hdmi_lpcg_0_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DI_HDMI_LPCG_4 - na */
/*! @{ */
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_0_16_MASK (0x1FFFFU)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_0_16_SHIFT (0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_0_16_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_0_16_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_SWEN_MASK (0x20000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_SWEN_SHIFT (17U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_SWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_18_18_MASK (0x40000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_18_18_SHIFT (18U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_18_18_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_STOP_MASK (0x80000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_STOP_SHIFT (19U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_lis_ipg_clk_STOP_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_20_31_MASK (0xFFF00000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_20_31_SHIFT (20U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_4_LPCG_di_hdmi_lpcg_4_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DI_HDMI_LPCG_8 - na */
/*! @{ */
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_0_15_MASK (0xFFFFU)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_0_15_SHIFT (0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_0_15_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_0_15_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_HWEN_AND_hdp_pwm_ipg_clk_s_HWEN_MASK (0x10000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_HWEN_AND_hdp_pwm_ipg_clk_s_HWEN_SHIFT (16U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_HWEN_AND_hdp_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_HWEN_AND_hdp_pwm_ipg_clk_s_HWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_HWEN_AND_hdp_pwm_ipg_clk_s_HWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_SWEN_AND_hdp_pwm_ipg_clk_s_SWEN_AND_hdp_pwm_ipg_clk_highfreq_SWEN_AND_hdp_pwm_ipg_clk_32k_SWEN_MASK (0x20000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_SWEN_AND_hdp_pwm_ipg_clk_s_SWEN_AND_hdp_pwm_ipg_clk_highfreq_SWEN_AND_hdp_pwm_ipg_clk_32k_SWEN_SHIFT (17U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_SWEN_AND_hdp_pwm_ipg_clk_s_SWEN_AND_hdp_pwm_ipg_clk_highfreq_SWEN_AND_hdp_pwm_ipg_clk_32k_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_SWEN_AND_hdp_pwm_ipg_clk_s_SWEN_AND_hdp_pwm_ipg_clk_highfreq_SWEN_AND_hdp_pwm_ipg_clk_32k_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_SWEN_AND_hdp_pwm_ipg_clk_s_SWEN_AND_hdp_pwm_ipg_clk_highfreq_SWEN_AND_hdp_pwm_ipg_clk_32k_SWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_18_18_MASK (0x40000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_18_18_SHIFT (18U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_18_18_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_STOP_AND_hdp_pwm_ipg_clk_s_STOP_AND_hdp_pwm_ipg_clk_highfreq_STOP_AND_hdp_pwm_ipg_clk_32k_STOP_MASK (0x80000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_STOP_AND_hdp_pwm_ipg_clk_s_STOP_AND_hdp_pwm_ipg_clk_highfreq_STOP_AND_hdp_pwm_ipg_clk_32k_STOP_SHIFT (19U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_STOP_AND_hdp_pwm_ipg_clk_s_STOP_AND_hdp_pwm_ipg_clk_highfreq_STOP_AND_hdp_pwm_ipg_clk_32k_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_STOP_AND_hdp_pwm_ipg_clk_s_STOP_AND_hdp_pwm_ipg_clk_highfreq_STOP_AND_hdp_pwm_ipg_clk_32k_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_hdp_pwm_ipg_clk_STOP_AND_hdp_pwm_ipg_clk_s_STOP_AND_hdp_pwm_ipg_clk_highfreq_STOP_AND_hdp_pwm_ipg_clk_32k_STOP_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_20_31_MASK (0xFFF00000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_20_31_SHIFT (20U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_8_LPCG_di_hdmi_lpcg_8_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DI_HDMI_LPCG_12 - na */
/*! @{ */
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_0_0_MASK (0x1U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_0_0_SHIFT (0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_0_0_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_0_0_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_SWEN_MASK (0x2U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_SWEN_SHIFT (1U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_SWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_2_2_MASK (0x4U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_2_2_SHIFT (2U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_2_2_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_2_2_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_STOP_MASK (0x8U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_STOP_SHIFT (3U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_hdp_ctrl_phy_source_i2s_clk_STOP_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_4_31_SHIFT (4U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_4_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_12_LPCG_di_hdmi_lpcg_12_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_HDMI_LPCG_16 - na */
/*! @{ */
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_0_15_MASK (0xFFFFU)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_0_15_SHIFT (0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_0_15_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_0_15_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_HWEN_MASK (0x10000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_HWEN_SHIFT (16U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_HWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_HWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_SWEN_MASK (0x20000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_SWEN_SHIFT (17U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_SWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_18_18_MASK (0x40000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_18_18_SHIFT (18U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_18_18_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_STOP_MASK (0x80000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_STOP_SHIFT (19U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_hdp_gpio_ipg_clk_s_STOP_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_20_31_MASK (0xFFF00000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_20_31_SHIFT (20U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_16_LPCG_di_hdmi_lpcg_16_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DI_HDMI_LPCG_20 - na */
/*! @{ */
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_0_0_MASK (0x1U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_0_0_SHIFT (0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_0_0_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_0_0_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_SWEN_MASK (0x2U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_SWEN_SHIFT (1U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_SWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_2_2_MASK (0x4U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_2_2_SHIFT (2U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_2_2_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_2_2_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_STOP_MASK (0x8U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_STOP_SHIFT (3U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_secure_msi_slave_hclk_STOP_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_4_31_SHIFT (4U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_4_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_20_LPCG_di_hdmi_lpcg_20_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_HDMI_LPCG_24 - na */
/*! @{ */
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_0_0_MASK (0x1U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_0_0_SHIFT (0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_0_0_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_0_0_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_SWEN_AND_pixel_link_slv_even_ingress_clk_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_SWEN_AND_ss_di_hdmi_pxl_mux_double_clk_SWEN_AND_hdp_ctrl_phy_source_core_clk_SWEN_MASK (0x2U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_SWEN_AND_pixel_link_slv_even_ingress_clk_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_SWEN_AND_ss_di_hdmi_pxl_mux_double_clk_SWEN_AND_hdp_ctrl_phy_source_core_clk_SWEN_SHIFT (1U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_SWEN_AND_pixel_link_slv_even_ingress_clk_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_SWEN_AND_ss_di_hdmi_pxl_mux_double_clk_SWEN_AND_hdp_ctrl_phy_source_core_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_SWEN_AND_pixel_link_slv_even_ingress_clk_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_SWEN_AND_ss_di_hdmi_pxl_mux_double_clk_SWEN_AND_hdp_ctrl_phy_source_core_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_SWEN_AND_pixel_link_slv_even_ingress_clk_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_SWEN_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_SWEN_AND_ss_di_hdmi_pxl_mux_double_clk_SWEN_AND_hdp_ctrl_phy_source_core_clk_SWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_2_2_MASK (0x4U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_2_2_SHIFT (2U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_2_2_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_2_2_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_STOP_AND_pixel_link_slv_even_ingress_clk_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_STOP_AND_ss_di_hdmi_pxl_mux_double_clk_STOP_AND_hdp_ctrl_phy_source_core_clk_STOP_MASK (0x8U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_STOP_AND_pixel_link_slv_even_ingress_clk_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_STOP_AND_ss_di_hdmi_pxl_mux_double_clk_STOP_AND_hdp_ctrl_phy_source_core_clk_STOP_SHIFT (3U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_STOP_AND_pixel_link_slv_even_ingress_clk_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_STOP_AND_ss_di_hdmi_pxl_mux_double_clk_STOP_AND_hdp_ctrl_phy_source_core_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_STOP_AND_pixel_link_slv_even_ingress_clk_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_STOP_AND_ss_di_hdmi_pxl_mux_double_clk_STOP_AND_hdp_ctrl_phy_source_core_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_pixel_link_slv_odd_ingress_clk_STOP_AND_pixel_link_slv_even_ingress_clk_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_even_STOP_AND_ss_di_hdmi_pxl_mux_pixel_clk_odd_STOP_AND_ss_di_hdmi_pxl_mux_double_clk_STOP_AND_hdp_ctrl_phy_source_core_clk_STOP_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_4_31_SHIFT (4U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_4_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_24_LPCG_di_hdmi_lpcg_24_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_HDMI_LPCG_28 - na */
/*! @{ */
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_0_0_MASK (0x1U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_0_0_SHIFT (0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_0_0_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_0_0_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_SWEN_MASK (0x2U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_SWEN_SHIFT (1U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_SWEN_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_SWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_2_2_MASK (0x4U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_2_2_SHIFT (2U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_2_2_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_2_2_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_STOP_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_STOP_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_STOP_MASK (0x8U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_STOP_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_STOP_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_STOP_SHIFT (3U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_STOP_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_STOP_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_STOP_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_STOP_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_vif_clk_STOP_AND_hdp_ctrl_phy_scan_phy_pma_data_clk_in_STOP_AND_hdp_ctrl_phy_scan_phy_pma_refclk_in_STOP_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_4_16_MASK (0x1FFF0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_4_16_SHIFT (4U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_4_16_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_4_16_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_SWEN_AND_hdp_ctrl_phy_source_sclk_SWEN_AND_hdp_ctrl_phy_source_cclk_SWEN_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_SWEN_AND_hdp_ctrl_phy_source_ref_clk_in_SWEN_MASK (0x20000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_SWEN_AND_hdp_ctrl_phy_source_sclk_SWEN_AND_hdp_ctrl_phy_source_cclk_SWEN_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_SWEN_AND_hdp_ctrl_phy_source_ref_clk_in_SWEN_SHIFT (17U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_SWEN_AND_hdp_ctrl_phy_source_sclk_SWEN_AND_hdp_ctrl_phy_source_cclk_SWEN_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_SWEN_AND_hdp_ctrl_phy_source_ref_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_SWEN_AND_hdp_ctrl_phy_source_sclk_SWEN_AND_hdp_ctrl_phy_source_cclk_SWEN_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_SWEN_AND_hdp_ctrl_phy_source_ref_clk_in_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_SWEN_AND_hdp_ctrl_phy_source_sclk_SWEN_AND_hdp_ctrl_phy_source_cclk_SWEN_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_SWEN_AND_hdp_ctrl_phy_source_ref_clk_in_SWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_18_18_MASK (0x40000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_18_18_SHIFT (18U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_18_18_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_STOP_AND_hdp_ctrl_phy_source_sclk_STOP_AND_hdp_ctrl_phy_source_cclk_STOP_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_STOP_AND_hdp_ctrl_phy_source_ref_clk_in_STOP_MASK (0x80000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_STOP_AND_hdp_ctrl_phy_source_sclk_STOP_AND_hdp_ctrl_phy_source_cclk_STOP_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_STOP_AND_hdp_ctrl_phy_source_ref_clk_in_STOP_SHIFT (19U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_STOP_AND_hdp_ctrl_phy_source_sclk_STOP_AND_hdp_ctrl_phy_source_cclk_STOP_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_STOP_AND_hdp_ctrl_phy_source_ref_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_STOP_AND_hdp_ctrl_phy_source_sclk_STOP_AND_hdp_ctrl_phy_source_cclk_STOP_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_STOP_AND_hdp_ctrl_phy_source_ref_clk_in_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_hdp_ctrl_phy_source_pclk_STOP_AND_hdp_ctrl_phy_source_sclk_STOP_AND_hdp_ctrl_phy_source_cclk_STOP_AND_hdp_ctrl_phy_spdif_cdr_mclk_in_STOP_AND_hdp_ctrl_phy_source_ref_clk_in_STOP_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_20_31_MASK (0xFFF00000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_20_31_SHIFT (20U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_28_LPCG_di_hdmi_lpcg_28_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DI_HDMI_LPCG_32 - na */
/*! @{ */
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_0_16_MASK (0x1FFFFU)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_0_16_SHIFT (0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_0_16_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_0_16_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_SWEN_MASK (0x20000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_SWEN_SHIFT (17U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_SWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_18_18_MASK (0x40000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_18_18_SHIFT (18U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_18_18_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_STOP_MASK (0x80000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_STOP_SHIFT (19U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_apb_mux_csr_clk_STOP_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_20_31_MASK (0xFFF00000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_20_31_SHIFT (20U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_32_LPCG_di_hdmi_lpcg_32_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DI_HDMI_LPCG_36 - na */
/*! @{ */
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_0_16_MASK (0x1FFFFU)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_0_16_SHIFT (0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_0_16_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_0_16_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_SWEN_MASK (0x20000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_SWEN_SHIFT (17U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_SWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_18_18_MASK (0x40000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_18_18_SHIFT (18U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_18_18_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_STOP_MASK (0x80000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_STOP_SHIFT (19U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_apb_mux_ctrl_clk_STOP_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_20_31_MASK (0xFFF00000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_20_31_SHIFT (20U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_36_LPCG_di_hdmi_lpcg_36_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DI_HDMI_LPCG_40 - na */
/*! @{ */
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_0_16_MASK (0x1FFFFU)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_0_16_SHIFT (0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_0_16_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_0_16_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_SWEN_MASK (0x20000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_SWEN_SHIFT (17U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_SWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_18_18_MASK (0x40000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_18_18_SHIFT (18U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_18_18_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_18_18_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_STOP_MASK (0x80000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_STOP_SHIFT (19U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_di_hdmi_regs_apb_clk_STOP_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_20_31_MASK (0xFFF00000U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_20_31_SHIFT (20U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_20_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_40_LPCG_di_hdmi_lpcg_40_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DI_HDMI_LPCG_44 - na */
/*! @{ */
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_0_0_MASK (0x1U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_0_0_SHIFT (0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_0_0_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_0_0_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_SWEN_AND_bist_dca_ipg_clk_SWEN_AND_ipsyncs_bist_ipg_slave_clk_SWEN_MASK (0x2U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_SWEN_AND_bist_dca_ipg_clk_SWEN_AND_ipsyncs_bist_ipg_slave_clk_SWEN_SHIFT (1U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_SWEN_AND_bist_dca_ipg_clk_SWEN_AND_ipsyncs_bist_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_SWEN_AND_bist_dca_ipg_clk_SWEN_AND_ipsyncs_bist_ipg_slave_clk_SWEN_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_SWEN_AND_bist_dca_ipg_clk_SWEN_AND_ipsyncs_bist_ipg_slave_clk_SWEN_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_2_2_MASK (0x4U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_2_2_SHIFT (2U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_2_2_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_2_2_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_STOP_AND_bist_dca_ipg_clk_STOP_AND_ipsyncs_bist_ipg_slave_clk_STOP_MASK (0x8U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_STOP_AND_bist_dca_ipg_clk_STOP_AND_ipsyncs_bist_ipg_slave_clk_STOP_SHIFT (3U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_STOP_AND_bist_dca_ipg_clk_STOP_AND_ipsyncs_bist_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_STOP_AND_bist_dca_ipg_clk_STOP_AND_ipsyncs_bist_ipg_slave_clk_STOP_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_bist_ips_clk_STOP_AND_bist_dca_ipg_clk_STOP_AND_ipsyncs_bist_ipg_slave_clk_STOP_MASK)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_4_31_SHIFT (4U)
#define DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_4_31_SHIFT)) & DI_HDMI_LPCG_LPCG_DI_HDMI_LPCG_44_LPCG_di_hdmi_lpcg_44_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DI_HDMI_LPCG_Register_Masks */


/* DI_HDMI_LPCG - Peripheral instance base addresses */
/** Peripheral DI_HDMI__LPCG_CLK base address */
#define DI_HDMI__LPCG_CLK_BASE                   (0x56263000u)
/** Peripheral DI_HDMI__LPCG_CLK base pointer */
#define DI_HDMI__LPCG_CLK                        ((DI_HDMI_LPCG_Type *)DI_HDMI__LPCG_CLK_BASE)
/** Array initializer of DI_HDMI_LPCG peripheral base addresses */
#define DI_HDMI_LPCG_BASE_ADDRS                  { DI_HDMI__LPCG_CLK_BASE }
/** Array initializer of DI_HDMI_LPCG peripheral base pointers */
#define DI_HDMI_LPCG_BASE_PTRS                   { DI_HDMI__LPCG_CLK }

/*!
 * @}
 */ /* end of group DI_HDMI_LPCG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DI_LVDS_LPCG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DI_LVDS_LPCG_Peripheral_Access_Layer DI_LVDS_LPCG Peripheral Access Layer
 * @{
 */

/** DI_LVDS_LPCG - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_DI_LVDS_LPCG_0;               /**< na, offset: 0x0 */
  __IO uint32_t LPCG_DI_LVDS_LPCG_4;               /**< na, offset: 0x4 */
  __IO uint32_t LPCG_DI_LVDS_LPCG_8;               /**< na, offset: 0x8 */
  __IO uint32_t LPCG_DI_LVDS_LPCG_12;              /**< na, offset: 0xC */
  __IO uint32_t LPCG_DI_LVDS_LPCG_16;              /**< na, offset: 0x10 */
  __IO uint32_t LPCG_DI_LVDS_LPCG_20;              /**< na, offset: 0x14 */
} DI_LVDS_LPCG_Type;

/* ----------------------------------------------------------------------------
   -- DI_LVDS_LPCG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DI_LVDS_LPCG_Register_Masks DI_LVDS_LPCG Register Masks
 * @{
 */

/*! @name LPCG_DI_LVDS_LPCG_0 - na */
/*! @{ */
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_0_16_MASK (0x1FFFFU)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_0_16_SHIFT (0U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_0_16_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_0_16_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_SWEN_MASK (0x20000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_SWEN_SHIFT (17U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_SWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_18_18_MASK (0x40000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_18_18_SHIFT (18U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_18_18_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_18_18_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_STOP_MASK (0x80000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_STOP_SHIFT (19U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_lis_ipg_clk_STOP_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_20_31_MASK (0xFFF00000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_20_31_SHIFT (20U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_20_31_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_0_LPCG_di_lvds_lpcg_0_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DI_LVDS_LPCG_4 - na */
/*! @{ */
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_0_16_MASK (0x1FFFFU)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_0_16_SHIFT (0U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_0_16_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_0_16_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_SWEN_MASK (0x20000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_SWEN_SHIFT (17U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_SWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_18_18_MASK (0x40000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_18_18_SHIFT (18U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_18_18_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_18_18_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_STOP_MASK (0x80000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_STOP_SHIFT (19U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_di_lvds_regs_ipg_clk_STOP_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_20_31_MASK (0xFFF00000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_20_31_SHIFT (20U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_20_31_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_4_LPCG_di_lvds_lpcg_4_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DI_LVDS_LPCG_8 - na */
/*! @{ */
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_0_15_MASK (0xFFFFU)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_0_15_SHIFT (0U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_0_15_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_0_15_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_MASK (0x10000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT (16U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_HWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_MASK (0x20000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT (17U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_SWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_18_18_MASK (0x40000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_18_18_SHIFT (18U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_18_18_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_18_18_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_MASK (0x80000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT (19U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_gpio_ipg_clk_s_STOP_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_20_31_MASK (0xFFF00000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_20_31_SHIFT (20U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_20_31_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_8_LPCG_di_lvds_lpcg_8_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DI_LVDS_LPCG_12 - na */
/*! @{ */
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_0_0_MASK (0x1U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_0_0_SHIFT (0U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_0_0_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_0_0_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_MASK (0x2U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_SHIFT (1U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_SWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_2_2_MASK (0x4U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_2_2_SHIFT (2U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_2_2_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_2_2_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_MASK (0x8U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_SHIFT (3U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_highfreq_STOP_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_4_4_MASK (0x10U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_4_4_SHIFT (4U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_4_4_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_4_4_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_MASK (0x20U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_SHIFT (5U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_SWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_6_6_MASK (0x40U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_6_6_SHIFT (6U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_6_6_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_6_6_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_MASK (0x80U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_SHIFT (7U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ccm_ckil_sync_wrapper_clk_in_STOP_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_8_15_MASK (0xFF00U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_8_15_SHIFT (8U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_8_15(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_8_15_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_8_15_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK (0x10000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT (16U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK (0x20000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT (17U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_18_18_MASK (0x40000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_18_18_SHIFT (18U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_18_18_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_18_18_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK (0x80000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT (19U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_MASK (0x100000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_SHIFT (20U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_HWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_MASK (0x200000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_SHIFT (21U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_SWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_22_22_MASK (0x400000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_22_22_SHIFT (22U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_22_22_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_22_22_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_MASK (0x800000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_SHIFT (23U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_master_clk_STOP_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_HWEN_MASK (0x1000000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_HWEN_SHIFT (24U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_HWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_MASK (0x2000000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_SHIFT (25U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_SWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_26_26_MASK (0x4000000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_26_26_SHIFT (26U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_26_26_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_26_26_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_MASK (0x8000000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_SHIFT (27U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_ipsync_pwm_ipg_slave_clk_STOP_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_28_31_MASK (0xF0000000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_28_31_SHIFT (28U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_28_31_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_12_LPCG_di_lvds_lpcg_12_reserved_28_31_MASK)
/*! @} */

/*! @name LPCG_DI_LVDS_LPCG_16 - na */
/*! @{ */
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_MASK (0x1U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_SHIFT (0U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_div_clk_HWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK (0x2U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT (1U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_2_2_MASK (0x4U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_2_2_SHIFT (2U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_2_2_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_2_2_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK (0x8U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT (3U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_4_15_MASK (0xFFF0U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_4_15_SHIFT (4U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_4_15_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_4_15_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_MASK (0x10000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_SHIFT (16U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_s_HWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK (0x20000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT (17U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_18_18_MASK (0x40000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_18_18_SHIFT (18U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_18_18_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_18_18_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK (0x80000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT (19U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_20_31_MASK (0xFFF00000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_20_31_SHIFT (20U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_20_31_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_16_LPCG_di_lvds_lpcg_16_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_DI_LVDS_LPCG_20 - na */
/*! @{ */
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_div_clk_HWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_2_2_MASK (0x4U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_2_2_SHIFT (2U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_2_2_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_2_2_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_4_15_MASK (0xFFF0U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_4_15_SHIFT (4U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_4_15_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_4_15_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_MASK (0x10000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_SHIFT (16U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_s_HWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_MASK (0x20000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_SHIFT (17U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_18_18_MASK (0x40000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_18_18_SHIFT (18U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_18_18_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_18_18_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_MASK (0x80000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_SHIFT (19U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_MASK)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_20_31_MASK (0xFFF00000U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_20_31_SHIFT (20U)
#define DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_20_31_SHIFT)) & DI_LVDS_LPCG_LPCG_DI_LVDS_LPCG_20_LPCG_di_lvds_lpcg_20_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DI_LVDS_LPCG_Register_Masks */


/* DI_LVDS_LPCG - Peripheral instance base addresses */
/** Peripheral DI_LVDS_0__LPCG_CLK base address */
#define DI_LVDS_0__LPCG_CLK_BASE                 (0x56243000u)
/** Peripheral DI_LVDS_0__LPCG_CLK base pointer */
#define DI_LVDS_0__LPCG_CLK                      ((DI_LVDS_LPCG_Type *)DI_LVDS_0__LPCG_CLK_BASE)
/** Peripheral DI_LVDS_1__LPCG_CLK base address */
#define DI_LVDS_1__LPCG_CLK_BASE                 (0x57243000u)
/** Peripheral DI_LVDS_1__LPCG_CLK base pointer */
#define DI_LVDS_1__LPCG_CLK                      ((DI_LVDS_LPCG_Type *)DI_LVDS_1__LPCG_CLK_BASE)
/** Array initializer of DI_LVDS_LPCG peripheral base addresses */
#define DI_LVDS_LPCG_BASE_ADDRS                  { DI_LVDS_0__LPCG_CLK_BASE, DI_LVDS_1__LPCG_CLK_BASE }
/** Array initializer of DI_LVDS_LPCG peripheral base pointers */
#define DI_LVDS_LPCG_BASE_PTRS                   { DI_LVDS_0__LPCG_CLK, DI_LVDS_1__LPCG_CLK }

/*!
 * @}
 */ /* end of group DI_LVDS_LPCG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DI_MIPI_LPCG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DI_MIPI_LPCG_Peripheral_Access_Layer DI_MIPI_LPCG Peripheral Access Layer
 * @{
 */

/** DI_MIPI_LPCG - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_DI_MIPI_LPCG_0;               /**< na, offset: 0x0 */
  __IO uint32_t LPCG_DI_MIPI_LPCG_4;               /**< na, offset: 0x4 */
  __IO uint32_t LPCG_DI_MIPI_LPCG_8;               /**< na, offset: 0x8 */
  __IO uint32_t LPCG_DI_MIPI_LPCG_12;              /**< na, offset: 0xC */
  __IO uint32_t LPCG_DI_MIPI_LPCG_16;              /**< na, offset: 0x10 */
  __IO uint32_t LPCG_DI_MIPI_LPCG_20;              /**< na, offset: 0x14 */
  __IO uint32_t LPCG_DI_MIPI_LPCG_24;              /**< na, offset: 0x18 */
  __IO uint32_t LPCG_DI_MIPI_LPCG_28;              /**< na, offset: 0x1C */
  __IO uint32_t LPCG_DI_MIPI_LPCG_32;              /**< na, offset: 0x20 */
  __IO uint32_t LPCG_DI_MIPI_LPCG_36;              /**< na, offset: 0x24 */
  __IO uint32_t LPCG_DI_MIPI_LPCG_40;              /**< na, offset: 0x28 */
  __IO uint32_t LPCG_DI_MIPI_LPCG_44;              /**< na, offset: 0x2C */
  __IO uint32_t LPCG_DI_MIPI_LPCG_48;              /**< na, offset: 0x30 */
  __IO uint32_t LPCG_DI_MIPI_LPCG_52;              /**< na, offset: 0x34 */
  __IO uint32_t LPCG_DI_MIPI_LPCG_56;              /**< na, offset: 0x38 */
  __IO uint32_t LPCG_DI_MIPI_LPCG_60;              /**< na, offset: 0x3C */
} DI_MIPI_LPCG_Type;

/* ----------------------------------------------------------------------------
   -- DI_MIPI_LPCG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DI_MIPI_LPCG_Register_Masks DI_MIPI_LPCG Register Masks
 * @{
 */

/*! @name LPCG_DI_MIPI_LPCG_0 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_0_0_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_0_0_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_0_0_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_lis_ipg_clk_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_0_LPCG_di_mipi_lpcg_0_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_4 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_HWEN_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_HWEN_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_HWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_HWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_gpio_ipg_clk_s_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_4_LPCG_di_mipi_lpcg_4_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_8 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_HWEN_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_HWEN_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_HWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_HWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_pwm_ipg_clk_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_8_LPCG_di_mipi_lpcg_8_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_12 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_HWEN_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_HWEN_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_HWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_HWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_pwm_ipg_clk_s_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_12_LPCG_di_mipi_lpcg_12_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_16 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_0_0_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_0_0_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_0_0_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_pwm_ipg_clk_highfreq_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_16_LPCG_di_mipi_lpcg_16_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_20 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_0_0_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_0_0_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_0_0_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_lpi2c0_ipg_clk_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_20_LPCG_di_mipi_lpcg_20_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_24 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_HWEN_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_HWEN_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_HWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_HWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_lpi2c0_ipg_clk_s_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_24_LPCG_di_mipi_lpcg_24_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_28 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_0_0_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_0_0_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_0_0_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_lpi2c0_lpi2c_clk_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_28_LPCG_di_mipi_lpcg_28_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_32 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_HWEN_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_HWEN_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_HWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_HWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_lpi2c0_lpi2c_div_clk_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_32_LPCG_di_mipi_lpcg_32_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_36 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_0_0_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_0_0_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_0_0_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_lpi2c1_ipg_clk_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_36_LPCG_di_mipi_lpcg_36_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_40 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_HWEN_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_HWEN_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_HWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_HWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_lpi2c1_ipg_clk_s_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_40_LPCG_di_mipi_lpcg_40_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_44 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_0_0_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_0_0_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_0_0_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_lpi2c1_lpi2c_clk_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_44_LPCG_di_mipi_lpcg_44_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_48 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_HWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_lpi2c1_lpi2c_div_clk_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_48_LPCG_di_mipi_lpcg_48_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_52 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_0_0_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_0_0_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_0_0_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_mipi_dsi_ctrl_CLKREF_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_52_LPCG_di_mipi_lpcg_52_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_56 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_0_0_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_0_0_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_0_0_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_mipi_dsi_ctrl_TxClkEsc_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_56_LPCG_di_mipi_lpcg_56_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_DI_MIPI_LPCG_60 - na */
/*! @{ */
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_0_0_MASK (0x1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_0_0_SHIFT (0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_0_0_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_0_0_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_SWEN_MASK (0x2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_SWEN_SHIFT (1U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_SWEN_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_SWEN_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_2_2_MASK (0x4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_2_2_SHIFT (2U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_2_2_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_2_2_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_STOP_MASK (0x8U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_STOP_SHIFT (3U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_STOP(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_STOP_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_mipi_dsi_ctrl_RxClkEsc_STOP_MASK)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_4_31_MASK (0xFFFFFFF0U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_4_31_SHIFT (4U)
#define DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_4_31_SHIFT)) & DI_MIPI_LPCG_LPCG_DI_MIPI_LPCG_60_LPCG_di_mipi_lpcg_60_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DI_MIPI_LPCG_Register_Masks */


/* DI_MIPI_LPCG - Peripheral instance base addresses */
/** Peripheral DI_MIPI_0__LPCG_CLK base address */
#define DI_MIPI_0__LPCG_CLK_BASE                 (0x56223000u)
/** Peripheral DI_MIPI_0__LPCG_CLK base pointer */
#define DI_MIPI_0__LPCG_CLK                      ((DI_MIPI_LPCG_Type *)DI_MIPI_0__LPCG_CLK_BASE)
/** Peripheral DI_MIPI_1__LPCG_CLK base address */
#define DI_MIPI_1__LPCG_CLK_BASE                 (0x57223000u)
/** Peripheral DI_MIPI_1__LPCG_CLK base pointer */
#define DI_MIPI_1__LPCG_CLK                      ((DI_MIPI_LPCG_Type *)DI_MIPI_1__LPCG_CLK_BASE)
/** Array initializer of DI_MIPI_LPCG peripheral base addresses */
#define DI_MIPI_LPCG_BASE_ADDRS                  { DI_MIPI_0__LPCG_CLK_BASE, DI_MIPI_1__LPCG_CLK_BASE }
/** Array initializer of DI_MIPI_LPCG peripheral base pointers */
#define DI_MIPI_LPCG_BASE_PTRS                   { DI_MIPI_0__LPCG_CLK, DI_MIPI_1__LPCG_CLK }

/*!
 * @}
 */ /* end of group DI_MIPI_LPCG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
 * @{
 */

/** DMA - Register Layout Typedef */
typedef struct {
  __IO uint32_t MP_CSR;                            /**< Management Page Control Register, offset: 0x0 */
  __I  uint32_t MP_ES;                             /**< Management Page Error Status Register, offset: 0x4 */
       uint8_t RESERVED_0[4];
  __I  uint32_t MP_HRS;                            /**< Management Page Hardware Request Status Register, offset: 0xC */
       uint8_t RESERVED_1[240];
  __IO uint32_t CH_GRPRI[32];                      /**< Channel Arbitration Group Register, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_2[65152];
  struct {                                         /* offset: 0x10000, array step: 0x10000 */
    __IO uint32_t CH_CSR;                            /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
    __IO uint32_t CH_ES;                             /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
    __IO uint32_t CH_INT;                            /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */
    __IO uint32_t CH_SBR;                            /**< Channel System Bus Register, array offset: 0x1000C, array step: 0x10000 */
    __IO uint32_t CH_PRI;                            /**< Channel Priority Register, array offset: 0x10010, array step: 0x10000 */
         uint8_t RESERVED_0[12];
    __IO uint32_t TCD_SADDR;                         /**< TCD Source Address, array offset: 0x10020, array step: 0x10000 */
    __IO uint16_t TCD_SOFF;                          /**< TCD Signed Source Address Offset, array offset: 0x10024, array step: 0x10000 */
    __IO uint16_t TCD_ATTR;                          /**< TCD Transfer Attributes, array offset: 0x10026, array step: 0x10000 */
    union {                                          /* offset: 0x10028, array step: 0x10000 */
      __IO uint32_t TCD_NBYTES_MLOFFNO;                /**< TCD Transfer Size without Minor Loop Offsets, array offset: 0x10028, array step: 0x10000 */
      __IO uint32_t TCD_NBYTES_MLOFFYES;               /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x10028, array step: 0x10000 */
    };
    __IO uint32_t TCD_SLAST_SDA;                     /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x1002C, array step: 0x10000 */
    __IO uint32_t TCD_DADDR;                         /**< TCD Destination Address, array offset: 0x10030, array step: 0x10000 */
    __IO uint16_t TCD_DOFF;                          /**< TCD Signed Destination Address Offset, array offset: 0x10034, array step: 0x10000 */
    union {                                          /* offset: 0x10036, array step: 0x10000 */
      __IO uint16_t TCD_CITER_ELINKNO;                 /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x10036, array step: 0x10000 */
      __IO uint16_t TCD_CITER_ELINKYES;                /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x10036, array step: 0x10000 */
    };
    __IO uint32_t TCD_DLAST_SGA;                     /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x10038, array step: 0x10000 */
    __IO uint16_t TCD_CSR;                           /**< TCD Control and Status, array offset: 0x1003C, array step: 0x10000 */
    union {                                          /* offset: 0x1003E, array step: 0x10000 */
      __IO uint16_t TCD_BITER_ELINKNO;                 /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1003E, array step: 0x10000 */
      __IO uint16_t TCD_BITER_ELINKYES;                /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1003E, array step: 0x10000 */
    };
         uint8_t RESERVED_1[65472];
  } CH[32];
} DMA_Type;

/* ----------------------------------------------------------------------------
   -- DMA Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_Register_Masks DMA Register Masks
 * @{
 */

/*! @name MP_CSR - Management Page Control Register */
/*! @{ */
#define DMA_MP_CSR_EBW_MASK                      (0x1U)
#define DMA_MP_CSR_EBW_SHIFT                     (0U)
/*! EBW - Enable Buffered Writes
 *  0b0..Buffered writes on the system bus are disabled.
 *  0b1..Buffered writes on the system bus are enabled.
 */
#define DMA_MP_CSR_EBW(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EBW_SHIFT)) & DMA_MP_CSR_EBW_MASK)
#define DMA_MP_CSR_EDBG_MASK                     (0x2U)
#define DMA_MP_CSR_EDBG_SHIFT                    (1U)
/*! EDBG - Enable Debug
 *  0b0..Debug mode is disabled.
 *  0b1..Debug mode is enabled.
 */
#define DMA_MP_CSR_EDBG(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK)
#define DMA_MP_CSR_ERCA_MASK                     (0x4U)
#define DMA_MP_CSR_ERCA_SHIFT                    (2U)
/*! ERCA - Enable Round Robin Channel Arbitration
 *  0b0..Round robin channel arbitration is disabled.
 *  0b1..Round robin channel arbitration is enabled.
 */
#define DMA_MP_CSR_ERCA(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK)
#define DMA_MP_CSR_HAE_MASK                      (0x10U)
#define DMA_MP_CSR_HAE_SHIFT                     (4U)
/*! HAE - Halt After Error
 *  0b0..Normal operation
 *  0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
 */
#define DMA_MP_CSR_HAE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK)
#define DMA_MP_CSR_HALT_MASK                     (0x20U)
#define DMA_MP_CSR_HALT_SHIFT                    (5U)
/*! HALT - Halt DMA Operations
 *  0b0..Normal operation
 *  0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
 */
#define DMA_MP_CSR_HALT(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK)
#define DMA_MP_CSR_GCLC_MASK                     (0x40U)
#define DMA_MP_CSR_GCLC_SHIFT                    (6U)
/*! GCLC - Global Channel Linking Control
 *  0b0..Channel linking is disabled for all channels.
 *  0b1..Channel linking is available and controlled by each channel's link settings.
 */
#define DMA_MP_CSR_GCLC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK)
#define DMA_MP_CSR_GMRC_MASK                     (0x80U)
#define DMA_MP_CSR_GMRC_SHIFT                    (7U)
/*! GMRC - Global Master ID Replication Control
 *  0b0..Master ID replication is disabled for all channels.
 *  0b1..Master ID replication is available and is controlled by each channel's CHn_SBR[EMI] setting.
 */
#define DMA_MP_CSR_GMRC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK)
#define DMA_MP_CSR_ECX_MASK                      (0x100U)
#define DMA_MP_CSR_ECX_SHIFT                     (8U)
/*! ECX - Cancel Transfer with Error
 *  0b0..Normal operation
 *  0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
 */
#define DMA_MP_CSR_ECX(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK)
#define DMA_MP_CSR_CX_MASK                       (0x200U)
#define DMA_MP_CSR_CX_SHIFT                      (9U)
/*! CX - Cancel Transfer
 *  0b0..Normal operation
 *  0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
 */
#define DMA_MP_CSR_CX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK)
#define DMA_MP_CSR_ACTIVE_ID_MASK                (0x1F000000U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define DMA_MP_CSR_ACTIVE_ID_SHIFT               (24U)
#define DMA_MP_CSR_ACTIVE_ID(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define DMA_MP_CSR_ACTIVE_MASK                   (0x80000000U)
#define DMA_MP_CSR_ACTIVE_SHIFT                  (31U)
/*! ACTIVE - DMA Active Status
 *  0b0..eDMA is idle.
 *  0b1..eDMA is executing a channel.
 */
#define DMA_MP_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK)
/*! @} */

/*! @name MP_ES - Management Page Error Status Register */
/*! @{ */
#define DMA_MP_ES_DBE_MASK                       (0x1U)
#define DMA_MP_ES_DBE_SHIFT                      (0U)
/*! DBE - Destination Bus Error
 *  0b0..No destination bus error
 *  0b1..The last recorded error was a bus error on a destination write
 */
#define DMA_MP_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK)
#define DMA_MP_ES_SBE_MASK                       (0x2U)
#define DMA_MP_ES_SBE_SHIFT                      (1U)
/*! SBE - Source Bus Error
 *  0b0..No source bus error
 *  0b1..The last recorded error was a bus error on a source read
 */
#define DMA_MP_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK)
#define DMA_MP_ES_SGE_MASK                       (0x4U)
#define DMA_MP_ES_SGE_SHIFT                      (2U)
/*! SGE - Scatter/Gather Configuration Error
 *  0b0..No scatter/gather configuration error
 *  0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
 */
#define DMA_MP_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK)
#define DMA_MP_ES_NCE_MASK                       (0x8U)
#define DMA_MP_ES_NCE_SHIFT                      (3U)
/*! NCE - NBYTES/CITER Configuration Error
 *  0b0..No NBYTES/CITER configuration error
 *  0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
 */
#define DMA_MP_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK)
#define DMA_MP_ES_DOE_MASK                       (0x10U)
#define DMA_MP_ES_DOE_SHIFT                      (4U)
/*! DOE - Destination Offset Error
 *  0b0..No destination offset configuration error
 *  0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
 */
#define DMA_MP_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK)
#define DMA_MP_ES_DAE_MASK                       (0x20U)
#define DMA_MP_ES_DAE_SHIFT                      (5U)
/*! DAE - Destination Address Error
 *  0b0..No destination address configuration error
 *  0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
 */
#define DMA_MP_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK)
#define DMA_MP_ES_SOE_MASK                       (0x40U)
#define DMA_MP_ES_SOE_SHIFT                      (6U)
/*! SOE - Source Offset Error
 *  0b0..No source offset configuration error
 *  0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
 */
#define DMA_MP_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK)
#define DMA_MP_ES_SAE_MASK                       (0x80U)
#define DMA_MP_ES_SAE_SHIFT                      (7U)
/*! SAE - Source Address Error
 *  0b0..No source address configuration error.
 *  0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
 */
#define DMA_MP_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK)
#define DMA_MP_ES_ECX_MASK                       (0x100U)
#define DMA_MP_ES_ECX_SHIFT                      (8U)
/*! ECX - Transfer Canceled
 *  0b0..No canceled transfers
 *  0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
 */
#define DMA_MP_ES_ECX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK)
#define DMA_MP_ES_ERRCHN_MASK                    (0x1F000000U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define DMA_MP_ES_ERRCHN_SHIFT                   (24U)
#define DMA_MP_ES_ERRCHN(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define DMA_MP_ES_VLD_MASK                       (0x80000000U)
#define DMA_MP_ES_VLD_SHIFT                      (31U)
/*! VLD - Valid
 *  0b0..No ERR bits are set.
 *  0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
 */
#define DMA_MP_ES_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK)
/*! @} */

/*! @name MP_HRS - Management Page Hardware Request Status Register */
/*! @{ */
#define DMA_MP_HRS_HRS_MASK                      (0xFFFFFFFFU)
#define DMA_MP_HRS_HRS_SHIFT                     (0U)
/*! HRS - Hardware Request Status
 *  0b00000000000000000000000000000000..A hardware service request for the channel is not present
 *  0b00000000000000000000000000000001..A hardware service request for channel 0 is present
 */
#define DMA_MP_HRS_HRS(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK)
/*! @} */

/*! @name CH_GRPRI - Channel Arbitration Group Register */
/*! @{ */
#define DMA_CH_GRPRI_GRPRI_MASK                  (0x1FU)
#define DMA_CH_GRPRI_GRPRI_SHIFT                 (0U)
#define DMA_CH_GRPRI_GRPRI(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK)
/*! @} */

/* The count of DMA_CH_GRPRI */
#define DMA_CH_GRPRI_COUNT                       (32U)

/*! @name CH_CSR - Channel Control and Status */
/*! @{ */
#define DMA_CH_CSR_ERQ_MASK                      (0x1U)
#define DMA_CH_CSR_ERQ_SHIFT                     (0U)
/*! ERQ - Enable DMA Request
 *  0b0..The DMA hardware request signal for the corresponding channel is disabled.
 *  0b1..The DMA hardware request signal for the corresponding channel is enabled.
 */
#define DMA_CH_CSR_ERQ(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
#define DMA_CH_CSR_EARQ_MASK                     (0x2U)
#define DMA_CH_CSR_EARQ_SHIFT                    (1U)
/*! EARQ - Enable Asynchronous DMA Request in stop mode for channel
 *  0b0..Disable asynchronous DMA request for the channel.
 *  0b1..Enable asynchronous DMA request for the channel.
 */
#define DMA_CH_CSR_EARQ(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK)
#define DMA_CH_CSR_EEI_MASK                      (0x4U)
#define DMA_CH_CSR_EEI_SHIFT                     (2U)
/*! EEI - Enable Error Interrupt
 *  0b0..The error signal for corresponding channel does not generate an error interrupt
 *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
 */
#define DMA_CH_CSR_EEI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK)
#define DMA_CH_CSR_DONE_MASK                     (0x40000000U)
#define DMA_CH_CSR_DONE_SHIFT                    (30U)
#define DMA_CH_CSR_DONE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK)
#define DMA_CH_CSR_ACTIVE_MASK                   (0x80000000U)
#define DMA_CH_CSR_ACTIVE_SHIFT                  (31U)
#define DMA_CH_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK)
/*! @} */

/* The count of DMA_CH_CSR */
#define DMA_CH_CSR_COUNT                         (32U)

/*! @name CH_ES - Channel Error Status */
/*! @{ */
#define DMA_CH_ES_DBE_MASK                       (0x1U)
#define DMA_CH_ES_DBE_SHIFT                      (0U)
/*! DBE - Destination Bus Error
 *  0b0..No destination bus error
 *  0b1..The last recorded error was a bus error on a destination write
 */
#define DMA_CH_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK)
#define DMA_CH_ES_SBE_MASK                       (0x2U)
#define DMA_CH_ES_SBE_SHIFT                      (1U)
/*! SBE - Source Bus Error
 *  0b0..No source bus error
 *  0b1..The last recorded error was a bus error on a source read
 */
#define DMA_CH_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK)
#define DMA_CH_ES_SGE_MASK                       (0x4U)
#define DMA_CH_ES_SGE_SHIFT                      (2U)
/*! SGE - Scatter/Gather Configuration Error
 *  0b0..No scatter/gather configuration error
 *  0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
 */
#define DMA_CH_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK)
#define DMA_CH_ES_NCE_MASK                       (0x8U)
#define DMA_CH_ES_NCE_SHIFT                      (3U)
/*! NCE - NBYTES/CITER Configuration Error
 *  0b0..No NBYTES/CITER configuration error
 */
#define DMA_CH_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK)
#define DMA_CH_ES_DOE_MASK                       (0x10U)
#define DMA_CH_ES_DOE_SHIFT                      (4U)
/*! DOE - Destination Offset Error
 *  0b0..No destination offset configuration error
 *  0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
 */
#define DMA_CH_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK)
#define DMA_CH_ES_DAE_MASK                       (0x20U)
#define DMA_CH_ES_DAE_SHIFT                      (5U)
/*! DAE - Destination Address Error
 *  0b0..No destination address configuration error
 *  0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
 */
#define DMA_CH_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK)
#define DMA_CH_ES_SOE_MASK                       (0x40U)
#define DMA_CH_ES_SOE_SHIFT                      (6U)
/*! SOE - Source Offset Error
 *  0b0..No source offset configuration error
 *  0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
 */
#define DMA_CH_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK)
#define DMA_CH_ES_SAE_MASK                       (0x80U)
#define DMA_CH_ES_SAE_SHIFT                      (7U)
/*! SAE - Source Address Error
 *  0b0..No source address configuration error.
 *  0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
 */
#define DMA_CH_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK)
#define DMA_CH_ES_ERR_MASK                       (0x80000000U)
#define DMA_CH_ES_ERR_SHIFT                      (31U)
/*! ERR - Error In Channel
 *  0b0..An error in this channel has not occurred
 *  0b1..An error in this channel has occurred
 */
#define DMA_CH_ES_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK)
/*! @} */

/* The count of DMA_CH_ES */
#define DMA_CH_ES_COUNT                          (32U)

/*! @name CH_INT - Channel Interrupt Status */
/*! @{ */
#define DMA_CH_INT_INT_MASK                      (0x1U)
#define DMA_CH_INT_INT_SHIFT                     (0U)
/*! INT - Interrupt Request
 *  0b0..The interrupt request for corresponding channel is cleared
 *  0b1..The interrupt request for corresponding channel is active
 */
#define DMA_CH_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/*! @} */

/* The count of DMA_CH_INT */
#define DMA_CH_INT_COUNT                         (32U)

/*! @name CH_SBR - Channel System Bus Register */
/*! @{ */
#define DMA_CH_SBR_MID_MASK                      (0x1FU)
#define DMA_CH_SBR_MID_SHIFT                     (0U)
#define DMA_CH_SBR_MID(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK)
#define DMA_CH_SBR_PAL_MASK                      (0x8000U)
#define DMA_CH_SBR_PAL_SHIFT                     (15U)
/*! PAL - Privileged Access Level
 *  0b0..User protection level for DMA transfers
 *  0b1..Privileged protection level for DMA transfers
 */
#define DMA_CH_SBR_PAL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK)
#define DMA_CH_SBR_ATTR_MASK                     (0x7E0000U)
#define DMA_CH_SBR_ATTR_SHIFT                    (17U)
#define DMA_CH_SBR_ATTR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_ATTR_SHIFT)) & DMA_CH_SBR_ATTR_MASK)
/*! @} */

/* The count of DMA_CH_SBR */
#define DMA_CH_SBR_COUNT                         (32U)

/*! @name CH_PRI - Channel Priority Register */
/*! @{ */
#define DMA_CH_PRI_APL_MASK                      (0x7U)
#define DMA_CH_PRI_APL_SHIFT                     (0U)
#define DMA_CH_PRI_APL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK)
#define DMA_CH_PRI_DPA_MASK                      (0x40000000U)
#define DMA_CH_PRI_DPA_SHIFT                     (30U)
/*! DPA - Disable Preempt Ability.
 *  0b0..The channel can suspend a lower priority channel.
 *  0b1..The channel cannot suspend any other channel, regardless of channel priority.
 */
#define DMA_CH_PRI_DPA(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK)
#define DMA_CH_PRI_ECP_MASK                      (0x80000000U)
#define DMA_CH_PRI_ECP_SHIFT                     (31U)
/*! ECP - Enable Channel Preemption.
 *  0b0..The channel cannot be suspended by a higher priority channel's service request.
 *  0b1..The channel can be temporarily suspended by the service request of a higher priority channel.
 */
#define DMA_CH_PRI_ECP(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK)
/*! @} */

/* The count of DMA_CH_PRI */
#define DMA_CH_PRI_COUNT                         (32U)

/*! @name TCD_SADDR - TCD Source Address */
/*! @{ */
#define DMA_TCD_SADDR_SADDR_MASK                 (0xFFFFFFFFU)
#define DMA_TCD_SADDR_SADDR_SHIFT                (0U)
#define DMA_TCD_SADDR_SADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK)
/*! @} */

/* The count of DMA_TCD_SADDR */
#define DMA_TCD_SADDR_COUNT                      (32U)

/*! @name TCD_SOFF - TCD Signed Source Address Offset */
/*! @{ */
#define DMA_TCD_SOFF_SOFF_MASK                   (0xFFFFU)
#define DMA_TCD_SOFF_SOFF_SHIFT                  (0U)
#define DMA_TCD_SOFF_SOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK)
/*! @} */

/* The count of DMA_TCD_SOFF */
#define DMA_TCD_SOFF_COUNT                       (32U)

/*! @name TCD_ATTR - TCD Transfer Attributes */
/*! @{ */
#define DMA_TCD_ATTR_DSIZE_MASK                  (0x7U)
#define DMA_TCD_ATTR_DSIZE_SHIFT                 (0U)
#define DMA_TCD_ATTR_DSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK)
#define DMA_TCD_ATTR_DMOD_MASK                   (0xF8U)
#define DMA_TCD_ATTR_DMOD_SHIFT                  (3U)
#define DMA_TCD_ATTR_DMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK)
#define DMA_TCD_ATTR_SSIZE_MASK                  (0x700U)
#define DMA_TCD_ATTR_SSIZE_SHIFT                 (8U)
/*! SSIZE - Source data transfer size
 *  0b000..8-bit
 *  0b001..16-bit
 *  0b010..32-bit
 *  0b011..64-bit
 *  0b100..16-byte
 *  0b101..32-byte
 *  0b110..64-byte
 *  0b111..Reserved
 */
#define DMA_TCD_ATTR_SSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK)
#define DMA_TCD_ATTR_SMOD_MASK                   (0xF800U)
#define DMA_TCD_ATTR_SMOD_SHIFT                  (11U)
/*! SMOD - Source address modulo
 *  0b00000..Source address modulo feature is disabled
 *  0b00001..Source address modulo feature is enabled for any non-zero value [1-31]
 */
#define DMA_TCD_ATTR_SMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK)
/*! @} */

/* The count of DMA_TCD_ATTR */
#define DMA_TCD_ATTR_COUNT                       (32U)

/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size without Minor Loop Offsets */
/*! @{ */
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK       (0x3FFFFFFFU)
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT      (0U)
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK        (0x40000000U)
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT       (30U)
/*! DMLOE - Destination Minor Loop Offset Enable
 *  0b0..The minor loop offset is not applied to the DADDR
 *  0b1..The minor loop offset is applied to the DADDR
 */
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK        (0x80000000U)
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT       (31U)
/*! SMLOE - Source Minor Loop Offset Enable
 *  0b0..The minor loop offset is not applied to the SADDR
 *  0b1..The minor loop offset is applied to the SADDR
 */
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
/*! @} */

/* The count of DMA_TCD_NBYTES_MLOFFNO */
#define DMA_TCD_NBYTES_MLOFFNO_COUNT             (32U)

/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */
/*! @{ */
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK      (0x3FFU)
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT     (0U)
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)        (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK       (0x3FFFFC00U)
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT      (10U)
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK       (0x40000000U)
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT      (30U)
/*! DMLOE - Destination Minor Loop Offset Enable
 *  0b0..The minor loop offset is not applied to the DADDR
 *  0b1..The minor loop offset is applied to the DADDR
 */
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK       (0x80000000U)
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT      (31U)
/*! SMLOE - Source Minor Loop Offset Enable
 *  0b0..The minor loop offset is not applied to the SADDR
 *  0b1..The minor loop offset is applied to the SADDR
 */
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
/*! @} */

/* The count of DMA_TCD_NBYTES_MLOFFYES */
#define DMA_TCD_NBYTES_MLOFFYES_COUNT            (32U)

/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */
/*! @{ */
#define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK         (0xFFFFFFFFU)
#define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT        (0U)
#define DMA_TCD_SLAST_SDA_SLAST_SDA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK)
/*! @} */

/* The count of DMA_TCD_SLAST_SDA */
#define DMA_TCD_SLAST_SDA_COUNT                  (32U)

/*! @name TCD_DADDR - TCD Destination Address */
/*! @{ */
#define DMA_TCD_DADDR_DADDR_MASK                 (0xFFFFFFFFU)
#define DMA_TCD_DADDR_DADDR_SHIFT                (0U)
#define DMA_TCD_DADDR_DADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK)
/*! @} */

/* The count of DMA_TCD_DADDR */
#define DMA_TCD_DADDR_COUNT                      (32U)

/*! @name TCD_DOFF - TCD Signed Destination Address Offset */
/*! @{ */
#define DMA_TCD_DOFF_DOFF_MASK                   (0xFFFFU)
#define DMA_TCD_DOFF_DOFF_SHIFT                  (0U)
#define DMA_TCD_DOFF_DOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK)
/*! @} */

/* The count of DMA_TCD_DOFF */
#define DMA_TCD_DOFF_COUNT                       (32U)

/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */
/*! @{ */
#define DMA_TCD_CITER_ELINKNO_CITER_MASK         (0x7FFFU)
#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT        (0U)
#define DMA_TCD_CITER_ELINKNO_CITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK)
#define DMA_TCD_CITER_ELINKNO_ELINK_MASK         (0x8000U)
#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT        (15U)
/*! ELINK - Enable channel-to-channel linking on minor-loop complete
 *  0b0..The channel-to-channel linking is disabled
 *  0b1..The channel-to-channel linking is enabled
 */
#define DMA_TCD_CITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_CITER_ELINKNO */
#define DMA_TCD_CITER_ELINKNO_COUNT              (32U)

/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */
/*! @{ */
#define DMA_TCD_CITER_ELINKYES_CITER_MASK        (0x1FFU)
#define DMA_TCD_CITER_ELINKYES_CITER_SHIFT       (0U)
#define DMA_TCD_CITER_ELINKYES_CITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK)
#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK       (0x3E00U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT      (9U)
#define DMA_TCD_CITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define DMA_TCD_CITER_ELINKYES_ELINK_MASK        (0x8000U)
#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT       (15U)
/*! ELINK - Enable channel-to-channel linking on minor-loop complete
 *  0b0..The channel-to-channel linking is disabled
 *  0b1..The channel-to-channel linking is enabled
 */
#define DMA_TCD_CITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_CITER_ELINKYES */
#define DMA_TCD_CITER_ELINKYES_COUNT             (32U)

/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */
/*! @{ */
#define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK         (0xFFFFFFFFU)
#define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT        (0U)
#define DMA_TCD_DLAST_SGA_DLAST_SGA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK)
/*! @} */

/* The count of DMA_TCD_DLAST_SGA */
#define DMA_TCD_DLAST_SGA_COUNT                  (32U)

/*! @name TCD_CSR - TCD Control and Status */
/*! @{ */
#define DMA_TCD_CSR_START_MASK                   (0x1U)
#define DMA_TCD_CSR_START_SHIFT                  (0U)
/*! START - Channel Start
 *  0b0..The channel is not explicitly started.
 *  0b1..The channel is explicitly started via a software initiated service request.
 */
#define DMA_TCD_CSR_START(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK)
#define DMA_TCD_CSR_INTMAJOR_MASK                (0x2U)
#define DMA_TCD_CSR_INTMAJOR_SHIFT               (1U)
/*! INTMAJOR - Enable an interrupt when major iteration count completes.
 *  0b0..The end-of-major loop interrupt is disabled.
 *  0b1..The end-of-major loop interrupt is enabled.
 */
#define DMA_TCD_CSR_INTMAJOR(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK)
#define DMA_TCD_CSR_INTHALF_MASK                 (0x4U)
#define DMA_TCD_CSR_INTHALF_SHIFT                (2U)
/*! INTHALF - Enable an interrupt when major counter is half complete.
 *  0b0..The half-point interrupt is disabled.
 *  0b1..The half-point interrupt is enabled.
 */
#define DMA_TCD_CSR_INTHALF(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK)
#define DMA_TCD_CSR_DREQ_MASK                    (0x8U)
#define DMA_TCD_CSR_DREQ_SHIFT                   (3U)
/*! DREQ - Disable request
 *  0b0..No operation
 *  0b1..Clear the ERQ bit upon major loop completion, thus disabling hardware service requests.
 */
#define DMA_TCD_CSR_DREQ(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
#define DMA_TCD_CSR_ESG_MASK                     (0x10U)
#define DMA_TCD_CSR_ESG_SHIFT                    (4U)
/*! ESG - Enable Scatter/Gather processing
 *  0b0..The current channel's TCD is normal format.
 *  0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
 */
#define DMA_TCD_CSR_ESG(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK)
#define DMA_TCD_CSR_MAJORELINK_MASK              (0x20U)
#define DMA_TCD_CSR_MAJORELINK_SHIFT             (5U)
/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
 *  0b0..The channel-to-channel linking is disabled.
 *  0b1..The channel-to-channel linking is enabled.
 */
#define DMA_TCD_CSR_MAJORELINK(x)                (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK)
#define DMA_TCD_CSR_EEOP_MASK                    (0x40U)
#define DMA_TCD_CSR_EEOP_SHIFT                   (6U)
/*! EEOP - Enable end-of-packet processing
 *  0b0..The end-of-packet operation is disabled.
 *  0b1..The end-of-packet hardware input signal is enabled.
 */
#define DMA_TCD_CSR_EEOP(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK)
#define DMA_TCD_CSR_ESDA_MASK                    (0x80U)
#define DMA_TCD_CSR_ESDA_SHIFT                   (7U)
/*! ESDA - Enable store destination address
 *  0b0..The store destination address to system memory operation is disabled.
 *  0b1..The store destination address to system memory operation is enabled.
 */
#define DMA_TCD_CSR_ESDA(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK)
#define DMA_TCD_CSR_MAJORLINKCH_MASK             (0x1F00U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define DMA_TCD_CSR_MAJORLINKCH_SHIFT            (8U)
#define DMA_TCD_CSR_MAJORLINKCH(x)               (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define DMA_TCD_CSR_BWC_MASK                     (0xC000U)
#define DMA_TCD_CSR_BWC_SHIFT                    (14U)
/*! BWC - Bandwidth Control
 *  0b00..No eDMA engine stalls.
 *  0b01..Reserved
 *  0b10..eDMA engine stalls for 4 cycles after each R/W.
 *  0b11..eDMA engine stalls for 8 cycles after each R/W.
 */
#define DMA_TCD_CSR_BWC(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK)
/*! @} */

/* The count of DMA_TCD_CSR */
#define DMA_TCD_CSR_COUNT                        (32U)

/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */
/*! @{ */
#define DMA_TCD_BITER_ELINKNO_BITER_MASK         (0x7FFFU)
#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT        (0U)
#define DMA_TCD_BITER_ELINKNO_BITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK)
#define DMA_TCD_BITER_ELINKNO_ELINK_MASK         (0x8000U)
#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT        (15U)
/*! ELINK - Enables channel-to-channel linking on minor loop complete
 *  0b0..The channel-to-channel linking is disabled
 *  0b1..The channel-to-channel linking is enabled
 */
#define DMA_TCD_BITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_BITER_ELINKNO */
#define DMA_TCD_BITER_ELINKNO_COUNT              (32U)

/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */
/*! @{ */
#define DMA_TCD_BITER_ELINKYES_BITER_MASK        (0x1FFU)
#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT       (0U)
#define DMA_TCD_BITER_ELINKYES_BITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK)
#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK       (0x3E00U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT      (9U)
#define DMA_TCD_BITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define DMA_TCD_BITER_ELINKYES_ELINK_MASK        (0x8000U)
#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT       (15U)
/*! ELINK - Enables channel-to-channel linking on minor loop complete
 *  0b0..The channel-to-channel linking is disabled
 *  0b1..The channel-to-channel linking is enabled
 */
#define DMA_TCD_BITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_BITER_ELINKYES */
#define DMA_TCD_BITER_ELINKYES_COUNT             (32U)


/*!
 * @}
 */ /* end of group DMA_Register_Masks */


/* DMA - Peripheral instance base addresses */
/** Peripheral AUDIO__EDMA0 base address */
#define AUDIO__EDMA0_BASE                        (0x591F0000u)
/** Peripheral AUDIO__EDMA0 base pointer */
#define AUDIO__EDMA0                             ((DMA_Type *)AUDIO__EDMA0_BASE)
/** Peripheral AUDIO__EDMA1 base address */
#define AUDIO__EDMA1_BASE                        (0x599F0000u)
/** Peripheral AUDIO__EDMA1 base pointer */
#define AUDIO__EDMA1                             ((DMA_Type *)AUDIO__EDMA1_BASE)
/** Peripheral CONNECTIVITY__EDMA base address */
#define CONNECTIVITY__EDMA_BASE                  (0x5B070000u)
/** Peripheral CONNECTIVITY__EDMA base pointer */
#define CONNECTIVITY__EDMA                       ((DMA_Type *)CONNECTIVITY__EDMA_BASE)
/** Peripheral DMA__EDMA0 base address */
#define DMA__EDMA0_BASE                          (0x5A1F0000u)
/** Peripheral DMA__EDMA0 base pointer */
#define DMA__EDMA0                               ((DMA_Type *)DMA__EDMA0_BASE)
/** Peripheral DMA__EDMA1 base address */
#define DMA__EDMA1_BASE                          (0x5A9F0000u)
/** Peripheral DMA__EDMA1 base pointer */
#define DMA__EDMA1                               ((DMA_Type *)DMA__EDMA1_BASE)
/** Array initializer of DMA peripheral base addresses */
#define DMA_BASE_ADDRS                           { AUDIO__EDMA0_BASE, AUDIO__EDMA1_BASE, CONNECTIVITY__EDMA_BASE, DMA__EDMA0_BASE, DMA__EDMA1_BASE }
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASE_PTRS                            { AUDIO__EDMA0, AUDIO__EDMA1, CONNECTIVITY__EDMA, DMA__EDMA0, DMA__EDMA1 }
/** Interrupt vectors for the DMA peripheral type */
#define DMA_IRQS                                 { { AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn, AUDIO_EDMA0_INT_IRQn }, \
                                                   { AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn, AUDIO_EDMA1_INT_IRQn }, \
                                                   { CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn }, \
                                                   { DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn, DMA_EDMA0_INT_IRQn }, \
                                                   { DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn, DMA_EDMA1_INT_IRQn } }
#define DMA_ERROR_IRQS                           { AUDIO_EDMA0_ERR_INT_IRQn, AUDIO_EDMA1_ERR_INT_IRQn, CONNECTIVITY_DMA_ERR_INT_IRQn, DMA_EDMA0_ERR_INT_IRQn, DMA_EDMA1_ERR_INT_IRQn }

/*!
 * @}
 */ /* end of group DMA_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DPR Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DPR_Peripheral_Access_Layer DPR Peripheral Access Layer
 * @{
 */

/** DPR - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0 */
    __IO uint32_t RW;                                /**< System Control 0, offset: 0x0 */
    __IO uint32_t SET;                               /**< System Control 0, offset: 0x4 */
    __IO uint32_t CLR;                               /**< System Control 0, offset: 0x8 */
    __IO uint32_t TOG;                               /**< System Control 0, offset: 0xC */
  } SYSTEM_CTRL0;
       uint8_t RESERVED_0[16];
  struct {                                         /* offset: 0x20 */
    __IO uint32_t RW;                                /**< Interrupt Mask, offset: 0x20 */
    __IO uint32_t SET;                               /**< Interrupt Mask, offset: 0x24 */
    __IO uint32_t CLR;                               /**< Interrupt Mask, offset: 0x28 */
    __IO uint32_t TOG;                               /**< Interrupt Mask, offset: 0x2C */
  } IRQ_MASK;
  struct {                                         /* offset: 0x30 */
    __I  uint32_t RW;                                /**< Status Register of Masked IRQ, offset: 0x30 */
    __I  uint32_t SET;                               /**< Status Register of Masked IRQ, offset: 0x34 */
    __I  uint32_t CLR;                               /**< Status Register of Masked IRQ, offset: 0x38 */
    __I  uint32_t TOG;                               /**< Status Register of Masked IRQ, offset: 0x3C */
  } IRQ_MASK_STATUS;
  struct {                                         /* offset: 0x40 */
    __IO uint32_t RW;                                /**< Status of Non-Masked IRQ, offset: 0x40 */
    __IO uint32_t SET;                               /**< Status of Non-Masked IRQ, offset: 0x44 */
    __IO uint32_t CLR;                               /**< Status of Non-Masked IRQ, offset: 0x48 */
    __IO uint32_t TOG;                               /**< Status of Non-Masked IRQ, offset: 0x4C */
  } IRQ_NONMASK_STATUS;
  struct {                                         /* offset: 0x50 */
    __IO uint32_t RW;                                /**< Mode Control 0, offset: 0x50 */
    __IO uint32_t SET;                               /**< Mode Control 0, offset: 0x54 */
    __IO uint32_t CLR;                               /**< Mode Control 0, offset: 0x58 */
    __IO uint32_t TOG;                               /**< Mode Control 0, offset: 0x5C */
  } MODE_CTRL0;
       uint8_t RESERVED_1[16];
  struct {                                         /* offset: 0x70 */
    __IO uint32_t RW;                                /**< Frame Control 0, offset: 0x70 */
    __IO uint32_t SET;                               /**< Frame Control 0, offset: 0x74 */
    __IO uint32_t CLR;                               /**< Frame Control 0, offset: 0x78 */
    __IO uint32_t TOG;                               /**< Frame Control 0, offset: 0x7C */
  } FRAME_CTRL0;
       uint8_t RESERVED_2[16];
  struct {                                         /* offset: 0x90 */
    __IO uint32_t RW;                                /**< Frame 1-Plane Control 0, offset: 0x90 */
    __IO uint32_t SET;                               /**< Frame 1-Plane Control 0, offset: 0x94 */
    __IO uint32_t CLR;                               /**< Frame 1-Plane Control 0, offset: 0x98 */
    __IO uint32_t TOG;                               /**< Frame 1-Plane Control 0, offset: 0x9C */
  } FRAME_1P_CTRL0;
  struct {                                         /* offset: 0xA0 */
    __IO uint32_t RW;                                /**< Frame 1-Plane Pix X Control, offset: 0xA0 */
    __IO uint32_t SET;                               /**< Frame 1-Plane Pix X Control, offset: 0xA4 */
    __IO uint32_t CLR;                               /**< Frame 1-Plane Pix X Control, offset: 0xA8 */
    __IO uint32_t TOG;                               /**< Frame 1-Plane Pix X Control, offset: 0xAC */
  } FRAME_1P_PIX_X_CTRL;
  struct {                                         /* offset: 0xB0 */
    __IO uint32_t RW;                                /**< Frame 1-Plane Pix Y Control, offset: 0xB0 */
    __IO uint32_t SET;                               /**< Frame 1-Plane Pix Y Control, offset: 0xB4 */
    __IO uint32_t CLR;                               /**< Frame 1-Plane Pix Y Control, offset: 0xB8 */
    __IO uint32_t TOG;                               /**< Frame 1-Plane Pix Y Control, offset: 0xBC */
  } FRAME_1P_PIX_Y_CTRL;
  struct {                                         /* offset: 0xC0 */
    __IO uint32_t RW;                                /**< Frame 1-Plane Base Address Control 0, offset: 0xC0 */
    __IO uint32_t SET;                               /**< Frame 1-Plane Base Address Control 0, offset: 0xC4 */
    __IO uint32_t CLR;                               /**< Frame 1-Plane Base Address Control 0, offset: 0xC8 */
    __IO uint32_t TOG;                               /**< Frame 1-Plane Base Address Control 0, offset: 0xCC */
  } FRAME_1P_BASE_ADDR_CTRL0;
       uint8_t RESERVED_3[16];
  struct {                                         /* offset: 0xE0 */
    __IO uint32_t RW;                                /**< Frame 2-Plane Control 0, offset: 0xE0 */
    __IO uint32_t SET;                               /**< Frame 2-Plane Control 0, offset: 0xE4 */
    __IO uint32_t CLR;                               /**< Frame 2-Plane Control 0, offset: 0xE8 */
    __IO uint32_t TOG;                               /**< Frame 2-Plane Control 0, offset: 0xEC */
  } FRAME_2P_CTRL0;
  struct {                                         /* offset: 0xF0 */
    __IO uint32_t RW;                                /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xF0 */
    __IO uint32_t SET;                               /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xF4 */
    __IO uint32_t CLR;                               /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xF8 */
    __IO uint32_t TOG;                               /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xFC */
  } FRAME_PIX_X_ULC_CTRL;
  struct {                                         /* offset: 0x100 */
    __IO uint32_t RW;                                /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x100 */
    __IO uint32_t SET;                               /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x104 */
    __IO uint32_t CLR;                               /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x108 */
    __IO uint32_t TOG;                               /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x10C */
  } FRAME_PIX_Y_ULC_CTRL;
  struct {                                         /* offset: 0x110 */
    __IO uint32_t RW;                                /**< Frame 2-Plane Base Address Control 0, offset: 0x110 */
    __IO uint32_t SET;                               /**< Frame 2-Plane Base Address Control 0, offset: 0x114 */
    __IO uint32_t CLR;                               /**< Frame 2-Plane Base Address Control 0, offset: 0x118 */
    __IO uint32_t TOG;                               /**< Frame 2-Plane Base Address Control 0, offset: 0x11C */
  } FRAME_2P_BASE_ADDR_CTRL0;
       uint8_t RESERVED_4[16];
  struct {                                         /* offset: 0x130 */
    __IO uint32_t RW;                                /**< Status Control 0, offset: 0x130 */
    __IO uint32_t SET;                               /**< Status Control 0, offset: 0x134 */
    __IO uint32_t CLR;                               /**< Status Control 0, offset: 0x138 */
    __IO uint32_t TOG;                               /**< Status Control 0, offset: 0x13C */
  } STATUS_CTRL0;
  struct {                                         /* offset: 0x140 */
    __I  uint32_t RW;                                /**< Status Control 1, offset: 0x140 */
    __I  uint32_t SET;                               /**< Status Control 1, offset: 0x144 */
    __I  uint32_t CLR;                               /**< Status Control 1, offset: 0x148 */
    __I  uint32_t TOG;                               /**< Status Control 1, offset: 0x14C */
  } STATUS_CTRL1;
       uint8_t RESERVED_5[176];
  struct {                                         /* offset: 0x200 */
    __IO uint32_t RW;                                /**< RTRAM Control 0, offset: 0x200 */
    __IO uint32_t SET;                               /**< RTRAM Control 0, offset: 0x204 */
    __IO uint32_t CLR;                               /**< RTRAM Control 0, offset: 0x208 */
    __IO uint32_t TOG;                               /**< RTRAM Control 0, offset: 0x20C */
  } RTRAM_CTRL0;
} DPR_Type;

/* ----------------------------------------------------------------------------
   -- DPR Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DPR_Register_Masks DPR Register Masks
 * @{
 */

/*! @name SYSTEM_CTRL0 - System Control 0 */
/*! @{ */
#define DPR_SYSTEM_CTRL0_RUN_EN_MASK             (0x1U)
#define DPR_SYSTEM_CTRL0_RUN_EN_SHIFT            (0U)
/*! RUN_EN - Run Enable
 */
#define DPR_SYSTEM_CTRL0_RUN_EN(x)               (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_RUN_EN_SHIFT)) & DPR_SYSTEM_CTRL0_RUN_EN_MASK)
#define DPR_SYSTEM_CTRL0_SOFT_RESET_MASK         (0x2U)
#define DPR_SYSTEM_CTRL0_SOFT_RESET_SHIFT        (1U)
/*! SOFT_RESET - Soft Reset
 */
#define DPR_SYSTEM_CTRL0_SOFT_RESET(x)           (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SOFT_RESET_SHIFT)) & DPR_SYSTEM_CTRL0_SOFT_RESET_MASK)
#define DPR_SYSTEM_CTRL0_REPEAT_EN_MASK          (0x4U)
#define DPR_SYSTEM_CTRL0_REPEAT_EN_SHIFT         (2U)
/*! REPEAT_EN - Repeat Enable
 */
#define DPR_SYSTEM_CTRL0_REPEAT_EN(x)            (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_REPEAT_EN_SHIFT)) & DPR_SYSTEM_CTRL0_REPEAT_EN_MASK)
#define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_MASK     (0x8U)
#define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_SHIFT    (3U)
/*! SHADOW_LOAD_EN - Shadow Load Enable
 */
#define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN(x)       (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_SHIFT)) & DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_MASK)
#define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK (0x10U)
#define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_SHIFT (4U)
/*! SW_SHADOW_LOAD_SEL - Software Shadow Load Select
 */
#define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL(x)   (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_SHIFT)) & DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK)
#define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_MASK (0x10000U)
#define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_SHIFT (16U)
/*! BCMD2AXI_MSTR_ID_CTRL - Buscmd To AXI Master ID Control
 */
#define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_SHIFT)) & DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_MASK)
/*! @} */

/*! @name IRQ_MASK - Interrupt Mask */
/*! @{ */
#define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_MASK      (0x1U)
#define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_SHIFT     (0U)
/*! IRQ_DPR_CTRL_DONE - DPR Control Done IRQ Mask
 */
#define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE(x)        (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_MASK)
#define DPR_IRQ_MASK_IRQ_DPR_RUN_MASK            (0x2U)
#define DPR_IRQ_MASK_IRQ_DPR_RUN_SHIFT           (1U)
/*! IRQ_DPR_RUN - DPR Run IRQ Mask
 */
#define DPR_IRQ_MASK_IRQ_DPR_RUN(x)              (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_RUN_MASK)
#define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_MASK (0x4U)
#define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_SHIFT (2U)
/*! IRQ_DPR_SHADOW_LOADED_MASK - DPR Shadow Loaded IRQ Mask
 */
#define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_MASK)
#define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_MASK     (0x8U)
#define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_SHIFT    (3U)
/*! IRQ_AXI_READ_ERROR - AXI Read Error IRQ Mask
 */
#define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR(x)       (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_MASK)
#define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U)
#define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U)
/*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow IRQ Mask
 */
#define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL(x)   (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_MASK)
#define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_MASK   (0x20U)
#define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_SHIFT  (5U)
/*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow IRQ Mask
 */
#define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL(x)     (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_MASK)
#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U)
#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U)
/*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer ready IRQ error Mask
 */
#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK)
#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U)
#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U)
/*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer ready IRQ error Mask
 */
#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK)
/*! @} */

/*! @name IRQ_MASK_STATUS - Status Register of Masked IRQ */
/*! @{ */
#define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_MASK (0x1U)
#define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT (0U)
/*! IRQ_DPR_CTRL_DONE - DPR Control Done Masked IRQ
 */
#define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_MASK)
#define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_MASK     (0x2U)
#define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_SHIFT    (1U)
/*! IRQ_DPR_RUN - DPR Run Masked IRQ
 */
#define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN(x)       (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_MASK)
#define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_MASK (0x4U)
#define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_SHIFT (2U)
/*! IRQ_DPR_SHADOW_LOADED - DPR Shadow Loaded Masked IRQ
 */
#define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_MASK)
#define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_MASK (0x8U)
#define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT (3U)
/*! IRQ_AXI_READ_ERROR - AXI Read Error Masked IRQ
 */
#define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_MASK)
#define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U)
#define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U)
/*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow Masked IRQ
 */
#define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK)
#define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U)
#define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U)
/*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow Masked IRQ
 */
#define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK)
#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U)
#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U)
/*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer error Masked IRQ
 */
#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK)
#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U)
#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U)
/*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer error Masked IRQ
 */
#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK)
/*! @} */

/*! @name IRQ_NONMASK_STATUS - Status of Non-Masked IRQ */
/*! @{ */
#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_MASK (0x1U)
#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT (0U)
/*! IRQ_DPR_CTRL_DONE - DPR Control Done Non-Masked IRQ
 */
#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_MASK)
#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_MASK  (0x2U)
#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_SHIFT (1U)
/*! IRQ_DPR_RUN - DPR Run Non-Masked IRQ
 */
#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN(x)    (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_MASK)
#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_MASK (0x4U)
#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_SHIFT (2U)
/*! IRQ_DPR_SHADOW_LOADED_NMSTAT - DPR Shadow Loaded Non-Masked IRQ
 */
#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_MASK)
#define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_MASK (0x8U)
#define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT (3U)
/*! IRQ_AXI_READ_ERROR - AXI Read Error Non-Masked IRQ
 */
#define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_MASK)
#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U)
#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U)
/*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow Non-Masked IRQ
 */
#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK)
#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U)
#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U)
/*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow Non-Masked IRQ
 */
#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK)
#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U)
#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U)
/*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer ready error Non-Masked IRQ
 */
#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK)
#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U)
#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U)
/*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer ready error Non-Masked IRQ
 */
#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK)
/*! @} */

/*! @name MODE_CTRL0 - Mode Control 0 */
/*! @{ */
#define DPR_MODE_CTRL0_RTR_3BUF_EN_MASK          (0x1U)
#define DPR_MODE_CTRL0_RTR_3BUF_EN_SHIFT         (0U)
/*! RTR_3BUF_EN - RTRAM Buffer Implementation
 */
#define DPR_MODE_CTRL0_RTR_3BUF_EN(x)            (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_RTR_3BUF_EN_SHIFT)) & DPR_MODE_CTRL0_RTR_3BUF_EN_MASK)
#define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK     (0x2U)
#define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_SHIFT    (1U)
/*! RTR_4LINE_BUF_EN - RTRAM Lines Per Buffer
 */
#define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN(x)       (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_SHIFT)) & DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK)
#define DPR_MODE_CTRL0_TILE_TYPE_MASK            (0xCU)
#define DPR_MODE_CTRL0_TILE_TYPE_SHIFT           (2U)
/*! TILE_TYPE - Tile Type
 */
#define DPR_MODE_CTRL0_TILE_TYPE(x)              (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_TILE_TYPE_SHIFT)) & DPR_MODE_CTRL0_TILE_TYPE_MASK)
#define DPR_MODE_CTRL0_YUV_EN_MASK               (0x10U)
#define DPR_MODE_CTRL0_YUV_EN_SHIFT              (4U)
/*! YUV_EN - YUV Enable
 */
#define DPR_MODE_CTRL0_YUV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_YUV_EN_SHIFT)) & DPR_MODE_CTRL0_YUV_EN_MASK)
#define DPR_MODE_CTRL0_COMP_2PLANE_EN_MASK       (0x20U)
#define DPR_MODE_CTRL0_COMP_2PLANE_EN_SHIFT      (5U)
/*! COMP_2PLANE_EN - Component 2-Plane Enable
 */
#define DPR_MODE_CTRL0_COMP_2PLANE_EN(x)         (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_COMP_2PLANE_EN_SHIFT)) & DPR_MODE_CTRL0_COMP_2PLANE_EN_MASK)
#define DPR_MODE_CTRL0_PIX_SIZE_MASK             (0xC0U)
#define DPR_MODE_CTRL0_PIX_SIZE_SHIFT            (6U)
/*! PIX_SIZE - Pixel Size
 */
#define DPR_MODE_CTRL0_PIX_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_SIZE_SHIFT)) & DPR_MODE_CTRL0_PIX_SIZE_MASK)
#define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_MASK     (0x100U)
#define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_SHIFT    (8U)
/*! PIX_LUMA_UV_SWAP - Pixel luma/UV position Swap
 */
#define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP(x)       (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_SHIFT)) & DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_MASK)
#define DPR_MODE_CTRL0_PIX_UV_SWAP_MASK          (0x200U)
#define DPR_MODE_CTRL0_PIX_UV_SWAP_SHIFT         (9U)
/*! PIX_UV_SWAP - Pixel UV Swap
 */
#define DPR_MODE_CTRL0_PIX_UV_SWAP(x)            (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_UV_SWAP_SHIFT)) & DPR_MODE_CTRL0_PIX_UV_SWAP_MASK)
#define DPR_MODE_CTRL0_B_COMP_SEL_MASK           (0xC00U)
#define DPR_MODE_CTRL0_B_COMP_SEL_SHIFT          (10U)
/*! B_COMP_SEL - B Component Select
 */
#define DPR_MODE_CTRL0_B_COMP_SEL(x)             (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_B_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_B_COMP_SEL_MASK)
#define DPR_MODE_CTRL0_G_COMP_SEL_MASK           (0x3000U)
#define DPR_MODE_CTRL0_G_COMP_SEL_SHIFT          (12U)
/*! G_COMP_SEL - G Component Select
 */
#define DPR_MODE_CTRL0_G_COMP_SEL(x)             (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_G_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_G_COMP_SEL_MASK)
#define DPR_MODE_CTRL0_R_COMP_SEL_MASK           (0xC000U)
#define DPR_MODE_CTRL0_R_COMP_SEL_SHIFT          (14U)
/*! R_COMP_SEL - R Component Select
 */
#define DPR_MODE_CTRL0_R_COMP_SEL(x)             (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_R_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_R_COMP_SEL_MASK)
#define DPR_MODE_CTRL0_A_COMP_SEL_MASK           (0x30000U)
#define DPR_MODE_CTRL0_A_COMP_SEL_SHIFT          (16U)
/*! A_COMP_SEL - A Component Select
 */
#define DPR_MODE_CTRL0_A_COMP_SEL(x)             (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_A_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_A_COMP_SEL_MASK)
/*! @} */

/*! @name FRAME_CTRL0 - Frame Control 0 */
/*! @{ */
#define DPR_FRAME_CTRL0_HFLIP_EN_MASK            (0x1U)
#define DPR_FRAME_CTRL0_HFLIP_EN_SHIFT           (0U)
/*! HFLIP_EN - Horizontal Flip Enable
 */
#define DPR_FRAME_CTRL0_HFLIP_EN(x)              (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_HFLIP_EN_SHIFT)) & DPR_FRAME_CTRL0_HFLIP_EN_MASK)
#define DPR_FRAME_CTRL0_VFLIP_EN_MASK            (0x2U)
#define DPR_FRAME_CTRL0_VFLIP_EN_SHIFT           (1U)
/*! VFLIP_EN - Vertical Flip Enable
 */
#define DPR_FRAME_CTRL0_VFLIP_EN(x)              (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_VFLIP_EN_SHIFT)) & DPR_FRAME_CTRL0_VFLIP_EN_MASK)
#define DPR_FRAME_CTRL0_ROT_ENC_MASK             (0xCU)
#define DPR_FRAME_CTRL0_ROT_ENC_SHIFT            (2U)
/*! ROT_ENC - Encoded Rotation
 */
#define DPR_FRAME_CTRL0_ROT_ENC(x)               (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_ROT_ENC_SHIFT)) & DPR_FRAME_CTRL0_ROT_ENC_MASK)
#define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_MASK   (0x10U)
#define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_SHIFT  (4U)
/*! ROT_FLIP_ORDER_EN - Rotation Flip Order
 */
#define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN(x)     (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_SHIFT)) & DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_MASK)
#define DPR_FRAME_CTRL0_PITCH_MASK               (0xFFFF0000U)
#define DPR_FRAME_CTRL0_PITCH_SHIFT              (16U)
/*! PITCH - Image Pitch
 */
#define DPR_FRAME_CTRL0_PITCH(x)                 (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_PITCH_SHIFT)) & DPR_FRAME_CTRL0_PITCH_MASK)
/*! @} */

/*! @name FRAME_1P_CTRL0 - Frame 1-Plane Control 0 */
/*! @{ */
#define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_MASK   (0x7U)
#define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_SHIFT  (0U)
/*! MAX_BYTES_PREQ - Max Bytes Per Request
 */
#define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ(x)     (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_SHIFT)) & DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_MASK)
/*! @} */

/*! @name FRAME_1P_PIX_X_CTRL - Frame 1-Plane Pix X Control */
/*! @{ */
#define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK (0xFFFFU)
#define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT (0U)
/*! NUM_X_PIX_WIDE - Number of Pixels Wide in X-direction
 */
#define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT)) & DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK)
/*! @} */

/*! @name FRAME_1P_PIX_Y_CTRL - Frame 1-Plane Pix Y Control */
/*! @{ */
#define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK (0xFFFFU)
#define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT (0U)
/*! NUM_Y_PIX_HIGH - Number of Pixels High in Y-direction
 */
#define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT)) & DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK)
/*! @} */

/*! @name FRAME_1P_BASE_ADDR_CTRL0 - Frame 1-Plane Base Address Control 0 */
/*! @{ */
#define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_MASK (0xFFFFFFFFU)
#define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT (0U)
/*! BASE_ADDR - Base Address
 */
#define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT)) & DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_MASK)
/*! @} */

/*! @name FRAME_2P_CTRL0 - Frame 2-Plane Control 0 */
/*! @{ */
#define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_MASK   (0x7U)
#define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_SHIFT  (0U)
/*! MAX_BYTES_PREQ - Max Bytes Per Request
 */
#define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ(x)     (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_SHIFT)) & DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_MASK)
/*! @} */

/*! @name FRAME_PIX_X_ULC_CTRL - Frame Pixel X Upper Left Coordinate Control */
/*! @{ */
#define DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_MASK (0xFFFFU)
#define DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_SHIFT (0U)
/*! CROP_ULC_X - Starting Coordinate of Cropped Image X (1-Plane or 2-Plane Luma)
 */
#define DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X(x)   (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_SHIFT)) & DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_MASK)
/*! @} */

/*! @name FRAME_PIX_Y_ULC_CTRL - Frame Pixel Y Upper Left Coordinate Control */
/*! @{ */
#define DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_MASK (0xFFFFU)
#define DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_SHIFT (0U)
/*! CROP_ULC_y - Starting Coordinate of Cropped Image X (1-Plane or 2-Plane Luma)
 */
#define DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y(x)   (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_SHIFT)) & DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_MASK)
/*! @} */

/*! @name FRAME_2P_BASE_ADDR_CTRL0 - Frame 2-Plane Base Address Control 0 */
/*! @{ */
#define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_MASK (0xFFFFFFFFU)
#define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT (0U)
/*! BASE_ADDR - Base Address
 */
#define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT)) & DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_MASK)
/*! @} */

/*! @name STATUS_CTRL0 - Status Control 0 */
/*! @{ */
#define DPR_STATUS_CTRL0_STATUS_MUX_SEL_MASK     (0x7U)
#define DPR_STATUS_CTRL0_STATUS_MUX_SEL_SHIFT    (0U)
/*! STATUS_MUX_SEL - Status Mux Select
 */
#define DPR_STATUS_CTRL0_STATUS_MUX_SEL(x)       (((uint32_t)(((uint32_t)(x)) << DPR_STATUS_CTRL0_STATUS_MUX_SEL_SHIFT)) & DPR_STATUS_CTRL0_STATUS_MUX_SEL_MASK)
#define DPR_STATUS_CTRL0_STATUS_SRC_SEL_MASK     (0x70000U)
#define DPR_STATUS_CTRL0_STATUS_SRC_SEL_SHIFT    (16U)
/*! STATUS_SRC_SEL - Status Source Select
 */
#define DPR_STATUS_CTRL0_STATUS_SRC_SEL(x)       (((uint32_t)(((uint32_t)(x)) << DPR_STATUS_CTRL0_STATUS_SRC_SEL_SHIFT)) & DPR_STATUS_CTRL0_STATUS_SRC_SEL_MASK)
/*! @} */

/*! @name STATUS_CTRL1 - Status Control 1 */
/*! @{ */
#define DPR_STATUS_CTRL1_STATUS_MASK             (0xFFFFFFFFU)
#define DPR_STATUS_CTRL1_STATUS_SHIFT            (0U)
/*! STATUS - Status Register
 */
#define DPR_STATUS_CTRL1_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << DPR_STATUS_CTRL1_STATUS_SHIFT)) & DPR_STATUS_CTRL1_STATUS_MASK)
/*! @} */

/*! @name RTRAM_CTRL0 - RTRAM Control 0 */
/*! @{ */
#define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_MASK     (0x1U)
#define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_SHIFT    (0U)
/*! NUM_ROWS_ACTIVE - Number of Rows Active
 */
#define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE(x)       (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_SHIFT)) & DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_MASK)
#define DPR_RTRAM_CTRL0_THRES_HIGH_MASK          (0xEU)
#define DPR_RTRAM_CTRL0_THRES_HIGH_SHIFT         (1U)
/*! THRES_HIGH - Threshold High
 */
#define DPR_RTRAM_CTRL0_THRES_HIGH(x)            (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_THRES_HIGH_SHIFT)) & DPR_RTRAM_CTRL0_THRES_HIGH_MASK)
#define DPR_RTRAM_CTRL0_THRES_LOW_MASK           (0x70U)
#define DPR_RTRAM_CTRL0_THRES_LOW_SHIFT          (4U)
/*! THRES_LOW - Threshold Low
 */
#define DPR_RTRAM_CTRL0_THRES_LOW(x)             (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_THRES_LOW_SHIFT)) & DPR_RTRAM_CTRL0_THRES_LOW_MASK)
#define DPR_RTRAM_CTRL0_ABORT_SEL_MASK           (0x80U)
#define DPR_RTRAM_CTRL0_ABORT_SEL_SHIFT          (7U)
/*! ABORT_SEL - Abort Select
 */
#define DPR_RTRAM_CTRL0_ABORT_SEL(x)             (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_ABORT_SEL_SHIFT)) & DPR_RTRAM_CTRL0_ABORT_SEL_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DPR_Register_Masks */


/* DPR - Peripheral instance base addresses */
/** Peripheral DC_0__DPR0 base address */
#define DC_0__DPR0_BASE                            (0x560D0000u)
/** Peripheral DC_0__DPR0 base pointer */
#define DC_0__DPR0                                 ((DPR_Type *)DC_0__DPR0_BASE)
/** Peripheral DC_0__DPR1 base address */
#define DC_0__DPR1_BASE                            (0x56100000u)
/** Peripheral DC_0__DPR1 base pointer */
#define DC_0__DPR1                                 ((DPR_Type *)DC_0__DPR1_BASE)
/** Peripheral DC_1__DPR0 base address */
#define DC_1__DPR0_BASE                            (0x570D0000u)
/** Peripheral DC_1__DPR0 base pointer */
#define DC_1__DPR0                                 ((DPR_Type *)DC_1__DPR0_BASE)
/** Peripheral DC_1__DPR1 base address */
#define DC_1__DPR1_BASE                            (0x57100000u)
/** Peripheral DC_1__DPR1 base pointer */
#define DC_1__DPR1                                 ((DPR_Type *)DC_1__DPR1_BASE)

/** Array initializer of DPR peripheral base addresses */
#define DPR_BASE_ADDRS                           { DC_0__DPR0_BASE, DC_0__DPR1_BASE, DC_1__DPR0_BASE, DC_1__DPR1_BASE }
/** Array initializer of DPR peripheral base pointers */
#define DPR_BASE_PTRS                            { DC_0__DPR0, DC_0__DPR1, DC_1__DPR0, DC_1__DPR1 }

/* Backward compatibility */
/** Peripheral DC_0__DPR0_CH0 base address */
#define DC_0__DPR0_CH0_BASE                        DC_0__DPR0_BASE
/** Peripheral DC_0__DPR0_CH0 base pointer */
#define DC_0__DPR0_CH0                             ((DPR_Type *)DC_0__DPR0_CH0_BASE)
/** Peripheral DC_0__DPR0_CH1 base address */
#define DC_0__DPR0_CH1_BASE                        (0x560E0000u)
/** Peripheral DC_0__DPR0_CH1 base pointer */
#define DC_0__DPR0_CH1                             ((DPR_Type *)DC_0__DPR0_CH1_BASE)
/** Peripheral DC_0__DPR0_CH2 base address */
#define DC_0__DPR0_CH2_BASE                        (0x560F0000u)
/** Peripheral DC_0__DPR0_CH2 base pointer */
#define DC_0__DPR0_CH2                             ((DPR_Type *)DC_0__DPR0_CH2_BASE)
/** Peripheral DC_0__DPR1_CH0 base address */
#define DC_0__DPR1_CH0_BASE                        DC_0__DPR1_BASE
/** Peripheral DC_0__DPR1_CH0 base pointer */
#define DC_0__DPR1_CH0                             ((DPR_Type *)DC_0__DPR1_CH0_BASE)
/** Peripheral DC_0__DPR1_CH1 base address */
#define DC_0__DPR1_CH1_BASE                        (0x56110000u)
/** Peripheral DC_0__DPR1_CH1 base pointer */
#define DC_0__DPR1_CH1                             ((DPR_Type *)DC_0__DPR1_CH1_BASE)
/** Peripheral DC_0__DPR1_CH2 base address */
#define DC_0__DPR1_CH2_BASE                        (0x56120000u)
/** Peripheral DC_0__DPR1_CH2 base pointer */
#define DC_0__DPR1_CH2                             ((DPR_Type *)DC_0__DPR1_CH2_BASE)
/** Peripheral DC_1__DPR0_CH0 base address */
#define DC_1__DPR0_CH0_BASE                        DC_1__DPR0_BASE
/** Peripheral DC_1__DPR0_CH0 base pointer */
#define DC_1__DPR0_CH0                             ((DPR_Type *)DC_1__DPR0_CH0_BASE)
/** Peripheral DC_1__DPR0_CH1 base address */
#define DC_1__DPR0_CH1_BASE                        (0x570E0000u)
/** Peripheral DC_1__DPR0_CH1 base pointer */
#define DC_1__DPR0_CH1                             ((DPR_Type *)DC_1__DPR0_CH1_BASE)
/** Peripheral DC_1__DPR0_CH2 base address */
#define DC_1__DPR0_CH2_BASE                        (0x570F0000u)
/** Peripheral DC_1__DPR0_CH2 base pointer */
#define DC_1__DPR0_CH2                             ((DPR_Type *)DC_1__DPR0_CH2_BASE)
/** Peripheral DC_1__DPR1_CH0 base address */
#define DC_1__DPR1_CH0_BASE                        DC_1__DPR1_BASE
/** Peripheral DC_1__DPR1_CH0 base pointer */
#define DC_1__DPR1_CH0                             ((DPR_Type *)DC_1__DPR1_CH0_BASE)
/** Peripheral DC_1__DPR1_CH1 base address */
#define DC_1__DPR1_CH1_BASE                        (0x57110000u)
/** Peripheral DC_1__DPR1_CH1 base pointer */
#define DC_1__DPR1_CH1                             ((DPR_Type *)DC_1__DPR1_CH1_BASE)
/** Peripheral DC_1__DPR1_CH2 base address */
#define DC_1__DPR1_CH2_BASE                        (0x57120000u)
/** Peripheral DC_1__DPR1_CH2 base pointer */
#define DC_1__DPR1_CH2                             ((DPR_Type *)DC_1__DPR1_CH2_BASE)

/** Array initializer of DPR peripheral base addresses */
#define DPR_CH_BASE_ADDRS                        { DC_0__DPR0_CH0_BASE, DC_0__DPR0_CH1_BASE, DC_0__DPR0_CH2_BASE, DC_0__DPR1_CH0_BASE, DC_0__DPR1_CH1_BASE, DC_0__DPR1_CH2_BASE, \
                                                   DC_1__DPR0_CH0_BASE, DC_1__DPR0_CH1_BASE, DC_1__DPR0_CH2_BASE, DC_1__DPR1_CH0_BASE, DC_1__DPR1_CH1_BASE, DC_1__DPR1_CH2_BASE }
/** Array initializer of DPR peripheral base pointers */
#define DPR_CH_BASE_PTRS                         { DC_0__DPR0_CH0, DC_0__DPR0_CH1, DC_0__DPR0_CH2, DC_0__DPR1_CH0, DC_0__DPR1_CH1, DC_0__DPR1_CH2, \
                                                   DC_1__DPR0_CH0, DC_1__DPR0_CH1, DC_1__DPR0_CH2, DC_1__DPR1_CH0, DC_1__DPR1_CH1, DC_1__DPR1_CH2 }


/*!
 * @}
 */ /* end of group DPR_Peripheral_Access_Layer */
 

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_ADC0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_ADC0_Peripheral_Access_Layer DMA_LPCG_ADC0 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_ADC0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_ANAMIX_ADC0_0;                /**< na, offset: 0x0 */
} DMA_LPCG_ADC0_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_ADC0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_ADC0_Register_Masks DMA_LPCG_ADC0 Register Masks
 * @{
 */

/*! @name LPCG_ANAMIX_ADC0_0 - na */
/*! @{ */
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_0_0_MASK (0x1U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_0_0_SHIFT (0U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_0_0_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_0_0_MASK)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_SWEN_MASK (0x2U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_SWEN_SHIFT (1U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_SWEN_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_SWEN_MASK)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_2_2_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_2_2_MASK)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_STOP_MASK (0x8U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_STOP_SHIFT (3U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_STOP_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_adc_clk_adc0_STOP_MASK)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_4_15_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_4_15_MASK)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_MASK (0x10000U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_SHIFT (16U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_s_adc0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_s_adc0_HWEN_MASK)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_MASK (0x20000U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_SHIFT (17U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN_MASK)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_18_18_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_18_18_MASK)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_MASK (0x80000U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_SHIFT (19U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP_MASK)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_20_31_SHIFT)) & DMA_LPCG_ADC0_LPCG_ANAMIX_ADC0_0_LPCG_ANAMIX_ADC0_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_ADC0_Register_Masks */


/* DMA_LPCG_ADC0 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_ADC0 base address */
#define DMA__LPCG_ADC0_BASE                      (0x5AC80000u)
/** Peripheral DMA__LPCG_ADC0 base pointer */
#define DMA__LPCG_ADC0                           ((DMA_LPCG_ADC0_Type *)DMA__LPCG_ADC0_BASE)
/** Array initializer of DMA_LPCG_ADC0 peripheral base addresses */
#define DMA_LPCG_ADC0_BASE_ADDRS                 { DMA__LPCG_ADC0_BASE }
/** Array initializer of DMA_LPCG_ADC0 peripheral base pointers */
#define DMA_LPCG_ADC0_BASE_PTRS                  { DMA__LPCG_ADC0 }

/*!
 * @}
 */ /* end of group DMA_LPCG_ADC0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_ADC1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_ADC1_Peripheral_Access_Layer DMA_LPCG_ADC1 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_ADC1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_ANAMIX_ADC1_0;                /**< na, offset: 0x0 */
} DMA_LPCG_ADC1_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_ADC1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_ADC1_Register_Masks DMA_LPCG_ADC1 Register Masks
 * @{
 */

/*! @name LPCG_ANAMIX_ADC1_0 - na */
/*! @{ */
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_0_0_MASK (0x1U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_0_0_SHIFT (0U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_0_0_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_0_0_MASK)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_SWEN_MASK (0x2U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_SWEN_SHIFT (1U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_SWEN_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_SWEN_MASK)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_2_2_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_2_2_MASK)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_STOP_MASK (0x8U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_STOP_SHIFT (3U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_STOP_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_adc_clk_adc1_STOP_MASK)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_4_15_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_4_15_MASK)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_s_adc1_HWEN_MASK (0x10000U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_s_adc1_HWEN_SHIFT (16U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_s_adc1_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_s_adc1_HWEN_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_s_adc1_HWEN_MASK)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_SWEN_AND_anamix_ipg_clk_s_adc1_SWEN_MASK (0x20000U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_SWEN_AND_anamix_ipg_clk_s_adc1_SWEN_SHIFT (17U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_SWEN_AND_anamix_ipg_clk_s_adc1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_SWEN_AND_anamix_ipg_clk_s_adc1_SWEN_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_SWEN_AND_anamix_ipg_clk_s_adc1_SWEN_MASK)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_18_18_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_18_18_MASK)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_STOP_AND_anamix_ipg_clk_s_adc1_STOP_MASK (0x80000U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_STOP_AND_anamix_ipg_clk_s_adc1_STOP_SHIFT (19U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_STOP_AND_anamix_ipg_clk_s_adc1_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_STOP_AND_anamix_ipg_clk_s_adc1_STOP_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_anamix_ipg_clk_adc1_STOP_AND_anamix_ipg_clk_s_adc1_STOP_MASK)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_20_31_SHIFT)) & DMA_LPCG_ADC1_LPCG_ANAMIX_ADC1_0_LPCG_ANAMIX_ADC1_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_ADC1_Register_Masks */


/* DMA_LPCG_ADC1 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_ADC1 base address */
#define DMA__LPCG_ADC1_BASE                      (0x5AC90000u)
/** Peripheral DMA__LPCG_ADC1 base pointer */
#define DMA__LPCG_ADC1                           ((DMA_LPCG_ADC1_Type *)DMA__LPCG_ADC1_BASE)
/** Array initializer of DMA_LPCG_ADC1 peripheral base addresses */
#define DMA_LPCG_ADC1_BASE_ADDRS                 { DMA__LPCG_ADC1_BASE }
/** Array initializer of DMA_LPCG_ADC1 peripheral base pointers */
#define DMA_LPCG_ADC1_BASE_PTRS                  { DMA__LPCG_ADC1 }

/*!
 * @}
 */ /* end of group DMA_LPCG_ADC1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_CAN0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_CAN0_Peripheral_Access_Layer DMA_LPCG_CAN0 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_CAN0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_CAN0_0;                       /**< na, offset: 0x0 */
} DMA_LPCG_CAN0_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_CAN0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_CAN0_Register_Masks DMA_LPCG_CAN0 Register Masks
 * @{
 */

/*! @name LPCG_CAN0_0 - na */
/*! @{ */
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_MASK (0x1U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_SHIFT (0U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_HWEN_MASK)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_SWEN_AND_can0_ipg_clk_pe_nogate_SWEN_MASK (0x2U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_SWEN_AND_can0_ipg_clk_pe_nogate_SWEN_SHIFT (1U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_SWEN_AND_can0_ipg_clk_pe_nogate_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_SWEN_AND_can0_ipg_clk_pe_nogate_SWEN_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_SWEN_AND_can0_ipg_clk_pe_nogate_SWEN_MASK)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_2_2_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_2_2_MASK)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_STOP_AND_can0_ipg_clk_pe_nogate_STOP_MASK (0x8U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_STOP_AND_can0_ipg_clk_pe_nogate_STOP_SHIFT (3U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_STOP_AND_can0_ipg_clk_pe_nogate_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_STOP_AND_can0_ipg_clk_pe_nogate_STOP_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_pe_STOP_AND_can0_ipg_clk_pe_nogate_STOP_MASK)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_4_15_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_4_15_MASK)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_18_18_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_18_18_MASK)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_MASK (0x100000U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_SHIFT (20U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_HWEN_MASK)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_MASK (0x200000U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_SHIFT (21U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_SWEN_MASK)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_22_22_MASK (0x400000U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_22_22_SHIFT (22U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_22_22_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_22_22_MASK)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_MASK (0x800000U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_SHIFT (23U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_can0_ipg_clk_chi_STOP_MASK)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_24_31_MASK (0xFF000000U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_24_31_SHIFT (24U)
#define DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_24_31_SHIFT)) & DMA_LPCG_CAN0_LPCG_CAN0_0_LPCG_CAN0_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_CAN0_Register_Masks */


/* DMA_LPCG_CAN0 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_CAN0 base address */
#define DMA__LPCG_CAN0_BASE                      (0x5ACD0000u)
/** Peripheral DMA__LPCG_CAN0 base pointer */
#define DMA__LPCG_CAN0                           ((DMA_LPCG_CAN0_Type *)DMA__LPCG_CAN0_BASE)
/** Array initializer of DMA_LPCG_CAN0 peripheral base addresses */
#define DMA_LPCG_CAN0_BASE_ADDRS                 { DMA__LPCG_CAN0_BASE }
/** Array initializer of DMA_LPCG_CAN0 peripheral base pointers */
#define DMA_LPCG_CAN0_BASE_PTRS                  { DMA__LPCG_CAN0 }

/*!
 * @}
 */ /* end of group DMA_LPCG_CAN0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_CAN1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_CAN1_Peripheral_Access_Layer DMA_LPCG_CAN1 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_CAN1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_CAN1_0;                       /**< na, offset: 0x0 */
} DMA_LPCG_CAN1_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_CAN1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_CAN1_Register_Masks DMA_LPCG_CAN1 Register Masks
 * @{
 */

/*! @name LPCG_CAN1_0 - na */
/*! @{ */
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_MASK (0x1U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_SHIFT (0U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_HWEN_MASK)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_SWEN_AND_can1_ipg_clk_pe_nogate_SWEN_MASK (0x2U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_SWEN_AND_can1_ipg_clk_pe_nogate_SWEN_SHIFT (1U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_SWEN_AND_can1_ipg_clk_pe_nogate_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_SWEN_AND_can1_ipg_clk_pe_nogate_SWEN_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_SWEN_AND_can1_ipg_clk_pe_nogate_SWEN_MASK)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_2_2_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_2_2_MASK)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_STOP_AND_can1_ipg_clk_pe_nogate_STOP_MASK (0x8U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_STOP_AND_can1_ipg_clk_pe_nogate_STOP_SHIFT (3U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_STOP_AND_can1_ipg_clk_pe_nogate_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_STOP_AND_can1_ipg_clk_pe_nogate_STOP_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_pe_STOP_AND_can1_ipg_clk_pe_nogate_STOP_MASK)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_4_15_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_4_15_MASK)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_18_18_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_18_18_MASK)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_MASK (0x100000U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_SHIFT (20U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_HWEN_MASK)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_MASK (0x200000U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_SHIFT (21U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_SWEN_MASK)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_22_22_MASK (0x400000U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_22_22_SHIFT (22U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_22_22_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_22_22_MASK)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_MASK (0x800000U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_SHIFT (23U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_can1_ipg_clk_chi_STOP_MASK)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_24_31_MASK (0xFF000000U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_24_31_SHIFT (24U)
#define DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_24_31_SHIFT)) & DMA_LPCG_CAN1_LPCG_CAN1_0_LPCG_CAN1_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_CAN1_Register_Masks */


/* DMA_LPCG_CAN1 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_CAN1 base address */
#define DMA__LPCG_CAN1_BASE                      (0x5ACE0000u)
/** Peripheral DMA__LPCG_CAN1 base pointer */
#define DMA__LPCG_CAN1                           ((DMA_LPCG_CAN1_Type *)DMA__LPCG_CAN1_BASE)
/** Array initializer of DMA_LPCG_CAN1 peripheral base addresses */
#define DMA_LPCG_CAN1_BASE_ADDRS                 { DMA__LPCG_CAN1_BASE }
/** Array initializer of DMA_LPCG_CAN1 peripheral base pointers */
#define DMA_LPCG_CAN1_BASE_PTRS                  { DMA__LPCG_CAN1 }

/*!
 * @}
 */ /* end of group DMA_LPCG_CAN1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_CAN2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_CAN2_Peripheral_Access_Layer DMA_LPCG_CAN2 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_CAN2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_CAN2_0;                       /**< na, offset: 0x0 */
} DMA_LPCG_CAN2_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_CAN2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_CAN2_Register_Masks DMA_LPCG_CAN2 Register Masks
 * @{
 */

/*! @name LPCG_CAN2_0 - na */
/*! @{ */
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_MASK (0x1U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_SHIFT (0U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_HWEN_MASK)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_SWEN_AND_can2_ipg_clk_pe_nogate_SWEN_MASK (0x2U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_SWEN_AND_can2_ipg_clk_pe_nogate_SWEN_SHIFT (1U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_SWEN_AND_can2_ipg_clk_pe_nogate_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_SWEN_AND_can2_ipg_clk_pe_nogate_SWEN_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_SWEN_AND_can2_ipg_clk_pe_nogate_SWEN_MASK)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_2_2_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_2_2_MASK)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_STOP_AND_can2_ipg_clk_pe_nogate_STOP_MASK (0x8U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_STOP_AND_can2_ipg_clk_pe_nogate_STOP_SHIFT (3U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_STOP_AND_can2_ipg_clk_pe_nogate_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_STOP_AND_can2_ipg_clk_pe_nogate_STOP_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_pe_STOP_AND_can2_ipg_clk_pe_nogate_STOP_MASK)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_4_15_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_4_15_MASK)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_18_18_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_18_18_MASK)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_MASK (0x100000U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_SHIFT (20U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_HWEN_MASK)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_MASK (0x200000U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_SHIFT (21U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_SWEN_MASK)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_22_22_MASK (0x400000U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_22_22_SHIFT (22U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_22_22_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_22_22_MASK)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_MASK (0x800000U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_SHIFT (23U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_can2_ipg_clk_chi_STOP_MASK)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_24_31_MASK (0xFF000000U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_24_31_SHIFT (24U)
#define DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_24_31_SHIFT)) & DMA_LPCG_CAN2_LPCG_CAN2_0_LPCG_CAN2_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_CAN2_Register_Masks */


/* DMA_LPCG_CAN2 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_CAN2 base address */
#define DMA__LPCG_CAN2_BASE                      (0x5ACF0000u)
/** Peripheral DMA__LPCG_CAN2 base pointer */
#define DMA__LPCG_CAN2                           ((DMA_LPCG_CAN2_Type *)DMA__LPCG_CAN2_BASE)
/** Array initializer of DMA_LPCG_CAN2 peripheral base addresses */
#define DMA_LPCG_CAN2_BASE_ADDRS                 { DMA__LPCG_CAN2_BASE }
/** Array initializer of DMA_LPCG_CAN2 peripheral base pointers */
#define DMA_LPCG_CAN2_BASE_PTRS                  { DMA__LPCG_CAN2 }

/*!
 * @}
 */ /* end of group DMA_LPCG_CAN2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_EMV_SIM0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_EMV_SIM0_Peripheral_Access_Layer DMA_LPCG_EMV_SIM0 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_EMV_SIM0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_EMV_SIM0_0;                   /**< na, offset: 0x0 */
} DMA_LPCG_EMV_SIM0_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_EMV_SIM0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_EMV_SIM0_Register_Masks DMA_LPCG_EMV_SIM0 Register Masks
 * @{
 */

/*! @name LPCG_EMV_SIM0_0 - na */
/*! @{ */
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_HWEN_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_HWEN_MASK)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_SWEN_AND_emv_sim0_ipg_ungated_sim_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_SWEN_AND_emv_sim0_ipg_ungated_sim_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_SWEN_AND_emv_sim0_ipg_ungated_sim_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_SWEN_AND_emv_sim0_ipg_ungated_sim_clk_SWEN_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_SWEN_AND_emv_sim0_ipg_ungated_sim_clk_SWEN_MASK)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_2_2_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_2_2_MASK)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_STOP_AND_emv_sim0_ipg_ungated_sim_clk_STOP_MASK (0x8U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_STOP_AND_emv_sim0_ipg_ungated_sim_clk_STOP_SHIFT (3U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_STOP_AND_emv_sim0_ipg_ungated_sim_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_STOP_AND_emv_sim0_ipg_ungated_sim_clk_STOP_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_sim_clk_STOP_AND_emv_sim0_ipg_ungated_sim_clk_STOP_MASK)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_4_15_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_4_15_MASK)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_SWEN_AND_emv_sim0_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_SWEN_AND_emv_sim0_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_SWEN_AND_emv_sim0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_SWEN_AND_emv_sim0_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_SWEN_AND_emv_sim0_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_18_18_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_18_18_MASK)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_STOP_AND_emv_sim0_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_STOP_AND_emv_sim0_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_STOP_AND_emv_sim0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_STOP_AND_emv_sim0_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_emv_sim0_ipg_clk_STOP_AND_emv_sim0_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_20_31_SHIFT)) & DMA_LPCG_EMV_SIM0_LPCG_EMV_SIM0_0_LPCG_EMV_SIM0_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_EMV_SIM0_Register_Masks */


/* DMA_LPCG_EMV_SIM0 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_EMV_SIM0 base address */
#define DMA__LPCG_EMV_SIM0_BASE                  (0x5A4D0000u)
/** Peripheral DMA__LPCG_EMV_SIM0 base pointer */
#define DMA__LPCG_EMV_SIM0                       ((DMA_LPCG_EMV_SIM0_Type *)DMA__LPCG_EMV_SIM0_BASE)
/** Array initializer of DMA_LPCG_EMV_SIM0 peripheral base addresses */
#define DMA_LPCG_EMV_SIM0_BASE_ADDRS             { DMA__LPCG_EMV_SIM0_BASE }
/** Array initializer of DMA_LPCG_EMV_SIM0 peripheral base pointers */
#define DMA_LPCG_EMV_SIM0_BASE_PTRS              { DMA__LPCG_EMV_SIM0 }

/*!
 * @}
 */ /* end of group DMA_LPCG_EMV_SIM0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_EMV_SIM1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_EMV_SIM1_Peripheral_Access_Layer DMA_LPCG_EMV_SIM1 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_EMV_SIM1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_EMV_SIM1_0;                   /**< na, offset: 0x0 */
} DMA_LPCG_EMV_SIM1_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_EMV_SIM1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_EMV_SIM1_Register_Masks DMA_LPCG_EMV_SIM1 Register Masks
 * @{
 */

/*! @name LPCG_EMV_SIM1_0 - na */
/*! @{ */
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_HWEN_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_HWEN_MASK)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_SWEN_AND_emv_sim1_ipg_ungated_sim_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_SWEN_AND_emv_sim1_ipg_ungated_sim_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_SWEN_AND_emv_sim1_ipg_ungated_sim_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_SWEN_AND_emv_sim1_ipg_ungated_sim_clk_SWEN_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_SWEN_AND_emv_sim1_ipg_ungated_sim_clk_SWEN_MASK)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_2_2_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_2_2_MASK)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_STOP_AND_emv_sim1_ipg_ungated_sim_clk_STOP_MASK (0x8U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_STOP_AND_emv_sim1_ipg_ungated_sim_clk_STOP_SHIFT (3U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_STOP_AND_emv_sim1_ipg_ungated_sim_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_STOP_AND_emv_sim1_ipg_ungated_sim_clk_STOP_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_sim_clk_STOP_AND_emv_sim1_ipg_ungated_sim_clk_STOP_MASK)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_4_15_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_4_15_MASK)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_SWEN_AND_emv_sim1_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_SWEN_AND_emv_sim1_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_SWEN_AND_emv_sim1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_SWEN_AND_emv_sim1_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_SWEN_AND_emv_sim1_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_18_18_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_18_18_MASK)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_STOP_AND_emv_sim1_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_STOP_AND_emv_sim1_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_STOP_AND_emv_sim1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_STOP_AND_emv_sim1_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_emv_sim1_ipg_clk_STOP_AND_emv_sim1_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_20_31_SHIFT)) & DMA_LPCG_EMV_SIM1_LPCG_EMV_SIM1_0_LPCG_EMV_SIM1_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_EMV_SIM1_Register_Masks */


/* DMA_LPCG_EMV_SIM1 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_EMV_SIM1 base address */
#define DMA__LPCG_EMV_SIM1_BASE                  (0x5A4E0000u)
/** Peripheral DMA__LPCG_EMV_SIM1 base pointer */
#define DMA__LPCG_EMV_SIM1                       ((DMA_LPCG_EMV_SIM1_Type *)DMA__LPCG_EMV_SIM1_BASE)
/** Array initializer of DMA_LPCG_EMV_SIM1 peripheral base addresses */
#define DMA_LPCG_EMV_SIM1_BASE_ADDRS             { DMA__LPCG_EMV_SIM1_BASE }
/** Array initializer of DMA_LPCG_EMV_SIM1 peripheral base pointers */
#define DMA_LPCG_EMV_SIM1_BASE_PTRS              { DMA__LPCG_EMV_SIM1 }

/*!
 * @}
 */ /* end of group DMA_LPCG_EMV_SIM1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_FTM0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_FTM0_Peripheral_Access_Layer DMA_LPCG_FTM0 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_FTM0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_FTM0_0;                       /**< na, offset: 0x0 */
} DMA_LPCG_FTM0_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_FTM0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_FTM0_Register_Masks DMA_LPCG_FTM0 Register Masks
 * @{
 */

/*! @name LPCG_FTM0_0 - na */
/*! @{ */
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_MASK (0x1U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_SHIFT (0U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_HWEN_MASK)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_MASK (0x2U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_SHIFT (1U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_SWEN_MASK)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_2_2_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_2_2_MASK)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_MASK (0x8U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_SHIFT (3U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipp_ind_extclk_STOP_MASK)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_4_15_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_4_15_MASK)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_18_18_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_18_18_MASK)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_20_31_SHIFT)) & DMA_LPCG_FTM0_LPCG_FTM0_0_LPCG_FTM0_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_FTM0_Register_Masks */


/* DMA_LPCG_FTM0 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_FTM0 base address */
#define DMA__LPCG_FTM0_BASE                      (0x5ACA0000u)
/** Peripheral DMA__LPCG_FTM0 base pointer */
#define DMA__LPCG_FTM0                           ((DMA_LPCG_FTM0_Type *)DMA__LPCG_FTM0_BASE)
/** Array initializer of DMA_LPCG_FTM0 peripheral base addresses */
#define DMA_LPCG_FTM0_BASE_ADDRS                 { DMA__LPCG_FTM0_BASE }
/** Array initializer of DMA_LPCG_FTM0 peripheral base pointers */
#define DMA_LPCG_FTM0_BASE_PTRS                  { DMA__LPCG_FTM0 }

/*!
 * @}
 */ /* end of group DMA_LPCG_FTM0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_FTM1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_FTM1_Peripheral_Access_Layer DMA_LPCG_FTM1 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_FTM1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_FTM1_0;                       /**< na, offset: 0x0 */
} DMA_LPCG_FTM1_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_FTM1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_FTM1_Register_Masks DMA_LPCG_FTM1 Register Masks
 * @{
 */

/*! @name LPCG_FTM1_0 - na */
/*! @{ */
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_MASK (0x1U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_SHIFT (0U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_HWEN_MASK)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_MASK (0x2U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_SHIFT (1U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_SWEN_MASK)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_2_2_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_2_2_MASK)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_MASK (0x8U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_SHIFT (3U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipp_ind_extclk_STOP_MASK)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_4_15_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_4_15_MASK)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_18_18_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_18_18_MASK)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_20_31_SHIFT)) & DMA_LPCG_FTM1_LPCG_FTM1_0_LPCG_FTM1_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_FTM1_Register_Masks */


/* DMA_LPCG_FTM1 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_FTM1 base address */
#define DMA__LPCG_FTM1_BASE                      (0x5ACB0000u)
/** Peripheral DMA__LPCG_FTM1 base pointer */
#define DMA__LPCG_FTM1                           ((DMA_LPCG_FTM1_Type *)DMA__LPCG_FTM1_BASE)
/** Array initializer of DMA_LPCG_FTM1 peripheral base addresses */
#define DMA_LPCG_FTM1_BASE_ADDRS                 { DMA__LPCG_FTM1_BASE }
/** Array initializer of DMA_LPCG_FTM1 peripheral base pointers */
#define DMA_LPCG_FTM1_BASE_PTRS                  { DMA__LPCG_FTM1 }

/*!
 * @}
 */ /* end of group DMA_LPCG_FTM1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPI2C0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPI2C0_Peripheral_Access_Layer DMA_LPCG_LPI2C0 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_LPI2C0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPI2C0_0;                     /**< na, offset: 0x0 */
} DMA_LPCG_LPI2C0_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPI2C0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPI2C0_Register_Masks DMA_LPCG_LPI2C0 Register Masks
 * @{
 */

/*! @name LPCG_LPI2C0_0 - na */
/*! @{ */
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_div_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_div_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_div_clk_HWEN_MASK)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_SWEN_AND_lpi2c0_lpi2c_div_clk_SWEN_MASK)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_2_2_MASK)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK (0x8U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT (3U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_lpi2c_clk_STOP_AND_lpi2c0_lpi2c_div_clk_STOP_MASK)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_4_15_MASK)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_SWEN_AND_lpi2c0_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_18_18_MASK)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_lpi2c0_ipg_clk_STOP_AND_lpi2c0_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPI2C0_LPCG_LPI2C0_0_LPCG_LPI2C0_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_LPI2C0_Register_Masks */


/* DMA_LPCG_LPI2C0 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_LPI2C0 base address */
#define DMA__LPCG_LPI2C0_BASE                    (0x5AC00000u)
/** Peripheral DMA__LPCG_LPI2C0 base pointer */
#define DMA__LPCG_LPI2C0                         ((DMA_LPCG_LPI2C0_Type *)DMA__LPCG_LPI2C0_BASE)
/** Array initializer of DMA_LPCG_LPI2C0 peripheral base addresses */
#define DMA_LPCG_LPI2C0_BASE_ADDRS               { DMA__LPCG_LPI2C0_BASE }
/** Array initializer of DMA_LPCG_LPI2C0 peripheral base pointers */
#define DMA_LPCG_LPI2C0_BASE_PTRS                { DMA__LPCG_LPI2C0 }

/*!
 * @}
 */ /* end of group DMA_LPCG_LPI2C0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPI2C1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPI2C1_Peripheral_Access_Layer DMA_LPCG_LPI2C1 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_LPI2C1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPI2C1_0;                     /**< na, offset: 0x0 */
} DMA_LPCG_LPI2C1_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPI2C1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPI2C1_Register_Masks DMA_LPCG_LPI2C1 Register Masks
 * @{
 */

/*! @name LPCG_LPI2C1_0 - na */
/*! @{ */
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_div_clk_HWEN_MASK)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_2_2_MASK)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_4_15_MASK)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_SWEN_AND_lpi2c1_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_18_18_MASK)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_lpi2c1_ipg_clk_STOP_AND_lpi2c1_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPI2C1_LPCG_LPI2C1_0_LPCG_LPI2C1_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_LPI2C1_Register_Masks */


/* DMA_LPCG_LPI2C1 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_LPI2C1 base address */
#define DMA__LPCG_LPI2C1_BASE                    (0x5AC10000u)
/** Peripheral DMA__LPCG_LPI2C1 base pointer */
#define DMA__LPCG_LPI2C1                         ((DMA_LPCG_LPI2C1_Type *)DMA__LPCG_LPI2C1_BASE)
/** Array initializer of DMA_LPCG_LPI2C1 peripheral base addresses */
#define DMA_LPCG_LPI2C1_BASE_ADDRS               { DMA__LPCG_LPI2C1_BASE }
/** Array initializer of DMA_LPCG_LPI2C1 peripheral base pointers */
#define DMA_LPCG_LPI2C1_BASE_PTRS                { DMA__LPCG_LPI2C1 }

/*!
 * @}
 */ /* end of group DMA_LPCG_LPI2C1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPI2C2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPI2C2_Peripheral_Access_Layer DMA_LPCG_LPI2C2 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_LPI2C2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPI2C2_0;                     /**< na, offset: 0x0 */
} DMA_LPCG_LPI2C2_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPI2C2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPI2C2_Register_Masks DMA_LPCG_LPI2C2 Register Masks
 * @{
 */

/*! @name LPCG_LPI2C2_0 - na */
/*! @{ */
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_div_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_div_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_div_clk_HWEN_MASK)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_SWEN_AND_lpi2c2_lpi2c_div_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_SWEN_AND_lpi2c2_lpi2c_div_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_SWEN_AND_lpi2c2_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_SWEN_AND_lpi2c2_lpi2c_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_SWEN_AND_lpi2c2_lpi2c_div_clk_SWEN_MASK)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_2_2_MASK)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_STOP_AND_lpi2c2_lpi2c_div_clk_STOP_MASK (0x8U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_STOP_AND_lpi2c2_lpi2c_div_clk_STOP_SHIFT (3U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_STOP_AND_lpi2c2_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_STOP_AND_lpi2c2_lpi2c_div_clk_STOP_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_lpi2c_clk_STOP_AND_lpi2c2_lpi2c_div_clk_STOP_MASK)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_4_15_MASK)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_SWEN_AND_lpi2c2_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_SWEN_AND_lpi2c2_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_SWEN_AND_lpi2c2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_SWEN_AND_lpi2c2_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_SWEN_AND_lpi2c2_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_18_18_MASK)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_STOP_AND_lpi2c2_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_STOP_AND_lpi2c2_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_STOP_AND_lpi2c2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_STOP_AND_lpi2c2_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_lpi2c2_ipg_clk_STOP_AND_lpi2c2_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPI2C2_LPCG_LPI2C2_0_LPCG_LPI2C2_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_LPI2C2_Register_Masks */


/* DMA_LPCG_LPI2C2 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_LPI2C2 base address */
#define DMA__LPCG_LPI2C2_BASE                    (0x5AC20000u)
/** Peripheral DMA__LPCG_LPI2C2 base pointer */
#define DMA__LPCG_LPI2C2                         ((DMA_LPCG_LPI2C2_Type *)DMA__LPCG_LPI2C2_BASE)
/** Array initializer of DMA_LPCG_LPI2C2 peripheral base addresses */
#define DMA_LPCG_LPI2C2_BASE_ADDRS               { DMA__LPCG_LPI2C2_BASE }
/** Array initializer of DMA_LPCG_LPI2C2 peripheral base pointers */
#define DMA_LPCG_LPI2C2_BASE_PTRS                { DMA__LPCG_LPI2C2 }

/*!
 * @}
 */ /* end of group DMA_LPCG_LPI2C2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPI2C3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPI2C3_Peripheral_Access_Layer DMA_LPCG_LPI2C3 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_LPI2C3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPI2C3_0;                     /**< na, offset: 0x0 */
} DMA_LPCG_LPI2C3_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPI2C3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPI2C3_Register_Masks DMA_LPCG_LPI2C3 Register Masks
 * @{
 */

/*! @name LPCG_LPI2C3_0 - na */
/*! @{ */
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_div_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_div_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_div_clk_HWEN_MASK)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_SWEN_AND_lpi2c3_lpi2c_div_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_SWEN_AND_lpi2c3_lpi2c_div_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_SWEN_AND_lpi2c3_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_SWEN_AND_lpi2c3_lpi2c_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_SWEN_AND_lpi2c3_lpi2c_div_clk_SWEN_MASK)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_2_2_MASK)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_STOP_AND_lpi2c3_lpi2c_div_clk_STOP_MASK (0x8U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_STOP_AND_lpi2c3_lpi2c_div_clk_STOP_SHIFT (3U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_STOP_AND_lpi2c3_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_STOP_AND_lpi2c3_lpi2c_div_clk_STOP_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_lpi2c_clk_STOP_AND_lpi2c3_lpi2c_div_clk_STOP_MASK)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_4_15_MASK)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_SWEN_AND_lpi2c3_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_SWEN_AND_lpi2c3_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_SWEN_AND_lpi2c3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_SWEN_AND_lpi2c3_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_SWEN_AND_lpi2c3_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_18_18_MASK)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_STOP_AND_lpi2c3_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_STOP_AND_lpi2c3_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_STOP_AND_lpi2c3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_STOP_AND_lpi2c3_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_lpi2c3_ipg_clk_STOP_AND_lpi2c3_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPI2C3_LPCG_LPI2C3_0_LPCG_LPI2C3_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_LPI2C3_Register_Masks */


/* DMA_LPCG_LPI2C3 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_LPI2C3 base address */
#define DMA__LPCG_LPI2C3_BASE                    (0x5AC30000u)
/** Peripheral DMA__LPCG_LPI2C3 base pointer */
#define DMA__LPCG_LPI2C3                         ((DMA_LPCG_LPI2C3_Type *)DMA__LPCG_LPI2C3_BASE)
/** Array initializer of DMA_LPCG_LPI2C3 peripheral base addresses */
#define DMA_LPCG_LPI2C3_BASE_ADDRS               { DMA__LPCG_LPI2C3_BASE }
/** Array initializer of DMA_LPCG_LPI2C3 peripheral base pointers */
#define DMA_LPCG_LPI2C3_BASE_PTRS                { DMA__LPCG_LPI2C3 }

/*!
 * @}
 */ /* end of group DMA_LPCG_LPI2C3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPI2C4 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPI2C4_Peripheral_Access_Layer DMA_LPCG_LPI2C4 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_LPI2C4 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPI2C4_0;                     /**< na, offset: 0x0 */
} DMA_LPCG_LPI2C4_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPI2C4 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPI2C4_Register_Masks DMA_LPCG_LPI2C4 Register Masks
 * @{
 */

/*! @name LPCG_LPI2C4_0 - na */
/*! @{ */
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_div_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_div_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_div_clk_HWEN_MASK)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_SWEN_AND_lpi2c4_lpi2c_div_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_SWEN_AND_lpi2c4_lpi2c_div_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_SWEN_AND_lpi2c4_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_SWEN_AND_lpi2c4_lpi2c_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_SWEN_AND_lpi2c4_lpi2c_div_clk_SWEN_MASK)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_2_2_MASK)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_STOP_AND_lpi2c4_lpi2c_div_clk_STOP_MASK (0x8U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_STOP_AND_lpi2c4_lpi2c_div_clk_STOP_SHIFT (3U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_STOP_AND_lpi2c4_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_STOP_AND_lpi2c4_lpi2c_div_clk_STOP_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_lpi2c_clk_STOP_AND_lpi2c4_lpi2c_div_clk_STOP_MASK)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_4_15_MASK)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_SWEN_AND_lpi2c4_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_SWEN_AND_lpi2c4_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_SWEN_AND_lpi2c4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_SWEN_AND_lpi2c4_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_SWEN_AND_lpi2c4_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_18_18_MASK)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_STOP_AND_lpi2c4_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_STOP_AND_lpi2c4_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_STOP_AND_lpi2c4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_STOP_AND_lpi2c4_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_lpi2c4_ipg_clk_STOP_AND_lpi2c4_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPI2C4_LPCG_LPI2C4_0_LPCG_LPI2C4_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_LPI2C4_Register_Masks */


/* DMA_LPCG_LPI2C4 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_LPI2C4 base address */
#define DMA__LPCG_LPI2C4_BASE                    (0x5AC40000u)
/** Peripheral DMA__LPCG_LPI2C4 base pointer */
#define DMA__LPCG_LPI2C4                         ((DMA_LPCG_LPI2C4_Type *)DMA__LPCG_LPI2C4_BASE)
/** Array initializer of DMA_LPCG_LPI2C4 peripheral base addresses */
#define DMA_LPCG_LPI2C4_BASE_ADDRS               { DMA__LPCG_LPI2C4_BASE }
/** Array initializer of DMA_LPCG_LPI2C4 peripheral base pointers */
#define DMA_LPCG_LPI2C4_BASE_PTRS                { DMA__LPCG_LPI2C4 }

/*!
 * @}
 */ /* end of group DMA_LPCG_LPI2C4_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPSPI0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPSPI0_Peripheral_Access_Layer DMA_LPCG_LPSPI0 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_LPSPI0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPSPI0_0;                     /**< na, offset: 0x0 */
} DMA_LPCG_LPSPI0_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPSPI0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPSPI0_Register_Masks DMA_LPCG_LPSPI0 Register Masks
 * @{
 */

/*! @name LPCG_LPSPI0_0 - na */
/*! @{ */
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_div_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_div_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_div_clk_HWEN_MASK)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_SWEN_AND_lpspi0_lpspi_div_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_SWEN_AND_lpspi0_lpspi_div_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_SWEN_AND_lpspi0_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_SWEN_AND_lpspi0_lpspi_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_SWEN_AND_lpspi0_lpspi_div_clk_SWEN_MASK)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_2_2_MASK)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_STOP_AND_lpspi0_lpspi_div_clk_STOP_MASK (0x8U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_STOP_AND_lpspi0_lpspi_div_clk_STOP_SHIFT (3U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_STOP_AND_lpspi0_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_STOP_AND_lpspi0_lpspi_div_clk_STOP_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_lpspi_clk_STOP_AND_lpspi0_lpspi_div_clk_STOP_MASK)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_4_15_MASK)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_SWEN_AND_lpspi0_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_SWEN_AND_lpspi0_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_SWEN_AND_lpspi0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_SWEN_AND_lpspi0_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_SWEN_AND_lpspi0_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_18_18_MASK)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_STOP_AND_lpspi0_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_STOP_AND_lpspi0_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_STOP_AND_lpspi0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_STOP_AND_lpspi0_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_lpspi0_ipg_clk_STOP_AND_lpspi0_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPSPI0_LPCG_LPSPI0_0_LPCG_LPSPI0_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_LPSPI0_Register_Masks */


/* DMA_LPCG_LPSPI0 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_LPSPI0 base address */
#define DMA__LPCG_LPSPI0_BASE                    (0x5A400000u)
/** Peripheral DMA__LPCG_LPSPI0 base pointer */
#define DMA__LPCG_LPSPI0                         ((DMA_LPCG_LPSPI0_Type *)DMA__LPCG_LPSPI0_BASE)
/** Array initializer of DMA_LPCG_LPSPI0 peripheral base addresses */
#define DMA_LPCG_LPSPI0_BASE_ADDRS               { DMA__LPCG_LPSPI0_BASE }
/** Array initializer of DMA_LPCG_LPSPI0 peripheral base pointers */
#define DMA_LPCG_LPSPI0_BASE_PTRS                { DMA__LPCG_LPSPI0 }

/*!
 * @}
 */ /* end of group DMA_LPCG_LPSPI0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPSPI1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPSPI1_Peripheral_Access_Layer DMA_LPCG_LPSPI1 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_LPSPI1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPSPI1_0;                     /**< na, offset: 0x0 */
} DMA_LPCG_LPSPI1_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPSPI1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPSPI1_Register_Masks DMA_LPCG_LPSPI1 Register Masks
 * @{
 */

/*! @name LPCG_LPSPI1_0 - na */
/*! @{ */
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_div_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_div_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_div_clk_HWEN_MASK)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_SWEN_AND_lpspi1_lpspi_div_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_SWEN_AND_lpspi1_lpspi_div_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_SWEN_AND_lpspi1_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_SWEN_AND_lpspi1_lpspi_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_SWEN_AND_lpspi1_lpspi_div_clk_SWEN_MASK)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_2_2_MASK)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_STOP_AND_lpspi1_lpspi_div_clk_STOP_MASK (0x8U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_STOP_AND_lpspi1_lpspi_div_clk_STOP_SHIFT (3U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_STOP_AND_lpspi1_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_STOP_AND_lpspi1_lpspi_div_clk_STOP_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_lpspi_clk_STOP_AND_lpspi1_lpspi_div_clk_STOP_MASK)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_4_15_MASK)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_SWEN_AND_lpspi1_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_SWEN_AND_lpspi1_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_SWEN_AND_lpspi1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_SWEN_AND_lpspi1_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_SWEN_AND_lpspi1_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_18_18_MASK)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_STOP_AND_lpspi1_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_STOP_AND_lpspi1_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_STOP_AND_lpspi1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_STOP_AND_lpspi1_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_lpspi1_ipg_clk_STOP_AND_lpspi1_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPSPI1_LPCG_LPSPI1_0_LPCG_LPSPI1_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_LPSPI1_Register_Masks */


/* DMA_LPCG_LPSPI1 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_LPSPI1 base address */
#define DMA__LPCG_LPSPI1_BASE                    (0x5A410000u)
/** Peripheral DMA__LPCG_LPSPI1 base pointer */
#define DMA__LPCG_LPSPI1                         ((DMA_LPCG_LPSPI1_Type *)DMA__LPCG_LPSPI1_BASE)
/** Array initializer of DMA_LPCG_LPSPI1 peripheral base addresses */
#define DMA_LPCG_LPSPI1_BASE_ADDRS               { DMA__LPCG_LPSPI1_BASE }
/** Array initializer of DMA_LPCG_LPSPI1 peripheral base pointers */
#define DMA_LPCG_LPSPI1_BASE_PTRS                { DMA__LPCG_LPSPI1 }

/*!
 * @}
 */ /* end of group DMA_LPCG_LPSPI1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPSPI2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPSPI2_Peripheral_Access_Layer DMA_LPCG_LPSPI2 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_LPSPI2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPSPI2_0;                     /**< na, offset: 0x0 */
} DMA_LPCG_LPSPI2_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPSPI2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPSPI2_Register_Masks DMA_LPCG_LPSPI2 Register Masks
 * @{
 */

/*! @name LPCG_LPSPI2_0 - na */
/*! @{ */
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_div_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_div_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_div_clk_HWEN_MASK)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_SWEN_AND_lpspi2_lpspi_div_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_SWEN_AND_lpspi2_lpspi_div_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_SWEN_AND_lpspi2_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_SWEN_AND_lpspi2_lpspi_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_SWEN_AND_lpspi2_lpspi_div_clk_SWEN_MASK)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_2_2_MASK)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_STOP_AND_lpspi2_lpspi_div_clk_STOP_MASK (0x8U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_STOP_AND_lpspi2_lpspi_div_clk_STOP_SHIFT (3U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_STOP_AND_lpspi2_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_STOP_AND_lpspi2_lpspi_div_clk_STOP_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_lpspi_clk_STOP_AND_lpspi2_lpspi_div_clk_STOP_MASK)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_4_15_MASK)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_SWEN_AND_lpspi2_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_SWEN_AND_lpspi2_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_SWEN_AND_lpspi2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_SWEN_AND_lpspi2_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_SWEN_AND_lpspi2_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_18_18_MASK)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_STOP_AND_lpspi2_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_STOP_AND_lpspi2_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_STOP_AND_lpspi2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_STOP_AND_lpspi2_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_lpspi2_ipg_clk_STOP_AND_lpspi2_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPSPI2_LPCG_LPSPI2_0_LPCG_LPSPI2_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_LPSPI2_Register_Masks */


/* DMA_LPCG_LPSPI2 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_LPSPI2 base address */
#define DMA__LPCG_LPSPI2_BASE                    (0x5A420000u)
/** Peripheral DMA__LPCG_LPSPI2 base pointer */
#define DMA__LPCG_LPSPI2                         ((DMA_LPCG_LPSPI2_Type *)DMA__LPCG_LPSPI2_BASE)
/** Array initializer of DMA_LPCG_LPSPI2 peripheral base addresses */
#define DMA_LPCG_LPSPI2_BASE_ADDRS               { DMA__LPCG_LPSPI2_BASE }
/** Array initializer of DMA_LPCG_LPSPI2 peripheral base pointers */
#define DMA_LPCG_LPSPI2_BASE_PTRS                { DMA__LPCG_LPSPI2 }

/*!
 * @}
 */ /* end of group DMA_LPCG_LPSPI2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPSPI3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPSPI3_Peripheral_Access_Layer DMA_LPCG_LPSPI3 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_LPSPI3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPSPI3_0;                     /**< na, offset: 0x0 */
} DMA_LPCG_LPSPI3_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPSPI3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPSPI3_Register_Masks DMA_LPCG_LPSPI3 Register Masks
 * @{
 */

/*! @name LPCG_LPSPI3_0 - na */
/*! @{ */
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_div_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_div_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_div_clk_HWEN_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_div_clk_HWEN_MASK)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_SWEN_AND_lpspi3_lpspi_div_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_SWEN_AND_lpspi3_lpspi_div_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_SWEN_AND_lpspi3_lpspi_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_SWEN_AND_lpspi3_lpspi_div_clk_SWEN_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_SWEN_AND_lpspi3_lpspi_div_clk_SWEN_MASK)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_2_2_MASK)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_STOP_AND_lpspi3_lpspi_div_clk_STOP_MASK (0x8U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_STOP_AND_lpspi3_lpspi_div_clk_STOP_SHIFT (3U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_STOP_AND_lpspi3_lpspi_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_STOP_AND_lpspi3_lpspi_div_clk_STOP_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_lpspi_clk_STOP_AND_lpspi3_lpspi_div_clk_STOP_MASK)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_4_15_MASK)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_SWEN_AND_lpspi3_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_SWEN_AND_lpspi3_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_SWEN_AND_lpspi3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_SWEN_AND_lpspi3_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_SWEN_AND_lpspi3_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_18_18_MASK)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_STOP_AND_lpspi3_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_STOP_AND_lpspi3_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_STOP_AND_lpspi3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_STOP_AND_lpspi3_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_lpspi3_ipg_clk_STOP_AND_lpspi3_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPSPI3_LPCG_LPSPI3_0_LPCG_LPSPI3_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_LPSPI3_Register_Masks */


/* DMA_LPCG_LPSPI3 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_LPSPI3 base address */
#define DMA__LPCG_LPSPI3_BASE                    (0x5A430000u)
/** Peripheral DMA__LPCG_LPSPI3 base pointer */
#define DMA__LPCG_LPSPI3                         ((DMA_LPCG_LPSPI3_Type *)DMA__LPCG_LPSPI3_BASE)
/** Array initializer of DMA_LPCG_LPSPI3 peripheral base addresses */
#define DMA_LPCG_LPSPI3_BASE_ADDRS               { DMA__LPCG_LPSPI3_BASE }
/** Array initializer of DMA_LPCG_LPSPI3 peripheral base pointers */
#define DMA_LPCG_LPSPI3_BASE_PTRS                { DMA__LPCG_LPSPI3 }

/*!
 * @}
 */ /* end of group DMA_LPCG_LPSPI3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPUART0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPUART0_Peripheral_Access_Layer DMA_LPCG_LPUART0 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_LPUART0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPUART0_0;                    /**< na, offset: 0x0 */
} DMA_LPCG_LPUART0_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPUART0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPUART0_Register_Masks DMA_LPCG_LPUART0 Register Masks
 * @{
 */

/*! @name LPCG_LPUART0_0 - na */
/*! @{ */
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_gated_clk_HWEN_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_gated_clk_HWEN_MASK)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_SWEN_AND_lpuart0_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_SWEN_AND_lpuart0_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_SWEN_AND_lpuart0_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_SWEN_AND_lpuart0_lpuart_baud_gated_clk_SWEN_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_SWEN_AND_lpuart0_lpuart_baud_gated_clk_SWEN_MASK)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_2_2_MASK)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_STOP_AND_lpuart0_lpuart_baud_gated_clk_STOP_MASK (0x8U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_STOP_AND_lpuart0_lpuart_baud_gated_clk_STOP_SHIFT (3U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_STOP_AND_lpuart0_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_STOP_AND_lpuart0_lpuart_baud_gated_clk_STOP_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_lpuart_baud_clk_STOP_AND_lpuart0_lpuart_baud_gated_clk_STOP_MASK)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_4_15_MASK)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_SWEN_AND_lpuart0_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_SWEN_AND_lpuart0_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_SWEN_AND_lpuart0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_SWEN_AND_lpuart0_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_SWEN_AND_lpuart0_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_18_18_MASK)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_STOP_AND_lpuart0_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_STOP_AND_lpuart0_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_STOP_AND_lpuart0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_STOP_AND_lpuart0_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_lpuart0_ipg_clk_STOP_AND_lpuart0_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPUART0_LPCG_LPUART0_0_LPCG_LPUART0_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_LPUART0_Register_Masks */


/* DMA_LPCG_LPUART0 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_LPUART0 base address */
#define DMA__LPCG_LPUART0_BASE                   (0x5A460000u)
/** Peripheral DMA__LPCG_LPUART0 base pointer */
#define DMA__LPCG_LPUART0                        ((DMA_LPCG_LPUART0_Type *)DMA__LPCG_LPUART0_BASE)
/** Array initializer of DMA_LPCG_LPUART0 peripheral base addresses */
#define DMA_LPCG_LPUART0_BASE_ADDRS              { DMA__LPCG_LPUART0_BASE }
/** Array initializer of DMA_LPCG_LPUART0 peripheral base pointers */
#define DMA_LPCG_LPUART0_BASE_PTRS               { DMA__LPCG_LPUART0 }

/*!
 * @}
 */ /* end of group DMA_LPCG_LPUART0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPUART1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPUART1_Peripheral_Access_Layer DMA_LPCG_LPUART1 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_LPUART1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPUART1_0;                    /**< na, offset: 0x0 */
} DMA_LPCG_LPUART1_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPUART1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPUART1_Register_Masks DMA_LPCG_LPUART1 Register Masks
 * @{
 */

/*! @name LPCG_LPUART1_0 - na */
/*! @{ */
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_2_2_MASK)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK (0x8U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT (3U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_4_15_MASK)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_SWEN_AND_lpuart1_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_SWEN_AND_lpuart1_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_SWEN_AND_lpuart1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_SWEN_AND_lpuart1_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_SWEN_AND_lpuart1_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_18_18_MASK)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_STOP_AND_lpuart1_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_STOP_AND_lpuart1_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_STOP_AND_lpuart1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_STOP_AND_lpuart1_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_lpuart1_ipg_clk_STOP_AND_lpuart1_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPUART1_LPCG_LPUART1_0_LPCG_LPUART1_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_LPUART1_Register_Masks */


/* DMA_LPCG_LPUART1 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_LPUART1 base address */
#define DMA__LPCG_LPUART1_BASE                   (0x5A470000u)
/** Peripheral DMA__LPCG_LPUART1 base pointer */
#define DMA__LPCG_LPUART1                        ((DMA_LPCG_LPUART1_Type *)DMA__LPCG_LPUART1_BASE)
/** Array initializer of DMA_LPCG_LPUART1 peripheral base addresses */
#define DMA_LPCG_LPUART1_BASE_ADDRS              { DMA__LPCG_LPUART1_BASE }
/** Array initializer of DMA_LPCG_LPUART1 peripheral base pointers */
#define DMA_LPCG_LPUART1_BASE_PTRS               { DMA__LPCG_LPUART1 }

/*!
 * @}
 */ /* end of group DMA_LPCG_LPUART1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPUART2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPUART2_Peripheral_Access_Layer DMA_LPCG_LPUART2 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_LPUART2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPUART2_0;                    /**< na, offset: 0x0 */
} DMA_LPCG_LPUART2_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPUART2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPUART2_Register_Masks DMA_LPCG_LPUART2 Register Masks
 * @{
 */

/*! @name LPCG_LPUART2_0 - na */
/*! @{ */
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_gated_clk_HWEN_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_gated_clk_HWEN_MASK)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_SWEN_AND_lpuart2_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_SWEN_AND_lpuart2_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_SWEN_AND_lpuart2_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_SWEN_AND_lpuart2_lpuart_baud_gated_clk_SWEN_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_SWEN_AND_lpuart2_lpuart_baud_gated_clk_SWEN_MASK)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_2_2_MASK)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_STOP_AND_lpuart2_lpuart_baud_gated_clk_STOP_MASK (0x8U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_STOP_AND_lpuart2_lpuart_baud_gated_clk_STOP_SHIFT (3U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_STOP_AND_lpuart2_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_STOP_AND_lpuart2_lpuart_baud_gated_clk_STOP_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_lpuart_baud_clk_STOP_AND_lpuart2_lpuart_baud_gated_clk_STOP_MASK)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_4_15_MASK)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_SWEN_AND_lpuart2_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_SWEN_AND_lpuart2_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_SWEN_AND_lpuart2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_SWEN_AND_lpuart2_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_SWEN_AND_lpuart2_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_18_18_MASK)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_STOP_AND_lpuart2_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_STOP_AND_lpuart2_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_STOP_AND_lpuart2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_STOP_AND_lpuart2_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_lpuart2_ipg_clk_STOP_AND_lpuart2_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPUART2_LPCG_LPUART2_0_LPCG_LPUART2_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_LPUART2_Register_Masks */


/* DMA_LPCG_LPUART2 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_LPUART2 base address */
#define DMA__LPCG_LPUART2_BASE                   (0x5A480000u)
/** Peripheral DMA__LPCG_LPUART2 base pointer */
#define DMA__LPCG_LPUART2                        ((DMA_LPCG_LPUART2_Type *)DMA__LPCG_LPUART2_BASE)
/** Array initializer of DMA_LPCG_LPUART2 peripheral base addresses */
#define DMA_LPCG_LPUART2_BASE_ADDRS              { DMA__LPCG_LPUART2_BASE }
/** Array initializer of DMA_LPCG_LPUART2 peripheral base pointers */
#define DMA_LPCG_LPUART2_BASE_PTRS               { DMA__LPCG_LPUART2 }

/*!
 * @}
 */ /* end of group DMA_LPCG_LPUART2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPUART3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPUART3_Peripheral_Access_Layer DMA_LPCG_LPUART3 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_LPUART3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPUART3_0;                    /**< na, offset: 0x0 */
} DMA_LPCG_LPUART3_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPUART3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPUART3_Register_Masks DMA_LPCG_LPUART3 Register Masks
 * @{
 */

/*! @name LPCG_LPUART3_0 - na */
/*! @{ */
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_gated_clk_HWEN_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_gated_clk_HWEN_MASK)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_SWEN_AND_lpuart3_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_SWEN_AND_lpuart3_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_SWEN_AND_lpuart3_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_SWEN_AND_lpuart3_lpuart_baud_gated_clk_SWEN_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_SWEN_AND_lpuart3_lpuart_baud_gated_clk_SWEN_MASK)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_2_2_MASK)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_STOP_AND_lpuart3_lpuart_baud_gated_clk_STOP_MASK (0x8U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_STOP_AND_lpuart3_lpuart_baud_gated_clk_STOP_SHIFT (3U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_STOP_AND_lpuart3_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_STOP_AND_lpuart3_lpuart_baud_gated_clk_STOP_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_lpuart_baud_clk_STOP_AND_lpuart3_lpuart_baud_gated_clk_STOP_MASK)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_4_15_MASK)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_SWEN_AND_lpuart3_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_SWEN_AND_lpuart3_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_SWEN_AND_lpuart3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_SWEN_AND_lpuart3_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_SWEN_AND_lpuart3_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_18_18_MASK)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_STOP_AND_lpuart3_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_STOP_AND_lpuart3_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_STOP_AND_lpuart3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_STOP_AND_lpuart3_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_lpuart3_ipg_clk_STOP_AND_lpuart3_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPUART3_LPCG_LPUART3_0_LPCG_LPUART3_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_LPUART3_Register_Masks */


/* DMA_LPCG_LPUART3 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_LPUART3 base address */
#define DMA__LPCG_LPUART3_BASE                   (0x5A490000u)
/** Peripheral DMA__LPCG_LPUART3 base pointer */
#define DMA__LPCG_LPUART3                        ((DMA_LPCG_LPUART3_Type *)DMA__LPCG_LPUART3_BASE)
/** Array initializer of DMA_LPCG_LPUART3 peripheral base addresses */
#define DMA_LPCG_LPUART3_BASE_ADDRS              { DMA__LPCG_LPUART3_BASE }
/** Array initializer of DMA_LPCG_LPUART3 peripheral base pointers */
#define DMA_LPCG_LPUART3_BASE_PTRS               { DMA__LPCG_LPUART3 }

/*!
 * @}
 */ /* end of group DMA_LPCG_LPUART3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPUART4 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPUART4_Peripheral_Access_Layer DMA_LPCG_LPUART4 Peripheral Access Layer
 * @{
 */

/** DMA_LPCG_LPUART4 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPUART4_0;                    /**< na, offset: 0x0 */
} DMA_LPCG_LPUART4_Type;

/* ----------------------------------------------------------------------------
   -- DMA_LPCG_LPUART4 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_LPCG_LPUART4_Register_Masks DMA_LPCG_LPUART4 Register Masks
 * @{
 */

/*! @name LPCG_LPUART4_0 - na */
/*! @{ */
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_gated_clk_HWEN_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_gated_clk_HWEN_MASK)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_SWEN_AND_lpuart4_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_SWEN_AND_lpuart4_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_SWEN_AND_lpuart4_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_SWEN_AND_lpuart4_lpuart_baud_gated_clk_SWEN_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_SWEN_AND_lpuart4_lpuart_baud_gated_clk_SWEN_MASK)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_2_2_MASK (0x4U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_2_2_SHIFT (2U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_2_2_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_2_2_MASK)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_STOP_AND_lpuart4_lpuart_baud_gated_clk_STOP_MASK (0x8U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_STOP_AND_lpuart4_lpuart_baud_gated_clk_STOP_SHIFT (3U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_STOP_AND_lpuart4_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_STOP_AND_lpuart4_lpuart_baud_gated_clk_STOP_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_lpuart_baud_clk_STOP_AND_lpuart4_lpuart_baud_gated_clk_STOP_MASK)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_4_15_MASK (0xFFF0U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_4_15_SHIFT (4U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_4_15_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_4_15_MASK)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_s_HWEN_MASK (0x10000U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_s_HWEN_SHIFT (16U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_s_HWEN_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_s_HWEN_MASK)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_SWEN_AND_lpuart4_ipg_clk_s_SWEN_MASK (0x20000U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_SWEN_AND_lpuart4_ipg_clk_s_SWEN_SHIFT (17U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_SWEN_AND_lpuart4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_SWEN_AND_lpuart4_ipg_clk_s_SWEN_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_SWEN_AND_lpuart4_ipg_clk_s_SWEN_MASK)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_18_18_MASK (0x40000U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_18_18_SHIFT (18U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_18_18_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_18_18_MASK)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_STOP_AND_lpuart4_ipg_clk_s_STOP_MASK (0x80000U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_STOP_AND_lpuart4_ipg_clk_s_STOP_SHIFT (19U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_STOP_AND_lpuart4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_STOP_AND_lpuart4_ipg_clk_s_STOP_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_lpuart4_ipg_clk_STOP_AND_lpuart4_ipg_clk_s_STOP_MASK)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_20_31_MASK (0xFFF00000U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_20_31_SHIFT (20U)
#define DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_20_31_SHIFT)) & DMA_LPCG_LPUART4_LPCG_LPUART4_0_LPCG_LPUART4_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMA_LPCG_LPUART4_Register_Masks */


/* DMA_LPCG_LPUART4 - Peripheral instance base addresses */
/** Peripheral DMA__LPCG_LPUART4 base address */
#define DMA__LPCG_LPUART4_BASE                   (0x5A4A0000u)
/** Peripheral DMA__LPCG_LPUART4 base pointer */
#define DMA__LPCG_LPUART4                        ((DMA_LPCG_LPUART4_Type *)DMA__LPCG_LPUART4_BASE)
/** Array initializer of DMA_LPCG_LPUART4 peripheral base addresses */
#define DMA_LPCG_LPUART4_BASE_ADDRS              { DMA__LPCG_LPUART4_BASE }
/** Array initializer of DMA_LPCG_LPUART4 peripheral base pointers */
#define DMA_LPCG_LPUART4_BASE_PTRS               { DMA__LPCG_LPUART4 }

/*!
 * @}
 */ /* end of group DMA_LPCG_LPUART4_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DRC_LPCG_0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DRC_LPCG_0_Peripheral_Access_Layer DRC_LPCG_0 Peripheral Access Layer
 * @{
 */

/** DRC_LPCG_0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_0_0;                     /**< na, offset: 0x0 */
} DRC_LPCG_0_Type;

/* ----------------------------------------------------------------------------
   -- DRC_LPCG_0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DRC_LPCG_0_Register_Masks DRC_LPCG_0 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_0_0 - na */
/*! @{ */
#define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_MASK (0x1U)
#define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_SHIFT (0U)
#define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_SHIFT)) & DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_0_0_MASK)
#define DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_MASK (0x2U)
#define DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_SHIFT (1U)
#define DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_SHIFT)) & DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_SWEN_MASK)
#define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_MASK (0x4U)
#define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_SHIFT (2U)
#define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_SHIFT)) & DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_2_2_MASK)
#define DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_MASK (0x8U)
#define DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_SHIFT (3U)
#define DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_SHIFT)) & DRC_LPCG_0_LPCG_LPCG_0_0_ssi_port0_clk_STOP_MASK)
#define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_SHIFT (4U)
#define DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_SHIFT)) & DRC_LPCG_0_LPCG_LPCG_0_0_LPCG_lpcg_0_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DRC_LPCG_0_Register_Masks */


/* DRC_LPCG_0 - Peripheral instance base addresses */
/** Peripheral DRC_0__LPCG_SSI_PORT0_CLK base address */
#define DRC_0__LPCG_SSI_PORT0_CLK_BASE           (0x5C0C0000u)
/** Peripheral DRC_0__LPCG_SSI_PORT0_CLK base pointer */
#define DRC_0__LPCG_SSI_PORT0_CLK                ((DRC_LPCG_0_Type *)DRC_0__LPCG_SSI_PORT0_CLK_BASE)
/** Peripheral DRC_1__LPCG_SSI_PORT0_CLK base address */
#define DRC_1__LPCG_SSI_PORT0_CLK_BASE           (0x5C1C0000u)
/** Peripheral DRC_1__LPCG_SSI_PORT0_CLK base pointer */
#define DRC_1__LPCG_SSI_PORT0_CLK                ((DRC_LPCG_0_Type *)DRC_1__LPCG_SSI_PORT0_CLK_BASE)
/** Array initializer of DRC_LPCG_0 peripheral base addresses */
#define DRC_LPCG_0_BASE_ADDRS                    { DRC_0__LPCG_SSI_PORT0_CLK_BASE, DRC_1__LPCG_SSI_PORT0_CLK_BASE }
/** Array initializer of DRC_LPCG_0 peripheral base pointers */
#define DRC_LPCG_0_BASE_PTRS                     { DRC_0__LPCG_SSI_PORT0_CLK, DRC_1__LPCG_SSI_PORT0_CLK }

/*!
 * @}
 */ /* end of group DRC_LPCG_0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DRC_LPCG_1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DRC_LPCG_1_Peripheral_Access_Layer DRC_LPCG_1 Peripheral Access Layer
 * @{
 */

/** DRC_LPCG_1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_1_0;                     /**< na, offset: 0x0 */
} DRC_LPCG_1_Type;

/* ----------------------------------------------------------------------------
   -- DRC_LPCG_1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DRC_LPCG_1_Register_Masks DRC_LPCG_1 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_1_0 - na */
/*! @{ */
#define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_MASK (0x1U)
#define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_SHIFT (0U)
#define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_SHIFT)) & DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_0_0_MASK)
#define DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_MASK (0x2U)
#define DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_SHIFT (1U)
#define DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_SHIFT)) & DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_SWEN_MASK)
#define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_MASK (0x4U)
#define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_SHIFT (2U)
#define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_SHIFT)) & DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_2_2_MASK)
#define DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_MASK (0x8U)
#define DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_SHIFT (3U)
#define DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_SHIFT)) & DRC_LPCG_1_LPCG_LPCG_1_0_ddr_ctl_core_ddrc_core_clk_STOP_MASK)
#define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_SHIFT (4U)
#define DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_SHIFT)) & DRC_LPCG_1_LPCG_LPCG_1_0_LPCG_lpcg_1_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DRC_LPCG_1_Register_Masks */


/* DRC_LPCG_1 - Peripheral instance base addresses */
/** Peripheral DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK base address */
#define DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE (0x5C0D0000u)
/** Peripheral DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK base pointer */
#define DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK   ((DRC_LPCG_1_Type *)DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE)
/** Peripheral DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK base address */
#define DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE (0x5C1D0000u)
/** Peripheral DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK base pointer */
#define DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK   ((DRC_LPCG_1_Type *)DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE)
/** Array initializer of DRC_LPCG_1 peripheral base addresses */
#define DRC_LPCG_1_BASE_ADDRS                    { DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE, DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK_BASE }
/** Array initializer of DRC_LPCG_1 peripheral base pointers */
#define DRC_LPCG_1_BASE_PTRS                     { DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK, DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK }

/*!
 * @}
 */ /* end of group DRC_LPCG_1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DRC_LPCG_2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DRC_LPCG_2_Peripheral_Access_Layer DRC_LPCG_2 Peripheral Access Layer
 * @{
 */

/** DRC_LPCG_2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_2_0;                     /**< na, offset: 0x0 */
} DRC_LPCG_2_Type;

/* ----------------------------------------------------------------------------
   -- DRC_LPCG_2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DRC_LPCG_2_Register_Masks DRC_LPCG_2 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_2_0 - na */
/*! @{ */
#define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_0_0_MASK (0x1U)
#define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_0_0_SHIFT (0U)
#define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_0_0_SHIFT)) & DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_0_0_MASK)
#define DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_SWEN_MASK (0x2U)
#define DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_SWEN_SHIFT (1U)
#define DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_SWEN_SHIFT)) & DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_SWEN_MASK)
#define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_2_2_MASK (0x4U)
#define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_2_2_SHIFT (2U)
#define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_2_2_SHIFT)) & DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_2_2_MASK)
#define DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_STOP_MASK (0x8U)
#define DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_STOP_SHIFT (3U)
#define DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_STOP(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_STOP_SHIFT)) & DRC_LPCG_2_LPCG_LPCG_2_0_ddr_phy_pub_clk_clk_mux_D1_STOP_MASK)
#define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_4_31_SHIFT (4U)
#define DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_4_31_SHIFT)) & DRC_LPCG_2_LPCG_LPCG_2_0_LPCG_lpcg_2_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DRC_LPCG_2_Register_Masks */


/* DRC_LPCG_2 - Peripheral instance base addresses */
/** Peripheral DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1 base address */
#define DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1_BASE (0x5C0E0000u)
/** Peripheral DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1 base pointer */
#define DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1   ((DRC_LPCG_2_Type *)DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1_BASE)
/** Peripheral DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1 base address */
#define DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1_BASE (0x5C1E0000u)
/** Peripheral DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1 base pointer */
#define DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1   ((DRC_LPCG_2_Type *)DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1_BASE)
/** Array initializer of DRC_LPCG_2 peripheral base addresses */
#define DRC_LPCG_2_BASE_ADDRS                    { DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1_BASE, DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1_BASE }
/** Array initializer of DRC_LPCG_2 peripheral base pointers */
#define DRC_LPCG_2_BASE_PTRS                     { DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1, DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1 }

/*!
 * @}
 */ /* end of group DRC_LPCG_2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DRC_LPCG_3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DRC_LPCG_3_Peripheral_Access_Layer DRC_LPCG_3 Peripheral Access Layer
 * @{
 */

/** DRC_LPCG_3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPCG_3_0;                     /**< na, offset: 0x0 */
  __IO uint32_t LPCG_LPCG_3_4;                     /**< na, offset: 0x4 */
} DRC_LPCG_3_Type;

/* ----------------------------------------------------------------------------
   -- DRC_LPCG_3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DRC_LPCG_3_Register_Masks DRC_LPCG_3 Register Masks
 * @{
 */

/*! @name LPCG_LPCG_3_0 - na */
/*! @{ */
#define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_MASK (0x1U)
#define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_SHIFT (0U)
#define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_0_0_MASK)
#define DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_MASK (0x2U)
#define DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT (1U)
#define DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_SWEN_MASK)
#define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_MASK (0x4U)
#define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_SHIFT (2U)
#define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_2_2_MASK)
#define DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_MASK (0x8U)
#define DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT (3U)
#define DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_0_ddr_ctl_pclk_lpddr_init_clk_mux_D0_STOP_MASK)
#define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_SHIFT (4U)
#define DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_0_LPCG_lpcg_3_0_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_LPCG_3_4 - na */
/*! @{ */
#define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_MASK (0x1U)
#define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_SHIFT (0U)
#define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_0_0_MASK)
#define DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_MASK (0x2U)
#define DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT (1U)
#define DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_SWEN_MASK)
#define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_MASK (0x4U)
#define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_SHIFT (2U)
#define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_2_2_MASK)
#define DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_MASK (0x8U)
#define DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT (3U)
#define DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_4_ddr_phy_pclk_lpddr_init_clk_mux_D0_STOP_MASK)
#define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_MASK (0xFFFFFFF0U)
#define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_SHIFT (4U)
#define DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_SHIFT)) & DRC_LPCG_3_LPCG_LPCG_3_4_LPCG_lpcg_3_4_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DRC_LPCG_3_Register_Masks */


/* DRC_LPCG_3 - Peripheral instance base addresses */
/** Peripheral DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 base address */
#define DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE (0x5C0F0000u)
/** Peripheral DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 base pointer */
#define DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 ((DRC_LPCG_3_Type *)DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE)
/** Peripheral DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 base address */
#define DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE (0x5C1F0000u)
/** Peripheral DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 base pointer */
#define DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 ((DRC_LPCG_3_Type *)DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE)
/** Array initializer of DRC_LPCG_3 peripheral base addresses */
#define DRC_LPCG_3_BASE_ADDRS                    { DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE, DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0_BASE }
/** Array initializer of DRC_LPCG_3 peripheral base pointers */
#define DRC_LPCG_3_BASE_PTRS                     { DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0, DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0 }

/*!
 * @}
 */ /* end of group DRC_LPCG_3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DTCP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DTCP_Peripheral_Access_Layer DTCP Peripheral Access Layer
 * @{
 */

/** DTCP - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[1024];
  __IO uint16_t DTCP_INT_MASK;                     /**< Initial mask, offset: 0x400 */
  __IO uint16_t DTCP_INT_FLAG;                     /**< Initial Flag, offset: 0x402 */
  __IO uint16_t DTCP_STATE;                        /**< Initial State, offset: 0x404 */
       uint8_t RESERVED_1[2];
  __IO uint16_t DTCP_REQ_MASK;                     /**< Request Mask, offset: 0x408 */
} DTCP_Type;

/* ----------------------------------------------------------------------------
   -- DTCP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DTCP_Register_Masks DTCP Register Masks
 * @{
 */

/*! @name DTCP_INT_MASK - Initial mask */
/*! @{ */
#define DTCP_DTCP_INT_MASK_CHN0_INT_MASK_MASK    (0x1U)
#define DTCP_DTCP_INT_MASK_CHN0_INT_MASK_SHIFT   (0U)
/*! CHN0_INT_MASK - Channel 0 Interrupt Mask
 *  0b0..DTCP generates interrupt when channel 0 #8 or #9 service finish.
 *  0b1..DTCP does not generate service interrupt for channel 0.
 */
#define DTCP_DTCP_INT_MASK_CHN0_INT_MASK(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN0_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN0_INT_MASK_MASK)
#define DTCP_DTCP_INT_MASK_CHN1_INT_MASK_MASK    (0x2U)
#define DTCP_DTCP_INT_MASK_CHN1_INT_MASK_SHIFT   (1U)
/*! CHN1_INT_MASK - Channel 1 Interrupt Mask
 *  0b0..DTCP generates interrupt when channel 1 #8 or #9 service finish.
 *  0b1..DTCP does not generate service interrupt for channel 1.
 */
#define DTCP_DTCP_INT_MASK_CHN1_INT_MASK(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN1_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN1_INT_MASK_MASK)
#define DTCP_DTCP_INT_MASK_CHN2_INT_MASK_MASK    (0x4U)
#define DTCP_DTCP_INT_MASK_CHN2_INT_MASK_SHIFT   (2U)
/*! CHN2_INT_MASK - Channel 2 Interrupt Mask
 *  0b0..DTCP generates interrupt when channel 2 #8 or #9 service finish.
 *  0b1..DTCP does not generate service interrupt for channel 2.
 */
#define DTCP_DTCP_INT_MASK_CHN2_INT_MASK(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN2_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN2_INT_MASK_MASK)
#define DTCP_DTCP_INT_MASK_CHN3_INT_MASK_MASK    (0x8U)
#define DTCP_DTCP_INT_MASK_CHN3_INT_MASK_SHIFT   (3U)
/*! CHN3_INT_MASK - Channel 3 Interrupt Mask
 *  0b0..DTCP generates interrupt when channel 3 #8 or #9 service finish.
 *  0b1..DTCP does not generate service interrupt for channel 3.
 */
#define DTCP_DTCP_INT_MASK_CHN3_INT_MASK(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN3_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN3_INT_MASK_MASK)
#define DTCP_DTCP_INT_MASK_CHN4_INT_MASK_MASK    (0x10U)
#define DTCP_DTCP_INT_MASK_CHN4_INT_MASK_SHIFT   (4U)
/*! CHN4_INT_MASK - Channel 4 Interrupt Mask
 *  0b0..DTCP generates interrupt when channel 4 #8 or #9 service finish.
 *  0b1..DTCP does not generate service interrupt for channel 4.
 */
#define DTCP_DTCP_INT_MASK_CHN4_INT_MASK(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN4_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN4_INT_MASK_MASK)
#define DTCP_DTCP_INT_MASK_CHN5_INT_MASK_MASK    (0x20U)
#define DTCP_DTCP_INT_MASK_CHN5_INT_MASK_SHIFT   (5U)
/*! CHN5_INT_MASK - Channel 5 Interrupt Mask
 *  0b0..DTCP generates interrupt when channel 5 #8 or #9 service finish.
 *  0b1..DTCP does not generate service interrupt for channel 5.
 */
#define DTCP_DTCP_INT_MASK_CHN5_INT_MASK(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN5_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN5_INT_MASK_MASK)
#define DTCP_DTCP_INT_MASK_CHN6_INT_MASK_MASK    (0x40U)
#define DTCP_DTCP_INT_MASK_CHN6_INT_MASK_SHIFT   (6U)
/*! CHN6_INT_MASK - Channel 6 Interrupt Mask
 *  0b0..DTCP generates interrupt when channel 6 #8 or #9 service finish.
 *  0b1..DTCP does not generate service interrupt for channel 6.
 */
#define DTCP_DTCP_INT_MASK_CHN6_INT_MASK(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN6_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN6_INT_MASK_MASK)
#define DTCP_DTCP_INT_MASK_CHN7_INT_MASK_MASK    (0x80U)
#define DTCP_DTCP_INT_MASK_CHN7_INT_MASK_SHIFT   (7U)
/*! CHN7_INT_MASK - Channel 6 Interrupt Mask
 *  0b0..DTCP generates interrupt when channel 7 #8 or #9 service finish.
 *  0b1..DTCP does not generate service interrupt for channel 7.
 */
#define DTCP_DTCP_INT_MASK_CHN7_INT_MASK(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN7_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN7_INT_MASK_MASK)
#define DTCP_DTCP_INT_MASK_CHN8_INT_MASK_MASK    (0x100U)
#define DTCP_DTCP_INT_MASK_CHN8_INT_MASK_SHIFT   (8U)
/*! CHN8_INT_MASK - Channel 8 Interrupt Mask
 *  0b0..DTCP generates interrupt when AKE service finish.
 *  0b1..DTCP does not generate service interrupt for SKE service.
 */
#define DTCP_DTCP_INT_MASK_CHN8_INT_MASK(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_MASK_CHN8_INT_MASK_SHIFT)) & DTCP_DTCP_INT_MASK_CHN8_INT_MASK_MASK)
/*! @} */

/*! @name DTCP_INT_FLAG - Initial Flag */
/*! @{ */
#define DTCP_DTCP_INT_FLAG_CHN0_INT_FLAG_MASK    (0x1U)
#define DTCP_DTCP_INT_FLAG_CHN0_INT_FLAG_SHIFT   (0U)
/*! CHN0_INT_FLAG - Channel 0 Interrupt Flag
 *  0b1..DTCP channel 0 #8 or #9 service finish.
 */
#define DTCP_DTCP_INT_FLAG_CHN0_INT_FLAG(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN0_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN0_INT_FLAG_MASK)
#define DTCP_DTCP_INT_FLAG_CHN1_INT_FLAG_MASK    (0x2U)
#define DTCP_DTCP_INT_FLAG_CHN1_INT_FLAG_SHIFT   (1U)
/*! CHN1_INT_FLAG - Channel 1 Interrupt Flag
 *  0b1..DTCP channel 1 #8 or #9 service finish.
 */
#define DTCP_DTCP_INT_FLAG_CHN1_INT_FLAG(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN1_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN1_INT_FLAG_MASK)
#define DTCP_DTCP_INT_FLAG_CHN2_INT_FLAG_MASK    (0x4U)
#define DTCP_DTCP_INT_FLAG_CHN2_INT_FLAG_SHIFT   (2U)
/*! CHN2_INT_FLAG - Channel 2 Interrupt FLAG
 *  0b1..DTCP channel 2 #8 or #9 service finish.
 */
#define DTCP_DTCP_INT_FLAG_CHN2_INT_FLAG(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN2_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN2_INT_FLAG_MASK)
#define DTCP_DTCP_INT_FLAG_CHN3_INT_FLAG_MASK    (0x8U)
#define DTCP_DTCP_INT_FLAG_CHN3_INT_FLAG_SHIFT   (3U)
/*! CHN3_INT_FLAG - Channel 3 Interrupt Flag
 *  0b1..DTCP channel 3 #8 or #9 service finish.
 */
#define DTCP_DTCP_INT_FLAG_CHN3_INT_FLAG(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN3_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN3_INT_FLAG_MASK)
#define DTCP_DTCP_INT_FLAG_CHN4_INT_FLAG_MASK    (0x10U)
#define DTCP_DTCP_INT_FLAG_CHN4_INT_FLAG_SHIFT   (4U)
/*! CHN4_INT_FLAG - Channel 4 Interrupt Flag
 *  0b1..DTCP channel 4 #8 or #9 service finish.
 */
#define DTCP_DTCP_INT_FLAG_CHN4_INT_FLAG(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN4_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN4_INT_FLAG_MASK)
#define DTCP_DTCP_INT_FLAG_CHN5_INT_FLAG_MASK    (0x20U)
#define DTCP_DTCP_INT_FLAG_CHN5_INT_FLAG_SHIFT   (5U)
/*! CHN5_INT_FLAG - Channel 5 Interrupt Flag
 *  0b1..DTCP channel 5 #8 or #9 service finish.
 */
#define DTCP_DTCP_INT_FLAG_CHN5_INT_FLAG(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN5_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN5_INT_FLAG_MASK)
#define DTCP_DTCP_INT_FLAG_CHN6_INT_FLAG_MASK    (0x40U)
#define DTCP_DTCP_INT_FLAG_CHN6_INT_FLAG_SHIFT   (6U)
/*! CHN6_INT_FLAG - Channel 6 Interrupt Flag
 *  0b1..DTCP channel 6 #8 or #9 service finish.
 */
#define DTCP_DTCP_INT_FLAG_CHN6_INT_FLAG(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN6_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN6_INT_FLAG_MASK)
#define DTCP_DTCP_INT_FLAG_CHN7_INT_FLAG_MASK    (0x80U)
#define DTCP_DTCP_INT_FLAG_CHN7_INT_FLAG_SHIFT   (7U)
/*! CHN7_INT_FLAG - Channel 6 Interrupt Flag
 *  0b1..DTCP channel 7 #8 or #9 service finish.
 */
#define DTCP_DTCP_INT_FLAG_CHN7_INT_FLAG(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN7_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN7_INT_FLAG_MASK)
#define DTCP_DTCP_INT_FLAG_CHN8_INT_FLAG_MASK    (0x100U)
#define DTCP_DTCP_INT_FLAG_CHN8_INT_FLAG_SHIFT   (8U)
/*! CHN8_INT_FLAG - Channel 8 Interrupt Flag
 *  0b1..AKE service finish.
 */
#define DTCP_DTCP_INT_FLAG_CHN8_INT_FLAG(x)      (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_INT_FLAG_CHN8_INT_FLAG_SHIFT)) & DTCP_DTCP_INT_FLAG_CHN8_INT_FLAG_MASK)
/*! @} */

/*! @name DTCP_STATE - Initial State */
/*! @{ */
#define DTCP_DTCP_STATE_BUFF_MT_MASK             (0xFFU)
#define DTCP_DTCP_STATE_BUFF_MT_SHIFT            (0U)
#define DTCP_DTCP_STATE_BUFF_MT(x)               (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_STATE_BUFF_MT_SHIFT)) & DTCP_DTCP_STATE_BUFF_MT_MASK)
#define DTCP_DTCP_STATE_CUR_CHN_MASK             (0x700U)
#define DTCP_DTCP_STATE_CUR_CHN_SHIFT            (8U)
#define DTCP_DTCP_STATE_CUR_CHN(x)               (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_STATE_CUR_CHN_SHIFT)) & DTCP_DTCP_STATE_CUR_CHN_MASK)
/*! @} */

/*! @name DTCP_REQ_MASK - Request Mask */
/*! @{ */
#define DTCP_DTCP_REQ_MASK_CHN0_DMA_REQ_MASK_MASK (0x1U)
#define DTCP_DTCP_REQ_MASK_CHN0_DMA_REQ_MASK_SHIFT (0U)
/*! CHN0_DMA_REQ_MASK - Channel 0 DMA Request Mask
 *  0b0..DTCP generates DMA request when channel 0 #8 or #9 service finish.
 *  0b1..DTCP does not generate DMA request interrupt for channel 0.
 */
#define DTCP_DTCP_REQ_MASK_CHN0_DMA_REQ_MASK(x)  (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN0_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN0_DMA_REQ_MASK_MASK)
#define DTCP_DTCP_REQ_MASK_CHN1_DMA_REQ_MASK_MASK (0x2U)
#define DTCP_DTCP_REQ_MASK_CHN1_DMA_REQ_MASK_SHIFT (1U)
/*! CHN1_DMA_REQ_MASK - Channel 1 DMA Request Mask
 *  0b0..DTCP generates DMA request when channel 1 #8 or #9 service finish.
 *  0b1..DTCP does not generate DMA request for channel 1.
 */
#define DTCP_DTCP_REQ_MASK_CHN1_DMA_REQ_MASK(x)  (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN1_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN1_DMA_REQ_MASK_MASK)
#define DTCP_DTCP_REQ_MASK_CHN2_DMA_REQ_MASK_MASK (0x4U)
#define DTCP_DTCP_REQ_MASK_CHN2_DMA_REQ_MASK_SHIFT (2U)
/*! CHN2_DMA_REQ_MASK - Channel 2 DMA Request Mask
 *  0b0..DTCP generates DMA request when channel 2 #8 or #9 service finish.
 *  0b1..DTCP does not generate DMA request for channel 2.
 */
#define DTCP_DTCP_REQ_MASK_CHN2_DMA_REQ_MASK(x)  (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN2_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN2_DMA_REQ_MASK_MASK)
#define DTCP_DTCP_REQ_MASK_CHN3_DMA_REQ_MASK_MASK (0x8U)
#define DTCP_DTCP_REQ_MASK_CHN3_DMA_REQ_MASK_SHIFT (3U)
/*! CHN3_DMA_REQ_MASK - Channel 3 DMA Request Mask
 *  0b0..DTCP generates DMA request when channel 3 #8 or #9 service finish.
 *  0b1..DTCP does not generate DMA request for channel 3.
 */
#define DTCP_DTCP_REQ_MASK_CHN3_DMA_REQ_MASK(x)  (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN3_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN3_DMA_REQ_MASK_MASK)
#define DTCP_DTCP_REQ_MASK_CHN4_DMA_REQ_MASK_MASK (0x10U)
#define DTCP_DTCP_REQ_MASK_CHN4_DMA_REQ_MASK_SHIFT (4U)
/*! CHN4_DMA_REQ_MASK - Channel 4 DMA Request Mask
 *  0b0..DTCP generates DMA request when channel 4 #8 or #9 service finish.
 *  0b1..DTCP does not generate DMA request for channel 4.
 */
#define DTCP_DTCP_REQ_MASK_CHN4_DMA_REQ_MASK(x)  (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN4_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN4_DMA_REQ_MASK_MASK)
#define DTCP_DTCP_REQ_MASK_CHN5_DMA_REQ_MASK_MASK (0x20U)
#define DTCP_DTCP_REQ_MASK_CHN5_DMA_REQ_MASK_SHIFT (5U)
/*! CHN5_DMA_REQ_MASK - Channel 5 DMA Request Mask
 *  0b0..DTCP generates DMA request when channel 5 #8 or #9 service finish.
 *  0b1..DTCP does not generate DMA request for channel 5.
 */
#define DTCP_DTCP_REQ_MASK_CHN5_DMA_REQ_MASK(x)  (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN5_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN5_DMA_REQ_MASK_MASK)
#define DTCP_DTCP_REQ_MASK_CHN6_DMA_REQ_MASK_MASK (0x40U)
#define DTCP_DTCP_REQ_MASK_CHN6_DMA_REQ_MASK_SHIFT (6U)
/*! CHN6_DMA_REQ_MASK - Channel 6 DMA Request Mask
 *  0b0..DTCP generates DMA request when channel 6 #8 or #9 service finish.
 *  0b1..DTCP does not generate DMA request for channel 6.
 */
#define DTCP_DTCP_REQ_MASK_CHN6_DMA_REQ_MASK(x)  (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN6_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN6_DMA_REQ_MASK_MASK)
#define DTCP_DTCP_REQ_MASK_CHN7_DMA_REQ_MASK_MASK (0x80U)
#define DTCP_DTCP_REQ_MASK_CHN7_DMA_REQ_MASK_SHIFT (7U)
/*! CHN7_DMA_REQ_MASK - Channel 6 DMA Request Mask
 *  0b0..DTCP generates DMA request when channel 7 #8 or #9 service finish.
 *  0b1..DTCP does not generate DMA request for channel 7.
 */
#define DTCP_DTCP_REQ_MASK_CHN7_DMA_REQ_MASK(x)  (((uint16_t)(((uint16_t)(x)) << DTCP_DTCP_REQ_MASK_CHN7_DMA_REQ_MASK_SHIFT)) & DTCP_DTCP_REQ_MASK_CHN7_DMA_REQ_MASK_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DTCP_Register_Masks */


/* DTCP - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__DTCP base address */
#define CONNECTIVITY__DTCP_BASE                  (0x5B800000u)
/** Peripheral CONNECTIVITY__DTCP base pointer */
#define CONNECTIVITY__DTCP                       ((DTCP_Type *)CONNECTIVITY__DTCP_BASE)
/** Array initializer of DTCP peripheral base addresses */
#define DTCP_BASE_ADDRS                          { CONNECTIVITY__DTCP_BASE }
/** Array initializer of DTCP peripheral base pointers */
#define DTCP_BASE_PTRS                           { CONNECTIVITY__DTCP }
/** Interrupt vectors for the DTCP peripheral type */
#define DTCP_IRQS                                { CONNECTIVITY_DTCP_INT_IRQn }

/*!
 * @}
 */ /* end of group DTCP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- EMVSIM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
 * @{
 */

/** EMVSIM - Register Layout Typedef */
typedef struct {
  __I  uint32_t VER_ID;                            /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __IO uint32_t CLKCFG;                            /**< Clock Configuration Register, offset: 0x8 */
  __IO uint32_t DIVISOR;                           /**< Baud Rate Divisor Register, offset: 0xC */
  __IO uint32_t CTRL;                              /**< Control Register, offset: 0x10 */
  __IO uint32_t INT_MASK;                          /**< Interrupt Mask Register, offset: 0x14 */
  __IO uint32_t RX_THD;                            /**< Receiver Threshold Register, offset: 0x18 */
  __IO uint32_t TX_THD;                            /**< Transmitter Threshold Register, offset: 0x1C */
  __IO uint32_t RX_STATUS;                         /**< Receive Status Register, offset: 0x20 */
  __IO uint32_t TX_STATUS;                         /**< Transmitter Status Register, offset: 0x24 */
  __IO uint32_t PCSR;                              /**< Port Control and Status Register, offset: 0x28 */
  __I  uint32_t RX_BUF;                            /**< Receive Data Read Buffer, offset: 0x2C */
  __O  uint32_t TX_BUF;                            /**< Transmit Data Buffer, offset: 0x30 */
  __IO uint32_t TX_GETU;                           /**< Transmitter Guard ETU Value Register, offset: 0x34 */
  __IO uint32_t CWT_VAL;                           /**< Character Wait Time Value Register, offset: 0x38 */
  __IO uint32_t BWT_VAL;                           /**< Block Wait Time Value Register, offset: 0x3C */
  __IO uint32_t BGT_VAL;                           /**< Block Guard Time Value Register, offset: 0x40 */
  __IO uint32_t GPCNT0_VAL;                        /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
  __IO uint32_t GPCNT1_VAL;                        /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
} EMVSIM_Type;

/* ----------------------------------------------------------------------------
   -- EMVSIM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
 * @{
 */

/*! @name VER_ID - Version ID Register */
/*! @{ */
#define EMVSIM_VER_ID_VER_MASK                   (0xFFFFFFFFU)
#define EMVSIM_VER_ID_VER_SHIFT                  (0U)
#define EMVSIM_VER_ID_VER(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */
#define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK          (0xFFU)
#define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT         (0U)
#define EMVSIM_PARAM_RX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
#define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK          (0xFF00U)
#define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT         (8U)
#define EMVSIM_PARAM_TX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
/*! @} */

/*! @name CLKCFG - Clock Configuration Register */
/*! @{ */
#define EMVSIM_CLKCFG_CLK_PRSC_MASK              (0xFFU)
#define EMVSIM_CLKCFG_CLK_PRSC_SHIFT             (0U)
/*! CLK_PRSC - Clock Prescaler Value
 *  0b00000010..Divide by 2
 */
#define EMVSIM_CLKCFG_CLK_PRSC(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK        (0x300U)
#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT       (8U)
/*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select
 *  0b00..Disabled / Reset (default)
 *  0b01..Card Clock
 *  0b10..Receive Clock
 *  0b11..ETU Clock (transmit clock)
 */
#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK        (0xC00U)
#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT       (10U)
/*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select
 *  0b00..Disabled / Reset (default)
 *  0b01..Card Clock
 *  0b10..Receive Clock
 *  0b11..ETU Clock (transmit clock)
 */
#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
/*! @} */

/*! @name DIVISOR - Baud Rate Divisor Register */
/*! @{ */
#define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK        (0x1FFU)
#define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT       (0U)
/*! DIVISOR_VALUE - Divisor (F/D) Value
 *  0b000000000-0b000000100..Invalid. As per ISO 7816 specification, minimum value of F/D is 5
 *  0b101110100..Divisor value for F = 372 and D = 1 (default)
 */
#define EMVSIM_DIVISOR_DIVISOR_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
/*! @} */

/*! @name CTRL - Control Register */
/*! @{ */
#define EMVSIM_CTRL_IC_MASK                      (0x1U)
#define EMVSIM_CTRL_IC_SHIFT                     (0U)
/*! IC - Inverse Convention
 *  0b0..Direction convention transfers enabled (default)
 *  0b1..Inverse convention transfers enabled
 */
#define EMVSIM_CTRL_IC(x)                        (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
#define EMVSIM_CTRL_ICM_MASK                     (0x2U)
#define EMVSIM_CTRL_ICM_SHIFT                    (1U)
/*! ICM - Initial Character Mode
 *  0b0..Initial Character Mode disabled
 *  0b1..Initial Character Mode enabled (default)
 */
#define EMVSIM_CTRL_ICM(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
#define EMVSIM_CTRL_ANACK_MASK                   (0x4U)
#define EMVSIM_CTRL_ANACK_SHIFT                  (2U)
/*! ANACK - Auto NACK Enable
 *  0b0..NACK generation on errors disabled
 *  0b1..NACK generation on errors enabled (default)
 */
#define EMVSIM_CTRL_ANACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
#define EMVSIM_CTRL_ONACK_MASK                   (0x8U)
#define EMVSIM_CTRL_ONACK_SHIFT                  (3U)
/*! ONACK - Overrun NACK Enable
 *  0b0..NACK generation on overrun is disabled (default)
 *  0b1..NACK generation on overrun is enabled
 */
#define EMVSIM_CTRL_ONACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
#define EMVSIM_CTRL_FLSH_RX_MASK                 (0x100U)
#define EMVSIM_CTRL_FLSH_RX_SHIFT                (8U)
/*! FLSH_RX - Flush Receiver Bit
 *  0b0..EMV SIM Receiver normal operation (default)
 *  0b1..EMV SIM Receiver held in Reset
 */
#define EMVSIM_CTRL_FLSH_RX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
#define EMVSIM_CTRL_FLSH_TX_MASK                 (0x200U)
#define EMVSIM_CTRL_FLSH_TX_SHIFT                (9U)
/*! FLSH_TX - Flush Transmitter Bit
 *  0b0..EMV SIM Transmitter normal operation (default)
 *  0b1..EMV SIM Transmitter held in Reset
 */
#define EMVSIM_CTRL_FLSH_TX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
#define EMVSIM_CTRL_SW_RST_MASK                  (0x400U)
#define EMVSIM_CTRL_SW_RST_SHIFT                 (10U)
/*! SW_RST - Software Reset Bit
 *  0b0..EMV SIM Normal operation (default)
 *  0b1..EMV SIM held in Reset
 */
#define EMVSIM_CTRL_SW_RST(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
#define EMVSIM_CTRL_KILL_CLOCKS_MASK             (0x800U)
#define EMVSIM_CTRL_KILL_CLOCKS_SHIFT            (11U)
/*! KILL_CLOCKS - Kill all internal clocks
 *  0b0..EMV SIM input clock enabled (default)
 *  0b1..EMV SIM input clock is disabled
 */
#define EMVSIM_CTRL_KILL_CLOCKS(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
#define EMVSIM_CTRL_DOZE_EN_MASK                 (0x1000U)
#define EMVSIM_CTRL_DOZE_EN_SHIFT                (12U)
/*! DOZE_EN - Doze Enable
 *  0b0..DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default)
 *  0b1..DOZE instruction has no effect on EMV SIM module
 */
#define EMVSIM_CTRL_DOZE_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
#define EMVSIM_CTRL_STOP_EN_MASK                 (0x2000U)
#define EMVSIM_CTRL_STOP_EN_SHIFT                (13U)
/*! STOP_EN - STOP Enable
 *  0b0..STOP instruction shuts down all EMV SIM clocks (default)
 *  0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card)
 */
#define EMVSIM_CTRL_STOP_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
#define EMVSIM_CTRL_RCV_EN_MASK                  (0x10000U)
#define EMVSIM_CTRL_RCV_EN_SHIFT                 (16U)
/*! RCV_EN - Receiver Enable
 *  0b0..EMV SIM Receiver disabled (default)
 *  0b1..EMV SIM Receiver enabled
 */
#define EMVSIM_CTRL_RCV_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
#define EMVSIM_CTRL_XMT_EN_MASK                  (0x20000U)
#define EMVSIM_CTRL_XMT_EN_SHIFT                 (17U)
/*! XMT_EN - Transmitter Enable
 *  0b0..EMV SIM Transmitter disabled (default)
 *  0b1..EMV SIM Transmitter enabled
 */
#define EMVSIM_CTRL_XMT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
#define EMVSIM_CTRL_RCVR_11_MASK                 (0x40000U)
#define EMVSIM_CTRL_RCVR_11_SHIFT                (18U)
/*! RCVR_11 - Receiver 11 ETU Mode Enable
 *  0b0..Receiver configured for 12 ETU operation mode (default)
 *  0b1..Receiver configured for 11 ETU operation mode
 */
#define EMVSIM_CTRL_RCVR_11(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
#define EMVSIM_CTRL_RX_DMA_EN_MASK               (0x80000U)
#define EMVSIM_CTRL_RX_DMA_EN_SHIFT              (19U)
/*! RX_DMA_EN - Receive DMA Enable
 *  0b0..No DMA Read Request asserted for Receiver (default)
 *  0b1..DMA Read Request asserted for Receiver
 */
#define EMVSIM_CTRL_RX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
#define EMVSIM_CTRL_TX_DMA_EN_MASK               (0x100000U)
#define EMVSIM_CTRL_TX_DMA_EN_SHIFT              (20U)
/*! TX_DMA_EN - Transmit DMA Enable
 *  0b0..No DMA Write Request asserted for Transmitter (default)
 *  0b1..DMA Write Request asserted for Transmitter
 */
#define EMVSIM_CTRL_TX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
#define EMVSIM_CTRL_INV_CRC_VAL_MASK             (0x1000000U)
#define EMVSIM_CTRL_INV_CRC_VAL_SHIFT            (24U)
/*! INV_CRC_VAL - Invert bits in the CRC Output Value
 *  0b0..Bits in CRC Output value will not be inverted.
 *  0b1..Bits in CRC Output value will be inverted. (default)
 */
#define EMVSIM_CTRL_INV_CRC_VAL(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
#define EMVSIM_CTRL_CRC_OUT_FLIP_MASK            (0x2000000U)
#define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT           (25U)
/*! CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip
 *  0b0..Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default)
 *  0b1..Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7}
 */
#define EMVSIM_CTRL_CRC_OUT_FLIP(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
#define EMVSIM_CTRL_CRC_IN_FLIP_MASK             (0x4000000U)
#define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT            (26U)
/*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control
 *  0b0..Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default)
 *  0b1..Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation
 */
#define EMVSIM_CTRL_CRC_IN_FLIP(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
#define EMVSIM_CTRL_CWT_EN_MASK                  (0x8000000U)
#define EMVSIM_CTRL_CWT_EN_SHIFT                 (27U)
/*! CWT_EN - Character Wait Time Counter Enable
 *  0b0..Character Wait time Counter is disabled (default)
 *  0b1..Character Wait time counter is enabled
 */
#define EMVSIM_CTRL_CWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
#define EMVSIM_CTRL_LRC_EN_MASK                  (0x10000000U)
#define EMVSIM_CTRL_LRC_EN_SHIFT                 (28U)
/*! LRC_EN - LRC Enable
 *  0b0..8-bit Linear Redundancy Checking disabled (default)
 *  0b1..8-bit Linear Redundancy Checking enabled
 */
#define EMVSIM_CTRL_LRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
#define EMVSIM_CTRL_CRC_EN_MASK                  (0x20000000U)
#define EMVSIM_CTRL_CRC_EN_SHIFT                 (29U)
/*! CRC_EN - CRC Enable
 *  0b0..16-bit Cyclic Redundancy Checking disabled (default)
 *  0b1..16-bit Cyclic Redundancy Checking enabled
 */
#define EMVSIM_CTRL_CRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
#define EMVSIM_CTRL_XMT_CRC_LRC_MASK             (0x40000000U)
#define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT            (30U)
/*! XMT_CRC_LRC - Transmit CRC or LRC Enable
 *  0b0..No CRC or LRC value is transmitted (default)
 *  0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled)
 */
#define EMVSIM_CTRL_XMT_CRC_LRC(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
#define EMVSIM_CTRL_BWT_EN_MASK                  (0x80000000U)
#define EMVSIM_CTRL_BWT_EN_SHIFT                 (31U)
/*! BWT_EN - Block Wait Time Counter Enable
 *  0b0..Disable BWT, BGT Counters (default)
 *  0b1..Enable BWT, BGT Counters
 */
#define EMVSIM_CTRL_BWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
/*! @} */

/*! @name INT_MASK - Interrupt Mask Register */
/*! @{ */
#define EMVSIM_INT_MASK_RDT_IM_MASK              (0x1U)
#define EMVSIM_INT_MASK_RDT_IM_SHIFT             (0U)
/*! RDT_IM - Receive Data Threshold Interrupt Mask
 *  0b0..RDTF interrupt enabled
 *  0b1..RDTF interrupt masked (default)
 */
#define EMVSIM_INT_MASK_RDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
#define EMVSIM_INT_MASK_TC_IM_MASK               (0x2U)
#define EMVSIM_INT_MASK_TC_IM_SHIFT              (1U)
/*! TC_IM - Transmit Complete Interrupt Mask
 *  0b0..TCF interrupt enabled
 *  0b1..TCF interrupt masked (default)
 */
#define EMVSIM_INT_MASK_TC_IM(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
#define EMVSIM_INT_MASK_RFO_IM_MASK              (0x4U)
#define EMVSIM_INT_MASK_RFO_IM_SHIFT             (2U)
/*! RFO_IM - Receive FIFO Overflow Interrupt Mask
 *  0b0..RFO interrupt enabled
 *  0b1..RFO interrupt masked (default)
 */
#define EMVSIM_INT_MASK_RFO_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
#define EMVSIM_INT_MASK_ETC_IM_MASK              (0x8U)
#define EMVSIM_INT_MASK_ETC_IM_SHIFT             (3U)
/*! ETC_IM - Early Transmit Complete Interrupt Mask
 *  0b0..ETC interrupt enabled
 *  0b1..ETC interrupt masked (default)
 */
#define EMVSIM_INT_MASK_ETC_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
#define EMVSIM_INT_MASK_TFE_IM_MASK              (0x10U)
#define EMVSIM_INT_MASK_TFE_IM_SHIFT             (4U)
/*! TFE_IM - Transmit FIFO Empty Interrupt Mask
 *  0b0..TFE interrupt enabled
 *  0b1..TFE interrupt masked (default)
 */
#define EMVSIM_INT_MASK_TFE_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
#define EMVSIM_INT_MASK_TNACK_IM_MASK            (0x20U)
#define EMVSIM_INT_MASK_TNACK_IM_SHIFT           (5U)
/*! TNACK_IM - Transmit NACK Threshold Interrupt Mask
 *  0b0..TNTE interrupt enabled
 *  0b1..TNTE interrupt masked (default)
 */
#define EMVSIM_INT_MASK_TNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
#define EMVSIM_INT_MASK_TFF_IM_MASK              (0x40U)
#define EMVSIM_INT_MASK_TFF_IM_SHIFT             (6U)
/*! TFF_IM - Transmit FIFO Full Interrupt Mask
 *  0b0..TFF interrupt enabled
 *  0b1..TFF interrupt masked (default)
 */
#define EMVSIM_INT_MASK_TFF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
#define EMVSIM_INT_MASK_TDT_IM_MASK              (0x80U)
#define EMVSIM_INT_MASK_TDT_IM_SHIFT             (7U)
/*! TDT_IM - Transmit Data Threshold Interrupt Mask
 *  0b0..TDTF interrupt enabled
 *  0b1..TDTF interrupt masked (default)
 */
#define EMVSIM_INT_MASK_TDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
#define EMVSIM_INT_MASK_GPCNT0_IM_MASK           (0x100U)
#define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT          (8U)
/*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask
 *  0b0..GPCNT0_TO interrupt enabled
 *  0b1..GPCNT0_TO interrupt masked (default)
 */
#define EMVSIM_INT_MASK_GPCNT0_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
#define EMVSIM_INT_MASK_CWT_ERR_IM_MASK          (0x200U)
#define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT         (9U)
/*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask
 *  0b0..CWT_ERR interrupt enabled
 *  0b1..CWT_ERR interrupt masked (default)
 */
#define EMVSIM_INT_MASK_CWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
#define EMVSIM_INT_MASK_RNACK_IM_MASK            (0x400U)
#define EMVSIM_INT_MASK_RNACK_IM_SHIFT           (10U)
/*! RNACK_IM - Receiver NACK Threshold Interrupt Mask
 *  0b0..RTE interrupt enabled
 *  0b1..RTE interrupt masked (default)
 */
#define EMVSIM_INT_MASK_RNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
#define EMVSIM_INT_MASK_BWT_ERR_IM_MASK          (0x800U)
#define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT         (11U)
/*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask
 *  0b0..BWT_ERR interrupt enabled
 *  0b1..BWT_ERR interrupt masked (default)
 */
#define EMVSIM_INT_MASK_BWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
#define EMVSIM_INT_MASK_BGT_ERR_IM_MASK          (0x1000U)
#define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT         (12U)
/*! BGT_ERR_IM - Block Guard Time Error Interrupt
 *  0b0..BGT_ERR interrupt enabled
 *  0b1..BGT_ERR interrupt masked (default)
 */
#define EMVSIM_INT_MASK_BGT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
#define EMVSIM_INT_MASK_GPCNT1_IM_MASK           (0x2000U)
#define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT          (13U)
/*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask
 *  0b0..GPCNT1_TO interrupt enabled
 *  0b1..GPCNT1_TO interrupt masked (default)
 */
#define EMVSIM_INT_MASK_GPCNT1_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
#define EMVSIM_INT_MASK_RX_DATA_IM_MASK          (0x4000U)
#define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT         (14U)
/*! RX_DATA_IM - Receive Data Interrupt Mask
 *  0b0..RX_DATA interrupt enabled
 *  0b1..RX_DATA interrupt masked (default)
 */
#define EMVSIM_INT_MASK_RX_DATA_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
#define EMVSIM_INT_MASK_PEF_IM_MASK              (0x8000U)
#define EMVSIM_INT_MASK_PEF_IM_SHIFT             (15U)
/*! PEF_IM - Parity Error Interrupt Mask
 *  0b0..PEF interrupt enabled
 *  0b1..PEF interrupt masked (default)
 */
#define EMVSIM_INT_MASK_PEF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/*! @} */

/*! @name RX_THD - Receiver Threshold Register */
/*! @{ */
#define EMVSIM_RX_THD_RDT_MASK                   (0xFU)
#define EMVSIM_RX_THD_RDT_SHIFT                  (0U)
#define EMVSIM_RX_THD_RDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
#define EMVSIM_RX_THD_RNCK_THD_MASK              (0xF00U)
#define EMVSIM_RX_THD_RNCK_THD_SHIFT             (8U)
/*! RNCK_THD - Receiver NACK Threshold Value
 *  0b0000..Zero Threshold. RTE will not be set
 */
#define EMVSIM_RX_THD_RNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
/*! @} */

/*! @name TX_THD - Transmitter Threshold Register */
/*! @{ */
#define EMVSIM_TX_THD_TDT_MASK                   (0xFU)
#define EMVSIM_TX_THD_TDT_SHIFT                  (0U)
#define EMVSIM_TX_THD_TDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
#define EMVSIM_TX_THD_TNCK_THD_MASK              (0xF00U)
#define EMVSIM_TX_THD_TNCK_THD_SHIFT             (8U)
/*! TNCK_THD - Transmitter NACK Threshold Value
 *  0b0000..TNTE will never be set; retransmission after NACK reception is disabled.
 *  0b0001..TNTE will be set after 1 nack is received; 0 retransmissions occurs.
 *  0b0010..TNTE will be set after 2 nacks are received; at most 1 retransmission occurs.
 *  0b0011..TNTE will be set after 3 nacks are received; at most 2 retransmissions occurs.
 *  0b1111..TNTE will be set after 15 nacks are received; at most 14 retransmissions occurs.
 */
#define EMVSIM_TX_THD_TNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
/*! @} */

/*! @name RX_STATUS - Receive Status Register */
/*! @{ */
#define EMVSIM_RX_STATUS_RFO_MASK                (0x1U)
#define EMVSIM_RX_STATUS_RFO_SHIFT               (0U)
/*! RFO - Receive FIFO Overflow Flag
 *  0b0..No overrun error has occurred (default)
 *  0b1..A byte was received when the received FIFO was already full
 */
#define EMVSIM_RX_STATUS_RFO(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
#define EMVSIM_RX_STATUS_RX_DATA_MASK            (0x10U)
#define EMVSIM_RX_STATUS_RX_DATA_SHIFT           (4U)
/*! RX_DATA - Receive Data Interrupt Flag
 *  0b0..No new byte is received
 *  0b1..New byte is received ans stored in Receive FIFO
 */
#define EMVSIM_RX_STATUS_RX_DATA(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
#define EMVSIM_RX_STATUS_RDTF_MASK               (0x20U)
#define EMVSIM_RX_STATUS_RDTF_SHIFT              (5U)
/*! RDTF - Receive Data Threshold Interrupt Flag
 *  0b0..Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default).
 *  0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0].
 */
#define EMVSIM_RX_STATUS_RDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
#define EMVSIM_RX_STATUS_LRC_OK_MASK             (0x40U)
#define EMVSIM_RX_STATUS_LRC_OK_SHIFT            (6U)
/*! LRC_OK - LRC Check OK Flag
 *  0b0..Current LRC value does not match remainder.
 *  0b1..Current calculated LRC value matches the expected result (i.e. zero).
 */
#define EMVSIM_RX_STATUS_LRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
#define EMVSIM_RX_STATUS_CRC_OK_MASK             (0x80U)
#define EMVSIM_RX_STATUS_CRC_OK_SHIFT            (7U)
/*! CRC_OK - CRC Check OK Flag
 *  0b0..Current CRC value does not match remainder.
 *  0b1..Current calculated CRC value matches the expected result.
 */
#define EMVSIM_RX_STATUS_CRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
#define EMVSIM_RX_STATUS_CWT_ERR_MASK            (0x100U)
#define EMVSIM_RX_STATUS_CWT_ERR_SHIFT           (8U)
/*! CWT_ERR - Character Wait Time Error Flag
 *  0b0..No CWT violation has occurred (default).
 *  0b1..Time between two consecutive characters has exceeded the value in CHAR_WAIT.
 */
#define EMVSIM_RX_STATUS_CWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
#define EMVSIM_RX_STATUS_RTE_MASK                (0x200U)
#define EMVSIM_RX_STATUS_RTE_SHIFT               (9U)
/*! RTE - Received NACK Threshold Error Flag
 *  0b0..Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0]
 *  0b1..Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0]
 */
#define EMVSIM_RX_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
#define EMVSIM_RX_STATUS_BWT_ERR_MASK            (0x400U)
#define EMVSIM_RX_STATUS_BWT_ERR_SHIFT           (10U)
/*! BWT_ERR - Block Wait Time Error Flag
 *  0b0..Block wait time not exceeded
 *  0b1..Block wait time was exceeded
 */
#define EMVSIM_RX_STATUS_BWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
#define EMVSIM_RX_STATUS_BGT_ERR_MASK            (0x800U)
#define EMVSIM_RX_STATUS_BGT_ERR_SHIFT           (11U)
/*! BGT_ERR - Block Guard Time Error Flag
 *  0b0..Block guard time was sufficient
 *  0b1..Block guard time was too small
 */
#define EMVSIM_RX_STATUS_BGT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
#define EMVSIM_RX_STATUS_PEF_MASK                (0x1000U)
#define EMVSIM_RX_STATUS_PEF_SHIFT               (12U)
/*! PEF - Parity Error Flag
 *  0b0..No parity error detected
 *  0b1..Parity error detected
 */
#define EMVSIM_RX_STATUS_PEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
#define EMVSIM_RX_STATUS_FEF_MASK                (0x2000U)
#define EMVSIM_RX_STATUS_FEF_SHIFT               (13U)
/*! FEF - Frame Error Flag
 *  0b0..No frame error detected
 *  0b1..Frame error detected
 */
#define EMVSIM_RX_STATUS_FEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
#define EMVSIM_RX_STATUS_RX_WPTR_MASK            (0xF0000U)
#define EMVSIM_RX_STATUS_RX_WPTR_SHIFT           (16U)
#define EMVSIM_RX_STATUS_RX_WPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
#define EMVSIM_RX_STATUS_RX_CNT_MASK             (0xF000000U)
#define EMVSIM_RX_STATUS_RX_CNT_SHIFT            (24U)
/*! RX_CNT - Receive FIFO Byte Count
 *  0b0000..FIFO is emtpy
 */
#define EMVSIM_RX_STATUS_RX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
/*! @} */

/*! @name TX_STATUS - Transmitter Status Register */
/*! @{ */
#define EMVSIM_TX_STATUS_TNTE_MASK               (0x1U)
#define EMVSIM_TX_STATUS_TNTE_SHIFT              (0U)
/*! TNTE - Transmit NACK Threshold Error Flag
 *  0b0..Transmit NACK threshold has not been reached (default)
 *  0b1..Transmit NACK threshold reached; transmitter frozen
 */
#define EMVSIM_TX_STATUS_TNTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
#define EMVSIM_TX_STATUS_TFE_MASK                (0x8U)
#define EMVSIM_TX_STATUS_TFE_SHIFT               (3U)
/*! TFE - Transmit FIFO Empty Flag
 *  0b0..Transmit FIFO is not empty
 *  0b1..Transmit FIFO is empty (default)
 */
#define EMVSIM_TX_STATUS_TFE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
#define EMVSIM_TX_STATUS_ETCF_MASK               (0x10U)
#define EMVSIM_TX_STATUS_ETCF_SHIFT              (4U)
/*! ETCF - Early Transmit Complete Flag
 *  0b0..Transmit pending or in progress
 *  0b1..Transmit complete (default)
 */
#define EMVSIM_TX_STATUS_ETCF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
#define EMVSIM_TX_STATUS_TCF_MASK                (0x20U)
#define EMVSIM_TX_STATUS_TCF_SHIFT               (5U)
/*! TCF - Transmit Complete Flag
 *  0b0..Transmit pending or in progress
 *  0b1..Transmit complete (default)
 */
#define EMVSIM_TX_STATUS_TCF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
#define EMVSIM_TX_STATUS_TFF_MASK                (0x40U)
#define EMVSIM_TX_STATUS_TFF_SHIFT               (6U)
/*! TFF - Transmit FIFO Full Flag
 *  0b1..A Transmit FIFO Full condition has occurred
 */
#define EMVSIM_TX_STATUS_TFF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
#define EMVSIM_TX_STATUS_TDTF_MASK               (0x80U)
#define EMVSIM_TX_STATUS_TDTF_SHIFT              (7U)
/*! TDTF - Transmit Data Threshold Flag
 *  0b0..Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared
 *  0b1..Number of bytes in FIFO is less than or equal to TDT[3:0] (default)
 */
#define EMVSIM_TX_STATUS_TDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
#define EMVSIM_TX_STATUS_GPCNT0_TO_MASK          (0x100U)
#define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT         (8U)
/*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag
 *  0b0..GPCNT0_VAL time not reached, or bit has been cleared. (default)
 *  0b1..General Purpose counter has reached the GPCNT0_VAL value
 */
#define EMVSIM_TX_STATUS_GPCNT0_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
#define EMVSIM_TX_STATUS_GPCNT1_TO_MASK          (0x200U)
#define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT         (9U)
/*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag
 *  0b0..GPCNT1_VAL time not reached, or bit has been cleared. (default)
 *  0b1..General Purpose counter has reached the GPCNT1_VAL value
 */
#define EMVSIM_TX_STATUS_GPCNT1_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
#define EMVSIM_TX_STATUS_TX_RPTR_MASK            (0xF0000U)
#define EMVSIM_TX_STATUS_TX_RPTR_SHIFT           (16U)
#define EMVSIM_TX_STATUS_TX_RPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
#define EMVSIM_TX_STATUS_TX_CNT_MASK             (0xF000000U)
#define EMVSIM_TX_STATUS_TX_CNT_SHIFT            (24U)
/*! TX_CNT - Transmit FIFO Byte Count
 *  0b0000..FIFO is emtpy
 */
#define EMVSIM_TX_STATUS_TX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
/*! @} */

/*! @name PCSR - Port Control and Status Register */
/*! @{ */
#define EMVSIM_PCSR_SAPD_MASK                    (0x1U)
#define EMVSIM_PCSR_SAPD_SHIFT                   (0U)
/*! SAPD - Auto Power Down Enable
 *  0b0..Auto power down disabled (default)
 *  0b1..Auto power down enabled
 */
#define EMVSIM_PCSR_SAPD(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
#define EMVSIM_PCSR_SVCC_EN_MASK                 (0x2U)
#define EMVSIM_PCSR_SVCC_EN_SHIFT                (1U)
/*! SVCC_EN - Vcc Enable for Smart Card
 *  0b0..Smart Card Voltage disabled (default)
 *  0b1..Smart Card Voltage enabled
 */
#define EMVSIM_PCSR_SVCC_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
#define EMVSIM_PCSR_VCCENP_MASK                  (0x4U)
#define EMVSIM_PCSR_VCCENP_SHIFT                 (2U)
/*! VCCENP - VCC Enable Polarity Control
 *  0b0..VCC_EN is active high. Polarity of SVCC_EN is unchanged.
 *  0b1..VCC_EN is active low. Polarity of SVCC_EN is inverted.
 */
#define EMVSIM_PCSR_VCCENP(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
#define EMVSIM_PCSR_SRST_MASK                    (0x8U)
#define EMVSIM_PCSR_SRST_SHIFT                   (3U)
/*! SRST - Reset to Smart Card
 *  0b0..Smart Card Reset is asserted (default)
 *  0b1..Smart Card Reset is de-asserted
 */
#define EMVSIM_PCSR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
#define EMVSIM_PCSR_SCEN_MASK                    (0x10U)
#define EMVSIM_PCSR_SCEN_SHIFT                   (4U)
/*! SCEN - Clock Enable for Smart Card
 *  0b0..Smart Card Clock Disabled
 *  0b1..Smart Card Clock Enabled
 */
#define EMVSIM_PCSR_SCEN(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
#define EMVSIM_PCSR_SCSP_MASK                    (0x20U)
#define EMVSIM_PCSR_SCSP_SHIFT                   (5U)
/*! SCSP - Smart Card Clock Stop Polarity
 *  0b0..Clock is logic 0 when stopped by SCEN
 *  0b1..Clock is logic 1 when stopped by SCEN
 */
#define EMVSIM_PCSR_SCSP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
#define EMVSIM_PCSR_SPD_MASK                     (0x80U)
#define EMVSIM_PCSR_SPD_SHIFT                    (7U)
/*! SPD - Auto Power Down Control
 *  0b0..No effect (default)
 *  0b1..Start Auto Powerdown or Power Down is in progress
 */
#define EMVSIM_PCSR_SPD(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
#define EMVSIM_PCSR_SPDIM_MASK                   (0x1000000U)
#define EMVSIM_PCSR_SPDIM_SHIFT                  (24U)
/*! SPDIM - Smart Card Presence Detect Interrupt Mask
 *  0b0..SIM presence detect interrupt is enabled
 *  0b1..SIM presence detect interrupt is masked (default)
 */
#define EMVSIM_PCSR_SPDIM(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
#define EMVSIM_PCSR_SPDIF_MASK                   (0x2000000U)
#define EMVSIM_PCSR_SPDIF_SHIFT                  (25U)
/*! SPDIF - Smart Card Presence Detect Interrupt Flag
 *  0b0..No insertion or removal of Smart Card detected on Port (default)
 *  0b1..Insertion or removal of Smart Card detected on Port
 */
#define EMVSIM_PCSR_SPDIF(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
#define EMVSIM_PCSR_SPDP_MASK                    (0x4000000U)
#define EMVSIM_PCSR_SPDP_SHIFT                   (26U)
/*! SPDP - Smart Card Presence Detect Pin Status
 *  0b0..SIM Presence Detect pin is logic low
 *  0b1..SIM Presence Detectpin is logic high
 */
#define EMVSIM_PCSR_SPDP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
#define EMVSIM_PCSR_SPDES_MASK                   (0x8000000U)
#define EMVSIM_PCSR_SPDES_SHIFT                  (27U)
/*! SPDES - SIM Presence Detect Edge Select
 *  0b0..Falling edge on the pin (default)
 *  0b1..Rising edge on the pin
 */
#define EMVSIM_PCSR_SPDES(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
/*! @} */

/*! @name RX_BUF - Receive Data Read Buffer */
/*! @{ */
#define EMVSIM_RX_BUF_RX_BYTE_MASK               (0xFFU)
#define EMVSIM_RX_BUF_RX_BYTE_SHIFT              (0U)
#define EMVSIM_RX_BUF_RX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
/*! @} */

/*! @name TX_BUF - Transmit Data Buffer */
/*! @{ */
#define EMVSIM_TX_BUF_TX_BYTE_MASK               (0xFFU)
#define EMVSIM_TX_BUF_TX_BYTE_SHIFT              (0U)
#define EMVSIM_TX_BUF_TX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
/*! @} */

/*! @name TX_GETU - Transmitter Guard ETU Value Register */
/*! @{ */
#define EMVSIM_TX_GETU_GETU_MASK                 (0xFFU)
#define EMVSIM_TX_GETU_GETU_SHIFT                (0U)
/*! GETU - Transmitter Guard Time Value in ETU
 *  0b00000000..no additional ETUs inserted (default)
 *  0b00000001..1 additional ETU inserted
 *  0b11111110..254 additional ETUs inserted
 *  0b11111111..Subtracts one ETU by reducing the number of STOP bits from two to one
 */
#define EMVSIM_TX_GETU_GETU(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/*! @} */

/*! @name CWT_VAL - Character Wait Time Value Register */
/*! @{ */
#define EMVSIM_CWT_VAL_CWT_MASK                  (0xFFFFU)
#define EMVSIM_CWT_VAL_CWT_SHIFT                 (0U)
#define EMVSIM_CWT_VAL_CWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
/*! @} */

/*! @name BWT_VAL - Block Wait Time Value Register */
/*! @{ */
#define EMVSIM_BWT_VAL_BWT_MASK                  (0xFFFFFFFFU)
#define EMVSIM_BWT_VAL_BWT_SHIFT                 (0U)
#define EMVSIM_BWT_VAL_BWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
/*! @} */

/*! @name BGT_VAL - Block Guard Time Value Register */
/*! @{ */
#define EMVSIM_BGT_VAL_BGT_MASK                  (0xFFFFU)
#define EMVSIM_BGT_VAL_BGT_SHIFT                 (0U)
#define EMVSIM_BGT_VAL_BGT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
/*! @} */

/*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */
/*! @{ */
#define EMVSIM_GPCNT0_VAL_GPCNT0_MASK            (0xFFFFU)
#define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT           (0U)
#define EMVSIM_GPCNT0_VAL_GPCNT0(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
/*! @} */

/*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */
/*! @{ */
#define EMVSIM_GPCNT1_VAL_GPCNT1_MASK            (0xFFFFU)
#define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT           (0U)
#define EMVSIM_GPCNT1_VAL_GPCNT1(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group EMVSIM_Register_Masks */


/* EMVSIM - Peripheral instance base addresses */
/** Peripheral DMA__EMV_SIM0 base address */
#define DMA__EMV_SIM0_BASE                       (0x5A0D0000u)
/** Peripheral DMA__EMV_SIM0 base pointer */
#define DMA__EMV_SIM0                            ((EMVSIM_Type *)DMA__EMV_SIM0_BASE)
/** Peripheral DMA__EMV_SIM1 base address */
#define DMA__EMV_SIM1_BASE                       (0x5A0E0000u)
/** Peripheral DMA__EMV_SIM1 base pointer */
#define DMA__EMV_SIM1                            ((EMVSIM_Type *)DMA__EMV_SIM1_BASE)
/** Array initializer of EMVSIM peripheral base addresses */
#define EMVSIM_BASE_ADDRS                        { DMA__EMV_SIM0_BASE, DMA__EMV_SIM1_BASE }
/** Array initializer of EMVSIM peripheral base pointers */
#define EMVSIM_BASE_PTRS                         { DMA__EMV_SIM0, DMA__EMV_SIM1 }
/** Interrupt vectors for the EMVSIM peripheral type */
#define EMVSIM_IRQS                              { DMA_SIM0_INT_IRQn, DMA_SIM1_INT_IRQn }

/*!
 * @}
 */ /* end of group EMVSIM_Peripheral_Access_Layer */
 
 
/* ----------------------------------------------------------------------------
   -- ENET Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
 * @{
 */

/** ENET - Register Layout Typedef */
typedef struct {
  uint8_t RESERVED_0[4];
  __IO  uint32_t  EIR; /**< offset: 0x4 */
  __IO  uint32_t  EIMR; /**< offset: 0x8 */
  uint8_t RESERVED_1[4];
  __IO  uint32_t  RDAR; /**< offset: 0x10 */
  __IO  uint32_t  TDAR; /**< offset: 0x14 */
  uint8_t RESERVED_2[12];
  __IO  uint32_t  ECR; /**< offset: 0x24 */
  uint8_t RESERVED_3[24];
  __IO  uint32_t  MMFR; /**< offset: 0x40 */
  __IO  uint32_t  MSCR; /**< offset: 0x44 */
  uint8_t RESERVED_4[28];
  __IO  uint32_t  MIBC; /**< offset: 0x64 */
  uint8_t RESERVED_5[28];
  __IO  uint32_t  RCR; /**< offset: 0x84 */
  uint8_t RESERVED_6[60];
  __IO  uint32_t  TCR; /**< offset: 0xC4 */
  uint8_t RESERVED_7[28];
  __IO  uint32_t  PALR; /**< offset: 0xE4 */
  __IO  uint32_t  PAUR; /**< offset: 0xE8 */
  __IO  uint32_t  OPD; /**< offset: 0xEC */
  __IO  uint32_t  TXIC[3]; /**< offset: 0xF0 */
  uint8_t RESERVED_8[4];
  __IO  uint32_t  RXIC[3]; /**< offset: 0x100 */
  uint8_t RESERVED_9[12];
  __IO  uint32_t  IAUR; /**< offset: 0x118 */
  __IO  uint32_t  IALR; /**< offset: 0x11C */
  __IO  uint32_t  GAUR; /**< offset: 0x120 */
  __IO  uint32_t  GALR; /**< offset: 0x124 */
  uint8_t RESERVED_10[28];
  __IO  uint32_t  TFWR; /**< offset: 0x144 */
  uint8_t RESERVED_11[24];
  __IO  uint32_t  RDSR1; /**< offset: 0x160 */
  __IO  uint32_t  TDSR1; /**< offset: 0x164 */
  __IO  uint32_t  MRBR1; /**< offset: 0x168 */
  __IO  uint32_t  RDSR2; /**< offset: 0x16C */
  __IO  uint32_t  TDSR2; /**< offset: 0x170 */
  __IO  uint32_t  MRBR2; /**< offset: 0x174 */
  uint8_t RESERVED_12[8];
  __IO  uint32_t  RDSR; /**< offset: 0x180 */
  __IO  uint32_t  TDSR; /**< offset: 0x184 */
  __IO  uint32_t  MRBR; /**< offset: 0x188 */
  uint8_t RESERVED_13[4];
  __IO  uint32_t  RSFL; /**< offset: 0x190 */
  __IO  uint32_t  RSEM; /**< offset: 0x194 */
  __IO  uint32_t  RAEM; /**< offset: 0x198 */
  __IO  uint32_t  RAFL; /**< offset: 0x19C */
  __IO  uint32_t  TSEM; /**< offset: 0x1A0 */
  __IO  uint32_t  TAEM; /**< offset: 0x1A4 */
  __IO  uint32_t  TAFL; /**< offset: 0x1A8 */
  __IO  uint32_t  TIPG; /**< offset: 0x1AC */
  __IO  uint32_t  FTRL; /**< offset: 0x1B0 */
  uint8_t RESERVED_14[12];
  __IO  uint32_t  TACC; /**< offset: 0x1C0 */
  __IO  uint32_t  RACC; /**< offset: 0x1C4 */
  __IO  uint32_t  RCMR[2]; /**< offset: 0x1C8 */
  uint8_t RESERVED_15[8];
  __IO  uint32_t  DMACFG[2]; /**< offset: 0x1D8 */
  __IO  uint32_t  RDAR1; /**< offset: 0x1E0 */
  __IO  uint32_t  TDAR1; /**< offset: 0x1E4 */
  __IO  uint32_t  RDAR2; /**< offset: 0x1E8 */
  __IO  uint32_t  TDAR2; /**< offset: 0x1EC */
  __IO  uint32_t  QOS; /**< offset: 0x1F0 */
  uint8_t RESERVED_16[12];
  __I   uint32_t  RMON_T_DROP; /**< offset: 0x200 */
  __I   uint32_t  RMON_T_PACKETS; /**< offset: 0x204 */
  __I   uint32_t  RMON_T_BC_PKT; /**< offset: 0x208 */
  __I   uint32_t  RMON_T_MC_PKT; /**< offset: 0x20C */
  __I   uint32_t  RMON_T_CRC_ALIGN; /**< offset: 0x210 */
  __I   uint32_t  RMON_T_UNDERSIZE; /**< offset: 0x214 */
  __I   uint32_t  RMON_T_OVERSIZE; /**< offset: 0x218 */
  __I   uint32_t  RMON_T_FRAG; /**< offset: 0x21C */
  __I   uint32_t  RMON_T_JAB; /**< offset: 0x220 */
  __I   uint32_t  RMON_T_COL; /**< offset: 0x224 */
  __I   uint32_t  RMON_T_P64; /**< offset: 0x228 */
  __I   uint32_t  RMON_T_P65TO127; /**< offset: 0x22C */
  __I   uint32_t  RMON_T_P128TO255; /**< offset: 0x230 */
  __I   uint32_t  RMON_T_P256TO511; /**< offset: 0x234 */
  __I   uint32_t  RMON_T_P512TO1023; /**< offset: 0x238 */
  __I   uint32_t  RMON_T_P1024TO2047; /**< offset: 0x23C */
  __I   uint32_t  RMON_T_P_GTE2048; /**< offset: 0x240 */
  __I   uint32_t  RMON_T_OCTETS; /**< offset: 0x244 */
  __I   uint32_t  IEEE_T_DROP; /**< offset: 0x248 */
  __I   uint32_t  IEEE_T_FRAME_OK; /**< offset: 0x24C */
  __I   uint32_t  IEEE_T_1COL; /**< offset: 0x250 */
  __I   uint32_t  IEEE_T_MCOL; /**< offset: 0x254 */
  __I   uint32_t  IEEE_T_DEF; /**< offset: 0x258 */
  __I   uint32_t  IEEE_T_LCOL; /**< offset: 0x25C */
  __I   uint32_t  IEEE_T_EXCOL; /**< offset: 0x260 */
  __I   uint32_t  IEEE_T_MACERR; /**< offset: 0x264 */
  __I   uint32_t  IEEE_T_CSERR; /**< offset: 0x268 */
  __I   uint32_t  IEEE_T_SQE; /**< offset: 0x26C */
  __I   uint32_t  IEEE_T_FDXFC; /**< offset: 0x270 */
  __I   uint32_t  IEEE_T_OCTETS_OK; /**< offset: 0x274 */
  uint8_t RESERVED_17[12];
  __I   uint32_t  RMON_R_PACKETS; /**< offset: 0x284 */
  __I   uint32_t  RMON_R_BC_PKT; /**< offset: 0x288 */
  __I   uint32_t  RMON_R_MC_PKT; /**< offset: 0x28C */
  __I   uint32_t  RMON_R_CRC_ALIGN; /**< offset: 0x290 */
  __I   uint32_t  RMON_R_UNDERSIZE; /**< offset: 0x294 */
  __I   uint32_t  RMON_R_OVERSIZE; /**< offset: 0x298 */
  __I   uint32_t  RMON_R_FRAG; /**< offset: 0x29C */
  __I   uint32_t  RMON_R_JAB; /**< offset: 0x2A0 */
  __I   uint32_t  RMON_R_RESVD_0; /**< offset: 0x2A4 */
  __I   uint32_t  RMON_R_P64; /**< offset: 0x2A8 */
  __I   uint32_t  RMON_R_P65TO127; /**< offset: 0x2AC */
  __I   uint32_t  RMON_R_P128TO255; /**< offset: 0x2B0 */
  __I   uint32_t  RMON_R_P256TO511; /**< offset: 0x2B4 */
  __I   uint32_t  RMON_R_P512TO1023; /**< offset: 0x2B8 */
  __I   uint32_t  RMON_R_P1024TO2047; /**< offset: 0x2BC */
  __I   uint32_t  RMON_R_P_GTE2048; /**< offset: 0x2C0 */
  __I   uint32_t  RMON_R_OCTETS; /**< offset: 0x2C4 */
  __I   uint32_t  IEEE_R_DROP; /**< offset: 0x2C8 */
  __I   uint32_t  IEEE_R_FRAME_OK; /**< offset: 0x2CC */
  __I   uint32_t  IEEE_R_CRC; /**< offset: 0x2D0 */
  __I   uint32_t  IEEE_R_ALIGN; /**< offset: 0x2D4 */
  __I   uint32_t  IEEE_R_MACERR; /**< offset: 0x2D8 */
  __I   uint32_t  IEEE_R_FDXFC; /**< offset: 0x2DC */
  __I   uint32_t  IEEE_R_OCTETS_OK; /**< offset: 0x2E0 */
  uint8_t RESERVED_18[284];
  __IO  uint32_t  ATCR; /**< offset: 0x400 */
  __IO  uint32_t  ATVR; /**< offset: 0x404 */
  __IO  uint32_t  ATOFF; /**< offset: 0x408 */
  __IO  uint32_t  ATPER; /**< offset: 0x40C */
  __IO  uint32_t  ATCOR; /**< offset: 0x410 */
  __IO  uint32_t  ATINC; /**< offset: 0x414 */
  __I   uint32_t  ATSTMP; /**< offset: 0x418 */
  uint8_t RESERVED_19[356];
  __IO  uint32_t  MDATA; /**< offset: 0x580 */
  __IO  uint32_t  MMASK; /**< offset: 0x584 */
  __IO  uint32_t  MCONFIG; /**< offset: 0x588 */
  __IO  uint32_t  MENTRYRW; /**< offset: 0x58C */
  __IO  uint32_t  RXPCTL; /**< offset: 0x590 */
  __IO  uint32_t  MAXFRMOFF; /**< offset: 0x594 */
  __I   uint32_t  RXPARST; /**< offset: 0x598 */
  uint8_t RESERVED_20[4];
  __I   uint32_t  PARSDSCD; /**< offset: 0x5A0 */
  struct {                  /**< offset: 0x5A4 */
  __I     uint32_t  PRSACPT;
  __I     uint32_t  PRSRJCT;
  } PRS[3];
  uint8_t RESERVED_21[72];
  __IO  uint32_t  TGSR; /**< offset: 0x604 */
  struct {              /**< offset: 0x608 */
  __IO    uint32_t TCSR;
  __IO    uint32_t TCCR;
  } CHANNEL[4];
} ENET_Type;

/* ----------------------------------------------------------------------------
   -- ENET Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ENET_Register_Masks ENET Register Masks
 * @{
 */

/* EIR Bit Fields */
#define ENET_EIR_RXB1_MASK                       0x1u
#define ENET_EIR_RXB1_SHIFT                      0
#define ENET_EIR_RXF1_MASK                       0x2u
#define ENET_EIR_RXF1_SHIFT                      1
#define ENET_EIR_TXB1_MASK                       0x4u
#define ENET_EIR_TXB1_SHIFT                      2
#define ENET_EIR_TXF1_MASK                       0x8u
#define ENET_EIR_TXF1_SHIFT                      3
#define ENET_EIR_RXB2_MASK                       0x10u
#define ENET_EIR_RXB2_SHIFT                      4
#define ENET_EIR_RXF2_MASK                       0x20u
#define ENET_EIR_RXF2_SHIFT                      5
#define ENET_EIR_TXB2_MASK                       0x40u
#define ENET_EIR_TXB2_SHIFT                      6
#define ENET_EIR_TXF2_MASK                       0x80u
#define ENET_EIR_TXF2_SHIFT                      7
#define ENET_EIR_RXFLUSH_0_MASK                  0x1000u
#define ENET_EIR_RXFLUSH_0_SHIFT                 12
#define ENET_EIR_RXFLUSH_1_MASK                  0x2000u
#define ENET_EIR_RXFLUSH_1_SHIFT                 13
#define ENET_EIR_RXFLUSH_2_MASK                  0x4000u
#define ENET_EIR_RXFLUSH_2_SHIFT                 14
#define ENET_EIR_TS_TIMER_MASK                   0x8000u
#define ENET_EIR_TS_TIMER_SHIFT                  15
#define ENET_EIR_TS_AVAIL_MASK                   0x10000u
#define ENET_EIR_TS_AVAIL_SHIFT                  16
#define ENET_EIR_WAKEUP_MASK                     0x20000u
#define ENET_EIR_WAKEUP_SHIFT                    17
#define ENET_EIR_PLR_MASK                        0x40000u
#define ENET_EIR_PLR_SHIFT                       18
#define ENET_EIR_UN_MASK                         0x80000u
#define ENET_EIR_UN_SHIFT                        19
#define ENET_EIR_RL_MASK                         0x100000u
#define ENET_EIR_RL_SHIFT                        20
#define ENET_EIR_LC_MASK                         0x200000u
#define ENET_EIR_LC_SHIFT                        21
#define ENET_EIR_EBERR_MASK                      0x400000u
#define ENET_EIR_EBERR_SHIFT                     22
#define ENET_EIR_MII_MASK                        0x800000u
#define ENET_EIR_MII_SHIFT                       23
#define ENET_EIR_RXB_MASK                        0x1000000u
#define ENET_EIR_RXB_SHIFT                       24
#define ENET_EIR_RXF_MASK                        0x2000000u
#define ENET_EIR_RXF_SHIFT                       25
#define ENET_EIR_TXB_MASK                        0x4000000u
#define ENET_EIR_TXB_SHIFT                       26
#define ENET_EIR_TXF_MASK                        0x8000000u
#define ENET_EIR_TXF_SHIFT                       27
#define ENET_EIR_GRA_MASK                        0x10000000u
#define ENET_EIR_GRA_SHIFT                       28
#define ENET_EIR_BABT_MASK                       0x20000000u
#define ENET_EIR_BABT_SHIFT                      29
#define ENET_EIR_BABR_MASK                       0x40000000u
#define ENET_EIR_BABR_SHIFT                      30
/* EIMR Bit Fields */
#define ENET_EIMR_RXB1_MASK                      0x1u
#define ENET_EIMR_RXB1_SHIFT                     0
#define ENET_EIMR_RXF1_MASK                      0x2u
#define ENET_EIMR_RXF1_SHIFT                     1
#define ENET_EIMR_TXB1_MASK                      0x4u
#define ENET_EIMR_TXB1_SHIFT                     2
#define ENET_EIMR_TXF1_MASK                      0x8u
#define ENET_EIMR_TXF1_SHIFT                     3
#define ENET_EIMR_RXB2_MASK                      0x10u
#define ENET_EIMR_RXB2_SHIFT                     4
#define ENET_EIMR_RXF2_MASK                      0x20u
#define ENET_EIMR_RXF2_SHIFT                     5
#define ENET_EIMR_TXB2_MASK                      0x40u
#define ENET_EIMR_TXB2_SHIFT                     6
#define ENET_EIMR_TXF2_MASK                      0x80u
#define ENET_EIMR_TXF2_SHIFT                     7
#define ENET_EIMR_RXFLUSH_0_MASK                 0x1000u
#define ENET_EIMR_RXFLUSH_0_SHIFT                12
#define ENET_EIMR_RXFLUSH_1_MASK                 0x2000u
#define ENET_EIMR_RXFLUSH_1_SHIFT                13
#define ENET_EIMR_RXFLUSH_2_MASK                 0x4000u
#define ENET_EIMR_RXFLUSH_2_SHIFT                14
#define ENET_EIMR_TS_TIMER_MASK                  0x8000u
#define ENET_EIMR_TS_TIMER_SHIFT                 15
#define ENET_EIMR_TS_AVAIL_MASK                  0x10000u
#define ENET_EIMR_TS_AVAIL_SHIFT                 16
#define ENET_EIMR_WAKEUP_MASK                    0x20000u
#define ENET_EIMR_WAKEUP_SHIFT                   17
#define ENET_EIMR_PLR_MASK                       0x40000u
#define ENET_EIMR_PLR_SHIFT                      18
#define ENET_EIMR_UN_MASK                        0x80000u
#define ENET_EIMR_UN_SHIFT                       19
#define ENET_EIMR_RL_MASK                        0x100000u
#define ENET_EIMR_RL_SHIFT                       20
#define ENET_EIMR_LC_MASK                        0x200000u
#define ENET_EIMR_LC_SHIFT                       21
#define ENET_EIMR_EBERR_MASK                     0x400000u
#define ENET_EIMR_EBERR_SHIFT                    22
#define ENET_EIMR_MII_MASK                       0x800000u
#define ENET_EIMR_MII_SHIFT                      23
#define ENET_EIMR_RXB_MASK                       0x1000000u
#define ENET_EIMR_RXB_SHIFT                      24
#define ENET_EIMR_RXF_MASK                       0x2000000u
#define ENET_EIMR_RXF_SHIFT                      25
#define ENET_EIMR_TXB_MASK                       0x4000000u
#define ENET_EIMR_TXB_SHIFT                      26
#define ENET_EIMR_TXF_MASK                       0x8000000u
#define ENET_EIMR_TXF_SHIFT                      27
#define ENET_EIMR_GRA_MASK                       0x10000000u
#define ENET_EIMR_GRA_SHIFT                      28
#define ENET_EIMR_BABT_MASK                      0x20000000u
#define ENET_EIMR_BABT_SHIFT                     29
#define ENET_EIMR_BABR_MASK                      0x40000000u
#define ENET_EIMR_BABR_SHIFT                     30
/* RDAR Bit Fields */
#define ENET_RDAR_RDAR_MASK                      0x1000000u
#define ENET_RDAR_RDAR_SHIFT                     24
/* TDAR Bit Fields */
#define ENET_TDAR_TDAR_MASK                      0x1000000u
#define ENET_TDAR_TDAR_SHIFT                     24
/* ECR Bit Fields */
#define ENET_ECR_RESET_MASK                      0x1u
#define ENET_ECR_RESET_SHIFT                     0
#define ENET_ECR_ETHEREN_MASK                    0x2u
#define ENET_ECR_ETHEREN_SHIFT                   1
#define ENET_ECR_MAGICEN_MASK                    0x4u
#define ENET_ECR_MAGICEN_SHIFT                   2
#define ENET_ECR_SLEEP_MASK                      0x8u
#define ENET_ECR_SLEEP_SHIFT                     3
#define ENET_ECR_EN1588_MASK                     0x10u
#define ENET_ECR_EN1588_SHIFT                    4
#define ENET_ECR_SPEED_MASK                      0x20u
#define ENET_ECR_SPEED_SHIFT                     5
#define ENET_ECR_DBGEN_MASK                      0x40u
#define ENET_ECR_DBGEN_SHIFT                     6
#define ENET_ECR_DBSWP_MASK                      0x100u
#define ENET_ECR_DBSWP_SHIFT                     8
#define ENET_ECR_SVLANEN_MASK                    0x200u
#define ENET_ECR_SVLANEN_SHIFT                   9
#define ENET_ECR_VLANUSE2ND_MASK                 0x400u
#define ENET_ECR_VLANUSE2ND_SHIFT                10
#define ENET_ECR_SVLANDBL_MASK                   0x800u
#define ENET_ECR_SVLANDBL_SHIFT                  11
#define ENET_ECR_TXC_DLY_MASK                    0x10000u
#define ENET_ECR_TXC_DLY_SHIFT                   16
#define ENET_ECR_RXC_DLY_MASK                    0x20000u
#define ENET_ECR_RXC_DLY_SHIFT                   17
/* MMFR Bit Fields */
#define ENET_MMFR_DATA_MASK                      0xFFFFu
#define ENET_MMFR_DATA_SHIFT                     0
#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
#define ENET_MMFR_TA_MASK                        0x30000u
#define ENET_MMFR_TA_SHIFT                       16
#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
#define ENET_MMFR_RA_MASK                        0x7C0000u
#define ENET_MMFR_RA_SHIFT                       18
#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
#define ENET_MMFR_PA_MASK                        0xF800000u
#define ENET_MMFR_PA_SHIFT                       23
#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
#define ENET_MMFR_OP_MASK                        0x30000000u
#define ENET_MMFR_OP_SHIFT                       28
#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
#define ENET_MMFR_ST_MASK                        0xC0000000u
#define ENET_MMFR_ST_SHIFT                       30
#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
/* MSCR Bit Fields */
#define ENET_MSCR_MII_SPEED_MASK                 0x7Eu
#define ENET_MSCR_MII_SPEED_SHIFT                1
#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
#define ENET_MSCR_DIS_PRE_MASK                   0x80u
#define ENET_MSCR_DIS_PRE_SHIFT                  7
#define ENET_MSCR_HOLDTIME_MASK                  0x700u
#define ENET_MSCR_HOLDTIME_SHIFT                 8
#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
/* MIBC Bit Fields */
#define ENET_MIBC_MIB_CLEAR_MASK                 0x20000000u
#define ENET_MIBC_MIB_CLEAR_SHIFT                29
#define ENET_MIBC_MIB_IDLE_MASK                  0x40000000u
#define ENET_MIBC_MIB_IDLE_SHIFT                 30
#define ENET_MIBC_MIB_DIS_MASK                   0x80000000u
#define ENET_MIBC_MIB_DIS_SHIFT                  31
/* RCR Bit Fields */
#define ENET_RCR_LOOP_MASK                       0x1u
#define ENET_RCR_LOOP_SHIFT                      0
#define ENET_RCR_DRT_MASK                        0x2u
#define ENET_RCR_DRT_SHIFT                       1
#define ENET_RCR_MII_MODE_MASK                   0x4u
#define ENET_RCR_MII_MODE_SHIFT                  2
#define ENET_RCR_PROM_MASK                       0x8u
#define ENET_RCR_PROM_SHIFT                      3
#define ENET_RCR_BC_REJ_MASK                     0x10u
#define ENET_RCR_BC_REJ_SHIFT                    4
#define ENET_RCR_FCE_MASK                        0x20u
#define ENET_RCR_FCE_SHIFT                       5
#define ENET_RCR_RGMII_EN_MASK                   0x40u
#define ENET_RCR_RGMII_EN_SHIFT                  6
#define ENET_RCR_RMII_MODE_MASK                  0x100u
#define ENET_RCR_RMII_MODE_SHIFT                 8
#define ENET_RCR_RMII_10T_MASK                   0x200u
#define ENET_RCR_RMII_10T_SHIFT                  9
#define ENET_RCR_PADEN_MASK                      0x1000u
#define ENET_RCR_PADEN_SHIFT                     12
#define ENET_RCR_PAUFWD_MASK                     0x2000u
#define ENET_RCR_PAUFWD_SHIFT                    13
#define ENET_RCR_CRCFWD_MASK                     0x4000u
#define ENET_RCR_CRCFWD_SHIFT                    14
#define ENET_RCR_CFEN_MASK                       0x8000u
#define ENET_RCR_CFEN_SHIFT                      15
#define ENET_RCR_MAX_FL_MASK                     0x3FFF0000u
#define ENET_RCR_MAX_FL_SHIFT                    16
#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
#define ENET_RCR_NLC_MASK                        0x40000000u
#define ENET_RCR_NLC_SHIFT                       30
#define ENET_RCR_GRS_MASK                        0x80000000u
#define ENET_RCR_GRS_SHIFT                       31
/* TCR Bit Fields */
#define ENET_TCR_GTS_MASK                        0x1u
#define ENET_TCR_GTS_SHIFT                       0
#define ENET_TCR_FDEN_MASK                       0x4u
#define ENET_TCR_FDEN_SHIFT                      2
#define ENET_TCR_TFC_PAUSE_MASK                  0x8u
#define ENET_TCR_TFC_PAUSE_SHIFT                 3
#define ENET_TCR_RFC_PAUSE_MASK                  0x10u
#define ENET_TCR_RFC_PAUSE_SHIFT                 4
#define ENET_TCR_ADDSEL_MASK                     0xE0u
#define ENET_TCR_ADDSEL_SHIFT                    5
#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
#define ENET_TCR_ADDINS_MASK                     0x100u
#define ENET_TCR_ADDINS_SHIFT                    8
#define ENET_TCR_CRCFWD_MASK                     0x200u
#define ENET_TCR_CRCFWD_SHIFT                    9
/* PALR Bit Fields */
#define ENET_PALR_PADDR1_MASK                    0xFFFFFFFFu
#define ENET_PALR_PADDR1_SHIFT                   0
#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
/* PAUR Bit Fields */
#define ENET_PAUR_TYPE_MASK                      0xFFFFu
#define ENET_PAUR_TYPE_SHIFT                     0
#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
#define ENET_PAUR_PADDR2_MASK                    0xFFFF0000u
#define ENET_PAUR_PADDR2_SHIFT                   16
#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
/* OPD Bit Fields */
#define ENET_OPD_PAUSE_DUR_MASK                  0xFFFFu
#define ENET_OPD_PAUSE_DUR_SHIFT                 0
#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
#define ENET_OPD_OPCODE_MASK                     0xFFFF0000u
#define ENET_OPD_OPCODE_SHIFT                    16
#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
/* TXIC Bit Fields */
#define ENET_TXIC_ICTT_MASK                      0xFFFFu
#define ENET_TXIC_ICTT_SHIFT                     0
#define ENET_TXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TXIC_ICTT_SHIFT))&ENET_TXIC_ICTT_MASK)
#define ENET_TXIC_ICFT_MASK                      0xFF00000u
#define ENET_TXIC_ICFT_SHIFT                     20
#define ENET_TXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TXIC_ICFT_SHIFT))&ENET_TXIC_ICFT_MASK)
#define ENET_TXIC_ICCS_MASK                      0x40000000u
#define ENET_TXIC_ICCS_SHIFT                     30
#define ENET_TXIC_ICEN_MASK                      0x80000000u
#define ENET_TXIC_ICEN_SHIFT                     31
/* RXIC Bit Fields */
#define ENET_RXIC_ICTT_MASK                      0xFFFFu
#define ENET_RXIC_ICTT_SHIFT                     0
#define ENET_RXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RXIC_ICTT_SHIFT))&ENET_RXIC_ICTT_MASK)
#define ENET_RXIC_ICFT_MASK                      0xFF00000u
#define ENET_RXIC_ICFT_SHIFT                     20
#define ENET_RXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RXIC_ICFT_SHIFT))&ENET_RXIC_ICFT_MASK)
#define ENET_RXIC_ICCS_MASK                      0x40000000u
#define ENET_RXIC_ICCS_SHIFT                     30
#define ENET_RXIC_ICEN_MASK                      0x80000000u
#define ENET_RXIC_ICEN_SHIFT                     31
/* IAUR Bit Fields */
#define ENET_IAUR_IADDR1_MASK                    0xFFFFFFFFu
#define ENET_IAUR_IADDR1_SHIFT                   0
#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
/* IALR Bit Fields */
#define ENET_IALR_IADDR2_MASK                    0xFFFFFFFFu
#define ENET_IALR_IADDR2_SHIFT                   0
#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
/* GAUR Bit Fields */
#define ENET_GAUR_GADDR1_MASK                    0xFFFFFFFFu
#define ENET_GAUR_GADDR1_SHIFT                   0
#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
/* GALR Bit Fields */
#define ENET_GALR_GADDR2_MASK                    0xFFFFFFFFu
#define ENET_GALR_GADDR2_SHIFT                   0
#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
/* TFWR Bit Fields */
#define ENET_TFWR_TFWR_MASK                      0x3Fu
#define ENET_TFWR_TFWR_SHIFT                     0
#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
#define ENET_TFWR_STRFWD_MASK                    0x100u
#define ENET_TFWR_STRFWD_SHIFT                   8
/* RDSR1 Bit Fields */
#define ENET_RDSR1_R_DES_START_MASK              0xFFFFFFF8u
#define ENET_RDSR1_R_DES_START_SHIFT             3
#define ENET_RDSR1_R_DES_START(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RDSR1_R_DES_START_SHIFT))&ENET_RDSR1_R_DES_START_MASK)
/* TDSR1 Bit Fields */
#define ENET_TDSR1_X_DES_START_MASK              0xFFFFFFF8u
#define ENET_TDSR1_X_DES_START_SHIFT             3
#define ENET_TDSR1_X_DES_START(x)                (((uint32_t)(((uint32_t)(x))<<ENET_TDSR1_X_DES_START_SHIFT))&ENET_TDSR1_X_DES_START_MASK)
/* MRBR1 Bit Fields */
#define ENET_MRBR1_R_BUF_SIZE_MASK               0x7F0u
#define ENET_MRBR1_R_BUF_SIZE_SHIFT              4
#define ENET_MRBR1_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_MRBR1_R_BUF_SIZE_SHIFT))&ENET_MRBR1_R_BUF_SIZE_MASK)
/* RDSR2 Bit Fields */
#define ENET_RDSR2_R_DES_START_MASK              0xFFFFFFF8u
#define ENET_RDSR2_R_DES_START_SHIFT             3
#define ENET_RDSR2_R_DES_START(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RDSR2_R_DES_START_SHIFT))&ENET_RDSR2_R_DES_START_MASK)
/* TDSR2 Bit Fields */
#define ENET_TDSR2_X_DES_START_MASK              0xFFFFFFF8u
#define ENET_TDSR2_X_DES_START_SHIFT             3
#define ENET_TDSR2_X_DES_START(x)                (((uint32_t)(((uint32_t)(x))<<ENET_TDSR2_X_DES_START_SHIFT))&ENET_TDSR2_X_DES_START_MASK)
/* MRBR2 Bit Fields */
#define ENET_MRBR2_R_BUF_SIZE_MASK               0x7F0u
#define ENET_MRBR2_R_BUF_SIZE_SHIFT              4
#define ENET_MRBR2_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_MRBR2_R_BUF_SIZE_SHIFT))&ENET_MRBR2_R_BUF_SIZE_MASK)
/* RDSR Bit Fields */
#define ENET_RDSR_R_DES_START_MASK               0xFFFFFFF8u
#define ENET_RDSR_R_DES_START_SHIFT              3
#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
/* TDSR Bit Fields */
#define ENET_TDSR_X_DES_START_MASK               0xFFFFFFF8u
#define ENET_TDSR_X_DES_START_SHIFT              3
#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
/* MRBR Bit Fields */
#define ENET_MRBR_R_BUF_SIZE_MASK                0x7F0u
#define ENET_MRBR_R_BUF_SIZE_SHIFT               4
#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
/* RSFL Bit Fields */
#define ENET_RSFL_RX_SECTION_FULL_MASK           0x3FFu
#define ENET_RSFL_RX_SECTION_FULL_SHIFT          0
#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
/* RSEM Bit Fields */
#define ENET_RSEM_RX_SECTION_EMPTY_MASK          0x3FFu
#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         0
#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
#define ENET_RSEM_STAT_SECTION_EMPTY_MASK        0x1F0000u
#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       16
#define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
/* RAEM Bit Fields */
#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           0x3FFu
#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          0
#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
/* RAFL Bit Fields */
#define ENET_RAFL_RX_ALMOST_FULL_MASK            0x3FFu
#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           0
#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
/* TSEM Bit Fields */
#define ENET_TSEM_TX_SECTION_EMPTY_MASK          0x3FFu
#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         0
#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
/* TAEM Bit Fields */
#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           0x3FFu
#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          0
#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
/* TAFL Bit Fields */
#define ENET_TAFL_TX_ALMOST_FULL_MASK            0x3FFu
#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           0
#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
/* TIPG Bit Fields */
#define ENET_TIPG_IPG_MASK                       0x1Fu
#define ENET_TIPG_IPG_SHIFT                      0
#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
/* FTRL Bit Fields */
#define ENET_FTRL_TRUNC_FL_MASK                  0x3FFFu
#define ENET_FTRL_TRUNC_FL_SHIFT                 0
#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
/* TACC Bit Fields */
#define ENET_TACC_SHIFT16_MASK                   0x1u
#define ENET_TACC_SHIFT16_SHIFT                  0
#define ENET_TACC_IPCHK_MASK                     0x8u
#define ENET_TACC_IPCHK_SHIFT                    3
#define ENET_TACC_PROCHK_MASK                    0x10u
#define ENET_TACC_PROCHK_SHIFT                   4
/* RACC Bit Fields */
#define ENET_RACC_PADREM_MASK                    0x1u
#define ENET_RACC_PADREM_SHIFT                   0
#define ENET_RACC_IPDIS_MASK                     0x2u
#define ENET_RACC_IPDIS_SHIFT                    1
#define ENET_RACC_PRODIS_MASK                    0x4u
#define ENET_RACC_PRODIS_SHIFT                   2
#define ENET_RACC_LINEDIS_MASK                   0x40u
#define ENET_RACC_LINEDIS_SHIFT                  6
#define ENET_RACC_SHIFT16_MASK                   0x80u
#define ENET_RACC_SHIFT16_SHIFT                  7
/* RCMR Bit Fields */
#define ENET_RCMR_CMP0_MASK                      0x7u
#define ENET_RCMR_CMP0_SHIFT                     0
#define ENET_RCMR_CMP0(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP0_SHIFT))&ENET_RCMR_CMP0_MASK)
#define ENET_RCMR_CMP1_MASK                      0x70u
#define ENET_RCMR_CMP1_SHIFT                     4
#define ENET_RCMR_CMP1(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP1_SHIFT))&ENET_RCMR_CMP1_MASK)
#define ENET_RCMR_CMP2_MASK                      0x700u
#define ENET_RCMR_CMP2_SHIFT                     8
#define ENET_RCMR_CMP2(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP2_SHIFT))&ENET_RCMR_CMP2_MASK)
#define ENET_RCMR_CMP3_MASK                      0x7000u
#define ENET_RCMR_CMP3_SHIFT                     12
#define ENET_RCMR_CMP3(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP3_SHIFT))&ENET_RCMR_CMP3_MASK)
#define ENET_RCMR_MATCHEN_MASK                   0x10000u
#define ENET_RCMR_MATCHEN_SHIFT                  16
/* DMACFG Bit Fields */
#define ENET_DMACFG_IDLE_SLOPE_MASK              0xFFFFu
#define ENET_DMACFG_IDLE_SLOPE_SHIFT             0
#define ENET_DMACFG_IDLE_SLOPE(x)                (((uint32_t)(((uint32_t)(x))<<ENET_DMACFG_IDLE_SLOPE_SHIFT))&ENET_DMACFG_IDLE_SLOPE_MASK)
#define ENET_DMACFG_DMA_CLASS_EN_MASK            0x10000u
#define ENET_DMACFG_DMA_CLASS_EN_SHIFT           16
#define ENET_DMACFG_CALC_NOIPG_MASK              0x20000u
#define ENET_DMACFG_CALC_NOIPG_SHIFT             17
/* RDAR1 Bit Fields */
#define ENET_RDAR1_RDAR_MASK                     0x1000000u
#define ENET_RDAR1_RDAR_SHIFT                    24
/* TDAR1 Bit Fields */
#define ENET_TDAR1_TDAR_MASK                     0x1000000u
#define ENET_TDAR1_TDAR_SHIFT                    24
/* RDAR2 Bit Fields */
#define ENET_RDAR2_RDAR_MASK                     0x1000000u
#define ENET_RDAR2_RDAR_SHIFT                    24
/* TDAR2 Bit Fields */
#define ENET_TDAR2_TDAR_MASK                     0x1000000u
#define ENET_TDAR2_TDAR_SHIFT                    24
/* QOS Bit Fields */
#define ENET_QOS_TX_SCHEME_MASK                  0x7u
#define ENET_QOS_TX_SCHEME_SHIFT                 0
#define ENET_QOS_TX_SCHEME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_QOS_TX_SCHEME_SHIFT))&ENET_QOS_TX_SCHEME_MASK)
#define ENET_QOS_RX_FLUSH0_MASK                  0x8u
#define ENET_QOS_RX_FLUSH0_SHIFT                 3
#define ENET_QOS_RX_FLUSH1_MASK                  0x10u
#define ENET_QOS_RX_FLUSH1_SHIFT                 4
#define ENET_QOS_RX_FLUSH2_MASK                  0x20u
#define ENET_QOS_RX_FLUSH2_SHIFT                 5
/* RMON_T_DROP Bit Fields */
/* RMON_T_PACKETS Bit Fields */
#define ENET_RMON_T_PACKETS_TXPKTS_MASK          0xFFFFu
#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         0
#define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
/* RMON_T_BC_PKT Bit Fields */
#define ENET_RMON_T_BC_PKT_TXPKTS_MASK           0xFFFFu
#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          0
#define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
/* RMON_T_MC_PKT Bit Fields */
#define ENET_RMON_T_MC_PKT_TXPKTS_MASK           0xFFFFu
#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          0
#define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
/* RMON_T_CRC_ALIGN Bit Fields */
#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        0xFFFFu
#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       0
#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
/* RMON_T_UNDERSIZE Bit Fields */
#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        0xFFFFu
#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       0
#define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
/* RMON_T_OVERSIZE Bit Fields */
#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         0xFFFFu
#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        0
#define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
/* RMON_T_FRAG Bit Fields */
#define ENET_RMON_T_FRAG_TXPKTS_MASK             0xFFFFu
#define ENET_RMON_T_FRAG_TXPKTS_SHIFT            0
#define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
/* RMON_T_JAB Bit Fields */
#define ENET_RMON_T_JAB_TXPKTS_MASK              0xFFFFu
#define ENET_RMON_T_JAB_TXPKTS_SHIFT             0
#define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
/* RMON_T_COL Bit Fields */
#define ENET_RMON_T_COL_TXPKTS_MASK              0xFFFFu
#define ENET_RMON_T_COL_TXPKTS_SHIFT             0
#define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
/* RMON_T_P64 Bit Fields */
#define ENET_RMON_T_P64_TXPKTS_MASK              0xFFFFu
#define ENET_RMON_T_P64_TXPKTS_SHIFT             0
#define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
/* RMON_T_P65TO127 Bit Fields */
#define ENET_RMON_T_P65TO127_TXPKTS_MASK         0xFFFFu
#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        0
#define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
/* RMON_T_P128TO255 Bit Fields */
#define ENET_RMON_T_P128TO255_TXPKTS_MASK        0xFFFFu
#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       0
#define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
/* RMON_T_P256TO511 Bit Fields */
#define ENET_RMON_T_P256TO511_TXPKTS_MASK        0xFFFFu
#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       0
#define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
/* RMON_T_P512TO1023 Bit Fields */
#define ENET_RMON_T_P512TO1023_TXPKTS_MASK       0xFFFFu
#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      0
#define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
/* RMON_T_P1024TO2047 Bit Fields */
#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      0xFFFFu
#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     0
#define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
/* RMON_T_P_GTE2048 Bit Fields */
#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        0xFFFFu
#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       0
#define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
/* RMON_T_OCTETS Bit Fields */
#define ENET_RMON_T_OCTETS_TXOCTS_MASK           0xFFFFFFFFu
#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          0
#define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
/* IEEE_T_DROP Bit Fields */
/* IEEE_T_FRAME_OK Bit Fields */
#define ENET_IEEE_T_FRAME_OK_COUNT_MASK          0xFFFFu
#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         0
#define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
/* IEEE_T_1COL Bit Fields */
#define ENET_IEEE_T_1COL_COUNT_MASK              0xFFFFu
#define ENET_IEEE_T_1COL_COUNT_SHIFT             0
#define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
/* IEEE_T_MCOL Bit Fields */
#define ENET_IEEE_T_MCOL_COUNT_MASK              0xFFFFu
#define ENET_IEEE_T_MCOL_COUNT_SHIFT             0
#define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
/* IEEE_T_DEF Bit Fields */
#define ENET_IEEE_T_DEF_COUNT_MASK               0xFFFFu
#define ENET_IEEE_T_DEF_COUNT_SHIFT              0
#define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
/* IEEE_T_LCOL Bit Fields */
#define ENET_IEEE_T_LCOL_COUNT_MASK              0xFFFFu
#define ENET_IEEE_T_LCOL_COUNT_SHIFT             0
#define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
/* IEEE_T_EXCOL Bit Fields */
#define ENET_IEEE_T_EXCOL_COUNT_MASK             0xFFFFu
#define ENET_IEEE_T_EXCOL_COUNT_SHIFT            0
#define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
/* IEEE_T_MACERR Bit Fields */
#define ENET_IEEE_T_MACERR_COUNT_MASK            0xFFFFu
#define ENET_IEEE_T_MACERR_COUNT_SHIFT           0
#define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
/* IEEE_T_CSERR Bit Fields */
#define ENET_IEEE_T_CSERR_COUNT_MASK             0xFFFFu
#define ENET_IEEE_T_CSERR_COUNT_SHIFT            0
#define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
/* IEEE_T_SQE Bit Fields */
#define ENET_IEEE_T_SQE_COUNT_MASK               0xFFFFu
#define ENET_IEEE_T_SQE_COUNT_SHIFT              0
#define ENET_IEEE_T_SQE_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_SQE_COUNT_SHIFT))&ENET_IEEE_T_SQE_COUNT_MASK)
/* IEEE_T_FDXFC Bit Fields */
#define ENET_IEEE_T_FDXFC_COUNT_MASK             0xFFFFu
#define ENET_IEEE_T_FDXFC_COUNT_SHIFT            0
#define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
/* IEEE_T_OCTETS_OK Bit Fields */
#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        0
#define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
/* RMON_R_PACKETS Bit Fields */
#define ENET_RMON_R_PACKETS_COUNT_MASK           0xFFFFu
#define ENET_RMON_R_PACKETS_COUNT_SHIFT          0
#define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
/* RMON_R_BC_PKT Bit Fields */
#define ENET_RMON_R_BC_PKT_COUNT_MASK            0xFFFFu
#define ENET_RMON_R_BC_PKT_COUNT_SHIFT           0
#define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
/* RMON_R_MC_PKT Bit Fields */
#define ENET_RMON_R_MC_PKT_COUNT_MASK            0xFFFFu
#define ENET_RMON_R_MC_PKT_COUNT_SHIFT           0
#define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
/* RMON_R_CRC_ALIGN Bit Fields */
#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         0xFFFFu
#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        0
#define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
/* RMON_R_UNDERSIZE Bit Fields */
#define ENET_RMON_R_UNDERSIZE_COUNT_MASK         0xFFFFu
#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        0
#define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
/* RMON_R_OVERSIZE Bit Fields */
#define ENET_RMON_R_OVERSIZE_COUNT_MASK          0xFFFFu
#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         0
#define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
/* RMON_R_FRAG Bit Fields */
#define ENET_RMON_R_FRAG_COUNT_MASK              0xFFFFu
#define ENET_RMON_R_FRAG_COUNT_SHIFT             0
#define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
/* RMON_R_JAB Bit Fields */
#define ENET_RMON_R_JAB_COUNT_MASK               0xFFFFu
#define ENET_RMON_R_JAB_COUNT_SHIFT              0
#define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
/* RMON_R_RESVD_0 Bit Fields */
/* RMON_R_P64 Bit Fields */
#define ENET_RMON_R_P64_COUNT_MASK               0xFFFFu
#define ENET_RMON_R_P64_COUNT_SHIFT              0
#define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
/* RMON_R_P65TO127 Bit Fields */
#define ENET_RMON_R_P65TO127_COUNT_MASK          0xFFFFu
#define ENET_RMON_R_P65TO127_COUNT_SHIFT         0
#define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
/* RMON_R_P128TO255 Bit Fields */
#define ENET_RMON_R_P128TO255_COUNT_MASK         0xFFFFu
#define ENET_RMON_R_P128TO255_COUNT_SHIFT        0
#define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
/* RMON_R_P256TO511 Bit Fields */
#define ENET_RMON_R_P256TO511_COUNT_MASK         0xFFFFu
#define ENET_RMON_R_P256TO511_COUNT_SHIFT        0
#define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
/* RMON_R_P512TO1023 Bit Fields */
#define ENET_RMON_R_P512TO1023_COUNT_MASK        0xFFFFu
#define ENET_RMON_R_P512TO1023_COUNT_SHIFT       0
#define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
/* RMON_R_P1024TO2047 Bit Fields */
#define ENET_RMON_R_P1024TO2047_COUNT_MASK       0xFFFFu
#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      0
#define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
/* RMON_R_P_GTE2048 Bit Fields */
#define ENET_RMON_R_P_GTE2048_COUNT_MASK         0xFFFFu
#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        0
#define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
/* RMON_R_OCTETS Bit Fields */
#define ENET_RMON_R_OCTETS_COUNT_MASK            0xFFFFFFFFu
#define ENET_RMON_R_OCTETS_COUNT_SHIFT           0
#define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
/* IEEE_R_DROP Bit Fields */
#define ENET_IEEE_R_DROP_COUNT_MASK              0xFFFFu
#define ENET_IEEE_R_DROP_COUNT_SHIFT             0
#define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
/* IEEE_R_FRAME_OK Bit Fields */
#define ENET_IEEE_R_FRAME_OK_COUNT_MASK          0xFFFFu
#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         0
#define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
/* IEEE_R_CRC Bit Fields */
#define ENET_IEEE_R_CRC_COUNT_MASK               0xFFFFu
#define ENET_IEEE_R_CRC_COUNT_SHIFT              0
#define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
/* IEEE_R_ALIGN Bit Fields */
#define ENET_IEEE_R_ALIGN_COUNT_MASK             0xFFFFu
#define ENET_IEEE_R_ALIGN_COUNT_SHIFT            0
#define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
/* IEEE_R_MACERR Bit Fields */
#define ENET_IEEE_R_MACERR_COUNT_MASK            0xFFFFu
#define ENET_IEEE_R_MACERR_COUNT_SHIFT           0
#define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
/* IEEE_R_FDXFC Bit Fields */
#define ENET_IEEE_R_FDXFC_COUNT_MASK             0xFFFFu
#define ENET_IEEE_R_FDXFC_COUNT_SHIFT            0
#define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
/* IEEE_R_OCTETS_OK Bit Fields */
#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        0
#define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
/* ATCR Bit Fields */
#define ENET_ATCR_EN_MASK                        0x1u
#define ENET_ATCR_EN_SHIFT                       0
#define ENET_ATCR_OFFEN_MASK                     0x4u
#define ENET_ATCR_OFFEN_SHIFT                    2
#define ENET_ATCR_OFFRST_MASK                    0x8u
#define ENET_ATCR_OFFRST_SHIFT                   3
#define ENET_ATCR_PEREN_MASK                     0x10u
#define ENET_ATCR_PEREN_SHIFT                    4
#define ENET_ATCR_PINPER_MASK                    0x80u
#define ENET_ATCR_PINPER_SHIFT                   7
#define ENET_ATCR_RESTART_MASK                   0x200u
#define ENET_ATCR_RESTART_SHIFT                  9
#define ENET_ATCR_CAPTURE_MASK                   0x800u
#define ENET_ATCR_CAPTURE_SHIFT                  11
#define ENET_ATCR_SLAVE_MASK                     0x2000u
#define ENET_ATCR_SLAVE_SHIFT                    13
/* ATVR Bit Fields */
#define ENET_ATVR_ATIME_MASK                     0xFFFFFFFFu
#define ENET_ATVR_ATIME_SHIFT                    0
#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
/* ATOFF Bit Fields */
#define ENET_ATOFF_OFFSET_MASK                   0xFFFFFFFFu
#define ENET_ATOFF_OFFSET_SHIFT                  0
#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
/* ATPER Bit Fields */
#define ENET_ATPER_PERIOD_MASK                   0xFFFFFFFFu
#define ENET_ATPER_PERIOD_SHIFT                  0
#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
/* ATCOR Bit Fields */
#define ENET_ATCOR_COR_MASK                      0x7FFFFFFFu
#define ENET_ATCOR_COR_SHIFT                     0
#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
/* ATINC Bit Fields */
#define ENET_ATINC_INC_MASK                      0x7Fu
#define ENET_ATINC_INC_SHIFT                     0
#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
#define ENET_ATINC_INC_CORR_MASK                 0x7F00u
#define ENET_ATINC_INC_CORR_SHIFT                8
#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
/* ATSTMP Bit Fields */
#define ENET_ATSTMP_TIMESTAMP_MASK               0xFFFFFFFFu
#define ENET_ATSTMP_TIMESTAMP_SHIFT              0
#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
/* TGSR Bit Fields */
#define ENET_TGSR_TF0_MASK                       0x1u
#define ENET_TGSR_TF0_SHIFT                      0
#define ENET_TGSR_TF1_MASK                       0x2u
#define ENET_TGSR_TF1_SHIFT                      1
#define ENET_TGSR_TF2_MASK                       0x4u
#define ENET_TGSR_TF2_SHIFT                      2
#define ENET_TGSR_TF3_MASK                       0x8u
#define ENET_TGSR_TF3_SHIFT                      3
/* TCSR Bit Fields */
#define ENET_TCSR_TDRE_MASK                      0x1u
#define ENET_TCSR_TDRE_SHIFT                     0
#define ENET_TCSR_TMODE_MASK                     0x3Cu
#define ENET_TCSR_TMODE_SHIFT                    2
#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
#define ENET_TCSR_TIE_MASK                       0x40u
#define ENET_TCSR_TIE_SHIFT                      6
#define ENET_TCSR_TF_MASK                        0x80u
#define ENET_TCSR_TF_SHIFT                       7
/* The count of ENET_TCSR */
#define ENET_TCSR_COUNT                          (4U)
/* TCCR Bit Fields */
#define ENET_TCCR_TCC_MASK                       0xFFFFFFFFu
#define ENET_TCCR_TCC_SHIFT                      0
#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
/* The count of ENET_TCCR */
#define ENET_TCCR_COUNT                          (4U)

/*!
 * @}
 */ /* end of group ENET_Register_Masks */

/* ENET - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__ENET0 base address */
#define CONNECTIVITY__ENET0_BASE                               (0x5B040000u)
/** Peripheral CONNECTIVITY__ENET0 base pointer */
#define CONNECTIVITY__ENET0                                    ((ENET_Type *)CONNECTIVITY__ENET0_BASE)
/** Peripheral CONNECTIVITY__ENET1 base address */
#define CONNECTIVITY__ENET1_BASE                               (0x5B050000u)
/** Peripheral CONNECTIVITY__ENET1 base pointer */
#define CONNECTIVITY__ENET1                                    ((ENET_Type *)CONNECTIVITY__ENET1_BASE)
/** Array initializer of ENET peripheral base addresses */
#define ENET_BASE_ADDRS                          { CONNECTIVITY__ENET0_BASE, CONNECTIVITY__ENET1_BASE }
/** Array initializer of ENET peripheral base pointers */
#define ENET_BASE_PTRS                           { CONNECTIVITY__ENET0, CONNECTIVITY__ENET1 }
/** Interrupt vectors for the ENET peripheral type */
#define ENET_Transmit_IRQS                       { NotAvail_IRQn, NotAvail_IRQn }
#define ENET_Receive_IRQS                        { NotAvail_IRQn, NotAvail_IRQn }
#define ENET_Error_IRQS                          { NotAvail_IRQn, NotAvail_IRQn }
#define ENET_1588_Timer_IRQS                     { NotAvail_IRQn, NotAvail_IRQn }
/* ENET Buffer Descriptor and Buffer Address Alignment. */
#define ENET_BUFF_ALIGNMENT                      (64U)

/*!
 * @}
 */ /* end of group ENET_Peripheral */


/* ----------------------------------------------------------------------------
   -- ESAI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ESAI_Peripheral_Access_Layer ESAI Peripheral Access Layer
 * @{
 */

/** ESAI - Register Layout Typedef */
typedef struct {
  __O  uint32_t ETDR;                              /**< ESAI Transmit Data Register, offset: 0x0 */
  __I  uint32_t ERDR;                              /**< ESAI Receive Data Register, offset: 0x4 */
  __IO uint32_t ECR;                               /**< ESAI Control Register, offset: 0x8 */
  __I  uint32_t ESR;                               /**< ESAI Status Register, offset: 0xC */
  __IO uint32_t TFCR;                              /**< Transmit FIFO Configuration Register, offset: 0x10 */
  __I  uint32_t TFSR;                              /**< Transmit FIFO Status Register, offset: 0x14 */
  __IO uint32_t RFCR;                              /**< Receive FIFO Configuration Register, offset: 0x18 */
  __I  uint32_t RFSR;                              /**< Receive FIFO Status Register, offset: 0x1C */
       uint8_t RESERVED_0[96];
  __O  uint32_t TX[6];                             /**< Transmit Data Register n, array offset: 0x80, array step: 0x4 */
  __O  uint32_t TSR;                               /**< ESAI Transmit Slot Register, offset: 0x98 */
       uint8_t RESERVED_1[4];
  __I  uint32_t RX[4];                             /**< Receive Data Register n, array offset: 0xA0, array step: 0x4 */
       uint8_t RESERVED_2[28];
  __I  uint32_t SAISR;                             /**< Serial Audio Interface Status Register, offset: 0xCC */
  __IO uint32_t SAICR;                             /**< Serial Audio Interface Control Register, offset: 0xD0 */
  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xD4 */
  __IO uint32_t TCCR;                              /**< Transmit Clock Control Register, offset: 0xD8 */
  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0xDC */
  __IO uint32_t RCCR;                              /**< Receive Clock Control Register, offset: 0xE0 */
  __IO uint32_t TSMA;                              /**< Transmit Slot Mask Register A, offset: 0xE4 */
  __IO uint32_t TSMB;                              /**< Transmit Slot Mask Register B, offset: 0xE8 */
  __IO uint32_t RSMA;                              /**< Receive Slot Mask Register A, offset: 0xEC */
  __IO uint32_t RSMB;                              /**< Receive Slot Mask Register B, offset: 0xF0 */
  __IO uint32_t PDRC;                              /**< Port C Data Register, offset: 0xF4 */
  __IO uint32_t PRRC;                              /**< Port C Direction Register, offset: 0xF8 */
  __IO uint32_t PCRC;                              /**< Port C Control Register, offset: 0xFC */
} ESAI_Type;

/* ----------------------------------------------------------------------------
   -- ESAI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ESAI_Register_Masks ESAI Register Masks
 * @{
 */

/*! @name ETDR - ESAI Transmit Data Register */
/*! @{ */
#define ESAI_ETDR_ETDR_MASK                      (0xFFFFFFFFU)
#define ESAI_ETDR_ETDR_SHIFT                     (0U)
#define ESAI_ETDR_ETDR(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_ETDR_ETDR_SHIFT)) & ESAI_ETDR_ETDR_MASK)
/*! @} */

/*! @name ERDR - ESAI Receive Data Register */
/*! @{ */
#define ESAI_ERDR_ERDR_MASK                      (0xFFFFFFFFU)
#define ESAI_ERDR_ERDR_SHIFT                     (0U)
#define ESAI_ERDR_ERDR(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_ERDR_ERDR_SHIFT)) & ESAI_ERDR_ERDR_MASK)
/*! @} */

/*! @name ECR - ESAI Control Register */
/*! @{ */
#define ESAI_ECR_ESAIEN_MASK                     (0x1U)
#define ESAI_ECR_ESAIEN_SHIFT                    (0U)
/*! ESAIEN - ESAIEN
 *  0b0..ESAI disabled.
 *  0b1..ESAI enabled.
 */
#define ESAI_ECR_ESAIEN(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ESAIEN_SHIFT)) & ESAI_ECR_ESAIEN_MASK)
#define ESAI_ECR_ERST_MASK                       (0x2U)
#define ESAI_ECR_ERST_SHIFT                      (1U)
/*! ERST - ERST
 *  0b0..ESAI not reset.
 *  0b1..ESAI reset.
 */
#define ESAI_ECR_ERST(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERST_SHIFT)) & ESAI_ECR_ERST_MASK)
#define ESAI_ECR_ERO_MASK                        (0x10000U)
#define ESAI_ECR_ERO_SHIFT                       (16U)
/*! ERO - ERO
 *  0b0..HCKR pin has normal function.
 *  0b1..EXTAL driven onto HCKR pin.
 */
#define ESAI_ECR_ERO(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERO_SHIFT)) & ESAI_ECR_ERO_MASK)
#define ESAI_ECR_ERI_MASK                        (0x20000U)
#define ESAI_ECR_ERI_SHIFT                       (17U)
/*! ERI - ERI
 *  0b0..HCKR pin has normal function.
 *  0b1..EXTAL muxed into HCKR input.
 */
#define ESAI_ECR_ERI(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERI_SHIFT)) & ESAI_ECR_ERI_MASK)
#define ESAI_ECR_ETO_MASK                        (0x40000U)
#define ESAI_ECR_ETO_SHIFT                       (18U)
/*! ETO - ETO
 *  0b0..HCKT pin has normal function.
 *  0b1..EXTAL driven onto HCKT pin.
 */
#define ESAI_ECR_ETO(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETO_SHIFT)) & ESAI_ECR_ETO_MASK)
#define ESAI_ECR_ETI_MASK                        (0x80000U)
#define ESAI_ECR_ETI_SHIFT                       (19U)
/*! ETI - ETI
 *  0b0..HCKT pin has normal function.
 *  0b1..EXTAL muxed into HCKT input.
 */
#define ESAI_ECR_ETI(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETI_SHIFT)) & ESAI_ECR_ETI_MASK)
/*! @} */

/*! @name ESR - ESAI Status Register */
/*! @{ */
#define ESAI_ESR_RD_MASK                         (0x1U)
#define ESAI_ESR_RD_SHIFT                        (0U)
/*! RD - RD
 *  0b0..RD is not the highest priority active interrupt.
 *  0b1..RD is the highest priority active interrupt.
 */
#define ESAI_ESR_RD(x)                           (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RD_SHIFT)) & ESAI_ESR_RD_MASK)
#define ESAI_ESR_RED_MASK                        (0x2U)
#define ESAI_ESR_RED_SHIFT                       (1U)
/*! RED - RED
 *  0b0..RED is not the highest priority active interrupt.
 *  0b1..RED is the highest priority active interrupt.
 */
#define ESAI_ESR_RED(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RED_SHIFT)) & ESAI_ESR_RED_MASK)
#define ESAI_ESR_RDE_MASK                        (0x4U)
#define ESAI_ESR_RDE_SHIFT                       (2U)
/*! RDE - RDE
 *  0b0..RDE is not the highest priority active interrupt.
 *  0b1..RDE is the highest priority active interrupt.
 */
#define ESAI_ESR_RDE(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RDE_SHIFT)) & ESAI_ESR_RDE_MASK)
#define ESAI_ESR_RLS_MASK                        (0x8U)
#define ESAI_ESR_RLS_SHIFT                       (3U)
/*! RLS - RLS
 *  0b0..RLS is not the highest priority active interrupt.
 *  0b1..RLS is the highest priority active interrupt.
 */
#define ESAI_ESR_RLS(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RLS_SHIFT)) & ESAI_ESR_RLS_MASK)
#define ESAI_ESR_TD_MASK                         (0x10U)
#define ESAI_ESR_TD_SHIFT                        (4U)
/*! TD - TD
 *  0b0..TD is not the highest priority active interrupt.
 *  0b1..TD is the highest priority active interrupt.
 */
#define ESAI_ESR_TD(x)                           (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TD_SHIFT)) & ESAI_ESR_TD_MASK)
#define ESAI_ESR_TED_MASK                        (0x20U)
#define ESAI_ESR_TED_SHIFT                       (5U)
/*! TED - TED
 *  0b0..TED is not the highest priority active interrupt.
 *  0b1..TED is the highest priority active interrupt.
 */
#define ESAI_ESR_TED(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TED_SHIFT)) & ESAI_ESR_TED_MASK)
#define ESAI_ESR_TDE_MASK                        (0x40U)
#define ESAI_ESR_TDE_SHIFT                       (6U)
/*! TDE - TDE
 *  0b0..TDE is not the highest priority active interrupt.
 *  0b1..TDE is the highest priority active interrupt.
 */
#define ESAI_ESR_TDE(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TDE_SHIFT)) & ESAI_ESR_TDE_MASK)
#define ESAI_ESR_TLS_MASK                        (0x80U)
#define ESAI_ESR_TLS_SHIFT                       (7U)
/*! TLS - TLS
 *  0b0..TLS is not the highest priority active interrupt.
 *  0b1..TLS is the highest priority active interrupt.
 */
#define ESAI_ESR_TLS(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TLS_SHIFT)) & ESAI_ESR_TLS_MASK)
#define ESAI_ESR_TFE_MASK                        (0x100U)
#define ESAI_ESR_TFE_SHIFT                       (8U)
/*! TFE - TFE
 *  0b0..Number of empty slots in Transmit FIFO less than Transmit FIFO watermark.
 *  0b1..Number of empty slots in Transmit FIFO is equal to or greater than Transmit FIFO watermark.
 */
#define ESAI_ESR_TFE(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TFE_SHIFT)) & ESAI_ESR_TFE_MASK)
#define ESAI_ESR_RFF_MASK                        (0x200U)
#define ESAI_ESR_RFF_SHIFT                       (9U)
/*! RFF - RFF
 *  0b0..Number of words in Receive FIFO less than Receive FIFO watermark.
 *  0b1..Number of words in Receive FIFO is equal to or greater than Receive FIFO watermark.
 */
#define ESAI_ESR_RFF(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RFF_SHIFT)) & ESAI_ESR_RFF_MASK)
#define ESAI_ESR_TINIT_MASK                      (0x400U)
#define ESAI_ESR_TINIT_SHIFT                     (10U)
/*! TINIT - TINIT
 *  0b0..Transmitter has finished initializing the Transmit Data Registers (or Transmit FIFO is not enabled or Transmit Initialization is not enabled).
 *  0b1..Transmitter has not finished initializing the Transmit Data Registers.
 */
#define ESAI_ESR_TINIT(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TINIT_SHIFT)) & ESAI_ESR_TINIT_MASK)
/*! @} */

/*! @name TFCR - Transmit FIFO Configuration Register */
/*! @{ */
#define ESAI_TFCR_TFE_MASK                       (0x1U)
#define ESAI_TFCR_TFE_SHIFT                      (0U)
/*! TFE - TFE
 *  0b0..Transmit FIFO disabled.
 *  0b1..Transmit FIFO enabled.
 */
#define ESAI_TFCR_TFE(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFE_SHIFT)) & ESAI_TFCR_TFE_MASK)
#define ESAI_TFCR_TFR_MASK                       (0x2U)
#define ESAI_TFCR_TFR_SHIFT                      (1U)
/*! TFR - TFR
 *  0b0..Transmit FIFO not reset.
 *  0b1..Transmit FIFO reset.
 */
#define ESAI_TFCR_TFR(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFR_SHIFT)) & ESAI_TFCR_TFR_MASK)
#define ESAI_TFCR_TE0_MASK                       (0x4U)
#define ESAI_TFCR_TE0_SHIFT                      (2U)
/*! TE0 - TE0
 *  0b0..Transmitter #0 is not using the Transmit FIFO.
 *  0b1..Transmitter #0 is using the Transmit FIFO.
 */
#define ESAI_TFCR_TE0(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE0_SHIFT)) & ESAI_TFCR_TE0_MASK)
#define ESAI_TFCR_TE1_MASK                       (0x8U)
#define ESAI_TFCR_TE1_SHIFT                      (3U)
/*! TE1 - TE1
 *  0b0..Transmitter #1 is not using the Transmit FIFO.
 *  0b1..Transmitter #1 is using the Transmit FIFO.
 */
#define ESAI_TFCR_TE1(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE1_SHIFT)) & ESAI_TFCR_TE1_MASK)
#define ESAI_TFCR_TE2_MASK                       (0x10U)
#define ESAI_TFCR_TE2_SHIFT                      (4U)
/*! TE2 - TE2
 *  0b0..Transmitter #2 is not using the Transmit FIFO.
 *  0b1..Transmitter #2 is using the Transmit FIFO.
 */
#define ESAI_TFCR_TE2(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE2_SHIFT)) & ESAI_TFCR_TE2_MASK)
#define ESAI_TFCR_TE3_MASK                       (0x20U)
#define ESAI_TFCR_TE3_SHIFT                      (5U)
/*! TE3 - TE3
 *  0b0..Transmitter #3 is not using the Transmit FIFO.
 *  0b1..Transmitter #3 is using the Transmit FIFO.
 */
#define ESAI_TFCR_TE3(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE3_SHIFT)) & ESAI_TFCR_TE3_MASK)
#define ESAI_TFCR_TE4_MASK                       (0x40U)
#define ESAI_TFCR_TE4_SHIFT                      (6U)
/*! TE4 - TE4
 *  0b0..Transmitter #4 is not using the Transmit FIFO.
 *  0b1..Transmitter #4 is using the Transmit FIFO.
 */
#define ESAI_TFCR_TE4(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE4_SHIFT)) & ESAI_TFCR_TE4_MASK)
#define ESAI_TFCR_TE5_MASK                       (0x80U)
#define ESAI_TFCR_TE5_SHIFT                      (7U)
/*! TE5 - TE5
 *  0b0..Transmitter #5 is not using the Transmit FIFO.
 *  0b1..Transmitter #5 is using the Transmit FIFO.
 */
#define ESAI_TFCR_TE5(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE5_SHIFT)) & ESAI_TFCR_TE5_MASK)
#define ESAI_TFCR_TFWM_MASK                      (0xFF00U)
#define ESAI_TFCR_TFWM_SHIFT                     (8U)
#define ESAI_TFCR_TFWM(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFWM_SHIFT)) & ESAI_TFCR_TFWM_MASK)
#define ESAI_TFCR_TWA_MASK                       (0x70000U)
#define ESAI_TFCR_TWA_SHIFT                      (16U)
/*! TWA - TWA
 *  0b000..MSB of data is bit 31. Data bits 7-0 are ignored when passed to transmit shift register.
 *  0b001..MSB of data is bit 27. Data bits 3-0 are ignored when passed to transmit shift register.
 *  0b010..MSB of data is bit 23.
 *  0b011..MSB of data is bit 19. Bottom 4 bits of transmit shift register are zeroed.
 *  0b100..MSB of data is bit 15. Bottom 8 bits of transmit shift register are zeroed.
 *  0b101..MSB of data is bit 11. Bottom 12 bits of transmit shift register are zeroed.
 *  0b110..MSB of data is bit 7. Bottom 16 bits of transmit shift register are zeroed.
 *  0b111..MSB of data is bit 3. Bottom 20 bits of transmit shift register are zeroed.
 */
#define ESAI_TFCR_TWA(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TWA_SHIFT)) & ESAI_TFCR_TWA_MASK)
#define ESAI_TFCR_TIEN_MASK                      (0x80000U)
#define ESAI_TFCR_TIEN_SHIFT                     (19U)
/*! TIEN - TIEN
 *  0b0..Transmit Data Registers are not initialized from the FIFO once the Transmit FIFO is enabled. Software must manually initialize the Transmit Data Registers separately.
 *  0b1..Transmit Data Registers are initialized from the FIFO once the Transmit FIFO is enabled.
 */
#define ESAI_TFCR_TIEN(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TIEN_SHIFT)) & ESAI_TFCR_TIEN_MASK)
/*! @} */

/*! @name TFSR - Transmit FIFO Status Register */
/*! @{ */
#define ESAI_TFSR_TFCNT_MASK                     (0xFFU)
#define ESAI_TFSR_TFCNT_SHIFT                    (0U)
#define ESAI_TFSR_TFCNT(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_TFCNT_SHIFT)) & ESAI_TFSR_TFCNT_MASK)
#define ESAI_TFSR_NTFI_MASK                      (0x700U)
#define ESAI_TFSR_NTFI_SHIFT                     (8U)
/*! NTFI - NTFI
 *  0b000..Transmitter #0 receives next word written to the Transmit FIFO.
 *  0b001..Transmitter #1 receives next word written to the Transmit FIFO.
 *  0b010..Transmitter #2 receives next word written to the Transmit FIFO.
 *  0b011..Transmitter #3 receives next word written to the Transmit FIFO.
 *  0b100..Transmitter #4 receives next word written to the Transmit FIFO.
 *  0b101..Transmitter #5 receives next word written to the Transmit FIFO.
 *  0b110..Reserved.
 *  0b111..Reserved.
 */
#define ESAI_TFSR_NTFI(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFI_SHIFT)) & ESAI_TFSR_NTFI_MASK)
#define ESAI_TFSR_NTFO_MASK                      (0x7000U)
#define ESAI_TFSR_NTFO_SHIFT                     (12U)
/*! NTFO - NTFO
 *  0b000..Transmitter #0 receives next word from the Transmit FIFO.
 *  0b001..Transmitter #1 receives next word from the Transmit FIFO.
 *  0b010..Transmitter #2 receives next word from the Transmit FIFO.
 *  0b011..Transmitter #3 receives next word from the Transmit FIFO.
 *  0b100..Transmitter #4 receives next word from the Transmit FIFO.
 *  0b101..Transmitter #5 receives next word from the Transmit FIFO.
 *  0b110..Reserved.
 *  0b111..Reserved.
 */
#define ESAI_TFSR_NTFO(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFO_SHIFT)) & ESAI_TFSR_NTFO_MASK)
/*! @} */

/*! @name RFCR - Receive FIFO Configuration Register */
/*! @{ */
#define ESAI_RFCR_RFE_MASK                       (0x1U)
#define ESAI_RFCR_RFE_SHIFT                      (0U)
/*! RFE - RFE
 *  0b0..Receive FIFO disabled.
 *  0b1..Receive FIFO enabled.
 */
#define ESAI_RFCR_RFE(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFE_SHIFT)) & ESAI_RFCR_RFE_MASK)
#define ESAI_RFCR_RFR_MASK                       (0x2U)
#define ESAI_RFCR_RFR_SHIFT                      (1U)
/*! RFR - RFR
 *  0b0..Receive FIFO not reset.
 *  0b1..Receive FIFO reset.
 */
#define ESAI_RFCR_RFR(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFR_SHIFT)) & ESAI_RFCR_RFR_MASK)
#define ESAI_RFCR_RE0_MASK                       (0x4U)
#define ESAI_RFCR_RE0_SHIFT                      (2U)
/*! RE0 - RE0
 *  0b0..Receiver #0 is not using the Receive FIFO.
 *  0b1..Receiver #0 is using the Receive FIFO.
 */
#define ESAI_RFCR_RE0(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE0_SHIFT)) & ESAI_RFCR_RE0_MASK)
#define ESAI_RFCR_RE1_MASK                       (0x8U)
#define ESAI_RFCR_RE1_SHIFT                      (3U)
/*! RE1 - RE1
 *  0b0..Receiver #1 is not using the Receive FIFO.
 *  0b1..Receiver #1 is using the Receive FIFO.
 */
#define ESAI_RFCR_RE1(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE1_SHIFT)) & ESAI_RFCR_RE1_MASK)
#define ESAI_RFCR_RE2_MASK                       (0x10U)
#define ESAI_RFCR_RE2_SHIFT                      (4U)
/*! RE2 - RE2
 *  0b0..Receiver #2 is not using the Receive FIFO.
 *  0b1..Receiver #2 is using the Receive FIFO.
 */
#define ESAI_RFCR_RE2(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE2_SHIFT)) & ESAI_RFCR_RE2_MASK)
#define ESAI_RFCR_RE3_MASK                       (0x20U)
#define ESAI_RFCR_RE3_SHIFT                      (5U)
/*! RE3 - RE3
 *  0b0..Receiver #3 is not using the Receive FIFO.
 *  0b1..Receiver #3 is using the Receive FIFO.
 */
#define ESAI_RFCR_RE3(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE3_SHIFT)) & ESAI_RFCR_RE3_MASK)
#define ESAI_RFCR_RFWM_MASK                      (0xFF00U)
#define ESAI_RFCR_RFWM_SHIFT                     (8U)
#define ESAI_RFCR_RFWM(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFWM_SHIFT)) & ESAI_RFCR_RFWM_MASK)
#define ESAI_RFCR_RWA_MASK                       (0x70000U)
#define ESAI_RFCR_RWA_SHIFT                      (16U)
/*! RWA - RWA
 *  0b000..MSB of data is at bit 31. Data bits 7-0 are zeroed.
 *  0b001..MSB of data is at bit 27. Data bits 3-0 are zeroed.
 *  0b010..MSB of data is at bit 23.
 *  0b011..MSB of data is at bit 19. Data bits 3-0 from receive shift register are ignored.
 *  0b100..MSB of data is at bit 15. Data bits 7-0 from receive shift register are ignored.
 *  0b101..MSB of data is at bit 11. Data bits 11-0 from receive shift register are ignored.
 *  0b110..MSB of data is at bit 7. Data bits 15-0 from receive shift register are ignored.
 *  0b111..MSB of data is at bit 3. Data bits 19-0 from receive shift register are ignored.
 */
#define ESAI_RFCR_RWA(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RWA_SHIFT)) & ESAI_RFCR_RWA_MASK)
#define ESAI_RFCR_REXT_MASK                      (0x80000U)
#define ESAI_RFCR_REXT_SHIFT                     (19U)
/*! REXT - REXT
 *  0b0..Receive data is zero extended.
 *  0b1..Receive data is sign extended.
 */
#define ESAI_RFCR_REXT(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_REXT_SHIFT)) & ESAI_RFCR_REXT_MASK)
/*! @} */

/*! @name RFSR - Receive FIFO Status Register */
/*! @{ */
#define ESAI_RFSR_RFCNT_MASK                     (0xFFU)
#define ESAI_RFSR_RFCNT_SHIFT                    (0U)
#define ESAI_RFSR_RFCNT(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_RFCNT_SHIFT)) & ESAI_RFSR_RFCNT_MASK)
#define ESAI_RFSR_NRFO_MASK                      (0x300U)
#define ESAI_RFSR_NRFO_SHIFT                     (8U)
/*! NRFO - NRFO
 *  0b00..Receiver #0 returns next word from the Receive FIFO.
 *  0b01..Receiver #1 returns next word from the Receive FIFO.
 *  0b10..Receiver #2 returns next word from the Receive FIFO.
 *  0b11..Receiver #3 returns next word from the Receive FIFO.
 */
#define ESAI_RFSR_NRFO(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFO_SHIFT)) & ESAI_RFSR_NRFO_MASK)
#define ESAI_RFSR_NRFI_MASK                      (0x3000U)
#define ESAI_RFSR_NRFI_SHIFT                     (12U)
/*! NRFI - NRFI
 *  0b00..Receiver #0 returns next word to the Receive FIFO.
 *  0b01..Receiver #1 returns next word to the Receive FIFO.
 *  0b10..Receiver #2 returns next word to the Receive FIFO.
 *  0b11..Receiver #3 returns next word to the Receive FIFO.
 */
#define ESAI_RFSR_NRFI(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFI_SHIFT)) & ESAI_RFSR_NRFI_MASK)
/*! @} */

/*! @name TX - Transmit Data Register n */
/*! @{ */
#define ESAI_TX_TXn_MASK                         (0xFFFFFFU)
#define ESAI_TX_TXn_SHIFT                        (0U)
#define ESAI_TX_TXn(x)                           (((uint32_t)(((uint32_t)(x)) << ESAI_TX_TXn_SHIFT)) & ESAI_TX_TXn_MASK)
/*! @} */

/* The count of ESAI_TX */
#define ESAI_TX_COUNT                            (6U)

/*! @name TSR - ESAI Transmit Slot Register */
/*! @{ */
#define ESAI_TSR_TSR_MASK                        (0xFFFFFFU)
#define ESAI_TSR_TSR_SHIFT                       (0U)
#define ESAI_TSR_TSR(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TSR_TSR_SHIFT)) & ESAI_TSR_TSR_MASK)
/*! @} */

/*! @name RX - Receive Data Register n */
/*! @{ */
#define ESAI_RX_RXn_MASK                         (0xFFFFFFU)
#define ESAI_RX_RXn_SHIFT                        (0U)
#define ESAI_RX_RXn(x)                           (((uint32_t)(((uint32_t)(x)) << ESAI_RX_RXn_SHIFT)) & ESAI_RX_RXn_MASK)
/*! @} */

/* The count of ESAI_RX */
#define ESAI_RX_COUNT                            (4U)

/*! @name SAISR - Serial Audio Interface Status Register */
/*! @{ */
#define ESAI_SAISR_IF0_MASK                      (0x1U)
#define ESAI_SAISR_IF0_SHIFT                     (0U)
#define ESAI_SAISR_IF0(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF0_SHIFT)) & ESAI_SAISR_IF0_MASK)
#define ESAI_SAISR_IF1_MASK                      (0x2U)
#define ESAI_SAISR_IF1_SHIFT                     (1U)
#define ESAI_SAISR_IF1(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF1_SHIFT)) & ESAI_SAISR_IF1_MASK)
#define ESAI_SAISR_IF2_MASK                      (0x4U)
#define ESAI_SAISR_IF2_SHIFT                     (2U)
#define ESAI_SAISR_IF2(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF2_SHIFT)) & ESAI_SAISR_IF2_MASK)
#define ESAI_SAISR_RFS_MASK                      (0x40U)
#define ESAI_SAISR_RFS_SHIFT                     (6U)
#define ESAI_SAISR_RFS(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RFS_SHIFT)) & ESAI_SAISR_RFS_MASK)
#define ESAI_SAISR_ROE_MASK                      (0x80U)
#define ESAI_SAISR_ROE_SHIFT                     (7U)
#define ESAI_SAISR_ROE(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_ROE_SHIFT)) & ESAI_SAISR_ROE_MASK)
#define ESAI_SAISR_RDF_MASK                      (0x100U)
#define ESAI_SAISR_RDF_SHIFT                     (8U)
#define ESAI_SAISR_RDF(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RDF_SHIFT)) & ESAI_SAISR_RDF_MASK)
#define ESAI_SAISR_REDF_MASK                     (0x200U)
#define ESAI_SAISR_REDF_SHIFT                    (9U)
#define ESAI_SAISR_REDF(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_REDF_SHIFT)) & ESAI_SAISR_REDF_MASK)
#define ESAI_SAISR_RODF_MASK                     (0x400U)
#define ESAI_SAISR_RODF_SHIFT                    (10U)
#define ESAI_SAISR_RODF(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RODF_SHIFT)) & ESAI_SAISR_RODF_MASK)
#define ESAI_SAISR_TFS_MASK                      (0x2000U)
#define ESAI_SAISR_TFS_SHIFT                     (13U)
#define ESAI_SAISR_TFS(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TFS_SHIFT)) & ESAI_SAISR_TFS_MASK)
#define ESAI_SAISR_TUE_MASK                      (0x4000U)
#define ESAI_SAISR_TUE_SHIFT                     (14U)
#define ESAI_SAISR_TUE(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TUE_SHIFT)) & ESAI_SAISR_TUE_MASK)
#define ESAI_SAISR_TDE_MASK                      (0x8000U)
#define ESAI_SAISR_TDE_SHIFT                     (15U)
#define ESAI_SAISR_TDE(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TDE_SHIFT)) & ESAI_SAISR_TDE_MASK)
#define ESAI_SAISR_TEDE_MASK                     (0x10000U)
#define ESAI_SAISR_TEDE_SHIFT                    (16U)
#define ESAI_SAISR_TEDE(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TEDE_SHIFT)) & ESAI_SAISR_TEDE_MASK)
#define ESAI_SAISR_TODFE_MASK                    (0x20000U)
#define ESAI_SAISR_TODFE_SHIFT                   (17U)
#define ESAI_SAISR_TODFE(x)                      (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TODFE_SHIFT)) & ESAI_SAISR_TODFE_MASK)
/*! @} */

/*! @name SAICR - Serial Audio Interface Control Register */
/*! @{ */
#define ESAI_SAICR_OF0_MASK                      (0x1U)
#define ESAI_SAICR_OF0_SHIFT                     (0U)
#define ESAI_SAICR_OF0(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF0_SHIFT)) & ESAI_SAICR_OF0_MASK)
#define ESAI_SAICR_OF1_MASK                      (0x2U)
#define ESAI_SAICR_OF1_SHIFT                     (1U)
#define ESAI_SAICR_OF1(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF1_SHIFT)) & ESAI_SAICR_OF1_MASK)
#define ESAI_SAICR_OF2_MASK                      (0x4U)
#define ESAI_SAICR_OF2_SHIFT                     (2U)
#define ESAI_SAICR_OF2(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF2_SHIFT)) & ESAI_SAICR_OF2_MASK)
#define ESAI_SAICR_SYN_MASK                      (0x40U)
#define ESAI_SAICR_SYN_SHIFT                     (6U)
#define ESAI_SAICR_SYN(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_SYN_SHIFT)) & ESAI_SAICR_SYN_MASK)
#define ESAI_SAICR_TEBE_MASK                     (0x80U)
#define ESAI_SAICR_TEBE_SHIFT                    (7U)
#define ESAI_SAICR_TEBE(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_TEBE_SHIFT)) & ESAI_SAICR_TEBE_MASK)
#define ESAI_SAICR_ALC_MASK                      (0x100U)
#define ESAI_SAICR_ALC_SHIFT                     (8U)
#define ESAI_SAICR_ALC(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_ALC_SHIFT)) & ESAI_SAICR_ALC_MASK)
/*! @} */

/*! @name TCR - Transmit Control Register */
/*! @{ */
#define ESAI_TCR_TE0_MASK                        (0x1U)
#define ESAI_TCR_TE0_SHIFT                       (0U)
#define ESAI_TCR_TE0(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE0_SHIFT)) & ESAI_TCR_TE0_MASK)
#define ESAI_TCR_TE1_MASK                        (0x2U)
#define ESAI_TCR_TE1_SHIFT                       (1U)
#define ESAI_TCR_TE1(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE1_SHIFT)) & ESAI_TCR_TE1_MASK)
#define ESAI_TCR_TE2_MASK                        (0x4U)
#define ESAI_TCR_TE2_SHIFT                       (2U)
#define ESAI_TCR_TE2(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE2_SHIFT)) & ESAI_TCR_TE2_MASK)
#define ESAI_TCR_TE3_MASK                        (0x8U)
#define ESAI_TCR_TE3_SHIFT                       (3U)
#define ESAI_TCR_TE3(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE3_SHIFT)) & ESAI_TCR_TE3_MASK)
#define ESAI_TCR_TE4_MASK                        (0x10U)
#define ESAI_TCR_TE4_SHIFT                       (4U)
#define ESAI_TCR_TE4(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE4_SHIFT)) & ESAI_TCR_TE4_MASK)
#define ESAI_TCR_TE5_MASK                        (0x20U)
#define ESAI_TCR_TE5_SHIFT                       (5U)
#define ESAI_TCR_TE5(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE5_SHIFT)) & ESAI_TCR_TE5_MASK)
#define ESAI_TCR_TSHFD_MASK                      (0x40U)
#define ESAI_TCR_TSHFD_SHIFT                     (6U)
#define ESAI_TCR_TSHFD(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSHFD_SHIFT)) & ESAI_TCR_TSHFD_MASK)
#define ESAI_TCR_TWA_MASK                        (0x80U)
#define ESAI_TCR_TWA_SHIFT                       (7U)
#define ESAI_TCR_TWA(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TWA_SHIFT)) & ESAI_TCR_TWA_MASK)
#define ESAI_TCR_TMOD_MASK                       (0x300U)
#define ESAI_TCR_TMOD_SHIFT                      (8U)
#define ESAI_TCR_TMOD(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TMOD_SHIFT)) & ESAI_TCR_TMOD_MASK)
#define ESAI_TCR_TSWS_MASK                       (0x7C00U)
#define ESAI_TCR_TSWS_SHIFT                      (10U)
#define ESAI_TCR_TSWS(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSWS_SHIFT)) & ESAI_TCR_TSWS_MASK)
#define ESAI_TCR_TFSL_MASK                       (0x8000U)
#define ESAI_TCR_TFSL_SHIFT                      (15U)
#define ESAI_TCR_TFSL(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSL_SHIFT)) & ESAI_TCR_TFSL_MASK)
#define ESAI_TCR_TFSR_MASK                       (0x10000U)
#define ESAI_TCR_TFSR_SHIFT                      (16U)
#define ESAI_TCR_TFSR(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSR_SHIFT)) & ESAI_TCR_TFSR_MASK)
#define ESAI_TCR_PADC_MASK                       (0x20000U)
#define ESAI_TCR_PADC_SHIFT                      (17U)
#define ESAI_TCR_PADC(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_PADC_SHIFT)) & ESAI_TCR_PADC_MASK)
#define ESAI_TCR_TPR_MASK                        (0x80000U)
#define ESAI_TCR_TPR_SHIFT                       (19U)
#define ESAI_TCR_TPR(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TPR_SHIFT)) & ESAI_TCR_TPR_MASK)
#define ESAI_TCR_TEIE_MASK                       (0x100000U)
#define ESAI_TCR_TEIE_SHIFT                      (20U)
#define ESAI_TCR_TEIE(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEIE_SHIFT)) & ESAI_TCR_TEIE_MASK)
#define ESAI_TCR_TEDIE_MASK                      (0x200000U)
#define ESAI_TCR_TEDIE_SHIFT                     (21U)
#define ESAI_TCR_TEDIE(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEDIE_SHIFT)) & ESAI_TCR_TEDIE_MASK)
#define ESAI_TCR_TIE_MASK                        (0x400000U)
#define ESAI_TCR_TIE_SHIFT                       (22U)
#define ESAI_TCR_TIE(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TIE_SHIFT)) & ESAI_TCR_TIE_MASK)
#define ESAI_TCR_TLIE_MASK                       (0x800000U)
#define ESAI_TCR_TLIE_SHIFT                      (23U)
#define ESAI_TCR_TLIE(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TLIE_SHIFT)) & ESAI_TCR_TLIE_MASK)
/*! @} */

/*! @name TCCR - Transmit Clock Control Register */
/*! @{ */
#define ESAI_TCCR_TPM_MASK                       (0xFFU)
#define ESAI_TCCR_TPM_SHIFT                      (0U)
#define ESAI_TCCR_TPM(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPM_SHIFT)) & ESAI_TCCR_TPM_MASK)
#define ESAI_TCCR_TPSR_MASK                      (0x100U)
#define ESAI_TCCR_TPSR_SHIFT                     (8U)
#define ESAI_TCCR_TPSR(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPSR_SHIFT)) & ESAI_TCCR_TPSR_MASK)
#define ESAI_TCCR_TDC_MASK                       (0x3E00U)
#define ESAI_TCCR_TDC_SHIFT                      (9U)
#define ESAI_TCCR_TDC(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TDC_SHIFT)) & ESAI_TCCR_TDC_MASK)
#define ESAI_TCCR_TFP_MASK                       (0x3C000U)
#define ESAI_TCCR_TFP_SHIFT                      (14U)
#define ESAI_TCCR_TFP(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFP_SHIFT)) & ESAI_TCCR_TFP_MASK)
#define ESAI_TCCR_TCKP_MASK                      (0x40000U)
#define ESAI_TCCR_TCKP_SHIFT                     (18U)
#define ESAI_TCCR_TCKP(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKP_SHIFT)) & ESAI_TCCR_TCKP_MASK)
#define ESAI_TCCR_TFSP_MASK                      (0x80000U)
#define ESAI_TCCR_TFSP_SHIFT                     (19U)
#define ESAI_TCCR_TFSP(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSP_SHIFT)) & ESAI_TCCR_TFSP_MASK)
#define ESAI_TCCR_THCKP_MASK                     (0x100000U)
#define ESAI_TCCR_THCKP_SHIFT                    (20U)
#define ESAI_TCCR_THCKP(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKP_SHIFT)) & ESAI_TCCR_THCKP_MASK)
#define ESAI_TCCR_TCKD_MASK                      (0x200000U)
#define ESAI_TCCR_TCKD_SHIFT                     (21U)
#define ESAI_TCCR_TCKD(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKD_SHIFT)) & ESAI_TCCR_TCKD_MASK)
#define ESAI_TCCR_TFSD_MASK                      (0x400000U)
#define ESAI_TCCR_TFSD_SHIFT                     (22U)
#define ESAI_TCCR_TFSD(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSD_SHIFT)) & ESAI_TCCR_TFSD_MASK)
#define ESAI_TCCR_THCKD_MASK                     (0x800000U)
#define ESAI_TCCR_THCKD_SHIFT                    (23U)
#define ESAI_TCCR_THCKD(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKD_SHIFT)) & ESAI_TCCR_THCKD_MASK)
/*! @} */

/*! @name RCR - Receive Control Register */
/*! @{ */
#define ESAI_RCR_RE0_MASK                        (0x1U)
#define ESAI_RCR_RE0_SHIFT                       (0U)
#define ESAI_RCR_RE0(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE0_SHIFT)) & ESAI_RCR_RE0_MASK)
#define ESAI_RCR_RE1_MASK                        (0x2U)
#define ESAI_RCR_RE1_SHIFT                       (1U)
#define ESAI_RCR_RE1(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE1_SHIFT)) & ESAI_RCR_RE1_MASK)
#define ESAI_RCR_RE2_MASK                        (0x4U)
#define ESAI_RCR_RE2_SHIFT                       (2U)
#define ESAI_RCR_RE2(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE2_SHIFT)) & ESAI_RCR_RE2_MASK)
#define ESAI_RCR_RE3_MASK                        (0x8U)
#define ESAI_RCR_RE3_SHIFT                       (3U)
#define ESAI_RCR_RE3(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE3_SHIFT)) & ESAI_RCR_RE3_MASK)
#define ESAI_RCR_RSHFD_MASK                      (0x40U)
#define ESAI_RCR_RSHFD_SHIFT                     (6U)
#define ESAI_RCR_RSHFD(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSHFD_SHIFT)) & ESAI_RCR_RSHFD_MASK)
#define ESAI_RCR_RWA_MASK                        (0x80U)
#define ESAI_RCR_RWA_SHIFT                       (7U)
#define ESAI_RCR_RWA(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RWA_SHIFT)) & ESAI_RCR_RWA_MASK)
#define ESAI_RCR_RMOD_MASK                       (0x300U)
#define ESAI_RCR_RMOD_SHIFT                      (8U)
#define ESAI_RCR_RMOD(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RMOD_SHIFT)) & ESAI_RCR_RMOD_MASK)
#define ESAI_RCR_RSWS_MASK                       (0x7C00U)
#define ESAI_RCR_RSWS_SHIFT                      (10U)
#define ESAI_RCR_RSWS(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSWS_SHIFT)) & ESAI_RCR_RSWS_MASK)
#define ESAI_RCR_RFSL_MASK                       (0x8000U)
#define ESAI_RCR_RFSL_SHIFT                      (15U)
#define ESAI_RCR_RFSL(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSL_SHIFT)) & ESAI_RCR_RFSL_MASK)
#define ESAI_RCR_RFSR_MASK                       (0x10000U)
#define ESAI_RCR_RFSR_SHIFT                      (16U)
#define ESAI_RCR_RFSR(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSR_SHIFT)) & ESAI_RCR_RFSR_MASK)
#define ESAI_RCR_RPR_MASK                        (0x80000U)
#define ESAI_RCR_RPR_SHIFT                       (19U)
#define ESAI_RCR_RPR(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RPR_SHIFT)) & ESAI_RCR_RPR_MASK)
#define ESAI_RCR_REIE_MASK                       (0x100000U)
#define ESAI_RCR_REIE_SHIFT                      (20U)
#define ESAI_RCR_REIE(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REIE_SHIFT)) & ESAI_RCR_REIE_MASK)
#define ESAI_RCR_REDIE_MASK                      (0x200000U)
#define ESAI_RCR_REDIE_SHIFT                     (21U)
#define ESAI_RCR_REDIE(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REDIE_SHIFT)) & ESAI_RCR_REDIE_MASK)
#define ESAI_RCR_RIE_MASK                        (0x400000U)
#define ESAI_RCR_RIE_SHIFT                       (22U)
#define ESAI_RCR_RIE(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RIE_SHIFT)) & ESAI_RCR_RIE_MASK)
#define ESAI_RCR_RLIE_MASK                       (0x800000U)
#define ESAI_RCR_RLIE_SHIFT                      (23U)
#define ESAI_RCR_RLIE(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RLIE_SHIFT)) & ESAI_RCR_RLIE_MASK)
/*! @} */

/*! @name RCCR - Receive Clock Control Register */
/*! @{ */
#define ESAI_RCCR_RPM_MASK                       (0xFFU)
#define ESAI_RCCR_RPM_SHIFT                      (0U)
#define ESAI_RCCR_RPM(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPM_SHIFT)) & ESAI_RCCR_RPM_MASK)
#define ESAI_RCCR_RPSR_MASK                      (0x100U)
#define ESAI_RCCR_RPSR_SHIFT                     (8U)
#define ESAI_RCCR_RPSR(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPSR_SHIFT)) & ESAI_RCCR_RPSR_MASK)
#define ESAI_RCCR_RDC_MASK                       (0x3E00U)
#define ESAI_RCCR_RDC_SHIFT                      (9U)
#define ESAI_RCCR_RDC(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RDC_SHIFT)) & ESAI_RCCR_RDC_MASK)
#define ESAI_RCCR_RFP_MASK                       (0x3C000U)
#define ESAI_RCCR_RFP_SHIFT                      (14U)
#define ESAI_RCCR_RFP(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFP_SHIFT)) & ESAI_RCCR_RFP_MASK)
#define ESAI_RCCR_RCKP_MASK                      (0x40000U)
#define ESAI_RCCR_RCKP_SHIFT                     (18U)
#define ESAI_RCCR_RCKP(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKP_SHIFT)) & ESAI_RCCR_RCKP_MASK)
#define ESAI_RCCR_RFSP_MASK                      (0x80000U)
#define ESAI_RCCR_RFSP_SHIFT                     (19U)
#define ESAI_RCCR_RFSP(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSP_SHIFT)) & ESAI_RCCR_RFSP_MASK)
#define ESAI_RCCR_RHCKP_MASK                     (0x100000U)
#define ESAI_RCCR_RHCKP_SHIFT                    (20U)
#define ESAI_RCCR_RHCKP(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKP_SHIFT)) & ESAI_RCCR_RHCKP_MASK)
#define ESAI_RCCR_RCKD_MASK                      (0x200000U)
#define ESAI_RCCR_RCKD_SHIFT                     (21U)
#define ESAI_RCCR_RCKD(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKD_SHIFT)) & ESAI_RCCR_RCKD_MASK)
#define ESAI_RCCR_RFSD_MASK                      (0x400000U)
#define ESAI_RCCR_RFSD_SHIFT                     (22U)
#define ESAI_RCCR_RFSD(x)                        (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSD_SHIFT)) & ESAI_RCCR_RFSD_MASK)
#define ESAI_RCCR_RHCKD_MASK                     (0x800000U)
#define ESAI_RCCR_RHCKD_SHIFT                    (23U)
#define ESAI_RCCR_RHCKD(x)                       (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKD_SHIFT)) & ESAI_RCCR_RHCKD_MASK)
/*! @} */

/*! @name TSMA - Transmit Slot Mask Register A */
/*! @{ */
#define ESAI_TSMA_TS_MASK                        (0xFFFFU)
#define ESAI_TSMA_TS_SHIFT                       (0U)
#define ESAI_TSMA_TS(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TSMA_TS_SHIFT)) & ESAI_TSMA_TS_MASK)
/*! @} */

/*! @name TSMB - Transmit Slot Mask Register B */
/*! @{ */
#define ESAI_TSMB_TS_MASK                        (0xFFFFU)
#define ESAI_TSMB_TS_SHIFT                       (0U)
#define ESAI_TSMB_TS(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_TSMB_TS_SHIFT)) & ESAI_TSMB_TS_MASK)
/*! @} */

/*! @name RSMA - Receive Slot Mask Register A */
/*! @{ */
#define ESAI_RSMA_RS_MASK                        (0xFFFFU)
#define ESAI_RSMA_RS_SHIFT                       (0U)
#define ESAI_RSMA_RS(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RSMA_RS_SHIFT)) & ESAI_RSMA_RS_MASK)
/*! @} */

/*! @name RSMB - Receive Slot Mask Register B */
/*! @{ */
#define ESAI_RSMB_RS_MASK                        (0xFFFFU)
#define ESAI_RSMB_RS_SHIFT                       (0U)
#define ESAI_RSMB_RS(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_RSMB_RS_SHIFT)) & ESAI_RSMB_RS_MASK)
/*! @} */

/*! @name PDRC - Port C Data Register */
/*! @{ */
#define ESAI_PDRC_PD_MASK                        (0xFFFU)
#define ESAI_PDRC_PD_SHIFT                       (0U)
#define ESAI_PDRC_PD(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_PDRC_PD_SHIFT)) & ESAI_PDRC_PD_MASK)
/*! @} */

/*! @name PRRC - Port C Direction Register */
/*! @{ */
#define ESAI_PRRC_PDC_MASK                       (0xFFFU)
#define ESAI_PRRC_PDC_SHIFT                      (0U)
#define ESAI_PRRC_PDC(x)                         (((uint32_t)(((uint32_t)(x)) << ESAI_PRRC_PDC_SHIFT)) & ESAI_PRRC_PDC_MASK)
/*! @} */

/*! @name PCRC - Port C Control Register */
/*! @{ */
#define ESAI_PCRC_PC_MASK                        (0xFFFU)
#define ESAI_PCRC_PC_SHIFT                       (0U)
#define ESAI_PCRC_PC(x)                          (((uint32_t)(((uint32_t)(x)) << ESAI_PCRC_PC_SHIFT)) & ESAI_PCRC_PC_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ESAI_Register_Masks */


/* ESAI - Peripheral instance base addresses */
/** Peripheral AUDIO__ESAI0 base address */
#define AUDIO__ESAI0_BASE                        (0x59010000u)
/** Peripheral AUDIO__ESAI0 base pointer */
#define AUDIO__ESAI0                             ((ESAI_Type *)AUDIO__ESAI0_BASE)
/** Peripheral AUDIO__ESAI1 base address */
#define AUDIO__ESAI1_BASE                        (0x59810000u)
/** Peripheral AUDIO__ESAI1 base pointer */
#define AUDIO__ESAI1                             ((ESAI_Type *)AUDIO__ESAI1_BASE)
/** Array initializer of ESAI peripheral base addresses */
#define ESAI_BASE_ADDRS                          { AUDIO__ESAI0_BASE, AUDIO__ESAI1_BASE }
/** Array initializer of ESAI peripheral base pointers */
#define ESAI_BASE_PTRS                           { AUDIO__ESAI0, AUDIO__ESAI1 }
/** Interrupt vectors for the ESAI peripheral type */
#define ESAI_IRQS                                { AUDIO_ESAI0_INT_IRQn, AUDIO_ESAI1_INT_IRQn }

/*!
 * @}
 */ /* end of group ESAI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FLEXSPI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
 * @{
 */

/** FLEXSPI - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCR0;                              /**< Module Control Register 0, offset: 0x0 */
  __IO uint32_t MCR1;                              /**< Module Control Register 1, offset: 0x4 */
  __IO uint32_t MCR2;                              /**< Module Control Register 2, offset: 0x8 */
  __IO uint32_t AHBCR;                             /**< AHB Bus Control Register, offset: 0xC */
  __IO uint32_t INTEN;                             /**< Interrupt Enable Register, offset: 0x10 */
  __IO uint32_t INTR;                              /**< Interrupt Register, offset: 0x14 */
  __IO uint32_t LUTKEY;                            /**< LUT Key Register, offset: 0x18 */
  __IO uint32_t LUTCR;                             /**< LUT Control Register, offset: 0x1C */
  __IO uint32_t AHBRXBUFCR0[8];                    /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */
       uint32_t AHBRXBUFCR1[8];                    /**< AHB RX Buffer 0 Control Register 1..AHB RX Buffer 7 Control Register 1, array offset: 0x40, array step: 0x4 */
  __IO uint32_t FLSHCR0[4];                        /**< Flash A1 Control Register 0..Flash B2 Control Register 0, array offset: 0x60, array step: 0x4 */
  __IO uint32_t FLSHCR1[4];                        /**< Flash A1 Control Register 1..Flash B2 Control Register 1, array offset: 0x70, array step: 0x4 */
  __IO uint32_t FLSHCR2[4];                        /**< Flash A1 Control Register 2..Flash B2 Control Register 2, array offset: 0x80, array step: 0x4 */
  __IO uint32_t FLSHCR3;                           /**< Flash Control Register 3, offset: 0x90 */
  __IO uint32_t FLSHCR4;                           /**< Flash Control Register 4, offset: 0x94 */
       uint32_t FLSHCR5;                           /**< Flash Control Register 5, offset: 0x98 */
       uint32_t FLSHCR6;                           /**< Flash Control Register 6, offset: 0x9C */
  __IO uint32_t IPCR0;                             /**< IP Control Register 0, offset: 0xA0 */
  __IO uint32_t IPCR1;                             /**< IP Control Register 1, offset: 0xA4 */
       uint32_t IPCR2;                             /**< IP Control Register 2, offset: 0xA8 */
       uint32_t IPCR3;                             /**< IP Control Register 3, offset: 0xAC */
  __IO uint32_t IPCMD;                             /**< IP Command Register, offset: 0xB0 */
  __IO uint32_t DLPR;                              /**< Data Learn Pattern Register, offset: 0xB4 */
  __IO uint32_t IPRXFCR;                           /**< IP RX FIFO Control Register, offset: 0xB8 */
  __IO uint32_t IPTXFCR;                           /**< IP TX FIFO Control Register, offset: 0xBC */
  __IO uint32_t DLLCR[2];                          /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
  __IO uint32_t MISCCR2;                           /**< Misc Control Register 2, offset: 0xC8 */
       uint32_t MISCCR3;                           /**< Misc Control Register 3, offset: 0xCC */
       uint32_t MISCCR4;                           /**< Misc Control Register 4, offset: 0xD0 */
       uint32_t MISCCR5;                           /**< Misc Control Register 5, offset: 0xD4 */
       uint32_t MISCCR6;                           /**< Misc Control Register 6, offset: 0xD8 */
       uint32_t MISCCR7;                           /**< Misc Control Register 7, offset: 0xDC */
  __I  uint32_t STS0;                              /**< Status Register 0, offset: 0xE0 */
  __I  uint32_t STS1;                              /**< Status Register 1, offset: 0xE4 */
  __I  uint32_t STS2;                              /**< Status Register 2, offset: 0xE8 */
  __I  uint32_t AHBSPNDSTS;                        /**< AHB Suspend Status Register, offset: 0xEC */
  __I  uint32_t IPRXFSTS;                          /**< IP RX FIFO Status Register, offset: 0xF0 */
  __I  uint32_t IPTXFSTS;                          /**< IP TX FIFO Status Register, offset: 0xF4 */
       uint8_t RESERVED_0[8];
  __I  uint32_t RFDR[32];                          /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
  __O  uint32_t TFDR[32];                          /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
  __IO uint32_t LUT[128];                          /**< LUT 0..LUT 127, array offset: 0x200, array step: 0x4 */
} FLEXSPI_Type;

/* ----------------------------------------------------------------------------
   -- FLEXSPI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
 * @{
 */

/*! @name MCR0 - Module Control Register 0 */
/*! @{ */
#define FLEXSPI_MCR0_SWRESET_MASK                (0x1U)
#define FLEXSPI_MCR0_SWRESET_SHIFT               (0U)
#define FLEXSPI_MCR0_SWRESET(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
#define FLEXSPI_MCR0_MDIS_MASK                   (0x2U)
#define FLEXSPI_MCR0_MDIS_SHIFT                  (1U)
#define FLEXSPI_MCR0_MDIS(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
#define FLEXSPI_MCR0_ENDCFG_MASK                 (0xCU)
#define FLEXSPI_MCR0_ENDCFG_SHIFT                (2U)
/*! ENDCFG - AHB/IPS Bus Endian Configuration
 *  0b00..64 bit Little Endian
 *  0b01..64 bit Big Endian
 *  0b10..32 bit Little Endian
 *  0b11..32 bit Big Endian
 */
#define FLEXSPI_MCR0_ENDCFG(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ENDCFG_SHIFT)) & FLEXSPI_MCR0_ENDCFG_MASK)
#define FLEXSPI_MCR0_RXCLKSRC_MASK               (0x30U)
#define FLEXSPI_MCR0_RXCLKSRC_SHIFT              (4U)
/*! RXCLKSRC - Sample Clock source selection for Flash Reading
 *  0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
 *  0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
 *  0b10..SCK output clock and loopback from SCK pad
 *  0b11..Flash provided Read strobe and input from DQS pad
 */
#define FLEXSPI_MCR0_RXCLKSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
#define FLEXSPI_MCR0_ARDFEN_MASK                 (0x40U)
#define FLEXSPI_MCR0_ARDFEN_SHIFT                (6U)
/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
 *  0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
 *  0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
 */
#define FLEXSPI_MCR0_ARDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
#define FLEXSPI_MCR0_ATDFEN_MASK                 (0x80U)
#define FLEXSPI_MCR0_ATDFEN_SHIFT                (7U)
/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
 *  0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
 *  0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
 */
#define FLEXSPI_MCR0_ATDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
#define FLEXSPI_MCR0_SERCLKDIV_MASK              (0x700U)
#define FLEXSPI_MCR0_SERCLKDIV_SHIFT             (8U)
/*! SERCLKDIV - The serial root clock could be divided inside FlexSPI wrapper. Refer Clocks chapter for more details on clocking.
 *  0b000..Divided by 1
 *  0b001..Divided by 2
 *  0b010..Divided by 3
 *  0b011..Divided by 4
 *  0b100..Divided by 5
 *  0b101..Divided by 6
 *  0b110..Divided by 7
 *  0b111..Divided by 8
 */
#define FLEXSPI_MCR0_SERCLKDIV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
#define FLEXSPI_MCR0_HSEN_MASK                   (0x800U)
#define FLEXSPI_MCR0_HSEN_SHIFT                  (11U)
/*! HSEN - Half Speed Serial Flash access Enable.
 *  0b0..Disable divide by 2 of serial flash clock for half speed commands.
 *  0b1..Enable divide by 2 of serial flash clock for half speed commands.
 */
#define FLEXSPI_MCR0_HSEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
#define FLEXSPI_MCR0_DOZEEN_MASK                 (0x1000U)
#define FLEXSPI_MCR0_DOZEEN_SHIFT                (12U)
/*! DOZEEN - Doze mode enable bit
 *  0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
 *  0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
 */
#define FLEXSPI_MCR0_DOZEEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
#define FLEXSPI_MCR0_COMBINATIONEN_MASK          (0x2000U)
#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT         (13U)
/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]).
 *  0b0..Disable.
 *  0b1..Enable.
 */
#define FLEXSPI_MCR0_COMBINATIONEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
#define FLEXSPI_MCR0_SCKFREERUNEN_MASK           (0x4000U)
#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT          (14U)
/*! SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2).
 *  0b0..Disable.
 *  0b1..Enable.
 */
#define FLEXSPI_MCR0_SCKFREERUNEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
#define FLEXSPI_MCR0_LEARNEN_MASK                (0x8000U)
#define FLEXSPI_MCR0_LEARNEN_SHIFT               (15U)
/*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction is correctly executed.
 *  0b0..Disable.
 *  0b1..Enable.
 */
#define FLEXSPI_MCR0_LEARNEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK)
#define FLEXSPI_MCR0_IPGRANTWAIT_MASK            (0xFF0000U)
#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT           (16U)
#define FLEXSPI_MCR0_IPGRANTWAIT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK           (0xFF000000U)
#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT          (24U)
#define FLEXSPI_MCR0_AHBGRANTWAIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
/*! @} */

/*! @name MCR1 - Module Control Register 1 */
/*! @{ */
#define FLEXSPI_MCR1_AHBBUSWAIT_MASK             (0xFFFFU)
#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT            (0U)
#define FLEXSPI_MCR1_AHBBUSWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
#define FLEXSPI_MCR1_SEQWAIT_MASK                (0xFFFF0000U)
#define FLEXSPI_MCR1_SEQWAIT_SHIFT               (16U)
#define FLEXSPI_MCR1_SEQWAIT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
/*! @} */

/*! @name MCR2 - Module Control Register 2 */
/*! @{ */
#define FLEXSPI_MCR2_ABORTONCMDEN_MASK           (0x1U)
#define FLEXSPI_MCR2_ABORTONCMDEN_SHIFT          (0U)
/*! ABORTONCMDEN - Allow Command Sequence Abort during CMD (CMD_SDR/CMD_DDR) instruction.
 *  0b0..When command abort request received during CMD instruction, command sequence will wait for the CMD instruction to complete instead of aborting immediately.
 *  0b1..When command abort request received during CMD instruction, command sequence will be aborted immediately.
 */
#define FLEXSPI_MCR2_ABORTONCMDEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONCMDEN_SHIFT)) & FLEXSPI_MCR2_ABORTONCMDEN_MASK)
#define FLEXSPI_MCR2_ABORTONRADDREN_MASK         (0x2U)
#define FLEXSPI_MCR2_ABORTONRADDREN_SHIFT        (1U)
#define FLEXSPI_MCR2_ABORTONRADDREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONRADDREN_SHIFT)) & FLEXSPI_MCR2_ABORTONRADDREN_MASK)
#define FLEXSPI_MCR2_ABORTONCADDREN_MASK         (0x4U)
#define FLEXSPI_MCR2_ABORTONCADDREN_SHIFT        (2U)
#define FLEXSPI_MCR2_ABORTONCADDREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONCADDREN_SHIFT)) & FLEXSPI_MCR2_ABORTONCADDREN_MASK)
#define FLEXSPI_MCR2_ABORTONMODEEN_MASK          (0x8U)
#define FLEXSPI_MCR2_ABORTONMODEEN_SHIFT         (3U)
#define FLEXSPI_MCR2_ABORTONMODEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONMODEEN_SHIFT)) & FLEXSPI_MCR2_ABORTONMODEEN_MASK)
#define FLEXSPI_MCR2_ABORTONDUMMYEN_MASK         (0x10U)
#define FLEXSPI_MCR2_ABORTONDUMMYEN_SHIFT        (4U)
#define FLEXSPI_MCR2_ABORTONDUMMYEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONDUMMYEN_SHIFT)) & FLEXSPI_MCR2_ABORTONDUMMYEN_MASK)
#define FLEXSPI_MCR2_ABORTONWRITEEN_MASK         (0x20U)
#define FLEXSPI_MCR2_ABORTONWRITEEN_SHIFT        (5U)
#define FLEXSPI_MCR2_ABORTONWRITEEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONWRITEEN_SHIFT)) & FLEXSPI_MCR2_ABORTONWRITEEN_MASK)
#define FLEXSPI_MCR2_ABORTONREADEN_MASK          (0x40U)
#define FLEXSPI_MCR2_ABORTONREADEN_SHIFT         (6U)
#define FLEXSPI_MCR2_ABORTONREADEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONREADEN_SHIFT)) & FLEXSPI_MCR2_ABORTONREADEN_MASK)
#define FLEXSPI_MCR2_ABORTONLEARNEN_MASK         (0x80U)
#define FLEXSPI_MCR2_ABORTONLEARNEN_SHIFT        (7U)
#define FLEXSPI_MCR2_ABORTONLEARNEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONLEARNEN_SHIFT)) & FLEXSPI_MCR2_ABORTONLEARNEN_MASK)
#define FLEXSPI_MCR2_ABORTONDATSZEN_MASK         (0x100U)
#define FLEXSPI_MCR2_ABORTONDATSZEN_SHIFT        (8U)
#define FLEXSPI_MCR2_ABORTONDATSZEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONDATSZEN_SHIFT)) & FLEXSPI_MCR2_ABORTONDATSZEN_MASK)
#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK           (0x800U)
#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT          (11U)
/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
 *  0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
 *  0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
 */
#define FLEXSPI_MCR2_CLRAHBBUFOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
#define FLEXSPI_MCR2_SCK2OPT_MASK                (0x1000U)
#define FLEXSPI_MCR2_SCK2OPT_SHIFT               (12U)
/*! SCK2OPT - This bit controls the SCK2 toggle output.
 *  0b0..SCK2 output clock will toggle for READ/LEARN instructions only.
 *  0b1..SCK2 output clock will toggle for the whole sequence.
 */
#define FLEXSPI_MCR2_SCK2OPT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCK2OPT_SHIFT)) & FLEXSPI_MCR2_SCK2OPT_MASK)
#define FLEXSPI_MCR2_TSTMD_MASK                  (0x2000U)
#define FLEXSPI_MCR2_TSTMD_SHIFT                 (13U)
/*! TSTMD - This bit is to support ATE test.
 *  0b0..Test mode disable. Sequence execution is started when triggered by IP/AHB command as normal.
 *  0b1..Test mode Enable. Sequence execution is not started after triggered by IP/AHB command, it's blocked until ipt_tester_trigger input (another pin for test) is high. A high pulse of serial clock domain is needed.
 */
#define FLEXSPI_MCR2_TSTMD(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_TSTMD_SHIFT)) & FLEXSPI_MCR2_TSTMD_MASK)
#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK          (0x4000U)
#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT         (14U)
#define FLEXSPI_MCR2_CLRLEARNPHASE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK           (0x8000U)
#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT          (15U)
/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
 *  0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 seperately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored.
 *  0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
 */
#define FLEXSPI_MCR2_SAMEDEVICEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
#define FLEXSPI_MCR2_FLASHDQSOPT_MASK            (0x10000U)
#define FLEXSPI_MCR2_FLASHDQSOPT_SHIFT           (16U)
/*! FLASHDQSOPT - Option bit for Flash device priovided DQS. For internal use only.
 *  0b0..FlexSPI will drive toggling SCK output until it receives all flash read data bits, but there will be extra SCK cycle after all read data bits returned on SPI bus.
 *  0b1..FlexSPI will drvie SCK output according to read data size and pad number (no extra SCK toggling). If there is DQS latency, FlexSPI will receive less data than required. Never set this bit if there is DQS latency.
 */
#define FLEXSPI_MCR2_FLASHDQSOPT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_FLASHDQSOPT_SHIFT)) & FLEXSPI_MCR2_FLASHDQSOPT_MASK)
#define FLEXSPI_MCR2_RXDELAYOPT_MASK             (0x60000U)
#define FLEXSPI_MCR2_RXDELAYOPT_SHIFT            (17U)
/*! RXDELAYOPT - Option bit for RX data sampling (when MCR0[RXCLKSRC] is not set to 0x3), for internal use only.
 *  0b00..FlexSPI will sample RX data lines 4 cycles after SCK edge.
 *  0b01..FlexSPI will sample RX data lines 5 cycles after SCK edge.
 *  0b10..FlexSPI will sample RX data lines 6 cycles after SCK edge.
 *  0b11..FlexSPI will sample RX data lines 7 cycles after SCK edge.
 */
#define FLEXSPI_MCR2_RXDELAYOPT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RXDELAYOPT_SHIFT)) & FLEXSPI_MCR2_RXDELAYOPT_MASK)
#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK            (0x80000U)
#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT           (19U)
/*! SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set.
 *  0b1..SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available.
 *  0b0..SCKB pad is used as port B SCK clock output. Port B flash access is available.
 */
#define FLEXSPI_MCR2_SCKBDIFFOPT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
#define FLEXSPI_MCR2_CLKPHASERST_MASK            (0x100000U)
#define FLEXSPI_MCR2_CLKPHASERST_SHIFT           (20U)
#define FLEXSPI_MCR2_CLKPHASERST(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLKPHASERST_SHIFT)) & FLEXSPI_MCR2_CLKPHASERST_MASK)
#define FLEXSPI_MCR2_RESUMEWAIT_MASK             (0xFF000000U)
#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT            (24U)
#define FLEXSPI_MCR2_RESUMEWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
/*! @} */

/*! @name AHBCR - AHB Bus Control Register */
/*! @{ */
#define FLEXSPI_AHBCR_APAREN_MASK                (0x1U)
#define FLEXSPI_AHBCR_APAREN_SHIFT               (0U)
/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
 *  0b0..Flash will be accessed in Individual mode.
 *  0b1..Flash will be accessed in Parallel mode.
 */
#define FLEXSPI_AHBCR_APAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
#define FLEXSPI_AHBCR_CLRAHBRXBUF_MASK           (0x2U)
#define FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT          (1U)
#define FLEXSPI_AHBCR_CLRAHBRXBUF(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK)
#define FLEXSPI_AHBCR_CLRAHBTXBUF_MASK           (0x4U)
#define FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT          (2U)
#define FLEXSPI_AHBCR_CLRAHBTXBUF(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBTXBUF_MASK)
#define FLEXSPI_AHBCR_CACHABLEEN_MASK            (0x8U)
#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT           (3U)
/*! CACHABLEEN - Enable AHB bus cachable read access support.
 *  0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
 *  0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
 */
#define FLEXSPI_AHBCR_CACHABLEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK          (0x10U)
#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT         (4U)
/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write.
 *  0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable hprot[2]=0x1 or 0x0), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished.
 *  0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished.
 */
#define FLEXSPI_AHBCR_BUFFERABLEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
#define FLEXSPI_AHBCR_PREFETCHEN_MASK            (0x20U)
#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT           (5U)
#define FLEXSPI_AHBCR_PREFETCHEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
#define FLEXSPI_AHBCR_READADDROPT_MASK           (0x40U)
#define FLEXSPI_AHBCR_READADDROPT_SHIFT          (6U)
/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
 *  0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable.
 *  0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB burst required to meet the alignment requirement.
 */
#define FLEXSPI_AHBCR_READADDROPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
#define FLEXSPI_AHBCR_AFLASHBASE_MASK            (0xF0000000U)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
#define FLEXSPI_AHBCR_AFLASHBASE_SHIFT           (28U)
#define FLEXSPI_AHBCR_AFLASHBASE(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_AFLASHBASE_SHIFT)) & FLEXSPI_AHBCR_AFLASHBASE_MASK)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
/*! @} */

/*! @name INTEN - Interrupt Enable Register */
/*! @{ */
#define FLEXSPI_INTEN_IPCMDDONEEN_MASK           (0x1U)
#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT          (0U)
#define FLEXSPI_INTEN_IPCMDDONEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
#define FLEXSPI_INTEN_IPCMDGEEN_MASK             (0x2U)
#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT            (1U)
#define FLEXSPI_INTEN_IPCMDGEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
#define FLEXSPI_INTEN_AHBCMDGEEN_MASK            (0x4U)
#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT           (2U)
#define FLEXSPI_INTEN_AHBCMDGEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
#define FLEXSPI_INTEN_IPCMDERREN_MASK            (0x8U)
#define FLEXSPI_INTEN_IPCMDERREN_SHIFT           (3U)
#define FLEXSPI_INTEN_IPCMDERREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
#define FLEXSPI_INTEN_AHBCMDERREN_MASK           (0x10U)
#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT          (4U)
#define FLEXSPI_INTEN_AHBCMDERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
#define FLEXSPI_INTEN_IPRXWAEN_MASK              (0x20U)
#define FLEXSPI_INTEN_IPRXWAEN_SHIFT             (5U)
#define FLEXSPI_INTEN_IPRXWAEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
#define FLEXSPI_INTEN_IPTXWEEN_MASK              (0x40U)
#define FLEXSPI_INTEN_IPTXWEEN_SHIFT             (6U)
#define FLEXSPI_INTEN_IPTXWEEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK       (0x80U)
#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT      (7U)
#define FLEXSPI_INTEN_DATALEARNFAILEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK)
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK         (0x100U)
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT        (8U)
#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK         (0x200U)
#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT        (9U)
#define FLEXSPI_INTEN_SCKSTOPBYWREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK       (0x400U)
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT      (10U)
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK          (0x800U)
#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT         (11U)
#define FLEXSPI_INTEN_SEQTIMEOUTEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
/*! @} */

/*! @name INTR - Interrupt Register */
/*! @{ */
#define FLEXSPI_INTR_IPCMDDONE_MASK              (0x1U)
#define FLEXSPI_INTR_IPCMDDONE_SHIFT             (0U)
#define FLEXSPI_INTR_IPCMDDONE(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
#define FLEXSPI_INTR_IPCMDGE_MASK                (0x2U)
#define FLEXSPI_INTR_IPCMDGE_SHIFT               (1U)
#define FLEXSPI_INTR_IPCMDGE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
#define FLEXSPI_INTR_AHBCMDGE_MASK               (0x4U)
#define FLEXSPI_INTR_AHBCMDGE_SHIFT              (2U)
#define FLEXSPI_INTR_AHBCMDGE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
#define FLEXSPI_INTR_IPCMDERR_MASK               (0x8U)
#define FLEXSPI_INTR_IPCMDERR_SHIFT              (3U)
#define FLEXSPI_INTR_IPCMDERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
#define FLEXSPI_INTR_AHBCMDERR_MASK              (0x10U)
#define FLEXSPI_INTR_AHBCMDERR_SHIFT             (4U)
#define FLEXSPI_INTR_AHBCMDERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
#define FLEXSPI_INTR_IPRXWA_MASK                 (0x20U)
#define FLEXSPI_INTR_IPRXWA_SHIFT                (5U)
#define FLEXSPI_INTR_IPRXWA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
#define FLEXSPI_INTR_IPTXWE_MASK                 (0x40U)
#define FLEXSPI_INTR_IPTXWE_SHIFT                (6U)
#define FLEXSPI_INTR_IPTXWE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
#define FLEXSPI_INTR_DATALEARNFAIL_MASK          (0x80U)
#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT         (7U)
#define FLEXSPI_INTR_DATALEARNFAIL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK)
#define FLEXSPI_INTR_SCKSTOPBYRD_MASK            (0x100U)
#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT           (8U)
#define FLEXSPI_INTR_SCKSTOPBYRD(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
#define FLEXSPI_INTR_SCKSTOPBYWR_MASK            (0x200U)
#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT           (9U)
#define FLEXSPI_INTR_SCKSTOPBYWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK          (0x400U)
#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT         (10U)
#define FLEXSPI_INTR_AHBBUSTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
#define FLEXSPI_INTR_SEQTIMEOUT_MASK             (0x800U)
#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT            (11U)
#define FLEXSPI_INTR_SEQTIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
/*! @} */

/*! @name LUTKEY - LUT Key Register */
/*! @{ */
#define FLEXSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
#define FLEXSPI_LUTKEY_KEY_SHIFT                 (0U)
#define FLEXSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
/*! @} */

/*! @name LUTCR - LUT Control Register */
/*! @{ */
#define FLEXSPI_LUTCR_LOCK_MASK                  (0x1U)
#define FLEXSPI_LUTCR_LOCK_SHIFT                 (0U)
#define FLEXSPI_LUTCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
#define FLEXSPI_LUTCR_UNLOCK_MASK                (0x2U)
#define FLEXSPI_LUTCR_UNLOCK_SHIFT               (1U)
#define FLEXSPI_LUTCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
/*! @} */

/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */
/*! @{ */
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK           (0x1FFU)
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT          (0U)
#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK          (0xF0000U)
#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT         (16U)
#define FLEXSPI_AHBRXBUFCR0_MSTRID(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK        (0x7000000U)
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT       (24U)
#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK      (0x80000000U)
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT     (31U)
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
/*! @} */

/* The count of FLEXSPI_AHBRXBUFCR0 */
#define FLEXSPI_AHBRXBUFCR0_COUNT                (8U)

/* The count of FLEXSPI_AHBRXBUFCR1 */
#define FLEXSPI_AHBRXBUFCR1_COUNT                (8U)

/*! @name FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0 */
/*! @{ */
#define FLEXSPI_FLSHCR0_FLSHSZ_MASK              (0x7FFFFFU)
#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT             (0U)
#define FLEXSPI_FLSHCR0_FLSHSZ(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
/*! @} */

/* The count of FLEXSPI_FLSHCR0 */
#define FLEXSPI_FLSHCR0_COUNT                    (4U)

/*! @name FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1 */
/*! @{ */
#define FLEXSPI_FLSHCR1_TCSS_MASK                (0x1FU)
#define FLEXSPI_FLSHCR1_TCSS_SHIFT               (0U)
#define FLEXSPI_FLSHCR1_TCSS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
#define FLEXSPI_FLSHCR1_TCSH_MASK                (0x3E0U)
#define FLEXSPI_FLSHCR1_TCSH_SHIFT               (5U)
#define FLEXSPI_FLSHCR1_TCSH(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
#define FLEXSPI_FLSHCR1_WA_MASK                  (0x400U)
#define FLEXSPI_FLSHCR1_WA_SHIFT                 (10U)
#define FLEXSPI_FLSHCR1_WA(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
#define FLEXSPI_FLSHCR1_CAS_MASK                 (0x7800U)
#define FLEXSPI_FLSHCR1_CAS_SHIFT                (11U)
#define FLEXSPI_FLSHCR1_CAS(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK      (0x8000U)
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT     (15U)
/*! CSINTERVALUNIT - CS interval unit
 *  0b0..The CS interval unit is 1 serial clock cycle
 *  0b1..The CS interval unit is 256 serial clock cycle
 */
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK          (0xFFFF0000U)
#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT         (16U)
#define FLEXSPI_FLSHCR1_CSINTERVAL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
/*! @} */

/* The count of FLEXSPI_FLSHCR1 */
#define FLEXSPI_FLSHCR1_COUNT                    (4U)

/*! @name FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2 */
/*! @{ */
#define FLEXSPI_FLSHCR2_ARDSEQID_MASK            (0x1FU)
#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT           (0U)
#define FLEXSPI_FLSHCR2_ARDSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK           (0xE0U)
#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT          (5U)
#define FLEXSPI_FLSHCR2_ARDSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
#define FLEXSPI_FLSHCR2_AWRSEQID_MASK            (0x1F00U)
#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT           (8U)
#define FLEXSPI_FLSHCR2_AWRSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK           (0xE000U)
#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT          (13U)
#define FLEXSPI_FLSHCR2_AWRSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
#define FLEXSPI_FLSHCR2_AWRWAIT_MASK             (0xFFF0000U)
#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT            (16U)
#define FLEXSPI_FLSHCR2_AWRWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK         (0x70000000U)
#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT        (28U)
/*! AWRWAITUNIT - AWRWAIT unit
 *  0b000..The AWRWAIT unit is 2 ahb clock cycle
 *  0b001..The AWRWAIT unit is 8 ahb clock cycle
 *  0b010..The AWRWAIT unit is 32 ahb clock cycle
 *  0b011..The AWRWAIT unit is 128 ahb clock cycle
 *  0b100..The AWRWAIT unit is 512 ahb clock cycle
 *  0b101..The AWRWAIT unit is 2048 ahb clock cycle
 *  0b110..The AWRWAIT unit is 8192 ahb clock cycle
 *  0b111..The AWRWAIT unit is 32768 ahb clock cycle
 */
#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK         (0x80000000U)
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT        (31U)
#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
/*! @} */

/* The count of FLEXSPI_FLSHCR2 */
#define FLEXSPI_FLSHCR2_COUNT                    (4U)

/*! @name FLSHCR3 - Flash Control Register 3 */
/*! @{ */
#define FLEXSPI_FLSHCR3_SIODOIDLE_MASK           (0xFFU)
#define FLEXSPI_FLSHCR3_SIODOIDLE_SHIFT          (0U)
#define FLEXSPI_FLSHCR3_SIODOIDLE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR3_SIODOIDLE_SHIFT)) & FLEXSPI_FLSHCR3_SIODOIDLE_MASK)
#define FLEXSPI_FLSHCR3_SIODONONIDLE_MASK        (0xFF00U)
#define FLEXSPI_FLSHCR3_SIODONONIDLE_SHIFT       (8U)
#define FLEXSPI_FLSHCR3_SIODONONIDLE(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR3_SIODONONIDLE_SHIFT)) & FLEXSPI_FLSHCR3_SIODONONIDLE_MASK)
#define FLEXSPI_FLSHCR3_SIOOEIDLE_MASK           (0xFF0000U)
#define FLEXSPI_FLSHCR3_SIOOEIDLE_SHIFT          (16U)
#define FLEXSPI_FLSHCR3_SIOOEIDLE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR3_SIOOEIDLE_SHIFT)) & FLEXSPI_FLSHCR3_SIOOEIDLE_MASK)
#define FLEXSPI_FLSHCR3_SIOOENONIDLE_MASK        (0xFF000000U)
#define FLEXSPI_FLSHCR3_SIOOENONIDLE_SHIFT       (24U)
#define FLEXSPI_FLSHCR3_SIOOENONIDLE(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR3_SIOOENONIDLE_SHIFT)) & FLEXSPI_FLSHCR3_SIOOENONIDLE_MASK)
/*! @} */

/*! @name FLSHCR4 - Flash Control Register 4 */
/*! @{ */
#define FLEXSPI_FLSHCR4_WMOPT1_MASK              (0x1U)
#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT             (0U)
/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
 *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode.
 *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode.
 */
#define FLEXSPI_FLSHCR4_WMOPT1(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
#define FLEXSPI_FLSHCR4_WMENA_MASK               (0x4U)
#define FLEXSPI_FLSHCR4_WMENA_SHIFT              (2U)
/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set.
 *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
 *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
 */
#define FLEXSPI_FLSHCR4_WMENA(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
#define FLEXSPI_FLSHCR4_WMENB_MASK               (0x8U)
#define FLEXSPI_FLSHCR4_WMENB_SHIFT              (3U)
/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set.
 *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
 *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
 */
#define FLEXSPI_FLSHCR4_WMENB(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
#define FLEXSPI_FLSHCR4_SCKRSTDISABLED_MASK      (0x10U)
#define FLEXSPI_FLSHCR4_SCKRSTDISABLED_SHIFT     (4U)
/*! SCKRSTDISABLED - Reset the SCK to default level before PCS signal is desserted. Generally, this bit should not be touched.
 *  0b0..SCK will be reseted to return to default level before PCS signal is desserted.
 *  0b1..SCK will be reseted to return to default level after PCS signal is deseerted.
 */
#define FLEXSPI_FLSHCR4_SCKRSTDISABLED(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_SCKRSTDISABLED_SHIFT)) & FLEXSPI_FLSHCR4_SCKRSTDISABLED_MASK)
/*! @} */

/*! @name IPCR0 - IP Control Register 0 */
/*! @{ */
#define FLEXSPI_IPCR0_SFAR_MASK                  (0xFFFFFFFFU)
#define FLEXSPI_IPCR0_SFAR_SHIFT                 (0U)
#define FLEXSPI_IPCR0_SFAR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
/*! @} */

/*! @name IPCR1 - IP Control Register 1 */
/*! @{ */
#define FLEXSPI_IPCR1_IDATSZ_MASK                (0xFFFFU)
#define FLEXSPI_IPCR1_IDATSZ_SHIFT               (0U)
#define FLEXSPI_IPCR1_IDATSZ(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
#define FLEXSPI_IPCR1_ISEQID_MASK                (0x1F0000U)
#define FLEXSPI_IPCR1_ISEQID_SHIFT               (16U)
#define FLEXSPI_IPCR1_ISEQID(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
#define FLEXSPI_IPCR1_ISEQNUM_MASK               (0x7000000U)
#define FLEXSPI_IPCR1_ISEQNUM_SHIFT              (24U)
#define FLEXSPI_IPCR1_ISEQNUM(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
#define FLEXSPI_IPCR1_IPAREN_MASK                (0x80000000U)
#define FLEXSPI_IPCR1_IPAREN_SHIFT               (31U)
/*! IPAREN - Parallel mode Enabled for IP command.
 *  0b0..Flash will be accessed in Individual mode.
 *  0b1..Flash will be accessed in Parallel mode.
 */
#define FLEXSPI_IPCR1_IPAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
/*! @} */

/*! @name IPCMD - IP Command Register */
/*! @{ */
#define FLEXSPI_IPCMD_TRG_MASK                   (0x1U)
#define FLEXSPI_IPCMD_TRG_SHIFT                  (0U)
#define FLEXSPI_IPCMD_TRG(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
/*! @} */

/*! @name DLPR - Data Learn Pattern Register */
/*! @{ */
#define FLEXSPI_DLPR_DLP_MASK                    (0xFFFFFFFFU)
#define FLEXSPI_DLPR_DLP_SHIFT                   (0U)
#define FLEXSPI_DLPR_DLP(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK)
/*! @} */

/*! @name IPRXFCR - IP RX FIFO Control Register */
/*! @{ */
#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK            (0x1U)
#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT           (0U)
#define FLEXSPI_IPRXFCR_CLRIPRXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
#define FLEXSPI_IPRXFCR_RXDMAEN_MASK             (0x2U)
#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT            (1U)
/*! RXDMAEN - IP RX FIFO reading by DMA enabled.
 *  0b0..IP RX FIFO would be read by processor.
 *  0b1..IP RX FIFO would be read by DMA.
 */
#define FLEXSPI_IPRXFCR_RXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
#define FLEXSPI_IPRXFCR_RXWMRK_MASK              (0xFCU)
#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT             (2U)
#define FLEXSPI_IPRXFCR_RXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
/*! @} */

/*! @name IPTXFCR - IP TX FIFO Control Register */
/*! @{ */
#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK            (0x1U)
#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT           (0U)
#define FLEXSPI_IPTXFCR_CLRIPTXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
#define FLEXSPI_IPTXFCR_TXDMAEN_MASK             (0x2U)
#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT            (1U)
/*! TXDMAEN - IP TX FIFO filling by DMA enabled.
 *  0b0..IP TX FIFO would be filled by processor.
 *  0b1..IP TX FIFO would be filled by DMA.
 */
#define FLEXSPI_IPTXFCR_TXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
#define FLEXSPI_IPTXFCR_TXWMRK_MASK              (0x1FCU)
#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT             (2U)
#define FLEXSPI_IPTXFCR_TXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
/*! @} */

/*! @name DLLCR - DLL Control Register 0 */
/*! @{ */
#define FLEXSPI_DLLCR_DLLEN_MASK                 (0x1U)
#define FLEXSPI_DLLCR_DLLEN_SHIFT                (0U)
#define FLEXSPI_DLLCR_DLLEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
#define FLEXSPI_DLLCR_DLLRESET_MASK              (0x2U)
#define FLEXSPI_DLLCR_DLLRESET_SHIFT             (1U)
#define FLEXSPI_DLLCR_DLLRESET(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
#define FLEXSPI_DLLCR_FORCEUPDATE_MASK           (0x4U)
#define FLEXSPI_DLLCR_FORCEUPDATE_SHIFT          (2U)
#define FLEXSPI_DLLCR_FORCEUPDATE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_FORCEUPDATE_SHIFT)) & FLEXSPI_DLLCR_FORCEUPDATE_MASK)
#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK          (0x78U)
#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT         (3U)
#define FLEXSPI_DLLCR_SLVDLYTARGET(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
#define FLEXSPI_DLLCR_GATEUPDATE_MASK            (0x80U)
#define FLEXSPI_DLLCR_GATEUPDATE_SHIFT           (7U)
#define FLEXSPI_DLLCR_GATEUPDATE(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_GATEUPDATE_SHIFT)) & FLEXSPI_DLLCR_GATEUPDATE_MASK)
#define FLEXSPI_DLLCR_OVRDEN_MASK                (0x100U)
#define FLEXSPI_DLLCR_OVRDEN_SHIFT               (8U)
#define FLEXSPI_DLLCR_OVRDEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
#define FLEXSPI_DLLCR_OVRDVAL_MASK               (0x7E00U)
#define FLEXSPI_DLLCR_OVRDVAL_SHIFT              (9U)
#define FLEXSPI_DLLCR_OVRDVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
#define FLEXSPI_DLLCR_REFPHASEGAP_MASK           (0x18000U)
#define FLEXSPI_DLLCR_REFPHASEGAP_SHIFT          (15U)
#define FLEXSPI_DLLCR_REFPHASEGAP(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASEGAP_SHIFT)) & FLEXSPI_DLLCR_REFPHASEGAP_MASK)
#define FLEXSPI_DLLCR_REFPHASESTART_MASK         (0xE0000U)
#define FLEXSPI_DLLCR_REFPHASESTART_SHIFT        (17U)
#define FLEXSPI_DLLCR_REFPHASESTART(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASESTART_SHIFT)) & FLEXSPI_DLLCR_REFPHASESTART_MASK)
#define FLEXSPI_DLLCR_SLVUPDATEINT_MASK          (0xFF00000U)
#define FLEXSPI_DLLCR_SLVUPDATEINT_SHIFT         (20U)
#define FLEXSPI_DLLCR_SLVUPDATEINT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVUPDATEINT_SHIFT)) & FLEXSPI_DLLCR_SLVUPDATEINT_MASK)
#define FLEXSPI_DLLCR_REFUPDATEINT_MASK          (0xF0000000U)
#define FLEXSPI_DLLCR_REFUPDATEINT_SHIFT         (28U)
#define FLEXSPI_DLLCR_REFUPDATEINT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFUPDATEINT_SHIFT)) & FLEXSPI_DLLCR_REFUPDATEINT_MASK)
/*! @} */

/* The count of FLEXSPI_DLLCR */
#define FLEXSPI_DLLCR_COUNT                      (2U)

/*! @name MISCCR2 - Misc Control Register 2 */
/*! @{ */
#define FLEXSPI_MISCCR2_LEARNPHASEGAP_MASK       (0x3U)
#define FLEXSPI_MISCCR2_LEARNPHASEGAP_SHIFT      (0U)
/*! LEARNPHASEGAP - The clock phase gap for data learning is: N delay cells delay (75ps~200ps for each delay cell).
 *  0b00..N=2
 *  0b01..N=3
 *  0b10..N=4
 *  0b11..N=5
 */
#define FLEXSPI_MISCCR2_LEARNPHASEGAP(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR2_LEARNPHASEGAP_SHIFT)) & FLEXSPI_MISCCR2_LEARNPHASEGAP_MASK)
#define FLEXSPI_MISCCR2_PHASERSTOPT_MASK         (0xCU)
#define FLEXSPI_MISCCR2_PHASERSTOPT_SHIFT        (2U)
/*! PHASERSTOPT - SCK/DQS output clock phase may need reset after a DDR sequence finished (high level). FlexSPI controller will auto reset the clock phase.
 *  0b00..SCK/DQS output phase will be reset 0.5 cycle after CS de-assertion
 *  0b01..SCK/DQS output phase will be reset 1.5 cycle after CS de-assertion
 *  0b10..SCK/DQS output phase will be reset 2.5 cycle after CS de-assertion
 *  0b11..SCK/DQS output phase will be reset 3.5 cycle after CS de-assertion
 */
#define FLEXSPI_MISCCR2_PHASERSTOPT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR2_PHASERSTOPT_SHIFT)) & FLEXSPI_MISCCR2_PHASERSTOPT_MASK)
#define FLEXSPI_MISCCR2_DOEOPT_MASK              (0x10U)
#define FLEXSPI_MISCCR2_DOEOPT_SHIFT             (4U)
/*! DOEOPT - FlexSPI controller could delay the data lines output enable desertion by one cycle to relax transmit timing.
 *  0b0..Data line output enable desertion is delayed by one cycle
 *  0b1..Data line output enable desertion is not delayed by one cycle
 */
#define FLEXSPI_MISCCR2_DOEOPT(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR2_DOEOPT_SHIFT)) & FLEXSPI_MISCCR2_DOEOPT_MASK)
#define FLEXSPI_MISCCR2_RWDSOEOPT_MASK           (0x20U)
#define FLEXSPI_MISCCR2_RWDSOEOPT_SHIFT          (5U)
/*! RWDSOEOPT - FlexSPI controller could delay the RWDS (write mask) output enable desertion by one cycle to relax transmit timing.
 *  0b0..RWDS output enable desertion is delayed by one cycle
 *  0b1..RWDS output enable desertion is not delayed by one cycle
 */
#define FLEXSPI_MISCCR2_RWDSOEOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR2_RWDSOEOPT_SHIFT)) & FLEXSPI_MISCCR2_RWDSOEOPT_MASK)
/*! @} */

/*! @name STS0 - Status Register 0 */
/*! @{ */
#define FLEXSPI_STS0_SEQIDLE_MASK                (0x1U)
#define FLEXSPI_STS0_SEQIDLE_SHIFT               (0U)
#define FLEXSPI_STS0_SEQIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
#define FLEXSPI_STS0_ARBIDLE_MASK                (0x2U)
#define FLEXSPI_STS0_ARBIDLE_SHIFT               (1U)
#define FLEXSPI_STS0_ARBIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
#define FLEXSPI_STS0_ARBCMDSRC_MASK              (0xCU)
#define FLEXSPI_STS0_ARBCMDSRC_SHIFT             (2U)
/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
 *  0b00..Triggered by AHB read command (triggered by AHB read).
 *  0b01..Triggered by AHB write command (triggered by AHB Write).
 *  0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
 *  0b11..Triggered by suspended command (resumed).
 */
#define FLEXSPI_STS0_ARBCMDSRC(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
#define FLEXSPI_STS0_DATALEARNPHASEA_MASK        (0xF0U)
#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT       (4U)
#define FLEXSPI_STS0_DATALEARNPHASEA(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK)
#define FLEXSPI_STS0_DATALEARNPHASEB_MASK        (0xF00U)
#define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT       (8U)
#define FLEXSPI_STS0_DATALEARNPHASEB(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK)
/*! @} */

/*! @name STS1 - Status Register 1 */
/*! @{ */
#define FLEXSPI_STS1_AHBCMDERRID_MASK            (0x1FU)
#define FLEXSPI_STS1_AHBCMDERRID_SHIFT           (0U)
#define FLEXSPI_STS1_AHBCMDERRID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
#define FLEXSPI_STS1_AHBCMDERRCODE_MASK          (0xF00U)
#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT         (8U)
/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
 *  0b0000..No error.
 *  0b0001..Write/Read data size is not a multiple of 2 bytes while parallel mode is enabled (APAREN=0x1). This error only occur when FLSHCR4.WMOPT is set to 1.
 *  0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
 *  0b0011..There is unknown instruction opcode in the sequence.
 *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
 *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
 *  0b1110..Sequence execution timeout.
 */
#define FLEXSPI_STS1_AHBCMDERRCODE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
#define FLEXSPI_STS1_IPCMDERRID_MASK             (0x1F0000U)
#define FLEXSPI_STS1_IPCMDERRID_SHIFT            (16U)
#define FLEXSPI_STS1_IPCMDERRID(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
#define FLEXSPI_STS1_IPCMDERRCODE_MASK           (0xF000000U)
#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT          (24U)
/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c).
 *  0b0000..No error.
 *  0b0001..Write/Read data size is not a multiple of 2 bytes while parallel mode is enabled (IPAREN=0x1). This error only occur when FLSHCR4.WMOPT is set to 1.
 *  0b0010..IP command with JMP_ON_CS instruction used in the sequence.
 *  0b0011..There is unknown instruction opcode in the sequence.
 *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
 *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
 *  0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
 *  0b1110..Sequence execution timeout.
 *  0b1111..Flash boundary crossed.
 */
#define FLEXSPI_STS1_IPCMDERRCODE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
/*! @} */

/*! @name STS2 - Status Register 2 */
/*! @{ */
#define FLEXSPI_STS2_ASLVLOCK_MASK               (0x1U)
#define FLEXSPI_STS2_ASLVLOCK_SHIFT              (0U)
#define FLEXSPI_STS2_ASLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
#define FLEXSPI_STS2_AREFLOCK_MASK               (0x2U)
#define FLEXSPI_STS2_AREFLOCK_SHIFT              (1U)
#define FLEXSPI_STS2_AREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
#define FLEXSPI_STS2_ASLVSEL_MASK                (0xFCU)
#define FLEXSPI_STS2_ASLVSEL_SHIFT               (2U)
#define FLEXSPI_STS2_ASLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
#define FLEXSPI_STS2_AREFSEL_MASK                (0x3F00U)
#define FLEXSPI_STS2_AREFSEL_SHIFT               (8U)
#define FLEXSPI_STS2_AREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
#define FLEXSPI_STS2_BSLVLOCK_MASK               (0x10000U)
#define FLEXSPI_STS2_BSLVLOCK_SHIFT              (16U)
#define FLEXSPI_STS2_BSLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
#define FLEXSPI_STS2_BREFLOCK_MASK               (0x20000U)
#define FLEXSPI_STS2_BREFLOCK_SHIFT              (17U)
#define FLEXSPI_STS2_BREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
#define FLEXSPI_STS2_BSLVSEL_MASK                (0xFC0000U)
#define FLEXSPI_STS2_BSLVSEL_SHIFT               (18U)
#define FLEXSPI_STS2_BSLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
#define FLEXSPI_STS2_BREFSEL_MASK                (0x3F000000U)
#define FLEXSPI_STS2_BREFSEL_SHIFT               (24U)
#define FLEXSPI_STS2_BREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
/*! @} */

/*! @name AHBSPNDSTS - AHB Suspend Status Register */
/*! @{ */
#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK           (0x1U)
#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT          (0U)
#define FLEXSPI_AHBSPNDSTS_ACTIVE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
#define FLEXSPI_AHBSPNDSTS_BUFID_MASK            (0xEU)
#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT           (1U)
#define FLEXSPI_AHBSPNDSTS_BUFID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK           (0xFFFF0000U)
#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT          (16U)
#define FLEXSPI_AHBSPNDSTS_DATLFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
/*! @} */

/*! @name IPRXFSTS - IP RX FIFO Status Register */
/*! @{ */
#define FLEXSPI_IPRXFSTS_FILL_MASK               (0xFFU)
#define FLEXSPI_IPRXFSTS_FILL_SHIFT              (0U)
#define FLEXSPI_IPRXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
#define FLEXSPI_IPRXFSTS_RDCNTR_MASK             (0xFFFF0000U)
#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT            (16U)
#define FLEXSPI_IPRXFSTS_RDCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
/*! @} */

/*! @name IPTXFSTS - IP TX FIFO Status Register */
/*! @{ */
#define FLEXSPI_IPTXFSTS_FILL_MASK               (0xFFU)
#define FLEXSPI_IPTXFSTS_FILL_SHIFT              (0U)
#define FLEXSPI_IPTXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
#define FLEXSPI_IPTXFSTS_WRCNTR_MASK             (0xFFFF0000U)
#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT            (16U)
#define FLEXSPI_IPTXFSTS_WRCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
/*! @} */

/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
/*! @{ */
#define FLEXSPI_RFDR_RXDATA_MASK                 (0xFFFFFFFFU)
#define FLEXSPI_RFDR_RXDATA_SHIFT                (0U)
#define FLEXSPI_RFDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
/*! @} */

/* The count of FLEXSPI_RFDR */
#define FLEXSPI_RFDR_COUNT                       (32U)

/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
/*! @{ */
#define FLEXSPI_TFDR_TXDATA_MASK                 (0xFFFFFFFFU)
#define FLEXSPI_TFDR_TXDATA_SHIFT                (0U)
#define FLEXSPI_TFDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
/*! @} */

/* The count of FLEXSPI_TFDR */
#define FLEXSPI_TFDR_COUNT                       (32U)

/*! @name LUT - LUT 0..LUT 127 */
/*! @{ */
#define FLEXSPI_LUT_OPERAND0_MASK                (0xFFU)
#define FLEXSPI_LUT_OPERAND0_SHIFT               (0U)
#define FLEXSPI_LUT_OPERAND0(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
#define FLEXSPI_LUT_NUM_PADS0_MASK               (0x300U)
#define FLEXSPI_LUT_NUM_PADS0_SHIFT              (8U)
#define FLEXSPI_LUT_NUM_PADS0(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
#define FLEXSPI_LUT_OPCODE0_MASK                 (0xFC00U)
#define FLEXSPI_LUT_OPCODE0_SHIFT                (10U)
#define FLEXSPI_LUT_OPCODE0(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
#define FLEXSPI_LUT_OPERAND1_MASK                (0xFF0000U)
#define FLEXSPI_LUT_OPERAND1_SHIFT               (16U)
#define FLEXSPI_LUT_OPERAND1(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
#define FLEXSPI_LUT_NUM_PADS1_MASK               (0x3000000U)
#define FLEXSPI_LUT_NUM_PADS1_SHIFT              (24U)
#define FLEXSPI_LUT_NUM_PADS1(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
#define FLEXSPI_LUT_OPCODE1_MASK                 (0xFC000000U)
#define FLEXSPI_LUT_OPCODE1_SHIFT                (26U)
#define FLEXSPI_LUT_OPCODE1(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
/*! @} */

/* The count of FLEXSPI_LUT */
#define FLEXSPI_LUT_COUNT                        (128U)


/*!
 * @}
 */ /* end of group FLEXSPI_Register_Masks */


/* FLEXSPI - Peripheral instance base addresses */
/** Peripheral LSIO__FLEXSPI0 base address */
#define LSIO__FLEXSPI0_BASE                      (0x5D120000u)
/** Peripheral LSIO__FLEXSPI0 base pointer */
#define LSIO__FLEXSPI0                           ((FLEXSPI_Type *)LSIO__FLEXSPI0_BASE)
/** Peripheral LSIO__FLEXSPI1 base address */
#define LSIO__FLEXSPI1_BASE                      (0x5D130000u)
/** Peripheral LSIO__FLEXSPI1 base pointer */
#define LSIO__FLEXSPI1                           ((FLEXSPI_Type *)LSIO__FLEXSPI1_BASE)
/** Array initializer of FLEXSPI peripheral base addresses */
#define FLEXSPI_BASE_ADDRS                       { LSIO__FLEXSPI0_BASE, LSIO__FLEXSPI1_BASE }
/** Array initializer of FLEXSPI peripheral base pointers */
#define FLEXSPI_BASE_PTRS                        { LSIO__FLEXSPI0, LSIO__FLEXSPI1 }
/** Interrupt vectors for the FLEXSPI peripheral type */
#define FLEXSPI_IRQS                             { LSIO_OCTASPI0_INT_IRQn, LSIO_OCTASPI1_INT_IRQn }
/* FlexSPI0 AMBA address. */
#define FlexSPI0_AMBA_BASE                       (0x08000000U)


/*!
 * @}
 */ /* end of group FLEXSPI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FTM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
 * @{
 */

/** FTM - Register Layout Typedef */
typedef struct {
  __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
  struct {                                         /* offset: 0xC, array step: 0x8 */
    __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
  } CONTROLS[8];
  __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
  __IO uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
  __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
  __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
  __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
  __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
  __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
  __IO uint32_t DEADTIME;                          /**< Deadtime Configuration, offset: 0x68 */
  __IO uint32_t EXTTRIG;                           /**< FTM External Trigger, offset: 0x6C */
  __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
  __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
  __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
  __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control And Status, offset: 0x80 */
  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
  __IO uint32_t FLTPOL;                            /**< FTM Fault Input Polarity, offset: 0x88 */
  __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
  __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
  __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
  __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
  __IO uint32_t HCR;                               /**< Half Cycle Register, offset: 0x9C */
       uint8_t RESERVED_0[352];
  __IO uint32_t MOD_MIRROR;                        /**< Mirror of Modulo Value, offset: 0x200 */
  __IO uint32_t CV_MIRROR[8];                      /**< Mirror of Channel (n) Match Value, array offset: 0x204, array step: 0x4 */
} FTM_Type;

/* ----------------------------------------------------------------------------
   -- FTM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FTM_Register_Masks FTM Register Masks
 * @{
 */

/*! @name SC - Status And Control */
/*! @{ */
#define FTM_SC_PS_MASK                           (0x7U)
#define FTM_SC_PS_SHIFT                          (0U)
/*! PS - Prescale Factor Selection
 *  0b000..Divide by 1
 *  0b001..Divide by 2
 *  0b010..Divide by 4
 *  0b011..Divide by 8
 *  0b100..Divide by 16
 *  0b101..Divide by 32
 *  0b110..Divide by 64
 *  0b111..Divide by 128
 */
#define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
#define FTM_SC_CLKS_MASK                         (0x18U)
#define FTM_SC_CLKS_SHIFT                        (3U)
/*! CLKS - Clock Source Selection
 *  0b00..No clock selected. This in effect disables the FTM counter.
 *  0b01..FTM input clock
 *  0b10..Fixed frequency clock
 *  0b11..External clock
 */
#define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
#define FTM_SC_CPWMS_MASK                        (0x20U)
#define FTM_SC_CPWMS_SHIFT                       (5U)
/*! CPWMS - Center-Aligned PWM Select
 *  0b0..FTM counter operates in Up Counting mode.
 *  0b1..FTM counter operates in Up-Down Counting mode.
 */
#define FTM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
#define FTM_SC_RIE_MASK                          (0x40U)
#define FTM_SC_RIE_SHIFT                         (6U)
/*! RIE - Reload Point Interrupt Enable
 *  0b0..Reload point interrupt is disabled.
 *  0b1..Reload point interrupt is enabled.
 */
#define FTM_SC_RIE(x)                            (((uint32_t)(((uint32_t)(x)) << FTM_SC_RIE_SHIFT)) & FTM_SC_RIE_MASK)
#define FTM_SC_RF_MASK                           (0x80U)
#define FTM_SC_RF_SHIFT                          (7U)
/*! RF - Reload Flag
 *  0b0..A selected reload point did not happen.
 *  0b1..A selected reload point happened.
 */
#define FTM_SC_RF(x)                             (((uint32_t)(((uint32_t)(x)) << FTM_SC_RF_SHIFT)) & FTM_SC_RF_MASK)
#define FTM_SC_TOIE_MASK                         (0x100U)
#define FTM_SC_TOIE_SHIFT                        (8U)
/*! TOIE - Timer Overflow Interrupt Enable
 *  0b0..Disable TOF interrupts. Use software polling.
 *  0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
 */
#define FTM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
#define FTM_SC_TOF_MASK                          (0x200U)
#define FTM_SC_TOF_SHIFT                         (9U)
/*! TOF - Timer Overflow Flag
 *  0b0..FTM counter has not overflowed.
 *  0b1..FTM counter has overflowed.
 */
#define FTM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
#define FTM_SC_PWMEN0_MASK                       (0x10000U)
#define FTM_SC_PWMEN0_SHIFT                      (16U)
/*! PWMEN0 - Channel 0 PWM enable bit
 *  0b0..Channel output port is disabled.
 *  0b1..Channel output port is enabled.
 */
#define FTM_SC_PWMEN0(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN0_SHIFT)) & FTM_SC_PWMEN0_MASK)
#define FTM_SC_PWMEN1_MASK                       (0x20000U)
#define FTM_SC_PWMEN1_SHIFT                      (17U)
/*! PWMEN1 - Channel 1 PWM enable bit
 *  0b0..Channel output port is disabled.
 *  0b1..Channel output port is enabled.
 */
#define FTM_SC_PWMEN1(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN1_SHIFT)) & FTM_SC_PWMEN1_MASK)
#define FTM_SC_PWMEN2_MASK                       (0x40000U)
#define FTM_SC_PWMEN2_SHIFT                      (18U)
/*! PWMEN2 - Channel 2 PWM enable bit
 *  0b0..Channel output port is disabled.
 *  0b1..Channel output port is enabled.
 */
#define FTM_SC_PWMEN2(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN2_SHIFT)) & FTM_SC_PWMEN2_MASK)
#define FTM_SC_PWMEN3_MASK                       (0x80000U)
#define FTM_SC_PWMEN3_SHIFT                      (19U)
/*! PWMEN3 - Channel 3 PWM enable bit
 *  0b0..Channel output port is disabled.
 *  0b1..Channel output port is enabled.
 */
#define FTM_SC_PWMEN3(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN3_SHIFT)) & FTM_SC_PWMEN3_MASK)
#define FTM_SC_PWMEN4_MASK                       (0x100000U)
#define FTM_SC_PWMEN4_SHIFT                      (20U)
/*! PWMEN4 - Channel 4 PWM enable bit
 *  0b0..Channel output port is disabled.
 *  0b1..Channel output port is enabled.
 */
#define FTM_SC_PWMEN4(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN4_SHIFT)) & FTM_SC_PWMEN4_MASK)
#define FTM_SC_PWMEN5_MASK                       (0x200000U)
#define FTM_SC_PWMEN5_SHIFT                      (21U)
/*! PWMEN5 - Channel 5 PWM enable bit
 *  0b0..Channel output port is disabled.
 *  0b1..Channel output port is enabled.
 */
#define FTM_SC_PWMEN5(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN5_SHIFT)) & FTM_SC_PWMEN5_MASK)
#define FTM_SC_PWMEN6_MASK                       (0x400000U)
#define FTM_SC_PWMEN6_SHIFT                      (22U)
/*! PWMEN6 - Channel 6 PWM enable bit
 *  0b0..Channel output port is disabled.
 *  0b1..Channel output port is enabled.
 */
#define FTM_SC_PWMEN6(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN6_SHIFT)) & FTM_SC_PWMEN6_MASK)
#define FTM_SC_PWMEN7_MASK                       (0x800000U)
#define FTM_SC_PWMEN7_SHIFT                      (23U)
/*! PWMEN7 - Channel 7 PWM enable bit
 *  0b0..Channel output port is disabled.
 *  0b1..Channel output port is enabled.
 */
#define FTM_SC_PWMEN7(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN7_SHIFT)) & FTM_SC_PWMEN7_MASK)
#define FTM_SC_FLTPS_MASK                        (0xF000000U)
#define FTM_SC_FLTPS_SHIFT                       (24U)
/*! FLTPS - Filter Prescaler
 *  0b0000..Divide by 1
 *  0b0001..Divide by 2
 *  0b0010..Divide by 3
 *  0b0011..Divide by 4
 *  0b0100..Divide by 5
 *  0b0101..Divide by 6
 *  0b0110..Divide by 7
 *  0b0111..Divide by 8
 *  0b1000..Divide by 9
 *  0b1001..Divide by 10
 *  0b1010..Divide by 11
 *  0b1011..Divide by 12
 *  0b1100..Divide by 13
 *  0b1101..Divide by 14
 *  0b1110..Divide by 15
 *  0b1111..Divide by 16
 */
#define FTM_SC_FLTPS(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_SC_FLTPS_SHIFT)) & FTM_SC_FLTPS_MASK)
/*! @} */

/*! @name CNT - Counter */
/*! @{ */
#define FTM_CNT_COUNT_MASK                       (0xFFFFU)
#define FTM_CNT_COUNT_SHIFT                      (0U)
#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
/*! @} */

/*! @name MOD - Modulo */
/*! @{ */
#define FTM_MOD_MOD_MASK                         (0xFFFFU)
#define FTM_MOD_MOD_SHIFT                        (0U)
#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
/*! @} */

/*! @name CnSC - Channel (n) Status And Control */
/*! @{ */
#define FTM_CnSC_DMA_MASK                        (0x1U)
#define FTM_CnSC_DMA_SHIFT                       (0U)
/*! DMA - DMA Enable
 *  0b0..Disable DMA transfers.
 *  0b1..Enable DMA transfers.
 */
#define FTM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
#define FTM_CnSC_ICRST_MASK                      (0x2U)
#define FTM_CnSC_ICRST_SHIFT                     (1U)
/*! ICRST - FTM counter reset by the selected input capture event.
 *  0b0..FTM counter is not reset when the selected channel (n) input event is detected.
 *  0b1..FTM counter is reset when the selected channel (n) input event is detected.
 */
#define FTM_CnSC_ICRST(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK)
#define FTM_CnSC_ELSA_MASK                       (0x4U)
#define FTM_CnSC_ELSA_SHIFT                      (2U)
#define FTM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
#define FTM_CnSC_ELSB_MASK                       (0x8U)
#define FTM_CnSC_ELSB_SHIFT                      (3U)
#define FTM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
#define FTM_CnSC_MSA_MASK                        (0x10U)
#define FTM_CnSC_MSA_SHIFT                       (4U)
#define FTM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
#define FTM_CnSC_MSB_MASK                        (0x20U)
#define FTM_CnSC_MSB_SHIFT                       (5U)
#define FTM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
#define FTM_CnSC_CHIE_MASK                       (0x40U)
#define FTM_CnSC_CHIE_SHIFT                      (6U)
/*! CHIE - Channel (n) Interrupt Enable
 *  0b0..Disable channel (n) interrupt. Use software polling.
 *  0b1..Enable channel (n) interrupt.
 */
#define FTM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
#define FTM_CnSC_CHF_MASK                        (0x80U)
#define FTM_CnSC_CHF_SHIFT                       (7U)
/*! CHF - Channel (n) Flag
 *  0b0..No channel (n) event has occurred.
 *  0b1..A channel (n) event has occurred.
 */
#define FTM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
#define FTM_CnSC_TRIGMODE_MASK                   (0x100U)
#define FTM_CnSC_TRIGMODE_SHIFT                  (8U)
/*! TRIGMODE - Trigger mode control
 *  0b0..Channel outputs will generate the normal PWM outputs without generating a pulse.
 *  0b1..If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
 */
#define FTM_CnSC_TRIGMODE(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_TRIGMODE_SHIFT)) & FTM_CnSC_TRIGMODE_MASK)
#define FTM_CnSC_CHIS_MASK                       (0x200U)
#define FTM_CnSC_CHIS_SHIFT                      (9U)
/*! CHIS - Channel (n) Input State
 *  0b0..The channel (n) input is zero.
 *  0b1..The channel (n) input is one.
 */
#define FTM_CnSC_CHIS(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIS_SHIFT)) & FTM_CnSC_CHIS_MASK)
#define FTM_CnSC_CHOV_MASK                       (0x400U)
#define FTM_CnSC_CHOV_SHIFT                      (10U)
/*! CHOV - Channel (n) Output Value
 *  0b0..The channel (n) output is zero.
 *  0b1..The channel (n) output is one.
 */
#define FTM_CnSC_CHOV(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHOV_SHIFT)) & FTM_CnSC_CHOV_MASK)
/*! @} */

/* The count of FTM_CnSC */
#define FTM_CnSC_COUNT                           (8U)

/*! @name CnV - Channel (n) Value */
/*! @{ */
#define FTM_CnV_VAL_MASK                         (0xFFFFU)
#define FTM_CnV_VAL_SHIFT                        (0U)
#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
/*! @} */

/* The count of FTM_CnV */
#define FTM_CnV_COUNT                            (8U)

/*! @name CNTIN - Counter Initial Value */
/*! @{ */
#define FTM_CNTIN_INIT_MASK                      (0xFFFFU)
#define FTM_CNTIN_INIT_SHIFT                     (0U)
#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
/*! @} */

/*! @name STATUS - Capture And Compare Status */
/*! @{ */
#define FTM_STATUS_CH0F_MASK                     (0x1U)
#define FTM_STATUS_CH0F_SHIFT                    (0U)
/*! CH0F - Channel 0 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define FTM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
#define FTM_STATUS_CH1F_MASK                     (0x2U)
#define FTM_STATUS_CH1F_SHIFT                    (1U)
/*! CH1F - Channel 1 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define FTM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
#define FTM_STATUS_CH2F_MASK                     (0x4U)
#define FTM_STATUS_CH2F_SHIFT                    (2U)
/*! CH2F - Channel 2 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define FTM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
#define FTM_STATUS_CH3F_MASK                     (0x8U)
#define FTM_STATUS_CH3F_SHIFT                    (3U)
/*! CH3F - Channel 3 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define FTM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
#define FTM_STATUS_CH4F_MASK                     (0x10U)
#define FTM_STATUS_CH4F_SHIFT                    (4U)
/*! CH4F - Channel 4 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define FTM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
#define FTM_STATUS_CH5F_MASK                     (0x20U)
#define FTM_STATUS_CH5F_SHIFT                    (5U)
/*! CH5F - Channel 5 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define FTM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
#define FTM_STATUS_CH6F_MASK                     (0x40U)
#define FTM_STATUS_CH6F_SHIFT                    (6U)
/*! CH6F - Channel 6 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define FTM_STATUS_CH6F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
#define FTM_STATUS_CH7F_MASK                     (0x80U)
#define FTM_STATUS_CH7F_SHIFT                    (7U)
/*! CH7F - Channel 7 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define FTM_STATUS_CH7F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
/*! @} */

/*! @name MODE - Features Mode Selection */
/*! @{ */
#define FTM_MODE_FTMEN_MASK                      (0x1U)
#define FTM_MODE_FTMEN_SHIFT                     (0U)
/*! FTMEN - FTM Enable
 *  0b0..TPM compatibility. Free running counter and synchronization compatible with TPM.
 *  0b1..Free running counter and synchronization are different from TPM behavior.
 */
#define FTM_MODE_FTMEN(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
#define FTM_MODE_INIT_MASK                       (0x2U)
#define FTM_MODE_INIT_SHIFT                      (1U)
#define FTM_MODE_INIT(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
#define FTM_MODE_WPDIS_MASK                      (0x4U)
#define FTM_MODE_WPDIS_SHIFT                     (2U)
/*! WPDIS - Write Protection Disable
 *  0b0..Write protection is enabled.
 *  0b1..Write protection is disabled.
 */
#define FTM_MODE_WPDIS(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
#define FTM_MODE_PWMSYNC_MASK                    (0x8U)
#define FTM_MODE_PWMSYNC_SHIFT                   (3U)
/*! PWMSYNC - PWM Synchronization Mode
 *  0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
 *  0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
 */
#define FTM_MODE_PWMSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
#define FTM_MODE_CAPTEST_MASK                    (0x10U)
#define FTM_MODE_CAPTEST_SHIFT                   (4U)
/*! CAPTEST - Capture Test Mode Enable
 *  0b0..Capture test mode is disabled.
 *  0b1..Capture test mode is enabled.
 */
#define FTM_MODE_CAPTEST(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
#define FTM_MODE_FAULTM_MASK                     (0x60U)
#define FTM_MODE_FAULTM_SHIFT                    (5U)
/*! FAULTM - Fault Control Mode
 *  0b00..Fault control is disabled for all channels.
 *  0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
 *  0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
 *  0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
 */
#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
#define FTM_MODE_FAULTIE_MASK                    (0x80U)
#define FTM_MODE_FAULTIE_SHIFT                   (7U)
/*! FAULTIE - Fault Interrupt Enable
 *  0b0..Fault control interrupt is disabled.
 *  0b1..Fault control interrupt is enabled.
 */
#define FTM_MODE_FAULTIE(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
/*! @} */

/*! @name SYNC - Synchronization */
/*! @{ */
#define FTM_SYNC_CNTMIN_MASK                     (0x1U)
#define FTM_SYNC_CNTMIN_SHIFT                    (0U)
/*! CNTMIN - Minimum Loading Point Enable
 *  0b0..The minimum loading point is disabled.
 *  0b1..The minimum loading point is enabled.
 */
#define FTM_SYNC_CNTMIN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
#define FTM_SYNC_CNTMAX_MASK                     (0x2U)
#define FTM_SYNC_CNTMAX_SHIFT                    (1U)
/*! CNTMAX - Maximum Loading Point Enable
 *  0b0..The maximum loading point is disabled.
 *  0b1..The maximum loading point is enabled.
 */
#define FTM_SYNC_CNTMAX(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
#define FTM_SYNC_REINIT_MASK                     (0x4U)
#define FTM_SYNC_REINIT_SHIFT                    (2U)
/*! REINIT - FTM Counter Reinitialization by Synchronization
 *  0b0..FTM counter continues to count normally.
 *  0b1..FTM counter is updated with its initial value when the selected trigger is detected.
 */
#define FTM_SYNC_REINIT(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
#define FTM_SYNC_SYNCHOM_MASK                    (0x8U)
#define FTM_SYNC_SYNCHOM_SHIFT                   (3U)
/*! SYNCHOM - Output Mask Synchronization
 *  0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the FTM input clock.
 *  0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
 */
#define FTM_SYNC_SYNCHOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
#define FTM_SYNC_TRIG0_MASK                      (0x10U)
#define FTM_SYNC_TRIG0_SHIFT                     (4U)
/*! TRIG0 - PWM Synchronization Hardware Trigger 0
 *  0b0..Trigger is disabled.
 *  0b1..Trigger is enabled.
 */
#define FTM_SYNC_TRIG0(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
#define FTM_SYNC_TRIG1_MASK                      (0x20U)
#define FTM_SYNC_TRIG1_SHIFT                     (5U)
/*! TRIG1 - PWM Synchronization Hardware Trigger 1
 *  0b0..Trigger is disabled.
 *  0b1..Trigger is enabled.
 */
#define FTM_SYNC_TRIG1(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
#define FTM_SYNC_TRIG2_MASK                      (0x40U)
#define FTM_SYNC_TRIG2_SHIFT                     (6U)
/*! TRIG2 - PWM Synchronization Hardware Trigger 2
 *  0b0..Trigger is disabled.
 *  0b1..Trigger is enabled.
 */
#define FTM_SYNC_TRIG2(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
#define FTM_SYNC_SWSYNC_MASK                     (0x80U)
#define FTM_SYNC_SWSYNC_SHIFT                    (7U)
/*! SWSYNC - PWM Synchronization Software Trigger
 *  0b0..Software trigger is not selected.
 *  0b1..Software trigger is selected.
 */
#define FTM_SYNC_SWSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
/*! @} */

/*! @name OUTINIT - Initial State For Channels Output */
/*! @{ */
#define FTM_OUTINIT_CH0OI_MASK                   (0x1U)
#define FTM_OUTINIT_CH0OI_SHIFT                  (0U)
/*! CH0OI - Channel 0 Output Initialization Value
 *  0b0..The initialization value is 0.
 *  0b1..The initialization value is 1.
 */
#define FTM_OUTINIT_CH0OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
#define FTM_OUTINIT_CH1OI_MASK                   (0x2U)
#define FTM_OUTINIT_CH1OI_SHIFT                  (1U)
/*! CH1OI - Channel 1 Output Initialization Value
 *  0b0..The initialization value is 0.
 *  0b1..The initialization value is 1.
 */
#define FTM_OUTINIT_CH1OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
#define FTM_OUTINIT_CH2OI_MASK                   (0x4U)
#define FTM_OUTINIT_CH2OI_SHIFT                  (2U)
/*! CH2OI - Channel 2 Output Initialization Value
 *  0b0..The initialization value is 0.
 *  0b1..The initialization value is 1.
 */
#define FTM_OUTINIT_CH2OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
#define FTM_OUTINIT_CH3OI_MASK                   (0x8U)
#define FTM_OUTINIT_CH3OI_SHIFT                  (3U)
/*! CH3OI - Channel 3 Output Initialization Value
 *  0b0..The initialization value is 0.
 *  0b1..The initialization value is 1.
 */
#define FTM_OUTINIT_CH3OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
#define FTM_OUTINIT_CH4OI_MASK                   (0x10U)
#define FTM_OUTINIT_CH4OI_SHIFT                  (4U)
/*! CH4OI - Channel 4 Output Initialization Value
 *  0b0..The initialization value is 0.
 *  0b1..The initialization value is 1.
 */
#define FTM_OUTINIT_CH4OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
#define FTM_OUTINIT_CH5OI_MASK                   (0x20U)
#define FTM_OUTINIT_CH5OI_SHIFT                  (5U)
/*! CH5OI - Channel 5 Output Initialization Value
 *  0b0..The initialization value is 0.
 *  0b1..The initialization value is 1.
 */
#define FTM_OUTINIT_CH5OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
#define FTM_OUTINIT_CH6OI_MASK                   (0x40U)
#define FTM_OUTINIT_CH6OI_SHIFT                  (6U)
/*! CH6OI - Channel 6 Output Initialization Value
 *  0b0..The initialization value is 0.
 *  0b1..The initialization value is 1.
 */
#define FTM_OUTINIT_CH6OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
#define FTM_OUTINIT_CH7OI_MASK                   (0x80U)
#define FTM_OUTINIT_CH7OI_SHIFT                  (7U)
/*! CH7OI - Channel 7 Output Initialization Value
 *  0b0..The initialization value is 0.
 *  0b1..The initialization value is 1.
 */
#define FTM_OUTINIT_CH7OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
/*! @} */

/*! @name OUTMASK - Output Mask */
/*! @{ */
#define FTM_OUTMASK_CH0OM_MASK                   (0x1U)
#define FTM_OUTMASK_CH0OM_SHIFT                  (0U)
/*! CH0OM - Channel 0 Output Mask
 *  0b0..Channel output is not masked. It continues to operate normally.
 *  0b1..Channel output is masked. It is forced to its inactive state.
 */
#define FTM_OUTMASK_CH0OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
#define FTM_OUTMASK_CH1OM_MASK                   (0x2U)
#define FTM_OUTMASK_CH1OM_SHIFT                  (1U)
/*! CH1OM - Channel 1 Output Mask
 *  0b0..Channel output is not masked. It continues to operate normally.
 *  0b1..Channel output is masked. It is forced to its inactive state.
 */
#define FTM_OUTMASK_CH1OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
#define FTM_OUTMASK_CH2OM_MASK                   (0x4U)
#define FTM_OUTMASK_CH2OM_SHIFT                  (2U)
/*! CH2OM - Channel 2 Output Mask
 *  0b0..Channel output is not masked. It continues to operate normally.
 *  0b1..Channel output is masked. It is forced to its inactive state.
 */
#define FTM_OUTMASK_CH2OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
#define FTM_OUTMASK_CH3OM_MASK                   (0x8U)
#define FTM_OUTMASK_CH3OM_SHIFT                  (3U)
/*! CH3OM - Channel 3 Output Mask
 *  0b0..Channel output is not masked. It continues to operate normally.
 *  0b1..Channel output is masked. It is forced to its inactive state.
 */
#define FTM_OUTMASK_CH3OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
#define FTM_OUTMASK_CH4OM_MASK                   (0x10U)
#define FTM_OUTMASK_CH4OM_SHIFT                  (4U)
/*! CH4OM - Channel 4 Output Mask
 *  0b0..Channel output is not masked. It continues to operate normally.
 *  0b1..Channel output is masked. It is forced to its inactive state.
 */
#define FTM_OUTMASK_CH4OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
#define FTM_OUTMASK_CH5OM_MASK                   (0x20U)
#define FTM_OUTMASK_CH5OM_SHIFT                  (5U)
/*! CH5OM - Channel 5 Output Mask
 *  0b0..Channel output is not masked. It continues to operate normally.
 *  0b1..Channel output is masked. It is forced to its inactive state.
 */
#define FTM_OUTMASK_CH5OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
#define FTM_OUTMASK_CH6OM_MASK                   (0x40U)
#define FTM_OUTMASK_CH6OM_SHIFT                  (6U)
/*! CH6OM - Channel 6 Output Mask
 *  0b0..Channel output is not masked. It continues to operate normally.
 *  0b1..Channel output is masked. It is forced to its inactive state.
 */
#define FTM_OUTMASK_CH6OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
#define FTM_OUTMASK_CH7OM_MASK                   (0x80U)
#define FTM_OUTMASK_CH7OM_SHIFT                  (7U)
/*! CH7OM - Channel 7 Output Mask
 *  0b0..Channel output is not masked. It continues to operate normally.
 *  0b1..Channel output is masked. It is forced to its inactive state.
 */
#define FTM_OUTMASK_CH7OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
/*! @} */

/*! @name COMBINE - Function For Linked Channels */
/*! @{ */
#define FTM_COMBINE_COMBINE0_MASK                (0x1U)
#define FTM_COMBINE_COMBINE0_SHIFT               (0U)
#define FTM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
#define FTM_COMBINE_COMP0_MASK                   (0x2U)
#define FTM_COMBINE_COMP0_SHIFT                  (1U)
/*! COMP0 - Complement Of Channel (n) For n = 0
 *  0b0..The channel (n+1) output is the same as the channel (n) output.
 *  0b1..The channel (n+1) output is the complement of the channel (n) output.
 */
#define FTM_COMBINE_COMP0(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
#define FTM_COMBINE_DECAPEN0_MASK                (0x4U)
#define FTM_COMBINE_DECAPEN0_SHIFT               (2U)
#define FTM_COMBINE_DECAPEN0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
#define FTM_COMBINE_DECAP0_MASK                  (0x8U)
#define FTM_COMBINE_DECAP0_SHIFT                 (3U)
/*! DECAP0 - Dual Edge Capture Mode Captures For n = 0
 *  0b0..The dual edge captures are inactive.
 *  0b1..The dual edge captures are active.
 */
#define FTM_COMBINE_DECAP0(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
#define FTM_COMBINE_DTEN0_MASK                   (0x10U)
#define FTM_COMBINE_DTEN0_SHIFT                  (4U)
/*! DTEN0 - Deadtime Enable For n = 0
 *  0b0..The deadtime insertion in this pair of channels is disabled.
 *  0b1..The deadtime insertion in this pair of channels is enabled.
 */
#define FTM_COMBINE_DTEN0(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
#define FTM_COMBINE_SYNCEN0_MASK                 (0x20U)
#define FTM_COMBINE_SYNCEN0_SHIFT                (5U)
/*! SYNCEN0 - Synchronization Enable For n = 0
 *  0b0..The PWM synchronization in this pair of channels is disabled.
 *  0b1..The PWM synchronization in this pair of channels is enabled.
 */
#define FTM_COMBINE_SYNCEN0(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
#define FTM_COMBINE_FAULTEN0_MASK                (0x40U)
#define FTM_COMBINE_FAULTEN0_SHIFT               (6U)
/*! FAULTEN0 - Fault Control Enable For n = 0
 *  0b0..The fault control in this pair of channels is disabled.
 *  0b1..The fault control in this pair of channels is enabled.
 */
#define FTM_COMBINE_FAULTEN0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
#define FTM_COMBINE_MCOMBINE0_MASK               (0x80U)
#define FTM_COMBINE_MCOMBINE0_SHIFT              (7U)
#define FTM_COMBINE_MCOMBINE0(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE0_SHIFT)) & FTM_COMBINE_MCOMBINE0_MASK)
#define FTM_COMBINE_COMBINE1_MASK                (0x100U)
#define FTM_COMBINE_COMBINE1_SHIFT               (8U)
#define FTM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
#define FTM_COMBINE_COMP1_MASK                   (0x200U)
#define FTM_COMBINE_COMP1_SHIFT                  (9U)
/*! COMP1 - Complement Of Channel (n) For n = 2
 *  0b0..The channel (n+1) output is the same as the channel (n) output.
 *  0b1..The channel (n+1) output is the complement of the channel (n) output.
 */
#define FTM_COMBINE_COMP1(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
#define FTM_COMBINE_DECAPEN1_MASK                (0x400U)
#define FTM_COMBINE_DECAPEN1_SHIFT               (10U)
#define FTM_COMBINE_DECAPEN1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
#define FTM_COMBINE_DECAP1_MASK                  (0x800U)
#define FTM_COMBINE_DECAP1_SHIFT                 (11U)
/*! DECAP1 - Dual Edge Capture Mode Captures For n = 2
 *  0b0..The dual edge captures are inactive.
 *  0b1..The dual edge captures are active.
 */
#define FTM_COMBINE_DECAP1(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
#define FTM_COMBINE_DTEN1_MASK                   (0x1000U)
#define FTM_COMBINE_DTEN1_SHIFT                  (12U)
/*! DTEN1 - Deadtime Enable For n = 2
 *  0b0..The deadtime insertion in this pair of channels is disabled.
 *  0b1..The deadtime insertion in this pair of channels is enabled.
 */
#define FTM_COMBINE_DTEN1(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
#define FTM_COMBINE_SYNCEN1_MASK                 (0x2000U)
#define FTM_COMBINE_SYNCEN1_SHIFT                (13U)
/*! SYNCEN1 - Synchronization Enable For n = 2
 *  0b0..The PWM synchronization in this pair of channels is disabled.
 *  0b1..The PWM synchronization in this pair of channels is enabled.
 */
#define FTM_COMBINE_SYNCEN1(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
#define FTM_COMBINE_FAULTEN1_MASK                (0x4000U)
#define FTM_COMBINE_FAULTEN1_SHIFT               (14U)
/*! FAULTEN1 - Fault Control Enable For n = 2
 *  0b0..The fault control in this pair of channels is disabled.
 *  0b1..The fault control in this pair of channels is enabled.
 */
#define FTM_COMBINE_FAULTEN1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
#define FTM_COMBINE_MCOMBINE1_MASK               (0x8000U)
#define FTM_COMBINE_MCOMBINE1_SHIFT              (15U)
#define FTM_COMBINE_MCOMBINE1(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE1_SHIFT)) & FTM_COMBINE_MCOMBINE1_MASK)
#define FTM_COMBINE_COMBINE2_MASK                (0x10000U)
#define FTM_COMBINE_COMBINE2_SHIFT               (16U)
#define FTM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
#define FTM_COMBINE_COMP2_MASK                   (0x20000U)
#define FTM_COMBINE_COMP2_SHIFT                  (17U)
/*! COMP2 - Complement Of Channel (n) For n = 4
 *  0b0..The channel (n+1) output is the same as the channel (n) output.
 *  0b1..The channel (n+1) output is the complement of the channel (n) output.
 */
#define FTM_COMBINE_COMP2(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
#define FTM_COMBINE_DECAPEN2_MASK                (0x40000U)
#define FTM_COMBINE_DECAPEN2_SHIFT               (18U)
#define FTM_COMBINE_DECAPEN2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
#define FTM_COMBINE_DECAP2_MASK                  (0x80000U)
#define FTM_COMBINE_DECAP2_SHIFT                 (19U)
/*! DECAP2 - Dual Edge Capture Mode Captures For n = 4
 *  0b0..The dual edge captures are inactive.
 *  0b1..The dual edge captures are active.
 */
#define FTM_COMBINE_DECAP2(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
#define FTM_COMBINE_DTEN2_MASK                   (0x100000U)
#define FTM_COMBINE_DTEN2_SHIFT                  (20U)
/*! DTEN2 - Deadtime Enable For n = 4
 *  0b0..The deadtime insertion in this pair of channels is disabled.
 *  0b1..The deadtime insertion in this pair of channels is enabled.
 */
#define FTM_COMBINE_DTEN2(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
#define FTM_COMBINE_SYNCEN2_MASK                 (0x200000U)
#define FTM_COMBINE_SYNCEN2_SHIFT                (21U)
/*! SYNCEN2 - Synchronization Enable For n = 4
 *  0b0..The PWM synchronization in this pair of channels is disabled.
 *  0b1..The PWM synchronization in this pair of channels is enabled.
 */
#define FTM_COMBINE_SYNCEN2(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
#define FTM_COMBINE_FAULTEN2_MASK                (0x400000U)
#define FTM_COMBINE_FAULTEN2_SHIFT               (22U)
/*! FAULTEN2 - Fault Control Enable For n = 4
 *  0b0..The fault control in this pair of channels is disabled.
 *  0b1..The fault control in this pair of channels is enabled.
 */
#define FTM_COMBINE_FAULTEN2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
#define FTM_COMBINE_MCOMBINE2_MASK               (0x800000U)
#define FTM_COMBINE_MCOMBINE2_SHIFT              (23U)
#define FTM_COMBINE_MCOMBINE2(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE2_SHIFT)) & FTM_COMBINE_MCOMBINE2_MASK)
#define FTM_COMBINE_COMBINE3_MASK                (0x1000000U)
#define FTM_COMBINE_COMBINE3_SHIFT               (24U)
#define FTM_COMBINE_COMBINE3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
#define FTM_COMBINE_COMP3_MASK                   (0x2000000U)
#define FTM_COMBINE_COMP3_SHIFT                  (25U)
/*! COMP3 - Complement Of Channel (n) for n = 6
 *  0b0..The channel (n+1) output is the same as the channel (n) output.
 *  0b1..The channel (n+1) output is the complement of the channel (n) output.
 */
#define FTM_COMBINE_COMP3(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
#define FTM_COMBINE_DECAPEN3_MASK                (0x4000000U)
#define FTM_COMBINE_DECAPEN3_SHIFT               (26U)
#define FTM_COMBINE_DECAPEN3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
#define FTM_COMBINE_DECAP3_MASK                  (0x8000000U)
#define FTM_COMBINE_DECAP3_SHIFT                 (27U)
/*! DECAP3 - Dual Edge Capture Mode Captures For n = 6
 *  0b0..The dual edge captures are inactive.
 *  0b1..The dual edge captures are active.
 */
#define FTM_COMBINE_DECAP3(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
#define FTM_COMBINE_DTEN3_MASK                   (0x10000000U)
#define FTM_COMBINE_DTEN3_SHIFT                  (28U)
/*! DTEN3 - Deadtime Enable For n = 6
 *  0b0..The deadtime insertion in this pair of channels is disabled.
 *  0b1..The deadtime insertion in this pair of channels is enabled.
 */
#define FTM_COMBINE_DTEN3(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
#define FTM_COMBINE_SYNCEN3_MASK                 (0x20000000U)
#define FTM_COMBINE_SYNCEN3_SHIFT                (29U)
/*! SYNCEN3 - Synchronization Enable For n = 6
 *  0b0..The PWM synchronization in this pair of channels is disabled.
 *  0b1..The PWM synchronization in this pair of channels is enabled.
 */
#define FTM_COMBINE_SYNCEN3(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
#define FTM_COMBINE_FAULTEN3_MASK                (0x40000000U)
#define FTM_COMBINE_FAULTEN3_SHIFT               (30U)
/*! FAULTEN3 - Fault Control Enable For n = 6
 *  0b0..The fault control in this pair of channels is disabled.
 *  0b1..The fault control in this pair of channels is enabled.
 */
#define FTM_COMBINE_FAULTEN3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
#define FTM_COMBINE_MCOMBINE3_MASK               (0x80000000U)
#define FTM_COMBINE_MCOMBINE3_SHIFT              (31U)
#define FTM_COMBINE_MCOMBINE3(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE3_SHIFT)) & FTM_COMBINE_MCOMBINE3_MASK)
/*! @} */

/*! @name DEADTIME - Deadtime Configuration */
/*! @{ */
#define FTM_DEADTIME_DTVAL_MASK                  (0x3FU)
#define FTM_DEADTIME_DTVAL_SHIFT                 (0U)
#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
#define FTM_DEADTIME_DTPS_MASK                   (0xC0U)
#define FTM_DEADTIME_DTPS_SHIFT                  (6U)
/*! DTPS - Deadtime Prescaler Value
 *  0b0x..Divide the FTM input clock by 1.
 *  0b10..Divide the FTM input clock by 4.
 *  0b11..Divide the FTM input clock by 16.
 */
#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
#define FTM_DEADTIME_DTVALEX_MASK                (0xF0000U)
#define FTM_DEADTIME_DTVALEX_SHIFT               (16U)
#define FTM_DEADTIME_DTVALEX(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVALEX_SHIFT)) & FTM_DEADTIME_DTVALEX_MASK)
/*! @} */

/*! @name EXTTRIG - FTM External Trigger */
/*! @{ */
#define FTM_EXTTRIG_CH2TRIG_MASK                 (0x1U)
#define FTM_EXTTRIG_CH2TRIG_SHIFT                (0U)
/*! CH2TRIG - Channel 2 External Trigger Enable
 *  0b0..The generation of this external trigger is disabled.
 *  0b1..The generation of this external trigger is enabled.
 */
#define FTM_EXTTRIG_CH2TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
#define FTM_EXTTRIG_CH3TRIG_MASK                 (0x2U)
#define FTM_EXTTRIG_CH3TRIG_SHIFT                (1U)
/*! CH3TRIG - Channel 3 External Trigger Enable
 *  0b0..The generation of this external trigger is disabled.
 *  0b1..The generation of this external trigger is enabled.
 */
#define FTM_EXTTRIG_CH3TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
#define FTM_EXTTRIG_CH4TRIG_MASK                 (0x4U)
#define FTM_EXTTRIG_CH4TRIG_SHIFT                (2U)
/*! CH4TRIG - Channel 4 External Trigger Enable
 *  0b0..The generation of this external trigger is disabled.
 *  0b1..The generation of this external trigger is enabled.
 */
#define FTM_EXTTRIG_CH4TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
#define FTM_EXTTRIG_CH5TRIG_MASK                 (0x8U)
#define FTM_EXTTRIG_CH5TRIG_SHIFT                (3U)
/*! CH5TRIG - Channel 5 External Trigger Enable
 *  0b0..The generation of this external trigger is disabled.
 *  0b1..The generation of this external trigger is enabled.
 */
#define FTM_EXTTRIG_CH5TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
#define FTM_EXTTRIG_CH0TRIG_MASK                 (0x10U)
#define FTM_EXTTRIG_CH0TRIG_SHIFT                (4U)
/*! CH0TRIG - Channel 0 External Trigger Enable
 *  0b0..The generation of this external trigger is disabled.
 *  0b1..The generation of this external trigger is enabled.
 */
#define FTM_EXTTRIG_CH0TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
#define FTM_EXTTRIG_CH1TRIG_MASK                 (0x20U)
#define FTM_EXTTRIG_CH1TRIG_SHIFT                (5U)
/*! CH1TRIG - Channel 1 External Trigger Enable
 *  0b0..The generation of this external trigger is disabled.
 *  0b1..The generation of this external trigger is enabled.
 */
#define FTM_EXTTRIG_CH1TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
#define FTM_EXTTRIG_INITTRIGEN_MASK              (0x40U)
#define FTM_EXTTRIG_INITTRIGEN_SHIFT             (6U)
/*! INITTRIGEN - Initialization Trigger Enable
 *  0b0..The generation of initialization trigger is disabled.
 *  0b1..The generation of initialization trigger is enabled.
 */
#define FTM_EXTTRIG_INITTRIGEN(x)                (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
#define FTM_EXTTRIG_TRIGF_MASK                   (0x80U)
#define FTM_EXTTRIG_TRIGF_SHIFT                  (7U)
/*! TRIGF - Channel Trigger Flag
 *  0b0..No channel trigger was generated.
 *  0b1..A channel trigger was generated.
 */
#define FTM_EXTTRIG_TRIGF(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
#define FTM_EXTTRIG_CH6TRIG_MASK                 (0x100U)
#define FTM_EXTTRIG_CH6TRIG_SHIFT                (8U)
/*! CH6TRIG - Channel 6 External Trigger Enable
 *  0b0..The generation of this external trigger is disabled.
 *  0b1..The generation of this external trigger is enabled.
 */
#define FTM_EXTTRIG_CH6TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH6TRIG_SHIFT)) & FTM_EXTTRIG_CH6TRIG_MASK)
#define FTM_EXTTRIG_CH7TRIG_MASK                 (0x200U)
#define FTM_EXTTRIG_CH7TRIG_SHIFT                (9U)
/*! CH7TRIG - Channel 7 External Trigger Enable
 *  0b0..The generation of this external trigger is disabled.
 *  0b1..The generation of this external trigger is enabled.
 */
#define FTM_EXTTRIG_CH7TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH7TRIG_SHIFT)) & FTM_EXTTRIG_CH7TRIG_MASK)
/*! @} */

/*! @name POL - Channels Polarity */
/*! @{ */
#define FTM_POL_POL0_MASK                        (0x1U)
#define FTM_POL_POL0_SHIFT                       (0U)
/*! POL0 - Channel 0 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define FTM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
#define FTM_POL_POL1_MASK                        (0x2U)
#define FTM_POL_POL1_SHIFT                       (1U)
/*! POL1 - Channel 1 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define FTM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
#define FTM_POL_POL2_MASK                        (0x4U)
#define FTM_POL_POL2_SHIFT                       (2U)
/*! POL2 - Channel 2 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define FTM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
#define FTM_POL_POL3_MASK                        (0x8U)
#define FTM_POL_POL3_SHIFT                       (3U)
/*! POL3 - Channel 3 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define FTM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
#define FTM_POL_POL4_MASK                        (0x10U)
#define FTM_POL_POL4_SHIFT                       (4U)
/*! POL4 - Channel 4 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define FTM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
#define FTM_POL_POL5_MASK                        (0x20U)
#define FTM_POL_POL5_SHIFT                       (5U)
/*! POL5 - Channel 5 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define FTM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
#define FTM_POL_POL6_MASK                        (0x40U)
#define FTM_POL_POL6_SHIFT                       (6U)
/*! POL6 - Channel 6 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define FTM_POL_POL6(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
#define FTM_POL_POL7_MASK                        (0x80U)
#define FTM_POL_POL7_SHIFT                       (7U)
/*! POL7 - Channel 7 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define FTM_POL_POL7(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
/*! @} */

/*! @name FMS - Fault Mode Status */
/*! @{ */
#define FTM_FMS_FAULTF0_MASK                     (0x1U)
#define FTM_FMS_FAULTF0_SHIFT                    (0U)
/*! FAULTF0 - Fault Detection Flag 0
 *  0b0..No fault condition was detected at the fault input.
 *  0b1..A fault condition was detected at the fault input.
 */
#define FTM_FMS_FAULTF0(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
#define FTM_FMS_FAULTF1_MASK                     (0x2U)
#define FTM_FMS_FAULTF1_SHIFT                    (1U)
/*! FAULTF1 - Fault Detection Flag 1
 *  0b0..No fault condition was detected at the fault input.
 *  0b1..A fault condition was detected at the fault input.
 */
#define FTM_FMS_FAULTF1(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
#define FTM_FMS_FAULTF2_MASK                     (0x4U)
#define FTM_FMS_FAULTF2_SHIFT                    (2U)
/*! FAULTF2 - Fault Detection Flag 2
 *  0b0..No fault condition was detected at the fault input.
 *  0b1..A fault condition was detected at the fault input.
 */
#define FTM_FMS_FAULTF2(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
#define FTM_FMS_FAULTF3_MASK                     (0x8U)
#define FTM_FMS_FAULTF3_SHIFT                    (3U)
/*! FAULTF3 - Fault Detection Flag 3
 *  0b0..No fault condition was detected at the fault input.
 *  0b1..A fault condition was detected at the fault input.
 */
#define FTM_FMS_FAULTF3(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
#define FTM_FMS_FAULTIN_MASK                     (0x20U)
#define FTM_FMS_FAULTIN_SHIFT                    (5U)
/*! FAULTIN - Fault Inputs
 *  0b0..The logic OR of the enabled fault inputs is 0.
 *  0b1..The logic OR of the enabled fault inputs is 1.
 */
#define FTM_FMS_FAULTIN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
#define FTM_FMS_WPEN_MASK                        (0x40U)
#define FTM_FMS_WPEN_SHIFT                       (6U)
/*! WPEN - Write Protection Enable
 *  0b0..Write protection is disabled. Write protected bits can be written.
 *  0b1..Write protection is enabled. Write protected bits cannot be written.
 */
#define FTM_FMS_WPEN(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
#define FTM_FMS_FAULTF_MASK                      (0x80U)
#define FTM_FMS_FAULTF_SHIFT                     (7U)
/*! FAULTF - Fault Detection Flag
 *  0b0..No fault condition was detected.
 *  0b1..A fault condition was detected.
 */
#define FTM_FMS_FAULTF(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
/*! @} */

/*! @name FILTER - Input Capture Filter Control */
/*! @{ */
#define FTM_FILTER_CH0FVAL_MASK                  (0xFU)
#define FTM_FILTER_CH0FVAL_SHIFT                 (0U)
#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
#define FTM_FILTER_CH1FVAL_MASK                  (0xF0U)
#define FTM_FILTER_CH1FVAL_SHIFT                 (4U)
#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
#define FTM_FILTER_CH2FVAL_MASK                  (0xF00U)
#define FTM_FILTER_CH2FVAL_SHIFT                 (8U)
#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
#define FTM_FILTER_CH3FVAL_MASK                  (0xF000U)
#define FTM_FILTER_CH3FVAL_SHIFT                 (12U)
#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
/*! @} */

/*! @name FLTCTRL - Fault Control */
/*! @{ */
#define FTM_FLTCTRL_FAULT0EN_MASK                (0x1U)
#define FTM_FLTCTRL_FAULT0EN_SHIFT               (0U)
/*! FAULT0EN - Fault Input 0 Enable
 *  0b0..Fault input is disabled.
 *  0b1..Fault input is enabled.
 */
#define FTM_FLTCTRL_FAULT0EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
#define FTM_FLTCTRL_FAULT1EN_MASK                (0x2U)
#define FTM_FLTCTRL_FAULT1EN_SHIFT               (1U)
/*! FAULT1EN - Fault Input 1 Enable
 *  0b0..Fault input is disabled.
 *  0b1..Fault input is enabled.
 */
#define FTM_FLTCTRL_FAULT1EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
#define FTM_FLTCTRL_FAULT2EN_MASK                (0x4U)
#define FTM_FLTCTRL_FAULT2EN_SHIFT               (2U)
/*! FAULT2EN - Fault Input 2 Enable
 *  0b0..Fault input is disabled.
 *  0b1..Fault input is enabled.
 */
#define FTM_FLTCTRL_FAULT2EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
#define FTM_FLTCTRL_FAULT3EN_MASK                (0x8U)
#define FTM_FLTCTRL_FAULT3EN_SHIFT               (3U)
/*! FAULT3EN - Fault Input 3 Enable
 *  0b0..Fault input is disabled.
 *  0b1..Fault input is enabled.
 */
#define FTM_FLTCTRL_FAULT3EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
#define FTM_FLTCTRL_FFLTR0EN_MASK                (0x10U)
#define FTM_FLTCTRL_FFLTR0EN_SHIFT               (4U)
/*! FFLTR0EN - Fault Input 0 Filter Enable
 *  0b0..Fault input filter is disabled.
 *  0b1..Fault input filter is enabled.
 */
#define FTM_FLTCTRL_FFLTR0EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
#define FTM_FLTCTRL_FFLTR1EN_MASK                (0x20U)
#define FTM_FLTCTRL_FFLTR1EN_SHIFT               (5U)
/*! FFLTR1EN - Fault Input 1 Filter Enable
 *  0b0..Fault input filter is disabled.
 *  0b1..Fault input filter is enabled.
 */
#define FTM_FLTCTRL_FFLTR1EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
#define FTM_FLTCTRL_FFLTR2EN_MASK                (0x40U)
#define FTM_FLTCTRL_FFLTR2EN_SHIFT               (6U)
/*! FFLTR2EN - Fault Input 2 Filter Enable
 *  0b0..Fault input filter is disabled.
 *  0b1..Fault input filter is enabled.
 */
#define FTM_FLTCTRL_FFLTR2EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
#define FTM_FLTCTRL_FFLTR3EN_MASK                (0x80U)
#define FTM_FLTCTRL_FFLTR3EN_SHIFT               (7U)
/*! FFLTR3EN - Fault Input 3 Filter Enable
 *  0b0..Fault input filter is disabled.
 *  0b1..Fault input filter is enabled.
 */
#define FTM_FLTCTRL_FFLTR3EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
#define FTM_FLTCTRL_FFVAL_MASK                   (0xF00U)
#define FTM_FLTCTRL_FFVAL_SHIFT                  (8U)
#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
#define FTM_FLTCTRL_FSTATE_MASK                  (0x8000U)
#define FTM_FLTCTRL_FSTATE_SHIFT                 (15U)
/*! FSTATE - Fault output state
 *  0b0..FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits).
 *  0b1..FTM outputs will be tri-stated when fault event is ongoing
 */
#define FTM_FLTCTRL_FSTATE(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FSTATE_SHIFT)) & FTM_FLTCTRL_FSTATE_MASK)
/*! @} */

/*! @name QDCTRL - Quadrature Decoder Control And Status */
/*! @{ */
#define FTM_QDCTRL_QUADEN_MASK                   (0x1U)
#define FTM_QDCTRL_QUADEN_SHIFT                  (0U)
/*! QUADEN - Quadrature Decoder Mode Enable
 *  0b0..Quadrature Decoder mode is disabled.
 *  0b1..Quadrature Decoder mode is enabled.
 */
#define FTM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
#define FTM_QDCTRL_TOFDIR_MASK                   (0x2U)
#define FTM_QDCTRL_TOFDIR_SHIFT                  (1U)
/*! TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode
 *  0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
 *  0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
 */
#define FTM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
#define FTM_QDCTRL_QUADIR_MASK                   (0x4U)
#define FTM_QDCTRL_QUADIR_SHIFT                  (2U)
/*! QUADIR - FTM Counter Direction In Quadrature Decoder Mode
 *  0b0..Counting direction is decreasing (FTM counter decrement).
 *  0b1..Counting direction is increasing (FTM counter increment).
 */
#define FTM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
#define FTM_QDCTRL_QUADMODE_MASK                 (0x8U)
#define FTM_QDCTRL_QUADMODE_SHIFT                (3U)
/*! QUADMODE - Quadrature Decoder Mode
 *  0b0..Phase A and phase B encoding mode.
 *  0b1..Count and direction encoding mode.
 */
#define FTM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
#define FTM_QDCTRL_PHBPOL_MASK                   (0x10U)
#define FTM_QDCTRL_PHBPOL_SHIFT                  (4U)
/*! PHBPOL - Phase B Input Polarity
 *  0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
 *  0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
 */
#define FTM_QDCTRL_PHBPOL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
#define FTM_QDCTRL_PHAPOL_MASK                   (0x20U)
#define FTM_QDCTRL_PHAPOL_SHIFT                  (5U)
/*! PHAPOL - Phase A Input Polarity
 *  0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
 *  0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
 */
#define FTM_QDCTRL_PHAPOL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
#define FTM_QDCTRL_PHBFLTREN_MASK                (0x40U)
#define FTM_QDCTRL_PHBFLTREN_SHIFT               (6U)
/*! PHBFLTREN - Phase B Input Filter Enable
 *  0b0..Phase B input filter is disabled.
 *  0b1..Phase B input filter is enabled.
 */
#define FTM_QDCTRL_PHBFLTREN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
#define FTM_QDCTRL_PHAFLTREN_MASK                (0x80U)
#define FTM_QDCTRL_PHAFLTREN_SHIFT               (7U)
/*! PHAFLTREN - Phase A Input Filter Enable
 *  0b0..Phase A input filter is disabled.
 *  0b1..Phase A input filter is enabled.
 */
#define FTM_QDCTRL_PHAFLTREN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/*! @} */

/*! @name CONF - Configuration */
/*! @{ */
#define FTM_CONF_LDFQ_MASK                       (0x1FU)
#define FTM_CONF_LDFQ_SHIFT                      (0U)
#define FTM_CONF_LDFQ(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CONF_LDFQ_SHIFT)) & FTM_CONF_LDFQ_MASK)
#define FTM_CONF_BDMMODE_MASK                    (0xC0U)
#define FTM_CONF_BDMMODE_SHIFT                   (6U)
#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
#define FTM_CONF_GTBEEN_MASK                     (0x200U)
#define FTM_CONF_GTBEEN_SHIFT                    (9U)
#define FTM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
#define FTM_CONF_GTBEOUT_MASK                    (0x400U)
#define FTM_CONF_GTBEOUT_SHIFT                   (10U)
#define FTM_CONF_GTBEOUT(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
#define FTM_CONF_ITRIGR_MASK                     (0x800U)
#define FTM_CONF_ITRIGR_SHIFT                    (11U)
/*! ITRIGR - Initialization trigger on Reload Point
 *  0b0..Initialization trigger is generated on counter wrap events.
 *  0b1..Initialization trigger is generated when a reload point is reached.
 */
#define FTM_CONF_ITRIGR(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_CONF_ITRIGR_SHIFT)) & FTM_CONF_ITRIGR_MASK)
/*! @} */

/*! @name FLTPOL - FTM Fault Input Polarity */
/*! @{ */
#define FTM_FLTPOL_FLT0POL_MASK                  (0x1U)
#define FTM_FLTPOL_FLT0POL_SHIFT                 (0U)
/*! FLT0POL - Fault Input 0 Polarity
 *  0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
 *  0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
 */
#define FTM_FLTPOL_FLT0POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
#define FTM_FLTPOL_FLT1POL_MASK                  (0x2U)
#define FTM_FLTPOL_FLT1POL_SHIFT                 (1U)
/*! FLT1POL - Fault Input 1 Polarity
 *  0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
 *  0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
 */
#define FTM_FLTPOL_FLT1POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
#define FTM_FLTPOL_FLT2POL_MASK                  (0x4U)
#define FTM_FLTPOL_FLT2POL_SHIFT                 (2U)
/*! FLT2POL - Fault Input 2 Polarity
 *  0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
 *  0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
 */
#define FTM_FLTPOL_FLT2POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
#define FTM_FLTPOL_FLT3POL_MASK                  (0x8U)
#define FTM_FLTPOL_FLT3POL_SHIFT                 (3U)
/*! FLT3POL - Fault Input 3 Polarity
 *  0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
 *  0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
 */
#define FTM_FLTPOL_FLT3POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
/*! @} */

/*! @name SYNCONF - Synchronization Configuration */
/*! @{ */
#define FTM_SYNCONF_HWTRIGMODE_MASK              (0x1U)
#define FTM_SYNCONF_HWTRIGMODE_SHIFT             (0U)
/*! HWTRIGMODE - Hardware Trigger Mode
 *  0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
 *  0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
 */
#define FTM_SYNCONF_HWTRIGMODE(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
#define FTM_SYNCONF_CNTINC_MASK                  (0x4U)
#define FTM_SYNCONF_CNTINC_SHIFT                 (2U)
/*! CNTINC - CNTIN Register Synchronization
 *  0b0..CNTIN register is updated with its buffer value at all rising edges of FTM input clock.
 *  0b1..CNTIN register is updated with its buffer value by the PWM synchronization.
 */
#define FTM_SYNCONF_CNTINC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
#define FTM_SYNCONF_INVC_MASK                    (0x10U)
#define FTM_SYNCONF_INVC_SHIFT                   (4U)
/*! INVC - INVCTRL Register Synchronization
 *  0b0..INVCTRL register is updated with its buffer value at all rising edges of FTM input clock.
 *  0b1..INVCTRL register is updated with its buffer value by the PWM synchronization.
 */
#define FTM_SYNCONF_INVC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
#define FTM_SYNCONF_SWOC_MASK                    (0x20U)
#define FTM_SYNCONF_SWOC_SHIFT                   (5U)
/*! SWOC - SWOCTRL Register Synchronization
 *  0b0..SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock.
 *  0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization.
 */
#define FTM_SYNCONF_SWOC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
#define FTM_SYNCONF_SYNCMODE_MASK                (0x80U)
#define FTM_SYNCONF_SYNCMODE_SHIFT               (7U)
/*! SYNCMODE - Synchronization Mode
 *  0b0..Legacy PWM synchronization is selected.
 *  0b1..Enhanced PWM synchronization is selected.
 */
#define FTM_SYNCONF_SYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
#define FTM_SYNCONF_SWRSTCNT_MASK                (0x100U)
#define FTM_SYNCONF_SWRSTCNT_SHIFT               (8U)
/*! SWRSTCNT - FTM counter synchronization is activated by the software trigger
 *  0b0..The software trigger does not activate the FTM counter synchronization.
 *  0b1..The software trigger activates the FTM counter synchronization.
 */
#define FTM_SYNCONF_SWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
#define FTM_SYNCONF_SWWRBUF_MASK                 (0x200U)
#define FTM_SYNCONF_SWWRBUF_SHIFT                (9U)
/*! SWWRBUF - MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger
 *  0b0..The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.
 *  0b1..The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization.
 */
#define FTM_SYNCONF_SWWRBUF(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
#define FTM_SYNCONF_SWOM_MASK                    (0x400U)
#define FTM_SYNCONF_SWOM_SHIFT                   (10U)
/*! SWOM - Output mask synchronization is activated by the software trigger
 *  0b0..The software trigger does not activate the OUTMASK register synchronization.
 *  0b1..The software trigger activates the OUTMASK register synchronization.
 */
#define FTM_SYNCONF_SWOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
#define FTM_SYNCONF_SWINVC_MASK                  (0x800U)
#define FTM_SYNCONF_SWINVC_SHIFT                 (11U)
/*! SWINVC - Inverting control synchronization is activated by the software trigger
 *  0b0..The software trigger does not activate the INVCTRL register synchronization.
 *  0b1..The software trigger activates the INVCTRL register synchronization.
 */
#define FTM_SYNCONF_SWINVC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
#define FTM_SYNCONF_SWSOC_MASK                   (0x1000U)
#define FTM_SYNCONF_SWSOC_SHIFT                  (12U)
/*! SWSOC - Software output control synchronization is activated by the software trigger
 *  0b0..The software trigger does not activate the SWOCTRL register synchronization.
 *  0b1..The software trigger activates the SWOCTRL register synchronization.
 */
#define FTM_SYNCONF_SWSOC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
#define FTM_SYNCONF_HWRSTCNT_MASK                (0x10000U)
#define FTM_SYNCONF_HWRSTCNT_SHIFT               (16U)
/*! HWRSTCNT - FTM counter synchronization is activated by a hardware trigger
 *  0b0..A hardware trigger does not activate the FTM counter synchronization.
 *  0b1..A hardware trigger activates the FTM counter synchronization.
 */
#define FTM_SYNCONF_HWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
#define FTM_SYNCONF_HWWRBUF_MASK                 (0x20000U)
#define FTM_SYNCONF_HWWRBUF_SHIFT                (17U)
/*! HWWRBUF - MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger
 *  0b0..A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.
 *  0b1..A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization.
 */
#define FTM_SYNCONF_HWWRBUF(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
#define FTM_SYNCONF_HWOM_MASK                    (0x40000U)
#define FTM_SYNCONF_HWOM_SHIFT                   (18U)
/*! HWOM - Output mask synchronization is activated by a hardware trigger
 *  0b0..A hardware trigger does not activate the OUTMASK register synchronization.
 *  0b1..A hardware trigger activates the OUTMASK register synchronization.
 */
#define FTM_SYNCONF_HWOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
#define FTM_SYNCONF_HWINVC_MASK                  (0x80000U)
#define FTM_SYNCONF_HWINVC_SHIFT                 (19U)
/*! HWINVC - Inverting control synchronization is activated by a hardware trigger
 *  0b0..A hardware trigger does not activate the INVCTRL register synchronization.
 *  0b1..A hardware trigger activates the INVCTRL register synchronization.
 */
#define FTM_SYNCONF_HWINVC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
#define FTM_SYNCONF_HWSOC_MASK                   (0x100000U)
#define FTM_SYNCONF_HWSOC_SHIFT                  (20U)
/*! HWSOC - Software output control synchronization is activated by a hardware trigger
 *  0b0..A hardware trigger does not activate the SWOCTRL register synchronization.
 *  0b1..A hardware trigger activates the SWOCTRL register synchronization.
 */
#define FTM_SYNCONF_HWSOC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
/*! @} */

/*! @name INVCTRL - FTM Inverting Control */
/*! @{ */
#define FTM_INVCTRL_INV0EN_MASK                  (0x1U)
#define FTM_INVCTRL_INV0EN_SHIFT                 (0U)
/*! INV0EN - Pair Channels 0 Inverting Enable
 *  0b0..Inverting is disabled.
 *  0b1..Inverting is enabled.
 */
#define FTM_INVCTRL_INV0EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
#define FTM_INVCTRL_INV1EN_MASK                  (0x2U)
#define FTM_INVCTRL_INV1EN_SHIFT                 (1U)
/*! INV1EN - Pair Channels 1 Inverting Enable
 *  0b0..Inverting is disabled.
 *  0b1..Inverting is enabled.
 */
#define FTM_INVCTRL_INV1EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
#define FTM_INVCTRL_INV2EN_MASK                  (0x4U)
#define FTM_INVCTRL_INV2EN_SHIFT                 (2U)
/*! INV2EN - Pair Channels 2 Inverting Enable
 *  0b0..Inverting is disabled.
 *  0b1..Inverting is enabled.
 */
#define FTM_INVCTRL_INV2EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
#define FTM_INVCTRL_INV3EN_MASK                  (0x8U)
#define FTM_INVCTRL_INV3EN_SHIFT                 (3U)
/*! INV3EN - Pair Channels 3 Inverting Enable
 *  0b0..Inverting is disabled.
 *  0b1..Inverting is enabled.
 */
#define FTM_INVCTRL_INV3EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
/*! @} */

/*! @name SWOCTRL - FTM Software Output Control */
/*! @{ */
#define FTM_SWOCTRL_CH0OC_MASK                   (0x1U)
#define FTM_SWOCTRL_CH0OC_SHIFT                  (0U)
/*! CH0OC - Channel 0 Software Output Control Enable
 *  0b0..The channel output is not affected by software output control.
 *  0b1..The channel output is affected by software output control.
 */
#define FTM_SWOCTRL_CH0OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
#define FTM_SWOCTRL_CH1OC_MASK                   (0x2U)
#define FTM_SWOCTRL_CH1OC_SHIFT                  (1U)
/*! CH1OC - Channel 1 Software Output Control Enable
 *  0b0..The channel output is not affected by software output control.
 *  0b1..The channel output is affected by software output control.
 */
#define FTM_SWOCTRL_CH1OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
#define FTM_SWOCTRL_CH2OC_MASK                   (0x4U)
#define FTM_SWOCTRL_CH2OC_SHIFT                  (2U)
/*! CH2OC - Channel 2 Software Output Control Enable
 *  0b0..The channel output is not affected by software output control.
 *  0b1..The channel output is affected by software output control.
 */
#define FTM_SWOCTRL_CH2OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
#define FTM_SWOCTRL_CH3OC_MASK                   (0x8U)
#define FTM_SWOCTRL_CH3OC_SHIFT                  (3U)
/*! CH3OC - Channel 3 Software Output Control Enable
 *  0b0..The channel output is not affected by software output control.
 *  0b1..The channel output is affected by software output control.
 */
#define FTM_SWOCTRL_CH3OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
#define FTM_SWOCTRL_CH4OC_MASK                   (0x10U)
#define FTM_SWOCTRL_CH4OC_SHIFT                  (4U)
/*! CH4OC - Channel 4 Software Output Control Enable
 *  0b0..The channel output is not affected by software output control.
 *  0b1..The channel output is affected by software output control.
 */
#define FTM_SWOCTRL_CH4OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
#define FTM_SWOCTRL_CH5OC_MASK                   (0x20U)
#define FTM_SWOCTRL_CH5OC_SHIFT                  (5U)
/*! CH5OC - Channel 5 Software Output Control Enable
 *  0b0..The channel output is not affected by software output control.
 *  0b1..The channel output is affected by software output control.
 */
#define FTM_SWOCTRL_CH5OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
#define FTM_SWOCTRL_CH6OC_MASK                   (0x40U)
#define FTM_SWOCTRL_CH6OC_SHIFT                  (6U)
/*! CH6OC - Channel 6 Software Output Control Enable
 *  0b0..The channel output is not affected by software output control.
 *  0b1..The channel output is affected by software output control.
 */
#define FTM_SWOCTRL_CH6OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
#define FTM_SWOCTRL_CH7OC_MASK                   (0x80U)
#define FTM_SWOCTRL_CH7OC_SHIFT                  (7U)
/*! CH7OC - Channel 7 Software Output Control Enable
 *  0b0..The channel output is not affected by software output control.
 *  0b1..The channel output is affected by software output control.
 */
#define FTM_SWOCTRL_CH7OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
#define FTM_SWOCTRL_CH0OCV_MASK                  (0x100U)
#define FTM_SWOCTRL_CH0OCV_SHIFT                 (8U)
/*! CH0OCV - Channel 0 Software Output Control Value
 *  0b0..The software output control forces 0 to the channel output.
 *  0b1..The software output control forces 1 to the channel output.
 */
#define FTM_SWOCTRL_CH0OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
#define FTM_SWOCTRL_CH1OCV_MASK                  (0x200U)
#define FTM_SWOCTRL_CH1OCV_SHIFT                 (9U)
/*! CH1OCV - Channel 1 Software Output Control Value
 *  0b0..The software output control forces 0 to the channel output.
 *  0b1..The software output control forces 1 to the channel output.
 */
#define FTM_SWOCTRL_CH1OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
#define FTM_SWOCTRL_CH2OCV_MASK                  (0x400U)
#define FTM_SWOCTRL_CH2OCV_SHIFT                 (10U)
/*! CH2OCV - Channel 2 Software Output Control Value
 *  0b0..The software output control forces 0 to the channel output.
 *  0b1..The software output control forces 1 to the channel output.
 */
#define FTM_SWOCTRL_CH2OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
#define FTM_SWOCTRL_CH3OCV_MASK                  (0x800U)
#define FTM_SWOCTRL_CH3OCV_SHIFT                 (11U)
/*! CH3OCV - Channel 3 Software Output Control Value
 *  0b0..The software output control forces 0 to the channel output.
 *  0b1..The software output control forces 1 to the channel output.
 */
#define FTM_SWOCTRL_CH3OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
#define FTM_SWOCTRL_CH4OCV_MASK                  (0x1000U)
#define FTM_SWOCTRL_CH4OCV_SHIFT                 (12U)
/*! CH4OCV - Channel 4 Software Output Control Value
 *  0b0..The software output control forces 0 to the channel output.
 *  0b1..The software output control forces 1 to the channel output.
 */
#define FTM_SWOCTRL_CH4OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
#define FTM_SWOCTRL_CH5OCV_MASK                  (0x2000U)
#define FTM_SWOCTRL_CH5OCV_SHIFT                 (13U)
/*! CH5OCV - Channel 5 Software Output Control Value
 *  0b0..The software output control forces 0 to the channel output.
 *  0b1..The software output control forces 1 to the channel output.
 */
#define FTM_SWOCTRL_CH5OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
#define FTM_SWOCTRL_CH6OCV_MASK                  (0x4000U)
#define FTM_SWOCTRL_CH6OCV_SHIFT                 (14U)
/*! CH6OCV - Channel 6 Software Output Control Value
 *  0b0..The software output control forces 0 to the channel output.
 *  0b1..The software output control forces 1 to the channel output.
 */
#define FTM_SWOCTRL_CH6OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
#define FTM_SWOCTRL_CH7OCV_MASK                  (0x8000U)
#define FTM_SWOCTRL_CH7OCV_SHIFT                 (15U)
/*! CH7OCV - Channel 7 Software Output Control Value
 *  0b0..The software output control forces 0 to the channel output.
 *  0b1..The software output control forces 1 to the channel output.
 */
#define FTM_SWOCTRL_CH7OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
/*! @} */

/*! @name PWMLOAD - FTM PWM Load */
/*! @{ */
#define FTM_PWMLOAD_CH0SEL_MASK                  (0x1U)
#define FTM_PWMLOAD_CH0SEL_SHIFT                 (0U)
/*! CH0SEL - Channel 0 Select
 *  0b0..Channel match is not included as a reload opportunity.
 *  0b1..Channel match is included as a reload opportunity.
 */
#define FTM_PWMLOAD_CH0SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
#define FTM_PWMLOAD_CH1SEL_MASK                  (0x2U)
#define FTM_PWMLOAD_CH1SEL_SHIFT                 (1U)
/*! CH1SEL - Channel 1 Select
 *  0b0..Channel match is not included as a reload opportunity.
 *  0b1..Channel match is included as a reload opportunity.
 */
#define FTM_PWMLOAD_CH1SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
#define FTM_PWMLOAD_CH2SEL_MASK                  (0x4U)
#define FTM_PWMLOAD_CH2SEL_SHIFT                 (2U)
/*! CH2SEL - Channel 2 Select
 *  0b0..Channel match is not included as a reload opportunity.
 *  0b1..Channel match is included as a reload opportunity.
 */
#define FTM_PWMLOAD_CH2SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
#define FTM_PWMLOAD_CH3SEL_MASK                  (0x8U)
#define FTM_PWMLOAD_CH3SEL_SHIFT                 (3U)
/*! CH3SEL - Channel 3 Select
 *  0b0..Channel match is not included as a reload opportunity.
 *  0b1..Channel match is included as a reload opportunity.
 */
#define FTM_PWMLOAD_CH3SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
#define FTM_PWMLOAD_CH4SEL_MASK                  (0x10U)
#define FTM_PWMLOAD_CH4SEL_SHIFT                 (4U)
/*! CH4SEL - Channel 4 Select
 *  0b0..Channel match is not included as a reload opportunity.
 *  0b1..Channel match is included as a reload opportunity.
 */
#define FTM_PWMLOAD_CH4SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
#define FTM_PWMLOAD_CH5SEL_MASK                  (0x20U)
#define FTM_PWMLOAD_CH5SEL_SHIFT                 (5U)
/*! CH5SEL - Channel 5 Select
 *  0b0..Channel match is not included as a reload opportunity.
 *  0b1..Channel match is included as a reload opportunity.
 */
#define FTM_PWMLOAD_CH5SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
#define FTM_PWMLOAD_CH6SEL_MASK                  (0x40U)
#define FTM_PWMLOAD_CH6SEL_SHIFT                 (6U)
/*! CH6SEL - Channel 6 Select
 *  0b0..Channel match is not included as a reload opportunity.
 *  0b1..Channel match is included as a reload opportunity.
 */
#define FTM_PWMLOAD_CH6SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
#define FTM_PWMLOAD_CH7SEL_MASK                  (0x80U)
#define FTM_PWMLOAD_CH7SEL_SHIFT                 (7U)
/*! CH7SEL - Channel 7 Select
 *  0b0..Channel match is not included as a reload opportunity.
 *  0b1..Channel match is included as a reload opportunity.
 */
#define FTM_PWMLOAD_CH7SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
#define FTM_PWMLOAD_HCSEL_MASK                   (0x100U)
#define FTM_PWMLOAD_HCSEL_SHIFT                  (8U)
/*! HCSEL - Half Cycle Select
 *  0b0..Half cycle reload is disabled and it is not considered as a reload opportunity.
 *  0b1..Half cycle reload is enabled and it is considered as a reload opportunity.
 */
#define FTM_PWMLOAD_HCSEL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_HCSEL_SHIFT)) & FTM_PWMLOAD_HCSEL_MASK)
#define FTM_PWMLOAD_LDOK_MASK                    (0x200U)
#define FTM_PWMLOAD_LDOK_SHIFT                   (9U)
/*! LDOK - Load Enable
 *  0b0..Loading updated values is disabled.
 *  0b1..Loading updated values is enabled.
 */
#define FTM_PWMLOAD_LDOK(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
#define FTM_PWMLOAD_GLEN_MASK                    (0x400U)
#define FTM_PWMLOAD_GLEN_SHIFT                   (10U)
/*! GLEN - Global Load Enable
 *  0b0..Global Load Ok disabled.
 *  0b1..Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit.
 */
#define FTM_PWMLOAD_GLEN(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLEN_SHIFT)) & FTM_PWMLOAD_GLEN_MASK)
#define FTM_PWMLOAD_GLDOK_MASK                   (0x800U)
#define FTM_PWMLOAD_GLDOK_SHIFT                  (11U)
/*! GLDOK - Global Load OK
 *  0b0..No action.
 *  0b1..LDOK bit is set.
 */
#define FTM_PWMLOAD_GLDOK(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLDOK_SHIFT)) & FTM_PWMLOAD_GLDOK_MASK)
/*! @} */

/*! @name HCR - Half Cycle Register */
/*! @{ */
#define FTM_HCR_HCVAL_MASK                       (0xFFFFU)
#define FTM_HCR_HCVAL_SHIFT                      (0U)
#define FTM_HCR_HCVAL(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_HCR_HCVAL_SHIFT)) & FTM_HCR_HCVAL_MASK)
/*! @} */

/*! @name MOD_MIRROR - Mirror of Modulo Value */
/*! @{ */
#define FTM_MOD_MIRROR_FRACMOD_MASK              (0xF800U)
#define FTM_MOD_MIRROR_FRACMOD_SHIFT             (11U)
#define FTM_MOD_MIRROR_FRACMOD(x)                (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_FRACMOD_SHIFT)) & FTM_MOD_MIRROR_FRACMOD_MASK)
#define FTM_MOD_MIRROR_MOD_MASK                  (0xFFFF0000U)
#define FTM_MOD_MIRROR_MOD_SHIFT                 (16U)
#define FTM_MOD_MIRROR_MOD(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_MOD_SHIFT)) & FTM_MOD_MIRROR_MOD_MASK)
/*! @} */

/*! @name CV_MIRROR - Mirror of Channel (n) Match Value */
/*! @{ */
#define FTM_CV_MIRROR_FRACVAL_MASK               (0xF800U)
#define FTM_CV_MIRROR_FRACVAL_SHIFT              (11U)
#define FTM_CV_MIRROR_FRACVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_FRACVAL_SHIFT)) & FTM_CV_MIRROR_FRACVAL_MASK)
#define FTM_CV_MIRROR_VAL_MASK                   (0xFFFF0000U)
#define FTM_CV_MIRROR_VAL_SHIFT                  (16U)
#define FTM_CV_MIRROR_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_VAL_SHIFT)) & FTM_CV_MIRROR_VAL_MASK)
/*! @} */

/* The count of FTM_CV_MIRROR */
#define FTM_CV_MIRROR_COUNT                      (8U)


/*!
 * @}
 */ /* end of group FTM_Register_Masks */


/* FTM - Peripheral instance base addresses */
/** Peripheral DMA__FTM0 base address */
#define DMA__FTM0_BASE                           (0x5A8A0000u)
/** Peripheral DMA__FTM0 base pointer */
#define DMA__FTM0                                ((FTM_Type *)DMA__FTM0_BASE)
/** Peripheral DMA__FTM1 base address */
#define DMA__FTM1_BASE                           (0x5A8B0000u)
/** Peripheral DMA__FTM1 base pointer */
#define DMA__FTM1                                ((FTM_Type *)DMA__FTM1_BASE)
/** Array initializer of FTM peripheral base addresses */
#define FTM_BASE_ADDRS                           { DMA__FTM0_BASE, DMA__FTM1_BASE }
/** Array initializer of FTM peripheral base pointers */
#define FTM_BASE_PTRS                            { DMA__FTM0, DMA__FTM1 }
/** Interrupt vectors for the FTM peripheral type */
#define FTM_IRQS                                 { DMA_FTM0_INT_IRQn, DMA_FTM1_INT_IRQn }

/*!
 * @}
 */ /* end of group FTM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GPIO Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
 * @{
 */

/** GPIO - Register Layout Typedef */
typedef struct {
  __IO uint32_t DR;                                /**< GPIO data register, offset: 0x0 */
  __IO uint32_t GDIR;                              /**< GPIO direction register, offset: 0x4 */
  __I  uint32_t PSR;                               /**< GPIO pad status register, offset: 0x8 */
  __IO uint32_t ICR1;                              /**< GPIO interrupt configuration register1, offset: 0xC */
  __IO uint32_t ICR2;                              /**< GPIO interrupt configuration register2, offset: 0x10 */
  __IO uint32_t IMR;                               /**< GPIO interrupt mask register, offset: 0x14 */
  __IO uint32_t ISR;                               /**< GPIO interrupt status register, offset: 0x18 */
  __IO uint32_t EDGE_SEL;                          /**< GPIO edge select register, offset: 0x1C */
       uint8_t RESERVED_0[100];
  __O  uint32_t DR_SET;                            /**< GPIO data register SET, offset: 0x84 */
  __O  uint32_t DR_CLEAR;                          /**< GPIO data register CLEAR, offset: 0x88 */
  __O  uint32_t DR_TOGGLE;                         /**< GPIO data register TOGGLE, offset: 0x8C */
} GPIO_Type;

/* ----------------------------------------------------------------------------
   -- GPIO Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GPIO_Register_Masks GPIO Register Masks
 * @{
 */

/*! @name DR - GPIO data register */
/*! @{ */
#define GPIO_DR_DR_MASK                          (0xFFFFFFFFU)
#define GPIO_DR_DR_SHIFT                         (0U)
#define GPIO_DR_DR(x)                            (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
/*! @} */

/*! @name GDIR - GPIO direction register */
/*! @{ */
#define GPIO_GDIR_GDIR_MASK                      (0xFFFFFFFFU)
#define GPIO_GDIR_GDIR_SHIFT                     (0U)
#define GPIO_GDIR_GDIR(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
/*! @} */

/*! @name PSR - GPIO pad status register */
/*! @{ */
#define GPIO_PSR_PSR_MASK                        (0xFFFFFFFFU)
#define GPIO_PSR_PSR_SHIFT                       (0U)
#define GPIO_PSR_PSR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
/*! @} */

/*! @name ICR1 - GPIO interrupt configuration register1 */
/*! @{ */
#define GPIO_ICR1_ICR0_MASK                      (0x3U)
#define GPIO_ICR1_ICR0_SHIFT                     (0U)
/*! ICR0 - ICR0
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
#define GPIO_ICR1_ICR1_MASK                      (0xCU)
#define GPIO_ICR1_ICR1_SHIFT                     (2U)
/*! ICR1 - ICR1
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
#define GPIO_ICR1_ICR2_MASK                      (0x30U)
#define GPIO_ICR1_ICR2_SHIFT                     (4U)
/*! ICR2 - ICR2
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
#define GPIO_ICR1_ICR3_MASK                      (0xC0U)
#define GPIO_ICR1_ICR3_SHIFT                     (6U)
/*! ICR3 - ICR3
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
#define GPIO_ICR1_ICR4_MASK                      (0x300U)
#define GPIO_ICR1_ICR4_SHIFT                     (8U)
/*! ICR4 - ICR4
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
#define GPIO_ICR1_ICR5_MASK                      (0xC00U)
#define GPIO_ICR1_ICR5_SHIFT                     (10U)
/*! ICR5 - ICR5
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
#define GPIO_ICR1_ICR6_MASK                      (0x3000U)
#define GPIO_ICR1_ICR6_SHIFT                     (12U)
/*! ICR6 - ICR6
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
#define GPIO_ICR1_ICR7_MASK                      (0xC000U)
#define GPIO_ICR1_ICR7_SHIFT                     (14U)
/*! ICR7 - ICR7
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
#define GPIO_ICR1_ICR8_MASK                      (0x30000U)
#define GPIO_ICR1_ICR8_SHIFT                     (16U)
/*! ICR8 - ICR8
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
#define GPIO_ICR1_ICR9_MASK                      (0xC0000U)
#define GPIO_ICR1_ICR9_SHIFT                     (18U)
/*! ICR9 - ICR9
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
#define GPIO_ICR1_ICR10_MASK                     (0x300000U)
#define GPIO_ICR1_ICR10_SHIFT                    (20U)
/*! ICR10 - ICR10
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
#define GPIO_ICR1_ICR11_MASK                     (0xC00000U)
#define GPIO_ICR1_ICR11_SHIFT                    (22U)
/*! ICR11 - ICR11
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
#define GPIO_ICR1_ICR12_MASK                     (0x3000000U)
#define GPIO_ICR1_ICR12_SHIFT                    (24U)
/*! ICR12 - ICR12
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
#define GPIO_ICR1_ICR13_MASK                     (0xC000000U)
#define GPIO_ICR1_ICR13_SHIFT                    (26U)
/*! ICR13 - ICR13
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
#define GPIO_ICR1_ICR14_MASK                     (0x30000000U)
#define GPIO_ICR1_ICR14_SHIFT                    (28U)
/*! ICR14 - ICR14
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
#define GPIO_ICR1_ICR15_MASK                     (0xC0000000U)
#define GPIO_ICR1_ICR15_SHIFT                    (30U)
/*! ICR15 - ICR15
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR1_ICR15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
/*! @} */

/*! @name ICR2 - GPIO interrupt configuration register2 */
/*! @{ */
#define GPIO_ICR2_ICR16_MASK                     (0x3U)
#define GPIO_ICR2_ICR16_SHIFT                    (0U)
/*! ICR16 - ICR16
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
#define GPIO_ICR2_ICR17_MASK                     (0xCU)
#define GPIO_ICR2_ICR17_SHIFT                    (2U)
/*! ICR17 - ICR17
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
#define GPIO_ICR2_ICR18_MASK                     (0x30U)
#define GPIO_ICR2_ICR18_SHIFT                    (4U)
/*! ICR18 - ICR18
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
#define GPIO_ICR2_ICR19_MASK                     (0xC0U)
#define GPIO_ICR2_ICR19_SHIFT                    (6U)
/*! ICR19 - ICR19
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
#define GPIO_ICR2_ICR20_MASK                     (0x300U)
#define GPIO_ICR2_ICR20_SHIFT                    (8U)
/*! ICR20 - ICR20
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
#define GPIO_ICR2_ICR21_MASK                     (0xC00U)
#define GPIO_ICR2_ICR21_SHIFT                    (10U)
/*! ICR21 - ICR21
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
#define GPIO_ICR2_ICR22_MASK                     (0x3000U)
#define GPIO_ICR2_ICR22_SHIFT                    (12U)
/*! ICR22 - ICR22
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
#define GPIO_ICR2_ICR23_MASK                     (0xC000U)
#define GPIO_ICR2_ICR23_SHIFT                    (14U)
/*! ICR23 - ICR23
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
#define GPIO_ICR2_ICR24_MASK                     (0x30000U)
#define GPIO_ICR2_ICR24_SHIFT                    (16U)
/*! ICR24 - ICR24
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
#define GPIO_ICR2_ICR25_MASK                     (0xC0000U)
#define GPIO_ICR2_ICR25_SHIFT                    (18U)
/*! ICR25 - ICR25
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
#define GPIO_ICR2_ICR26_MASK                     (0x300000U)
#define GPIO_ICR2_ICR26_SHIFT                    (20U)
/*! ICR26 - ICR26
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
#define GPIO_ICR2_ICR27_MASK                     (0xC00000U)
#define GPIO_ICR2_ICR27_SHIFT                    (22U)
/*! ICR27 - ICR27
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
#define GPIO_ICR2_ICR28_MASK                     (0x3000000U)
#define GPIO_ICR2_ICR28_SHIFT                    (24U)
/*! ICR28 - ICR28
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
#define GPIO_ICR2_ICR29_MASK                     (0xC000000U)
#define GPIO_ICR2_ICR29_SHIFT                    (26U)
/*! ICR29 - ICR29
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
#define GPIO_ICR2_ICR30_MASK                     (0x30000000U)
#define GPIO_ICR2_ICR30_SHIFT                    (28U)
/*! ICR30 - ICR30
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
#define GPIO_ICR2_ICR31_MASK                     (0xC0000000U)
#define GPIO_ICR2_ICR31_SHIFT                    (30U)
/*! ICR31 - ICR31
 *  0b00..Interrupt n is low-level sensitive.
 *  0b01..Interrupt n is high-level sensitive.
 *  0b10..Interrupt n is rising-edge sensitive.
 *  0b11..Interrupt n is falling-edge sensitive.
 */
#define GPIO_ICR2_ICR31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
/*! @} */

/*! @name IMR - GPIO interrupt mask register */
/*! @{ */
#define GPIO_IMR_IMR_MASK                        (0xFFFFFFFFU)
#define GPIO_IMR_IMR_SHIFT                       (0U)
#define GPIO_IMR_IMR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
/*! @} */

/*! @name ISR - GPIO interrupt status register */
/*! @{ */
#define GPIO_ISR_ISR_MASK                        (0xFFFFFFFFU)
#define GPIO_ISR_ISR_SHIFT                       (0U)
#define GPIO_ISR_ISR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
/*! @} */

/*! @name EDGE_SEL - GPIO edge select register */
/*! @{ */
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK         (0xFFFFFFFFU)
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT        (0U)
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
/*! @} */

/*! @name DR_SET - GPIO data register SET */
/*! @{ */
#define GPIO_DR_SET_DR_SET_MASK                  (0xFFFFFFFFU)
#define GPIO_DR_SET_DR_SET_SHIFT                 (0U)
#define GPIO_DR_SET_DR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
/*! @} */

/*! @name DR_CLEAR - GPIO data register CLEAR */
/*! @{ */
#define GPIO_DR_CLEAR_DR_CLEAR_MASK              (0xFFFFFFFFU)
#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT             (0U)
#define GPIO_DR_CLEAR_DR_CLEAR(x)                (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
/*! @} */

/*! @name DR_TOGGLE - GPIO data register TOGGLE */
/*! @{ */
#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK            (0xFFFFFFFFU)
#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT           (0U)
#define GPIO_DR_TOGGLE_DR_TOGGLE(x)              (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group GPIO_Register_Masks */


/* GPIO - Peripheral instance base addresses */
/** Peripheral DI_HDMI__GPIO base address */
#define DI_HDMI__GPIO_BASE                       (0x56262000u)
/** Peripheral DI_HDMI__GPIO base pointer */
#define DI_HDMI__GPIO                            ((GPIO_Type *)DI_HDMI__GPIO_BASE)
/** Peripheral DI_LVDS_0__GPIO base address */
#define DI_LVDS_0__GPIO_BASE                     (0x56242000u)
/** Peripheral DI_LVDS_0__GPIO base pointer */
#define DI_LVDS_0__GPIO                          ((GPIO_Type *)DI_LVDS_0__GPIO_BASE)
/** Peripheral DI_LVDS_1__GPIO base address */
#define DI_LVDS_1__GPIO_BASE                     (0x57242000u)
/** Peripheral DI_LVDS_1__GPIO base pointer */
#define DI_LVDS_1__GPIO                          ((GPIO_Type *)DI_LVDS_1__GPIO_BASE)
/** Peripheral DI_MIPI_0__GPIO base address */
#define DI_MIPI_0__GPIO_BASE                     (0x56222000u)
/** Peripheral DI_MIPI_0__GPIO base pointer */
#define DI_MIPI_0__GPIO                          ((GPIO_Type *)DI_MIPI_0__GPIO_BASE)
/** Peripheral DI_MIPI_1__GPIO base address */
#define DI_MIPI_1__GPIO_BASE                     (0x57222000u)
/** Peripheral DI_MIPI_1__GPIO base pointer */
#define DI_MIPI_1__GPIO                          ((GPIO_Type *)DI_MIPI_1__GPIO_BASE)
/** Peripheral HSIO__GPIO base address */
#define HSIO__GPIO_BASE                          (0x5F170000u)
/** Peripheral HSIO__GPIO base pointer */
#define HSIO__GPIO                               ((GPIO_Type *)HSIO__GPIO_BASE)
/** Peripheral LSIO__GPIO0 base address */
#define LSIO__GPIO0_BASE                         (0x5D080000u)
/** Peripheral LSIO__GPIO0 base pointer */
#define LSIO__GPIO0                              ((GPIO_Type *)LSIO__GPIO0_BASE)
/** Peripheral LSIO__GPIO1 base address */
#define LSIO__GPIO1_BASE                         (0x5D090000u)
/** Peripheral LSIO__GPIO1 base pointer */
#define LSIO__GPIO1                              ((GPIO_Type *)LSIO__GPIO1_BASE)
/** Peripheral LSIO__GPIO2 base address */
#define LSIO__GPIO2_BASE                         (0x5D0A0000u)
/** Peripheral LSIO__GPIO2 base pointer */
#define LSIO__GPIO2                              ((GPIO_Type *)LSIO__GPIO2_BASE)
/** Peripheral LSIO__GPIO3 base address */
#define LSIO__GPIO3_BASE                         (0x5D0B0000u)
/** Peripheral LSIO__GPIO3 base pointer */
#define LSIO__GPIO3                              ((GPIO_Type *)LSIO__GPIO3_BASE)
/** Peripheral LSIO__GPIO4 base address */
#define LSIO__GPIO4_BASE                         (0x5D0C0000u)
/** Peripheral LSIO__GPIO4 base pointer */
#define LSIO__GPIO4                              ((GPIO_Type *)LSIO__GPIO4_BASE)
/** Peripheral LSIO__GPIO5 base address */
#define LSIO__GPIO5_BASE                         (0x5D0D0000u)
/** Peripheral LSIO__GPIO5 base pointer */
#define LSIO__GPIO5                              ((GPIO_Type *)LSIO__GPIO5_BASE)
/** Peripheral LSIO__GPIO6 base address */
#define LSIO__GPIO6_BASE                         (0x5D0E0000u)
/** Peripheral LSIO__GPIO6 base pointer */
#define LSIO__GPIO6                              ((GPIO_Type *)LSIO__GPIO6_BASE)
/** Peripheral LSIO__GPIO7 base address */
#define LSIO__GPIO7_BASE                         (0x5D0F0000u)
/** Peripheral LSIO__GPIO7 base pointer */
#define LSIO__GPIO7                              ((GPIO_Type *)LSIO__GPIO7_BASE)
/** Peripheral MIPI_CSI_0__GPIO base address */
#define MIPI_CSI_0__GPIO_BASE                    (0x58222000u)
/** Peripheral MIPI_CSI_0__GPIO base pointer */
#define MIPI_CSI_0__GPIO                         ((GPIO_Type *)MIPI_CSI_0__GPIO_BASE)
/** Peripheral MIPI_CSI_1__GPIO base address */
#define MIPI_CSI_1__GPIO_BASE                    (0x58242000u)
/** Peripheral MIPI_CSI_1__GPIO base pointer */
#define MIPI_CSI_1__GPIO                         ((GPIO_Type *)MIPI_CSI_1__GPIO_BASE)
/** Peripheral RX_HDMI__GPIO base address */
#define RX_HDMI__GPIO_BASE                       (0x58262000u)
/** Peripheral RX_HDMI__GPIO base pointer */
#define RX_HDMI__GPIO                            ((GPIO_Type *)RX_HDMI__GPIO_BASE)
/** Array initializer of GPIO peripheral base addresses */
#define GPIO_BASE_ADDRS                          { DI_HDMI__GPIO_BASE, DI_LVDS_0__GPIO_BASE, DI_LVDS_1__GPIO_BASE, DI_MIPI_0__GPIO_BASE, DI_MIPI_1__GPIO_BASE, HSIO__GPIO_BASE, LSIO__GPIO0_BASE, LSIO__GPIO1_BASE, LSIO__GPIO2_BASE, LSIO__GPIO3_BASE, LSIO__GPIO4_BASE, LSIO__GPIO5_BASE, LSIO__GPIO6_BASE, LSIO__GPIO7_BASE, MIPI_CSI_0__GPIO_BASE, MIPI_CSI_1__GPIO_BASE, RX_HDMI__GPIO_BASE }
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASE_PTRS                           { DI_HDMI__GPIO, DI_LVDS_0__GPIO, DI_LVDS_1__GPIO, DI_MIPI_0__GPIO, DI_MIPI_1__GPIO, HSIO__GPIO, LSIO__GPIO0, LSIO__GPIO1, LSIO__GPIO2, LSIO__GPIO3, LSIO__GPIO4, LSIO__GPIO5, LSIO__GPIO6, LSIO__GPIO7, MIPI_CSI_0__GPIO, MIPI_CSI_1__GPIO, RX_HDMI__GPIO }
/** Interrupt vectors for the GPIO peripheral type */
#define GPIO_IRQS                                { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, LSIO_GPIO_INT0_IRQn, LSIO_GPIO_INT1_IRQn, LSIO_GPIO_INT2_IRQn, LSIO_GPIO_INT3_IRQn, LSIO_GPIO_INT4_IRQn, LSIO_GPIO_INT5_IRQn, LSIO_GPIO_INT6_IRQn, LSIO_GPIO_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }

/*!
 * @}
 */ /* end of group GPIO_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GPMI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer
 * @{
 */

/** GPMI - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0 */
    __IO uint32_t RW;                                /**< GPMI Control Register 0 Description, offset: 0x0 */
    __IO uint32_t SET;                               /**< GPMI Control Register 0 Description, offset: 0x4 */
    __IO uint32_t CLR;                               /**< GPMI Control Register 0 Description, offset: 0x8 */
    __IO uint32_t TOG;                               /**< GPMI Control Register 0 Description, offset: 0xC */
  } CTRL0;
  __IO uint32_t COMPARE;                           /**< GPMI Compare Register Description, offset: 0x10 */
       uint8_t RESERVED_0[12];
  struct {                                         /* offset: 0x20 */
    __IO uint32_t RW;                                /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */
    __IO uint32_t SET;                               /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */
    __IO uint32_t CLR;                               /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */
    __IO uint32_t TOG;                               /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */
  } ECCCTRL;
  __IO uint32_t ECCCOUNT;                          /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */
       uint8_t RESERVED_1[12];
  __IO uint32_t PAYLOAD;                           /**< GPMI Payload Address Register Description, offset: 0x40 */
       uint8_t RESERVED_2[12];
  __IO uint32_t AUXILIARY;                         /**< GPMI Auxiliary Address Register Description, offset: 0x50 */
       uint8_t RESERVED_3[12];
  struct {                                         /* offset: 0x60 */
    __IO uint32_t RW;                                /**< GPMI Control Register 1 Description, offset: 0x60 */
    __IO uint32_t SET;                               /**< GPMI Control Register 1 Description, offset: 0x64 */
    __IO uint32_t CLR;                               /**< GPMI Control Register 1 Description, offset: 0x68 */
    __IO uint32_t TOG;                               /**< GPMI Control Register 1 Description, offset: 0x6C */
  } CTRL1;
  __IO uint32_t TIMING0;                           /**< GPMI Timing Register 0 Description, offset: 0x70 */
       uint8_t RESERVED_4[12];
  __IO uint32_t TIMING1;                           /**< GPMI Timing Register 1 Description, offset: 0x80 */
       uint8_t RESERVED_5[12];
  __IO uint32_t TIMING2;                           /**< GPMI Timing Register 2 Description, offset: 0x90 */
       uint8_t RESERVED_6[12];
  __IO uint32_t DATA;                              /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */
       uint8_t RESERVED_7[12];
  __I  uint32_t STAT;                              /**< GPMI Status Register Description, offset: 0xB0 */
       uint8_t RESERVED_8[12];
  __I  uint32_t DEBUGr;                            /**< GPMI Debug Information Register Description, offset: 0xC0 */
       uint8_t RESERVED_9[12];
  __I  uint32_t VERSION;                           /**< GPMI Version Register Description, offset: 0xD0 */
       uint8_t RESERVED_10[12];
  __IO uint32_t DEBUG2;                            /**< GPMI Debug2 Information Register Description, offset: 0xE0 */
       uint8_t RESERVED_11[12];
  __I  uint32_t DEBUG3;                            /**< GPMI Debug3 Information Register Description, offset: 0xF0 */
       uint8_t RESERVED_12[12];
  __IO uint32_t READ_DDR_DLL_CTRL;                 /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */
       uint8_t RESERVED_13[12];
  __IO uint32_t WRITE_DDR_DLL_CTRL;                /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */
       uint8_t RESERVED_14[12];
  __I  uint32_t READ_DDR_DLL_STS;                  /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */
       uint8_t RESERVED_15[12];
  __I  uint32_t WRITE_DDR_DLL_STS;                 /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */
} GPMI_Type;

/* ----------------------------------------------------------------------------
   -- GPMI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GPMI_Register_Masks GPMI Register Masks
 * @{
 */

/*! @name CTRL0 - GPMI Control Register 0 Description */
/*! @{ */
#define GPMI_CTRL0_XFER_COUNT_MASK               (0xFFFFU)
#define GPMI_CTRL0_XFER_COUNT_SHIFT              (0U)
#define GPMI_CTRL0_XFER_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK)
#define GPMI_CTRL0_ADDRESS_INCREMENT_MASK        (0x10000U)
#define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT       (16U)
#define GPMI_CTRL0_ADDRESS_INCREMENT(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK)
#define GPMI_CTRL0_ADDRESS_MASK                  (0xE0000U)
#define GPMI_CTRL0_ADDRESS_SHIFT                 (17U)
#define GPMI_CTRL0_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK)
#define GPMI_CTRL0_CS_MASK                       (0x700000U)
#define GPMI_CTRL0_CS_SHIFT                      (20U)
#define GPMI_CTRL0_CS(x)                         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK)
#define GPMI_CTRL0_WORD_LENGTH_MASK              (0x800000U)
#define GPMI_CTRL0_WORD_LENGTH_SHIFT             (23U)
/*! WORD_LENGTH - WORD_LENGTH
 *  0b0..Reserved.
 *  0b1..8-bit Data Bus mode.
 */
#define GPMI_CTRL0_WORD_LENGTH(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK)
#define GPMI_CTRL0_COMMAND_MODE_MASK             (0x3000000U)
#define GPMI_CTRL0_COMMAND_MODE_SHIFT            (24U)
/*! COMMAND_MODE - COMMAND_MODE
 *  0b00..Write mode.
 *  0b01..Read Mode.
 *  0b10..Read and Compare Mode (setting sense flop).
 *  0b11..Wait for Ready.
 */
#define GPMI_CTRL0_COMMAND_MODE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK)
#define GPMI_CTRL0_UDMA_MASK                     (0x4000000U)
#define GPMI_CTRL0_UDMA_SHIFT                    (26U)
/*! UDMA - UDMA
 *  0b0..Use ATA-PIO mode on the external bus.
 *  0b1..Use ATA-Ultra DMA mode on the external bus.
 */
#define GPMI_CTRL0_UDMA(x)                       (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK)
#define GPMI_CTRL0_LOCK_CS_MASK                  (0x8000000U)
#define GPMI_CTRL0_LOCK_CS_SHIFT                 (27U)
#define GPMI_CTRL0_LOCK_CS(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK)
#define GPMI_CTRL0_WR_DATA_EN_MASK               (0x10000000U)
#define GPMI_CTRL0_WR_DATA_EN_SHIFT              (28U)
#define GPMI_CTRL0_WR_DATA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WR_DATA_EN_SHIFT)) & GPMI_CTRL0_WR_DATA_EN_MASK)
#define GPMI_CTRL0_RUN_MASK                      (0x20000000U)
#define GPMI_CTRL0_RUN_SHIFT                     (29U)
#define GPMI_CTRL0_RUN(x)                        (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK)
#define GPMI_CTRL0_CLKGATE_MASK                  (0x40000000U)
#define GPMI_CTRL0_CLKGATE_SHIFT                 (30U)
#define GPMI_CTRL0_CLKGATE(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK)
#define GPMI_CTRL0_SFTRST_MASK                   (0x80000000U)
#define GPMI_CTRL0_SFTRST_SHIFT                  (31U)
#define GPMI_CTRL0_SFTRST(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK)
/*! @} */

/*! @name COMPARE - GPMI Compare Register Description */
/*! @{ */
#define GPMI_COMPARE_REFERENCE_MASK              (0xFFFFU)
#define GPMI_COMPARE_REFERENCE_SHIFT             (0U)
#define GPMI_COMPARE_REFERENCE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK)
#define GPMI_COMPARE_MASK_MASK                   (0xFFFF0000U)
#define GPMI_COMPARE_MASK_SHIFT                  (16U)
#define GPMI_COMPARE_MASK(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK)
/*! @} */

/*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */
/*! @{ */
#define GPMI_ECCCTRL_BUFFER_MASK_MASK            (0x1FFU)
#define GPMI_ECCCTRL_BUFFER_MASK_SHIFT           (0U)
#define GPMI_ECCCTRL_BUFFER_MASK(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK)
#define GPMI_ECCCTRL_RSVD1_MASK                  (0xE00U)
#define GPMI_ECCCTRL_RSVD1_SHIFT                 (9U)
#define GPMI_ECCCTRL_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD1_SHIFT)) & GPMI_ECCCTRL_RSVD1_MASK)
#define GPMI_ECCCTRL_ENABLE_ECC_MASK             (0x1000U)
#define GPMI_ECCCTRL_ENABLE_ECC_SHIFT            (12U)
#define GPMI_ECCCTRL_ENABLE_ECC(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK)
#define GPMI_ECCCTRL_ECC_CMD_MASK                (0x6000U)
#define GPMI_ECCCTRL_ECC_CMD_SHIFT               (13U)
#define GPMI_ECCCTRL_ECC_CMD(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK)
#define GPMI_ECCCTRL_RSVD2_MASK                  (0x8000U)
#define GPMI_ECCCTRL_RSVD2_SHIFT                 (15U)
#define GPMI_ECCCTRL_RSVD2(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK)
#define GPMI_ECCCTRL_HANDLE_MASK                 (0xFFFF0000U)
#define GPMI_ECCCTRL_HANDLE_SHIFT                (16U)
#define GPMI_ECCCTRL_HANDLE(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK)
/*! @} */

/*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */
/*! @{ */
#define GPMI_ECCCOUNT_COUNT_MASK                 (0xFFFFU)
#define GPMI_ECCCOUNT_COUNT_SHIFT                (0U)
#define GPMI_ECCCOUNT_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK)
#define GPMI_ECCCOUNT_RSVD2_MASK                 (0xFFFF0000U)
#define GPMI_ECCCOUNT_RSVD2_SHIFT                (16U)
#define GPMI_ECCCOUNT_RSVD2(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RSVD2_SHIFT)) & GPMI_ECCCOUNT_RSVD2_MASK)
/*! @} */

/*! @name PAYLOAD - GPMI Payload Address Register Description */
/*! @{ */
#define GPMI_PAYLOAD_RSVD0_MASK                  (0x3U)
#define GPMI_PAYLOAD_RSVD0_SHIFT                 (0U)
#define GPMI_PAYLOAD_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK)
#define GPMI_PAYLOAD_ADDRESS_MASK                (0xFFFFFFFCU)
#define GPMI_PAYLOAD_ADDRESS_SHIFT               (2U)
#define GPMI_PAYLOAD_ADDRESS(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK)
/*! @} */

/*! @name AUXILIARY - GPMI Auxiliary Address Register Description */
/*! @{ */
#define GPMI_AUXILIARY_RSVD0_MASK                (0x3U)
#define GPMI_AUXILIARY_RSVD0_SHIFT               (0U)
#define GPMI_AUXILIARY_RSVD0(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK)
#define GPMI_AUXILIARY_ADDRESS_MASK              (0xFFFFFFFCU)
#define GPMI_AUXILIARY_ADDRESS_SHIFT             (2U)
#define GPMI_AUXILIARY_ADDRESS(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK)
/*! @} */

/*! @name CTRL1 - GPMI Control Register 1 Description */
/*! @{ */
#define GPMI_CTRL1_GPMI_MODE_MASK                (0x1U)
#define GPMI_CTRL1_GPMI_MODE_SHIFT               (0U)
/*! GPMI_MODE - GPMI_MODE
 *  0b0..NAND mode.
 *  0b1..ATA mode.
 */
#define GPMI_CTRL1_GPMI_MODE(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK)
#define GPMI_CTRL1_CAMERA_MODE_MASK              (0x2U)
#define GPMI_CTRL1_CAMERA_MODE_SHIFT             (1U)
#define GPMI_CTRL1_CAMERA_MODE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK)
#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK      (0x4U)
#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT     (2U)
/*! ATA_IRQRDY_POLARITY - ATA_IRQRDY_POLARITY
 *  0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
 *  0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
 */
#define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK)
#define GPMI_CTRL1_DEV_RESET_MASK                (0x8U)
#define GPMI_CTRL1_DEV_RESET_SHIFT               (3U)
/*! DEV_RESET - DEV_RESET
 *  0b0..NANDF_WP_B pin is held low (asserted).
 *  0b1..NANDF_WP_B pin is held high (de-asserted).
 */
#define GPMI_CTRL1_DEV_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK)
#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
#define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK       (0x80U)
#define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT      (7U)
#define GPMI_CTRL1_ABORT_WAIT_REQUEST(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK)
#define GPMI_CTRL1_BURST_EN_MASK                 (0x100U)
#define GPMI_CTRL1_BURST_EN_SHIFT                (8U)
#define GPMI_CTRL1_BURST_EN(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK)
#define GPMI_CTRL1_TIMEOUT_IRQ_MASK              (0x200U)
#define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT             (9U)
#define GPMI_CTRL1_TIMEOUT_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK)
#define GPMI_CTRL1_DEV_IRQ_MASK                  (0x400U)
#define GPMI_CTRL1_DEV_IRQ_SHIFT                 (10U)
#define GPMI_CTRL1_DEV_IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK)
#define GPMI_CTRL1_DMA2ECC_MODE_MASK             (0x800U)
#define GPMI_CTRL1_DMA2ECC_MODE_SHIFT            (11U)
#define GPMI_CTRL1_DMA2ECC_MODE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK)
#define GPMI_CTRL1_RDN_DELAY_MASK                (0xF000U)
#define GPMI_CTRL1_RDN_DELAY_SHIFT               (12U)
#define GPMI_CTRL1_RDN_DELAY(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK)
#define GPMI_CTRL1_HALF_PERIOD_MASK              (0x10000U)
#define GPMI_CTRL1_HALF_PERIOD_SHIFT             (16U)
#define GPMI_CTRL1_HALF_PERIOD(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK)
#define GPMI_CTRL1_DLL_ENABLE_MASK               (0x20000U)
#define GPMI_CTRL1_DLL_ENABLE_SHIFT              (17U)
#define GPMI_CTRL1_DLL_ENABLE(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK)
#define GPMI_CTRL1_BCH_MODE_MASK                 (0x40000U)
#define GPMI_CTRL1_BCH_MODE_SHIFT                (18U)
#define GPMI_CTRL1_BCH_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK)
#define GPMI_CTRL1_GANGED_RDYBUSY_MASK           (0x80000U)
#define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT          (19U)
#define GPMI_CTRL1_GANGED_RDYBUSY(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK)
#define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK           (0x100000U)
#define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT          (20U)
#define GPMI_CTRL1_TIMEOUT_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK)
#define GPMI_CTRL1_RSVD1_MASK                    (0x200000U)
#define GPMI_CTRL1_RSVD1_SHIFT                   (21U)
#define GPMI_CTRL1_RSVD1(x)                      (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RSVD1_SHIFT)) & GPMI_CTRL1_RSVD1_MASK)
#define GPMI_CTRL1_WRN_DLY_SEL_MASK              (0xC00000U)
#define GPMI_CTRL1_WRN_DLY_SEL_SHIFT             (22U)
#define GPMI_CTRL1_WRN_DLY_SEL(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK)
#define GPMI_CTRL1_DECOUPLE_CS_MASK              (0x1000000U)
#define GPMI_CTRL1_DECOUPLE_CS_SHIFT             (24U)
#define GPMI_CTRL1_DECOUPLE_CS(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK)
#define GPMI_CTRL1_SSYNCMODE_MASK                (0x2000000U)
#define GPMI_CTRL1_SSYNCMODE_SHIFT               (25U)
#define GPMI_CTRL1_SSYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK)
#define GPMI_CTRL1_UPDATE_CS_MASK                (0x4000000U)
#define GPMI_CTRL1_UPDATE_CS_SHIFT               (26U)
#define GPMI_CTRL1_UPDATE_CS(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK)
#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK         (0x8000000U)
#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT        (27U)
/*! GPMI_CLK_DIV2_EN - GPMI_CLK_DIV2_EN
 *  0b0..internal factor-2 clock divider is disabled
 *  0b1..internal factor-2 clock divider is enabled.
 */
#define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK)
#define GPMI_CTRL1_TOGGLE_MODE_MASK              (0x10000000U)
#define GPMI_CTRL1_TOGGLE_MODE_SHIFT             (28U)
#define GPMI_CTRL1_TOGGLE_MODE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK)
#define GPMI_CTRL1_WRITE_CLK_STOP_MASK           (0x20000000U)
#define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT          (29U)
#define GPMI_CTRL1_WRITE_CLK_STOP(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK)
#define GPMI_CTRL1_SSYNC_CLK_STOP_MASK           (0x40000000U)
#define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT          (30U)
#define GPMI_CTRL1_SSYNC_CLK_STOP(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK)
#define GPMI_CTRL1_DEV_CLK_STOP_MASK             (0x80000000U)
#define GPMI_CTRL1_DEV_CLK_STOP_SHIFT            (31U)
#define GPMI_CTRL1_DEV_CLK_STOP(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK)
/*! @} */

/*! @name TIMING0 - GPMI Timing Register 0 Description */
/*! @{ */
#define GPMI_TIMING0_DATA_SETUP_MASK             (0xFFU)
#define GPMI_TIMING0_DATA_SETUP_SHIFT            (0U)
#define GPMI_TIMING0_DATA_SETUP(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK)
#define GPMI_TIMING0_DATA_HOLD_MASK              (0xFF00U)
#define GPMI_TIMING0_DATA_HOLD_SHIFT             (8U)
#define GPMI_TIMING0_DATA_HOLD(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK)
#define GPMI_TIMING0_ADDRESS_SETUP_MASK          (0xFF0000U)
#define GPMI_TIMING0_ADDRESS_SETUP_SHIFT         (16U)
#define GPMI_TIMING0_ADDRESS_SETUP(x)            (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK)
#define GPMI_TIMING0_RSVD1_MASK                  (0xFF000000U)
#define GPMI_TIMING0_RSVD1_SHIFT                 (24U)
#define GPMI_TIMING0_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK)
/*! @} */

/*! @name TIMING1 - GPMI Timing Register 1 Description */
/*! @{ */
#define GPMI_TIMING1_RSVD1_MASK                  (0xFFFFU)
#define GPMI_TIMING1_RSVD1_SHIFT                 (0U)
#define GPMI_TIMING1_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK)
#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK    (0xFFFF0000U)
#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT   (16U)
#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x)      (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK)
/*! @} */

/*! @name TIMING2 - GPMI Timing Register 2 Description */
/*! @{ */
#define GPMI_TIMING2_DATA_PAUSE_MASK             (0xFU)
#define GPMI_TIMING2_DATA_PAUSE_SHIFT            (0U)
#define GPMI_TIMING2_DATA_PAUSE(x)               (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK)
#define GPMI_TIMING2_CMDADD_PAUSE_MASK           (0xF0U)
#define GPMI_TIMING2_CMDADD_PAUSE_SHIFT          (4U)
#define GPMI_TIMING2_CMDADD_PAUSE(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK)
#define GPMI_TIMING2_POSTAMBLE_DELAY_MASK        (0xF00U)
#define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT       (8U)
#define GPMI_TIMING2_POSTAMBLE_DELAY(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK)
#define GPMI_TIMING2_PREAMBLE_DELAY_MASK         (0xF000U)
#define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT        (12U)
#define GPMI_TIMING2_PREAMBLE_DELAY(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK)
#define GPMI_TIMING2_CE_DELAY_MASK               (0x1F0000U)
#define GPMI_TIMING2_CE_DELAY_SHIFT              (16U)
#define GPMI_TIMING2_CE_DELAY(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK)
#define GPMI_TIMING2_RSVD0_MASK                  (0xE00000U)
#define GPMI_TIMING2_RSVD0_SHIFT                 (21U)
#define GPMI_TIMING2_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK)
#define GPMI_TIMING2_READ_LATENCY_MASK           (0x7000000U)
#define GPMI_TIMING2_READ_LATENCY_SHIFT          (24U)
/*! READ_LATENCY - READ_LATENCY
 *  0b000..READ LATENCY is 0
 *  0b001..READ LATENCY is 1
 *  0b010..READ LATENCY is 2
 *  0b011..READ LATENCY is 3
 *  0b100..READ LATENCY is 4
 *  0b101..READ LATENCY is 5
 */
#define GPMI_TIMING2_READ_LATENCY(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK)
#define GPMI_TIMING2_RSVD1_MASK                  (0xF8000000U)
#define GPMI_TIMING2_RSVD1_SHIFT                 (27U)
#define GPMI_TIMING2_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD1_SHIFT)) & GPMI_TIMING2_RSVD1_MASK)
/*! @} */

/*! @name DATA - GPMI DMA Data Transfer Register Description */
/*! @{ */
#define GPMI_DATA_DATA_MASK                      (0xFFFFFFFFU)
#define GPMI_DATA_DATA_SHIFT                     (0U)
#define GPMI_DATA_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK)
/*! @} */

/*! @name STAT - GPMI Status Register Description */
/*! @{ */
#define GPMI_STAT_PRESENT_MASK                   (0x1U)
#define GPMI_STAT_PRESENT_SHIFT                  (0U)
/*! PRESENT - PRESENT
 *  0b0..GPMI is not present in this product.
 *  0b1..GPMI is present is in this product.
 */
#define GPMI_STAT_PRESENT(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK)
#define GPMI_STAT_FIFO_FULL_MASK                 (0x2U)
#define GPMI_STAT_FIFO_FULL_SHIFT                (1U)
/*! FIFO_FULL - FIFO_FULL
 *  0b0..FIFO is not full.
 *  0b1..FIFO is full.
 */
#define GPMI_STAT_FIFO_FULL(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK)
#define GPMI_STAT_FIFO_EMPTY_MASK                (0x4U)
#define GPMI_STAT_FIFO_EMPTY_SHIFT               (2U)
/*! FIFO_EMPTY - FIFO_EMPTY
 *  0b0..FIFO is not empty.
 *  0b1..FIFO is empty.
 */
#define GPMI_STAT_FIFO_EMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK)
#define GPMI_STAT_INVALID_BUFFER_MASK_MASK       (0x8U)
#define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT      (3U)
/*! INVALID_BUFFER_MASK - INVALID_BUFFER_MASK
 *  0b0..ECC Buffer Mask is not invalid.
 *  0b1..ECC Buffer Mask is invalid.
 */
#define GPMI_STAT_INVALID_BUFFER_MASK(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK)
#define GPMI_STAT_ATA_IRQ_MASK                   (0x10U)
#define GPMI_STAT_ATA_IRQ_SHIFT                  (4U)
#define GPMI_STAT_ATA_IRQ(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK)
#define GPMI_STAT_RSVD1_MASK                     (0xE0U)
#define GPMI_STAT_RSVD1_SHIFT                    (5U)
#define GPMI_STAT_RSVD1(x)                       (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK)
#define GPMI_STAT_DEV0_ERROR_MASK                (0x100U)
#define GPMI_STAT_DEV0_ERROR_SHIFT               (8U)
/*! DEV0_ERROR - DEV0_ERROR
 *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 0.
 *  0b1..An Error has occurred on ATA/NAND Device accessed by
 */
#define GPMI_STAT_DEV0_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK)
#define GPMI_STAT_DEV1_ERROR_MASK                (0x200U)
#define GPMI_STAT_DEV1_ERROR_SHIFT               (9U)
/*! DEV1_ERROR - DEV1_ERROR
 *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 1.
 *  0b1..An Error has occurred on ATA/NAND Device accessed by
 */
#define GPMI_STAT_DEV1_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK)
#define GPMI_STAT_DEV2_ERROR_MASK                (0x400U)
#define GPMI_STAT_DEV2_ERROR_SHIFT               (10U)
/*! DEV2_ERROR - DEV2_ERROR
 *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 2.
 *  0b1..An Error has occurred on ATA/NAND Device accessed by
 */
#define GPMI_STAT_DEV2_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK)
#define GPMI_STAT_DEV3_ERROR_MASK                (0x800U)
#define GPMI_STAT_DEV3_ERROR_SHIFT               (11U)
/*! DEV3_ERROR - DEV3_ERROR
 *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 3.
 *  0b1..An Error has occurred on ATA/NAND Device accessed by
 */
#define GPMI_STAT_DEV3_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK)
#define GPMI_STAT_DEV4_ERROR_MASK                (0x1000U)
#define GPMI_STAT_DEV4_ERROR_SHIFT               (12U)
/*! DEV4_ERROR - DEV4_ERROR
 *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 4.
 *  0b1..An Error has occurred on ATA/NAND Device accessed by
 */
#define GPMI_STAT_DEV4_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK)
#define GPMI_STAT_DEV5_ERROR_MASK                (0x2000U)
#define GPMI_STAT_DEV5_ERROR_SHIFT               (13U)
/*! DEV5_ERROR - DEV5_ERROR
 *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 5.
 *  0b1..An Error has occurred on ATA/NAND Device accessed by
 */
#define GPMI_STAT_DEV5_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK)
#define GPMI_STAT_DEV6_ERROR_MASK                (0x4000U)
#define GPMI_STAT_DEV6_ERROR_SHIFT               (14U)
/*! DEV6_ERROR - DEV6_ERROR
 *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 6.
 *  0b1..An Error has occurred on ATA/NAND Device accessed by
 */
#define GPMI_STAT_DEV6_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK)
#define GPMI_STAT_DEV7_ERROR_MASK                (0x8000U)
#define GPMI_STAT_DEV7_ERROR_SHIFT               (15U)
/*! DEV7_ERROR - DEV7_ERROR
 *  0b0..No error condition present on ATA/NAND Device accessed by DMA channel 7.
 *  0b1..An Error has occurred on ATA/NAND Device accessed by
 */
#define GPMI_STAT_DEV7_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK)
#define GPMI_STAT_RDY_TIMEOUT_MASK               (0xFF0000U)
#define GPMI_STAT_RDY_TIMEOUT_SHIFT              (16U)
#define GPMI_STAT_RDY_TIMEOUT(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK)
#define GPMI_STAT_READY_BUSY_MASK                (0xFF000000U)
#define GPMI_STAT_READY_BUSY_SHIFT               (24U)
#define GPMI_STAT_READY_BUSY(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK)
/*! @} */

/*! @name DEBUG - GPMI Debug Information Register Description */
/*! @{ */
#define GPMI_DEBUG_CMD_END_MASK                  (0xFFU)
#define GPMI_DEBUG_CMD_END_SHIFT                 (0U)
#define GPMI_DEBUG_CMD_END(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK)
#define GPMI_DEBUG_DMAREQ_MASK                   (0xFF00U)
#define GPMI_DEBUG_DMAREQ_SHIFT                  (8U)
#define GPMI_DEBUG_DMAREQ(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK)
#define GPMI_DEBUG_DMA_SENSE_MASK                (0xFF0000U)
#define GPMI_DEBUG_DMA_SENSE_SHIFT               (16U)
#define GPMI_DEBUG_DMA_SENSE(x)                  (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK)
#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK       (0xFF000000U)
#define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT      (24U)
#define GPMI_DEBUG_WAIT_FOR_READY_END(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK)
/*! @} */

/*! @name VERSION - GPMI Version Register Description */
/*! @{ */
#define GPMI_VERSION_STEP_MASK                   (0xFFFFU)
#define GPMI_VERSION_STEP_SHIFT                  (0U)
#define GPMI_VERSION_STEP(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK)
#define GPMI_VERSION_MINOR_MASK                  (0xFF0000U)
#define GPMI_VERSION_MINOR_SHIFT                 (16U)
#define GPMI_VERSION_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK)
#define GPMI_VERSION_MAJOR_MASK                  (0xFF000000U)
#define GPMI_VERSION_MAJOR_SHIFT                 (24U)
#define GPMI_VERSION_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK)
/*! @} */

/*! @name DEBUG2 - GPMI Debug2 Information Register Description */
/*! @{ */
#define GPMI_DEBUG2_RDN_TAP_MASK                 (0x3FU)
#define GPMI_DEBUG2_RDN_TAP_SHIFT                (0U)
#define GPMI_DEBUG2_RDN_TAP(x)                   (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK)
#define GPMI_DEBUG2_UPDATE_WINDOW_MASK           (0x40U)
#define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT          (6U)
#define GPMI_DEBUG2_UPDATE_WINDOW(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK)
#define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK        (0x80U)
#define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT       (7U)
#define GPMI_DEBUG2_VIEW_DELAYED_RDN(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK)
#define GPMI_DEBUG2_SYND2GPMI_READY_MASK         (0x100U)
#define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT        (8U)
#define GPMI_DEBUG2_SYND2GPMI_READY(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK)
#define GPMI_DEBUG2_SYND2GPMI_VALID_MASK         (0x200U)
#define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT        (9U)
#define GPMI_DEBUG2_SYND2GPMI_VALID(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK)
#define GPMI_DEBUG2_GPMI2SYND_READY_MASK         (0x400U)
#define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT        (10U)
#define GPMI_DEBUG2_GPMI2SYND_READY(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK)
#define GPMI_DEBUG2_GPMI2SYND_VALID_MASK         (0x800U)
#define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT        (11U)
#define GPMI_DEBUG2_GPMI2SYND_VALID(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK)
#define GPMI_DEBUG2_SYND2GPMI_BE_MASK            (0xF000U)
#define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT           (12U)
#define GPMI_DEBUG2_SYND2GPMI_BE(x)              (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK)
#define GPMI_DEBUG2_MAIN_STATE_MASK              (0xF0000U)
#define GPMI_DEBUG2_MAIN_STATE_SHIFT             (16U)
#define GPMI_DEBUG2_MAIN_STATE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK)
#define GPMI_DEBUG2_PIN_STATE_MASK               (0x700000U)
#define GPMI_DEBUG2_PIN_STATE_SHIFT              (20U)
#define GPMI_DEBUG2_PIN_STATE(x)                 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK)
#define GPMI_DEBUG2_BUSY_MASK                    (0x800000U)
#define GPMI_DEBUG2_BUSY_SHIFT                   (23U)
#define GPMI_DEBUG2_BUSY(x)                      (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK)
#define GPMI_DEBUG2_UDMA_STATE_MASK              (0xF000000U)
#define GPMI_DEBUG2_UDMA_STATE_SHIFT             (24U)
#define GPMI_DEBUG2_UDMA_STATE(x)                (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK)
#define GPMI_DEBUG2_RSVD1_MASK                   (0xF0000000U)
#define GPMI_DEBUG2_RSVD1_SHIFT                  (28U)
#define GPMI_DEBUG2_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK)
/*! @} */

/*! @name DEBUG3 - GPMI Debug3 Information Register Description */
/*! @{ */
#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK           (0xFFFFU)
#define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT          (0U)
#define GPMI_DEBUG3_DEV_WORD_CNTR(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK)
#define GPMI_DEBUG3_APB_WORD_CNTR_MASK           (0xFFFF0000U)
#define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT          (16U)
#define GPMI_DEBUG3_APB_WORD_CNTR(x)             (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK)
/*! @} */

/*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */
/*! @{ */
#define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK       (0x1U)
#define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT      (0U)
#define GPMI_READ_DDR_DLL_CTRL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK)
#define GPMI_READ_DDR_DLL_CTRL_RESET_MASK        (0x2U)
#define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT       (1U)
#define GPMI_READ_DDR_DLL_CTRL_RESET(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK)
#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x)  (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK)
#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK  (0x80U)
#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x)    (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK)
#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK    (0x100U)
#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT   (8U)
#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x)      (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK)
#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK)
#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
#define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK        (0xC0000U)
#define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT       (18U)
#define GPMI_READ_DDR_DLL_CTRL_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK)
#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */

/*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */
/*! @{ */
#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK      (0x1U)
#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT     (0U)
#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK       (0x2U)
#define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT      (1U)
#define GPMI_WRITE_DDR_DLL_CTRL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x)   (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK   (0x100U)
#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT  (8U)
#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x)     (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK       (0xC0000U)
#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT      (18U)
#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */

/*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */
/*! @{ */
#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK      (0x1U)
#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT     (0U)
#define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK)
#define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK       (0x1FEU)
#define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT      (1U)
#define GPMI_READ_DDR_DLL_STS_SLV_SEL(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK)
#define GPMI_READ_DDR_DLL_STS_RSVD0_MASK         (0xFE00U)
#define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT        (9U)
#define GPMI_READ_DDR_DLL_STS_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK)
#define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK      (0x10000U)
#define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT     (16U)
#define GPMI_READ_DDR_DLL_STS_REF_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK)
#define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK       (0x1FE0000U)
#define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT      (17U)
#define GPMI_READ_DDR_DLL_STS_REF_SEL(x)         (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK)
#define GPMI_READ_DDR_DLL_STS_RSVD1_MASK         (0xFE000000U)
#define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT        (25U)
#define GPMI_READ_DDR_DLL_STS_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK)
/*! @} */

/*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */
/*! @{ */
#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK     (0x1U)
#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT    (0U)
#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK)
#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK      (0x1FEU)
#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT     (1U)
#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK)
#define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK        (0xFE00U)
#define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT       (9U)
#define GPMI_WRITE_DDR_DLL_STS_RSVD0(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK)
#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK     (0x10000U)
#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT    (16U)
#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK)
#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK      (0x1FE0000U)
#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT     (17U)
#define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x)        (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK)
#define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK        (0xFE000000U)
#define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT       (25U)
#define GPMI_WRITE_DDR_DLL_STS_RSVD1(x)          (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group GPMI_Register_Masks */


/* GPMI - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__GPMI base address */
#define CONNECTIVITY__GPMI_BASE                  (0x5B812000u)
/** Peripheral CONNECTIVITY__GPMI base pointer */
#define CONNECTIVITY__GPMI                       ((GPMI_Type *)CONNECTIVITY__GPMI_BASE)
/** Array initializer of GPMI peripheral base addresses */
#define GPMI_BASE_ADDRS                          { CONNECTIVITY__GPMI_BASE }
/** Array initializer of GPMI peripheral base pointers */
#define GPMI_BASE_PTRS                           { CONNECTIVITY__GPMI }

/*!
 * @}
 */ /* end of group GPMI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GPT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
 * @{
 */

/** GPT - Register Layout Typedef */
typedef struct {
  __IO uint32_t CR;                                /**< GPT Control Register, offset: 0x0 */
  __IO uint32_t PR;                                /**< GPT Prescaler Register, offset: 0x4 */
  __IO uint32_t SR;                                /**< GPT Status Register, offset: 0x8 */
  __IO uint32_t IR;                                /**< GPT Interrupt Register, offset: 0xC */
  __IO uint32_t OCR[3];                            /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */
  __I  uint32_t ICR[2];                            /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */
  __I  uint32_t CNT;                               /**< GPT Counter Register, offset: 0x24 */
} GPT_Type;

/* ----------------------------------------------------------------------------
   -- GPT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GPT_Register_Masks GPT Register Masks
 * @{
 */

/*! @name CR - GPT Control Register */
/*! @{ */
#define GPT_CR_EN_MASK                           (0x1U)
#define GPT_CR_EN_SHIFT                          (0U)
/*! EN - EN
 *  0b0..GPT is disabled.
 *  0b1..GPT is enabled.
 */
#define GPT_CR_EN(x)                             (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
#define GPT_CR_ENMOD_MASK                        (0x2U)
#define GPT_CR_ENMOD_SHIFT                       (1U)
/*! ENMOD - ENMOD
 *  0b0..GPT counter will retain its value when it is disabled.
 *  0b1..GPT counter value is reset to 0 when it is disabled.
 */
#define GPT_CR_ENMOD(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
#define GPT_CR_DBGEN_MASK                        (0x4U)
#define GPT_CR_DBGEN_SHIFT                       (2U)
/*! DBGEN - DBGEN
 *  0b0..GPT is disabled in debug mode.
 *  0b1..GPT is enabled in debug mode.
 */
#define GPT_CR_DBGEN(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
#define GPT_CR_WAITEN_MASK                       (0x8U)
#define GPT_CR_WAITEN_SHIFT                      (3U)
/*! WAITEN - WAITEN
 *  0b0..GPT is disabled in wait mode.
 *  0b1..GPT is enabled in wait mode.
 */
#define GPT_CR_WAITEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
#define GPT_CR_DOZEEN_MASK                       (0x10U)
#define GPT_CR_DOZEEN_SHIFT                      (4U)
/*! DOZEEN - DOZEEN
 *  0b0..GPT is disabled in doze mode.
 *  0b1..GPT is enabled in doze mode.
 */
#define GPT_CR_DOZEEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
#define GPT_CR_STOPEN_MASK                       (0x20U)
#define GPT_CR_STOPEN_SHIFT                      (5U)
/*! STOPEN - STOPEN
 *  0b0..GPT is disabled in Stop mode.
 *  0b1..GPT is enabled in Stop mode.
 */
#define GPT_CR_STOPEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
#define GPT_CR_CLKSRC_MASK                       (0x1C0U)
#define GPT_CR_CLKSRC_SHIFT                      (6U)
/*! CLKSRC - CLKSRC
 *  0b000..No clock
 *  0b001..Peripheral Clock (ipg_clk)
 *  0b010..High Frequency Reference Clock (ipg_clk_highfreq)
 *  0b100..Low Frequency Reference Clock (ipg_clk_32k)
 *  0b101..Crystal oscillator as Reference Clock (ipg_clk_24M)
 */
#define GPT_CR_CLKSRC(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
#define GPT_CR_FRR_MASK                          (0x200U)
#define GPT_CR_FRR_SHIFT                         (9U)
/*! FRR - FRR
 *  0b0..Restart mode
 *  0b1..Free-Run mode
 */
#define GPT_CR_FRR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
#define GPT_CR_EN_24M_MASK                       (0x400U)
#define GPT_CR_EN_24M_SHIFT                      (10U)
/*! EN_24M - EN_24M
 *  0b0..24M clock disabled
 *  0b1..24M clock enabled
 */
#define GPT_CR_EN_24M(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
#define GPT_CR_SWR_MASK                          (0x8000U)
#define GPT_CR_SWR_SHIFT                         (15U)
/*! SWR - SWR
 *  0b0..GPT is not in reset state
 *  0b1..GPT is in reset state
 */
#define GPT_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
#define GPT_CR_IM1_MASK                          (0x30000U)
#define GPT_CR_IM1_SHIFT                         (16U)
#define GPT_CR_IM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
#define GPT_CR_IM2_MASK                          (0xC0000U)
#define GPT_CR_IM2_SHIFT                         (18U)
/*! IM2 - IM2
 *  0b00..capture disabled
 *  0b01..capture on rising edge only
 *  0b10..capture on falling edge only
 *  0b11..capture on both edges
 */
#define GPT_CR_IM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
#define GPT_CR_OM1_MASK                          (0x700000U)
#define GPT_CR_OM1_SHIFT                         (20U)
#define GPT_CR_OM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
#define GPT_CR_OM2_MASK                          (0x3800000U)
#define GPT_CR_OM2_SHIFT                         (23U)
#define GPT_CR_OM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
#define GPT_CR_OM3_MASK                          (0x1C000000U)
#define GPT_CR_OM3_SHIFT                         (26U)
/*! OM3 - OM3
 *  0b000..Output disconnected. No response on pin.
 *  0b001..Toggle output pin
 *  0b010..Clear output pin
 *  0b011..Set output pin
 *  0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin.
 */
#define GPT_CR_OM3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
#define GPT_CR_FO1_MASK                          (0x20000000U)
#define GPT_CR_FO1_SHIFT                         (29U)
#define GPT_CR_FO1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
#define GPT_CR_FO2_MASK                          (0x40000000U)
#define GPT_CR_FO2_SHIFT                         (30U)
#define GPT_CR_FO2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
#define GPT_CR_FO3_MASK                          (0x80000000U)
#define GPT_CR_FO3_SHIFT                         (31U)
/*! FO3 - FO3
 *  0b0..Writing a 0 has no effect.
 */
#define GPT_CR_FO3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
/*! @} */

/*! @name PR - GPT Prescaler Register */
/*! @{ */
#define GPT_PR_PRESCALER_MASK                    (0xFFFU)
#define GPT_PR_PRESCALER_SHIFT                   (0U)
/*! PRESCALER - PRESCALER
 *  0b000000000000..Divide by 1
 *  0b000000000001..Divide by 2
 *  0b111111111111..Divide by 4096
 */
#define GPT_PR_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
#define GPT_PR_PRESCALER24M_MASK                 (0xF000U)
#define GPT_PR_PRESCALER24M_SHIFT                (12U)
/*! PRESCALER24M - PRESCALER24M
 *  0b0000..Divide by 1
 *  0b0001..Divide by 2
 *  0b1111..Divide by 16
 */
#define GPT_PR_PRESCALER24M(x)                   (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
/*! @} */

/*! @name SR - GPT Status Register */
/*! @{ */
#define GPT_SR_OF1_MASK                          (0x1U)
#define GPT_SR_OF1_SHIFT                         (0U)
#define GPT_SR_OF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
#define GPT_SR_OF2_MASK                          (0x2U)
#define GPT_SR_OF2_SHIFT                         (1U)
#define GPT_SR_OF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
#define GPT_SR_OF3_MASK                          (0x4U)
#define GPT_SR_OF3_SHIFT                         (2U)
/*! OF3 - OF3
 *  0b0..Compare event has not occurred.
 *  0b1..Compare event has occurred.
 */
#define GPT_SR_OF3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
#define GPT_SR_IF1_MASK                          (0x8U)
#define GPT_SR_IF1_SHIFT                         (3U)
#define GPT_SR_IF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
#define GPT_SR_IF2_MASK                          (0x10U)
#define GPT_SR_IF2_SHIFT                         (4U)
/*! IF2 - IF2
 *  0b0..Capture event has not occurred.
 *  0b1..Capture event has occurred.
 */
#define GPT_SR_IF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
#define GPT_SR_ROV_MASK                          (0x20U)
#define GPT_SR_ROV_SHIFT                         (5U)
/*! ROV - ROV
 *  0b0..Rollover has not occurred.
 *  0b1..Rollover has occurred.
 */
#define GPT_SR_ROV(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
/*! @} */

/*! @name IR - GPT Interrupt Register */
/*! @{ */
#define GPT_IR_OF1IE_MASK                        (0x1U)
#define GPT_IR_OF1IE_SHIFT                       (0U)
#define GPT_IR_OF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
#define GPT_IR_OF2IE_MASK                        (0x2U)
#define GPT_IR_OF2IE_SHIFT                       (1U)
#define GPT_IR_OF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
#define GPT_IR_OF3IE_MASK                        (0x4U)
#define GPT_IR_OF3IE_SHIFT                       (2U)
#define GPT_IR_OF3IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
#define GPT_IR_IF1IE_MASK                        (0x8U)
#define GPT_IR_IF1IE_SHIFT                       (3U)
#define GPT_IR_IF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
#define GPT_IR_IF2IE_MASK                        (0x10U)
#define GPT_IR_IF2IE_SHIFT                       (4U)
#define GPT_IR_IF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
#define GPT_IR_ROVIE_MASK                        (0x20U)
#define GPT_IR_ROVIE_SHIFT                       (5U)
/*! ROVIE - ROVIE
 *  0b0..Rollover interrupt is disabled.
 *  0b1..Rollover interrupt enabled.
 */
#define GPT_IR_ROVIE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
/*! @} */

/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */
/*! @{ */
#define GPT_OCR_COMP_MASK                        (0xFFFFFFFFU)
#define GPT_OCR_COMP_SHIFT                       (0U)
#define GPT_OCR_COMP(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
/*! @} */

/* The count of GPT_OCR */
#define GPT_OCR_COUNT                            (3U)

/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */
/*! @{ */
#define GPT_ICR_CAPT_MASK                        (0xFFFFFFFFU)
#define GPT_ICR_CAPT_SHIFT                       (0U)
#define GPT_ICR_CAPT(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
/*! @} */

/* The count of GPT_ICR */
#define GPT_ICR_COUNT                            (2U)

/*! @name CNT - GPT Counter Register */
/*! @{ */
#define GPT_CNT_COUNT_MASK                       (0xFFFFFFFFU)
#define GPT_CNT_COUNT_SHIFT                      (0U)
#define GPT_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group GPT_Register_Masks */


/* GPT - Peripheral instance base addresses */
/** Peripheral AUDIO__GPT0 base address */
#define AUDIO__GPT0_BASE                         (0x590B0000u)
/** Peripheral AUDIO__GPT0 base pointer */
#define AUDIO__GPT0                              ((GPT_Type *)AUDIO__GPT0_BASE)
/** Peripheral AUDIO__GPT1 base address */
#define AUDIO__GPT1_BASE                         (0x590C0000u)
/** Peripheral AUDIO__GPT1 base pointer */
#define AUDIO__GPT1                              ((GPT_Type *)AUDIO__GPT1_BASE)
/** Peripheral AUDIO__GPT2 base address */
#define AUDIO__GPT2_BASE                         (0x590D0000u)
/** Peripheral AUDIO__GPT2 base pointer */
#define AUDIO__GPT2                              ((GPT_Type *)AUDIO__GPT2_BASE)
/** Peripheral AUDIO__GPT3 base address */
#define AUDIO__GPT3_BASE                         (0x590E0000u)
/** Peripheral AUDIO__GPT3 base pointer */
#define AUDIO__GPT3                              ((GPT_Type *)AUDIO__GPT3_BASE)
/** Peripheral AUDIO__GPT4 base address */
#define AUDIO__GPT4_BASE                         (0x590F0000u)
/** Peripheral AUDIO__GPT4 base pointer */
#define AUDIO__GPT4                              ((GPT_Type *)AUDIO__GPT4_BASE)
/** Peripheral AUDIO__GPT5 base address */
#define AUDIO__GPT5_BASE                         (0x59100000u)
/** Peripheral AUDIO__GPT5 base pointer */
#define AUDIO__GPT5                              ((GPT_Type *)AUDIO__GPT5_BASE)
/** Peripheral LSIO__GPT0 base address */
#define LSIO__GPT0_BASE                          (0x5D140000u)
/** Peripheral LSIO__GPT0 base pointer */
#define LSIO__GPT0                               ((GPT_Type *)LSIO__GPT0_BASE)
/** Peripheral LSIO__GPT1 base address */
#define LSIO__GPT1_BASE                          (0x5D150000u)
/** Peripheral LSIO__GPT1 base pointer */
#define LSIO__GPT1                               ((GPT_Type *)LSIO__GPT1_BASE)
/** Peripheral LSIO__GPT2 base address */
#define LSIO__GPT2_BASE                          (0x5D160000u)
/** Peripheral LSIO__GPT2 base pointer */
#define LSIO__GPT2                               ((GPT_Type *)LSIO__GPT2_BASE)
/** Peripheral LSIO__GPT3 base address */
#define LSIO__GPT3_BASE                          (0x5D170000u)
/** Peripheral LSIO__GPT3 base pointer */
#define LSIO__GPT3                               ((GPT_Type *)LSIO__GPT3_BASE)
/** Peripheral LSIO__GPT4 base address */
#define LSIO__GPT4_BASE                          (0x5D180000u)
/** Peripheral LSIO__GPT4 base pointer */
#define LSIO__GPT4                               ((GPT_Type *)LSIO__GPT4_BASE)
/** Array initializer of GPT peripheral base addresses */
#define GPT_BASE_ADDRS                           { AUDIO__GPT0_BASE, AUDIO__GPT1_BASE, AUDIO__GPT2_BASE, AUDIO__GPT3_BASE, AUDIO__GPT4_BASE, AUDIO__GPT5_BASE, LSIO__GPT0_BASE, LSIO__GPT1_BASE, LSIO__GPT2_BASE, LSIO__GPT3_BASE, LSIO__GPT4_BASE }
/** Array initializer of GPT peripheral base pointers */
#define GPT_BASE_PTRS                            { AUDIO__GPT0, AUDIO__GPT1, AUDIO__GPT2, AUDIO__GPT3, AUDIO__GPT4, AUDIO__GPT5, LSIO__GPT0, LSIO__GPT1, LSIO__GPT2, LSIO__GPT3, LSIO__GPT4 }
/** Interrupt vectors for the GPT peripheral type */
#define GPT_IRQS                                 { AUDIO_GPT0_INT_IRQn, AUDIO_GPT1_INT_IRQn, AUDIO_GPT2_INT_IRQn, AUDIO_GPT3_INT_IRQn, AUDIO_GPT4_INT_IRQn, AUDIO_GPT5_INT_IRQn, LSIO_GPT0_INT_IRQn, LSIO_GPT1_INT_IRQn, LSIO_GPT2_INT_IRQn, LSIO_GPT3_INT_IRQn, LSIO_GPT4_INT_IRQn }

/*!
 * @}
 */ /* end of group GPT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_GPIO Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_GPIO_Peripheral_Access_Layer HSIO_LPCG_GPIO Peripheral Access Layer
 * @{
 */

/** HSIO_LPCG_GPIO - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_GPIO_CLK_0;                   /**< na, offset: 0x0 */
} HSIO_LPCG_GPIO_Type;

/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_GPIO Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_GPIO_Register_Masks HSIO_LPCG_GPIO Register Masks
 * @{
 */

/*! @name LPCG_GPIO_CLK_0 - na */
/*! @{ */
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15_MASK (0xFFFFU)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15_SHIFT (0U)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15_SHIFT)) & HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_0_15_MASK)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN_MASK (0x10000U)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN_SHIFT (16U)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN_SHIFT)) & HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_HWEN_MASK)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN_MASK (0x20000U)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN_SHIFT (17U)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN_SHIFT)) & HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_SWEN_MASK)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18_MASK (0x40000U)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18_SHIFT (18U)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18_SHIFT)) & HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_18_18_MASK)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP_MASK (0x80000U)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP_SHIFT (19U)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP_SHIFT)) & HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_gpio_ipg_clk_s_STOP_MASK)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31_MASK (0xFFF00000U)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31_SHIFT (20U)
#define HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31_SHIFT)) & HSIO_LPCG_GPIO_LPCG_GPIO_CLK_0_LPCG_GPIO_CLK_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group HSIO_LPCG_GPIO_Register_Masks */


/* HSIO_LPCG_GPIO - Peripheral instance base addresses */
/** Peripheral HSIO__LPCG_GPIO base address */
#define HSIO__LPCG_GPIO_BASE                     (0x5F100000u)
/** Peripheral HSIO__LPCG_GPIO base pointer */
#define HSIO__LPCG_GPIO                          ((HSIO_LPCG_GPIO_Type *)HSIO__LPCG_GPIO_BASE)
/** Array initializer of HSIO_LPCG_GPIO peripheral base addresses */
#define HSIO_LPCG_GPIO_BASE_ADDRS                { HSIO__LPCG_GPIO_BASE }
/** Array initializer of HSIO_LPCG_GPIO peripheral base pointers */
#define HSIO_LPCG_GPIO_BASE_PTRS                 { HSIO__LPCG_GPIO }

/*!
 * @}
 */ /* end of group HSIO_LPCG_GPIO_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_MISC_REGS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_MISC_REGS_Peripheral_Access_Layer HSIO_LPCG_MISC_REGS Peripheral Access Layer
 * @{
 */

/** HSIO_LPCG_MISC_REGS - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MISC_CRR5_0;                  /**< na, offset: 0x0 */
} HSIO_LPCG_MISC_REGS_Type;

/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_MISC_REGS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_MISC_REGS_Register_Masks HSIO_LPCG_MISC_REGS Register Masks
 * @{
 */

/*! @name LPCG_MISC_CRR5_0 - na */
/*! @{ */
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15_MASK (0xFFFFU)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15_SHIFT (0U)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15_SHIFT)) & HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_0_15_MASK)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN_MASK (0x10000U)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN_SHIFT (16U)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN_SHIFT)) & HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_HWEN_MASK)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN_MASK (0x20000U)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN_SHIFT (17U)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN_SHIFT)) & HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_SWEN_MASK)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18_MASK (0x40000U)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18_SHIFT (18U)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18_SHIFT)) & HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_18_18_MASK)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP_MASK (0x80000U)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP_SHIFT (19U)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP_SHIFT)) & HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_hsio_misc_regs_ipg_clk_STOP_MASK)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31_MASK (0xFFF00000U)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31_SHIFT (20U)
#define HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31_SHIFT)) & HSIO_LPCG_MISC_REGS_LPCG_MISC_CRR5_0_LPCG_MISC_CRR5_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group HSIO_LPCG_MISC_REGS_Register_Masks */


/* HSIO_LPCG_MISC_REGS - Peripheral instance base addresses */
/** Peripheral HSIO__LPCG_MISC_REGS base address */
#define HSIO__LPCG_MISC_REGS_BASE                (0x5F0F0000u)
/** Peripheral HSIO__LPCG_MISC_REGS base pointer */
#define HSIO__LPCG_MISC_REGS                     ((HSIO_LPCG_MISC_REGS_Type *)HSIO__LPCG_MISC_REGS_BASE)
/** Array initializer of HSIO_LPCG_MISC_REGS peripheral base addresses */
#define HSIO_LPCG_MISC_REGS_BASE_ADDRS           { HSIO__LPCG_MISC_REGS_BASE }
/** Array initializer of HSIO_LPCG_MISC_REGS peripheral base pointers */
#define HSIO_LPCG_MISC_REGS_BASE_PTRS            { HSIO__LPCG_MISC_REGS }

/*!
 * @}
 */ /* end of group HSIO_LPCG_MISC_REGS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PCIEX1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PCIEX1_Peripheral_Access_Layer HSIO_LPCG_PCIEX1 Peripheral Access Layer
 * @{
 */

/** HSIO_LPCG_PCIEX1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PCIEX1_0;                     /**< na, offset: 0x0 */
} HSIO_LPCG_PCIEX1_Type;

/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PCIEX1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PCIEX1_Register_Masks HSIO_LPCG_PCIEX1 Register Masks
 * @{
 */

/*! @name LPCG_PCIEX1_0 - na */
/*! @{ */
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_16_MASK (0x1FFFFU)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_16_SHIFT (0U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_16_SHIFT)) & HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_0_16_MASK)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_mstr_axi_clk_SWEN_MASK (0x20000U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_mstr_axi_clk_SWEN_SHIFT (17U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_mstr_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_mstr_axi_clk_SWEN_SHIFT)) & HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_mstr_axi_clk_SWEN_MASK)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18_MASK (0x40000U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18_SHIFT (18U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18_SHIFT)) & HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_18_18_MASK)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_mstr_axi_clk_STOP_MASK (0x80000U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_mstr_axi_clk_STOP_SHIFT (19U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_mstr_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_mstr_axi_clk_STOP_SHIFT)) & HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_mstr_axi_clk_STOP_MASK)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_20_20_MASK (0x100000U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_20_20_SHIFT (20U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_20_20_SHIFT)) & HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_20_20_MASK)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_slv_axi_clk_SWEN_MASK (0x200000U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_slv_axi_clk_SWEN_SHIFT (21U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_slv_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_slv_axi_clk_SWEN_SHIFT)) & HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_slv_axi_clk_SWEN_MASK)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22_MASK (0x400000U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22_SHIFT (22U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22_SHIFT)) & HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_22_22_MASK)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_slv_axi_clk_STOP_MASK (0x800000U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_slv_axi_clk_STOP_SHIFT (23U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_slv_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_slv_axi_clk_STOP_SHIFT)) & HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_slv_axi_clk_STOP_MASK)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_24_24_MASK (0x1000000U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_24_24_SHIFT (24U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_24_24_SHIFT)) & HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_24_24_MASK)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_dbi_axi_clk_SWEN_MASK (0x2000000U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_dbi_axi_clk_SWEN_SHIFT (25U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_dbi_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_dbi_axi_clk_SWEN_SHIFT)) & HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_dbi_axi_clk_SWEN_MASK)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26_MASK (0x4000000U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26_SHIFT (26U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26_SHIFT)) & HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_26_26_MASK)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_dbi_axi_clk_STOP_MASK (0x8000000U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_dbi_axi_clk_STOP_SHIFT (27U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_dbi_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_dbi_axi_clk_STOP_SHIFT)) & HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_pcie_clk_rst_b_dbi_axi_clk_STOP_MASK)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31_MASK (0xF0000000U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31_SHIFT (28U)
#define HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31_SHIFT)) & HSIO_LPCG_PCIEX1_LPCG_PCIEX1_0_LPCG_PCIEX1_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group HSIO_LPCG_PCIEX1_Register_Masks */


/* HSIO_LPCG_PCIEX1 - Peripheral instance base addresses */
/** Peripheral HSIO__LPCG_PCIEX1 base address */
#define HSIO__LPCG_PCIEX1_BASE                   (0x5F060000u)
/** Peripheral HSIO__LPCG_PCIEX1 base pointer */
#define HSIO__LPCG_PCIEX1                        ((HSIO_LPCG_PCIEX1_Type *)HSIO__LPCG_PCIEX1_BASE)
/** Array initializer of HSIO_LPCG_PCIEX1 peripheral base addresses */
#define HSIO_LPCG_PCIEX1_BASE_ADDRS              { HSIO__LPCG_PCIEX1_BASE }
/** Array initializer of HSIO_LPCG_PCIEX1 peripheral base pointers */
#define HSIO_LPCG_PCIEX1_BASE_PTRS               { HSIO__LPCG_PCIEX1 }

/*!
 * @}
 */ /* end of group HSIO_LPCG_PCIEX1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PCIEX1_REGS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PCIEX1_REGS_Peripheral_Access_Layer HSIO_LPCG_PCIEX1_REGS Peripheral Access Layer
 * @{
 */

/** HSIO_LPCG_PCIEX1_REGS - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PCIEX1_CRR3_0;                /**< na, offset: 0x0 */
} HSIO_LPCG_PCIEX1_REGS_Type;

/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PCIEX1_REGS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PCIEX1_REGS_Register_Masks HSIO_LPCG_PCIEX1_REGS Register Masks
 * @{
 */

/*! @name LPCG_PCIEX1_CRR3_0 - na */
/*! @{ */
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15_MASK (0xFFFFU)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15_SHIFT (0U)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15_SHIFT)) & HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_0_15_MASK)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN_MASK (0x10000U)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN_SHIFT (16U)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN_SHIFT)) & HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_HWEN_MASK)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN_MASK (0x20000U)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN_SHIFT (17U)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN_SHIFT)) & HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_SWEN_MASK)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18_MASK (0x40000U)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18_SHIFT (18U)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18_SHIFT)) & HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_18_18_MASK)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP_MASK (0x80000U)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP_SHIFT (19U)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP_SHIFT)) & HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_hsio_pciex1_regs_ipg_clk_STOP_MASK)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31_MASK (0xFFF00000U)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31_SHIFT (20U)
#define HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31_SHIFT)) & HSIO_LPCG_PCIEX1_REGS_LPCG_PCIEX1_CRR3_0_LPCG_PCIEX1_CRR3_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group HSIO_LPCG_PCIEX1_REGS_Register_Masks */


/* HSIO_LPCG_PCIEX1_REGS - Peripheral instance base addresses */
/** Peripheral HSIO__LPCG_PCIEX1_REGS base address */
#define HSIO__LPCG_PCIEX1_REGS_BASE              (0x5F0D0000u)
/** Peripheral HSIO__LPCG_PCIEX1_REGS base pointer */
#define HSIO__LPCG_PCIEX1_REGS                   ((HSIO_LPCG_PCIEX1_REGS_Type *)HSIO__LPCG_PCIEX1_REGS_BASE)
/** Array initializer of HSIO_LPCG_PCIEX1_REGS peripheral base addresses */
#define HSIO_LPCG_PCIEX1_REGS_BASE_ADDRS         { HSIO__LPCG_PCIEX1_REGS_BASE }
/** Array initializer of HSIO_LPCG_PCIEX1_REGS peripheral base pointers */
#define HSIO_LPCG_PCIEX1_REGS_BASE_PTRS          { HSIO__LPCG_PCIEX1_REGS }

/*!
 * @}
 */ /* end of group HSIO_LPCG_PCIEX1_REGS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PCIEX2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PCIEX2_Peripheral_Access_Layer HSIO_LPCG_PCIEX2 Peripheral Access Layer
 * @{
 */

/** HSIO_LPCG_PCIEX2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PCIEX2_0;                     /**< na, offset: 0x0 */
} HSIO_LPCG_PCIEX2_Type;

/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PCIEX2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PCIEX2_Register_Masks HSIO_LPCG_PCIEX2 Register Masks
 * @{
 */

/*! @name LPCG_PCIEX2_0 - na */
/*! @{ */
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_0_16_MASK (0x1FFFFU)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_0_16_SHIFT (0U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_0_16_SHIFT)) & HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_0_16_MASK)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_mstr_axi_clk_SWEN_MASK (0x20000U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_mstr_axi_clk_SWEN_SHIFT (17U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_mstr_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_mstr_axi_clk_SWEN_SHIFT)) & HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_mstr_axi_clk_SWEN_MASK)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_18_18_MASK (0x40000U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_18_18_SHIFT (18U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_18_18_SHIFT)) & HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_18_18_MASK)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_mstr_axi_clk_STOP_MASK (0x80000U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_mstr_axi_clk_STOP_SHIFT (19U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_mstr_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_mstr_axi_clk_STOP_SHIFT)) & HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_mstr_axi_clk_STOP_MASK)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_20_20_MASK (0x100000U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_20_20_SHIFT (20U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_20_20_SHIFT)) & HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_20_20_MASK)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_slv_axi_clk_SWEN_MASK (0x200000U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_slv_axi_clk_SWEN_SHIFT (21U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_slv_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_slv_axi_clk_SWEN_SHIFT)) & HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_slv_axi_clk_SWEN_MASK)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_22_22_MASK (0x400000U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_22_22_SHIFT (22U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_22_22_SHIFT)) & HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_22_22_MASK)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_slv_axi_clk_STOP_MASK (0x800000U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_slv_axi_clk_STOP_SHIFT (23U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_slv_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_slv_axi_clk_STOP_SHIFT)) & HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_slv_axi_clk_STOP_MASK)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_24_24_MASK (0x1000000U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_24_24_SHIFT (24U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_24_24_SHIFT)) & HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_24_24_MASK)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_dbi_axi_clk_SWEN_MASK (0x2000000U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_dbi_axi_clk_SWEN_SHIFT (25U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_dbi_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_dbi_axi_clk_SWEN_SHIFT)) & HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_dbi_axi_clk_SWEN_MASK)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_26_26_MASK (0x4000000U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_26_26_SHIFT (26U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_26_26_SHIFT)) & HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_26_26_MASK)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_dbi_axi_clk_STOP_MASK (0x8000000U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_dbi_axi_clk_STOP_SHIFT (27U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_dbi_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_dbi_axi_clk_STOP_SHIFT)) & HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_pcie_clk_rst_a_dbi_axi_clk_STOP_MASK)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_28_31_MASK (0xF0000000U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_28_31_SHIFT (28U)
#define HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_28_31_SHIFT)) & HSIO_LPCG_PCIEX2_LPCG_PCIEX2_0_LPCG_PCIEX2_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group HSIO_LPCG_PCIEX2_Register_Masks */


/* HSIO_LPCG_PCIEX2 - Peripheral instance base addresses */
/** Peripheral HSIO__LPCG_PCIEX2 base address */
#define HSIO__LPCG_PCIEX2_BASE                   (0x5F050000u)
/** Peripheral HSIO__LPCG_PCIEX2 base pointer */
#define HSIO__LPCG_PCIEX2                        ((HSIO_LPCG_PCIEX2_Type *)HSIO__LPCG_PCIEX2_BASE)
/** Array initializer of HSIO_LPCG_PCIEX2 peripheral base addresses */
#define HSIO_LPCG_PCIEX2_BASE_ADDRS              { HSIO__LPCG_PCIEX2_BASE }
/** Array initializer of HSIO_LPCG_PCIEX2 peripheral base pointers */
#define HSIO_LPCG_PCIEX2_BASE_PTRS               { HSIO__LPCG_PCIEX2 }

/*!
 * @}
 */ /* end of group HSIO_LPCG_PCIEX2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PCIEX2_REGS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PCIEX2_REGS_Peripheral_Access_Layer HSIO_LPCG_PCIEX2_REGS Peripheral Access Layer
 * @{
 */

/** HSIO_LPCG_PCIEX2_REGS - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PCIEX2_CRR2_0;                /**< na, offset: 0x0 */
} HSIO_LPCG_PCIEX2_REGS_Type;

/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PCIEX2_REGS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PCIEX2_REGS_Register_Masks HSIO_LPCG_PCIEX2_REGS Register Masks
 * @{
 */

/*! @name LPCG_PCIEX2_CRR2_0 - na */
/*! @{ */
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_0_15_MASK (0xFFFFU)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_0_15_SHIFT (0U)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_0_15_SHIFT)) & HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_0_15_MASK)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_HWEN_MASK (0x10000U)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_HWEN_SHIFT (16U)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_HWEN_SHIFT)) & HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_HWEN_MASK)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_SWEN_MASK (0x20000U)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_SWEN_SHIFT (17U)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_SWEN_SHIFT)) & HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_SWEN_MASK)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_18_18_MASK (0x40000U)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_18_18_SHIFT (18U)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_18_18_SHIFT)) & HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_18_18_MASK)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_STOP_MASK (0x80000U)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_STOP_SHIFT (19U)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_STOP_SHIFT)) & HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_hsio_pciex2_regs_ipg_clk_STOP_MASK)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_20_31_MASK (0xFFF00000U)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_20_31_SHIFT (20U)
#define HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_20_31_SHIFT)) & HSIO_LPCG_PCIEX2_REGS_LPCG_PCIEX2_CRR2_0_LPCG_PCIEX2_CRR2_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group HSIO_LPCG_PCIEX2_REGS_Register_Masks */


/* HSIO_LPCG_PCIEX2_REGS - Peripheral instance base addresses */
/** Peripheral HSIO__LPCG_PCIEX2_REGS base address */
#define HSIO__LPCG_PCIEX2_REGS_BASE              (0x5F0C0000u)
/** Peripheral HSIO__LPCG_PCIEX2_REGS base pointer */
#define HSIO__LPCG_PCIEX2_REGS                   ((HSIO_LPCG_PCIEX2_REGS_Type *)HSIO__LPCG_PCIEX2_REGS_BASE)
/** Array initializer of HSIO_LPCG_PCIEX2_REGS peripheral base addresses */
#define HSIO_LPCG_PCIEX2_REGS_BASE_ADDRS         { HSIO__LPCG_PCIEX2_REGS_BASE }
/** Array initializer of HSIO_LPCG_PCIEX2_REGS peripheral base pointers */
#define HSIO_LPCG_PCIEX2_REGS_BASE_PTRS          { HSIO__LPCG_PCIEX2_REGS }

/*!
 * @}
 */ /* end of group HSIO_LPCG_PCIEX2_REGS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PHYX1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PHYX1_Peripheral_Access_Layer HSIO_LPCG_PHYX1 Peripheral Access Layer
 * @{
 */

/** HSIO_LPCG_PHYX1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PHYX1_0;                      /**< na, offset: 0x0 */
} HSIO_LPCG_PHYX1_Type;

/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PHYX1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PHYX1_Register_Masks HSIO_LPCG_PHYX1 Register Masks
 * @{
 */

/*! @name LPCG_PHYX1_0 - na */
/*! @{ */
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_0_MASK (0x1U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_0_SHIFT (0U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_0_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_0_0_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_hsio_glue_phyx1_pclk_SWEN_MASK (0x2U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_hsio_glue_phyx1_pclk_SWEN_SHIFT (1U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_hsio_glue_phyx1_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_hsio_glue_phyx1_pclk_SWEN_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_hsio_glue_phyx1_pclk_SWEN_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_2_2_MASK (0x4U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_2_2_SHIFT (2U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_2_2_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_2_2_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_hsio_glue_phyx1_pclk_STOP_MASK (0x8U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_hsio_glue_phyx1_pclk_STOP_SHIFT (3U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_hsio_glue_phyx1_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_hsio_glue_phyx1_pclk_STOP_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_hsio_glue_phyx1_pclk_STOP_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_4_4_MASK (0x10U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_4_4_SHIFT (4U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_4_4_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_4_4_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_txclk_SWEN_MASK (0x20U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_txclk_SWEN_SHIFT (5U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_txclk_SWEN_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_txclk_SWEN_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_6_6_MASK (0x40U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_6_6_SHIFT (6U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_6_6_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_6_6_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_txclk_STOP_MASK (0x80U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_txclk_STOP_SHIFT (7U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_txclk_STOP_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_txclk_STOP_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_8_8_MASK (0x100U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_8_8_SHIFT (8U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_8_8_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_8_8_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_rxclk_SWEN_MASK (0x200U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_rxclk_SWEN_SHIFT (9U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_rxclk_SWEN_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_rxclk_SWEN_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_10_10_MASK (0x400U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_10_10_SHIFT (10U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_10_10_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_10_10_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_rxclk_STOP_MASK (0x800U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_rxclk_STOP_SHIFT (11U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_rxclk_STOP_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_sata_pcs_shim_epcs_rxclk_STOP_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_12_16_MASK (0x1F000U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_12_16_SHIFT (12U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_12_16_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_12_16_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN_MASK (0x20000U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN_SHIFT (17U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_SWEN_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18_MASK (0x40000U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18_SHIFT (18U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_18_18_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP_MASK (0x80000U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP_SHIFT (19U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_pcs_phy_x1_apb_pclk_0_STOP_MASK)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31_MASK (0xFFF00000U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31_SHIFT (20U)
#define HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31_SHIFT)) & HSIO_LPCG_PHYX1_LPCG_PHYX1_0_LPCG_PHYX1_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group HSIO_LPCG_PHYX1_Register_Masks */


/* HSIO_LPCG_PHYX1 - Peripheral instance base addresses */
/** Peripheral HSIO__LPCG_PHYX1 base address */
#define HSIO__LPCG_PHYX1_BASE                    (0x5F090000u)
/** Peripheral HSIO__LPCG_PHYX1 base pointer */
#define HSIO__LPCG_PHYX1                         ((HSIO_LPCG_PHYX1_Type *)HSIO__LPCG_PHYX1_BASE)
/** Array initializer of HSIO_LPCG_PHYX1 peripheral base addresses */
#define HSIO_LPCG_PHYX1_BASE_ADDRS               { HSIO__LPCG_PHYX1_BASE }
/** Array initializer of HSIO_LPCG_PHYX1 peripheral base pointers */
#define HSIO_LPCG_PHYX1_BASE_PTRS                { HSIO__LPCG_PHYX1 }

/*!
 * @}
 */ /* end of group HSIO_LPCG_PHYX1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PHYX1_REGS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PHYX1_REGS_Peripheral_Access_Layer HSIO_LPCG_PHYX1_REGS Peripheral Access Layer
 * @{
 */

/** HSIO_LPCG_PHYX1_REGS - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PHYX1_CRR1_0;                 /**< na, offset: 0x0 */
} HSIO_LPCG_PHYX1_REGS_Type;

/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PHYX1_REGS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PHYX1_REGS_Register_Masks HSIO_LPCG_PHYX1_REGS Register Masks
 * @{
 */

/*! @name LPCG_PHYX1_CRR1_0 - na */
/*! @{ */
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15_MASK (0xFFFFU)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15_SHIFT (0U)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15_SHIFT)) & HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_0_15_MASK)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN_MASK (0x10000U)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN_SHIFT (16U)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN_SHIFT)) & HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_HWEN_MASK)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN_MASK (0x20000U)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN_SHIFT (17U)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN_SHIFT)) & HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_SWEN_MASK)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18_MASK (0x40000U)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18_SHIFT (18U)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18_SHIFT)) & HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_18_18_MASK)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP_MASK (0x80000U)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP_SHIFT (19U)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP_SHIFT)) & HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_hsio_phyx1_regs_ipg_clk_STOP_MASK)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31_MASK (0xFFF00000U)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31_SHIFT (20U)
#define HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31_SHIFT)) & HSIO_LPCG_PHYX1_REGS_LPCG_PHYX1_CRR1_0_LPCG_PHYX1_CRR1_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group HSIO_LPCG_PHYX1_REGS_Register_Masks */


/* HSIO_LPCG_PHYX1_REGS - Peripheral instance base addresses */
/** Peripheral HSIO__LPCG_PHYX1_REGS base address */
#define HSIO__LPCG_PHYX1_REGS_BASE               (0x5F0B0000u)
/** Peripheral HSIO__LPCG_PHYX1_REGS base pointer */
#define HSIO__LPCG_PHYX1_REGS                    ((HSIO_LPCG_PHYX1_REGS_Type *)HSIO__LPCG_PHYX1_REGS_BASE)
/** Array initializer of HSIO_LPCG_PHYX1_REGS peripheral base addresses */
#define HSIO_LPCG_PHYX1_REGS_BASE_ADDRS          { HSIO__LPCG_PHYX1_REGS_BASE }
/** Array initializer of HSIO_LPCG_PHYX1_REGS peripheral base pointers */
#define HSIO_LPCG_PHYX1_REGS_BASE_PTRS           { HSIO__LPCG_PHYX1_REGS }

/*!
 * @}
 */ /* end of group HSIO_LPCG_PHYX1_REGS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PHYX2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PHYX2_Peripheral_Access_Layer HSIO_LPCG_PHYX2 Peripheral Access Layer
 * @{
 */

/** HSIO_LPCG_PHYX2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PHYX2_0;                      /**< na, offset: 0x0 */
} HSIO_LPCG_PHYX2_Type;

/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PHYX2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PHYX2_Register_Masks HSIO_LPCG_PHYX2 Register Masks
 * @{
 */

/*! @name LPCG_PHYX2_0 - na */
/*! @{ */
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_0_0_MASK (0x1U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_0_0_SHIFT (0U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_0_0_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_0_0_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_0_SWEN_MASK (0x2U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_0_SWEN_SHIFT (1U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_0_SWEN_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_0_SWEN_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_2_2_MASK (0x4U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_2_2_SHIFT (2U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_2_2_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_2_2_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_0_STOP_MASK (0x8U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_0_STOP_SHIFT (3U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_0_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_0_STOP_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_0_STOP_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_4_4_MASK (0x10U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_4_4_SHIFT (4U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_4_4_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_4_4_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_1_SWEN_MASK (0x20U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_1_SWEN_SHIFT (5U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_1_SWEN_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_1_SWEN_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_6_6_MASK (0x40U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_6_6_SHIFT (6U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_6_6_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_6_6_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_1_STOP_MASK (0x80U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_1_STOP_SHIFT (7U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_1_STOP_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_hsio_glue_phyx2_pclk_1_STOP_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_8_16_MASK (0x1FF00U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_8_16_SHIFT (8U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_8_16_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_8_16_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_0_SWEN_MASK (0x20000U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_0_SWEN_SHIFT (17U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_0_SWEN_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_0_SWEN_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_18_18_MASK (0x40000U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_18_18_SHIFT (18U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_18_18_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_18_18_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_0_STOP_MASK (0x80000U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_0_STOP_SHIFT (19U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_0_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_0_STOP_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_0_STOP_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_20_20_MASK (0x100000U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_20_20_SHIFT (20U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_20_20_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_20_20_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_1_SWEN_MASK (0x200000U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_1_SWEN_SHIFT (21U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_1_SWEN_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_1_SWEN_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_22_22_MASK (0x400000U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_22_22_SHIFT (22U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_22_22_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_22_22_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_1_STOP_MASK (0x800000U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_1_STOP_SHIFT (23U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_1_STOP_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_pcs_phy_x2_apb_pclk_1_STOP_MASK)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_24_31_MASK (0xFF000000U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_24_31_SHIFT (24U)
#define HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_24_31_SHIFT)) & HSIO_LPCG_PHYX2_LPCG_PHYX2_0_LPCG_PHYX2_0_reserved_24_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group HSIO_LPCG_PHYX2_Register_Masks */


/* HSIO_LPCG_PHYX2 - Peripheral instance base addresses */
/** Peripheral HSIO__LPCG_PHYX2 base address */
#define HSIO__LPCG_PHYX2_BASE                    (0x5F080000u)
/** Peripheral HSIO__LPCG_PHYX2 base pointer */
#define HSIO__LPCG_PHYX2                         ((HSIO_LPCG_PHYX2_Type *)HSIO__LPCG_PHYX2_BASE)
/** Array initializer of HSIO_LPCG_PHYX2 peripheral base addresses */
#define HSIO_LPCG_PHYX2_BASE_ADDRS               { HSIO__LPCG_PHYX2_BASE }
/** Array initializer of HSIO_LPCG_PHYX2 peripheral base pointers */
#define HSIO_LPCG_PHYX2_BASE_PTRS                { HSIO__LPCG_PHYX2 }

/*!
 * @}
 */ /* end of group HSIO_LPCG_PHYX2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PHYX2_REGS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PHYX2_REGS_Peripheral_Access_Layer HSIO_LPCG_PHYX2_REGS Peripheral Access Layer
 * @{
 */

/** HSIO_LPCG_PHYX2_REGS - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PHYX2_CRR0_0;                 /**< na, offset: 0x0 */
} HSIO_LPCG_PHYX2_REGS_Type;

/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_PHYX2_REGS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_PHYX2_REGS_Register_Masks HSIO_LPCG_PHYX2_REGS Register Masks
 * @{
 */

/*! @name LPCG_PHYX2_CRR0_0 - na */
/*! @{ */
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_0_15_MASK (0xFFFFU)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_0_15_SHIFT (0U)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_0_15_SHIFT)) & HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_0_15_MASK)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_HWEN_MASK (0x10000U)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_HWEN_SHIFT (16U)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_HWEN_SHIFT)) & HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_HWEN_MASK)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_SWEN_MASK (0x20000U)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_SWEN_SHIFT (17U)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_SWEN_SHIFT)) & HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_SWEN_MASK)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_18_18_MASK (0x40000U)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_18_18_SHIFT (18U)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_18_18_SHIFT)) & HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_18_18_MASK)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_STOP_MASK (0x80000U)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_STOP_SHIFT (19U)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_STOP_SHIFT)) & HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_hsio_phyx2_regs_ipg_clk_STOP_MASK)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_20_31_MASK (0xFFF00000U)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_20_31_SHIFT (20U)
#define HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_20_31_SHIFT)) & HSIO_LPCG_PHYX2_REGS_LPCG_PHYX2_CRR0_0_LPCG_PHYX2_CRR0_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group HSIO_LPCG_PHYX2_REGS_Register_Masks */


/* HSIO_LPCG_PHYX2_REGS - Peripheral instance base addresses */
/** Peripheral HSIO__LPCG_PHYX2_REGS base address */
#define HSIO__LPCG_PHYX2_REGS_BASE               (0x5F0A0000u)
/** Peripheral HSIO__LPCG_PHYX2_REGS base pointer */
#define HSIO__LPCG_PHYX2_REGS                    ((HSIO_LPCG_PHYX2_REGS_Type *)HSIO__LPCG_PHYX2_REGS_BASE)
/** Array initializer of HSIO_LPCG_PHYX2_REGS peripheral base addresses */
#define HSIO_LPCG_PHYX2_REGS_BASE_ADDRS          { HSIO__LPCG_PHYX2_REGS_BASE }
/** Array initializer of HSIO_LPCG_PHYX2_REGS peripheral base pointers */
#define HSIO_LPCG_PHYX2_REGS_BASE_PTRS           { HSIO__LPCG_PHYX2_REGS }

/*!
 * @}
 */ /* end of group HSIO_LPCG_PHYX2_REGS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_SATA Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_SATA_Peripheral_Access_Layer HSIO_LPCG_SATA Peripheral Access Layer
 * @{
 */

/** HSIO_LPCG_SATA - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_SATA_0;                       /**< na, offset: 0x0 */
} HSIO_LPCG_SATA_Type;

/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_SATA Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_SATA_Register_Masks HSIO_LPCG_SATA Register Masks
 * @{
 */

/*! @name LPCG_SATA_0 - na */
/*! @{ */
#define HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_0_16_MASK (0x1FFFFU)
#define HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_0_16_SHIFT (0U)
#define HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_0_16_SHIFT)) & HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_0_16_MASK)
#define HSIO_LPCG_SATA_LPCG_SATA_0_sata_CLK_SWEN_MASK (0x20000U)
#define HSIO_LPCG_SATA_LPCG_SATA_0_sata_CLK_SWEN_SHIFT (17U)
#define HSIO_LPCG_SATA_LPCG_SATA_0_sata_CLK_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_SATA_LPCG_SATA_0_sata_CLK_SWEN_SHIFT)) & HSIO_LPCG_SATA_LPCG_SATA_0_sata_CLK_SWEN_MASK)
#define HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_18_18_MASK (0x40000U)
#define HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_18_18_SHIFT (18U)
#define HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_18_18_SHIFT)) & HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_18_18_MASK)
#define HSIO_LPCG_SATA_LPCG_SATA_0_sata_CLK_STOP_MASK (0x80000U)
#define HSIO_LPCG_SATA_LPCG_SATA_0_sata_CLK_STOP_SHIFT (19U)
#define HSIO_LPCG_SATA_LPCG_SATA_0_sata_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_SATA_LPCG_SATA_0_sata_CLK_STOP_SHIFT)) & HSIO_LPCG_SATA_LPCG_SATA_0_sata_CLK_STOP_MASK)
#define HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_20_31_MASK (0xFFF00000U)
#define HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_20_31_SHIFT (20U)
#define HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_20_31_SHIFT)) & HSIO_LPCG_SATA_LPCG_SATA_0_LPCG_SATA_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group HSIO_LPCG_SATA_Register_Masks */


/* HSIO_LPCG_SATA - Peripheral instance base addresses */
/** Peripheral HSIO__LPCG_SATA base address */
#define HSIO__LPCG_SATA_BASE                     (0x5F070000u)
/** Peripheral HSIO__LPCG_SATA base pointer */
#define HSIO__LPCG_SATA                          ((HSIO_LPCG_SATA_Type *)HSIO__LPCG_SATA_BASE)
/** Array initializer of HSIO_LPCG_SATA peripheral base addresses */
#define HSIO_LPCG_SATA_BASE_ADDRS                { HSIO__LPCG_SATA_BASE }
/** Array initializer of HSIO_LPCG_SATA peripheral base pointers */
#define HSIO_LPCG_SATA_BASE_PTRS                 { HSIO__LPCG_SATA }

/*!
 * @}
 */ /* end of group HSIO_LPCG_SATA_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_SATA_REGS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_SATA_REGS_Peripheral_Access_Layer HSIO_LPCG_SATA_REGS Peripheral Access Layer
 * @{
 */

/** HSIO_LPCG_SATA_REGS - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_SATA_CRR4_0;                  /**< na, offset: 0x0 */
} HSIO_LPCG_SATA_REGS_Type;

/* ----------------------------------------------------------------------------
   -- HSIO_LPCG_SATA_REGS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSIO_LPCG_SATA_REGS_Register_Masks HSIO_LPCG_SATA_REGS Register Masks
 * @{
 */

/*! @name LPCG_SATA_CRR4_0 - na */
/*! @{ */
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_0_15_MASK (0xFFFFU)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_0_15_SHIFT (0U)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_0_15_SHIFT)) & HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_0_15_MASK)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_HWEN_MASK (0x10000U)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_HWEN_SHIFT (16U)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_HWEN_SHIFT)) & HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_HWEN_MASK)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_SWEN_MASK (0x20000U)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_SWEN_SHIFT (17U)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_SWEN_SHIFT)) & HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_SWEN_MASK)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_18_18_MASK (0x40000U)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_18_18_SHIFT (18U)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_18_18_SHIFT)) & HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_18_18_MASK)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_STOP_MASK (0x80000U)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_STOP_SHIFT (19U)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_STOP_SHIFT)) & HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_hsio_sata_regs_ipg_clk_STOP_MASK)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_20_31_MASK (0xFFF00000U)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_20_31_SHIFT (20U)
#define HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_20_31_SHIFT)) & HSIO_LPCG_SATA_REGS_LPCG_SATA_CRR4_0_LPCG_SATA_CRR4_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group HSIO_LPCG_SATA_REGS_Register_Masks */


/* HSIO_LPCG_SATA_REGS - Peripheral instance base addresses */
/** Peripheral HSIO__LPCG_SATA_REGS base address */
#define HSIO__LPCG_SATA_REGS_BASE                (0x5F0E0000u)
/** Peripheral HSIO__LPCG_SATA_REGS base pointer */
#define HSIO__LPCG_SATA_REGS                     ((HSIO_LPCG_SATA_REGS_Type *)HSIO__LPCG_SATA_REGS_BASE)
/** Array initializer of HSIO_LPCG_SATA_REGS peripheral base addresses */
#define HSIO_LPCG_SATA_REGS_BASE_ADDRS           { HSIO__LPCG_SATA_REGS_BASE }
/** Array initializer of HSIO_LPCG_SATA_REGS peripheral base pointers */
#define HSIO_LPCG_SATA_REGS_BASE_PTRS            { HSIO__LPCG_SATA_REGS }

/*!
 * @}
 */ /* end of group HSIO_LPCG_SATA_REGS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- I2S Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
 * @{
 */

/** I2S - Register Layout Typedef */
typedef struct {
  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
  __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
       uint8_t RESERVED_0[8];
  __O  uint32_t TDR[4];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
       uint8_t RESERVED_1[16];
  __I  uint32_t TFR[4];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
       uint8_t RESERVED_2[16];
  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
       uint8_t RESERVED_3[28];
  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
  __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x84 */
  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
       uint8_t RESERVED_4[8];
  __I  uint32_t RDR[4];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
       uint8_t RESERVED_5[16];
  __I  uint32_t RFR[4];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
       uint8_t RESERVED_6[16];
  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
} I2S_Type;

/* ----------------------------------------------------------------------------
   -- I2S Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I2S_Register_Masks I2S Register Masks
 * @{
 */

/*! @name TCSR - SAI Transmit Control Register */
/*! @{ */
#define I2S_TCSR_FRDE_MASK                       (0x1U)
#define I2S_TCSR_FRDE_SHIFT                      (0U)
/*! FRDE - FIFO Request DMA Enable
 *  0b0..Disables the DMA request.
 *  0b1..Enables the DMA request.
 */
#define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
#define I2S_TCSR_FWDE_MASK                       (0x2U)
#define I2S_TCSR_FWDE_SHIFT                      (1U)
/*! FWDE - FIFO Warning DMA Enable
 *  0b0..Disables the DMA request.
 *  0b1..Enables the DMA request.
 */
#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
#define I2S_TCSR_FRIE_MASK                       (0x100U)
#define I2S_TCSR_FRIE_SHIFT                      (8U)
/*! FRIE - FIFO Request Interrupt Enable
 *  0b0..Disables the interrupt.
 *  0b1..Enables the interrupt.
 */
#define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
#define I2S_TCSR_FWIE_MASK                       (0x200U)
#define I2S_TCSR_FWIE_SHIFT                      (9U)
/*! FWIE - FIFO Warning Interrupt Enable
 *  0b0..Disables the interrupt.
 *  0b1..Enables the interrupt.
 */
#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
#define I2S_TCSR_FEIE_MASK                       (0x400U)
#define I2S_TCSR_FEIE_SHIFT                      (10U)
/*! FEIE - FIFO Error Interrupt Enable
 *  0b0..Disables the interrupt.
 *  0b1..Enables the interrupt.
 */
#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
#define I2S_TCSR_SEIE_MASK                       (0x800U)
#define I2S_TCSR_SEIE_SHIFT                      (11U)
/*! SEIE - Sync Error Interrupt Enable
 *  0b0..Disables interrupt.
 *  0b1..Enables interrupt.
 */
#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
#define I2S_TCSR_WSIE_MASK                       (0x1000U)
#define I2S_TCSR_WSIE_SHIFT                      (12U)
/*! WSIE - Word Start Interrupt Enable
 *  0b0..Disables interrupt.
 *  0b1..Enables interrupt.
 */
#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
#define I2S_TCSR_FRF_MASK                        (0x10000U)
#define I2S_TCSR_FRF_SHIFT                       (16U)
/*! FRF - FIFO Request Flag
 *  0b0..Transmit FIFO watermark has not been reached.
 *  0b1..Transmit FIFO watermark has been reached.
 */
#define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
#define I2S_TCSR_FWF_MASK                        (0x20000U)
#define I2S_TCSR_FWF_SHIFT                       (17U)
/*! FWF - FIFO Warning Flag
 *  0b0..No enabled transmit FIFO is empty.
 *  0b1..Enabled transmit FIFO is empty.
 */
#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
#define I2S_TCSR_FEF_MASK                        (0x40000U)
#define I2S_TCSR_FEF_SHIFT                       (18U)
/*! FEF - FIFO Error Flag
 *  0b0..Transmit underrun not detected.
 *  0b1..Transmit underrun detected.
 */
#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
#define I2S_TCSR_SEF_MASK                        (0x80000U)
#define I2S_TCSR_SEF_SHIFT                       (19U)
/*! SEF - Sync Error Flag
 *  0b0..Sync error not detected.
 *  0b1..Frame sync error detected.
 */
#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
#define I2S_TCSR_WSF_MASK                        (0x100000U)
#define I2S_TCSR_WSF_SHIFT                       (20U)
/*! WSF - Word Start Flag
 *  0b0..Start of word not detected.
 *  0b1..Start of word detected.
 */
#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
#define I2S_TCSR_SR_MASK                         (0x1000000U)
#define I2S_TCSR_SR_SHIFT                        (24U)
/*! SR - Software Reset
 *  0b0..No effect.
 *  0b1..Software reset.
 */
#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
#define I2S_TCSR_FR_MASK                         (0x2000000U)
#define I2S_TCSR_FR_SHIFT                        (25U)
/*! FR - FIFO Reset
 *  0b0..No effect.
 *  0b1..FIFO reset.
 */
#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
#define I2S_TCSR_BCE_MASK                        (0x10000000U)
#define I2S_TCSR_BCE_SHIFT                       (28U)
/*! BCE - Bit Clock Enable
 *  0b0..Transmit bit clock is disabled.
 *  0b1..Transmit bit clock is enabled.
 */
#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
#define I2S_TCSR_DBGE_MASK                       (0x20000000U)
#define I2S_TCSR_DBGE_SHIFT                      (29U)
/*! DBGE - Debug Enable
 *  0b0..Transmitter is disabled in Debug mode, after completing the current frame.
 *  0b1..Transmitter is enabled in Debug mode.
 */
#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
#define I2S_TCSR_STOPE_MASK                      (0x40000000U)
#define I2S_TCSR_STOPE_SHIFT                     (30U)
/*! STOPE - Stop Enable
 *  0b0..Transmitter disabled in Stop mode.
 *  0b1..Transmitter enabled in Stop mode.
 */
#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
#define I2S_TCSR_TE_MASK                         (0x80000000U)
#define I2S_TCSR_TE_SHIFT                        (31U)
/*! TE - Transmitter Enable
 *  0b0..Transmitter is disabled.
 *  0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
 */
#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
/*! @} */

/*! @name TCR1 - SAI Transmit Configuration 1 Register */
/*! @{ */
#define I2S_TCR1_TFW_MASK                        (0x3FU)
#define I2S_TCR1_TFW_SHIFT                       (0U)
#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
/*! @} */

/*! @name TCR2 - SAI Transmit Configuration 2 Register */
/*! @{ */
#define I2S_TCR2_DIV_MASK                        (0xFFU)
#define I2S_TCR2_DIV_SHIFT                       (0U)
#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
#define I2S_TCR2_BCD_MASK                        (0x1000000U)
#define I2S_TCR2_BCD_SHIFT                       (24U)
/*! BCD - Bit Clock Direction
 *  0b0..Bit clock is generated externally in Slave mode.
 *  0b1..Bit clock is generated internally in Master mode.
 */
#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
#define I2S_TCR2_BCP_MASK                        (0x2000000U)
#define I2S_TCR2_BCP_SHIFT                       (25U)
/*! BCP - Bit Clock Polarity
 *  0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
 *  0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
 */
#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
#define I2S_TCR2_MSEL_MASK                       (0xC000000U)
#define I2S_TCR2_MSEL_SHIFT                      (26U)
/*! MSEL - MCLK Select
 *  0b00..Bus Clock selected.
 *  0b01..Master Clock (MCLK) 1 option selected.
 *  0b10..Master Clock (MCLK) 2 option selected.
 *  0b11..Master Clock (MCLK) 3 option selected.
 */
#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
#define I2S_TCR2_BCI_MASK                        (0x10000000U)
#define I2S_TCR2_BCI_SHIFT                       (28U)
/*! BCI - Bit Clock Input
 *  0b0..No effect.
 *  0b1..Internal logic is clocked as if bit clock was externally generated.
 */
#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
#define I2S_TCR2_BCS_MASK                        (0x20000000U)
#define I2S_TCR2_BCS_SHIFT                       (29U)
/*! BCS - Bit Clock Swap
 *  0b0..Use the normal bit clock source.
 *  0b1..Swap the bit clock source.
 */
#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
#define I2S_TCR2_SYNC_MASK                       (0xC0000000U)
#define I2S_TCR2_SYNC_SHIFT                      (30U)
/*! SYNC - Synchronous Mode
 *  0b00..Asynchronous mode.
 *  0b01..Synchronous with receiver.
 *  0b10..Synchronous with another SAI transmitter.
 *  0b11..Synchronous with another SAI receiver.
 */
#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
/*! @} */

/*! @name TCR3 - SAI Transmit Configuration 3 Register */
/*! @{ */
#define I2S_TCR3_WDFL_MASK                       (0x1FU)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define I2S_TCR3_WDFL_SHIFT                      (0U)
#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define I2S_TCR3_TCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define I2S_TCR3_TCE_SHIFT                       (16U)
#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define I2S_TCR3_CFR_MASK                        (0xF000000U)
#define I2S_TCR3_CFR_SHIFT                       (24U)
#define I2S_TCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
/*! @} */

/*! @name TCR4 - SAI Transmit Configuration 4 Register */
/*! @{ */
#define I2S_TCR4_FSD_MASK                        (0x1U)
#define I2S_TCR4_FSD_SHIFT                       (0U)
/*! FSD - Frame Sync Direction
 *  0b0..Frame sync is generated externally in Slave mode.
 *  0b1..Frame sync is generated internally in Master mode.
 */
#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
#define I2S_TCR4_FSP_MASK                        (0x2U)
#define I2S_TCR4_FSP_SHIFT                       (1U)
/*! FSP - Frame Sync Polarity
 *  0b0..Frame sync is active high.
 *  0b1..Frame sync is active low.
 */
#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
#define I2S_TCR4_ONDEM_MASK                      (0x4U)
#define I2S_TCR4_ONDEM_SHIFT                     (2U)
/*! ONDEM - On Demand Mode
 *  0b0..Internal frame sync is generated continuously.
 *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
 */
#define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
#define I2S_TCR4_FSE_MASK                        (0x8U)
#define I2S_TCR4_FSE_SHIFT                       (3U)
/*! FSE - Frame Sync Early
 *  0b0..Frame sync asserts with the first bit of the frame.
 *  0b1..Frame sync asserts one bit before the first bit of the frame.
 */
#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
#define I2S_TCR4_MF_MASK                         (0x10U)
#define I2S_TCR4_MF_SHIFT                        (4U)
/*! MF - MSB First
 *  0b0..LSB is transmitted first.
 *  0b1..MSB is transmitted first.
 */
#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
#define I2S_TCR4_SYWD_MASK                       (0x1F00U)
#define I2S_TCR4_SYWD_SHIFT                      (8U)
#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
#define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define I2S_TCR4_FRSZ_SHIFT                      (16U)
#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define I2S_TCR4_FPACK_MASK                      (0x3000000U)
#define I2S_TCR4_FPACK_SHIFT                     (24U)
/*! FPACK - FIFO Packing Mode
 *  0b00..FIFO packing is disabled
 *  0b01..Reserved
 *  0b10..8-bit FIFO packing is enabled
 *  0b11..16-bit FIFO packing is enabled
 */
#define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
#define I2S_TCR4_FCOMB_MASK                      (0xC000000U)
#define I2S_TCR4_FCOMB_SHIFT                     (26U)
/*! FCOMB - FIFO Combine Mode
 *  0b00..FIFO combine mode disabled.
 *  0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
 *  0b10..FIFO combine mode enabled on FIFO writes (by software).
 *  0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
 */
#define I2S_TCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
#define I2S_TCR4_FCONT_MASK                      (0x10000000U)
#define I2S_TCR4_FCONT_SHIFT                     (28U)
/*! FCONT - FIFO Continue on Error
 *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
 *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
 */
#define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
/*! @} */

/*! @name TCR5 - SAI Transmit Configuration 5 Register */
/*! @{ */
#define I2S_TCR5_FBT_MASK                        (0x1F00U)
#define I2S_TCR5_FBT_SHIFT                       (8U)
#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
#define I2S_TCR5_W0W_MASK                        (0x1F0000U)
#define I2S_TCR5_W0W_SHIFT                       (16U)
#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
#define I2S_TCR5_WNW_MASK                        (0x1F000000U)
#define I2S_TCR5_WNW_SHIFT                       (24U)
#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
/*! @} */

/*! @name TDR - SAI Transmit Data Register */
/*! @{ */
#define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
#define I2S_TDR_TDR_SHIFT                        (0U)
#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
/*! @} */

/* The count of I2S_TDR */
#define I2S_TDR_COUNT                            (4U)

/*! @name TFR - SAI Transmit FIFO Register */
/*! @{ */
#define I2S_TFR_RFP_MASK                         (0x7FU)
#define I2S_TFR_RFP_SHIFT                        (0U)
#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
#define I2S_TFR_WFP_MASK                         (0x7F0000U)
#define I2S_TFR_WFP_SHIFT                        (16U)
#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
#define I2S_TFR_WCP_MASK                         (0x80000000U)
#define I2S_TFR_WCP_SHIFT                        (31U)
/*! WCP - Write Channel Pointer
 *  0b0..No effect.
 *  0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
 */
#define I2S_TFR_WCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
/*! @} */

/* The count of I2S_TFR */
#define I2S_TFR_COUNT                            (4U)

/*! @name TMR - SAI Transmit Mask Register */
/*! @{ */
#define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)  /* Merged from fields with different position or width, of widths (8, 32), largest definition used */
#define I2S_TMR_TWM_SHIFT                        (0U)
/*! TWM - Transmit Word Mask
 *  0b00000000000000000000000000000000..Word N is enabled.
 *  0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated when masked.
 */
#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)  /* Merged from fields with different position or width, of widths (8, 32), largest definition used */
/*! @} */

/*! @name RCSR - SAI Receive Control Register */
/*! @{ */
#define I2S_RCSR_FRDE_MASK                       (0x1U)
#define I2S_RCSR_FRDE_SHIFT                      (0U)
/*! FRDE - FIFO Request DMA Enable
 *  0b0..Disables the DMA request.
 *  0b1..Enables the DMA request.
 */
#define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
#define I2S_RCSR_FWDE_MASK                       (0x2U)
#define I2S_RCSR_FWDE_SHIFT                      (1U)
/*! FWDE - FIFO Warning DMA Enable
 *  0b0..Disables the DMA request.
 *  0b1..Enables the DMA request.
 */
#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
#define I2S_RCSR_FRIE_MASK                       (0x100U)
#define I2S_RCSR_FRIE_SHIFT                      (8U)
/*! FRIE - FIFO Request Interrupt Enable
 *  0b0..Disables the interrupt.
 *  0b1..Enables the interrupt.
 */
#define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
#define I2S_RCSR_FWIE_MASK                       (0x200U)
#define I2S_RCSR_FWIE_SHIFT                      (9U)
/*! FWIE - FIFO Warning Interrupt Enable
 *  0b0..Disables the interrupt.
 *  0b1..Enables the interrupt.
 */
#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
#define I2S_RCSR_FEIE_MASK                       (0x400U)
#define I2S_RCSR_FEIE_SHIFT                      (10U)
/*! FEIE - FIFO Error Interrupt Enable
 *  0b0..Disables the interrupt.
 *  0b1..Enables the interrupt.
 */
#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
#define I2S_RCSR_SEIE_MASK                       (0x800U)
#define I2S_RCSR_SEIE_SHIFT                      (11U)
/*! SEIE - Sync Error Interrupt Enable
 *  0b0..Disables interrupt.
 *  0b1..Enables interrupt.
 */
#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
#define I2S_RCSR_WSIE_MASK                       (0x1000U)
#define I2S_RCSR_WSIE_SHIFT                      (12U)
/*! WSIE - Word Start Interrupt Enable
 *  0b0..Disables interrupt.
 *  0b1..Enables interrupt.
 */
#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
#define I2S_RCSR_FRF_MASK                        (0x10000U)
#define I2S_RCSR_FRF_SHIFT                       (16U)
/*! FRF - FIFO Request Flag
 *  0b0..Receive FIFO watermark not reached.
 *  0b1..Receive FIFO watermark has been reached.
 */
#define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
#define I2S_RCSR_FWF_MASK                        (0x20000U)
#define I2S_RCSR_FWF_SHIFT                       (17U)
/*! FWF - FIFO Warning Flag
 *  0b0..No enabled receive FIFO is full.
 *  0b1..Enabled receive FIFO is full.
 */
#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
#define I2S_RCSR_FEF_MASK                        (0x40000U)
#define I2S_RCSR_FEF_SHIFT                       (18U)
/*! FEF - FIFO Error Flag
 *  0b0..Receive overflow not detected.
 *  0b1..Receive overflow detected.
 */
#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
#define I2S_RCSR_SEF_MASK                        (0x80000U)
#define I2S_RCSR_SEF_SHIFT                       (19U)
/*! SEF - Sync Error Flag
 *  0b0..Sync error not detected.
 *  0b1..Frame sync error detected.
 */
#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
#define I2S_RCSR_WSF_MASK                        (0x100000U)
#define I2S_RCSR_WSF_SHIFT                       (20U)
/*! WSF - Word Start Flag
 *  0b0..Start of word not detected.
 *  0b1..Start of word detected.
 */
#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
#define I2S_RCSR_SR_MASK                         (0x1000000U)
#define I2S_RCSR_SR_SHIFT                        (24U)
/*! SR - Software Reset
 *  0b0..No effect.
 *  0b1..Software reset.
 */
#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
#define I2S_RCSR_FR_MASK                         (0x2000000U)
#define I2S_RCSR_FR_SHIFT                        (25U)
/*! FR - FIFO Reset
 *  0b0..No effect.
 *  0b1..FIFO reset.
 */
#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
#define I2S_RCSR_BCE_MASK                        (0x10000000U)
#define I2S_RCSR_BCE_SHIFT                       (28U)
/*! BCE - Bit Clock Enable
 *  0b0..Receive bit clock is disabled.
 *  0b1..Receive bit clock is enabled.
 */
#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
#define I2S_RCSR_DBGE_MASK                       (0x20000000U)
#define I2S_RCSR_DBGE_SHIFT                      (29U)
/*! DBGE - Debug Enable
 *  0b0..Receiver is disabled in Debug mode, after completing the current frame.
 *  0b1..Receiver is enabled in Debug mode.
 */
#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
#define I2S_RCSR_STOPE_MASK                      (0x40000000U)
#define I2S_RCSR_STOPE_SHIFT                     (30U)
/*! STOPE - Stop Enable
 *  0b0..Receiver disabled in Stop mode.
 *  0b1..Receiver enabled in Stop mode.
 */
#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
#define I2S_RCSR_RE_MASK                         (0x80000000U)
#define I2S_RCSR_RE_SHIFT                        (31U)
/*! RE - Receiver Enable
 *  0b0..Receiver is disabled.
 *  0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
 */
#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
/*! @} */

/*! @name RCR1 - SAI Receive Configuration 1 Register */
/*! @{ */
#define I2S_RCR1_RFW_MASK                        (0x3FU)
#define I2S_RCR1_RFW_SHIFT                       (0U)
#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
/*! @} */

/*! @name RCR2 - SAI Receive Configuration 2 Register */
/*! @{ */
#define I2S_RCR2_DIV_MASK                        (0xFFU)
#define I2S_RCR2_DIV_SHIFT                       (0U)
#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
#define I2S_RCR2_BCD_MASK                        (0x1000000U)
#define I2S_RCR2_BCD_SHIFT                       (24U)
/*! BCD - Bit Clock Direction
 *  0b0..Bit clock is generated externally in Slave mode.
 *  0b1..Bit clock is generated internally in Master mode.
 */
#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
#define I2S_RCR2_BCP_MASK                        (0x2000000U)
#define I2S_RCR2_BCP_SHIFT                       (25U)
/*! BCP - Bit Clock Polarity
 *  0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
 *  0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
 */
#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
#define I2S_RCR2_MSEL_MASK                       (0xC000000U)
#define I2S_RCR2_MSEL_SHIFT                      (26U)
/*! MSEL - MCLK Select
 *  0b00..Bus Clock selected.
 *  0b01..Master Clock (MCLK) 1 option selected.
 *  0b10..Master Clock (MCLK) 2 option selected.
 *  0b11..Master Clock (MCLK) 3 option selected.
 */
#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
#define I2S_RCR2_BCI_MASK                        (0x10000000U)
#define I2S_RCR2_BCI_SHIFT                       (28U)
/*! BCI - Bit Clock Input
 *  0b0..No effect.
 *  0b1..Internal logic is clocked as if bit clock was externally generated.
 */
#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
#define I2S_RCR2_BCS_MASK                        (0x20000000U)
#define I2S_RCR2_BCS_SHIFT                       (29U)
/*! BCS - Bit Clock Swap
 *  0b0..Use the normal bit clock source.
 *  0b1..Swap the bit clock source.
 */
#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
#define I2S_RCR2_SYNC_MASK                       (0xC0000000U)
#define I2S_RCR2_SYNC_SHIFT                      (30U)
/*! SYNC - Synchronous Mode
 *  0b00..Asynchronous mode.
 *  0b01..Synchronous with transmitter.
 *  0b10..Synchronous with another SAI receiver.
 *  0b11..Synchronous with another SAI transmitter.
 */
#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
/*! @} */

/*! @name RCR3 - SAI Receive Configuration 3 Register */
/*! @{ */
#define I2S_RCR3_WDFL_MASK                       (0x1FU)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define I2S_RCR3_WDFL_SHIFT                      (0U)
#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define I2S_RCR3_RCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define I2S_RCR3_RCE_SHIFT                       (16U)
#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define I2S_RCR3_CFR_MASK                        (0xF000000U)
#define I2S_RCR3_CFR_SHIFT                       (24U)
#define I2S_RCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
/*! @} */

/*! @name RCR4 - SAI Receive Configuration 4 Register */
/*! @{ */
#define I2S_RCR4_FSD_MASK                        (0x1U)
#define I2S_RCR4_FSD_SHIFT                       (0U)
/*! FSD - Frame Sync Direction
 *  0b0..Frame Sync is generated externally in Slave mode.
 *  0b1..Frame Sync is generated internally in Master mode.
 */
#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
#define I2S_RCR4_FSP_MASK                        (0x2U)
#define I2S_RCR4_FSP_SHIFT                       (1U)
/*! FSP - Frame Sync Polarity
 *  0b0..Frame sync is active high.
 *  0b1..Frame sync is active low.
 */
#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
#define I2S_RCR4_ONDEM_MASK                      (0x4U)
#define I2S_RCR4_ONDEM_SHIFT                     (2U)
/*! ONDEM - On Demand Mode
 *  0b0..Internal frame sync is generated continuously.
 *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
 */
#define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
#define I2S_RCR4_FSE_MASK                        (0x8U)
#define I2S_RCR4_FSE_SHIFT                       (3U)
/*! FSE - Frame Sync Early
 *  0b0..Frame sync asserts with the first bit of the frame.
 *  0b1..Frame sync asserts one bit before the first bit of the frame.
 */
#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
#define I2S_RCR4_MF_MASK                         (0x10U)
#define I2S_RCR4_MF_SHIFT                        (4U)
/*! MF - MSB First
 *  0b0..LSB is received first.
 *  0b1..MSB is received first.
 */
#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
#define I2S_RCR4_SYWD_MASK                       (0x1F00U)
#define I2S_RCR4_SYWD_SHIFT                      (8U)
#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
#define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define I2S_RCR4_FRSZ_SHIFT                      (16U)
#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define I2S_RCR4_FPACK_MASK                      (0x3000000U)
#define I2S_RCR4_FPACK_SHIFT                     (24U)
/*! FPACK - FIFO Packing Mode
 *  0b00..FIFO packing is disabled
 *  0b01..Reserved.
 *  0b10..8-bit FIFO packing is enabled
 *  0b11..16-bit FIFO packing is enabled
 */
#define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
#define I2S_RCR4_FCOMB_MASK                      (0xC000000U)
#define I2S_RCR4_FCOMB_SHIFT                     (26U)
/*! FCOMB - FIFO Combine Mode
 *  0b00..FIFO combine mode disabled.
 *  0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
 *  0b10..FIFO combine mode enabled on FIFO reads (by software).
 *  0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
 */
#define I2S_RCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
#define I2S_RCR4_FCONT_MASK                      (0x10000000U)
#define I2S_RCR4_FCONT_SHIFT                     (28U)
/*! FCONT - FIFO Continue on Error
 *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
 *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
 */
#define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
/*! @} */

/*! @name RCR5 - SAI Receive Configuration 5 Register */
/*! @{ */
#define I2S_RCR5_FBT_MASK                        (0x1F00U)
#define I2S_RCR5_FBT_SHIFT                       (8U)
#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
#define I2S_RCR5_W0W_MASK                        (0x1F0000U)
#define I2S_RCR5_W0W_SHIFT                       (16U)
#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
#define I2S_RCR5_WNW_MASK                        (0x1F000000U)
#define I2S_RCR5_WNW_SHIFT                       (24U)
#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
/*! @} */

/*! @name RDR - SAI Receive Data Register */
/*! @{ */
#define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
#define I2S_RDR_RDR_SHIFT                        (0U)
#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
/*! @} */

/* The count of I2S_RDR */
#define I2S_RDR_COUNT                            (4U)

/*! @name RFR - SAI Receive FIFO Register */
/*! @{ */
#define I2S_RFR_RFP_MASK                         (0x7FU)
#define I2S_RFR_RFP_SHIFT                        (0U)
#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
#define I2S_RFR_RCP_MASK                         (0x8000U)
#define I2S_RFR_RCP_SHIFT                        (15U)
/*! RCP - Receive Channel Pointer
 *  0b0..No effect.
 *  0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
 */
#define I2S_RFR_RCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
#define I2S_RFR_WFP_MASK                         (0x7F0000U)
#define I2S_RFR_WFP_SHIFT                        (16U)
#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
/*! @} */

/* The count of I2S_RFR */
#define I2S_RFR_COUNT                            (4U)

/*! @name RMR - SAI Receive Mask Register */
/*! @{ */
#define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)  /* Merged from fields with different position or width, of widths (8, 32), largest definition used */
#define I2S_RMR_RWM_SHIFT                        (0U)
/*! RWM - Receive Word Mask
 *  0b00000000000000000000000000000000..Word N is enabled.
 *  0b00000000000000000000000000000001..Word N is masked.
 */
#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)  /* Merged from fields with different position or width, of widths (8, 32), largest definition used */
/*! @} */


/*!
 * @}
 */ /* end of group I2S_Register_Masks */


/* I2S - Peripheral instance base addresses */
/** Peripheral AUDIO__SAI0 base address */
#define AUDIO__SAI0_BASE                         (0x59040000u)
/** Peripheral AUDIO__SAI0 base pointer */
#define AUDIO__SAI0                              ((I2S_Type *)AUDIO__SAI0_BASE)
/** Peripheral AUDIO__SAI1 base address */
#define AUDIO__SAI1_BASE                         (0x59050000u)
/** Peripheral AUDIO__SAI1 base pointer */
#define AUDIO__SAI1                              ((I2S_Type *)AUDIO__SAI1_BASE)
/** Peripheral AUDIO__SAI2 base address */
#define AUDIO__SAI2_BASE                         (0x59060000u)
/** Peripheral AUDIO__SAI2 base pointer */
#define AUDIO__SAI2                              ((I2S_Type *)AUDIO__SAI2_BASE)
/** Peripheral AUDIO__SAI3 base address */
#define AUDIO__SAI3_BASE                         (0x59070000u)
/** Peripheral AUDIO__SAI3 base pointer */
#define AUDIO__SAI3                              ((I2S_Type *)AUDIO__SAI3_BASE)
/** Peripheral AUDIO__SAI6 base address */
#define AUDIO__SAI6_BASE                         (0x59820000u)
/** Peripheral AUDIO__SAI6 base pointer */
#define AUDIO__SAI6                              ((I2S_Type *)AUDIO__SAI6_BASE)
/** Peripheral AUDIO__SAI7 base address */
#define AUDIO__SAI7_BASE                         (0x59830000u)
/** Peripheral AUDIO__SAI7 base pointer */
#define AUDIO__SAI7                              ((I2S_Type *)AUDIO__SAI7_BASE)
/** Peripheral AUDIO__SAI_HDMIRX0 base address */
#define AUDIO__SAI_HDMIRX0_BASE                  (0x59080000u)
/** Peripheral AUDIO__SAI_HDMIRX0 base pointer */
#define AUDIO__SAI_HDMIRX0                       ((I2S_Type *)AUDIO__SAI_HDMIRX0_BASE)
/** Peripheral AUDIO__SAI_HDMITX0 base address */
#define AUDIO__SAI_HDMITX0_BASE                  (0x59090000u)
/** Peripheral AUDIO__SAI_HDMITX0 base pointer */
#define AUDIO__SAI_HDMITX0                       ((I2S_Type *)AUDIO__SAI_HDMITX0_BASE)
/** Array initializer of I2S peripheral base addresses */
#define I2S_BASE_ADDRS                           { AUDIO__SAI0_BASE, AUDIO__SAI1_BASE, AUDIO__SAI2_BASE, AUDIO__SAI3_BASE, AUDIO__SAI6_BASE, AUDIO__SAI7_BASE, AUDIO__SAI_HDMIRX0_BASE, AUDIO__SAI_HDMITX0_BASE }
/** Array initializer of I2S peripheral base pointers */
#define I2S_BASE_PTRS                            { AUDIO__SAI0, AUDIO__SAI1, AUDIO__SAI2, AUDIO__SAI3, AUDIO__SAI6, AUDIO__SAI7, AUDIO__SAI_HDMIRX0, AUDIO__SAI_HDMITX0 }
/** Interrupt vectors for the I2S peripheral type */
#define I2S_RX_IRQS                              { AUDIO_SAI0_INT_IRQn, AUDIO_SAI1_INT_IRQn, AUDIO_SAI2_INT_IRQn, AUDIO_SAI3_INT_IRQn, AUDIO_SAI6_INT_IRQn, AUDIO_SAI7_INT_IRQn, AUDIO_SAI_HDMI_RX_INT_IRQn, AUDIO_SAI_HDMI_TX_INT_IRQn }
#define I2S_TX_IRQS                              { AUDIO_SAI0_INT_IRQn, AUDIO_SAI1_INT_IRQn, AUDIO_SAI2_INT_IRQn, AUDIO_SAI3_INT_IRQn, AUDIO_SAI6_INT_IRQn, AUDIO_SAI7_INT_IRQn, AUDIO_SAI_HDMI_RX_INT_IRQn, AUDIO_SAI_HDMI_TX_INT_IRQn }

/*!
 * @}
 */ /* end of group I2S_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_MJPEG_COMMON_DEC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_MJPEG_COMMON_DEC_Peripheral_Access_Layer IMAGING_LPCG_MJPEG_COMMON_DEC Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_MJPEG_COMMON_DEC - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MJPEG_COMMON_DEC_0;           /**< na, offset: 0x0 */
} IMAGING_LPCG_MJPEG_COMMON_DEC_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_MJPEG_COMMON_DEC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_MJPEG_COMMON_DEC_Register_Masks IMAGING_LPCG_MJPEG_COMMON_DEC Register Masks
 * @{
 */

/*! @name LPCG_MJPEG_COMMON_DEC_0 - na */
/*! @{ */
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_MASK (0x1U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_SHIFT (0U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_MASK (0x2U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_SHIFT (1U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_MASK (0x8U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_SHIFT (3U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_MASK (0x1FFF0U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_SHIFT (4U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_MASK (0x20000U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_SHIFT (17U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_MASK (0x40000U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_SHIFT (18U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_MASK (0x80000U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_SHIFT (19U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_MASK (0xFFF00000U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_SHIFT (20U)
#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_MJPEG_COMMON_DEC_Register_Masks */


/* IMAGING_LPCG_MJPEG_COMMON_DEC - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_DECODE_JPEG_CLK base address */
#define IMAGING__LPCG_DECODE_JPEG_CLK_BASE       (0x585D0000u)
/** Peripheral IMAGING__LPCG_DECODE_JPEG_CLK base pointer */
#define IMAGING__LPCG_DECODE_JPEG_CLK            ((IMAGING_LPCG_MJPEG_COMMON_DEC_Type *)IMAGING__LPCG_DECODE_JPEG_CLK_BASE)
/** Array initializer of IMAGING_LPCG_MJPEG_COMMON_DEC peripheral base addresses
 * */
#define IMAGING_LPCG_MJPEG_COMMON_DEC_BASE_ADDRS { IMAGING__LPCG_DECODE_JPEG_CLK_BASE }
/** Array initializer of IMAGING_LPCG_MJPEG_COMMON_DEC peripheral base pointers
 * */
#define IMAGING_LPCG_MJPEG_COMMON_DEC_BASE_PTRS  { IMAGING__LPCG_DECODE_JPEG_CLK }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_MJPEG_COMMON_DEC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_MJPEG_COMMON_ENC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_MJPEG_COMMON_ENC_Peripheral_Access_Layer IMAGING_LPCG_MJPEG_COMMON_ENC Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_MJPEG_COMMON_ENC - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MJPEG_COMMON_ENC_0;           /**< na, offset: 0x0 */
} IMAGING_LPCG_MJPEG_COMMON_ENC_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_MJPEG_COMMON_ENC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_MJPEG_COMMON_ENC_Register_Masks IMAGING_LPCG_MJPEG_COMMON_ENC Register Masks
 * @{
 */

/*! @name LPCG_MJPEG_COMMON_ENC_0 - na */
/*! @{ */
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_MASK (0x1U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_SHIFT (0U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_MASK (0x2U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_SHIFT (1U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_MASK (0x8U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_SHIFT (3U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_MASK (0x1FFF0U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_SHIFT (4U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_MASK (0x20000U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_SHIFT (17U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_MASK (0x40000U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_SHIFT (18U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_MASK (0x80000U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_SHIFT (19U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_MASK)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_MASK (0xFFF00000U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_SHIFT (20U)
#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_MJPEG_COMMON_ENC_Register_Masks */


/* IMAGING_LPCG_MJPEG_COMMON_ENC - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_ENCODE_JPEG_CLK base address */
#define IMAGING__LPCG_ENCODE_JPEG_CLK_BASE       (0x585F0000u)
/** Peripheral IMAGING__LPCG_ENCODE_JPEG_CLK base pointer */
#define IMAGING__LPCG_ENCODE_JPEG_CLK            ((IMAGING_LPCG_MJPEG_COMMON_ENC_Type *)IMAGING__LPCG_ENCODE_JPEG_CLK_BASE)
/** Array initializer of IMAGING_LPCG_MJPEG_COMMON_ENC peripheral base addresses
 * */
#define IMAGING_LPCG_MJPEG_COMMON_ENC_BASE_ADDRS { IMAGING__LPCG_ENCODE_JPEG_CLK_BASE }
/** Array initializer of IMAGING_LPCG_MJPEG_COMMON_ENC peripheral base pointers
 * */
#define IMAGING_LPCG_MJPEG_COMMON_ENC_BASE_PTRS  { IMAGING__LPCG_ENCODE_JPEG_CLK }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_MJPEG_COMMON_ENC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA0_Peripheral_Access_Layer IMAGING_LPCG_PDMA0 Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_PDMA0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PDMA0_0;                      /**< na, offset: 0x0 */
} IMAGING_LPCG_PDMA0_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA0_Register_Masks IMAGING_LPCG_PDMA0 Register Masks
 * @{
 */

/*! @name LPCG_PDMA0_0 - na */
/*! @{ */
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_MASK (0x1U)
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_SHIFT (0U)
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_MASK)
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_MASK (0x2U)
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_SHIFT (1U)
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_MASK)
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_MASK)
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_MASK (0x8U)
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_SHIFT (3U)
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_MASK)
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_SHIFT (4U)
#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA0_Register_Masks */


/* IMAGING_LPCG_PDMA0 - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_PROC_CLK_0 base address */
#define IMAGING__LPCG_PROC_CLK_0_BASE            (0x58500000u)
/** Peripheral IMAGING__LPCG_PROC_CLK_0 base pointer */
#define IMAGING__LPCG_PROC_CLK_0                 ((IMAGING_LPCG_PDMA0_Type *)IMAGING__LPCG_PROC_CLK_0_BASE)
/** Array initializer of IMAGING_LPCG_PDMA0 peripheral base addresses */
#define IMAGING_LPCG_PDMA0_BASE_ADDRS            { IMAGING__LPCG_PROC_CLK_0_BASE }
/** Array initializer of IMAGING_LPCG_PDMA0 peripheral base pointers */
#define IMAGING_LPCG_PDMA0_BASE_PTRS             { IMAGING__LPCG_PROC_CLK_0 }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA1_Peripheral_Access_Layer IMAGING_LPCG_PDMA1 Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_PDMA1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PDMA1_0;                      /**< na, offset: 0x0 */
} IMAGING_LPCG_PDMA1_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA1_Register_Masks IMAGING_LPCG_PDMA1 Register Masks
 * @{
 */

/*! @name LPCG_PDMA1_0 - na */
/*! @{ */
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_MASK (0x1U)
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_SHIFT (0U)
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_MASK)
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_MASK (0x2U)
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_SHIFT (1U)
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_MASK)
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_MASK)
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_MASK (0x8U)
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_SHIFT (3U)
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_MASK)
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_SHIFT (4U)
#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA1_Register_Masks */


/* IMAGING_LPCG_PDMA1 - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_PROC_CLK_1 base address */
#define IMAGING__LPCG_PROC_CLK_1_BASE            (0x58510000u)
/** Peripheral IMAGING__LPCG_PROC_CLK_1 base pointer */
#define IMAGING__LPCG_PROC_CLK_1                 ((IMAGING_LPCG_PDMA1_Type *)IMAGING__LPCG_PROC_CLK_1_BASE)
/** Array initializer of IMAGING_LPCG_PDMA1 peripheral base addresses */
#define IMAGING_LPCG_PDMA1_BASE_ADDRS            { IMAGING__LPCG_PROC_CLK_1_BASE }
/** Array initializer of IMAGING_LPCG_PDMA1 peripheral base pointers */
#define IMAGING_LPCG_PDMA1_BASE_PTRS             { IMAGING__LPCG_PROC_CLK_1 }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA2_Peripheral_Access_Layer IMAGING_LPCG_PDMA2 Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_PDMA2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PDMA2_0;                      /**< na, offset: 0x0 */
} IMAGING_LPCG_PDMA2_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA2_Register_Masks IMAGING_LPCG_PDMA2 Register Masks
 * @{
 */

/*! @name LPCG_PDMA2_0 - na */
/*! @{ */
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_MASK (0x1U)
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_SHIFT (0U)
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_MASK)
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_MASK (0x2U)
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_SHIFT (1U)
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_MASK)
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_MASK)
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_MASK (0x8U)
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_SHIFT (3U)
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_MASK)
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_SHIFT (4U)
#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA2_Register_Masks */


/* IMAGING_LPCG_PDMA2 - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_PROC_CLK_2 base address */
#define IMAGING__LPCG_PROC_CLK_2_BASE            (0x58520000u)
/** Peripheral IMAGING__LPCG_PROC_CLK_2 base pointer */
#define IMAGING__LPCG_PROC_CLK_2                 ((IMAGING_LPCG_PDMA2_Type *)IMAGING__LPCG_PROC_CLK_2_BASE)
/** Array initializer of IMAGING_LPCG_PDMA2 peripheral base addresses */
#define IMAGING_LPCG_PDMA2_BASE_ADDRS            { IMAGING__LPCG_PROC_CLK_2_BASE }
/** Array initializer of IMAGING_LPCG_PDMA2 peripheral base pointers */
#define IMAGING_LPCG_PDMA2_BASE_PTRS             { IMAGING__LPCG_PROC_CLK_2 }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA3_Peripheral_Access_Layer IMAGING_LPCG_PDMA3 Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_PDMA3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PDMA3_0;                      /**< na, offset: 0x0 */
} IMAGING_LPCG_PDMA3_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA3_Register_Masks IMAGING_LPCG_PDMA3 Register Masks
 * @{
 */

/*! @name LPCG_PDMA3_0 - na */
/*! @{ */
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_MASK (0x1U)
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_SHIFT (0U)
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_MASK)
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_MASK (0x2U)
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_SHIFT (1U)
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_MASK)
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_MASK)
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_MASK (0x8U)
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_SHIFT (3U)
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_MASK)
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_SHIFT (4U)
#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA3_Register_Masks */


/* IMAGING_LPCG_PDMA3 - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_PROC_CLK_3 base address */
#define IMAGING__LPCG_PROC_CLK_3_BASE            (0x58530000u)
/** Peripheral IMAGING__LPCG_PROC_CLK_3 base pointer */
#define IMAGING__LPCG_PROC_CLK_3                 ((IMAGING_LPCG_PDMA3_Type *)IMAGING__LPCG_PROC_CLK_3_BASE)
/** Array initializer of IMAGING_LPCG_PDMA3 peripheral base addresses */
#define IMAGING_LPCG_PDMA3_BASE_ADDRS            { IMAGING__LPCG_PROC_CLK_3_BASE }
/** Array initializer of IMAGING_LPCG_PDMA3 peripheral base pointers */
#define IMAGING_LPCG_PDMA3_BASE_PTRS             { IMAGING__LPCG_PROC_CLK_3 }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA4 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA4_Peripheral_Access_Layer IMAGING_LPCG_PDMA4 Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_PDMA4 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PDMA4_0;                      /**< na, offset: 0x0 */
} IMAGING_LPCG_PDMA4_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA4 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA4_Register_Masks IMAGING_LPCG_PDMA4 Register Masks
 * @{
 */

/*! @name LPCG_PDMA4_0 - na */
/*! @{ */
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_MASK (0x1U)
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_SHIFT (0U)
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_MASK)
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_MASK (0x2U)
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_SHIFT (1U)
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_MASK)
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_MASK)
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_MASK (0x8U)
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_SHIFT (3U)
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_MASK)
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_SHIFT (4U)
#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA4_Register_Masks */


/* IMAGING_LPCG_PDMA4 - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_PROC_CLK_4 base address */
#define IMAGING__LPCG_PROC_CLK_4_BASE            (0x58540000u)
/** Peripheral IMAGING__LPCG_PROC_CLK_4 base pointer */
#define IMAGING__LPCG_PROC_CLK_4                 ((IMAGING_LPCG_PDMA4_Type *)IMAGING__LPCG_PROC_CLK_4_BASE)
/** Array initializer of IMAGING_LPCG_PDMA4 peripheral base addresses */
#define IMAGING_LPCG_PDMA4_BASE_ADDRS            { IMAGING__LPCG_PROC_CLK_4_BASE }
/** Array initializer of IMAGING_LPCG_PDMA4 peripheral base pointers */
#define IMAGING_LPCG_PDMA4_BASE_PTRS             { IMAGING__LPCG_PROC_CLK_4 }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA4_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA5 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA5_Peripheral_Access_Layer IMAGING_LPCG_PDMA5 Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_PDMA5 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PDMA5_0;                      /**< na, offset: 0x0 */
} IMAGING_LPCG_PDMA5_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA5 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA5_Register_Masks IMAGING_LPCG_PDMA5 Register Masks
 * @{
 */

/*! @name LPCG_PDMA5_0 - na */
/*! @{ */
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_MASK (0x1U)
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_SHIFT (0U)
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_MASK)
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_MASK (0x2U)
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_SHIFT (1U)
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_MASK)
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_MASK)
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_MASK (0x8U)
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_SHIFT (3U)
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_MASK)
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_SHIFT (4U)
#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA5_Register_Masks */


/* IMAGING_LPCG_PDMA5 - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_PROC_CLK_5 base address */
#define IMAGING__LPCG_PROC_CLK_5_BASE            (0x58550000u)
/** Peripheral IMAGING__LPCG_PROC_CLK_5 base pointer */
#define IMAGING__LPCG_PROC_CLK_5                 ((IMAGING_LPCG_PDMA5_Type *)IMAGING__LPCG_PROC_CLK_5_BASE)
/** Array initializer of IMAGING_LPCG_PDMA5 peripheral base addresses */
#define IMAGING_LPCG_PDMA5_BASE_ADDRS            { IMAGING__LPCG_PROC_CLK_5_BASE }
/** Array initializer of IMAGING_LPCG_PDMA5 peripheral base pointers */
#define IMAGING_LPCG_PDMA5_BASE_PTRS             { IMAGING__LPCG_PROC_CLK_5 }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA5_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA6 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA6_Peripheral_Access_Layer IMAGING_LPCG_PDMA6 Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_PDMA6 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PDMA6_0;                      /**< na, offset: 0x0 */
} IMAGING_LPCG_PDMA6_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA6 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA6_Register_Masks IMAGING_LPCG_PDMA6 Register Masks
 * @{
 */

/*! @name LPCG_PDMA6_0 - na */
/*! @{ */
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_HWEN_MASK (0x1U)
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_HWEN_SHIFT (0U)
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_HWEN_SHIFT)) & IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_HWEN_MASK)
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_SWEN_MASK (0x2U)
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_SWEN_SHIFT (1U)
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_SWEN_SHIFT)) & IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_SWEN_MASK)
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_LPCG_PDMA6_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_LPCG_PDMA6_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_LPCG_PDMA6_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_LPCG_PDMA6_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_LPCG_PDMA6_0_reserved_2_2_MASK)
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_STOP_MASK (0x8U)
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_STOP_SHIFT (3U)
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_STOP_SHIFT)) & IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_isi_ipg_proc_clk_6_STOP_MASK)
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_LPCG_PDMA6_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_LPCG_PDMA6_0_reserved_4_31_SHIFT (4U)
#define IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_LPCG_PDMA6_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_LPCG_PDMA6_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA6_LPCG_PDMA6_0_LPCG_PDMA6_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA6_Register_Masks */


/* IMAGING_LPCG_PDMA6 - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_PROC_CLK_6 base address */
#define IMAGING__LPCG_PROC_CLK_6_BASE            (0x58560000u)
/** Peripheral IMAGING__LPCG_PROC_CLK_6 base pointer */
#define IMAGING__LPCG_PROC_CLK_6                 ((IMAGING_LPCG_PDMA6_Type *)IMAGING__LPCG_PROC_CLK_6_BASE)
/** Array initializer of IMAGING_LPCG_PDMA6 peripheral base addresses */
#define IMAGING_LPCG_PDMA6_BASE_ADDRS            { IMAGING__LPCG_PROC_CLK_6_BASE }
/** Array initializer of IMAGING_LPCG_PDMA6 peripheral base pointers */
#define IMAGING_LPCG_PDMA6_BASE_PTRS             { IMAGING__LPCG_PROC_CLK_6 }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA6_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA7 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA7_Peripheral_Access_Layer IMAGING_LPCG_PDMA7 Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_PDMA7 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PDMA7_0;                      /**< na, offset: 0x0 */
} IMAGING_LPCG_PDMA7_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PDMA7 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PDMA7_Register_Masks IMAGING_LPCG_PDMA7 Register Masks
 * @{
 */

/*! @name LPCG_PDMA7_0 - na */
/*! @{ */
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_HWEN_MASK (0x1U)
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_HWEN_SHIFT (0U)
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_HWEN_SHIFT)) & IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_HWEN_MASK)
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_SWEN_MASK (0x2U)
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_SWEN_SHIFT (1U)
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_SWEN_SHIFT)) & IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_SWEN_MASK)
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_LPCG_PDMA7_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_LPCG_PDMA7_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_LPCG_PDMA7_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_LPCG_PDMA7_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_LPCG_PDMA7_0_reserved_2_2_MASK)
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_STOP_MASK (0x8U)
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_STOP_SHIFT (3U)
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_STOP_SHIFT)) & IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_isi_ipg_proc_clk_7_STOP_MASK)
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_LPCG_PDMA7_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_LPCG_PDMA7_0_reserved_4_31_SHIFT (4U)
#define IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_LPCG_PDMA7_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_LPCG_PDMA7_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA7_LPCG_PDMA7_0_LPCG_PDMA7_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA7_Register_Masks */


/* IMAGING_LPCG_PDMA7 - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_PROC_CLK_7 base address */
#define IMAGING__LPCG_PROC_CLK_7_BASE            (0x58570000u)
/** Peripheral IMAGING__LPCG_PROC_CLK_7 base pointer */
#define IMAGING__LPCG_PROC_CLK_7                 ((IMAGING_LPCG_PDMA7_Type *)IMAGING__LPCG_PROC_CLK_7_BASE)
/** Array initializer of IMAGING_LPCG_PDMA7 peripheral base addresses */
#define IMAGING_LPCG_PDMA7_BASE_ADDRS            { IMAGING__LPCG_PROC_CLK_7_BASE }
/** Array initializer of IMAGING_LPCG_PDMA7 peripheral base pointers */
#define IMAGING_LPCG_PDMA7_BASE_PTRS             { IMAGING__LPCG_PROC_CLK_7 }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_PDMA7_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PIXEL_LINK_SLAVE_CSI1_0;      /**< na, offset: 0x0 */
} IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Register Masks
 * @{
 */

/*! @name LPCG_PIXEL_LINK_SLAVE_CSI1_0 - na */
/*! @{ */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_MASK (0x1U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_SHIFT (0U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_MASK (0x2U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_SHIFT (1U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_MASK (0x8U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_SHIFT (3U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_SHIFT (4U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Register_Masks */


/* IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI0 base address */
#define IMAGING__LPCG_PIXEL_LINK_SLV_CSI0_BASE   (0x58580000u)
/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI0 base pointer */
#define IMAGING__LPCG_PIXEL_LINK_SLV_CSI0        ((IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_CSI0_BASE)
/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 peripheral base
 * addresses */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI0_BASE }
/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 peripheral base
 * pointers */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI0 }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PIXEL_LINK_SLAVE_CSI2_0;      /**< na, offset: 0x0 */
} IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Register Masks
 * @{
 */

/*! @name LPCG_PIXEL_LINK_SLAVE_CSI2_0 - na */
/*! @{ */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_MASK (0x1U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_SHIFT (0U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_MASK (0x2U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_SHIFT (1U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_MASK (0x8U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_SHIFT (3U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_SHIFT (4U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Register_Masks */


/* IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI1 base address */
#define IMAGING__LPCG_PIXEL_LINK_SLV_CSI1_BASE   (0x58590000u)
/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI1 base pointer */
#define IMAGING__LPCG_PIXEL_LINK_SLV_CSI1        ((IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_CSI1_BASE)
/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 peripheral base
 * addresses */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI1_BASE }
/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 peripheral base
 * pointers */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI1 }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PIXEL_LINK_SLAVE_DC0_0;       /**< na, offset: 0x0 */
} IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Register Masks
 * @{
 */

/*! @name LPCG_PIXEL_LINK_SLAVE_DC0_0 - na */
/*! @{ */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_MASK (0x1U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_SHIFT (0U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_MASK (0x2U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_SHIFT (1U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_MASK (0x8U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_SHIFT (3U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_SHIFT (4U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Register_Masks */


/* IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK base address */
#define IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK_BASE (0x585C0000u)
/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK base pointer */
#define IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK ((IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK_BASE)
/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 peripheral base
 * addresses */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK_BASE }
/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 peripheral base
 * pointers */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PIXEL_LINK_SLAVE_DC1_0;       /**< na, offset: 0x0 */
} IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Register Masks
 * @{
 */

/*! @name LPCG_PIXEL_LINK_SLAVE_DC1_0 - na */
/*! @{ */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_MASK (0x1U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_SHIFT (0U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_MASK (0x2U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_SHIFT (1U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_MASK (0x8U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_SHIFT (3U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_SHIFT (4U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Register_Masks */


/* IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK base address */
#define IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK_BASE (0x585E0000u)
/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK base pointer */
#define IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK ((IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK_BASE)
/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 peripheral base
 * addresses */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK_BASE }
/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 peripheral base
 * pointers */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Peripheral Access Layer
 * @{
 */

/** IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0;   /**< na, offset: 0x0 */
} IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Type;

/* ----------------------------------------------------------------------------
   -- IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Register Masks
 * @{
 */

/*! @name LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0 - na */
/*! @{ */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_MASK (0x1U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_SHIFT (0U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_MASK (0x2U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_SHIFT (1U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_MASK (0x4U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_SHIFT (2U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_MASK (0x8U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_SHIFT (3U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_MASK)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_SHIFT (4U)
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Register_Masks */


/* IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN - Peripheral instance base addresses */
/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK base address */
#define IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_BASE (0x585A0000u)
/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK base pointer */
#define IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK ((IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_BASE)
/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN peripheral base
 * addresses */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_BASE }
/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN peripheral base
 * pointers */
#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK }

/*!
 * @}
 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- INTMUX Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup INTMUX_Peripheral_Access_Layer INTMUX Peripheral Access Layer
 * @{
 */

/** INTMUX - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0, array step: 0x40 */
    __IO uint32_t CHn_CSR;                           /**< Channel n Control Status Register, array offset: 0x0, array step: 0x40 */
    __I  uint32_t CHn_VEC;                           /**< Channel n Vector Number Register, array offset: 0x4, array step: 0x40 */
         uint8_t RESERVED_0[8];
    __IO uint32_t CHn_IER_31_0;                      /**< Channel n Interrupt Enable Register, array offset: 0x10, array step: 0x40 */
         uint8_t RESERVED_1[12];
    __I  uint32_t CHn_IPR_31_0;                      /**< Channel n Interrupt Pending Register, array offset: 0x20, array step: 0x40 */
         uint8_t RESERVED_2[28];
  } CHANNEL[8];
} INTMUX_Type;

/* ----------------------------------------------------------------------------
   -- INTMUX Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup INTMUX_Register_Masks INTMUX Register Masks
 * @{
 */

/*! @name CHn_CSR - Channel n Control Status Register */
/*! @{ */
#define INTMUX_CHn_CSR_RST_MASK                  (0x1U)
#define INTMUX_CHn_CSR_RST_SHIFT                 (0U)
/*! RST - Software Reset
 *  0b0..No operation.
 *  0b1..Perform a software reset on this channel.
 */
#define INTMUX_CHn_CSR_RST(x)                    (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_RST_SHIFT)) & INTMUX_CHn_CSR_RST_MASK)
#define INTMUX_CHn_CSR_AND_MASK                  (0x2U)
#define INTMUX_CHn_CSR_AND_SHIFT                 (1U)
/*! AND - Logic AND
 *  0b0..Logic OR all enabled interrupt inputs.
 *  0b1..Logic AND all enabled interrupt inputs.
 */
#define INTMUX_CHn_CSR_AND(x)                    (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_AND_SHIFT)) & INTMUX_CHn_CSR_AND_MASK)
#define INTMUX_CHn_CSR_IRQN_MASK                 (0x30U)
#define INTMUX_CHn_CSR_IRQN_SHIFT                (4U)
#define INTMUX_CHn_CSR_IRQN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQN_SHIFT)) & INTMUX_CHn_CSR_IRQN_MASK)
#define INTMUX_CHn_CSR_CHIN_MASK                 (0xF00U)
#define INTMUX_CHn_CSR_CHIN_SHIFT                (8U)
#define INTMUX_CHn_CSR_CHIN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_CHIN_SHIFT)) & INTMUX_CHn_CSR_CHIN_MASK)
#define INTMUX_CHn_CSR_IRQP_MASK                 (0x80000000U)
#define INTMUX_CHn_CSR_IRQP_SHIFT                (31U)
/*! IRQP - Channel Interrupt Request Pending
 *  0b0..No interrupt is pending.
 *  0b1..The interrupt output of this channel is pending.
 */
#define INTMUX_CHn_CSR_IRQP(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQP_SHIFT)) & INTMUX_CHn_CSR_IRQP_MASK)
/*! @} */

/* The count of INTMUX_CHn_CSR */
#define INTMUX_CHn_CSR_COUNT                     (8U)

/*! @name CHn_VEC - Channel n Vector Number Register */
/*! @{ */
#define INTMUX_CHn_VEC_VECN_MASK                 (0x3FFCU)
#define INTMUX_CHn_VEC_VECN_SHIFT                (2U)
#define INTMUX_CHn_VEC_VECN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_VEC_VECN_SHIFT)) & INTMUX_CHn_VEC_VECN_MASK)
/*! @} */

/* The count of INTMUX_CHn_VEC */
#define INTMUX_CHn_VEC_COUNT                     (8U)

/*! @name CHn_IER_31_0 - Channel n Interrupt Enable Register */
/*! @{ */
#define INTMUX_CHn_IER_31_0_INTE_MASK            (0xFFFFFFFFU)
#define INTMUX_CHn_IER_31_0_INTE_SHIFT           (0U)
#define INTMUX_CHn_IER_31_0_INTE(x)              (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IER_31_0_INTE_SHIFT)) & INTMUX_CHn_IER_31_0_INTE_MASK)
/*! @} */

/* The count of INTMUX_CHn_IER_31_0 */
#define INTMUX_CHn_IER_31_0_COUNT                (8U)

/*! @name CHn_IPR_31_0 - Channel n Interrupt Pending Register */
/*! @{ */
#define INTMUX_CHn_IPR_31_0_INTP_MASK            (0xFFFFFFFFU)
#define INTMUX_CHn_IPR_31_0_INTP_SHIFT           (0U)
#define INTMUX_CHn_IPR_31_0_INTP(x)              (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IPR_31_0_INTP_SHIFT)) & INTMUX_CHn_IPR_31_0_INTP_MASK)
/*! @} */

/* The count of INTMUX_CHn_IPR_31_0 */
#define INTMUX_CHn_IPR_31_0_COUNT                (8U)


/*!
 * @}
 */ /* end of group INTMUX_Register_Masks */


/* INTMUX - Peripheral instance base addresses */
/** Peripheral CM4_0__INTMUX base address */
#define CM4_0__INTMUX_BASE                       (0x37400000u)
/** Peripheral CM4_0__INTMUX base pointer */
#define CM4_0__INTMUX                            ((INTMUX_Type *)CM4_0__INTMUX_BASE)
/** Peripheral CM4_1__INTMUX base address */
#define CM4_1__INTMUX_BASE                       (0x41400000u)
/** Peripheral CM4_1__INTMUX base pointer */
#define CM4_1__INTMUX                            ((INTMUX_Type *)CM4_1__INTMUX_BASE)
/** Peripheral SCU__INTMUX base address */
#define SCU__INTMUX_BASE                         (0x33400000u)
/** Peripheral SCU__INTMUX base pointer */
#define SCU__INTMUX                              ((INTMUX_Type *)SCU__INTMUX_BASE)
/** Array initializer of INTMUX peripheral base addresses */
#define INTMUX_BASE_ADDRS                        { CM4_0__INTMUX_BASE, CM4_1__INTMUX_BASE, SCU__INTMUX_BASE }
/** Array initializer of INTMUX peripheral base pointers */
#define INTMUX_BASE_PTRS                         { CM4_0__INTMUX, CM4_1__INTMUX, SCU__INTMUX }

/*!
 * @}
 */ /* end of group INTMUX_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IOMUXD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOMUXD_Peripheral_Access_Layer IOMUXD Peripheral Access Layer
 * @{
 */

/** IOMUXD - Register Layout Typedef */
typedef struct {
  __IO uint32_t SIM0_CLK;                          /**< SIM0_CLK, offset: 0x0 */
       uint8_t RESERVED_0[60];
  __IO uint32_t SIM0_RST;                          /**< SIM0_RST, offset: 0x40 */
       uint8_t RESERVED_1[60];
  __IO uint32_t SIM0_IO;                           /**< SIM0_IO, offset: 0x80 */
       uint8_t RESERVED_2[60];
  __IO uint32_t SIM0_PD;                           /**< SIM0_PD, offset: 0xC0 */
       uint8_t RESERVED_3[60];
  __IO uint32_t SIM0_POWER_EN;                     /**< SIM0_POWER_EN, offset: 0x100 */
       uint8_t RESERVED_4[60];
  __IO uint32_t SIM0_GPIO0_00;                     /**< SIM0_GPIO0_00, offset: 0x140 */
       uint8_t RESERVED_5[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM;  /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM, offset: 0x180 */
       uint8_t RESERVED_6[60];
  __IO uint32_t M40_I2C0_SCL;                      /**< M40_I2C0_SCL, offset: 0x1C0 */
       uint8_t RESERVED_7[60];
  __IO uint32_t M40_I2C0_SDA;                      /**< M40_I2C0_SDA, offset: 0x200 */
       uint8_t RESERVED_8[60];
  __IO uint32_t M40_GPIO0_00;                      /**< M40_GPIO0_00, offset: 0x240 */
       uint8_t RESERVED_9[60];
  __IO uint32_t M40_GPIO0_01;                      /**< M40_GPIO0_01, offset: 0x280 */
       uint8_t RESERVED_10[60];
  __IO uint32_t M41_I2C0_SCL;                      /**< M41_I2C0_SCL, offset: 0x2C0 */
       uint8_t RESERVED_11[60];
  __IO uint32_t M41_I2C0_SDA;                      /**< M41_I2C0_SDA, offset: 0x300 */
       uint8_t RESERVED_12[60];
  __IO uint32_t M41_GPIO0_00;                      /**< M41_GPIO0_00, offset: 0x340 */
       uint8_t RESERVED_13[60];
  __IO uint32_t M41_GPIO0_01;                      /**< M41_GPIO0_01, offset: 0x380 */
       uint8_t RESERVED_14[124];
  __I  uint32_t IOMUXD_GROUP_0_0;                  /**< na, offset: 0x400 */
       uint8_t RESERVED_15[3068];
  __IO uint32_t GPT0_CLK;                          /**< GPT0_CLK, offset: 0x1000 */
       uint8_t RESERVED_16[60];
  __IO uint32_t GPT0_CAPTURE;                      /**< GPT0_CAPTURE, offset: 0x1040 */
       uint8_t RESERVED_17[60];
  __IO uint32_t GPT0_COMPARE;                      /**< GPT0_COMPARE, offset: 0x1080 */
       uint8_t RESERVED_18[60];
  __IO uint32_t GPT1_CLK;                          /**< GPT1_CLK, offset: 0x10C0 */
       uint8_t RESERVED_19[60];
  __IO uint32_t GPT1_CAPTURE;                      /**< GPT1_CAPTURE, offset: 0x1100 */
       uint8_t RESERVED_20[60];
  __IO uint32_t GPT1_COMPARE;                      /**< GPT1_COMPARE, offset: 0x1140 */
       uint8_t RESERVED_21[60];
  __IO uint32_t UART0_RX;                          /**< UART0_RX, offset: 0x1180 */
       uint8_t RESERVED_22[60];
  __IO uint32_t UART0_TX;                          /**< UART0_TX, offset: 0x11C0 */
       uint8_t RESERVED_23[60];
  __IO uint32_t UART0_RTS_B;                       /**< UART0_RTS_B, offset: 0x1200 */
       uint8_t RESERVED_24[60];
  __IO uint32_t UART0_CTS_B;                       /**< UART0_CTS_B, offset: 0x1240 */
       uint8_t RESERVED_25[60];
  __IO uint32_t UART1_TX;                          /**< UART1_TX, offset: 0x1280 */
       uint8_t RESERVED_26[60];
  __IO uint32_t UART1_RX;                          /**< UART1_RX, offset: 0x12C0 */
       uint8_t RESERVED_27[60];
  __IO uint32_t UART1_RTS_B;                       /**< UART1_RTS_B, offset: 0x1300 */
       uint8_t RESERVED_28[60];
  __IO uint32_t UART1_CTS_B;                       /**< UART1_CTS_B, offset: 0x1340 */
       uint8_t RESERVED_29[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH, offset: 0x1380 */
       uint8_t RESERVED_30[60];
  __IO uint32_t SCU_PMIC_MEMC_ON;                  /**< SCU_PMIC_MEMC_ON, offset: 0x13C0 */
       uint8_t RESERVED_31[60];
  __I  uint32_t IOMUXD_GROUP_0_1;                  /**< na, offset: 0x1400 */
       uint8_t RESERVED_32[3068];
  __IO uint32_t SCU_WDOG_OUT;                      /**< SCU_WDOG_OUT, offset: 0x2000 */
       uint8_t RESERVED_33[60];
  __IO uint32_t PMIC_I2C_SDA;                      /**< PMIC_I2C_SDA, offset: 0x2040 */
       uint8_t RESERVED_34[60];
  __IO uint32_t PMIC_I2C_SCL;                      /**< PMIC_I2C_SCL, offset: 0x2080 */
       uint8_t RESERVED_35[60];
  __IO uint32_t PMIC_EARLY_WARNING;                /**< PMIC_EARLY_WARNING, offset: 0x20C0 */
       uint8_t RESERVED_36[60];
  __IO uint32_t PMIC_INT_B;                        /**< PMIC_INT_B, offset: 0x2100 */
       uint8_t RESERVED_37[60];
  __IO uint32_t SCU_GPIO0_00;                      /**< SCU_GPIO0_00, offset: 0x2140 */
       uint8_t RESERVED_38[60];
  __IO uint32_t SCU_GPIO0_01;                      /**< SCU_GPIO0_01, offset: 0x2180 */
       uint8_t RESERVED_39[636];
  __I  uint32_t IOMUXD_GROUP_0_2;                  /**< na, offset: 0x2400 */
       uint8_t RESERVED_40[3068];
  __IO uint32_t SCU_GPIO0_02;                      /**< SCU_GPIO0_02, offset: 0x3000 */
       uint8_t RESERVED_41[60];
  __IO uint32_t SCU_GPIO0_03;                      /**< SCU_GPIO0_03, offset: 0x3040 */
       uint8_t RESERVED_42[60];
  __IO uint32_t SCU_GPIO0_04;                      /**< SCU_GPIO0_04, offset: 0x3080 */
       uint8_t RESERVED_43[60];
  __IO uint32_t SCU_GPIO0_05;                      /**< SCU_GPIO0_05, offset: 0x30C0 */
       uint8_t RESERVED_44[60];
  __IO uint32_t SCU_GPIO0_06;                      /**< SCU_GPIO0_06, offset: 0x3100 */
       uint8_t RESERVED_45[60];
  __IO uint32_t SCU_GPIO0_07;                      /**< SCU_GPIO0_07, offset: 0x3140 */
       uint8_t RESERVED_46[60];
  __IO uint32_t SCU_BOOT_MODE0;                    /**< SCU_BOOT_MODE0, offset: 0x3180 */
       uint8_t RESERVED_47[60];
  __IO uint32_t SCU_BOOT_MODE1;                    /**< SCU_BOOT_MODE1, offset: 0x31C0 */
       uint8_t RESERVED_48[60];
  __IO uint32_t SCU_BOOT_MODE2;                    /**< SCU_BOOT_MODE2, offset: 0x3200 */
       uint8_t RESERVED_49[60];
  __IO uint32_t SCU_BOOT_MODE3;                    /**< SCU_BOOT_MODE3, offset: 0x3240 */
       uint8_t RESERVED_50[60];
  __IO uint32_t SCU_BOOT_MODE4;                    /**< SCU_BOOT_MODE4, offset: 0x3280 */
       uint8_t RESERVED_51[60];
  __IO uint32_t SCU_BOOT_MODE5;                    /**< SCU_BOOT_MODE5, offset: 0x32C0 */
       uint8_t RESERVED_52[316];
  __I  uint32_t IOMUXD_GROUP_0_3;                  /**< na, offset: 0x3400 */
       uint8_t RESERVED_53[3068];
  __IO uint32_t LVDS0_GPIO00;                      /**< LVDS0_GPIO00, offset: 0x4000 */
       uint8_t RESERVED_54[60];
  __IO uint32_t LVDS0_GPIO01;                      /**< LVDS0_GPIO01, offset: 0x4040 */
       uint8_t RESERVED_55[60];
  __IO uint32_t LVDS0_I2C0_SCL;                    /**< LVDS0_I2C0_SCL, offset: 0x4080 */
       uint8_t RESERVED_56[60];
  __IO uint32_t LVDS0_I2C0_SDA;                    /**< LVDS0_I2C0_SDA, offset: 0x40C0 */
       uint8_t RESERVED_57[60];
  __IO uint32_t LVDS0_I2C1_SCL;                    /**< LVDS0_I2C1_SCL, offset: 0x4100 */
       uint8_t RESERVED_58[60];
  __IO uint32_t LVDS0_I2C1_SDA;                    /**< LVDS0_I2C1_SDA, offset: 0x4140 */
       uint8_t RESERVED_59[60];
  __IO uint32_t LVDS1_GPIO00;                      /**< LVDS1_GPIO00, offset: 0x4180 */
       uint8_t RESERVED_60[60];
  __IO uint32_t LVDS1_GPIO01;                      /**< LVDS1_GPIO01, offset: 0x41C0 */
       uint8_t RESERVED_61[60];
  __IO uint32_t LVDS1_I2C0_SCL;                    /**< LVDS1_I2C0_SCL, offset: 0x4200 */
       uint8_t RESERVED_62[60];
  __IO uint32_t LVDS1_I2C0_SDA;                    /**< LVDS1_I2C0_SDA, offset: 0x4240 */
       uint8_t RESERVED_63[60];
  __IO uint32_t LVDS1_I2C1_SCL;                    /**< LVDS1_I2C1_SCL, offset: 0x4280 */
       uint8_t RESERVED_64[60];
  __IO uint32_t LVDS1_I2C1_SDA;                    /**< LVDS1_I2C1_SDA, offset: 0x42C0 */
       uint8_t RESERVED_65[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO, offset: 0x4300 */
       uint8_t RESERVED_66[252];
  __I  uint32_t IOMUXD_GROUP_0_4;                  /**< na, offset: 0x4400 */
       uint8_t RESERVED_67[113660];
  __IO uint32_t MIPI_DSI0_I2C0_SCL;                /**< MIPI_DSI0_I2C0_SCL, offset: 0x20000 */
       uint8_t RESERVED_68[60];
  __IO uint32_t MIPI_DSI0_I2C0_SDA;                /**< MIPI_DSI0_I2C0_SDA, offset: 0x20040 */
       uint8_t RESERVED_69[60];
  __IO uint32_t MIPI_DSI0_GPIO0_00;                /**< MIPI_DSI0_GPIO0_00, offset: 0x20080 */
       uint8_t RESERVED_70[60];
  __IO uint32_t MIPI_DSI0_GPIO0_01;                /**< MIPI_DSI0_GPIO0_01, offset: 0x200C0 */
       uint8_t RESERVED_71[60];
  __IO uint32_t MIPI_DSI1_I2C0_SCL;                /**< MIPI_DSI1_I2C0_SCL, offset: 0x20100 */
       uint8_t RESERVED_72[60];
  __IO uint32_t MIPI_DSI1_I2C0_SDA;                /**< MIPI_DSI1_I2C0_SDA, offset: 0x20140 */
       uint8_t RESERVED_73[60];
  __IO uint32_t MIPI_DSI1_GPIO0_00;                /**< MIPI_DSI1_GPIO0_00, offset: 0x20180 */
       uint8_t RESERVED_74[60];
  __IO uint32_t MIPI_DSI1_GPIO0_01;                /**< MIPI_DSI1_GPIO0_01, offset: 0x201C0 */
       uint8_t RESERVED_75[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO, offset: 0x20200 */
       uint8_t RESERVED_76[508];
  __I  uint32_t IOMUXD_GROUP_1_0;                  /**< na, offset: 0x20400 */
       uint8_t RESERVED_77[3068];
  __IO uint32_t MIPI_CSI0_MCLK_OUT;                /**< MIPI_CSI0_MCLK_OUT, offset: 0x21000 */
       uint8_t RESERVED_78[60];
  __IO uint32_t MIPI_CSI0_I2C0_SCL;                /**< MIPI_CSI0_I2C0_SCL, offset: 0x21040 */
       uint8_t RESERVED_79[60];
  __IO uint32_t MIPI_CSI0_I2C0_SDA;                /**< MIPI_CSI0_I2C0_SDA, offset: 0x21080 */
       uint8_t RESERVED_80[60];
  __IO uint32_t MIPI_CSI0_GPIO0_00;                /**< MIPI_CSI0_GPIO0_00, offset: 0x210C0 */
       uint8_t RESERVED_81[60];
  __IO uint32_t MIPI_CSI0_GPIO0_01;                /**< MIPI_CSI0_GPIO0_01, offset: 0x21100 */
       uint8_t RESERVED_82[60];
  __IO uint32_t MIPI_CSI1_MCLK_OUT;                /**< MIPI_CSI1_MCLK_OUT, offset: 0x21140 */
       uint8_t RESERVED_83[60];
  __IO uint32_t MIPI_CSI1_GPIO0_00;                /**< MIPI_CSI1_GPIO0_00, offset: 0x21180 */
       uint8_t RESERVED_84[60];
  __IO uint32_t MIPI_CSI1_GPIO0_01;                /**< MIPI_CSI1_GPIO0_01, offset: 0x211C0 */
       uint8_t RESERVED_85[60];
  __IO uint32_t MIPI_CSI1_I2C0_SCL;                /**< MIPI_CSI1_I2C0_SCL, offset: 0x21200 */
       uint8_t RESERVED_86[60];
  __IO uint32_t MIPI_CSI1_I2C0_SDA;                /**< MIPI_CSI1_I2C0_SDA, offset: 0x21240 */
       uint8_t RESERVED_87[60];
  __IO uint32_t HDMI_TX0_TS_SCL;                   /**< HDMI_TX0_TS_SCL, offset: 0x21280 */
       uint8_t RESERVED_88[60];
  __IO uint32_t HDMI_TX0_TS_SDA;                   /**< HDMI_TX0_TS_SDA, offset: 0x212C0 */
       uint8_t RESERVED_89[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO; /**< IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO, offset: 0x21300 */
       uint8_t RESERVED_90[252];
  __I  uint32_t IOMUXD_GROUP_1_1;                  /**< na, offset: 0x21400 */
       uint8_t RESERVED_91[3068];
  __IO uint32_t ESAI1_FSR;                         /**< ESAI1_FSR, offset: 0x22000 */
       uint8_t RESERVED_92[60];
  __IO uint32_t ESAI1_FST;                         /**< ESAI1_FST, offset: 0x22040 */
       uint8_t RESERVED_93[60];
  __IO uint32_t ESAI1_SCKR;                        /**< ESAI1_SCKR, offset: 0x22080 */
       uint8_t RESERVED_94[60];
  __IO uint32_t ESAI1_SCKT;                        /**< ESAI1_SCKT, offset: 0x220C0 */
       uint8_t RESERVED_95[60];
  __IO uint32_t ESAI1_TX0;                         /**< ESAI1_TX0, offset: 0x22100 */
       uint8_t RESERVED_96[60];
  __IO uint32_t ESAI1_TX1;                         /**< ESAI1_TX1, offset: 0x22140 */
       uint8_t RESERVED_97[60];
  __IO uint32_t ESAI1_TX2_RX3;                     /**< ESAI1_TX2_RX3, offset: 0x22180 */
       uint8_t RESERVED_98[60];
  __IO uint32_t ESAI1_TX3_RX2;                     /**< ESAI1_TX3_RX2, offset: 0x221C0 */
       uint8_t RESERVED_99[60];
  __IO uint32_t ESAI1_TX4_RX1;                     /**< ESAI1_TX4_RX1, offset: 0x22200 */
       uint8_t RESERVED_100[60];
  __IO uint32_t ESAI1_TX5_RX0;                     /**< ESAI1_TX5_RX0, offset: 0x22240 */
       uint8_t RESERVED_101[60];
  __IO uint32_t SPDIF0_RX;                         /**< SPDIF0_RX, offset: 0x22280 */
       uint8_t RESERVED_102[60];
  __IO uint32_t SPDIF0_TX;                         /**< SPDIF0_TX, offset: 0x222C0 */
       uint8_t RESERVED_103[60];
  __IO uint32_t SPDIF0_EXT_CLK;                    /**< SPDIF0_EXT_CLK, offset: 0x22300 */
       uint8_t RESERVED_104[60];
  __IO uint32_t SPI3_SCK;                          /**< SPI3_SCK, offset: 0x22340 */
       uint8_t RESERVED_105[60];
  __IO uint32_t SPI3_SDO;                          /**< SPI3_SDO, offset: 0x22380 */
       uint8_t RESERVED_106[124];
  __I  uint32_t IOMUXD_GROUP_1_2;                  /**< na, offset: 0x22400 */
       uint8_t RESERVED_107[3068];
  __IO uint32_t SPI3_SDI;                          /**< SPI3_SDI, offset: 0x23000 */
       uint8_t RESERVED_108[60];
  __IO uint32_t SPI3_CS0;                          /**< SPI3_CS0, offset: 0x23040 */
       uint8_t RESERVED_109[60];
  __IO uint32_t SPI3_CS1;                          /**< SPI3_CS1, offset: 0x23080 */
       uint8_t RESERVED_110[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB, offset: 0x230C0 */
       uint8_t RESERVED_111[60];
  __IO uint32_t ESAI0_FSR;                         /**< ESAI0_FSR, offset: 0x23100 */
       uint8_t RESERVED_112[60];
  __IO uint32_t ESAI0_FST;                         /**< ESAI0_FST, offset: 0x23140 */
       uint8_t RESERVED_113[60];
  __IO uint32_t ESAI0_SCKR;                        /**< ESAI0_SCKR, offset: 0x23180 */
       uint8_t RESERVED_114[60];
  __IO uint32_t ESAI0_SCKT;                        /**< ESAI0_SCKT, offset: 0x231C0 */
       uint8_t RESERVED_115[60];
  __IO uint32_t ESAI0_TX0;                         /**< ESAI0_TX0, offset: 0x23200 */
       uint8_t RESERVED_116[60];
  __IO uint32_t ESAI0_TX1;                         /**< ESAI0_TX1, offset: 0x23240 */
       uint8_t RESERVED_117[60];
  __IO uint32_t ESAI0_TX2_RX3;                     /**< ESAI0_TX2_RX3, offset: 0x23280 */
       uint8_t RESERVED_118[60];
  __IO uint32_t ESAI0_TX3_RX2;                     /**< ESAI0_TX3_RX2, offset: 0x232C0 */
       uint8_t RESERVED_119[60];
  __IO uint32_t ESAI0_TX4_RX1;                     /**< ESAI0_TX4_RX1, offset: 0x23300 */
       uint8_t RESERVED_120[60];
  __IO uint32_t ESAI0_TX5_RX0;                     /**< ESAI0_TX5_RX0, offset: 0x23340 */
       uint8_t RESERVED_121[60];
  __IO uint32_t MCLK_IN0;                          /**< MCLK_IN0, offset: 0x23380 */
       uint8_t RESERVED_122[124];
  __I  uint32_t IOMUXD_GROUP_1_3;                  /**< na, offset: 0x23400 */
       uint8_t RESERVED_123[3068];
  __IO uint32_t MCLK_OUT0;                         /**< MCLK_OUT0, offset: 0x24000 */
       uint8_t RESERVED_124[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC, offset: 0x24040 */
       uint8_t RESERVED_125[60];
  __IO uint32_t SPI0_SCK;                          /**< SPI0_SCK, offset: 0x24080 */
       uint8_t RESERVED_126[60];
  __IO uint32_t SPI0_SDO;                          /**< SPI0_SDO, offset: 0x240C0 */
       uint8_t RESERVED_127[60];
  __IO uint32_t SPI0_SDI;                          /**< SPI0_SDI, offset: 0x24100 */
       uint8_t RESERVED_128[60];
  __IO uint32_t SPI0_CS0;                          /**< SPI0_CS0, offset: 0x24140 */
       uint8_t RESERVED_129[60];
  __IO uint32_t SPI0_CS1;                          /**< SPI0_CS1, offset: 0x24180 */
       uint8_t RESERVED_130[60];
  __IO uint32_t SPI2_SCK;                          /**< SPI2_SCK, offset: 0x241C0 */
       uint8_t RESERVED_131[60];
  __IO uint32_t SPI2_SDO;                          /**< SPI2_SDO, offset: 0x24200 */
       uint8_t RESERVED_132[60];
  __IO uint32_t SPI2_SDI;                          /**< SPI2_SDI, offset: 0x24240 */
       uint8_t RESERVED_133[60];
  __IO uint32_t SPI2_CS0;                          /**< SPI2_CS0, offset: 0x24280 */
       uint8_t RESERVED_134[60];
  __IO uint32_t SPI2_CS1;                          /**< SPI2_CS1, offset: 0x242C0 */
       uint8_t RESERVED_135[60];
  __IO uint32_t SAI1_RXC;                          /**< SAI1_RXC, offset: 0x24300 */
       uint8_t RESERVED_136[60];
  __IO uint32_t SAI1_RXD;                          /**< SAI1_RXD, offset: 0x24340 */
       uint8_t RESERVED_137[60];
  __IO uint32_t SAI1_RXFS;                         /**< SAI1_RXFS, offset: 0x24380 */
       uint8_t RESERVED_138[124];
  __I  uint32_t IOMUXD_GROUP_1_4;                  /**< na, offset: 0x24400 */
       uint8_t RESERVED_139[3068];
  __IO uint32_t SAI1_TXC;                          /**< SAI1_TXC, offset: 0x25000 */
       uint8_t RESERVED_140[60];
  __IO uint32_t SAI1_TXD;                          /**< SAI1_TXD, offset: 0x25040 */
       uint8_t RESERVED_141[60];
  __IO uint32_t SAI1_TXFS;                         /**< SAI1_TXFS, offset: 0x25080 */
       uint8_t RESERVED_142[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT, offset: 0x250C0 */
       uint8_t RESERVED_143[60];
  __IO uint32_t ADC_IN7;                           /**< ADC_IN7, offset: 0x25100 */
       uint8_t RESERVED_144[60];
  __IO uint32_t ADC_IN6;                           /**< ADC_IN6, offset: 0x25140 */
       uint8_t RESERVED_145[60];
  __IO uint32_t ADC_IN5;                           /**< ADC_IN5, offset: 0x25180 */
       uint8_t RESERVED_146[60];
  __IO uint32_t ADC_IN4;                           /**< ADC_IN4, offset: 0x251C0 */
       uint8_t RESERVED_147[60];
  __IO uint32_t ADC_IN3;                           /**< ADC_IN3, offset: 0x25200 */
       uint8_t RESERVED_148[60];
  __IO uint32_t ADC_IN2;                           /**< ADC_IN2, offset: 0x25240 */
       uint8_t RESERVED_149[60];
  __IO uint32_t ADC_IN1;                           /**< ADC_IN1, offset: 0x25280 */
       uint8_t RESERVED_150[60];
  __IO uint32_t ADC_IN0;                           /**< ADC_IN0, offset: 0x252C0 */
       uint8_t RESERVED_151[316];
  __I  uint32_t IOMUXD_GROUP_1_5;                  /**< na, offset: 0x25400 */
       uint8_t RESERVED_152[109564];
  __IO uint32_t MLB_SIG;                           /**< MLB_SIG, offset: 0x40000 */
       uint8_t RESERVED_153[60];
  __IO uint32_t MLB_CLK;                           /**< MLB_CLK, offset: 0x40040 */
       uint8_t RESERVED_154[60];
  __IO uint32_t MLB_DATA;                          /**< MLB_DATA, offset: 0x40080 */
       uint8_t RESERVED_155[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT, offset: 0x400C0 */
       uint8_t RESERVED_156[60];
  __IO uint32_t FLEXCAN0_RX;                       /**< FLEXCAN0_RX, offset: 0x40100 */
       uint8_t RESERVED_157[60];
  __IO uint32_t FLEXCAN0_TX;                       /**< FLEXCAN0_TX, offset: 0x40140 */
       uint8_t RESERVED_158[60];
  __IO uint32_t FLEXCAN1_RX;                       /**< FLEXCAN1_RX, offset: 0x40180 */
       uint8_t RESERVED_159[60];
  __IO uint32_t FLEXCAN1_TX;                       /**< FLEXCAN1_TX, offset: 0x401C0 */
       uint8_t RESERVED_160[60];
  __IO uint32_t FLEXCAN2_RX;                       /**< FLEXCAN2_RX, offset: 0x40200 */
       uint8_t RESERVED_161[60];
  __IO uint32_t FLEXCAN2_TX;                       /**< FLEXCAN2_TX, offset: 0x40240 */
       uint8_t RESERVED_162[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR, offset: 0x40280 */
       uint8_t RESERVED_163[60];
  __IO uint32_t USB_SS3_TC0;                       /**< USB_SS3_TC0, offset: 0x402C0 */
       uint8_t RESERVED_164[60];
  __IO uint32_t USB_SS3_TC1;                       /**< USB_SS3_TC1, offset: 0x40300 */
       uint8_t RESERVED_165[60];
  __IO uint32_t USB_SS3_TC2;                       /**< USB_SS3_TC2, offset: 0x40340 */
       uint8_t RESERVED_166[60];
  __IO uint32_t USB_SS3_TC3;                       /**< USB_SS3_TC3, offset: 0x40380 */
       uint8_t RESERVED_167[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_3V3_USB3IO;   /**< IOMUXD_COMP_CTL_GPIO_3V3_USB3IO, offset: 0x403C0 */
       uint8_t RESERVED_168[60];
  __I  uint32_t IOMUXD_GROUP_2_0;                  /**< na, offset: 0x40400 */
       uint8_t RESERVED_169[3068];
  __IO uint32_t USDHC1_RESET_B;                    /**< USDHC1_RESET_B, offset: 0x41000 */
       uint8_t RESERVED_170[60];
  __IO uint32_t USDHC1_VSELECT;                    /**< USDHC1_VSELECT, offset: 0x41040 */
       uint8_t RESERVED_171[60];
  __IO uint32_t USDHC2_RESET_B;                    /**< USDHC2_RESET_B, offset: 0x41080 */
       uint8_t RESERVED_172[60];
  __IO uint32_t USDHC2_VSELECT;                    /**< USDHC2_VSELECT, offset: 0x410C0 */
       uint8_t RESERVED_173[60];
  __IO uint32_t USDHC2_WP;                         /**< USDHC2_WP, offset: 0x41100 */
       uint8_t RESERVED_174[60];
  __IO uint32_t USDHC2_CD_B;                       /**< USDHC2_CD_B, offset: 0x41140 */
       uint8_t RESERVED_175[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP, offset: 0x41180 */
       uint8_t RESERVED_176[60];
  __IO uint32_t ENET0_MDIO;                        /**< ENET0_MDIO, offset: 0x411C0 */
       uint8_t RESERVED_177[60];
  __IO uint32_t ENET0_MDC;                         /**< ENET0_MDC, offset: 0x41200 */
       uint8_t RESERVED_178[60];
  __IO uint32_t ENET0_REFCLK_125M_25M;             /**< ENET0_REFCLK_125M_25M, offset: 0x41240 */
       uint8_t RESERVED_179[60];
  __IO uint32_t ENET1_REFCLK_125M_25M;             /**< ENET1_REFCLK_125M_25M, offset: 0x41280 */
       uint8_t RESERVED_180[60];
  __IO uint32_t ENET1_MDIO;                        /**< ENET1_MDIO, offset: 0x412C0 */
       uint8_t RESERVED_181[60];
  __IO uint32_t ENET1_MDC;                         /**< ENET1_MDC, offset: 0x41300 */
       uint8_t RESERVED_182[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT, offset: 0x41340 */
       uint8_t RESERVED_183[60];
  __IO uint32_t QSPI1A_SS0_B;                      /**< QSPI1A_SS0_B, offset: 0x41380 */
       uint8_t RESERVED_184[124];
  __I  uint32_t IOMUXD_GROUP_2_1;                  /**< na, offset: 0x41400 */
       uint8_t RESERVED_185[3068];
  __IO uint32_t QSPI1A_SS1_B;                      /**< QSPI1A_SS1_B, offset: 0x42000 */
       uint8_t RESERVED_186[60];
  __IO uint32_t QSPI1A_SCLK;                       /**< QSPI1A_SCLK, offset: 0x42040 */
       uint8_t RESERVED_187[60];
  __IO uint32_t QSPI1A_DQS;                        /**< QSPI1A_DQS, offset: 0x42080 */
       uint8_t RESERVED_188[60];
  __IO uint32_t QSPI1A_DATA3;                      /**< QSPI1A_DATA3, offset: 0x420C0 */
       uint8_t RESERVED_189[60];
  __IO uint32_t QSPI1A_DATA2;                      /**< QSPI1A_DATA2, offset: 0x42100 */
       uint8_t RESERVED_190[60];
  __IO uint32_t QSPI1A_DATA1;                      /**< QSPI1A_DATA1, offset: 0x42140 */
       uint8_t RESERVED_191[60];
  __IO uint32_t QSPI1A_DATA0;                      /**< QSPI1A_DATA0, offset: 0x42180 */
       uint8_t RESERVED_192[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1, offset: 0x421C0 */
       uint8_t RESERVED_193[572];
  __I  uint32_t IOMUXD_GROUP_2_2;                  /**< na, offset: 0x42400 */
       uint8_t RESERVED_194[3068];
  __IO uint32_t QSPI0A_DATA0;                      /**< QSPI0A_DATA0, offset: 0x43000 */
       uint8_t RESERVED_195[60];
  __IO uint32_t QSPI0A_DATA1;                      /**< QSPI0A_DATA1, offset: 0x43040 */
       uint8_t RESERVED_196[60];
  __IO uint32_t QSPI0A_DATA2;                      /**< QSPI0A_DATA2, offset: 0x43080 */
       uint8_t RESERVED_197[60];
  __IO uint32_t QSPI0A_DATA3;                      /**< QSPI0A_DATA3, offset: 0x430C0 */
       uint8_t RESERVED_198[60];
  __IO uint32_t QSPI0A_DQS;                        /**< QSPI0A_DQS, offset: 0x43100 */
       uint8_t RESERVED_199[60];
  __IO uint32_t QSPI0A_SS0_B;                      /**< QSPI0A_SS0_B, offset: 0x43140 */
       uint8_t RESERVED_200[60];
  __IO uint32_t QSPI0A_SS1_B;                      /**< QSPI0A_SS1_B, offset: 0x43180 */
       uint8_t RESERVED_201[60];
  __IO uint32_t QSPI0A_SCLK;                       /**< QSPI0A_SCLK, offset: 0x431C0 */
       uint8_t RESERVED_202[60];
  __IO uint32_t QSPI0B_SCLK;                       /**< QSPI0B_SCLK, offset: 0x43200 */
       uint8_t RESERVED_203[60];
  __IO uint32_t QSPI0B_DATA0;                      /**< QSPI0B_DATA0, offset: 0x43240 */
       uint8_t RESERVED_204[60];
  __IO uint32_t QSPI0B_DATA1;                      /**< QSPI0B_DATA1, offset: 0x43280 */
       uint8_t RESERVED_205[60];
  __IO uint32_t QSPI0B_DATA2;                      /**< QSPI0B_DATA2, offset: 0x432C0 */
       uint8_t RESERVED_206[60];
  __IO uint32_t QSPI0B_DATA3;                      /**< QSPI0B_DATA3, offset: 0x43300 */
       uint8_t RESERVED_207[60];
  __IO uint32_t QSPI0B_DQS;                        /**< QSPI0B_DQS, offset: 0x43340 */
       uint8_t RESERVED_208[60];
  __IO uint32_t QSPI0B_SS0_B;                      /**< QSPI0B_SS0_B, offset: 0x43380 */
       uint8_t RESERVED_209[124];
  __I  uint32_t IOMUXD_GROUP_2_3;                  /**< na, offset: 0x43400 */
       uint8_t RESERVED_210[3068];
  __IO uint32_t QSPI0B_SS1_B;                      /**< QSPI0B_SS1_B, offset: 0x44000 */
       uint8_t RESERVED_211[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0, offset: 0x44040 */
       uint8_t RESERVED_212[60];
  __IO uint32_t PCIE_CTRL0_CLKREQ_B;               /**< PCIE_CTRL0_CLKREQ_B, offset: 0x44080 */
       uint8_t RESERVED_213[60];
  __IO uint32_t PCIE_CTRL0_WAKE_B;                 /**< PCIE_CTRL0_WAKE_B, offset: 0x440C0 */
       uint8_t RESERVED_214[60];
  __IO uint32_t PCIE_CTRL0_PERST_B;                /**< PCIE_CTRL0_PERST_B, offset: 0x44100 */
       uint8_t RESERVED_215[60];
  __IO uint32_t PCIE_CTRL1_CLKREQ_B;               /**< PCIE_CTRL1_CLKREQ_B, offset: 0x44140 */
       uint8_t RESERVED_216[60];
  __IO uint32_t PCIE_CTRL1_WAKE_B;                 /**< PCIE_CTRL1_WAKE_B, offset: 0x44180 */
       uint8_t RESERVED_217[60];
  __IO uint32_t PCIE_CTRL1_PERST_B;                /**< PCIE_CTRL1_PERST_B, offset: 0x441C0 */
       uint8_t RESERVED_218[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP, offset: 0x44200 */
       uint8_t RESERVED_219[508];
  __I  uint32_t IOMUXD_GROUP_2_4;                  /**< na, offset: 0x44400 */
       uint8_t RESERVED_220[3068];
  __IO uint32_t USB_HSIC0_DATA;                    /**< USB_HSIC0_DATA, offset: 0x45000 */
       uint8_t RESERVED_221[60];
  __IO uint32_t USB_HSIC0_STROBE;                  /**< USB_HSIC0_STROBE, offset: 0x45040 */
       uint8_t RESERVED_222[60];
  __IO uint32_t IOMUXD_CALIBRATION_0_HSIC;         /**< IOMUXD_CALIBRATION_0_HSIC, offset: 0x45080 */
       uint8_t RESERVED_223[60];
  __IO uint32_t IOMUXD_CALIBRATION_1_HSIC;         /**< IOMUXD_CALIBRATION_1_HSIC, offset: 0x450C0 */
       uint8_t RESERVED_224[828];
  __I  uint32_t IOMUXD_GROUP_2_5;                  /**< na, offset: 0x45400 */
       uint8_t RESERVED_225[109564];
  __IO uint32_t EMMC0_CLK;                         /**< EMMC0_CLK, offset: 0x60000 */
       uint8_t RESERVED_226[60];
  __IO uint32_t EMMC0_CMD;                         /**< EMMC0_CMD, offset: 0x60040 */
       uint8_t RESERVED_227[60];
  __IO uint32_t EMMC0_DATA0;                       /**< EMMC0_DATA0, offset: 0x60080 */
       uint8_t RESERVED_228[60];
  __IO uint32_t EMMC0_DATA1;                       /**< EMMC0_DATA1, offset: 0x600C0 */
       uint8_t RESERVED_229[60];
  __IO uint32_t EMMC0_DATA2;                       /**< EMMC0_DATA2, offset: 0x60100 */
       uint8_t RESERVED_230[60];
  __IO uint32_t EMMC0_DATA3;                       /**< EMMC0_DATA3, offset: 0x60140 */
       uint8_t RESERVED_231[60];
  __IO uint32_t EMMC0_DATA4;                       /**< EMMC0_DATA4, offset: 0x60180 */
       uint8_t RESERVED_232[60];
  __IO uint32_t EMMC0_DATA5;                       /**< EMMC0_DATA5, offset: 0x601C0 */
       uint8_t RESERVED_233[60];
  __IO uint32_t EMMC0_DATA6;                       /**< EMMC0_DATA6, offset: 0x60200 */
       uint8_t RESERVED_234[60];
  __IO uint32_t EMMC0_DATA7;                       /**< EMMC0_DATA7, offset: 0x60240 */
       uint8_t RESERVED_235[60];
  __IO uint32_t EMMC0_STROBE;                      /**< EMMC0_STROBE, offset: 0x60280 */
       uint8_t RESERVED_236[60];
  __IO uint32_t EMMC0_RESET_B;                     /**< EMMC0_RESET_B, offset: 0x602C0 */
       uint8_t RESERVED_237[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX, offset: 0x60300 */
       uint8_t RESERVED_238[60];
  __IO uint32_t USDHC1_CLK;                        /**< USDHC1_CLK, offset: 0x60340 */
       uint8_t RESERVED_239[60];
  __IO uint32_t USDHC1_CMD;                        /**< USDHC1_CMD, offset: 0x60380 */
       uint8_t RESERVED_240[60];
  __IO uint32_t USDHC1_DATA0;                      /**< USDHC1_DATA0, offset: 0x603C0 */
       uint8_t RESERVED_241[60];
  __I  uint32_t IOMUXD_GROUP_3_0;                  /**< na, offset: 0x60400 */
       uint8_t RESERVED_242[3068];
  __IO uint32_t USDHC1_DATA1;                      /**< USDHC1_DATA1, offset: 0x61000 */
       uint8_t RESERVED_243[60];
  __IO uint32_t IOMUXD_CTL_NAND_RE_P_N;            /**< IOMUXD_CTL_NAND_RE_P_N, offset: 0x61040 */
       uint8_t RESERVED_244[60];
  __IO uint32_t USDHC1_DATA2;                      /**< USDHC1_DATA2, offset: 0x61080 */
       uint8_t RESERVED_245[60];
  __IO uint32_t USDHC1_DATA3;                      /**< USDHC1_DATA3, offset: 0x610C0 */
       uint8_t RESERVED_246[60];
  __IO uint32_t IOMUXD_CTL_NAND_DQS_P_N;           /**< IOMUXD_CTL_NAND_DQS_P_N, offset: 0x61100 */
       uint8_t RESERVED_247[60];
  __IO uint32_t USDHC1_DATA4;                      /**< USDHC1_DATA4, offset: 0x61140 */
       uint8_t RESERVED_248[60];
  __IO uint32_t USDHC1_DATA5;                      /**< USDHC1_DATA5, offset: 0x61180 */
       uint8_t RESERVED_249[60];
  __IO uint32_t USDHC1_DATA6;                      /**< USDHC1_DATA6, offset: 0x611C0 */
       uint8_t RESERVED_250[60];
  __IO uint32_t USDHC1_DATA7;                      /**< USDHC1_DATA7, offset: 0x61200 */
       uint8_t RESERVED_251[60];
  __IO uint32_t USDHC1_STROBE;                     /**< USDHC1_STROBE, offset: 0x61240 */
       uint8_t RESERVED_252[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2, offset: 0x61280 */
       uint8_t RESERVED_253[60];
  __IO uint32_t USDHC2_CLK;                        /**< USDHC2_CLK, offset: 0x612C0 */
       uint8_t RESERVED_254[60];
  __IO uint32_t USDHC2_CMD;                        /**< USDHC2_CMD, offset: 0x61300 */
       uint8_t RESERVED_255[60];
  __IO uint32_t USDHC2_DATA0;                      /**< USDHC2_DATA0, offset: 0x61340 */
       uint8_t RESERVED_256[60];
  __IO uint32_t USDHC2_DATA1;                      /**< USDHC2_DATA1, offset: 0x61380 */
       uint8_t RESERVED_257[60];
  __IO uint32_t USDHC2_DATA2;                      /**< USDHC2_DATA2, offset: 0x613C0 */
       uint8_t RESERVED_258[60];
  __I  uint32_t IOMUXD_GROUP_3_1;                  /**< na, offset: 0x61400 */
       uint8_t RESERVED_259[3068];
  __IO uint32_t USDHC2_DATA3;                      /**< USDHC2_DATA3, offset: 0x62000 */
       uint8_t RESERVED_260[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3, offset: 0x62040 */
       uint8_t RESERVED_261[60];
  __IO uint32_t ENET0_RGMII_TXC;                   /**< ENET0_RGMII_TXC, offset: 0x62080 */
       uint8_t RESERVED_262[60];
  __IO uint32_t ENET0_RGMII_TX_CTL;                /**< ENET0_RGMII_TX_CTL, offset: 0x620C0 */
       uint8_t RESERVED_263[60];
  __IO uint32_t ENET0_RGMII_TXD0;                  /**< ENET0_RGMII_TXD0, offset: 0x62100 */
       uint8_t RESERVED_264[60];
  __IO uint32_t ENET0_RGMII_TXD1;                  /**< ENET0_RGMII_TXD1, offset: 0x62140 */
       uint8_t RESERVED_265[60];
  __IO uint32_t ENET0_RGMII_TXD2;                  /**< ENET0_RGMII_TXD2, offset: 0x62180 */
       uint8_t RESERVED_266[60];
  __IO uint32_t ENET0_RGMII_TXD3;                  /**< ENET0_RGMII_TXD3, offset: 0x621C0 */
       uint8_t RESERVED_267[60];
  __IO uint32_t ENET0_RGMII_RXC;                   /**< ENET0_RGMII_RXC, offset: 0x62200 */
       uint8_t RESERVED_268[60];
  __IO uint32_t ENET0_RGMII_RX_CTL;                /**< ENET0_RGMII_RX_CTL, offset: 0x62240 */
       uint8_t RESERVED_269[60];
  __IO uint32_t ENET0_RGMII_RXD0;                  /**< ENET0_RGMII_RXD0, offset: 0x62280 */
       uint8_t RESERVED_270[60];
  __IO uint32_t ENET0_RGMII_RXD1;                  /**< ENET0_RGMII_RXD1, offset: 0x622C0 */
       uint8_t RESERVED_271[60];
  __IO uint32_t ENET0_RGMII_RXD2;                  /**< ENET0_RGMII_RXD2, offset: 0x62300 */
       uint8_t RESERVED_272[60];
  __IO uint32_t ENET0_RGMII_RXD3;                  /**< ENET0_RGMII_RXD3, offset: 0x62340 */
       uint8_t RESERVED_273[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB, offset: 0x62380 */
       uint8_t RESERVED_274[60];
  __IO uint32_t ENET1_RGMII_TXC;                   /**< ENET1_RGMII_TXC, offset: 0x623C0 */
       uint8_t RESERVED_275[60];
  __I  uint32_t IOMUXD_GROUP_3_2;                  /**< na, offset: 0x62400 */
       uint8_t RESERVED_276[3068];
  __IO uint32_t ENET1_RGMII_TX_CTL;                /**< ENET1_RGMII_TX_CTL, offset: 0x63000 */
       uint8_t RESERVED_277[60];
  __IO uint32_t ENET1_RGMII_TXD0;                  /**< ENET1_RGMII_TXD0, offset: 0x63040 */
       uint8_t RESERVED_278[60];
  __IO uint32_t ENET1_RGMII_TXD1;                  /**< ENET1_RGMII_TXD1, offset: 0x63080 */
       uint8_t RESERVED_279[60];
  __IO uint32_t ENET1_RGMII_TXD2;                  /**< ENET1_RGMII_TXD2, offset: 0x630C0 */
       uint8_t RESERVED_280[60];
  __IO uint32_t ENET1_RGMII_TXD3;                  /**< ENET1_RGMII_TXD3, offset: 0x63100 */
       uint8_t RESERVED_281[60];
  __IO uint32_t ENET1_RGMII_RXC;                   /**< ENET1_RGMII_RXC, offset: 0x63140 */
       uint8_t RESERVED_282[60];
  __IO uint32_t ENET1_RGMII_RX_CTL;                /**< ENET1_RGMII_RX_CTL, offset: 0x63180 */
       uint8_t RESERVED_283[60];
  __IO uint32_t ENET1_RGMII_RXD0;                  /**< ENET1_RGMII_RXD0, offset: 0x631C0 */
       uint8_t RESERVED_284[60];
  __IO uint32_t ENET1_RGMII_RXD1;                  /**< ENET1_RGMII_RXD1, offset: 0x63200 */
       uint8_t RESERVED_285[60];
  __IO uint32_t ENET1_RGMII_RXD2;                  /**< ENET1_RGMII_RXD2, offset: 0x63240 */
       uint8_t RESERVED_286[60];
  __IO uint32_t ENET1_RGMII_RXD3;                  /**< ENET1_RGMII_RXD3, offset: 0x63280 */
       uint8_t RESERVED_287[60];
  __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA, offset: 0x632C0 */
       uint8_t RESERVED_288[316];
  __I  uint32_t IOMUXD_GROUP_3_3;                  /**< na, offset: 0x63400 */
} IOMUXD_Type;

/* ----------------------------------------------------------------------------
   -- IOMUXD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOMUXD_Register_Masks IOMUXD Register Masks
 * @{
 */

/*! @name SIM0_CLK - SIM0_CLK */
/*! @{ */
#define IOMUXD_SIM0_CLK_PDRV_MASK                (0x1U)
#define IOMUXD_SIM0_CLK_PDRV_SHIFT               (0U)
#define IOMUXD_SIM0_CLK_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_CLK_PDRV_SHIFT)) & IOMUXD_SIM0_CLK_PDRV_MASK)
#define IOMUXD_SIM0_CLK_SIM0_CLK_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SIM0_CLK_SIM0_CLK_reserved_1_4_SHIFT (1U)
#define IOMUXD_SIM0_CLK_SIM0_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_CLK_SIM0_CLK_reserved_1_4_SHIFT)) & IOMUXD_SIM0_CLK_SIM0_CLK_reserved_1_4_MASK)
#define IOMUXD_SIM0_CLK_PULL_MASK                (0x60U)
#define IOMUXD_SIM0_CLK_PULL_SHIFT               (5U)
#define IOMUXD_SIM0_CLK_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_CLK_PULL_SHIFT)) & IOMUXD_SIM0_CLK_PULL_MASK)
#define IOMUXD_SIM0_CLK_SIM0_CLK_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SIM0_CLK_SIM0_CLK_reserved_7_18_SHIFT (7U)
#define IOMUXD_SIM0_CLK_SIM0_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_CLK_SIM0_CLK_reserved_7_18_SHIFT)) & IOMUXD_SIM0_CLK_SIM0_CLK_reserved_7_18_MASK)
#define IOMUXD_SIM0_CLK_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SIM0_CLK_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SIM0_CLK_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SIM0_CLK_WAKEUP_CTRL_MASK)
#define IOMUXD_SIM0_CLK_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SIM0_CLK_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SIM0_CLK_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_SIM0_CLK_WAKEUP_MASK_MASK)
#define IOMUXD_SIM0_CLK_lp_config_MASK           (0x1800000U)
#define IOMUXD_SIM0_CLK_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SIM0_CLK_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_CLK_lp_config_SHIFT)) & IOMUXD_SIM0_CLK_lp_config_MASK)
#define IOMUXD_SIM0_CLK_sw_config_MASK           (0x6000000U)
#define IOMUXD_SIM0_CLK_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SIM0_CLK_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_CLK_sw_config_SHIFT)) & IOMUXD_SIM0_CLK_sw_config_MASK)
#define IOMUXD_SIM0_CLK_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SIM0_CLK_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SIM0.CLK
 *  0b011..LSIO.GPIO0.IO00
 */
#define IOMUXD_SIM0_CLK_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_CLK_mux_mode_SHIFT)) & IOMUXD_SIM0_CLK_mux_mode_MASK)
#define IOMUXD_SIM0_CLK_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SIM0_CLK_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SIM0_CLK_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_CLK_update_pad_ctl_SHIFT)) & IOMUXD_SIM0_CLK_update_pad_ctl_MASK)
#define IOMUXD_SIM0_CLK_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SIM0_CLK_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SIM0_CLK_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_CLK_update_mux_mode_SHIFT)) & IOMUXD_SIM0_CLK_update_mux_mode_MASK)
/*! @} */

/*! @name SIM0_RST - SIM0_RST */
/*! @{ */
#define IOMUXD_SIM0_RST_PDRV_MASK                (0x1U)
#define IOMUXD_SIM0_RST_PDRV_SHIFT               (0U)
#define IOMUXD_SIM0_RST_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_RST_PDRV_SHIFT)) & IOMUXD_SIM0_RST_PDRV_MASK)
#define IOMUXD_SIM0_RST_SIM0_RST_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SIM0_RST_SIM0_RST_reserved_1_4_SHIFT (1U)
#define IOMUXD_SIM0_RST_SIM0_RST_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_RST_SIM0_RST_reserved_1_4_SHIFT)) & IOMUXD_SIM0_RST_SIM0_RST_reserved_1_4_MASK)
#define IOMUXD_SIM0_RST_PULL_MASK                (0x60U)
#define IOMUXD_SIM0_RST_PULL_SHIFT               (5U)
#define IOMUXD_SIM0_RST_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_RST_PULL_SHIFT)) & IOMUXD_SIM0_RST_PULL_MASK)
#define IOMUXD_SIM0_RST_SIM0_RST_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SIM0_RST_SIM0_RST_reserved_7_18_SHIFT (7U)
#define IOMUXD_SIM0_RST_SIM0_RST_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_RST_SIM0_RST_reserved_7_18_SHIFT)) & IOMUXD_SIM0_RST_SIM0_RST_reserved_7_18_MASK)
#define IOMUXD_SIM0_RST_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SIM0_RST_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SIM0_RST_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_RST_WAKEUP_CTRL_SHIFT)) & IOMUXD_SIM0_RST_WAKEUP_CTRL_MASK)
#define IOMUXD_SIM0_RST_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SIM0_RST_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SIM0_RST_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_RST_WAKEUP_MASK_SHIFT)) & IOMUXD_SIM0_RST_WAKEUP_MASK_MASK)
#define IOMUXD_SIM0_RST_lp_config_MASK           (0x1800000U)
#define IOMUXD_SIM0_RST_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SIM0_RST_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_RST_lp_config_SHIFT)) & IOMUXD_SIM0_RST_lp_config_MASK)
#define IOMUXD_SIM0_RST_sw_config_MASK           (0x6000000U)
#define IOMUXD_SIM0_RST_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SIM0_RST_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_RST_sw_config_SHIFT)) & IOMUXD_SIM0_RST_sw_config_MASK)
#define IOMUXD_SIM0_RST_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SIM0_RST_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SIM0.RST
 *  0b011..LSIO.GPIO0.IO01
 */
#define IOMUXD_SIM0_RST_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_RST_mux_mode_SHIFT)) & IOMUXD_SIM0_RST_mux_mode_MASK)
#define IOMUXD_SIM0_RST_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SIM0_RST_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SIM0_RST_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_RST_update_pad_ctl_SHIFT)) & IOMUXD_SIM0_RST_update_pad_ctl_MASK)
#define IOMUXD_SIM0_RST_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SIM0_RST_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SIM0_RST_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_RST_update_mux_mode_SHIFT)) & IOMUXD_SIM0_RST_update_mux_mode_MASK)
/*! @} */

/*! @name SIM0_IO - SIM0_IO */
/*! @{ */
#define IOMUXD_SIM0_IO_PDRV_MASK                 (0x1U)
#define IOMUXD_SIM0_IO_PDRV_SHIFT                (0U)
#define IOMUXD_SIM0_IO_PDRV(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_IO_PDRV_SHIFT)) & IOMUXD_SIM0_IO_PDRV_MASK)
#define IOMUXD_SIM0_IO_SIM0_IO_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SIM0_IO_SIM0_IO_reserved_1_4_SHIFT (1U)
#define IOMUXD_SIM0_IO_SIM0_IO_reserved_1_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_IO_SIM0_IO_reserved_1_4_SHIFT)) & IOMUXD_SIM0_IO_SIM0_IO_reserved_1_4_MASK)
#define IOMUXD_SIM0_IO_PULL_MASK                 (0x60U)
#define IOMUXD_SIM0_IO_PULL_SHIFT                (5U)
#define IOMUXD_SIM0_IO_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_IO_PULL_SHIFT)) & IOMUXD_SIM0_IO_PULL_MASK)
#define IOMUXD_SIM0_IO_SIM0_IO_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SIM0_IO_SIM0_IO_reserved_7_18_SHIFT (7U)
#define IOMUXD_SIM0_IO_SIM0_IO_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_IO_SIM0_IO_reserved_7_18_SHIFT)) & IOMUXD_SIM0_IO_SIM0_IO_reserved_7_18_MASK)
#define IOMUXD_SIM0_IO_WAKEUP_CTRL_MASK          (0x380000U)
#define IOMUXD_SIM0_IO_WAKEUP_CTRL_SHIFT         (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SIM0_IO_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_IO_WAKEUP_CTRL_SHIFT)) & IOMUXD_SIM0_IO_WAKEUP_CTRL_MASK)
#define IOMUXD_SIM0_IO_WAKEUP_MASK_MASK          (0x400000U)
#define IOMUXD_SIM0_IO_WAKEUP_MASK_SHIFT         (22U)
#define IOMUXD_SIM0_IO_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_IO_WAKEUP_MASK_SHIFT)) & IOMUXD_SIM0_IO_WAKEUP_MASK_MASK)
#define IOMUXD_SIM0_IO_lp_config_MASK            (0x1800000U)
#define IOMUXD_SIM0_IO_lp_config_SHIFT           (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SIM0_IO_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_IO_lp_config_SHIFT)) & IOMUXD_SIM0_IO_lp_config_MASK)
#define IOMUXD_SIM0_IO_sw_config_MASK            (0x6000000U)
#define IOMUXD_SIM0_IO_sw_config_SHIFT           (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SIM0_IO_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_IO_sw_config_SHIFT)) & IOMUXD_SIM0_IO_sw_config_MASK)
#define IOMUXD_SIM0_IO_mux_mode_MASK             (0x38000000U)
#define IOMUXD_SIM0_IO_mux_mode_SHIFT            (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SIM0.IO
 *  0b011..LSIO.GPIO0.IO02
 */
#define IOMUXD_SIM0_IO_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_IO_mux_mode_SHIFT)) & IOMUXD_SIM0_IO_mux_mode_MASK)
#define IOMUXD_SIM0_IO_update_pad_ctl_MASK       (0x40000000U)
#define IOMUXD_SIM0_IO_update_pad_ctl_SHIFT      (30U)
#define IOMUXD_SIM0_IO_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_IO_update_pad_ctl_SHIFT)) & IOMUXD_SIM0_IO_update_pad_ctl_MASK)
#define IOMUXD_SIM0_IO_update_mux_mode_MASK      (0x80000000U)
#define IOMUXD_SIM0_IO_update_mux_mode_SHIFT     (31U)
#define IOMUXD_SIM0_IO_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_IO_update_mux_mode_SHIFT)) & IOMUXD_SIM0_IO_update_mux_mode_MASK)
/*! @} */

/*! @name SIM0_PD - SIM0_PD */
/*! @{ */
#define IOMUXD_SIM0_PD_PDRV_MASK                 (0x1U)
#define IOMUXD_SIM0_PD_PDRV_SHIFT                (0U)
#define IOMUXD_SIM0_PD_PDRV(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_PD_PDRV_SHIFT)) & IOMUXD_SIM0_PD_PDRV_MASK)
#define IOMUXD_SIM0_PD_SIM0_PD_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SIM0_PD_SIM0_PD_reserved_1_4_SHIFT (1U)
#define IOMUXD_SIM0_PD_SIM0_PD_reserved_1_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_PD_SIM0_PD_reserved_1_4_SHIFT)) & IOMUXD_SIM0_PD_SIM0_PD_reserved_1_4_MASK)
#define IOMUXD_SIM0_PD_PULL_MASK                 (0x60U)
#define IOMUXD_SIM0_PD_PULL_SHIFT                (5U)
#define IOMUXD_SIM0_PD_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_PD_PULL_SHIFT)) & IOMUXD_SIM0_PD_PULL_MASK)
#define IOMUXD_SIM0_PD_SIM0_PD_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SIM0_PD_SIM0_PD_reserved_7_18_SHIFT (7U)
#define IOMUXD_SIM0_PD_SIM0_PD_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_PD_SIM0_PD_reserved_7_18_SHIFT)) & IOMUXD_SIM0_PD_SIM0_PD_reserved_7_18_MASK)
#define IOMUXD_SIM0_PD_WAKEUP_CTRL_MASK          (0x380000U)
#define IOMUXD_SIM0_PD_WAKEUP_CTRL_SHIFT         (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SIM0_PD_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_PD_WAKEUP_CTRL_SHIFT)) & IOMUXD_SIM0_PD_WAKEUP_CTRL_MASK)
#define IOMUXD_SIM0_PD_WAKEUP_MASK_MASK          (0x400000U)
#define IOMUXD_SIM0_PD_WAKEUP_MASK_SHIFT         (22U)
#define IOMUXD_SIM0_PD_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_PD_WAKEUP_MASK_SHIFT)) & IOMUXD_SIM0_PD_WAKEUP_MASK_MASK)
#define IOMUXD_SIM0_PD_lp_config_MASK            (0x1800000U)
#define IOMUXD_SIM0_PD_lp_config_SHIFT           (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SIM0_PD_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_PD_lp_config_SHIFT)) & IOMUXD_SIM0_PD_lp_config_MASK)
#define IOMUXD_SIM0_PD_sw_config_MASK            (0x6000000U)
#define IOMUXD_SIM0_PD_sw_config_SHIFT           (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SIM0_PD_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_PD_sw_config_SHIFT)) & IOMUXD_SIM0_PD_sw_config_MASK)
#define IOMUXD_SIM0_PD_mux_mode_MASK             (0x38000000U)
#define IOMUXD_SIM0_PD_mux_mode_SHIFT            (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SIM0.PD
 *  0b001..DMA.I2C3.SCL
 *  0b011..LSIO.GPIO0.IO03
 */
#define IOMUXD_SIM0_PD_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_PD_mux_mode_SHIFT)) & IOMUXD_SIM0_PD_mux_mode_MASK)
#define IOMUXD_SIM0_PD_update_pad_ctl_MASK       (0x40000000U)
#define IOMUXD_SIM0_PD_update_pad_ctl_SHIFT      (30U)
#define IOMUXD_SIM0_PD_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_PD_update_pad_ctl_SHIFT)) & IOMUXD_SIM0_PD_update_pad_ctl_MASK)
#define IOMUXD_SIM0_PD_update_mux_mode_MASK      (0x80000000U)
#define IOMUXD_SIM0_PD_update_mux_mode_SHIFT     (31U)
#define IOMUXD_SIM0_PD_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_PD_update_mux_mode_SHIFT)) & IOMUXD_SIM0_PD_update_mux_mode_MASK)
/*! @} */

/*! @name SIM0_POWER_EN - SIM0_POWER_EN */
/*! @{ */
#define IOMUXD_SIM0_POWER_EN_PDRV_MASK           (0x1U)
#define IOMUXD_SIM0_POWER_EN_PDRV_SHIFT          (0U)
#define IOMUXD_SIM0_POWER_EN_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_POWER_EN_PDRV_SHIFT)) & IOMUXD_SIM0_POWER_EN_PDRV_MASK)
#define IOMUXD_SIM0_POWER_EN_SIM0_POWER_EN_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SIM0_POWER_EN_SIM0_POWER_EN_reserved_1_4_SHIFT (1U)
#define IOMUXD_SIM0_POWER_EN_SIM0_POWER_EN_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_POWER_EN_SIM0_POWER_EN_reserved_1_4_SHIFT)) & IOMUXD_SIM0_POWER_EN_SIM0_POWER_EN_reserved_1_4_MASK)
#define IOMUXD_SIM0_POWER_EN_PULL_MASK           (0x60U)
#define IOMUXD_SIM0_POWER_EN_PULL_SHIFT          (5U)
#define IOMUXD_SIM0_POWER_EN_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_POWER_EN_PULL_SHIFT)) & IOMUXD_SIM0_POWER_EN_PULL_MASK)
#define IOMUXD_SIM0_POWER_EN_SIM0_POWER_EN_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SIM0_POWER_EN_SIM0_POWER_EN_reserved_7_18_SHIFT (7U)
#define IOMUXD_SIM0_POWER_EN_SIM0_POWER_EN_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_POWER_EN_SIM0_POWER_EN_reserved_7_18_SHIFT)) & IOMUXD_SIM0_POWER_EN_SIM0_POWER_EN_reserved_7_18_MASK)
#define IOMUXD_SIM0_POWER_EN_WAKEUP_CTRL_MASK    (0x380000U)
#define IOMUXD_SIM0_POWER_EN_WAKEUP_CTRL_SHIFT   (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SIM0_POWER_EN_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_POWER_EN_WAKEUP_CTRL_SHIFT)) & IOMUXD_SIM0_POWER_EN_WAKEUP_CTRL_MASK)
#define IOMUXD_SIM0_POWER_EN_WAKEUP_MASK_MASK    (0x400000U)
#define IOMUXD_SIM0_POWER_EN_WAKEUP_MASK_SHIFT   (22U)
#define IOMUXD_SIM0_POWER_EN_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_POWER_EN_WAKEUP_MASK_SHIFT)) & IOMUXD_SIM0_POWER_EN_WAKEUP_MASK_MASK)
#define IOMUXD_SIM0_POWER_EN_lp_config_MASK      (0x1800000U)
#define IOMUXD_SIM0_POWER_EN_lp_config_SHIFT     (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SIM0_POWER_EN_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_POWER_EN_lp_config_SHIFT)) & IOMUXD_SIM0_POWER_EN_lp_config_MASK)
#define IOMUXD_SIM0_POWER_EN_sw_config_MASK      (0x6000000U)
#define IOMUXD_SIM0_POWER_EN_sw_config_SHIFT     (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SIM0_POWER_EN_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_POWER_EN_sw_config_SHIFT)) & IOMUXD_SIM0_POWER_EN_sw_config_MASK)
#define IOMUXD_SIM0_POWER_EN_mux_mode_MASK       (0x38000000U)
#define IOMUXD_SIM0_POWER_EN_mux_mode_SHIFT      (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SIM0.POWER_EN
 *  0b001..DMA.I2C3.SDA
 *  0b011..LSIO.GPIO0.IO04
 */
#define IOMUXD_SIM0_POWER_EN_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_POWER_EN_mux_mode_SHIFT)) & IOMUXD_SIM0_POWER_EN_mux_mode_MASK)
#define IOMUXD_SIM0_POWER_EN_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_SIM0_POWER_EN_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SIM0_POWER_EN_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_POWER_EN_update_pad_ctl_SHIFT)) & IOMUXD_SIM0_POWER_EN_update_pad_ctl_MASK)
#define IOMUXD_SIM0_POWER_EN_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SIM0_POWER_EN_update_mux_mode_SHIFT (31U)
#define IOMUXD_SIM0_POWER_EN_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_POWER_EN_update_mux_mode_SHIFT)) & IOMUXD_SIM0_POWER_EN_update_mux_mode_MASK)
/*! @} */

/*! @name SIM0_GPIO0_00 - SIM0_GPIO0_00 */
/*! @{ */
#define IOMUXD_SIM0_GPIO0_00_PDRV_MASK           (0x1U)
#define IOMUXD_SIM0_GPIO0_00_PDRV_SHIFT          (0U)
#define IOMUXD_SIM0_GPIO0_00_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_GPIO0_00_PDRV_SHIFT)) & IOMUXD_SIM0_GPIO0_00_PDRV_MASK)
#define IOMUXD_SIM0_GPIO0_00_SIM0_GPIO0_00_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SIM0_GPIO0_00_SIM0_GPIO0_00_reserved_1_4_SHIFT (1U)
#define IOMUXD_SIM0_GPIO0_00_SIM0_GPIO0_00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_GPIO0_00_SIM0_GPIO0_00_reserved_1_4_SHIFT)) & IOMUXD_SIM0_GPIO0_00_SIM0_GPIO0_00_reserved_1_4_MASK)
#define IOMUXD_SIM0_GPIO0_00_PULL_MASK           (0x60U)
#define IOMUXD_SIM0_GPIO0_00_PULL_SHIFT          (5U)
#define IOMUXD_SIM0_GPIO0_00_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_GPIO0_00_PULL_SHIFT)) & IOMUXD_SIM0_GPIO0_00_PULL_MASK)
#define IOMUXD_SIM0_GPIO0_00_SIM0_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SIM0_GPIO0_00_SIM0_GPIO0_00_reserved_7_18_SHIFT (7U)
#define IOMUXD_SIM0_GPIO0_00_SIM0_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_GPIO0_00_SIM0_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_SIM0_GPIO0_00_SIM0_GPIO0_00_reserved_7_18_MASK)
#define IOMUXD_SIM0_GPIO0_00_WAKEUP_CTRL_MASK    (0x380000U)
#define IOMUXD_SIM0_GPIO0_00_WAKEUP_CTRL_SHIFT   (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SIM0_GPIO0_00_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_SIM0_GPIO0_00_WAKEUP_CTRL_MASK)
#define IOMUXD_SIM0_GPIO0_00_WAKEUP_MASK_MASK    (0x400000U)
#define IOMUXD_SIM0_GPIO0_00_WAKEUP_MASK_SHIFT   (22U)
#define IOMUXD_SIM0_GPIO0_00_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_SIM0_GPIO0_00_WAKEUP_MASK_MASK)
#define IOMUXD_SIM0_GPIO0_00_lp_config_MASK      (0x1800000U)
#define IOMUXD_SIM0_GPIO0_00_lp_config_SHIFT     (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SIM0_GPIO0_00_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_GPIO0_00_lp_config_SHIFT)) & IOMUXD_SIM0_GPIO0_00_lp_config_MASK)
#define IOMUXD_SIM0_GPIO0_00_sw_config_MASK      (0x6000000U)
#define IOMUXD_SIM0_GPIO0_00_sw_config_SHIFT     (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SIM0_GPIO0_00_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_GPIO0_00_sw_config_SHIFT)) & IOMUXD_SIM0_GPIO0_00_sw_config_MASK)
#define IOMUXD_SIM0_GPIO0_00_mux_mode_MASK       (0x38000000U)
#define IOMUXD_SIM0_GPIO0_00_mux_mode_SHIFT      (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SIM0.POWER_EN
 *  0b011..LSIO.GPIO0.IO05
 */
#define IOMUXD_SIM0_GPIO0_00_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_SIM0_GPIO0_00_mux_mode_MASK)
#define IOMUXD_SIM0_GPIO0_00_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_SIM0_GPIO0_00_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SIM0_GPIO0_00_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_SIM0_GPIO0_00_update_pad_ctl_MASK)
#define IOMUXD_SIM0_GPIO0_00_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SIM0_GPIO0_00_update_mux_mode_SHIFT (31U)
#define IOMUXD_SIM0_GPIO0_00_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SIM0_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_SIM0_GPIO0_00_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM - IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM_update_mux_mode_MASK)
/*! @} */

/*! @name M40_I2C0_SCL - M40_I2C0_SCL */
/*! @{ */
#define IOMUXD_M40_I2C0_SCL_PDRV_MASK            (0x1U)
#define IOMUXD_M40_I2C0_SCL_PDRV_SHIFT           (0U)
#define IOMUXD_M40_I2C0_SCL_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SCL_PDRV_SHIFT)) & IOMUXD_M40_I2C0_SCL_PDRV_MASK)
#define IOMUXD_M40_I2C0_SCL_M40_I2C0_SCL_reserved_1_4_MASK (0x1EU)
#define IOMUXD_M40_I2C0_SCL_M40_I2C0_SCL_reserved_1_4_SHIFT (1U)
#define IOMUXD_M40_I2C0_SCL_M40_I2C0_SCL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SCL_M40_I2C0_SCL_reserved_1_4_SHIFT)) & IOMUXD_M40_I2C0_SCL_M40_I2C0_SCL_reserved_1_4_MASK)
#define IOMUXD_M40_I2C0_SCL_PULL_MASK            (0x60U)
#define IOMUXD_M40_I2C0_SCL_PULL_SHIFT           (5U)
#define IOMUXD_M40_I2C0_SCL_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SCL_PULL_SHIFT)) & IOMUXD_M40_I2C0_SCL_PULL_MASK)
#define IOMUXD_M40_I2C0_SCL_M40_I2C0_SCL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_M40_I2C0_SCL_M40_I2C0_SCL_reserved_7_18_SHIFT (7U)
#define IOMUXD_M40_I2C0_SCL_M40_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SCL_M40_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_M40_I2C0_SCL_M40_I2C0_SCL_reserved_7_18_MASK)
#define IOMUXD_M40_I2C0_SCL_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_M40_I2C0_SCL_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_M40_I2C0_SCL_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_M40_I2C0_SCL_WAKEUP_CTRL_MASK)
#define IOMUXD_M40_I2C0_SCL_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_M40_I2C0_SCL_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_M40_I2C0_SCL_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_M40_I2C0_SCL_WAKEUP_MASK_MASK)
#define IOMUXD_M40_I2C0_SCL_lp_config_MASK       (0x1800000U)
#define IOMUXD_M40_I2C0_SCL_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_M40_I2C0_SCL_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_M40_I2C0_SCL_lp_config_MASK)
#define IOMUXD_M40_I2C0_SCL_sw_config_MASK       (0x6000000U)
#define IOMUXD_M40_I2C0_SCL_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_M40_I2C0_SCL_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_M40_I2C0_SCL_sw_config_MASK)
#define IOMUXD_M40_I2C0_SCL_mux_mode_MASK        (0x38000000U)
#define IOMUXD_M40_I2C0_SCL_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..M40.I2C0.SCL
 *  0b001..M40.UART0.RX
 *  0b010..M40.GPIO0.IO02
 *  0b011..LSIO.GPIO0.IO06
 */
#define IOMUXD_M40_I2C0_SCL_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_M40_I2C0_SCL_mux_mode_MASK)
#define IOMUXD_M40_I2C0_SCL_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_M40_I2C0_SCL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_M40_I2C0_SCL_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_M40_I2C0_SCL_update_pad_ctl_MASK)
#define IOMUXD_M40_I2C0_SCL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_M40_I2C0_SCL_update_mux_mode_SHIFT (31U)
#define IOMUXD_M40_I2C0_SCL_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_M40_I2C0_SCL_update_mux_mode_MASK)
/*! @} */

/*! @name M40_I2C0_SDA - M40_I2C0_SDA */
/*! @{ */
#define IOMUXD_M40_I2C0_SDA_PDRV_MASK            (0x1U)
#define IOMUXD_M40_I2C0_SDA_PDRV_SHIFT           (0U)
#define IOMUXD_M40_I2C0_SDA_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SDA_PDRV_SHIFT)) & IOMUXD_M40_I2C0_SDA_PDRV_MASK)
#define IOMUXD_M40_I2C0_SDA_M40_I2C0_SDA_reserved_1_4_MASK (0x1EU)
#define IOMUXD_M40_I2C0_SDA_M40_I2C0_SDA_reserved_1_4_SHIFT (1U)
#define IOMUXD_M40_I2C0_SDA_M40_I2C0_SDA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SDA_M40_I2C0_SDA_reserved_1_4_SHIFT)) & IOMUXD_M40_I2C0_SDA_M40_I2C0_SDA_reserved_1_4_MASK)
#define IOMUXD_M40_I2C0_SDA_PULL_MASK            (0x60U)
#define IOMUXD_M40_I2C0_SDA_PULL_SHIFT           (5U)
#define IOMUXD_M40_I2C0_SDA_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SDA_PULL_SHIFT)) & IOMUXD_M40_I2C0_SDA_PULL_MASK)
#define IOMUXD_M40_I2C0_SDA_M40_I2C0_SDA_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_M40_I2C0_SDA_M40_I2C0_SDA_reserved_7_18_SHIFT (7U)
#define IOMUXD_M40_I2C0_SDA_M40_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SDA_M40_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_M40_I2C0_SDA_M40_I2C0_SDA_reserved_7_18_MASK)
#define IOMUXD_M40_I2C0_SDA_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_M40_I2C0_SDA_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_M40_I2C0_SDA_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_M40_I2C0_SDA_WAKEUP_CTRL_MASK)
#define IOMUXD_M40_I2C0_SDA_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_M40_I2C0_SDA_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_M40_I2C0_SDA_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_M40_I2C0_SDA_WAKEUP_MASK_MASK)
#define IOMUXD_M40_I2C0_SDA_lp_config_MASK       (0x1800000U)
#define IOMUXD_M40_I2C0_SDA_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_M40_I2C0_SDA_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_M40_I2C0_SDA_lp_config_MASK)
#define IOMUXD_M40_I2C0_SDA_sw_config_MASK       (0x6000000U)
#define IOMUXD_M40_I2C0_SDA_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_M40_I2C0_SDA_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_M40_I2C0_SDA_sw_config_MASK)
#define IOMUXD_M40_I2C0_SDA_mux_mode_MASK        (0x38000000U)
#define IOMUXD_M40_I2C0_SDA_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..M40.I2C0.SDA
 *  0b001..M40.UART0.TX
 *  0b010..M40.GPIO0.IO03
 *  0b011..LSIO.GPIO0.IO07
 */
#define IOMUXD_M40_I2C0_SDA_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_M40_I2C0_SDA_mux_mode_MASK)
#define IOMUXD_M40_I2C0_SDA_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_M40_I2C0_SDA_update_pad_ctl_SHIFT (30U)
#define IOMUXD_M40_I2C0_SDA_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_M40_I2C0_SDA_update_pad_ctl_MASK)
#define IOMUXD_M40_I2C0_SDA_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_M40_I2C0_SDA_update_mux_mode_SHIFT (31U)
#define IOMUXD_M40_I2C0_SDA_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_M40_I2C0_SDA_update_mux_mode_MASK)
/*! @} */

/*! @name M40_GPIO0_00 - M40_GPIO0_00 */
/*! @{ */
#define IOMUXD_M40_GPIO0_00_PDRV_MASK            (0x1U)
#define IOMUXD_M40_GPIO0_00_PDRV_SHIFT           (0U)
#define IOMUXD_M40_GPIO0_00_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_00_PDRV_SHIFT)) & IOMUXD_M40_GPIO0_00_PDRV_MASK)
#define IOMUXD_M40_GPIO0_00_M40_GPIO0_00_reserved_1_4_MASK (0x1EU)
#define IOMUXD_M40_GPIO0_00_M40_GPIO0_00_reserved_1_4_SHIFT (1U)
#define IOMUXD_M40_GPIO0_00_M40_GPIO0_00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_00_M40_GPIO0_00_reserved_1_4_SHIFT)) & IOMUXD_M40_GPIO0_00_M40_GPIO0_00_reserved_1_4_MASK)
#define IOMUXD_M40_GPIO0_00_PULL_MASK            (0x60U)
#define IOMUXD_M40_GPIO0_00_PULL_SHIFT           (5U)
#define IOMUXD_M40_GPIO0_00_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_00_PULL_SHIFT)) & IOMUXD_M40_GPIO0_00_PULL_MASK)
#define IOMUXD_M40_GPIO0_00_M40_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_M40_GPIO0_00_M40_GPIO0_00_reserved_7_18_SHIFT (7U)
#define IOMUXD_M40_GPIO0_00_M40_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_00_M40_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_M40_GPIO0_00_M40_GPIO0_00_reserved_7_18_MASK)
#define IOMUXD_M40_GPIO0_00_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_M40_GPIO0_00_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_M40_GPIO0_00_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_M40_GPIO0_00_WAKEUP_CTRL_MASK)
#define IOMUXD_M40_GPIO0_00_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_M40_GPIO0_00_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_M40_GPIO0_00_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_M40_GPIO0_00_WAKEUP_MASK_MASK)
#define IOMUXD_M40_GPIO0_00_lp_config_MASK       (0x1800000U)
#define IOMUXD_M40_GPIO0_00_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_M40_GPIO0_00_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_00_lp_config_SHIFT)) & IOMUXD_M40_GPIO0_00_lp_config_MASK)
#define IOMUXD_M40_GPIO0_00_sw_config_MASK       (0x6000000U)
#define IOMUXD_M40_GPIO0_00_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_M40_GPIO0_00_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_00_sw_config_SHIFT)) & IOMUXD_M40_GPIO0_00_sw_config_MASK)
#define IOMUXD_M40_GPIO0_00_mux_mode_MASK        (0x38000000U)
#define IOMUXD_M40_GPIO0_00_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..M40.GPIO0.IO00
 *  0b001..M40.TPM0.CH0
 *  0b010..DMA.UART4.RX
 *  0b011..LSIO.GPIO0.IO08
 */
#define IOMUXD_M40_GPIO0_00_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_M40_GPIO0_00_mux_mode_MASK)
#define IOMUXD_M40_GPIO0_00_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_M40_GPIO0_00_update_pad_ctl_SHIFT (30U)
#define IOMUXD_M40_GPIO0_00_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_M40_GPIO0_00_update_pad_ctl_MASK)
#define IOMUXD_M40_GPIO0_00_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_M40_GPIO0_00_update_mux_mode_SHIFT (31U)
#define IOMUXD_M40_GPIO0_00_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_M40_GPIO0_00_update_mux_mode_MASK)
/*! @} */

/*! @name M40_GPIO0_01 - M40_GPIO0_01 */
/*! @{ */
#define IOMUXD_M40_GPIO0_01_PDRV_MASK            (0x1U)
#define IOMUXD_M40_GPIO0_01_PDRV_SHIFT           (0U)
#define IOMUXD_M40_GPIO0_01_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_01_PDRV_SHIFT)) & IOMUXD_M40_GPIO0_01_PDRV_MASK)
#define IOMUXD_M40_GPIO0_01_M40_GPIO0_01_reserved_1_4_MASK (0x1EU)
#define IOMUXD_M40_GPIO0_01_M40_GPIO0_01_reserved_1_4_SHIFT (1U)
#define IOMUXD_M40_GPIO0_01_M40_GPIO0_01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_01_M40_GPIO0_01_reserved_1_4_SHIFT)) & IOMUXD_M40_GPIO0_01_M40_GPIO0_01_reserved_1_4_MASK)
#define IOMUXD_M40_GPIO0_01_PULL_MASK            (0x60U)
#define IOMUXD_M40_GPIO0_01_PULL_SHIFT           (5U)
#define IOMUXD_M40_GPIO0_01_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_01_PULL_SHIFT)) & IOMUXD_M40_GPIO0_01_PULL_MASK)
#define IOMUXD_M40_GPIO0_01_M40_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_M40_GPIO0_01_M40_GPIO0_01_reserved_7_18_SHIFT (7U)
#define IOMUXD_M40_GPIO0_01_M40_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_01_M40_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_M40_GPIO0_01_M40_GPIO0_01_reserved_7_18_MASK)
#define IOMUXD_M40_GPIO0_01_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_M40_GPIO0_01_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_M40_GPIO0_01_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_M40_GPIO0_01_WAKEUP_CTRL_MASK)
#define IOMUXD_M40_GPIO0_01_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_M40_GPIO0_01_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_M40_GPIO0_01_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_M40_GPIO0_01_WAKEUP_MASK_MASK)
#define IOMUXD_M40_GPIO0_01_lp_config_MASK       (0x1800000U)
#define IOMUXD_M40_GPIO0_01_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_M40_GPIO0_01_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_01_lp_config_SHIFT)) & IOMUXD_M40_GPIO0_01_lp_config_MASK)
#define IOMUXD_M40_GPIO0_01_sw_config_MASK       (0x6000000U)
#define IOMUXD_M40_GPIO0_01_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_M40_GPIO0_01_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_01_sw_config_SHIFT)) & IOMUXD_M40_GPIO0_01_sw_config_MASK)
#define IOMUXD_M40_GPIO0_01_mux_mode_MASK        (0x38000000U)
#define IOMUXD_M40_GPIO0_01_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..M40.GPIO0.IO01
 *  0b001..M40.TPM0.CH1
 *  0b010..DMA.UART4.TX
 *  0b011..LSIO.GPIO0.IO09
 */
#define IOMUXD_M40_GPIO0_01_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_M40_GPIO0_01_mux_mode_MASK)
#define IOMUXD_M40_GPIO0_01_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_M40_GPIO0_01_update_pad_ctl_SHIFT (30U)
#define IOMUXD_M40_GPIO0_01_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_M40_GPIO0_01_update_pad_ctl_MASK)
#define IOMUXD_M40_GPIO0_01_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_M40_GPIO0_01_update_mux_mode_SHIFT (31U)
#define IOMUXD_M40_GPIO0_01_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_M40_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_M40_GPIO0_01_update_mux_mode_MASK)
/*! @} */

/*! @name M41_I2C0_SCL - M41_I2C0_SCL */
/*! @{ */
#define IOMUXD_M41_I2C0_SCL_PDRV_MASK            (0x1U)
#define IOMUXD_M41_I2C0_SCL_PDRV_SHIFT           (0U)
#define IOMUXD_M41_I2C0_SCL_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SCL_PDRV_SHIFT)) & IOMUXD_M41_I2C0_SCL_PDRV_MASK)
#define IOMUXD_M41_I2C0_SCL_M41_I2C0_SCL_reserved_1_4_MASK (0x1EU)
#define IOMUXD_M41_I2C0_SCL_M41_I2C0_SCL_reserved_1_4_SHIFT (1U)
#define IOMUXD_M41_I2C0_SCL_M41_I2C0_SCL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SCL_M41_I2C0_SCL_reserved_1_4_SHIFT)) & IOMUXD_M41_I2C0_SCL_M41_I2C0_SCL_reserved_1_4_MASK)
#define IOMUXD_M41_I2C0_SCL_PULL_MASK            (0x60U)
#define IOMUXD_M41_I2C0_SCL_PULL_SHIFT           (5U)
#define IOMUXD_M41_I2C0_SCL_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SCL_PULL_SHIFT)) & IOMUXD_M41_I2C0_SCL_PULL_MASK)
#define IOMUXD_M41_I2C0_SCL_M41_I2C0_SCL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_M41_I2C0_SCL_M41_I2C0_SCL_reserved_7_18_SHIFT (7U)
#define IOMUXD_M41_I2C0_SCL_M41_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SCL_M41_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_M41_I2C0_SCL_M41_I2C0_SCL_reserved_7_18_MASK)
#define IOMUXD_M41_I2C0_SCL_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_M41_I2C0_SCL_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_M41_I2C0_SCL_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_M41_I2C0_SCL_WAKEUP_CTRL_MASK)
#define IOMUXD_M41_I2C0_SCL_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_M41_I2C0_SCL_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_M41_I2C0_SCL_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_M41_I2C0_SCL_WAKEUP_MASK_MASK)
#define IOMUXD_M41_I2C0_SCL_lp_config_MASK       (0x1800000U)
#define IOMUXD_M41_I2C0_SCL_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_M41_I2C0_SCL_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_M41_I2C0_SCL_lp_config_MASK)
#define IOMUXD_M41_I2C0_SCL_sw_config_MASK       (0x6000000U)
#define IOMUXD_M41_I2C0_SCL_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_M41_I2C0_SCL_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_M41_I2C0_SCL_sw_config_MASK)
#define IOMUXD_M41_I2C0_SCL_mux_mode_MASK        (0x38000000U)
#define IOMUXD_M41_I2C0_SCL_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..M41.I2C0.SCL
 *  0b001..M41.UART0.RX
 *  0b010..M41.GPIO0.IO02
 *  0b011..LSIO.GPIO0.IO10
 */
#define IOMUXD_M41_I2C0_SCL_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_M41_I2C0_SCL_mux_mode_MASK)
#define IOMUXD_M41_I2C0_SCL_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_M41_I2C0_SCL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_M41_I2C0_SCL_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_M41_I2C0_SCL_update_pad_ctl_MASK)
#define IOMUXD_M41_I2C0_SCL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_M41_I2C0_SCL_update_mux_mode_SHIFT (31U)
#define IOMUXD_M41_I2C0_SCL_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_M41_I2C0_SCL_update_mux_mode_MASK)
/*! @} */

/*! @name M41_I2C0_SDA - M41_I2C0_SDA */
/*! @{ */
#define IOMUXD_M41_I2C0_SDA_PDRV_MASK            (0x1U)
#define IOMUXD_M41_I2C0_SDA_PDRV_SHIFT           (0U)
#define IOMUXD_M41_I2C0_SDA_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SDA_PDRV_SHIFT)) & IOMUXD_M41_I2C0_SDA_PDRV_MASK)
#define IOMUXD_M41_I2C0_SDA_M41_I2C0_SDA_reserved_1_4_MASK (0x1EU)
#define IOMUXD_M41_I2C0_SDA_M41_I2C0_SDA_reserved_1_4_SHIFT (1U)
#define IOMUXD_M41_I2C0_SDA_M41_I2C0_SDA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SDA_M41_I2C0_SDA_reserved_1_4_SHIFT)) & IOMUXD_M41_I2C0_SDA_M41_I2C0_SDA_reserved_1_4_MASK)
#define IOMUXD_M41_I2C0_SDA_PULL_MASK            (0x60U)
#define IOMUXD_M41_I2C0_SDA_PULL_SHIFT           (5U)
#define IOMUXD_M41_I2C0_SDA_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SDA_PULL_SHIFT)) & IOMUXD_M41_I2C0_SDA_PULL_MASK)
#define IOMUXD_M41_I2C0_SDA_M41_I2C0_SDA_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_M41_I2C0_SDA_M41_I2C0_SDA_reserved_7_18_SHIFT (7U)
#define IOMUXD_M41_I2C0_SDA_M41_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SDA_M41_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_M41_I2C0_SDA_M41_I2C0_SDA_reserved_7_18_MASK)
#define IOMUXD_M41_I2C0_SDA_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_M41_I2C0_SDA_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_M41_I2C0_SDA_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_M41_I2C0_SDA_WAKEUP_CTRL_MASK)
#define IOMUXD_M41_I2C0_SDA_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_M41_I2C0_SDA_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_M41_I2C0_SDA_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_M41_I2C0_SDA_WAKEUP_MASK_MASK)
#define IOMUXD_M41_I2C0_SDA_lp_config_MASK       (0x1800000U)
#define IOMUXD_M41_I2C0_SDA_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_M41_I2C0_SDA_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_M41_I2C0_SDA_lp_config_MASK)
#define IOMUXD_M41_I2C0_SDA_sw_config_MASK       (0x6000000U)
#define IOMUXD_M41_I2C0_SDA_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_M41_I2C0_SDA_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_M41_I2C0_SDA_sw_config_MASK)
#define IOMUXD_M41_I2C0_SDA_mux_mode_MASK        (0x38000000U)
#define IOMUXD_M41_I2C0_SDA_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..M41.I2C0.SDA
 *  0b001..M41.UART0.TX
 *  0b010..M41.GPIO0.IO03
 *  0b011..LSIO.GPIO0.IO11
 */
#define IOMUXD_M41_I2C0_SDA_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_M41_I2C0_SDA_mux_mode_MASK)
#define IOMUXD_M41_I2C0_SDA_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_M41_I2C0_SDA_update_pad_ctl_SHIFT (30U)
#define IOMUXD_M41_I2C0_SDA_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_M41_I2C0_SDA_update_pad_ctl_MASK)
#define IOMUXD_M41_I2C0_SDA_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_M41_I2C0_SDA_update_mux_mode_SHIFT (31U)
#define IOMUXD_M41_I2C0_SDA_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_M41_I2C0_SDA_update_mux_mode_MASK)
/*! @} */

/*! @name M41_GPIO0_00 - M41_GPIO0_00 */
/*! @{ */
#define IOMUXD_M41_GPIO0_00_PDRV_MASK            (0x1U)
#define IOMUXD_M41_GPIO0_00_PDRV_SHIFT           (0U)
#define IOMUXD_M41_GPIO0_00_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_00_PDRV_SHIFT)) & IOMUXD_M41_GPIO0_00_PDRV_MASK)
#define IOMUXD_M41_GPIO0_00_M41_GPIO0_00_reserved_1_4_MASK (0x1EU)
#define IOMUXD_M41_GPIO0_00_M41_GPIO0_00_reserved_1_4_SHIFT (1U)
#define IOMUXD_M41_GPIO0_00_M41_GPIO0_00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_00_M41_GPIO0_00_reserved_1_4_SHIFT)) & IOMUXD_M41_GPIO0_00_M41_GPIO0_00_reserved_1_4_MASK)
#define IOMUXD_M41_GPIO0_00_PULL_MASK            (0x60U)
#define IOMUXD_M41_GPIO0_00_PULL_SHIFT           (5U)
#define IOMUXD_M41_GPIO0_00_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_00_PULL_SHIFT)) & IOMUXD_M41_GPIO0_00_PULL_MASK)
#define IOMUXD_M41_GPIO0_00_M41_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_M41_GPIO0_00_M41_GPIO0_00_reserved_7_18_SHIFT (7U)
#define IOMUXD_M41_GPIO0_00_M41_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_00_M41_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_M41_GPIO0_00_M41_GPIO0_00_reserved_7_18_MASK)
#define IOMUXD_M41_GPIO0_00_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_M41_GPIO0_00_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_M41_GPIO0_00_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_M41_GPIO0_00_WAKEUP_CTRL_MASK)
#define IOMUXD_M41_GPIO0_00_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_M41_GPIO0_00_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_M41_GPIO0_00_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_M41_GPIO0_00_WAKEUP_MASK_MASK)
#define IOMUXD_M41_GPIO0_00_lp_config_MASK       (0x1800000U)
#define IOMUXD_M41_GPIO0_00_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_M41_GPIO0_00_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_00_lp_config_SHIFT)) & IOMUXD_M41_GPIO0_00_lp_config_MASK)
#define IOMUXD_M41_GPIO0_00_sw_config_MASK       (0x6000000U)
#define IOMUXD_M41_GPIO0_00_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_M41_GPIO0_00_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_00_sw_config_SHIFT)) & IOMUXD_M41_GPIO0_00_sw_config_MASK)
#define IOMUXD_M41_GPIO0_00_mux_mode_MASK        (0x38000000U)
#define IOMUXD_M41_GPIO0_00_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..M41.GPIO0.IO00
 *  0b001..M41.TPM0.CH0
 *  0b010..DMA.UART3.RX
 *  0b011..LSIO.GPIO0.IO12
 */
#define IOMUXD_M41_GPIO0_00_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_M41_GPIO0_00_mux_mode_MASK)
#define IOMUXD_M41_GPIO0_00_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_M41_GPIO0_00_update_pad_ctl_SHIFT (30U)
#define IOMUXD_M41_GPIO0_00_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_M41_GPIO0_00_update_pad_ctl_MASK)
#define IOMUXD_M41_GPIO0_00_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_M41_GPIO0_00_update_mux_mode_SHIFT (31U)
#define IOMUXD_M41_GPIO0_00_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_M41_GPIO0_00_update_mux_mode_MASK)
/*! @} */

/*! @name M41_GPIO0_01 - M41_GPIO0_01 */
/*! @{ */
#define IOMUXD_M41_GPIO0_01_PDRV_MASK            (0x1U)
#define IOMUXD_M41_GPIO0_01_PDRV_SHIFT           (0U)
#define IOMUXD_M41_GPIO0_01_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_01_PDRV_SHIFT)) & IOMUXD_M41_GPIO0_01_PDRV_MASK)
#define IOMUXD_M41_GPIO0_01_M41_GPIO0_01_reserved_1_4_MASK (0x1EU)
#define IOMUXD_M41_GPIO0_01_M41_GPIO0_01_reserved_1_4_SHIFT (1U)
#define IOMUXD_M41_GPIO0_01_M41_GPIO0_01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_01_M41_GPIO0_01_reserved_1_4_SHIFT)) & IOMUXD_M41_GPIO0_01_M41_GPIO0_01_reserved_1_4_MASK)
#define IOMUXD_M41_GPIO0_01_PULL_MASK            (0x60U)
#define IOMUXD_M41_GPIO0_01_PULL_SHIFT           (5U)
#define IOMUXD_M41_GPIO0_01_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_01_PULL_SHIFT)) & IOMUXD_M41_GPIO0_01_PULL_MASK)
#define IOMUXD_M41_GPIO0_01_M41_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_M41_GPIO0_01_M41_GPIO0_01_reserved_7_18_SHIFT (7U)
#define IOMUXD_M41_GPIO0_01_M41_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_01_M41_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_M41_GPIO0_01_M41_GPIO0_01_reserved_7_18_MASK)
#define IOMUXD_M41_GPIO0_01_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_M41_GPIO0_01_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_M41_GPIO0_01_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_M41_GPIO0_01_WAKEUP_CTRL_MASK)
#define IOMUXD_M41_GPIO0_01_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_M41_GPIO0_01_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_M41_GPIO0_01_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_M41_GPIO0_01_WAKEUP_MASK_MASK)
#define IOMUXD_M41_GPIO0_01_lp_config_MASK       (0x1800000U)
#define IOMUXD_M41_GPIO0_01_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_M41_GPIO0_01_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_01_lp_config_SHIFT)) & IOMUXD_M41_GPIO0_01_lp_config_MASK)
#define IOMUXD_M41_GPIO0_01_sw_config_MASK       (0x6000000U)
#define IOMUXD_M41_GPIO0_01_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_M41_GPIO0_01_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_01_sw_config_SHIFT)) & IOMUXD_M41_GPIO0_01_sw_config_MASK)
#define IOMUXD_M41_GPIO0_01_mux_mode_MASK        (0x38000000U)
#define IOMUXD_M41_GPIO0_01_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..M41.GPIO0.IO01
 *  0b001..M41.TPM0.CH1
 *  0b010..DMA.UART3.TX
 *  0b011..LSIO.GPIO0.IO13
 */
#define IOMUXD_M41_GPIO0_01_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_M41_GPIO0_01_mux_mode_MASK)
#define IOMUXD_M41_GPIO0_01_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_M41_GPIO0_01_update_pad_ctl_SHIFT (30U)
#define IOMUXD_M41_GPIO0_01_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_M41_GPIO0_01_update_pad_ctl_MASK)
#define IOMUXD_M41_GPIO0_01_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_M41_GPIO0_01_update_mux_mode_SHIFT (31U)
#define IOMUXD_M41_GPIO0_01_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_M41_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_M41_GPIO0_01_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_0_0 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_CLK_MASK    (0x1U)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_CLK_SHIFT   (0U)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_CLK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_SIM0_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_SIM0_CLK_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_RST_MASK    (0x2U)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_RST_SHIFT   (1U)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_RST(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_SIM0_RST_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_SIM0_RST_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_IO_MASK     (0x4U)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_IO_SHIFT    (2U)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_IO(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_SIM0_IO_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_SIM0_IO_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_PD_MASK     (0x8U)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_PD_SHIFT    (3U)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_PD(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_SIM0_PD_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_SIM0_PD_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_POWER_EN_MASK (0x10U)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_POWER_EN_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_POWER_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_SIM0_POWER_EN_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_SIM0_POWER_EN_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_GPIO0_00_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_GPIO0_00_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_0_0_SIM0_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_SIM0_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_SIM0_GPIO0_00_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_6_6_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_6_6_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_6_6_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_6_6_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_M40_I2C0_SCL_MASK (0x80U)
#define IOMUXD_IOMUXD_GROUP_0_0_M40_I2C0_SCL_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_0_0_M40_I2C0_SCL(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_M40_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_M40_I2C0_SCL_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_M40_I2C0_SDA_MASK (0x100U)
#define IOMUXD_IOMUXD_GROUP_0_0_M40_I2C0_SDA_SHIFT (8U)
#define IOMUXD_IOMUXD_GROUP_0_0_M40_I2C0_SDA(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_M40_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_M40_I2C0_SDA_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_M40_GPIO0_00_MASK (0x200U)
#define IOMUXD_IOMUXD_GROUP_0_0_M40_GPIO0_00_SHIFT (9U)
#define IOMUXD_IOMUXD_GROUP_0_0_M40_GPIO0_00(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_M40_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_M40_GPIO0_00_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_M40_GPIO0_01_MASK (0x400U)
#define IOMUXD_IOMUXD_GROUP_0_0_M40_GPIO0_01_SHIFT (10U)
#define IOMUXD_IOMUXD_GROUP_0_0_M40_GPIO0_01(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_M40_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_M40_GPIO0_01_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_M41_I2C0_SCL_MASK (0x800U)
#define IOMUXD_IOMUXD_GROUP_0_0_M41_I2C0_SCL_SHIFT (11U)
#define IOMUXD_IOMUXD_GROUP_0_0_M41_I2C0_SCL(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_M41_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_M41_I2C0_SCL_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_M41_I2C0_SDA_MASK (0x1000U)
#define IOMUXD_IOMUXD_GROUP_0_0_M41_I2C0_SDA_SHIFT (12U)
#define IOMUXD_IOMUXD_GROUP_0_0_M41_I2C0_SDA(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_M41_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_M41_I2C0_SDA_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_M41_GPIO0_00_MASK (0x2000U)
#define IOMUXD_IOMUXD_GROUP_0_0_M41_GPIO0_00_SHIFT (13U)
#define IOMUXD_IOMUXD_GROUP_0_0_M41_GPIO0_00(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_M41_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_M41_GPIO0_00_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_M41_GPIO0_01_MASK (0x4000U)
#define IOMUXD_IOMUXD_GROUP_0_0_M41_GPIO0_01_SHIFT (14U)
#define IOMUXD_IOMUXD_GROUP_0_0_M41_GPIO0_01(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_M41_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_M41_GPIO0_01_MASK)
#define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_15_31_MASK (0xFFFF8000U)
#define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_15_31_SHIFT (15U)
#define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_15_31_MASK)
/*! @} */

/*! @name GPT0_CLK - GPT0_CLK */
/*! @{ */
#define IOMUXD_GPT0_CLK_PDRV_MASK                (0x1U)
#define IOMUXD_GPT0_CLK_PDRV_SHIFT               (0U)
#define IOMUXD_GPT0_CLK_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CLK_PDRV_SHIFT)) & IOMUXD_GPT0_CLK_PDRV_MASK)
#define IOMUXD_GPT0_CLK_GPT0_CLK_reserved_1_4_MASK (0x1EU)
#define IOMUXD_GPT0_CLK_GPT0_CLK_reserved_1_4_SHIFT (1U)
#define IOMUXD_GPT0_CLK_GPT0_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CLK_GPT0_CLK_reserved_1_4_SHIFT)) & IOMUXD_GPT0_CLK_GPT0_CLK_reserved_1_4_MASK)
#define IOMUXD_GPT0_CLK_PULL_MASK                (0x60U)
#define IOMUXD_GPT0_CLK_PULL_SHIFT               (5U)
#define IOMUXD_GPT0_CLK_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CLK_PULL_SHIFT)) & IOMUXD_GPT0_CLK_PULL_MASK)
#define IOMUXD_GPT0_CLK_GPT0_CLK_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_GPT0_CLK_GPT0_CLK_reserved_7_18_SHIFT (7U)
#define IOMUXD_GPT0_CLK_GPT0_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CLK_GPT0_CLK_reserved_7_18_SHIFT)) & IOMUXD_GPT0_CLK_GPT0_CLK_reserved_7_18_MASK)
#define IOMUXD_GPT0_CLK_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_GPT0_CLK_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_GPT0_CLK_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_GPT0_CLK_WAKEUP_CTRL_MASK)
#define IOMUXD_GPT0_CLK_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_GPT0_CLK_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_GPT0_CLK_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_GPT0_CLK_WAKEUP_MASK_MASK)
#define IOMUXD_GPT0_CLK_lp_config_MASK           (0x1800000U)
#define IOMUXD_GPT0_CLK_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_GPT0_CLK_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CLK_lp_config_SHIFT)) & IOMUXD_GPT0_CLK_lp_config_MASK)
#define IOMUXD_GPT0_CLK_sw_config_MASK           (0x6000000U)
#define IOMUXD_GPT0_CLK_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_GPT0_CLK_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CLK_sw_config_SHIFT)) & IOMUXD_GPT0_CLK_sw_config_MASK)
#define IOMUXD_GPT0_CLK_mux_mode_MASK            (0x38000000U)
#define IOMUXD_GPT0_CLK_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.GPT0.CLK
 *  0b001..DMA.I2C1.SCL
 *  0b010..LSIO.KPP0.COL4
 *  0b011..LSIO.GPIO0.IO14
 */
#define IOMUXD_GPT0_CLK_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CLK_mux_mode_SHIFT)) & IOMUXD_GPT0_CLK_mux_mode_MASK)
#define IOMUXD_GPT0_CLK_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_GPT0_CLK_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_GPT0_CLK_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CLK_update_pad_ctl_SHIFT)) & IOMUXD_GPT0_CLK_update_pad_ctl_MASK)
#define IOMUXD_GPT0_CLK_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_GPT0_CLK_update_mux_mode_SHIFT    (31U)
#define IOMUXD_GPT0_CLK_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CLK_update_mux_mode_SHIFT)) & IOMUXD_GPT0_CLK_update_mux_mode_MASK)
/*! @} */

/*! @name GPT0_CAPTURE - GPT0_CAPTURE */
/*! @{ */
#define IOMUXD_GPT0_CAPTURE_PDRV_MASK            (0x1U)
#define IOMUXD_GPT0_CAPTURE_PDRV_SHIFT           (0U)
#define IOMUXD_GPT0_CAPTURE_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CAPTURE_PDRV_SHIFT)) & IOMUXD_GPT0_CAPTURE_PDRV_MASK)
#define IOMUXD_GPT0_CAPTURE_GPT0_CAPTURE_reserved_1_4_MASK (0x1EU)
#define IOMUXD_GPT0_CAPTURE_GPT0_CAPTURE_reserved_1_4_SHIFT (1U)
#define IOMUXD_GPT0_CAPTURE_GPT0_CAPTURE_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CAPTURE_GPT0_CAPTURE_reserved_1_4_SHIFT)) & IOMUXD_GPT0_CAPTURE_GPT0_CAPTURE_reserved_1_4_MASK)
#define IOMUXD_GPT0_CAPTURE_PULL_MASK            (0x60U)
#define IOMUXD_GPT0_CAPTURE_PULL_SHIFT           (5U)
#define IOMUXD_GPT0_CAPTURE_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CAPTURE_PULL_SHIFT)) & IOMUXD_GPT0_CAPTURE_PULL_MASK)
#define IOMUXD_GPT0_CAPTURE_GPT0_CAPTURE_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_GPT0_CAPTURE_GPT0_CAPTURE_reserved_7_18_SHIFT (7U)
#define IOMUXD_GPT0_CAPTURE_GPT0_CAPTURE_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CAPTURE_GPT0_CAPTURE_reserved_7_18_SHIFT)) & IOMUXD_GPT0_CAPTURE_GPT0_CAPTURE_reserved_7_18_MASK)
#define IOMUXD_GPT0_CAPTURE_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_GPT0_CAPTURE_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_GPT0_CAPTURE_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CAPTURE_WAKEUP_CTRL_SHIFT)) & IOMUXD_GPT0_CAPTURE_WAKEUP_CTRL_MASK)
#define IOMUXD_GPT0_CAPTURE_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_GPT0_CAPTURE_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_GPT0_CAPTURE_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CAPTURE_WAKEUP_MASK_SHIFT)) & IOMUXD_GPT0_CAPTURE_WAKEUP_MASK_MASK)
#define IOMUXD_GPT0_CAPTURE_lp_config_MASK       (0x1800000U)
#define IOMUXD_GPT0_CAPTURE_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_GPT0_CAPTURE_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CAPTURE_lp_config_SHIFT)) & IOMUXD_GPT0_CAPTURE_lp_config_MASK)
#define IOMUXD_GPT0_CAPTURE_sw_config_MASK       (0x6000000U)
#define IOMUXD_GPT0_CAPTURE_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_GPT0_CAPTURE_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CAPTURE_sw_config_SHIFT)) & IOMUXD_GPT0_CAPTURE_sw_config_MASK)
#define IOMUXD_GPT0_CAPTURE_mux_mode_MASK        (0x38000000U)
#define IOMUXD_GPT0_CAPTURE_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.GPT0.CAPTURE
 *  0b001..DMA.I2C1.SDA
 *  0b010..LSIO.KPP0.COL5
 *  0b011..LSIO.GPIO0.IO15
 */
#define IOMUXD_GPT0_CAPTURE_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CAPTURE_mux_mode_SHIFT)) & IOMUXD_GPT0_CAPTURE_mux_mode_MASK)
#define IOMUXD_GPT0_CAPTURE_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_GPT0_CAPTURE_update_pad_ctl_SHIFT (30U)
#define IOMUXD_GPT0_CAPTURE_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CAPTURE_update_pad_ctl_SHIFT)) & IOMUXD_GPT0_CAPTURE_update_pad_ctl_MASK)
#define IOMUXD_GPT0_CAPTURE_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_GPT0_CAPTURE_update_mux_mode_SHIFT (31U)
#define IOMUXD_GPT0_CAPTURE_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_CAPTURE_update_mux_mode_SHIFT)) & IOMUXD_GPT0_CAPTURE_update_mux_mode_MASK)
/*! @} */

/*! @name GPT0_COMPARE - GPT0_COMPARE */
/*! @{ */
#define IOMUXD_GPT0_COMPARE_PDRV_MASK            (0x1U)
#define IOMUXD_GPT0_COMPARE_PDRV_SHIFT           (0U)
#define IOMUXD_GPT0_COMPARE_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_COMPARE_PDRV_SHIFT)) & IOMUXD_GPT0_COMPARE_PDRV_MASK)
#define IOMUXD_GPT0_COMPARE_GPT0_COMPARE_reserved_1_4_MASK (0x1EU)
#define IOMUXD_GPT0_COMPARE_GPT0_COMPARE_reserved_1_4_SHIFT (1U)
#define IOMUXD_GPT0_COMPARE_GPT0_COMPARE_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_COMPARE_GPT0_COMPARE_reserved_1_4_SHIFT)) & IOMUXD_GPT0_COMPARE_GPT0_COMPARE_reserved_1_4_MASK)
#define IOMUXD_GPT0_COMPARE_PULL_MASK            (0x60U)
#define IOMUXD_GPT0_COMPARE_PULL_SHIFT           (5U)
#define IOMUXD_GPT0_COMPARE_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_COMPARE_PULL_SHIFT)) & IOMUXD_GPT0_COMPARE_PULL_MASK)
#define IOMUXD_GPT0_COMPARE_GPT0_COMPARE_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_GPT0_COMPARE_GPT0_COMPARE_reserved_7_18_SHIFT (7U)
#define IOMUXD_GPT0_COMPARE_GPT0_COMPARE_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_COMPARE_GPT0_COMPARE_reserved_7_18_SHIFT)) & IOMUXD_GPT0_COMPARE_GPT0_COMPARE_reserved_7_18_MASK)
#define IOMUXD_GPT0_COMPARE_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_GPT0_COMPARE_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_GPT0_COMPARE_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_COMPARE_WAKEUP_CTRL_SHIFT)) & IOMUXD_GPT0_COMPARE_WAKEUP_CTRL_MASK)
#define IOMUXD_GPT0_COMPARE_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_GPT0_COMPARE_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_GPT0_COMPARE_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_COMPARE_WAKEUP_MASK_SHIFT)) & IOMUXD_GPT0_COMPARE_WAKEUP_MASK_MASK)
#define IOMUXD_GPT0_COMPARE_lp_config_MASK       (0x1800000U)
#define IOMUXD_GPT0_COMPARE_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_GPT0_COMPARE_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_COMPARE_lp_config_SHIFT)) & IOMUXD_GPT0_COMPARE_lp_config_MASK)
#define IOMUXD_GPT0_COMPARE_sw_config_MASK       (0x6000000U)
#define IOMUXD_GPT0_COMPARE_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_GPT0_COMPARE_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_COMPARE_sw_config_SHIFT)) & IOMUXD_GPT0_COMPARE_sw_config_MASK)
#define IOMUXD_GPT0_COMPARE_mux_mode_MASK        (0x38000000U)
#define IOMUXD_GPT0_COMPARE_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.GPT0.COMPARE
 *  0b001..LSIO.PWM3.OUT
 *  0b010..LSIO.KPP0.COL6
 *  0b011..LSIO.GPIO0.IO16
 */
#define IOMUXD_GPT0_COMPARE_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_COMPARE_mux_mode_SHIFT)) & IOMUXD_GPT0_COMPARE_mux_mode_MASK)
#define IOMUXD_GPT0_COMPARE_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_GPT0_COMPARE_update_pad_ctl_SHIFT (30U)
#define IOMUXD_GPT0_COMPARE_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_COMPARE_update_pad_ctl_SHIFT)) & IOMUXD_GPT0_COMPARE_update_pad_ctl_MASK)
#define IOMUXD_GPT0_COMPARE_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_GPT0_COMPARE_update_mux_mode_SHIFT (31U)
#define IOMUXD_GPT0_COMPARE_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT0_COMPARE_update_mux_mode_SHIFT)) & IOMUXD_GPT0_COMPARE_update_mux_mode_MASK)
/*! @} */

/*! @name GPT1_CLK - GPT1_CLK */
/*! @{ */
#define IOMUXD_GPT1_CLK_PDRV_MASK                (0x1U)
#define IOMUXD_GPT1_CLK_PDRV_SHIFT               (0U)
#define IOMUXD_GPT1_CLK_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CLK_PDRV_SHIFT)) & IOMUXD_GPT1_CLK_PDRV_MASK)
#define IOMUXD_GPT1_CLK_GPT1_CLK_reserved_1_4_MASK (0x1EU)
#define IOMUXD_GPT1_CLK_GPT1_CLK_reserved_1_4_SHIFT (1U)
#define IOMUXD_GPT1_CLK_GPT1_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CLK_GPT1_CLK_reserved_1_4_SHIFT)) & IOMUXD_GPT1_CLK_GPT1_CLK_reserved_1_4_MASK)
#define IOMUXD_GPT1_CLK_PULL_MASK                (0x60U)
#define IOMUXD_GPT1_CLK_PULL_SHIFT               (5U)
#define IOMUXD_GPT1_CLK_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CLK_PULL_SHIFT)) & IOMUXD_GPT1_CLK_PULL_MASK)
#define IOMUXD_GPT1_CLK_GPT1_CLK_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_GPT1_CLK_GPT1_CLK_reserved_7_18_SHIFT (7U)
#define IOMUXD_GPT1_CLK_GPT1_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CLK_GPT1_CLK_reserved_7_18_SHIFT)) & IOMUXD_GPT1_CLK_GPT1_CLK_reserved_7_18_MASK)
#define IOMUXD_GPT1_CLK_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_GPT1_CLK_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_GPT1_CLK_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_GPT1_CLK_WAKEUP_CTRL_MASK)
#define IOMUXD_GPT1_CLK_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_GPT1_CLK_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_GPT1_CLK_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_GPT1_CLK_WAKEUP_MASK_MASK)
#define IOMUXD_GPT1_CLK_lp_config_MASK           (0x1800000U)
#define IOMUXD_GPT1_CLK_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_GPT1_CLK_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CLK_lp_config_SHIFT)) & IOMUXD_GPT1_CLK_lp_config_MASK)
#define IOMUXD_GPT1_CLK_sw_config_MASK           (0x6000000U)
#define IOMUXD_GPT1_CLK_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_GPT1_CLK_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CLK_sw_config_SHIFT)) & IOMUXD_GPT1_CLK_sw_config_MASK)
#define IOMUXD_GPT1_CLK_mux_mode_MASK            (0x38000000U)
#define IOMUXD_GPT1_CLK_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.GPT1.CLK
 *  0b001..DMA.I2C2.SCL
 *  0b010..LSIO.KPP0.COL7
 *  0b011..LSIO.GPIO0.IO17
 */
#define IOMUXD_GPT1_CLK_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CLK_mux_mode_SHIFT)) & IOMUXD_GPT1_CLK_mux_mode_MASK)
#define IOMUXD_GPT1_CLK_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_GPT1_CLK_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_GPT1_CLK_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CLK_update_pad_ctl_SHIFT)) & IOMUXD_GPT1_CLK_update_pad_ctl_MASK)
#define IOMUXD_GPT1_CLK_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_GPT1_CLK_update_mux_mode_SHIFT    (31U)
#define IOMUXD_GPT1_CLK_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CLK_update_mux_mode_SHIFT)) & IOMUXD_GPT1_CLK_update_mux_mode_MASK)
/*! @} */

/*! @name GPT1_CAPTURE - GPT1_CAPTURE */
/*! @{ */
#define IOMUXD_GPT1_CAPTURE_PDRV_MASK            (0x1U)
#define IOMUXD_GPT1_CAPTURE_PDRV_SHIFT           (0U)
#define IOMUXD_GPT1_CAPTURE_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CAPTURE_PDRV_SHIFT)) & IOMUXD_GPT1_CAPTURE_PDRV_MASK)
#define IOMUXD_GPT1_CAPTURE_GPT1_CAPTURE_reserved_1_4_MASK (0x1EU)
#define IOMUXD_GPT1_CAPTURE_GPT1_CAPTURE_reserved_1_4_SHIFT (1U)
#define IOMUXD_GPT1_CAPTURE_GPT1_CAPTURE_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CAPTURE_GPT1_CAPTURE_reserved_1_4_SHIFT)) & IOMUXD_GPT1_CAPTURE_GPT1_CAPTURE_reserved_1_4_MASK)
#define IOMUXD_GPT1_CAPTURE_PULL_MASK            (0x60U)
#define IOMUXD_GPT1_CAPTURE_PULL_SHIFT           (5U)
#define IOMUXD_GPT1_CAPTURE_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CAPTURE_PULL_SHIFT)) & IOMUXD_GPT1_CAPTURE_PULL_MASK)
#define IOMUXD_GPT1_CAPTURE_GPT1_CAPTURE_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_GPT1_CAPTURE_GPT1_CAPTURE_reserved_7_18_SHIFT (7U)
#define IOMUXD_GPT1_CAPTURE_GPT1_CAPTURE_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CAPTURE_GPT1_CAPTURE_reserved_7_18_SHIFT)) & IOMUXD_GPT1_CAPTURE_GPT1_CAPTURE_reserved_7_18_MASK)
#define IOMUXD_GPT1_CAPTURE_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_GPT1_CAPTURE_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_GPT1_CAPTURE_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CAPTURE_WAKEUP_CTRL_SHIFT)) & IOMUXD_GPT1_CAPTURE_WAKEUP_CTRL_MASK)
#define IOMUXD_GPT1_CAPTURE_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_GPT1_CAPTURE_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_GPT1_CAPTURE_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CAPTURE_WAKEUP_MASK_SHIFT)) & IOMUXD_GPT1_CAPTURE_WAKEUP_MASK_MASK)
#define IOMUXD_GPT1_CAPTURE_lp_config_MASK       (0x1800000U)
#define IOMUXD_GPT1_CAPTURE_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_GPT1_CAPTURE_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CAPTURE_lp_config_SHIFT)) & IOMUXD_GPT1_CAPTURE_lp_config_MASK)
#define IOMUXD_GPT1_CAPTURE_sw_config_MASK       (0x6000000U)
#define IOMUXD_GPT1_CAPTURE_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_GPT1_CAPTURE_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CAPTURE_sw_config_SHIFT)) & IOMUXD_GPT1_CAPTURE_sw_config_MASK)
#define IOMUXD_GPT1_CAPTURE_mux_mode_MASK        (0x38000000U)
#define IOMUXD_GPT1_CAPTURE_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.GPT1.CAPTURE
 *  0b001..DMA.I2C2.SDA
 *  0b010..LSIO.KPP0.ROW4
 *  0b011..LSIO.GPIO0.IO18
 */
#define IOMUXD_GPT1_CAPTURE_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CAPTURE_mux_mode_SHIFT)) & IOMUXD_GPT1_CAPTURE_mux_mode_MASK)
#define IOMUXD_GPT1_CAPTURE_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_GPT1_CAPTURE_update_pad_ctl_SHIFT (30U)
#define IOMUXD_GPT1_CAPTURE_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CAPTURE_update_pad_ctl_SHIFT)) & IOMUXD_GPT1_CAPTURE_update_pad_ctl_MASK)
#define IOMUXD_GPT1_CAPTURE_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_GPT1_CAPTURE_update_mux_mode_SHIFT (31U)
#define IOMUXD_GPT1_CAPTURE_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_CAPTURE_update_mux_mode_SHIFT)) & IOMUXD_GPT1_CAPTURE_update_mux_mode_MASK)
/*! @} */

/*! @name GPT1_COMPARE - GPT1_COMPARE */
/*! @{ */
#define IOMUXD_GPT1_COMPARE_PDRV_MASK            (0x1U)
#define IOMUXD_GPT1_COMPARE_PDRV_SHIFT           (0U)
#define IOMUXD_GPT1_COMPARE_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_COMPARE_PDRV_SHIFT)) & IOMUXD_GPT1_COMPARE_PDRV_MASK)
#define IOMUXD_GPT1_COMPARE_GPT1_COMPARE_reserved_1_4_MASK (0x1EU)
#define IOMUXD_GPT1_COMPARE_GPT1_COMPARE_reserved_1_4_SHIFT (1U)
#define IOMUXD_GPT1_COMPARE_GPT1_COMPARE_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_COMPARE_GPT1_COMPARE_reserved_1_4_SHIFT)) & IOMUXD_GPT1_COMPARE_GPT1_COMPARE_reserved_1_4_MASK)
#define IOMUXD_GPT1_COMPARE_PULL_MASK            (0x60U)
#define IOMUXD_GPT1_COMPARE_PULL_SHIFT           (5U)
#define IOMUXD_GPT1_COMPARE_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_COMPARE_PULL_SHIFT)) & IOMUXD_GPT1_COMPARE_PULL_MASK)
#define IOMUXD_GPT1_COMPARE_GPT1_COMPARE_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_GPT1_COMPARE_GPT1_COMPARE_reserved_7_18_SHIFT (7U)
#define IOMUXD_GPT1_COMPARE_GPT1_COMPARE_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_COMPARE_GPT1_COMPARE_reserved_7_18_SHIFT)) & IOMUXD_GPT1_COMPARE_GPT1_COMPARE_reserved_7_18_MASK)
#define IOMUXD_GPT1_COMPARE_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_GPT1_COMPARE_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_GPT1_COMPARE_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_COMPARE_WAKEUP_CTRL_SHIFT)) & IOMUXD_GPT1_COMPARE_WAKEUP_CTRL_MASK)
#define IOMUXD_GPT1_COMPARE_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_GPT1_COMPARE_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_GPT1_COMPARE_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_COMPARE_WAKEUP_MASK_SHIFT)) & IOMUXD_GPT1_COMPARE_WAKEUP_MASK_MASK)
#define IOMUXD_GPT1_COMPARE_lp_config_MASK       (0x1800000U)
#define IOMUXD_GPT1_COMPARE_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_GPT1_COMPARE_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_COMPARE_lp_config_SHIFT)) & IOMUXD_GPT1_COMPARE_lp_config_MASK)
#define IOMUXD_GPT1_COMPARE_sw_config_MASK       (0x6000000U)
#define IOMUXD_GPT1_COMPARE_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_GPT1_COMPARE_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_COMPARE_sw_config_SHIFT)) & IOMUXD_GPT1_COMPARE_sw_config_MASK)
#define IOMUXD_GPT1_COMPARE_mux_mode_MASK        (0x38000000U)
#define IOMUXD_GPT1_COMPARE_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.GPT1.COMPARE
 *  0b001..LSIO.PWM2.OUT
 *  0b010..LSIO.KPP0.ROW5
 *  0b011..LSIO.GPIO0.IO19
 */
#define IOMUXD_GPT1_COMPARE_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_COMPARE_mux_mode_SHIFT)) & IOMUXD_GPT1_COMPARE_mux_mode_MASK)
#define IOMUXD_GPT1_COMPARE_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_GPT1_COMPARE_update_pad_ctl_SHIFT (30U)
#define IOMUXD_GPT1_COMPARE_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_COMPARE_update_pad_ctl_SHIFT)) & IOMUXD_GPT1_COMPARE_update_pad_ctl_MASK)
#define IOMUXD_GPT1_COMPARE_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_GPT1_COMPARE_update_mux_mode_SHIFT (31U)
#define IOMUXD_GPT1_COMPARE_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_GPT1_COMPARE_update_mux_mode_SHIFT)) & IOMUXD_GPT1_COMPARE_update_mux_mode_MASK)
/*! @} */

/*! @name UART0_RX - UART0_RX */
/*! @{ */
#define IOMUXD_UART0_RX_PDRV_MASK                (0x1U)
#define IOMUXD_UART0_RX_PDRV_SHIFT               (0U)
#define IOMUXD_UART0_RX_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_PDRV_SHIFT)) & IOMUXD_UART0_RX_PDRV_MASK)
#define IOMUXD_UART0_RX_UART0_RX_reserved_1_4_MASK (0x1EU)
#define IOMUXD_UART0_RX_UART0_RX_reserved_1_4_SHIFT (1U)
#define IOMUXD_UART0_RX_UART0_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_UART0_RX_reserved_1_4_SHIFT)) & IOMUXD_UART0_RX_UART0_RX_reserved_1_4_MASK)
#define IOMUXD_UART0_RX_PULL_MASK                (0x60U)
#define IOMUXD_UART0_RX_PULL_SHIFT               (5U)
#define IOMUXD_UART0_RX_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_PULL_SHIFT)) & IOMUXD_UART0_RX_PULL_MASK)
#define IOMUXD_UART0_RX_UART0_RX_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_UART0_RX_UART0_RX_reserved_7_18_SHIFT (7U)
#define IOMUXD_UART0_RX_UART0_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_UART0_RX_reserved_7_18_SHIFT)) & IOMUXD_UART0_RX_UART0_RX_reserved_7_18_MASK)
#define IOMUXD_UART0_RX_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_UART0_RX_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_UART0_RX_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART0_RX_WAKEUP_CTRL_MASK)
#define IOMUXD_UART0_RX_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_UART0_RX_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_UART0_RX_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART0_RX_WAKEUP_MASK_MASK)
#define IOMUXD_UART0_RX_lp_config_MASK           (0x1800000U)
#define IOMUXD_UART0_RX_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_UART0_RX_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_lp_config_SHIFT)) & IOMUXD_UART0_RX_lp_config_MASK)
#define IOMUXD_UART0_RX_sw_config_MASK           (0x6000000U)
#define IOMUXD_UART0_RX_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_UART0_RX_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_sw_config_SHIFT)) & IOMUXD_UART0_RX_sw_config_MASK)
#define IOMUXD_UART0_RX_mux_mode_MASK            (0x38000000U)
#define IOMUXD_UART0_RX_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.UART0.RX
 *  0b001..SCU.UART0.RX
 *  0b011..LSIO.GPIO0.IO20
 */
#define IOMUXD_UART0_RX_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_mux_mode_SHIFT)) & IOMUXD_UART0_RX_mux_mode_MASK)
#define IOMUXD_UART0_RX_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_UART0_RX_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_UART0_RX_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_update_pad_ctl_SHIFT)) & IOMUXD_UART0_RX_update_pad_ctl_MASK)
#define IOMUXD_UART0_RX_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_UART0_RX_update_mux_mode_SHIFT    (31U)
#define IOMUXD_UART0_RX_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_update_mux_mode_SHIFT)) & IOMUXD_UART0_RX_update_mux_mode_MASK)
/*! @} */

/*! @name UART0_TX - UART0_TX */
/*! @{ */
#define IOMUXD_UART0_TX_PDRV_MASK                (0x1U)
#define IOMUXD_UART0_TX_PDRV_SHIFT               (0U)
#define IOMUXD_UART0_TX_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_PDRV_SHIFT)) & IOMUXD_UART0_TX_PDRV_MASK)
#define IOMUXD_UART0_TX_UART0_TX_reserved_1_4_MASK (0x1EU)
#define IOMUXD_UART0_TX_UART0_TX_reserved_1_4_SHIFT (1U)
#define IOMUXD_UART0_TX_UART0_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_UART0_TX_reserved_1_4_SHIFT)) & IOMUXD_UART0_TX_UART0_TX_reserved_1_4_MASK)
#define IOMUXD_UART0_TX_PULL_MASK                (0x60U)
#define IOMUXD_UART0_TX_PULL_SHIFT               (5U)
#define IOMUXD_UART0_TX_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_PULL_SHIFT)) & IOMUXD_UART0_TX_PULL_MASK)
#define IOMUXD_UART0_TX_UART0_TX_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_UART0_TX_UART0_TX_reserved_7_18_SHIFT (7U)
#define IOMUXD_UART0_TX_UART0_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_UART0_TX_reserved_7_18_SHIFT)) & IOMUXD_UART0_TX_UART0_TX_reserved_7_18_MASK)
#define IOMUXD_UART0_TX_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_UART0_TX_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_UART0_TX_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART0_TX_WAKEUP_CTRL_MASK)
#define IOMUXD_UART0_TX_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_UART0_TX_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_UART0_TX_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART0_TX_WAKEUP_MASK_MASK)
#define IOMUXD_UART0_TX_lp_config_MASK           (0x1800000U)
#define IOMUXD_UART0_TX_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_UART0_TX_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_lp_config_SHIFT)) & IOMUXD_UART0_TX_lp_config_MASK)
#define IOMUXD_UART0_TX_sw_config_MASK           (0x6000000U)
#define IOMUXD_UART0_TX_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_UART0_TX_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_sw_config_SHIFT)) & IOMUXD_UART0_TX_sw_config_MASK)
#define IOMUXD_UART0_TX_mux_mode_MASK            (0x38000000U)
#define IOMUXD_UART0_TX_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.UART0.TX
 *  0b001..SCU.UART0.TX
 *  0b011..LSIO.GPIO0.IO21
 */
#define IOMUXD_UART0_TX_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_mux_mode_SHIFT)) & IOMUXD_UART0_TX_mux_mode_MASK)
#define IOMUXD_UART0_TX_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_UART0_TX_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_UART0_TX_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_update_pad_ctl_SHIFT)) & IOMUXD_UART0_TX_update_pad_ctl_MASK)
#define IOMUXD_UART0_TX_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_UART0_TX_update_mux_mode_SHIFT    (31U)
#define IOMUXD_UART0_TX_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_update_mux_mode_SHIFT)) & IOMUXD_UART0_TX_update_mux_mode_MASK)
/*! @} */

/*! @name UART0_RTS_B - UART0_RTS_B */
/*! @{ */
#define IOMUXD_UART0_RTS_B_PDRV_MASK             (0x1U)
#define IOMUXD_UART0_RTS_B_PDRV_SHIFT            (0U)
#define IOMUXD_UART0_RTS_B_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RTS_B_PDRV_SHIFT)) & IOMUXD_UART0_RTS_B_PDRV_MASK)
#define IOMUXD_UART0_RTS_B_UART0_RTS_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_UART0_RTS_B_UART0_RTS_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_UART0_RTS_B_UART0_RTS_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RTS_B_UART0_RTS_B_reserved_1_4_SHIFT)) & IOMUXD_UART0_RTS_B_UART0_RTS_B_reserved_1_4_MASK)
#define IOMUXD_UART0_RTS_B_PULL_MASK             (0x60U)
#define IOMUXD_UART0_RTS_B_PULL_SHIFT            (5U)
#define IOMUXD_UART0_RTS_B_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RTS_B_PULL_SHIFT)) & IOMUXD_UART0_RTS_B_PULL_MASK)
#define IOMUXD_UART0_RTS_B_UART0_RTS_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_UART0_RTS_B_UART0_RTS_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_UART0_RTS_B_UART0_RTS_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RTS_B_UART0_RTS_B_reserved_7_18_SHIFT)) & IOMUXD_UART0_RTS_B_UART0_RTS_B_reserved_7_18_MASK)
#define IOMUXD_UART0_RTS_B_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_UART0_RTS_B_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_UART0_RTS_B_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RTS_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART0_RTS_B_WAKEUP_CTRL_MASK)
#define IOMUXD_UART0_RTS_B_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_UART0_RTS_B_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_UART0_RTS_B_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RTS_B_WAKEUP_MASK_SHIFT)) & IOMUXD_UART0_RTS_B_WAKEUP_MASK_MASK)
#define IOMUXD_UART0_RTS_B_lp_config_MASK        (0x1800000U)
#define IOMUXD_UART0_RTS_B_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_UART0_RTS_B_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RTS_B_lp_config_SHIFT)) & IOMUXD_UART0_RTS_B_lp_config_MASK)
#define IOMUXD_UART0_RTS_B_sw_config_MASK        (0x6000000U)
#define IOMUXD_UART0_RTS_B_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_UART0_RTS_B_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RTS_B_sw_config_SHIFT)) & IOMUXD_UART0_RTS_B_sw_config_MASK)
#define IOMUXD_UART0_RTS_B_mux_mode_MASK         (0x38000000U)
#define IOMUXD_UART0_RTS_B_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.UART0.RTS_B
 *  0b001..LSIO.PWM0.OUT
 *  0b010..DMA.UART2.RX
 *  0b011..LSIO.GPIO0.IO22
 */
#define IOMUXD_UART0_RTS_B_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RTS_B_mux_mode_SHIFT)) & IOMUXD_UART0_RTS_B_mux_mode_MASK)
#define IOMUXD_UART0_RTS_B_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_UART0_RTS_B_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_UART0_RTS_B_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RTS_B_update_pad_ctl_SHIFT)) & IOMUXD_UART0_RTS_B_update_pad_ctl_MASK)
#define IOMUXD_UART0_RTS_B_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_UART0_RTS_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_UART0_RTS_B_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RTS_B_update_mux_mode_SHIFT)) & IOMUXD_UART0_RTS_B_update_mux_mode_MASK)
/*! @} */

/*! @name UART0_CTS_B - UART0_CTS_B */
/*! @{ */
#define IOMUXD_UART0_CTS_B_PDRV_MASK             (0x1U)
#define IOMUXD_UART0_CTS_B_PDRV_SHIFT            (0U)
#define IOMUXD_UART0_CTS_B_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_CTS_B_PDRV_SHIFT)) & IOMUXD_UART0_CTS_B_PDRV_MASK)
#define IOMUXD_UART0_CTS_B_UART0_CTS_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_UART0_CTS_B_UART0_CTS_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_UART0_CTS_B_UART0_CTS_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_CTS_B_UART0_CTS_B_reserved_1_4_SHIFT)) & IOMUXD_UART0_CTS_B_UART0_CTS_B_reserved_1_4_MASK)
#define IOMUXD_UART0_CTS_B_PULL_MASK             (0x60U)
#define IOMUXD_UART0_CTS_B_PULL_SHIFT            (5U)
#define IOMUXD_UART0_CTS_B_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_CTS_B_PULL_SHIFT)) & IOMUXD_UART0_CTS_B_PULL_MASK)
#define IOMUXD_UART0_CTS_B_UART0_CTS_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_UART0_CTS_B_UART0_CTS_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_UART0_CTS_B_UART0_CTS_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_CTS_B_UART0_CTS_B_reserved_7_18_SHIFT)) & IOMUXD_UART0_CTS_B_UART0_CTS_B_reserved_7_18_MASK)
#define IOMUXD_UART0_CTS_B_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_UART0_CTS_B_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_UART0_CTS_B_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_CTS_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART0_CTS_B_WAKEUP_CTRL_MASK)
#define IOMUXD_UART0_CTS_B_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_UART0_CTS_B_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_UART0_CTS_B_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_CTS_B_WAKEUP_MASK_SHIFT)) & IOMUXD_UART0_CTS_B_WAKEUP_MASK_MASK)
#define IOMUXD_UART0_CTS_B_lp_config_MASK        (0x1800000U)
#define IOMUXD_UART0_CTS_B_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_UART0_CTS_B_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_CTS_B_lp_config_SHIFT)) & IOMUXD_UART0_CTS_B_lp_config_MASK)
#define IOMUXD_UART0_CTS_B_sw_config_MASK        (0x6000000U)
#define IOMUXD_UART0_CTS_B_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_UART0_CTS_B_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_CTS_B_sw_config_SHIFT)) & IOMUXD_UART0_CTS_B_sw_config_MASK)
#define IOMUXD_UART0_CTS_B_mux_mode_MASK         (0x38000000U)
#define IOMUXD_UART0_CTS_B_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.UART0.CTS_B
 *  0b001..LSIO.PWM1.OUT
 *  0b010..DMA.UART2.TX
 *  0b011..LSIO.GPIO0.IO23
 */
#define IOMUXD_UART0_CTS_B_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_CTS_B_mux_mode_SHIFT)) & IOMUXD_UART0_CTS_B_mux_mode_MASK)
#define IOMUXD_UART0_CTS_B_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_UART0_CTS_B_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_UART0_CTS_B_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_CTS_B_update_pad_ctl_SHIFT)) & IOMUXD_UART0_CTS_B_update_pad_ctl_MASK)
#define IOMUXD_UART0_CTS_B_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_UART0_CTS_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_UART0_CTS_B_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_CTS_B_update_mux_mode_SHIFT)) & IOMUXD_UART0_CTS_B_update_mux_mode_MASK)
/*! @} */

/*! @name UART1_TX - UART1_TX */
/*! @{ */
#define IOMUXD_UART1_TX_PDRV_MASK                (0x1U)
#define IOMUXD_UART1_TX_PDRV_SHIFT               (0U)
#define IOMUXD_UART1_TX_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_PDRV_SHIFT)) & IOMUXD_UART1_TX_PDRV_MASK)
#define IOMUXD_UART1_TX_UART1_TX_reserved_1_4_MASK (0x1EU)
#define IOMUXD_UART1_TX_UART1_TX_reserved_1_4_SHIFT (1U)
#define IOMUXD_UART1_TX_UART1_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_UART1_TX_reserved_1_4_SHIFT)) & IOMUXD_UART1_TX_UART1_TX_reserved_1_4_MASK)
#define IOMUXD_UART1_TX_PULL_MASK                (0x60U)
#define IOMUXD_UART1_TX_PULL_SHIFT               (5U)
#define IOMUXD_UART1_TX_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_PULL_SHIFT)) & IOMUXD_UART1_TX_PULL_MASK)
#define IOMUXD_UART1_TX_UART1_TX_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_UART1_TX_UART1_TX_reserved_7_18_SHIFT (7U)
#define IOMUXD_UART1_TX_UART1_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_UART1_TX_reserved_7_18_SHIFT)) & IOMUXD_UART1_TX_UART1_TX_reserved_7_18_MASK)
#define IOMUXD_UART1_TX_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_UART1_TX_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_UART1_TX_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_TX_WAKEUP_CTRL_MASK)
#define IOMUXD_UART1_TX_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_UART1_TX_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_UART1_TX_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_TX_WAKEUP_MASK_MASK)
#define IOMUXD_UART1_TX_lp_config_MASK           (0x1800000U)
#define IOMUXD_UART1_TX_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_UART1_TX_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_lp_config_SHIFT)) & IOMUXD_UART1_TX_lp_config_MASK)
#define IOMUXD_UART1_TX_sw_config_MASK           (0x6000000U)
#define IOMUXD_UART1_TX_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_UART1_TX_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_sw_config_SHIFT)) & IOMUXD_UART1_TX_sw_config_MASK)
#define IOMUXD_UART1_TX_mux_mode_MASK            (0x38000000U)
#define IOMUXD_UART1_TX_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.UART1.TX
 *  0b001..DMA.SPI3.SCK
 *  0b011..LSIO.GPIO0.IO24
 */
#define IOMUXD_UART1_TX_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_mux_mode_SHIFT)) & IOMUXD_UART1_TX_mux_mode_MASK)
#define IOMUXD_UART1_TX_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_UART1_TX_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_UART1_TX_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_update_pad_ctl_SHIFT)) & IOMUXD_UART1_TX_update_pad_ctl_MASK)
#define IOMUXD_UART1_TX_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_UART1_TX_update_mux_mode_SHIFT    (31U)
#define IOMUXD_UART1_TX_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_update_mux_mode_SHIFT)) & IOMUXD_UART1_TX_update_mux_mode_MASK)
/*! @} */

/*! @name UART1_RX - UART1_RX */
/*! @{ */
#define IOMUXD_UART1_RX_PDRV_MASK                (0x1U)
#define IOMUXD_UART1_RX_PDRV_SHIFT               (0U)
#define IOMUXD_UART1_RX_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_PDRV_SHIFT)) & IOMUXD_UART1_RX_PDRV_MASK)
#define IOMUXD_UART1_RX_UART1_RX_reserved_1_4_MASK (0x1EU)
#define IOMUXD_UART1_RX_UART1_RX_reserved_1_4_SHIFT (1U)
#define IOMUXD_UART1_RX_UART1_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_UART1_RX_reserved_1_4_SHIFT)) & IOMUXD_UART1_RX_UART1_RX_reserved_1_4_MASK)
#define IOMUXD_UART1_RX_PULL_MASK                (0x60U)
#define IOMUXD_UART1_RX_PULL_SHIFT               (5U)
#define IOMUXD_UART1_RX_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_PULL_SHIFT)) & IOMUXD_UART1_RX_PULL_MASK)
#define IOMUXD_UART1_RX_UART1_RX_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_UART1_RX_UART1_RX_reserved_7_18_SHIFT (7U)
#define IOMUXD_UART1_RX_UART1_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_UART1_RX_reserved_7_18_SHIFT)) & IOMUXD_UART1_RX_UART1_RX_reserved_7_18_MASK)
#define IOMUXD_UART1_RX_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_UART1_RX_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_UART1_RX_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_RX_WAKEUP_CTRL_MASK)
#define IOMUXD_UART1_RX_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_UART1_RX_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_UART1_RX_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_RX_WAKEUP_MASK_MASK)
#define IOMUXD_UART1_RX_lp_config_MASK           (0x1800000U)
#define IOMUXD_UART1_RX_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_UART1_RX_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_lp_config_SHIFT)) & IOMUXD_UART1_RX_lp_config_MASK)
#define IOMUXD_UART1_RX_sw_config_MASK           (0x6000000U)
#define IOMUXD_UART1_RX_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_UART1_RX_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_sw_config_SHIFT)) & IOMUXD_UART1_RX_sw_config_MASK)
#define IOMUXD_UART1_RX_mux_mode_MASK            (0x38000000U)
#define IOMUXD_UART1_RX_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.UART1.RX
 *  0b001..DMA.SPI3.SDO
 *  0b011..LSIO.GPIO0.IO25
 */
#define IOMUXD_UART1_RX_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_mux_mode_SHIFT)) & IOMUXD_UART1_RX_mux_mode_MASK)
#define IOMUXD_UART1_RX_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_UART1_RX_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_UART1_RX_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_update_pad_ctl_SHIFT)) & IOMUXD_UART1_RX_update_pad_ctl_MASK)
#define IOMUXD_UART1_RX_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_UART1_RX_update_mux_mode_SHIFT    (31U)
#define IOMUXD_UART1_RX_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_update_mux_mode_SHIFT)) & IOMUXD_UART1_RX_update_mux_mode_MASK)
/*! @} */

/*! @name UART1_RTS_B - UART1_RTS_B */
/*! @{ */
#define IOMUXD_UART1_RTS_B_PDRV_MASK             (0x1U)
#define IOMUXD_UART1_RTS_B_PDRV_SHIFT            (0U)
#define IOMUXD_UART1_RTS_B_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_PDRV_SHIFT)) & IOMUXD_UART1_RTS_B_PDRV_MASK)
#define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_SHIFT)) & IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_MASK)
#define IOMUXD_UART1_RTS_B_PULL_MASK             (0x60U)
#define IOMUXD_UART1_RTS_B_PULL_SHIFT            (5U)
#define IOMUXD_UART1_RTS_B_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_PULL_SHIFT)) & IOMUXD_UART1_RTS_B_PULL_MASK)
#define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_SHIFT)) & IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_MASK)
#define IOMUXD_UART1_RTS_B_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_UART1_RTS_B_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_UART1_RTS_B_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_RTS_B_WAKEUP_CTRL_MASK)
#define IOMUXD_UART1_RTS_B_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_UART1_RTS_B_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_UART1_RTS_B_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_RTS_B_WAKEUP_MASK_MASK)
#define IOMUXD_UART1_RTS_B_lp_config_MASK        (0x1800000U)
#define IOMUXD_UART1_RTS_B_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_UART1_RTS_B_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_lp_config_SHIFT)) & IOMUXD_UART1_RTS_B_lp_config_MASK)
#define IOMUXD_UART1_RTS_B_sw_config_MASK        (0x6000000U)
#define IOMUXD_UART1_RTS_B_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_UART1_RTS_B_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_sw_config_SHIFT)) & IOMUXD_UART1_RTS_B_sw_config_MASK)
#define IOMUXD_UART1_RTS_B_mux_mode_MASK         (0x38000000U)
#define IOMUXD_UART1_RTS_B_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.UART1.RTS_B
 *  0b001..DMA.SPI3.SDI
 *  0b010..DMA.UART1.CTS_B
 *  0b011..LSIO.GPIO0.IO26
 */
#define IOMUXD_UART1_RTS_B_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_mux_mode_SHIFT)) & IOMUXD_UART1_RTS_B_mux_mode_MASK)
#define IOMUXD_UART1_RTS_B_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_UART1_RTS_B_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_UART1_RTS_B_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_update_pad_ctl_SHIFT)) & IOMUXD_UART1_RTS_B_update_pad_ctl_MASK)
#define IOMUXD_UART1_RTS_B_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_UART1_RTS_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_UART1_RTS_B_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_update_mux_mode_SHIFT)) & IOMUXD_UART1_RTS_B_update_mux_mode_MASK)
/*! @} */

/*! @name UART1_CTS_B - UART1_CTS_B */
/*! @{ */
#define IOMUXD_UART1_CTS_B_PDRV_MASK             (0x1U)
#define IOMUXD_UART1_CTS_B_PDRV_SHIFT            (0U)
#define IOMUXD_UART1_CTS_B_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_PDRV_SHIFT)) & IOMUXD_UART1_CTS_B_PDRV_MASK)
#define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_SHIFT)) & IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_MASK)
#define IOMUXD_UART1_CTS_B_PULL_MASK             (0x60U)
#define IOMUXD_UART1_CTS_B_PULL_SHIFT            (5U)
#define IOMUXD_UART1_CTS_B_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_PULL_SHIFT)) & IOMUXD_UART1_CTS_B_PULL_MASK)
#define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_SHIFT)) & IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_MASK)
#define IOMUXD_UART1_CTS_B_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_UART1_CTS_B_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_UART1_CTS_B_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_CTS_B_WAKEUP_CTRL_MASK)
#define IOMUXD_UART1_CTS_B_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_UART1_CTS_B_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_UART1_CTS_B_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_CTS_B_WAKEUP_MASK_MASK)
#define IOMUXD_UART1_CTS_B_lp_config_MASK        (0x1800000U)
#define IOMUXD_UART1_CTS_B_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_UART1_CTS_B_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_lp_config_SHIFT)) & IOMUXD_UART1_CTS_B_lp_config_MASK)
#define IOMUXD_UART1_CTS_B_sw_config_MASK        (0x6000000U)
#define IOMUXD_UART1_CTS_B_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_UART1_CTS_B_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_sw_config_SHIFT)) & IOMUXD_UART1_CTS_B_sw_config_MASK)
#define IOMUXD_UART1_CTS_B_mux_mode_MASK         (0x38000000U)
#define IOMUXD_UART1_CTS_B_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.UART1.CTS_B
 *  0b001..DMA.SPI3.CS0
 *  0b010..DMA.UART1.RTS_B
 *  0b011..LSIO.GPIO0.IO27
 */
#define IOMUXD_UART1_CTS_B_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_mux_mode_SHIFT)) & IOMUXD_UART1_CTS_B_mux_mode_MASK)
#define IOMUXD_UART1_CTS_B_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_UART1_CTS_B_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_UART1_CTS_B_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_update_pad_ctl_SHIFT)) & IOMUXD_UART1_CTS_B_update_pad_ctl_MASK)
#define IOMUXD_UART1_CTS_B_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_UART1_CTS_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_UART1_CTS_B_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_update_mux_mode_SHIFT)) & IOMUXD_UART1_CTS_B_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_MASK)
/*! @} */

/*! @name SCU_PMIC_MEMC_ON - SCU_PMIC_MEMC_ON */
/*! @{ */
#define IOMUXD_SCU_PMIC_MEMC_ON_DSE_MASK         (0x7U)
#define IOMUXD_SCU_PMIC_MEMC_ON_DSE_SHIFT        (0U)
#define IOMUXD_SCU_PMIC_MEMC_ON_DSE(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_MEMC_ON_DSE_SHIFT)) & IOMUXD_SCU_PMIC_MEMC_ON_DSE_MASK)
#define IOMUXD_SCU_PMIC_MEMC_ON_SCU_PMIC_MEMC_ON_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_PMIC_MEMC_ON_SCU_PMIC_MEMC_ON_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_PMIC_MEMC_ON_SCU_PMIC_MEMC_ON_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_MEMC_ON_SCU_PMIC_MEMC_ON_reserved_3_4_SHIFT)) & IOMUXD_SCU_PMIC_MEMC_ON_SCU_PMIC_MEMC_ON_reserved_3_4_MASK)
#define IOMUXD_SCU_PMIC_MEMC_ON_PULL_MASK        (0x60U)
#define IOMUXD_SCU_PMIC_MEMC_ON_PULL_SHIFT       (5U)
#define IOMUXD_SCU_PMIC_MEMC_ON_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_MEMC_ON_PULL_SHIFT)) & IOMUXD_SCU_PMIC_MEMC_ON_PULL_MASK)
#define IOMUXD_SCU_PMIC_MEMC_ON_SCU_PMIC_MEMC_ON_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_PMIC_MEMC_ON_SCU_PMIC_MEMC_ON_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_PMIC_MEMC_ON_SCU_PMIC_MEMC_ON_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_MEMC_ON_SCU_PMIC_MEMC_ON_reserved_7_18_SHIFT)) & IOMUXD_SCU_PMIC_MEMC_ON_SCU_PMIC_MEMC_ON_reserved_7_18_MASK)
#define IOMUXD_SCU_PMIC_MEMC_ON_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_SCU_PMIC_MEMC_ON_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_PMIC_MEMC_ON_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_MEMC_ON_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_PMIC_MEMC_ON_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_PMIC_MEMC_ON_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_SCU_PMIC_MEMC_ON_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_SCU_PMIC_MEMC_ON_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_MEMC_ON_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_PMIC_MEMC_ON_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_PMIC_MEMC_ON_lp_config_MASK   (0x1800000U)
#define IOMUXD_SCU_PMIC_MEMC_ON_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_PMIC_MEMC_ON_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_MEMC_ON_lp_config_SHIFT)) & IOMUXD_SCU_PMIC_MEMC_ON_lp_config_MASK)
#define IOMUXD_SCU_PMIC_MEMC_ON_sw_config_MASK   (0x6000000U)
#define IOMUXD_SCU_PMIC_MEMC_ON_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_PMIC_MEMC_ON_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_MEMC_ON_sw_config_SHIFT)) & IOMUXD_SCU_PMIC_MEMC_ON_sw_config_MASK)
#define IOMUXD_SCU_PMIC_MEMC_ON_mux_mode_MASK    (0x38000000U)
#define IOMUXD_SCU_PMIC_MEMC_ON_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.GPIO0.IOXX_PMIC_MEMC_ON
 */
#define IOMUXD_SCU_PMIC_MEMC_ON_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_MEMC_ON_mux_mode_SHIFT)) & IOMUXD_SCU_PMIC_MEMC_ON_mux_mode_MASK)
#define IOMUXD_SCU_PMIC_MEMC_ON_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_SCU_PMIC_MEMC_ON_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_PMIC_MEMC_ON_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_MEMC_ON_update_pad_ctl_SHIFT)) & IOMUXD_SCU_PMIC_MEMC_ON_update_pad_ctl_MASK)
#define IOMUXD_SCU_PMIC_MEMC_ON_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_PMIC_MEMC_ON_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_PMIC_MEMC_ON_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_MEMC_ON_update_mux_mode_SHIFT)) & IOMUXD_SCU_PMIC_MEMC_ON_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_0_1 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_0_1_GPT0_CLK_MASK    (0x1U)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT0_CLK_SHIFT   (0U)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT0_CLK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_GPT0_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_GPT0_CLK_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT0_CAPTURE_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT0_CAPTURE_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT0_CAPTURE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_GPT0_CAPTURE_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_GPT0_CAPTURE_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT0_COMPARE_MASK (0x4U)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT0_COMPARE_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT0_COMPARE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_GPT0_COMPARE_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_GPT0_COMPARE_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT1_CLK_MASK    (0x8U)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT1_CLK_SHIFT   (3U)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT1_CLK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_GPT1_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_GPT1_CLK_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT1_CAPTURE_MASK (0x10U)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT1_CAPTURE_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT1_CAPTURE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_GPT1_CAPTURE_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_GPT1_CAPTURE_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT1_COMPARE_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT1_COMPARE_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_0_1_GPT1_COMPARE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_GPT1_COMPARE_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_GPT1_COMPARE_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_UART0_RX_MASK    (0x40U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART0_RX_SHIFT   (6U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART0_RX(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_UART0_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_UART0_RX_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_UART0_TX_MASK    (0x80U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART0_TX_SHIFT   (7U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART0_TX(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_UART0_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_UART0_TX_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_UART0_RTS_B_MASK (0x100U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART0_RTS_B_SHIFT (8U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART0_RTS_B(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_UART0_RTS_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_UART0_RTS_B_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_UART0_CTS_B_MASK (0x200U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART0_CTS_B_SHIFT (9U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART0_CTS_B(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_UART0_CTS_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_UART0_CTS_B_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_UART1_TX_MASK    (0x400U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART1_TX_SHIFT   (10U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART1_TX(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_UART1_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_UART1_TX_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_UART1_RX_MASK    (0x800U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART1_RX_SHIFT   (11U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART1_RX(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_UART1_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_UART1_RX_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_UART1_RTS_B_MASK (0x1000U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART1_RTS_B_SHIFT (12U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART1_RTS_B(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_UART1_RTS_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_UART1_RTS_B_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_UART1_CTS_B_MASK (0x2000U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART1_CTS_B_SHIFT (13U)
#define IOMUXD_IOMUXD_GROUP_0_1_UART1_CTS_B(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_UART1_CTS_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_UART1_CTS_B_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_iomuxd_group_0_1_reserved_14_14_MASK (0x4000U)
#define IOMUXD_IOMUXD_GROUP_0_1_iomuxd_group_0_1_reserved_14_14_SHIFT (14U)
#define IOMUXD_IOMUXD_GROUP_0_1_iomuxd_group_0_1_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_iomuxd_group_0_1_reserved_14_14_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_iomuxd_group_0_1_reserved_14_14_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_SCU_PMIC_MEMC_ON_MASK (0x8000U)
#define IOMUXD_IOMUXD_GROUP_0_1_SCU_PMIC_MEMC_ON_SHIFT (15U)
#define IOMUXD_IOMUXD_GROUP_0_1_SCU_PMIC_MEMC_ON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_SCU_PMIC_MEMC_ON_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_SCU_PMIC_MEMC_ON_MASK)
#define IOMUXD_IOMUXD_GROUP_0_1_iomuxd_group_0_1_reserved_16_31_MASK (0xFFFF0000U)
#define IOMUXD_IOMUXD_GROUP_0_1_iomuxd_group_0_1_reserved_16_31_SHIFT (16U)
#define IOMUXD_IOMUXD_GROUP_0_1_iomuxd_group_0_1_reserved_16_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_1_iomuxd_group_0_1_reserved_16_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_1_iomuxd_group_0_1_reserved_16_31_MASK)
/*! @} */

/*! @name SCU_WDOG_OUT - SCU_WDOG_OUT */
/*! @{ */
#define IOMUXD_SCU_WDOG_OUT_DSE_MASK             (0x7U)
#define IOMUXD_SCU_WDOG_OUT_DSE_SHIFT            (0U)
#define IOMUXD_SCU_WDOG_OUT_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_DSE_SHIFT)) & IOMUXD_SCU_WDOG_OUT_DSE_MASK)
#define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_SHIFT)) & IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_MASK)
#define IOMUXD_SCU_WDOG_OUT_PULL_MASK            (0x60U)
#define IOMUXD_SCU_WDOG_OUT_PULL_SHIFT           (5U)
#define IOMUXD_SCU_WDOG_OUT_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_PULL_SHIFT)) & IOMUXD_SCU_WDOG_OUT_PULL_MASK)
#define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_SHIFT)) & IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_MASK)
#define IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_WDOG_OUT_lp_config_MASK       (0x1800000U)
#define IOMUXD_SCU_WDOG_OUT_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_WDOG_OUT_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_lp_config_SHIFT)) & IOMUXD_SCU_WDOG_OUT_lp_config_MASK)
#define IOMUXD_SCU_WDOG_OUT_sw_config_MASK       (0x6000000U)
#define IOMUXD_SCU_WDOG_OUT_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_WDOG_OUT_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_sw_config_SHIFT)) & IOMUXD_SCU_WDOG_OUT_sw_config_MASK)
#define IOMUXD_SCU_WDOG_OUT_mux_mode_MASK        (0x38000000U)
#define IOMUXD_SCU_WDOG_OUT_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.WDOG0.WDOG_OUT
 */
#define IOMUXD_SCU_WDOG_OUT_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_mux_mode_SHIFT)) & IOMUXD_SCU_WDOG_OUT_mux_mode_MASK)
#define IOMUXD_SCU_WDOG_OUT_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_SCU_WDOG_OUT_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_WDOG_OUT_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_update_pad_ctl_SHIFT)) & IOMUXD_SCU_WDOG_OUT_update_pad_ctl_MASK)
#define IOMUXD_SCU_WDOG_OUT_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_WDOG_OUT_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_WDOG_OUT_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_update_mux_mode_SHIFT)) & IOMUXD_SCU_WDOG_OUT_update_mux_mode_MASK)
/*! @} */

/*! @name PMIC_I2C_SDA - PMIC_I2C_SDA */
/*! @{ */
#define IOMUXD_PMIC_I2C_SDA_DSE_MASK             (0x7U)
#define IOMUXD_PMIC_I2C_SDA_DSE_SHIFT            (0U)
#define IOMUXD_PMIC_I2C_SDA_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_DSE_SHIFT)) & IOMUXD_PMIC_I2C_SDA_DSE_MASK)
#define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_MASK (0x18U)
#define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_SHIFT (3U)
#define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_SHIFT)) & IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_MASK)
#define IOMUXD_PMIC_I2C_SDA_PULL_MASK            (0x60U)
#define IOMUXD_PMIC_I2C_SDA_PULL_SHIFT           (5U)
#define IOMUXD_PMIC_I2C_SDA_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_PULL_SHIFT)) & IOMUXD_PMIC_I2C_SDA_PULL_MASK)
#define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_SHIFT (7U)
#define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_SHIFT)) & IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_MASK)
#define IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_MASK)
#define IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_MASK)
#define IOMUXD_PMIC_I2C_SDA_lp_config_MASK       (0x1800000U)
#define IOMUXD_PMIC_I2C_SDA_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_PMIC_I2C_SDA_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_lp_config_SHIFT)) & IOMUXD_PMIC_I2C_SDA_lp_config_MASK)
#define IOMUXD_PMIC_I2C_SDA_sw_config_MASK       (0x6000000U)
#define IOMUXD_PMIC_I2C_SDA_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_PMIC_I2C_SDA_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_sw_config_SHIFT)) & IOMUXD_PMIC_I2C_SDA_sw_config_MASK)
#define IOMUXD_PMIC_I2C_SDA_mux_mode_MASK        (0x38000000U)
#define IOMUXD_PMIC_I2C_SDA_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.PMIC_I2C.SDA
 */
#define IOMUXD_PMIC_I2C_SDA_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SDA_mux_mode_MASK)
#define IOMUXD_PMIC_I2C_SDA_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_PMIC_I2C_SDA_update_pad_ctl_SHIFT (30U)
#define IOMUXD_PMIC_I2C_SDA_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_update_pad_ctl_SHIFT)) & IOMUXD_PMIC_I2C_SDA_update_pad_ctl_MASK)
#define IOMUXD_PMIC_I2C_SDA_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_PMIC_I2C_SDA_update_mux_mode_SHIFT (31U)
#define IOMUXD_PMIC_I2C_SDA_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_update_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SDA_update_mux_mode_MASK)
/*! @} */

/*! @name PMIC_I2C_SCL - PMIC_I2C_SCL */
/*! @{ */
#define IOMUXD_PMIC_I2C_SCL_DSE_MASK             (0x7U)
#define IOMUXD_PMIC_I2C_SCL_DSE_SHIFT            (0U)
#define IOMUXD_PMIC_I2C_SCL_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_DSE_SHIFT)) & IOMUXD_PMIC_I2C_SCL_DSE_MASK)
#define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_MASK (0x18U)
#define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_SHIFT (3U)
#define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_SHIFT)) & IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_MASK)
#define IOMUXD_PMIC_I2C_SCL_PULL_MASK            (0x60U)
#define IOMUXD_PMIC_I2C_SCL_PULL_SHIFT           (5U)
#define IOMUXD_PMIC_I2C_SCL_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_PULL_SHIFT)) & IOMUXD_PMIC_I2C_SCL_PULL_MASK)
#define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_SHIFT (7U)
#define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_SHIFT)) & IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_MASK)
#define IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_MASK)
#define IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_MASK)
#define IOMUXD_PMIC_I2C_SCL_lp_config_MASK       (0x1800000U)
#define IOMUXD_PMIC_I2C_SCL_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_PMIC_I2C_SCL_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_lp_config_SHIFT)) & IOMUXD_PMIC_I2C_SCL_lp_config_MASK)
#define IOMUXD_PMIC_I2C_SCL_sw_config_MASK       (0x6000000U)
#define IOMUXD_PMIC_I2C_SCL_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_PMIC_I2C_SCL_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_sw_config_SHIFT)) & IOMUXD_PMIC_I2C_SCL_sw_config_MASK)
#define IOMUXD_PMIC_I2C_SCL_mux_mode_MASK        (0x38000000U)
#define IOMUXD_PMIC_I2C_SCL_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.PMIC_I2C.SCL
 */
#define IOMUXD_PMIC_I2C_SCL_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SCL_mux_mode_MASK)
#define IOMUXD_PMIC_I2C_SCL_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_PMIC_I2C_SCL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_PMIC_I2C_SCL_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_update_pad_ctl_SHIFT)) & IOMUXD_PMIC_I2C_SCL_update_pad_ctl_MASK)
#define IOMUXD_PMIC_I2C_SCL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_PMIC_I2C_SCL_update_mux_mode_SHIFT (31U)
#define IOMUXD_PMIC_I2C_SCL_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_update_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SCL_update_mux_mode_MASK)
/*! @} */

/*! @name PMIC_EARLY_WARNING - PMIC_EARLY_WARNING */
/*! @{ */
#define IOMUXD_PMIC_EARLY_WARNING_DSE_MASK       (0x7U)
#define IOMUXD_PMIC_EARLY_WARNING_DSE_SHIFT      (0U)
#define IOMUXD_PMIC_EARLY_WARNING_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_EARLY_WARNING_DSE_SHIFT)) & IOMUXD_PMIC_EARLY_WARNING_DSE_MASK)
#define IOMUXD_PMIC_EARLY_WARNING_PMIC_EARLY_WARNING_reserved_3_4_MASK (0x18U)
#define IOMUXD_PMIC_EARLY_WARNING_PMIC_EARLY_WARNING_reserved_3_4_SHIFT (3U)
#define IOMUXD_PMIC_EARLY_WARNING_PMIC_EARLY_WARNING_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_EARLY_WARNING_PMIC_EARLY_WARNING_reserved_3_4_SHIFT)) & IOMUXD_PMIC_EARLY_WARNING_PMIC_EARLY_WARNING_reserved_3_4_MASK)
#define IOMUXD_PMIC_EARLY_WARNING_PULL_MASK      (0x60U)
#define IOMUXD_PMIC_EARLY_WARNING_PULL_SHIFT     (5U)
#define IOMUXD_PMIC_EARLY_WARNING_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_EARLY_WARNING_PULL_SHIFT)) & IOMUXD_PMIC_EARLY_WARNING_PULL_MASK)
#define IOMUXD_PMIC_EARLY_WARNING_PMIC_EARLY_WARNING_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_PMIC_EARLY_WARNING_PMIC_EARLY_WARNING_reserved_7_18_SHIFT (7U)
#define IOMUXD_PMIC_EARLY_WARNING_PMIC_EARLY_WARNING_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_EARLY_WARNING_PMIC_EARLY_WARNING_reserved_7_18_SHIFT)) & IOMUXD_PMIC_EARLY_WARNING_PMIC_EARLY_WARNING_reserved_7_18_MASK)
#define IOMUXD_PMIC_EARLY_WARNING_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_PMIC_EARLY_WARNING_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_PMIC_EARLY_WARNING_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_EARLY_WARNING_WAKEUP_CTRL_SHIFT)) & IOMUXD_PMIC_EARLY_WARNING_WAKEUP_CTRL_MASK)
#define IOMUXD_PMIC_EARLY_WARNING_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_PMIC_EARLY_WARNING_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_PMIC_EARLY_WARNING_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_EARLY_WARNING_WAKEUP_MASK_SHIFT)) & IOMUXD_PMIC_EARLY_WARNING_WAKEUP_MASK_MASK)
#define IOMUXD_PMIC_EARLY_WARNING_lp_config_MASK (0x1800000U)
#define IOMUXD_PMIC_EARLY_WARNING_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_PMIC_EARLY_WARNING_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_EARLY_WARNING_lp_config_SHIFT)) & IOMUXD_PMIC_EARLY_WARNING_lp_config_MASK)
#define IOMUXD_PMIC_EARLY_WARNING_sw_config_MASK (0x6000000U)
#define IOMUXD_PMIC_EARLY_WARNING_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_PMIC_EARLY_WARNING_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_EARLY_WARNING_sw_config_SHIFT)) & IOMUXD_PMIC_EARLY_WARNING_sw_config_MASK)
#define IOMUXD_PMIC_EARLY_WARNING_mux_mode_MASK  (0x38000000U)
#define IOMUXD_PMIC_EARLY_WARNING_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.PMIC_EARLY_WARNING
 */
#define IOMUXD_PMIC_EARLY_WARNING_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_EARLY_WARNING_mux_mode_SHIFT)) & IOMUXD_PMIC_EARLY_WARNING_mux_mode_MASK)
#define IOMUXD_PMIC_EARLY_WARNING_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_PMIC_EARLY_WARNING_update_pad_ctl_SHIFT (30U)
#define IOMUXD_PMIC_EARLY_WARNING_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_EARLY_WARNING_update_pad_ctl_SHIFT)) & IOMUXD_PMIC_EARLY_WARNING_update_pad_ctl_MASK)
#define IOMUXD_PMIC_EARLY_WARNING_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_PMIC_EARLY_WARNING_update_mux_mode_SHIFT (31U)
#define IOMUXD_PMIC_EARLY_WARNING_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_EARLY_WARNING_update_mux_mode_SHIFT)) & IOMUXD_PMIC_EARLY_WARNING_update_mux_mode_MASK)
/*! @} */

/*! @name PMIC_INT_B - PMIC_INT_B */
/*! @{ */
#define IOMUXD_PMIC_INT_B_DSE_MASK               (0x7U)
#define IOMUXD_PMIC_INT_B_DSE_SHIFT              (0U)
#define IOMUXD_PMIC_INT_B_DSE(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_DSE_SHIFT)) & IOMUXD_PMIC_INT_B_DSE_MASK)
#define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_MASK (0x18U)
#define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_SHIFT (3U)
#define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_SHIFT)) & IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_MASK)
#define IOMUXD_PMIC_INT_B_PULL_MASK              (0x60U)
#define IOMUXD_PMIC_INT_B_PULL_SHIFT             (5U)
#define IOMUXD_PMIC_INT_B_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_PULL_SHIFT)) & IOMUXD_PMIC_INT_B_PULL_MASK)
#define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_SHIFT)) & IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_MASK)
#define IOMUXD_PMIC_INT_B_WAKEUP_CTRL_MASK       (0x380000U)
#define IOMUXD_PMIC_INT_B_WAKEUP_CTRL_SHIFT      (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_PMIC_INT_B_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PMIC_INT_B_WAKEUP_CTRL_MASK)
#define IOMUXD_PMIC_INT_B_WAKEUP_MASK_MASK       (0x400000U)
#define IOMUXD_PMIC_INT_B_WAKEUP_MASK_SHIFT      (22U)
#define IOMUXD_PMIC_INT_B_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PMIC_INT_B_WAKEUP_MASK_MASK)
#define IOMUXD_PMIC_INT_B_lp_config_MASK         (0x1800000U)
#define IOMUXD_PMIC_INT_B_lp_config_SHIFT        (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_PMIC_INT_B_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_lp_config_SHIFT)) & IOMUXD_PMIC_INT_B_lp_config_MASK)
#define IOMUXD_PMIC_INT_B_sw_config_MASK         (0x6000000U)
#define IOMUXD_PMIC_INT_B_sw_config_SHIFT        (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_PMIC_INT_B_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_sw_config_SHIFT)) & IOMUXD_PMIC_INT_B_sw_config_MASK)
#define IOMUXD_PMIC_INT_B_mux_mode_MASK          (0x38000000U)
#define IOMUXD_PMIC_INT_B_mux_mode_SHIFT         (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.DSC.PMIC_INT_B
 */
#define IOMUXD_PMIC_INT_B_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_mux_mode_SHIFT)) & IOMUXD_PMIC_INT_B_mux_mode_MASK)
#define IOMUXD_PMIC_INT_B_update_pad_ctl_MASK    (0x40000000U)
#define IOMUXD_PMIC_INT_B_update_pad_ctl_SHIFT   (30U)
#define IOMUXD_PMIC_INT_B_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_update_pad_ctl_SHIFT)) & IOMUXD_PMIC_INT_B_update_pad_ctl_MASK)
#define IOMUXD_PMIC_INT_B_update_mux_mode_MASK   (0x80000000U)
#define IOMUXD_PMIC_INT_B_update_mux_mode_SHIFT  (31U)
#define IOMUXD_PMIC_INT_B_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_update_mux_mode_SHIFT)) & IOMUXD_PMIC_INT_B_update_mux_mode_MASK)
/*! @} */

/*! @name SCU_GPIO0_00 - SCU_GPIO0_00 */
/*! @{ */
#define IOMUXD_SCU_GPIO0_00_DSE_MASK             (0x7U)
#define IOMUXD_SCU_GPIO0_00_DSE_SHIFT            (0U)
#define IOMUXD_SCU_GPIO0_00_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_DSE_SHIFT)) & IOMUXD_SCU_GPIO0_00_DSE_MASK)
#define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_SHIFT)) & IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_MASK)
#define IOMUXD_SCU_GPIO0_00_PULL_MASK            (0x60U)
#define IOMUXD_SCU_GPIO0_00_PULL_SHIFT           (5U)
#define IOMUXD_SCU_GPIO0_00_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_PULL_SHIFT)) & IOMUXD_SCU_GPIO0_00_PULL_MASK)
#define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_MASK)
#define IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_SCU_GPIO0_00_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_GPIO0_00_lp_config_MASK       (0x1800000U)
#define IOMUXD_SCU_GPIO0_00_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_GPIO0_00_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_lp_config_SHIFT)) & IOMUXD_SCU_GPIO0_00_lp_config_MASK)
#define IOMUXD_SCU_GPIO0_00_sw_config_MASK       (0x6000000U)
#define IOMUXD_SCU_GPIO0_00_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_GPIO0_00_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_sw_config_SHIFT)) & IOMUXD_SCU_GPIO0_00_sw_config_MASK)
#define IOMUXD_SCU_GPIO0_00_mux_mode_MASK        (0x38000000U)
#define IOMUXD_SCU_GPIO0_00_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.GPIO0.IO00
 *  0b001..SCU.UART0.RX
 *  0b011..LSIO.GPIO0.IO28
 */
#define IOMUXD_SCU_GPIO0_00_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_00_mux_mode_MASK)
#define IOMUXD_SCU_GPIO0_00_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_SCU_GPIO0_00_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_GPIO0_00_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_SCU_GPIO0_00_update_pad_ctl_MASK)
#define IOMUXD_SCU_GPIO0_00_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_GPIO0_00_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_GPIO0_00_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_00_update_mux_mode_MASK)
/*! @} */

/*! @name SCU_GPIO0_01 - SCU_GPIO0_01 */
/*! @{ */
#define IOMUXD_SCU_GPIO0_01_DSE_MASK             (0x7U)
#define IOMUXD_SCU_GPIO0_01_DSE_SHIFT            (0U)
#define IOMUXD_SCU_GPIO0_01_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_DSE_SHIFT)) & IOMUXD_SCU_GPIO0_01_DSE_MASK)
#define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_SHIFT)) & IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_MASK)
#define IOMUXD_SCU_GPIO0_01_PULL_MASK            (0x60U)
#define IOMUXD_SCU_GPIO0_01_PULL_SHIFT           (5U)
#define IOMUXD_SCU_GPIO0_01_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_PULL_SHIFT)) & IOMUXD_SCU_GPIO0_01_PULL_MASK)
#define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_MASK)
#define IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_SCU_GPIO0_01_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_GPIO0_01_lp_config_MASK       (0x1800000U)
#define IOMUXD_SCU_GPIO0_01_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_GPIO0_01_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_lp_config_SHIFT)) & IOMUXD_SCU_GPIO0_01_lp_config_MASK)
#define IOMUXD_SCU_GPIO0_01_sw_config_MASK       (0x6000000U)
#define IOMUXD_SCU_GPIO0_01_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_GPIO0_01_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_sw_config_SHIFT)) & IOMUXD_SCU_GPIO0_01_sw_config_MASK)
#define IOMUXD_SCU_GPIO0_01_mux_mode_MASK        (0x38000000U)
#define IOMUXD_SCU_GPIO0_01_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.GPIO0.IO01
 *  0b001..SCU.UART0.TX
 *  0b011..LSIO.GPIO0.IO29
 */
#define IOMUXD_SCU_GPIO0_01_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_01_mux_mode_MASK)
#define IOMUXD_SCU_GPIO0_01_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_SCU_GPIO0_01_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_GPIO0_01_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_SCU_GPIO0_01_update_pad_ctl_MASK)
#define IOMUXD_SCU_GPIO0_01_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_GPIO0_01_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_GPIO0_01_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_01_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_0_2 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_0_2_SCU_WDOG_OUT_MASK (0x1U)
#define IOMUXD_IOMUXD_GROUP_0_2_SCU_WDOG_OUT_SHIFT (0U)
#define IOMUXD_IOMUXD_GROUP_0_2_SCU_WDOG_OUT(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_2_SCU_WDOG_OUT_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_2_SCU_WDOG_OUT_MASK)
#define IOMUXD_IOMUXD_GROUP_0_2_PMIC_I2C_SDA_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_0_2_PMIC_I2C_SDA_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_0_2_PMIC_I2C_SDA(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_2_PMIC_I2C_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_2_PMIC_I2C_SDA_MASK)
#define IOMUXD_IOMUXD_GROUP_0_2_PMIC_I2C_SCL_MASK (0x4U)
#define IOMUXD_IOMUXD_GROUP_0_2_PMIC_I2C_SCL_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_0_2_PMIC_I2C_SCL(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_2_PMIC_I2C_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_2_PMIC_I2C_SCL_MASK)
#define IOMUXD_IOMUXD_GROUP_0_2_PMIC_EARLY_WARNING_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_0_2_PMIC_EARLY_WARNING_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_0_2_PMIC_EARLY_WARNING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_2_PMIC_EARLY_WARNING_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_2_PMIC_EARLY_WARNING_MASK)
#define IOMUXD_IOMUXD_GROUP_0_2_PMIC_INT_B_MASK  (0x10U)
#define IOMUXD_IOMUXD_GROUP_0_2_PMIC_INT_B_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_0_2_PMIC_INT_B(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_2_PMIC_INT_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_2_PMIC_INT_B_MASK)
#define IOMUXD_IOMUXD_GROUP_0_2_SCU_GPIO0_00_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_0_2_SCU_GPIO0_00_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_0_2_SCU_GPIO0_00(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_2_SCU_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_2_SCU_GPIO0_00_MASK)
#define IOMUXD_IOMUXD_GROUP_0_2_SCU_GPIO0_01_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_0_2_SCU_GPIO0_01_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_0_2_SCU_GPIO0_01(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_2_SCU_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_2_SCU_GPIO0_01_MASK)
#define IOMUXD_IOMUXD_GROUP_0_2_iomuxd_group_0_2_reserved_7_31_MASK (0xFFFFFF80U)
#define IOMUXD_IOMUXD_GROUP_0_2_iomuxd_group_0_2_reserved_7_31_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_0_2_iomuxd_group_0_2_reserved_7_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_2_iomuxd_group_0_2_reserved_7_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_2_iomuxd_group_0_2_reserved_7_31_MASK)
/*! @} */

/*! @name SCU_GPIO0_02 - SCU_GPIO0_02 */
/*! @{ */
#define IOMUXD_SCU_GPIO0_02_DSE_MASK             (0x7U)
#define IOMUXD_SCU_GPIO0_02_DSE_SHIFT            (0U)
#define IOMUXD_SCU_GPIO0_02_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_02_DSE_SHIFT)) & IOMUXD_SCU_GPIO0_02_DSE_MASK)
#define IOMUXD_SCU_GPIO0_02_SCU_GPIO0_02_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_GPIO0_02_SCU_GPIO0_02_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_GPIO0_02_SCU_GPIO0_02_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_02_SCU_GPIO0_02_reserved_3_4_SHIFT)) & IOMUXD_SCU_GPIO0_02_SCU_GPIO0_02_reserved_3_4_MASK)
#define IOMUXD_SCU_GPIO0_02_PULL_MASK            (0x60U)
#define IOMUXD_SCU_GPIO0_02_PULL_SHIFT           (5U)
#define IOMUXD_SCU_GPIO0_02_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_02_PULL_SHIFT)) & IOMUXD_SCU_GPIO0_02_PULL_MASK)
#define IOMUXD_SCU_GPIO0_02_SCU_GPIO0_02_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_GPIO0_02_SCU_GPIO0_02_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_GPIO0_02_SCU_GPIO0_02_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_02_SCU_GPIO0_02_reserved_7_18_SHIFT)) & IOMUXD_SCU_GPIO0_02_SCU_GPIO0_02_reserved_7_18_MASK)
#define IOMUXD_SCU_GPIO0_02_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_SCU_GPIO0_02_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_GPIO0_02_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_02_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_GPIO0_02_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_GPIO0_02_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_SCU_GPIO0_02_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_SCU_GPIO0_02_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_02_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_GPIO0_02_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_GPIO0_02_lp_config_MASK       (0x1800000U)
#define IOMUXD_SCU_GPIO0_02_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_GPIO0_02_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_02_lp_config_SHIFT)) & IOMUXD_SCU_GPIO0_02_lp_config_MASK)
#define IOMUXD_SCU_GPIO0_02_sw_config_MASK       (0x6000000U)
#define IOMUXD_SCU_GPIO0_02_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_GPIO0_02_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_02_sw_config_SHIFT)) & IOMUXD_SCU_GPIO0_02_sw_config_MASK)
#define IOMUXD_SCU_GPIO0_02_mux_mode_MASK        (0x38000000U)
#define IOMUXD_SCU_GPIO0_02_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.GPIO0.IO02
 *  0b001..SCU.GPIO0.IOXX_PMIC_GPU0_ON
 *  0b011..LSIO.GPIO0.IO30
 */
#define IOMUXD_SCU_GPIO0_02_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_02_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_02_mux_mode_MASK)
#define IOMUXD_SCU_GPIO0_02_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_SCU_GPIO0_02_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_GPIO0_02_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_02_update_pad_ctl_SHIFT)) & IOMUXD_SCU_GPIO0_02_update_pad_ctl_MASK)
#define IOMUXD_SCU_GPIO0_02_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_GPIO0_02_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_GPIO0_02_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_02_update_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_02_update_mux_mode_MASK)
/*! @} */

/*! @name SCU_GPIO0_03 - SCU_GPIO0_03 */
/*! @{ */
#define IOMUXD_SCU_GPIO0_03_DSE_MASK             (0x7U)
#define IOMUXD_SCU_GPIO0_03_DSE_SHIFT            (0U)
#define IOMUXD_SCU_GPIO0_03_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_03_DSE_SHIFT)) & IOMUXD_SCU_GPIO0_03_DSE_MASK)
#define IOMUXD_SCU_GPIO0_03_SCU_GPIO0_03_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_GPIO0_03_SCU_GPIO0_03_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_GPIO0_03_SCU_GPIO0_03_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_03_SCU_GPIO0_03_reserved_3_4_SHIFT)) & IOMUXD_SCU_GPIO0_03_SCU_GPIO0_03_reserved_3_4_MASK)
#define IOMUXD_SCU_GPIO0_03_PULL_MASK            (0x60U)
#define IOMUXD_SCU_GPIO0_03_PULL_SHIFT           (5U)
#define IOMUXD_SCU_GPIO0_03_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_03_PULL_SHIFT)) & IOMUXD_SCU_GPIO0_03_PULL_MASK)
#define IOMUXD_SCU_GPIO0_03_SCU_GPIO0_03_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_GPIO0_03_SCU_GPIO0_03_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_GPIO0_03_SCU_GPIO0_03_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_03_SCU_GPIO0_03_reserved_7_18_SHIFT)) & IOMUXD_SCU_GPIO0_03_SCU_GPIO0_03_reserved_7_18_MASK)
#define IOMUXD_SCU_GPIO0_03_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_SCU_GPIO0_03_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_GPIO0_03_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_03_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_GPIO0_03_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_GPIO0_03_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_SCU_GPIO0_03_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_SCU_GPIO0_03_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_03_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_GPIO0_03_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_GPIO0_03_lp_config_MASK       (0x1800000U)
#define IOMUXD_SCU_GPIO0_03_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_GPIO0_03_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_03_lp_config_SHIFT)) & IOMUXD_SCU_GPIO0_03_lp_config_MASK)
#define IOMUXD_SCU_GPIO0_03_sw_config_MASK       (0x6000000U)
#define IOMUXD_SCU_GPIO0_03_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_GPIO0_03_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_03_sw_config_SHIFT)) & IOMUXD_SCU_GPIO0_03_sw_config_MASK)
#define IOMUXD_SCU_GPIO0_03_mux_mode_MASK        (0x38000000U)
#define IOMUXD_SCU_GPIO0_03_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.GPIO0.IO03
 *  0b001..SCU.GPIO0.IOXX_PMIC_GPU1_ON
 *  0b011..LSIO.GPIO0.IO31
 */
#define IOMUXD_SCU_GPIO0_03_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_03_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_03_mux_mode_MASK)
#define IOMUXD_SCU_GPIO0_03_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_SCU_GPIO0_03_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_GPIO0_03_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_03_update_pad_ctl_SHIFT)) & IOMUXD_SCU_GPIO0_03_update_pad_ctl_MASK)
#define IOMUXD_SCU_GPIO0_03_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_GPIO0_03_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_GPIO0_03_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_03_update_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_03_update_mux_mode_MASK)
/*! @} */

/*! @name SCU_GPIO0_04 - SCU_GPIO0_04 */
/*! @{ */
#define IOMUXD_SCU_GPIO0_04_DSE_MASK             (0x7U)
#define IOMUXD_SCU_GPIO0_04_DSE_SHIFT            (0U)
#define IOMUXD_SCU_GPIO0_04_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_04_DSE_SHIFT)) & IOMUXD_SCU_GPIO0_04_DSE_MASK)
#define IOMUXD_SCU_GPIO0_04_SCU_GPIO0_04_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_GPIO0_04_SCU_GPIO0_04_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_GPIO0_04_SCU_GPIO0_04_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_04_SCU_GPIO0_04_reserved_3_4_SHIFT)) & IOMUXD_SCU_GPIO0_04_SCU_GPIO0_04_reserved_3_4_MASK)
#define IOMUXD_SCU_GPIO0_04_PULL_MASK            (0x60U)
#define IOMUXD_SCU_GPIO0_04_PULL_SHIFT           (5U)
#define IOMUXD_SCU_GPIO0_04_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_04_PULL_SHIFT)) & IOMUXD_SCU_GPIO0_04_PULL_MASK)
#define IOMUXD_SCU_GPIO0_04_SCU_GPIO0_04_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_GPIO0_04_SCU_GPIO0_04_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_GPIO0_04_SCU_GPIO0_04_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_04_SCU_GPIO0_04_reserved_7_18_SHIFT)) & IOMUXD_SCU_GPIO0_04_SCU_GPIO0_04_reserved_7_18_MASK)
#define IOMUXD_SCU_GPIO0_04_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_SCU_GPIO0_04_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_GPIO0_04_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_04_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_GPIO0_04_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_GPIO0_04_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_SCU_GPIO0_04_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_SCU_GPIO0_04_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_04_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_GPIO0_04_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_GPIO0_04_lp_config_MASK       (0x1800000U)
#define IOMUXD_SCU_GPIO0_04_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_GPIO0_04_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_04_lp_config_SHIFT)) & IOMUXD_SCU_GPIO0_04_lp_config_MASK)
#define IOMUXD_SCU_GPIO0_04_sw_config_MASK       (0x6000000U)
#define IOMUXD_SCU_GPIO0_04_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_GPIO0_04_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_04_sw_config_SHIFT)) & IOMUXD_SCU_GPIO0_04_sw_config_MASK)
#define IOMUXD_SCU_GPIO0_04_mux_mode_MASK        (0x38000000U)
#define IOMUXD_SCU_GPIO0_04_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.GPIO0.IO04
 *  0b001..SCU.GPIO0.IOXX_PMIC_A72_ON
 *  0b011..LSIO.GPIO1.IO00
 */
#define IOMUXD_SCU_GPIO0_04_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_04_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_04_mux_mode_MASK)
#define IOMUXD_SCU_GPIO0_04_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_SCU_GPIO0_04_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_GPIO0_04_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_04_update_pad_ctl_SHIFT)) & IOMUXD_SCU_GPIO0_04_update_pad_ctl_MASK)
#define IOMUXD_SCU_GPIO0_04_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_GPIO0_04_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_GPIO0_04_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_04_update_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_04_update_mux_mode_MASK)
/*! @} */

/*! @name SCU_GPIO0_05 - SCU_GPIO0_05 */
/*! @{ */
#define IOMUXD_SCU_GPIO0_05_DSE_MASK             (0x7U)
#define IOMUXD_SCU_GPIO0_05_DSE_SHIFT            (0U)
#define IOMUXD_SCU_GPIO0_05_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_05_DSE_SHIFT)) & IOMUXD_SCU_GPIO0_05_DSE_MASK)
#define IOMUXD_SCU_GPIO0_05_SCU_GPIO0_05_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_GPIO0_05_SCU_GPIO0_05_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_GPIO0_05_SCU_GPIO0_05_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_05_SCU_GPIO0_05_reserved_3_4_SHIFT)) & IOMUXD_SCU_GPIO0_05_SCU_GPIO0_05_reserved_3_4_MASK)
#define IOMUXD_SCU_GPIO0_05_PULL_MASK            (0x60U)
#define IOMUXD_SCU_GPIO0_05_PULL_SHIFT           (5U)
#define IOMUXD_SCU_GPIO0_05_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_05_PULL_SHIFT)) & IOMUXD_SCU_GPIO0_05_PULL_MASK)
#define IOMUXD_SCU_GPIO0_05_SCU_GPIO0_05_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_GPIO0_05_SCU_GPIO0_05_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_GPIO0_05_SCU_GPIO0_05_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_05_SCU_GPIO0_05_reserved_7_18_SHIFT)) & IOMUXD_SCU_GPIO0_05_SCU_GPIO0_05_reserved_7_18_MASK)
#define IOMUXD_SCU_GPIO0_05_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_SCU_GPIO0_05_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_GPIO0_05_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_05_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_GPIO0_05_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_GPIO0_05_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_SCU_GPIO0_05_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_SCU_GPIO0_05_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_05_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_GPIO0_05_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_GPIO0_05_lp_config_MASK       (0x1800000U)
#define IOMUXD_SCU_GPIO0_05_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_GPIO0_05_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_05_lp_config_SHIFT)) & IOMUXD_SCU_GPIO0_05_lp_config_MASK)
#define IOMUXD_SCU_GPIO0_05_sw_config_MASK       (0x6000000U)
#define IOMUXD_SCU_GPIO0_05_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_GPIO0_05_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_05_sw_config_SHIFT)) & IOMUXD_SCU_GPIO0_05_sw_config_MASK)
#define IOMUXD_SCU_GPIO0_05_mux_mode_MASK        (0x38000000U)
#define IOMUXD_SCU_GPIO0_05_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.GPIO0.IO05
 *  0b001..SCU.GPIO0.IOXX_PMIC_A53_ON
 *  0b011..LSIO.GPIO1.IO01
 */
#define IOMUXD_SCU_GPIO0_05_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_05_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_05_mux_mode_MASK)
#define IOMUXD_SCU_GPIO0_05_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_SCU_GPIO0_05_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_GPIO0_05_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_05_update_pad_ctl_SHIFT)) & IOMUXD_SCU_GPIO0_05_update_pad_ctl_MASK)
#define IOMUXD_SCU_GPIO0_05_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_GPIO0_05_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_GPIO0_05_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_05_update_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_05_update_mux_mode_MASK)
/*! @} */

/*! @name SCU_GPIO0_06 - SCU_GPIO0_06 */
/*! @{ */
#define IOMUXD_SCU_GPIO0_06_DSE_MASK             (0x7U)
#define IOMUXD_SCU_GPIO0_06_DSE_SHIFT            (0U)
#define IOMUXD_SCU_GPIO0_06_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_06_DSE_SHIFT)) & IOMUXD_SCU_GPIO0_06_DSE_MASK)
#define IOMUXD_SCU_GPIO0_06_SCU_GPIO0_06_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_GPIO0_06_SCU_GPIO0_06_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_GPIO0_06_SCU_GPIO0_06_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_06_SCU_GPIO0_06_reserved_3_4_SHIFT)) & IOMUXD_SCU_GPIO0_06_SCU_GPIO0_06_reserved_3_4_MASK)
#define IOMUXD_SCU_GPIO0_06_PULL_MASK            (0x60U)
#define IOMUXD_SCU_GPIO0_06_PULL_SHIFT           (5U)
#define IOMUXD_SCU_GPIO0_06_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_06_PULL_SHIFT)) & IOMUXD_SCU_GPIO0_06_PULL_MASK)
#define IOMUXD_SCU_GPIO0_06_SCU_GPIO0_06_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_GPIO0_06_SCU_GPIO0_06_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_GPIO0_06_SCU_GPIO0_06_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_06_SCU_GPIO0_06_reserved_7_18_SHIFT)) & IOMUXD_SCU_GPIO0_06_SCU_GPIO0_06_reserved_7_18_MASK)
#define IOMUXD_SCU_GPIO0_06_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_SCU_GPIO0_06_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_GPIO0_06_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_06_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_GPIO0_06_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_GPIO0_06_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_SCU_GPIO0_06_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_SCU_GPIO0_06_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_06_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_GPIO0_06_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_GPIO0_06_lp_config_MASK       (0x1800000U)
#define IOMUXD_SCU_GPIO0_06_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_GPIO0_06_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_06_lp_config_SHIFT)) & IOMUXD_SCU_GPIO0_06_lp_config_MASK)
#define IOMUXD_SCU_GPIO0_06_sw_config_MASK       (0x6000000U)
#define IOMUXD_SCU_GPIO0_06_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_GPIO0_06_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_06_sw_config_SHIFT)) & IOMUXD_SCU_GPIO0_06_sw_config_MASK)
#define IOMUXD_SCU_GPIO0_06_mux_mode_MASK        (0x38000000U)
#define IOMUXD_SCU_GPIO0_06_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.GPIO0.IO06
 *  0b001..SCU.TPM0.CH0
 *  0b011..LSIO.GPIO1.IO02
 */
#define IOMUXD_SCU_GPIO0_06_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_06_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_06_mux_mode_MASK)
#define IOMUXD_SCU_GPIO0_06_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_SCU_GPIO0_06_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_GPIO0_06_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_06_update_pad_ctl_SHIFT)) & IOMUXD_SCU_GPIO0_06_update_pad_ctl_MASK)
#define IOMUXD_SCU_GPIO0_06_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_GPIO0_06_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_GPIO0_06_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_06_update_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_06_update_mux_mode_MASK)
/*! @} */

/*! @name SCU_GPIO0_07 - SCU_GPIO0_07 */
/*! @{ */
#define IOMUXD_SCU_GPIO0_07_DSE_MASK             (0x7U)
#define IOMUXD_SCU_GPIO0_07_DSE_SHIFT            (0U)
#define IOMUXD_SCU_GPIO0_07_DSE(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_07_DSE_SHIFT)) & IOMUXD_SCU_GPIO0_07_DSE_MASK)
#define IOMUXD_SCU_GPIO0_07_SCU_GPIO0_07_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_GPIO0_07_SCU_GPIO0_07_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_GPIO0_07_SCU_GPIO0_07_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_07_SCU_GPIO0_07_reserved_3_4_SHIFT)) & IOMUXD_SCU_GPIO0_07_SCU_GPIO0_07_reserved_3_4_MASK)
#define IOMUXD_SCU_GPIO0_07_PULL_MASK            (0x60U)
#define IOMUXD_SCU_GPIO0_07_PULL_SHIFT           (5U)
#define IOMUXD_SCU_GPIO0_07_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_07_PULL_SHIFT)) & IOMUXD_SCU_GPIO0_07_PULL_MASK)
#define IOMUXD_SCU_GPIO0_07_SCU_GPIO0_07_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_GPIO0_07_SCU_GPIO0_07_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_GPIO0_07_SCU_GPIO0_07_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_07_SCU_GPIO0_07_reserved_7_18_SHIFT)) & IOMUXD_SCU_GPIO0_07_SCU_GPIO0_07_reserved_7_18_MASK)
#define IOMUXD_SCU_GPIO0_07_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_SCU_GPIO0_07_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_GPIO0_07_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_07_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_GPIO0_07_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_GPIO0_07_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_SCU_GPIO0_07_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_SCU_GPIO0_07_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_07_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_GPIO0_07_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_GPIO0_07_lp_config_MASK       (0x1800000U)
#define IOMUXD_SCU_GPIO0_07_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_GPIO0_07_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_07_lp_config_SHIFT)) & IOMUXD_SCU_GPIO0_07_lp_config_MASK)
#define IOMUXD_SCU_GPIO0_07_sw_config_MASK       (0x6000000U)
#define IOMUXD_SCU_GPIO0_07_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_GPIO0_07_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_07_sw_config_SHIFT)) & IOMUXD_SCU_GPIO0_07_sw_config_MASK)
#define IOMUXD_SCU_GPIO0_07_mux_mode_MASK        (0x38000000U)
#define IOMUXD_SCU_GPIO0_07_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.GPIO0.IO07
 *  0b001..SCU.TPM0.CH1
 *  0b010..SCU.DSC.RTC_CLOCK_OUTPUT_32K
 *  0b011..LSIO.GPIO1.IO03
 */
#define IOMUXD_SCU_GPIO0_07_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_07_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_07_mux_mode_MASK)
#define IOMUXD_SCU_GPIO0_07_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_SCU_GPIO0_07_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_GPIO0_07_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_07_update_pad_ctl_SHIFT)) & IOMUXD_SCU_GPIO0_07_update_pad_ctl_MASK)
#define IOMUXD_SCU_GPIO0_07_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_GPIO0_07_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_GPIO0_07_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_07_update_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_07_update_mux_mode_MASK)
/*! @} */

/*! @name SCU_BOOT_MODE0 - SCU_BOOT_MODE0 */
/*! @{ */
#define IOMUXD_SCU_BOOT_MODE0_DSE_MASK           (0x7U)
#define IOMUXD_SCU_BOOT_MODE0_DSE_SHIFT          (0U)
#define IOMUXD_SCU_BOOT_MODE0_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_DSE_MASK)
#define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_MASK)
#define IOMUXD_SCU_BOOT_MODE0_PULL_MASK          (0x60U)
#define IOMUXD_SCU_BOOT_MODE0_PULL_SHIFT         (5U)
#define IOMUXD_SCU_BOOT_MODE0_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_PULL_MASK)
#define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_MASK)
#define IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_BOOT_MODE0_lp_config_MASK     (0x1800000U)
#define IOMUXD_SCU_BOOT_MODE0_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_BOOT_MODE0_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_lp_config_MASK)
#define IOMUXD_SCU_BOOT_MODE0_sw_config_MASK     (0x6000000U)
#define IOMUXD_SCU_BOOT_MODE0_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_BOOT_MODE0_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_sw_config_MASK)
#define IOMUXD_SCU_BOOT_MODE0_mux_mode_MASK      (0x38000000U)
#define IOMUXD_SCU_BOOT_MODE0_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.DSC.BOOT_MODE0
 */
#define IOMUXD_SCU_BOOT_MODE0_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_mux_mode_MASK)
#define IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_BOOT_MODE0_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_MASK)
#define IOMUXD_SCU_BOOT_MODE0_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_BOOT_MODE0_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_BOOT_MODE0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_update_mux_mode_MASK)
/*! @} */

/*! @name SCU_BOOT_MODE1 - SCU_BOOT_MODE1 */
/*! @{ */
#define IOMUXD_SCU_BOOT_MODE1_DSE_MASK           (0x7U)
#define IOMUXD_SCU_BOOT_MODE1_DSE_SHIFT          (0U)
#define IOMUXD_SCU_BOOT_MODE1_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_DSE_MASK)
#define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_MASK)
#define IOMUXD_SCU_BOOT_MODE1_PULL_MASK          (0x60U)
#define IOMUXD_SCU_BOOT_MODE1_PULL_SHIFT         (5U)
#define IOMUXD_SCU_BOOT_MODE1_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_PULL_MASK)
#define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_MASK)
#define IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_BOOT_MODE1_lp_config_MASK     (0x1800000U)
#define IOMUXD_SCU_BOOT_MODE1_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_BOOT_MODE1_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_lp_config_MASK)
#define IOMUXD_SCU_BOOT_MODE1_sw_config_MASK     (0x6000000U)
#define IOMUXD_SCU_BOOT_MODE1_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_BOOT_MODE1_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_sw_config_MASK)
#define IOMUXD_SCU_BOOT_MODE1_mux_mode_MASK      (0x38000000U)
#define IOMUXD_SCU_BOOT_MODE1_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.DSC.BOOT_MODE1
 */
#define IOMUXD_SCU_BOOT_MODE1_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_mux_mode_MASK)
#define IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_BOOT_MODE1_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_MASK)
#define IOMUXD_SCU_BOOT_MODE1_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_BOOT_MODE1_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_BOOT_MODE1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_update_mux_mode_MASK)
/*! @} */

/*! @name SCU_BOOT_MODE2 - SCU_BOOT_MODE2 */
/*! @{ */
#define IOMUXD_SCU_BOOT_MODE2_DSE_MASK           (0x7U)
#define IOMUXD_SCU_BOOT_MODE2_DSE_SHIFT          (0U)
#define IOMUXD_SCU_BOOT_MODE2_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_DSE_MASK)
#define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_MASK)
#define IOMUXD_SCU_BOOT_MODE2_PULL_MASK          (0x60U)
#define IOMUXD_SCU_BOOT_MODE2_PULL_SHIFT         (5U)
#define IOMUXD_SCU_BOOT_MODE2_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_PULL_MASK)
#define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_MASK)
#define IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_BOOT_MODE2_lp_config_MASK     (0x1800000U)
#define IOMUXD_SCU_BOOT_MODE2_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_BOOT_MODE2_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_lp_config_MASK)
#define IOMUXD_SCU_BOOT_MODE2_sw_config_MASK     (0x6000000U)
#define IOMUXD_SCU_BOOT_MODE2_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_BOOT_MODE2_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_sw_config_MASK)
#define IOMUXD_SCU_BOOT_MODE2_mux_mode_MASK      (0x38000000U)
#define IOMUXD_SCU_BOOT_MODE2_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.DSC.BOOT_MODE2
 */
#define IOMUXD_SCU_BOOT_MODE2_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_mux_mode_MASK)
#define IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_BOOT_MODE2_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_MASK)
#define IOMUXD_SCU_BOOT_MODE2_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_BOOT_MODE2_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_BOOT_MODE2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_update_mux_mode_MASK)
/*! @} */

/*! @name SCU_BOOT_MODE3 - SCU_BOOT_MODE3 */
/*! @{ */
#define IOMUXD_SCU_BOOT_MODE3_DSE_MASK           (0x7U)
#define IOMUXD_SCU_BOOT_MODE3_DSE_SHIFT          (0U)
#define IOMUXD_SCU_BOOT_MODE3_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_DSE_MASK)
#define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_MASK)
#define IOMUXD_SCU_BOOT_MODE3_PULL_MASK          (0x60U)
#define IOMUXD_SCU_BOOT_MODE3_PULL_SHIFT         (5U)
#define IOMUXD_SCU_BOOT_MODE3_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_PULL_MASK)
#define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_MASK)
#define IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_BOOT_MODE3_lp_config_MASK     (0x1800000U)
#define IOMUXD_SCU_BOOT_MODE3_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_BOOT_MODE3_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_lp_config_MASK)
#define IOMUXD_SCU_BOOT_MODE3_sw_config_MASK     (0x6000000U)
#define IOMUXD_SCU_BOOT_MODE3_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_BOOT_MODE3_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_sw_config_MASK)
#define IOMUXD_SCU_BOOT_MODE3_mux_mode_MASK      (0x38000000U)
#define IOMUXD_SCU_BOOT_MODE3_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.DSC.BOOT_MODE3
 */
#define IOMUXD_SCU_BOOT_MODE3_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_mux_mode_MASK)
#define IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_BOOT_MODE3_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_MASK)
#define IOMUXD_SCU_BOOT_MODE3_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_BOOT_MODE3_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_BOOT_MODE3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_update_mux_mode_MASK)
/*! @} */

/*! @name SCU_BOOT_MODE4 - SCU_BOOT_MODE4 */
/*! @{ */
#define IOMUXD_SCU_BOOT_MODE4_DSE_MASK           (0x7U)
#define IOMUXD_SCU_BOOT_MODE4_DSE_SHIFT          (0U)
#define IOMUXD_SCU_BOOT_MODE4_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE4_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE4_DSE_MASK)
#define IOMUXD_SCU_BOOT_MODE4_SCU_BOOT_MODE4_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_BOOT_MODE4_SCU_BOOT_MODE4_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_BOOT_MODE4_SCU_BOOT_MODE4_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE4_SCU_BOOT_MODE4_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE4_SCU_BOOT_MODE4_reserved_3_4_MASK)
#define IOMUXD_SCU_BOOT_MODE4_PULL_MASK          (0x60U)
#define IOMUXD_SCU_BOOT_MODE4_PULL_SHIFT         (5U)
#define IOMUXD_SCU_BOOT_MODE4_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE4_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE4_PULL_MASK)
#define IOMUXD_SCU_BOOT_MODE4_SCU_BOOT_MODE4_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_BOOT_MODE4_SCU_BOOT_MODE4_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_BOOT_MODE4_SCU_BOOT_MODE4_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE4_SCU_BOOT_MODE4_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE4_SCU_BOOT_MODE4_reserved_7_18_MASK)
#define IOMUXD_SCU_BOOT_MODE4_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_SCU_BOOT_MODE4_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_BOOT_MODE4_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE4_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE4_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_BOOT_MODE4_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_SCU_BOOT_MODE4_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_SCU_BOOT_MODE4_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE4_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE4_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_BOOT_MODE4_lp_config_MASK     (0x1800000U)
#define IOMUXD_SCU_BOOT_MODE4_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_BOOT_MODE4_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE4_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE4_lp_config_MASK)
#define IOMUXD_SCU_BOOT_MODE4_sw_config_MASK     (0x6000000U)
#define IOMUXD_SCU_BOOT_MODE4_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_BOOT_MODE4_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE4_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE4_sw_config_MASK)
#define IOMUXD_SCU_BOOT_MODE4_mux_mode_MASK      (0x38000000U)
#define IOMUXD_SCU_BOOT_MODE4_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.DSC.BOOT_MODE4
 *  0b001..SCU.PMIC_I2C.SCL
 */
#define IOMUXD_SCU_BOOT_MODE4_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE4_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE4_mux_mode_MASK)
#define IOMUXD_SCU_BOOT_MODE4_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_SCU_BOOT_MODE4_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_BOOT_MODE4_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE4_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE4_update_pad_ctl_MASK)
#define IOMUXD_SCU_BOOT_MODE4_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_BOOT_MODE4_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_BOOT_MODE4_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE4_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE4_update_mux_mode_MASK)
/*! @} */

/*! @name SCU_BOOT_MODE5 - SCU_BOOT_MODE5 */
/*! @{ */
#define IOMUXD_SCU_BOOT_MODE5_DSE_MASK           (0x7U)
#define IOMUXD_SCU_BOOT_MODE5_DSE_SHIFT          (0U)
#define IOMUXD_SCU_BOOT_MODE5_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE5_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE5_DSE_MASK)
#define IOMUXD_SCU_BOOT_MODE5_SCU_BOOT_MODE5_reserved_3_4_MASK (0x18U)
#define IOMUXD_SCU_BOOT_MODE5_SCU_BOOT_MODE5_reserved_3_4_SHIFT (3U)
#define IOMUXD_SCU_BOOT_MODE5_SCU_BOOT_MODE5_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE5_SCU_BOOT_MODE5_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE5_SCU_BOOT_MODE5_reserved_3_4_MASK)
#define IOMUXD_SCU_BOOT_MODE5_PULL_MASK          (0x60U)
#define IOMUXD_SCU_BOOT_MODE5_PULL_SHIFT         (5U)
#define IOMUXD_SCU_BOOT_MODE5_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE5_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE5_PULL_MASK)
#define IOMUXD_SCU_BOOT_MODE5_SCU_BOOT_MODE5_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SCU_BOOT_MODE5_SCU_BOOT_MODE5_reserved_7_18_SHIFT (7U)
#define IOMUXD_SCU_BOOT_MODE5_SCU_BOOT_MODE5_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE5_SCU_BOOT_MODE5_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE5_SCU_BOOT_MODE5_reserved_7_18_MASK)
#define IOMUXD_SCU_BOOT_MODE5_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_SCU_BOOT_MODE5_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SCU_BOOT_MODE5_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE5_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE5_WAKEUP_CTRL_MASK)
#define IOMUXD_SCU_BOOT_MODE5_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_SCU_BOOT_MODE5_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_SCU_BOOT_MODE5_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE5_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE5_WAKEUP_MASK_MASK)
#define IOMUXD_SCU_BOOT_MODE5_lp_config_MASK     (0x1800000U)
#define IOMUXD_SCU_BOOT_MODE5_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SCU_BOOT_MODE5_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE5_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE5_lp_config_MASK)
#define IOMUXD_SCU_BOOT_MODE5_sw_config_MASK     (0x6000000U)
#define IOMUXD_SCU_BOOT_MODE5_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SCU_BOOT_MODE5_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE5_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE5_sw_config_MASK)
#define IOMUXD_SCU_BOOT_MODE5_mux_mode_MASK      (0x38000000U)
#define IOMUXD_SCU_BOOT_MODE5_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..SCU.DSC.BOOT_MODE5
 *  0b001..SCU.PMIC_I2C.SDA
 */
#define IOMUXD_SCU_BOOT_MODE5_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE5_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE5_mux_mode_MASK)
#define IOMUXD_SCU_BOOT_MODE5_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_SCU_BOOT_MODE5_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SCU_BOOT_MODE5_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE5_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE5_update_pad_ctl_MASK)
#define IOMUXD_SCU_BOOT_MODE5_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SCU_BOOT_MODE5_update_mux_mode_SHIFT (31U)
#define IOMUXD_SCU_BOOT_MODE5_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE5_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE5_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_0_3 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_02_MASK (0x1U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_02_SHIFT (0U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_02(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_02_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_02_MASK)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_03_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_03_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_03(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_03_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_03_MASK)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_04_MASK (0x4U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_04_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_04(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_04_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_04_MASK)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_05_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_05_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_05(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_05_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_05_MASK)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_06_MASK (0x10U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_06_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_06(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_06_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_06_MASK)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_07_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_07_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_07(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_07_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_3_SCU_GPIO0_07_MASK)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE0_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE0_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE0_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE0_MASK)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE1_MASK (0x80U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE1_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE1_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE1_MASK)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE2_MASK (0x100U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE2_SHIFT (8U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE2_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE2_MASK)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE3_MASK (0x200U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE3_SHIFT (9U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE3_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE3_MASK)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE4_MASK (0x400U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE4_SHIFT (10U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE4_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE4_MASK)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE5_MASK (0x800U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE5_SHIFT (11U)
#define IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE5_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_3_SCU_BOOT_MODE5_MASK)
#define IOMUXD_IOMUXD_GROUP_0_3_iomuxd_group_0_3_reserved_12_31_MASK (0xFFFFF000U)
#define IOMUXD_IOMUXD_GROUP_0_3_iomuxd_group_0_3_reserved_12_31_SHIFT (12U)
#define IOMUXD_IOMUXD_GROUP_0_3_iomuxd_group_0_3_reserved_12_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_3_iomuxd_group_0_3_reserved_12_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_3_iomuxd_group_0_3_reserved_12_31_MASK)
/*! @} */

/*! @name LVDS0_GPIO00 - LVDS0_GPIO00 */
/*! @{ */
#define IOMUXD_LVDS0_GPIO00_PDRV_MASK            (0x1U)
#define IOMUXD_LVDS0_GPIO00_PDRV_SHIFT           (0U)
#define IOMUXD_LVDS0_GPIO00_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO00_PDRV_SHIFT)) & IOMUXD_LVDS0_GPIO00_PDRV_MASK)
#define IOMUXD_LVDS0_GPIO00_LVDS0_GPIO00_reserved_1_4_MASK (0x1EU)
#define IOMUXD_LVDS0_GPIO00_LVDS0_GPIO00_reserved_1_4_SHIFT (1U)
#define IOMUXD_LVDS0_GPIO00_LVDS0_GPIO00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO00_LVDS0_GPIO00_reserved_1_4_SHIFT)) & IOMUXD_LVDS0_GPIO00_LVDS0_GPIO00_reserved_1_4_MASK)
#define IOMUXD_LVDS0_GPIO00_PULL_MASK            (0x60U)
#define IOMUXD_LVDS0_GPIO00_PULL_SHIFT           (5U)
#define IOMUXD_LVDS0_GPIO00_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO00_PULL_SHIFT)) & IOMUXD_LVDS0_GPIO00_PULL_MASK)
#define IOMUXD_LVDS0_GPIO00_LVDS0_GPIO00_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_LVDS0_GPIO00_LVDS0_GPIO00_reserved_7_18_SHIFT (7U)
#define IOMUXD_LVDS0_GPIO00_LVDS0_GPIO00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO00_LVDS0_GPIO00_reserved_7_18_SHIFT)) & IOMUXD_LVDS0_GPIO00_LVDS0_GPIO00_reserved_7_18_MASK)
#define IOMUXD_LVDS0_GPIO00_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_LVDS0_GPIO00_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_LVDS0_GPIO00_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO00_WAKEUP_CTRL_SHIFT)) & IOMUXD_LVDS0_GPIO00_WAKEUP_CTRL_MASK)
#define IOMUXD_LVDS0_GPIO00_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_LVDS0_GPIO00_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_LVDS0_GPIO00_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO00_WAKEUP_MASK_SHIFT)) & IOMUXD_LVDS0_GPIO00_WAKEUP_MASK_MASK)
#define IOMUXD_LVDS0_GPIO00_lp_config_MASK       (0x1800000U)
#define IOMUXD_LVDS0_GPIO00_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_LVDS0_GPIO00_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO00_lp_config_SHIFT)) & IOMUXD_LVDS0_GPIO00_lp_config_MASK)
#define IOMUXD_LVDS0_GPIO00_sw_config_MASK       (0x6000000U)
#define IOMUXD_LVDS0_GPIO00_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_LVDS0_GPIO00_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO00_sw_config_SHIFT)) & IOMUXD_LVDS0_GPIO00_sw_config_MASK)
#define IOMUXD_LVDS0_GPIO00_mux_mode_MASK        (0x38000000U)
#define IOMUXD_LVDS0_GPIO00_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LVDS0.GPIO0.IO00
 *  0b001..LVDS0.PWM0.OUT
 *  0b011..LSIO.GPIO1.IO04
 */
#define IOMUXD_LVDS0_GPIO00_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO00_mux_mode_SHIFT)) & IOMUXD_LVDS0_GPIO00_mux_mode_MASK)
#define IOMUXD_LVDS0_GPIO00_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_LVDS0_GPIO00_update_pad_ctl_SHIFT (30U)
#define IOMUXD_LVDS0_GPIO00_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO00_update_pad_ctl_SHIFT)) & IOMUXD_LVDS0_GPIO00_update_pad_ctl_MASK)
#define IOMUXD_LVDS0_GPIO00_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_LVDS0_GPIO00_update_mux_mode_SHIFT (31U)
#define IOMUXD_LVDS0_GPIO00_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO00_update_mux_mode_SHIFT)) & IOMUXD_LVDS0_GPIO00_update_mux_mode_MASK)
/*! @} */

/*! @name LVDS0_GPIO01 - LVDS0_GPIO01 */
/*! @{ */
#define IOMUXD_LVDS0_GPIO01_PDRV_MASK            (0x1U)
#define IOMUXD_LVDS0_GPIO01_PDRV_SHIFT           (0U)
#define IOMUXD_LVDS0_GPIO01_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO01_PDRV_SHIFT)) & IOMUXD_LVDS0_GPIO01_PDRV_MASK)
#define IOMUXD_LVDS0_GPIO01_LVDS0_GPIO01_reserved_1_4_MASK (0x1EU)
#define IOMUXD_LVDS0_GPIO01_LVDS0_GPIO01_reserved_1_4_SHIFT (1U)
#define IOMUXD_LVDS0_GPIO01_LVDS0_GPIO01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO01_LVDS0_GPIO01_reserved_1_4_SHIFT)) & IOMUXD_LVDS0_GPIO01_LVDS0_GPIO01_reserved_1_4_MASK)
#define IOMUXD_LVDS0_GPIO01_PULL_MASK            (0x60U)
#define IOMUXD_LVDS0_GPIO01_PULL_SHIFT           (5U)
#define IOMUXD_LVDS0_GPIO01_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO01_PULL_SHIFT)) & IOMUXD_LVDS0_GPIO01_PULL_MASK)
#define IOMUXD_LVDS0_GPIO01_LVDS0_GPIO01_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_LVDS0_GPIO01_LVDS0_GPIO01_reserved_7_18_SHIFT (7U)
#define IOMUXD_LVDS0_GPIO01_LVDS0_GPIO01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO01_LVDS0_GPIO01_reserved_7_18_SHIFT)) & IOMUXD_LVDS0_GPIO01_LVDS0_GPIO01_reserved_7_18_MASK)
#define IOMUXD_LVDS0_GPIO01_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_LVDS0_GPIO01_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_LVDS0_GPIO01_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO01_WAKEUP_CTRL_SHIFT)) & IOMUXD_LVDS0_GPIO01_WAKEUP_CTRL_MASK)
#define IOMUXD_LVDS0_GPIO01_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_LVDS0_GPIO01_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_LVDS0_GPIO01_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO01_WAKEUP_MASK_SHIFT)) & IOMUXD_LVDS0_GPIO01_WAKEUP_MASK_MASK)
#define IOMUXD_LVDS0_GPIO01_lp_config_MASK       (0x1800000U)
#define IOMUXD_LVDS0_GPIO01_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_LVDS0_GPIO01_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO01_lp_config_SHIFT)) & IOMUXD_LVDS0_GPIO01_lp_config_MASK)
#define IOMUXD_LVDS0_GPIO01_sw_config_MASK       (0x6000000U)
#define IOMUXD_LVDS0_GPIO01_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_LVDS0_GPIO01_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO01_sw_config_SHIFT)) & IOMUXD_LVDS0_GPIO01_sw_config_MASK)
#define IOMUXD_LVDS0_GPIO01_mux_mode_MASK        (0x38000000U)
#define IOMUXD_LVDS0_GPIO01_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LVDS0.GPIO0.IO01
 *  0b011..LSIO.GPIO1.IO05
 */
#define IOMUXD_LVDS0_GPIO01_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO01_mux_mode_SHIFT)) & IOMUXD_LVDS0_GPIO01_mux_mode_MASK)
#define IOMUXD_LVDS0_GPIO01_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_LVDS0_GPIO01_update_pad_ctl_SHIFT (30U)
#define IOMUXD_LVDS0_GPIO01_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO01_update_pad_ctl_SHIFT)) & IOMUXD_LVDS0_GPIO01_update_pad_ctl_MASK)
#define IOMUXD_LVDS0_GPIO01_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_LVDS0_GPIO01_update_mux_mode_SHIFT (31U)
#define IOMUXD_LVDS0_GPIO01_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_GPIO01_update_mux_mode_SHIFT)) & IOMUXD_LVDS0_GPIO01_update_mux_mode_MASK)
/*! @} */

/*! @name LVDS0_I2C0_SCL - LVDS0_I2C0_SCL */
/*! @{ */
#define IOMUXD_LVDS0_I2C0_SCL_PDRV_MASK          (0x1U)
#define IOMUXD_LVDS0_I2C0_SCL_PDRV_SHIFT         (0U)
#define IOMUXD_LVDS0_I2C0_SCL_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SCL_PDRV_SHIFT)) & IOMUXD_LVDS0_I2C0_SCL_PDRV_MASK)
#define IOMUXD_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL_reserved_1_4_MASK (0x1EU)
#define IOMUXD_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL_reserved_1_4_SHIFT (1U)
#define IOMUXD_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL_reserved_1_4_SHIFT)) & IOMUXD_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL_reserved_1_4_MASK)
#define IOMUXD_LVDS0_I2C0_SCL_PULL_MASK          (0x60U)
#define IOMUXD_LVDS0_I2C0_SCL_PULL_SHIFT         (5U)
#define IOMUXD_LVDS0_I2C0_SCL_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SCL_PULL_SHIFT)) & IOMUXD_LVDS0_I2C0_SCL_PULL_MASK)
#define IOMUXD_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL_reserved_7_18_SHIFT (7U)
#define IOMUXD_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL_reserved_7_18_MASK)
#define IOMUXD_LVDS0_I2C0_SCL_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_LVDS0_I2C0_SCL_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_LVDS0_I2C0_SCL_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_LVDS0_I2C0_SCL_WAKEUP_CTRL_MASK)
#define IOMUXD_LVDS0_I2C0_SCL_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_LVDS0_I2C0_SCL_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_LVDS0_I2C0_SCL_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_LVDS0_I2C0_SCL_WAKEUP_MASK_MASK)
#define IOMUXD_LVDS0_I2C0_SCL_lp_config_MASK     (0x1800000U)
#define IOMUXD_LVDS0_I2C0_SCL_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_LVDS0_I2C0_SCL_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_LVDS0_I2C0_SCL_lp_config_MASK)
#define IOMUXD_LVDS0_I2C0_SCL_sw_config_MASK     (0x6000000U)
#define IOMUXD_LVDS0_I2C0_SCL_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_LVDS0_I2C0_SCL_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_LVDS0_I2C0_SCL_sw_config_MASK)
#define IOMUXD_LVDS0_I2C0_SCL_mux_mode_MASK      (0x38000000U)
#define IOMUXD_LVDS0_I2C0_SCL_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..LVDS0.I2C0.SCL
 *  0b001..LVDS0.GPIO0.IO02
 *  0b011..LSIO.GPIO1.IO06
 */
#define IOMUXD_LVDS0_I2C0_SCL_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_LVDS0_I2C0_SCL_mux_mode_MASK)
#define IOMUXD_LVDS0_I2C0_SCL_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_LVDS0_I2C0_SCL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_LVDS0_I2C0_SCL_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_LVDS0_I2C0_SCL_update_pad_ctl_MASK)
#define IOMUXD_LVDS0_I2C0_SCL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_LVDS0_I2C0_SCL_update_mux_mode_SHIFT (31U)
#define IOMUXD_LVDS0_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_LVDS0_I2C0_SCL_update_mux_mode_MASK)
/*! @} */

/*! @name LVDS0_I2C0_SDA - LVDS0_I2C0_SDA */
/*! @{ */
#define IOMUXD_LVDS0_I2C0_SDA_PDRV_MASK          (0x1U)
#define IOMUXD_LVDS0_I2C0_SDA_PDRV_SHIFT         (0U)
#define IOMUXD_LVDS0_I2C0_SDA_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SDA_PDRV_SHIFT)) & IOMUXD_LVDS0_I2C0_SDA_PDRV_MASK)
#define IOMUXD_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA_reserved_1_4_MASK (0x1EU)
#define IOMUXD_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA_reserved_1_4_SHIFT (1U)
#define IOMUXD_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA_reserved_1_4_SHIFT)) & IOMUXD_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA_reserved_1_4_MASK)
#define IOMUXD_LVDS0_I2C0_SDA_PULL_MASK          (0x60U)
#define IOMUXD_LVDS0_I2C0_SDA_PULL_SHIFT         (5U)
#define IOMUXD_LVDS0_I2C0_SDA_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SDA_PULL_SHIFT)) & IOMUXD_LVDS0_I2C0_SDA_PULL_MASK)
#define IOMUXD_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA_reserved_7_18_SHIFT (7U)
#define IOMUXD_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA_reserved_7_18_MASK)
#define IOMUXD_LVDS0_I2C0_SDA_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_LVDS0_I2C0_SDA_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_LVDS0_I2C0_SDA_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_LVDS0_I2C0_SDA_WAKEUP_CTRL_MASK)
#define IOMUXD_LVDS0_I2C0_SDA_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_LVDS0_I2C0_SDA_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_LVDS0_I2C0_SDA_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_LVDS0_I2C0_SDA_WAKEUP_MASK_MASK)
#define IOMUXD_LVDS0_I2C0_SDA_lp_config_MASK     (0x1800000U)
#define IOMUXD_LVDS0_I2C0_SDA_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_LVDS0_I2C0_SDA_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_LVDS0_I2C0_SDA_lp_config_MASK)
#define IOMUXD_LVDS0_I2C0_SDA_sw_config_MASK     (0x6000000U)
#define IOMUXD_LVDS0_I2C0_SDA_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_LVDS0_I2C0_SDA_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_LVDS0_I2C0_SDA_sw_config_MASK)
#define IOMUXD_LVDS0_I2C0_SDA_mux_mode_MASK      (0x38000000U)
#define IOMUXD_LVDS0_I2C0_SDA_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..LVDS0.I2C0.SDA
 *  0b001..LVDS0.GPIO0.IO03
 *  0b011..LSIO.GPIO1.IO07
 */
#define IOMUXD_LVDS0_I2C0_SDA_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_LVDS0_I2C0_SDA_mux_mode_MASK)
#define IOMUXD_LVDS0_I2C0_SDA_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_LVDS0_I2C0_SDA_update_pad_ctl_SHIFT (30U)
#define IOMUXD_LVDS0_I2C0_SDA_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_LVDS0_I2C0_SDA_update_pad_ctl_MASK)
#define IOMUXD_LVDS0_I2C0_SDA_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_LVDS0_I2C0_SDA_update_mux_mode_SHIFT (31U)
#define IOMUXD_LVDS0_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_LVDS0_I2C0_SDA_update_mux_mode_MASK)
/*! @} */

/*! @name LVDS0_I2C1_SCL - LVDS0_I2C1_SCL */
/*! @{ */
#define IOMUXD_LVDS0_I2C1_SCL_PDRV_MASK          (0x1U)
#define IOMUXD_LVDS0_I2C1_SCL_PDRV_SHIFT         (0U)
#define IOMUXD_LVDS0_I2C1_SCL_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SCL_PDRV_SHIFT)) & IOMUXD_LVDS0_I2C1_SCL_PDRV_MASK)
#define IOMUXD_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL_reserved_1_4_MASK (0x1EU)
#define IOMUXD_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL_reserved_1_4_SHIFT (1U)
#define IOMUXD_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL_reserved_1_4_SHIFT)) & IOMUXD_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL_reserved_1_4_MASK)
#define IOMUXD_LVDS0_I2C1_SCL_PULL_MASK          (0x60U)
#define IOMUXD_LVDS0_I2C1_SCL_PULL_SHIFT         (5U)
#define IOMUXD_LVDS0_I2C1_SCL_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SCL_PULL_SHIFT)) & IOMUXD_LVDS0_I2C1_SCL_PULL_MASK)
#define IOMUXD_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL_reserved_7_18_SHIFT (7U)
#define IOMUXD_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL_reserved_7_18_SHIFT)) & IOMUXD_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL_reserved_7_18_MASK)
#define IOMUXD_LVDS0_I2C1_SCL_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_LVDS0_I2C1_SCL_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_LVDS0_I2C1_SCL_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_LVDS0_I2C1_SCL_WAKEUP_CTRL_MASK)
#define IOMUXD_LVDS0_I2C1_SCL_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_LVDS0_I2C1_SCL_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_LVDS0_I2C1_SCL_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_LVDS0_I2C1_SCL_WAKEUP_MASK_MASK)
#define IOMUXD_LVDS0_I2C1_SCL_lp_config_MASK     (0x1800000U)
#define IOMUXD_LVDS0_I2C1_SCL_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_LVDS0_I2C1_SCL_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SCL_lp_config_SHIFT)) & IOMUXD_LVDS0_I2C1_SCL_lp_config_MASK)
#define IOMUXD_LVDS0_I2C1_SCL_sw_config_MASK     (0x6000000U)
#define IOMUXD_LVDS0_I2C1_SCL_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_LVDS0_I2C1_SCL_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SCL_sw_config_SHIFT)) & IOMUXD_LVDS0_I2C1_SCL_sw_config_MASK)
#define IOMUXD_LVDS0_I2C1_SCL_mux_mode_MASK      (0x38000000U)
#define IOMUXD_LVDS0_I2C1_SCL_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..LVDS0.I2C1.SCL
 *  0b001..DMA.UART2.TX
 *  0b011..LSIO.GPIO1.IO08
 */
#define IOMUXD_LVDS0_I2C1_SCL_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SCL_mux_mode_SHIFT)) & IOMUXD_LVDS0_I2C1_SCL_mux_mode_MASK)
#define IOMUXD_LVDS0_I2C1_SCL_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_LVDS0_I2C1_SCL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_LVDS0_I2C1_SCL_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SCL_update_pad_ctl_SHIFT)) & IOMUXD_LVDS0_I2C1_SCL_update_pad_ctl_MASK)
#define IOMUXD_LVDS0_I2C1_SCL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_LVDS0_I2C1_SCL_update_mux_mode_SHIFT (31U)
#define IOMUXD_LVDS0_I2C1_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SCL_update_mux_mode_SHIFT)) & IOMUXD_LVDS0_I2C1_SCL_update_mux_mode_MASK)
/*! @} */

/*! @name LVDS0_I2C1_SDA - LVDS0_I2C1_SDA */
/*! @{ */
#define IOMUXD_LVDS0_I2C1_SDA_PDRV_MASK          (0x1U)
#define IOMUXD_LVDS0_I2C1_SDA_PDRV_SHIFT         (0U)
#define IOMUXD_LVDS0_I2C1_SDA_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SDA_PDRV_SHIFT)) & IOMUXD_LVDS0_I2C1_SDA_PDRV_MASK)
#define IOMUXD_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA_reserved_1_4_MASK (0x1EU)
#define IOMUXD_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA_reserved_1_4_SHIFT (1U)
#define IOMUXD_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA_reserved_1_4_SHIFT)) & IOMUXD_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA_reserved_1_4_MASK)
#define IOMUXD_LVDS0_I2C1_SDA_PULL_MASK          (0x60U)
#define IOMUXD_LVDS0_I2C1_SDA_PULL_SHIFT         (5U)
#define IOMUXD_LVDS0_I2C1_SDA_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SDA_PULL_SHIFT)) & IOMUXD_LVDS0_I2C1_SDA_PULL_MASK)
#define IOMUXD_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA_reserved_7_18_SHIFT (7U)
#define IOMUXD_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA_reserved_7_18_SHIFT)) & IOMUXD_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA_reserved_7_18_MASK)
#define IOMUXD_LVDS0_I2C1_SDA_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_LVDS0_I2C1_SDA_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_LVDS0_I2C1_SDA_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_LVDS0_I2C1_SDA_WAKEUP_CTRL_MASK)
#define IOMUXD_LVDS0_I2C1_SDA_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_LVDS0_I2C1_SDA_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_LVDS0_I2C1_SDA_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_LVDS0_I2C1_SDA_WAKEUP_MASK_MASK)
#define IOMUXD_LVDS0_I2C1_SDA_lp_config_MASK     (0x1800000U)
#define IOMUXD_LVDS0_I2C1_SDA_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_LVDS0_I2C1_SDA_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SDA_lp_config_SHIFT)) & IOMUXD_LVDS0_I2C1_SDA_lp_config_MASK)
#define IOMUXD_LVDS0_I2C1_SDA_sw_config_MASK     (0x6000000U)
#define IOMUXD_LVDS0_I2C1_SDA_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_LVDS0_I2C1_SDA_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SDA_sw_config_SHIFT)) & IOMUXD_LVDS0_I2C1_SDA_sw_config_MASK)
#define IOMUXD_LVDS0_I2C1_SDA_mux_mode_MASK      (0x38000000U)
#define IOMUXD_LVDS0_I2C1_SDA_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..LVDS0.I2C1.SDA
 *  0b001..DMA.UART2.RX
 *  0b011..LSIO.GPIO1.IO09
 */
#define IOMUXD_LVDS0_I2C1_SDA_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SDA_mux_mode_SHIFT)) & IOMUXD_LVDS0_I2C1_SDA_mux_mode_MASK)
#define IOMUXD_LVDS0_I2C1_SDA_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_LVDS0_I2C1_SDA_update_pad_ctl_SHIFT (30U)
#define IOMUXD_LVDS0_I2C1_SDA_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SDA_update_pad_ctl_SHIFT)) & IOMUXD_LVDS0_I2C1_SDA_update_pad_ctl_MASK)
#define IOMUXD_LVDS0_I2C1_SDA_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_LVDS0_I2C1_SDA_update_mux_mode_SHIFT (31U)
#define IOMUXD_LVDS0_I2C1_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS0_I2C1_SDA_update_mux_mode_SHIFT)) & IOMUXD_LVDS0_I2C1_SDA_update_mux_mode_MASK)
/*! @} */

/*! @name LVDS1_GPIO00 - LVDS1_GPIO00 */
/*! @{ */
#define IOMUXD_LVDS1_GPIO00_PDRV_MASK            (0x1U)
#define IOMUXD_LVDS1_GPIO00_PDRV_SHIFT           (0U)
#define IOMUXD_LVDS1_GPIO00_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO00_PDRV_SHIFT)) & IOMUXD_LVDS1_GPIO00_PDRV_MASK)
#define IOMUXD_LVDS1_GPIO00_LVDS1_GPIO00_reserved_1_4_MASK (0x1EU)
#define IOMUXD_LVDS1_GPIO00_LVDS1_GPIO00_reserved_1_4_SHIFT (1U)
#define IOMUXD_LVDS1_GPIO00_LVDS1_GPIO00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO00_LVDS1_GPIO00_reserved_1_4_SHIFT)) & IOMUXD_LVDS1_GPIO00_LVDS1_GPIO00_reserved_1_4_MASK)
#define IOMUXD_LVDS1_GPIO00_PULL_MASK            (0x60U)
#define IOMUXD_LVDS1_GPIO00_PULL_SHIFT           (5U)
#define IOMUXD_LVDS1_GPIO00_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO00_PULL_SHIFT)) & IOMUXD_LVDS1_GPIO00_PULL_MASK)
#define IOMUXD_LVDS1_GPIO00_LVDS1_GPIO00_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_LVDS1_GPIO00_LVDS1_GPIO00_reserved_7_18_SHIFT (7U)
#define IOMUXD_LVDS1_GPIO00_LVDS1_GPIO00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO00_LVDS1_GPIO00_reserved_7_18_SHIFT)) & IOMUXD_LVDS1_GPIO00_LVDS1_GPIO00_reserved_7_18_MASK)
#define IOMUXD_LVDS1_GPIO00_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_LVDS1_GPIO00_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_LVDS1_GPIO00_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO00_WAKEUP_CTRL_SHIFT)) & IOMUXD_LVDS1_GPIO00_WAKEUP_CTRL_MASK)
#define IOMUXD_LVDS1_GPIO00_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_LVDS1_GPIO00_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_LVDS1_GPIO00_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO00_WAKEUP_MASK_SHIFT)) & IOMUXD_LVDS1_GPIO00_WAKEUP_MASK_MASK)
#define IOMUXD_LVDS1_GPIO00_lp_config_MASK       (0x1800000U)
#define IOMUXD_LVDS1_GPIO00_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_LVDS1_GPIO00_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO00_lp_config_SHIFT)) & IOMUXD_LVDS1_GPIO00_lp_config_MASK)
#define IOMUXD_LVDS1_GPIO00_sw_config_MASK       (0x6000000U)
#define IOMUXD_LVDS1_GPIO00_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_LVDS1_GPIO00_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO00_sw_config_SHIFT)) & IOMUXD_LVDS1_GPIO00_sw_config_MASK)
#define IOMUXD_LVDS1_GPIO00_mux_mode_MASK        (0x38000000U)
#define IOMUXD_LVDS1_GPIO00_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LVDS1.GPIO0.IO00
 *  0b001..LVDS1.PWM0.OUT
 *  0b011..LSIO.GPIO1.IO10
 */
#define IOMUXD_LVDS1_GPIO00_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO00_mux_mode_SHIFT)) & IOMUXD_LVDS1_GPIO00_mux_mode_MASK)
#define IOMUXD_LVDS1_GPIO00_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_LVDS1_GPIO00_update_pad_ctl_SHIFT (30U)
#define IOMUXD_LVDS1_GPIO00_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO00_update_pad_ctl_SHIFT)) & IOMUXD_LVDS1_GPIO00_update_pad_ctl_MASK)
#define IOMUXD_LVDS1_GPIO00_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_LVDS1_GPIO00_update_mux_mode_SHIFT (31U)
#define IOMUXD_LVDS1_GPIO00_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO00_update_mux_mode_SHIFT)) & IOMUXD_LVDS1_GPIO00_update_mux_mode_MASK)
/*! @} */

/*! @name LVDS1_GPIO01 - LVDS1_GPIO01 */
/*! @{ */
#define IOMUXD_LVDS1_GPIO01_PDRV_MASK            (0x1U)
#define IOMUXD_LVDS1_GPIO01_PDRV_SHIFT           (0U)
#define IOMUXD_LVDS1_GPIO01_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO01_PDRV_SHIFT)) & IOMUXD_LVDS1_GPIO01_PDRV_MASK)
#define IOMUXD_LVDS1_GPIO01_LVDS1_GPIO01_reserved_1_4_MASK (0x1EU)
#define IOMUXD_LVDS1_GPIO01_LVDS1_GPIO01_reserved_1_4_SHIFT (1U)
#define IOMUXD_LVDS1_GPIO01_LVDS1_GPIO01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO01_LVDS1_GPIO01_reserved_1_4_SHIFT)) & IOMUXD_LVDS1_GPIO01_LVDS1_GPIO01_reserved_1_4_MASK)
#define IOMUXD_LVDS1_GPIO01_PULL_MASK            (0x60U)
#define IOMUXD_LVDS1_GPIO01_PULL_SHIFT           (5U)
#define IOMUXD_LVDS1_GPIO01_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO01_PULL_SHIFT)) & IOMUXD_LVDS1_GPIO01_PULL_MASK)
#define IOMUXD_LVDS1_GPIO01_LVDS1_GPIO01_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_LVDS1_GPIO01_LVDS1_GPIO01_reserved_7_18_SHIFT (7U)
#define IOMUXD_LVDS1_GPIO01_LVDS1_GPIO01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO01_LVDS1_GPIO01_reserved_7_18_SHIFT)) & IOMUXD_LVDS1_GPIO01_LVDS1_GPIO01_reserved_7_18_MASK)
#define IOMUXD_LVDS1_GPIO01_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_LVDS1_GPIO01_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_LVDS1_GPIO01_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO01_WAKEUP_CTRL_SHIFT)) & IOMUXD_LVDS1_GPIO01_WAKEUP_CTRL_MASK)
#define IOMUXD_LVDS1_GPIO01_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_LVDS1_GPIO01_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_LVDS1_GPIO01_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO01_WAKEUP_MASK_SHIFT)) & IOMUXD_LVDS1_GPIO01_WAKEUP_MASK_MASK)
#define IOMUXD_LVDS1_GPIO01_lp_config_MASK       (0x1800000U)
#define IOMUXD_LVDS1_GPIO01_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_LVDS1_GPIO01_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO01_lp_config_SHIFT)) & IOMUXD_LVDS1_GPIO01_lp_config_MASK)
#define IOMUXD_LVDS1_GPIO01_sw_config_MASK       (0x6000000U)
#define IOMUXD_LVDS1_GPIO01_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_LVDS1_GPIO01_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO01_sw_config_SHIFT)) & IOMUXD_LVDS1_GPIO01_sw_config_MASK)
#define IOMUXD_LVDS1_GPIO01_mux_mode_MASK        (0x38000000U)
#define IOMUXD_LVDS1_GPIO01_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LVDS1.GPIO0.IO01
 *  0b011..LSIO.GPIO1.IO11
 */
#define IOMUXD_LVDS1_GPIO01_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO01_mux_mode_SHIFT)) & IOMUXD_LVDS1_GPIO01_mux_mode_MASK)
#define IOMUXD_LVDS1_GPIO01_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_LVDS1_GPIO01_update_pad_ctl_SHIFT (30U)
#define IOMUXD_LVDS1_GPIO01_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO01_update_pad_ctl_SHIFT)) & IOMUXD_LVDS1_GPIO01_update_pad_ctl_MASK)
#define IOMUXD_LVDS1_GPIO01_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_LVDS1_GPIO01_update_mux_mode_SHIFT (31U)
#define IOMUXD_LVDS1_GPIO01_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_GPIO01_update_mux_mode_SHIFT)) & IOMUXD_LVDS1_GPIO01_update_mux_mode_MASK)
/*! @} */

/*! @name LVDS1_I2C0_SCL - LVDS1_I2C0_SCL */
/*! @{ */
#define IOMUXD_LVDS1_I2C0_SCL_PDRV_MASK          (0x1U)
#define IOMUXD_LVDS1_I2C0_SCL_PDRV_SHIFT         (0U)
#define IOMUXD_LVDS1_I2C0_SCL_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SCL_PDRV_SHIFT)) & IOMUXD_LVDS1_I2C0_SCL_PDRV_MASK)
#define IOMUXD_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL_reserved_1_4_MASK (0x1EU)
#define IOMUXD_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL_reserved_1_4_SHIFT (1U)
#define IOMUXD_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL_reserved_1_4_SHIFT)) & IOMUXD_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL_reserved_1_4_MASK)
#define IOMUXD_LVDS1_I2C0_SCL_PULL_MASK          (0x60U)
#define IOMUXD_LVDS1_I2C0_SCL_PULL_SHIFT         (5U)
#define IOMUXD_LVDS1_I2C0_SCL_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SCL_PULL_SHIFT)) & IOMUXD_LVDS1_I2C0_SCL_PULL_MASK)
#define IOMUXD_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL_reserved_7_18_SHIFT (7U)
#define IOMUXD_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL_reserved_7_18_MASK)
#define IOMUXD_LVDS1_I2C0_SCL_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_LVDS1_I2C0_SCL_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_LVDS1_I2C0_SCL_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_LVDS1_I2C0_SCL_WAKEUP_CTRL_MASK)
#define IOMUXD_LVDS1_I2C0_SCL_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_LVDS1_I2C0_SCL_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_LVDS1_I2C0_SCL_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_LVDS1_I2C0_SCL_WAKEUP_MASK_MASK)
#define IOMUXD_LVDS1_I2C0_SCL_lp_config_MASK     (0x1800000U)
#define IOMUXD_LVDS1_I2C0_SCL_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_LVDS1_I2C0_SCL_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_LVDS1_I2C0_SCL_lp_config_MASK)
#define IOMUXD_LVDS1_I2C0_SCL_sw_config_MASK     (0x6000000U)
#define IOMUXD_LVDS1_I2C0_SCL_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_LVDS1_I2C0_SCL_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_LVDS1_I2C0_SCL_sw_config_MASK)
#define IOMUXD_LVDS1_I2C0_SCL_mux_mode_MASK      (0x38000000U)
#define IOMUXD_LVDS1_I2C0_SCL_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..LVDS1.I2C0.SCL
 *  0b001..LVDS1.GPIO0.IO02
 *  0b011..LSIO.GPIO1.IO12
 */
#define IOMUXD_LVDS1_I2C0_SCL_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_LVDS1_I2C0_SCL_mux_mode_MASK)
#define IOMUXD_LVDS1_I2C0_SCL_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_LVDS1_I2C0_SCL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_LVDS1_I2C0_SCL_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_LVDS1_I2C0_SCL_update_pad_ctl_MASK)
#define IOMUXD_LVDS1_I2C0_SCL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_LVDS1_I2C0_SCL_update_mux_mode_SHIFT (31U)
#define IOMUXD_LVDS1_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_LVDS1_I2C0_SCL_update_mux_mode_MASK)
/*! @} */

/*! @name LVDS1_I2C0_SDA - LVDS1_I2C0_SDA */
/*! @{ */
#define IOMUXD_LVDS1_I2C0_SDA_PDRV_MASK          (0x1U)
#define IOMUXD_LVDS1_I2C0_SDA_PDRV_SHIFT         (0U)
#define IOMUXD_LVDS1_I2C0_SDA_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SDA_PDRV_SHIFT)) & IOMUXD_LVDS1_I2C0_SDA_PDRV_MASK)
#define IOMUXD_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA_reserved_1_4_MASK (0x1EU)
#define IOMUXD_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA_reserved_1_4_SHIFT (1U)
#define IOMUXD_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA_reserved_1_4_SHIFT)) & IOMUXD_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA_reserved_1_4_MASK)
#define IOMUXD_LVDS1_I2C0_SDA_PULL_MASK          (0x60U)
#define IOMUXD_LVDS1_I2C0_SDA_PULL_SHIFT         (5U)
#define IOMUXD_LVDS1_I2C0_SDA_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SDA_PULL_SHIFT)) & IOMUXD_LVDS1_I2C0_SDA_PULL_MASK)
#define IOMUXD_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA_reserved_7_18_SHIFT (7U)
#define IOMUXD_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA_reserved_7_18_MASK)
#define IOMUXD_LVDS1_I2C0_SDA_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_LVDS1_I2C0_SDA_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_LVDS1_I2C0_SDA_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_LVDS1_I2C0_SDA_WAKEUP_CTRL_MASK)
#define IOMUXD_LVDS1_I2C0_SDA_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_LVDS1_I2C0_SDA_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_LVDS1_I2C0_SDA_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_LVDS1_I2C0_SDA_WAKEUP_MASK_MASK)
#define IOMUXD_LVDS1_I2C0_SDA_lp_config_MASK     (0x1800000U)
#define IOMUXD_LVDS1_I2C0_SDA_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_LVDS1_I2C0_SDA_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_LVDS1_I2C0_SDA_lp_config_MASK)
#define IOMUXD_LVDS1_I2C0_SDA_sw_config_MASK     (0x6000000U)
#define IOMUXD_LVDS1_I2C0_SDA_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_LVDS1_I2C0_SDA_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_LVDS1_I2C0_SDA_sw_config_MASK)
#define IOMUXD_LVDS1_I2C0_SDA_mux_mode_MASK      (0x38000000U)
#define IOMUXD_LVDS1_I2C0_SDA_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..LVDS1.I2C0.SDA
 *  0b001..LVDS1.GPIO0.IO03
 *  0b011..LSIO.GPIO1.IO13
 */
#define IOMUXD_LVDS1_I2C0_SDA_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_LVDS1_I2C0_SDA_mux_mode_MASK)
#define IOMUXD_LVDS1_I2C0_SDA_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_LVDS1_I2C0_SDA_update_pad_ctl_SHIFT (30U)
#define IOMUXD_LVDS1_I2C0_SDA_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_LVDS1_I2C0_SDA_update_pad_ctl_MASK)
#define IOMUXD_LVDS1_I2C0_SDA_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_LVDS1_I2C0_SDA_update_mux_mode_SHIFT (31U)
#define IOMUXD_LVDS1_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_LVDS1_I2C0_SDA_update_mux_mode_MASK)
/*! @} */

/*! @name LVDS1_I2C1_SCL - LVDS1_I2C1_SCL */
/*! @{ */
#define IOMUXD_LVDS1_I2C1_SCL_PDRV_MASK          (0x1U)
#define IOMUXD_LVDS1_I2C1_SCL_PDRV_SHIFT         (0U)
#define IOMUXD_LVDS1_I2C1_SCL_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SCL_PDRV_SHIFT)) & IOMUXD_LVDS1_I2C1_SCL_PDRV_MASK)
#define IOMUXD_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL_reserved_1_4_MASK (0x1EU)
#define IOMUXD_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL_reserved_1_4_SHIFT (1U)
#define IOMUXD_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL_reserved_1_4_SHIFT)) & IOMUXD_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL_reserved_1_4_MASK)
#define IOMUXD_LVDS1_I2C1_SCL_PULL_MASK          (0x60U)
#define IOMUXD_LVDS1_I2C1_SCL_PULL_SHIFT         (5U)
#define IOMUXD_LVDS1_I2C1_SCL_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SCL_PULL_SHIFT)) & IOMUXD_LVDS1_I2C1_SCL_PULL_MASK)
#define IOMUXD_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL_reserved_7_18_SHIFT (7U)
#define IOMUXD_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL_reserved_7_18_SHIFT)) & IOMUXD_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL_reserved_7_18_MASK)
#define IOMUXD_LVDS1_I2C1_SCL_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_LVDS1_I2C1_SCL_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_LVDS1_I2C1_SCL_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_LVDS1_I2C1_SCL_WAKEUP_CTRL_MASK)
#define IOMUXD_LVDS1_I2C1_SCL_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_LVDS1_I2C1_SCL_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_LVDS1_I2C1_SCL_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_LVDS1_I2C1_SCL_WAKEUP_MASK_MASK)
#define IOMUXD_LVDS1_I2C1_SCL_lp_config_MASK     (0x1800000U)
#define IOMUXD_LVDS1_I2C1_SCL_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_LVDS1_I2C1_SCL_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SCL_lp_config_SHIFT)) & IOMUXD_LVDS1_I2C1_SCL_lp_config_MASK)
#define IOMUXD_LVDS1_I2C1_SCL_sw_config_MASK     (0x6000000U)
#define IOMUXD_LVDS1_I2C1_SCL_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_LVDS1_I2C1_SCL_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SCL_sw_config_SHIFT)) & IOMUXD_LVDS1_I2C1_SCL_sw_config_MASK)
#define IOMUXD_LVDS1_I2C1_SCL_mux_mode_MASK      (0x38000000U)
#define IOMUXD_LVDS1_I2C1_SCL_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..LVDS1.I2C1.SCL
 *  0b001..DMA.UART3.TX
 *  0b011..LSIO.GPIO1.IO14
 */
#define IOMUXD_LVDS1_I2C1_SCL_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SCL_mux_mode_SHIFT)) & IOMUXD_LVDS1_I2C1_SCL_mux_mode_MASK)
#define IOMUXD_LVDS1_I2C1_SCL_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_LVDS1_I2C1_SCL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_LVDS1_I2C1_SCL_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SCL_update_pad_ctl_SHIFT)) & IOMUXD_LVDS1_I2C1_SCL_update_pad_ctl_MASK)
#define IOMUXD_LVDS1_I2C1_SCL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_LVDS1_I2C1_SCL_update_mux_mode_SHIFT (31U)
#define IOMUXD_LVDS1_I2C1_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SCL_update_mux_mode_SHIFT)) & IOMUXD_LVDS1_I2C1_SCL_update_mux_mode_MASK)
/*! @} */

/*! @name LVDS1_I2C1_SDA - LVDS1_I2C1_SDA */
/*! @{ */
#define IOMUXD_LVDS1_I2C1_SDA_PDRV_MASK          (0x1U)
#define IOMUXD_LVDS1_I2C1_SDA_PDRV_SHIFT         (0U)
#define IOMUXD_LVDS1_I2C1_SDA_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SDA_PDRV_SHIFT)) & IOMUXD_LVDS1_I2C1_SDA_PDRV_MASK)
#define IOMUXD_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA_reserved_1_4_MASK (0x1EU)
#define IOMUXD_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA_reserved_1_4_SHIFT (1U)
#define IOMUXD_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA_reserved_1_4_SHIFT)) & IOMUXD_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA_reserved_1_4_MASK)
#define IOMUXD_LVDS1_I2C1_SDA_PULL_MASK          (0x60U)
#define IOMUXD_LVDS1_I2C1_SDA_PULL_SHIFT         (5U)
#define IOMUXD_LVDS1_I2C1_SDA_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SDA_PULL_SHIFT)) & IOMUXD_LVDS1_I2C1_SDA_PULL_MASK)
#define IOMUXD_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA_reserved_7_18_SHIFT (7U)
#define IOMUXD_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA_reserved_7_18_SHIFT)) & IOMUXD_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA_reserved_7_18_MASK)
#define IOMUXD_LVDS1_I2C1_SDA_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_LVDS1_I2C1_SDA_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_LVDS1_I2C1_SDA_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_LVDS1_I2C1_SDA_WAKEUP_CTRL_MASK)
#define IOMUXD_LVDS1_I2C1_SDA_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_LVDS1_I2C1_SDA_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_LVDS1_I2C1_SDA_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_LVDS1_I2C1_SDA_WAKEUP_MASK_MASK)
#define IOMUXD_LVDS1_I2C1_SDA_lp_config_MASK     (0x1800000U)
#define IOMUXD_LVDS1_I2C1_SDA_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_LVDS1_I2C1_SDA_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SDA_lp_config_SHIFT)) & IOMUXD_LVDS1_I2C1_SDA_lp_config_MASK)
#define IOMUXD_LVDS1_I2C1_SDA_sw_config_MASK     (0x6000000U)
#define IOMUXD_LVDS1_I2C1_SDA_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_LVDS1_I2C1_SDA_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SDA_sw_config_SHIFT)) & IOMUXD_LVDS1_I2C1_SDA_sw_config_MASK)
#define IOMUXD_LVDS1_I2C1_SDA_mux_mode_MASK      (0x38000000U)
#define IOMUXD_LVDS1_I2C1_SDA_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..LVDS1.I2C1.SDA
 *  0b001..DMA.UART3.RX
 *  0b011..LSIO.GPIO1.IO15
 */
#define IOMUXD_LVDS1_I2C1_SDA_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SDA_mux_mode_SHIFT)) & IOMUXD_LVDS1_I2C1_SDA_mux_mode_MASK)
#define IOMUXD_LVDS1_I2C1_SDA_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_LVDS1_I2C1_SDA_update_pad_ctl_SHIFT (30U)
#define IOMUXD_LVDS1_I2C1_SDA_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SDA_update_pad_ctl_SHIFT)) & IOMUXD_LVDS1_I2C1_SDA_update_pad_ctl_MASK)
#define IOMUXD_LVDS1_I2C1_SDA_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_LVDS1_I2C1_SDA_update_mux_mode_SHIFT (31U)
#define IOMUXD_LVDS1_I2C1_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_LVDS1_I2C1_SDA_update_mux_mode_SHIFT)) & IOMUXD_LVDS1_I2C1_SDA_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO - IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_0_4 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_GPIO00_MASK (0x1U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_GPIO00_SHIFT (0U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_GPIO00(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_4_LVDS0_GPIO00_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_4_LVDS0_GPIO00_MASK)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_GPIO01_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_GPIO01_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_GPIO01(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_4_LVDS0_GPIO01_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_4_LVDS0_GPIO01_MASK)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C0_SCL_MASK (0x4U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C0_SCL_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C0_SCL_MASK)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C0_SDA_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C0_SDA_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C0_SDA_MASK)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C1_SCL_MASK (0x10U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C1_SCL_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C1_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C1_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C1_SCL_MASK)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C1_SDA_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C1_SDA_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C1_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C1_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_4_LVDS0_I2C1_SDA_MASK)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_GPIO00_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_GPIO00_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_GPIO00(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_4_LVDS1_GPIO00_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_4_LVDS1_GPIO00_MASK)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_GPIO01_MASK (0x80U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_GPIO01_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_GPIO01(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_4_LVDS1_GPIO01_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_4_LVDS1_GPIO01_MASK)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C0_SCL_MASK (0x100U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C0_SCL_SHIFT (8U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C0_SCL_MASK)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C0_SDA_MASK (0x200U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C0_SDA_SHIFT (9U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C0_SDA_MASK)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C1_SCL_MASK (0x400U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C1_SCL_SHIFT (10U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C1_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C1_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C1_SCL_MASK)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C1_SDA_MASK (0x800U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C1_SDA_SHIFT (11U)
#define IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C1_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C1_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_4_LVDS1_I2C1_SDA_MASK)
#define IOMUXD_IOMUXD_GROUP_0_4_iomuxd_group_0_4_reserved_12_31_MASK (0xFFFFF000U)
#define IOMUXD_IOMUXD_GROUP_0_4_iomuxd_group_0_4_reserved_12_31_SHIFT (12U)
#define IOMUXD_IOMUXD_GROUP_0_4_iomuxd_group_0_4_reserved_12_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_4_iomuxd_group_0_4_reserved_12_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_4_iomuxd_group_0_4_reserved_12_31_MASK)
/*! @} */

/*! @name MIPI_DSI0_I2C0_SCL - MIPI_DSI0_I2C0_SCL */
/*! @{ */
#define IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_MASK      (0x1U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_SHIFT     (0U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_MASK (0x1EU)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_SHIFT (1U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_DSI0.I2C0.SCL
 *  0b011..LSIO.GPIO1.IO16
 */
#define IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_DSI0_I2C0_SDA - MIPI_DSI0_I2C0_SDA */
/*! @{ */
#define IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_MASK      (0x1U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_SHIFT     (0U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_MASK (0x1EU)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_SHIFT (1U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_DSI0.I2C0.SDA
 *  0b011..LSIO.GPIO1.IO17
 */
#define IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_MASK)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_DSI0_GPIO0_00 - MIPI_DSI0_GPIO0_00 */
/*! @{ */
#define IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_MASK      (0x1U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_SHIFT     (0U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_MASK (0x1EU)
#define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_SHIFT (1U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_00_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_PULL_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_DSI0_GPIO0_00_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_DSI0_GPIO0_00_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_DSI0.GPIO0.IO00
 *  0b001..MIPI_DSI0.PWM0.OUT
 *  0b011..LSIO.GPIO1.IO18
 */
#define IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_DSI0_GPIO0_01 - MIPI_DSI0_GPIO0_01 */
/*! @{ */
#define IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_MASK      (0x1U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_SHIFT     (0U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_MASK (0x1EU)
#define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_SHIFT (1U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_01_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_PULL_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_DSI0_GPIO0_01_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_DSI0_GPIO0_01_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_DSI0.GPIO0.IO01
 *  0b011..LSIO.GPIO1.IO19
 */
#define IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_MASK)
#define IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_DSI1_I2C0_SCL - MIPI_DSI1_I2C0_SCL */
/*! @{ */
#define IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_MASK      (0x1U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_SHIFT     (0U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_MASK (0x1EU)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_SHIFT (1U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_DSI1.I2C0.SCL
 *  0b011..LSIO.GPIO1.IO20
 */
#define IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_DSI1_I2C0_SDA - MIPI_DSI1_I2C0_SDA */
/*! @{ */
#define IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_MASK      (0x1U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_SHIFT     (0U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_MASK (0x1EU)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_SHIFT (1U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_DSI1.I2C0.SDA
 *  0b011..LSIO.GPIO1.IO21
 */
#define IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_MASK)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_DSI1_GPIO0_00 - MIPI_DSI1_GPIO0_00 */
/*! @{ */
#define IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_MASK      (0x1U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_SHIFT     (0U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_MASK (0x1EU)
#define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_SHIFT (1U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_00_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_PULL_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_DSI1_GPIO0_00_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_DSI1_GPIO0_00_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_DSI1.GPIO0.IO00
 *  0b001..MIPI_DSI1.PWM0.OUT
 *  0b011..LSIO.GPIO1.IO22
 */
#define IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_DSI1_GPIO0_01 - MIPI_DSI1_GPIO0_01 */
/*! @{ */
#define IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_MASK      (0x1U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_SHIFT     (0U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_MASK (0x1EU)
#define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_SHIFT (1U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_01_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_PULL_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_DSI1_GPIO0_01_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_DSI1_GPIO0_01_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_DSI1.GPIO0.IO01
 *  0b011..LSIO.GPIO1.IO23
 */
#define IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_MASK)
#define IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO - IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_1_0 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_I2C0_SCL_MASK (0x1U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_I2C0_SCL_SHIFT (0U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_I2C0_SCL_MASK)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_I2C0_SDA_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_I2C0_SDA_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_I2C0_SDA_MASK)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_GPIO0_00_MASK (0x4U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_GPIO0_00_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_GPIO0_00_MASK)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_GPIO0_01_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_GPIO0_01_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI0_GPIO0_01_MASK)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_I2C0_SCL_MASK (0x10U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_I2C0_SCL_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_I2C0_SCL_MASK)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_I2C0_SDA_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_I2C0_SDA_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_I2C0_SDA_MASK)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_GPIO0_00_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_GPIO0_00_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_GPIO0_00_MASK)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_GPIO0_01_MASK (0x80U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_GPIO0_01_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_MIPI_DSI1_GPIO0_01_MASK)
#define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_8_31_MASK (0xFFFFFF00U)
#define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_8_31_SHIFT (8U)
#define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_8_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_8_31_MASK)
/*! @} */

/*! @name MIPI_CSI0_MCLK_OUT - MIPI_CSI0_MCLK_OUT */
/*! @{ */
#define IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_MASK       (0x7U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_SHIFT      (0U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_MASK)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_MASK (0x18U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_SHIFT (3U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_MASK)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_MASK)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_MASK)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_MASK)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_MASK)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_CSI0.ACM.MCLK_OUT
 *  0b011..LSIO.GPIO1.IO24
 */
#define IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_MASK)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_MASK)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_CSI0_I2C0_SCL - MIPI_CSI0_I2C0_SCL */
/*! @{ */
#define IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_MASK       (0x7U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_SHIFT      (0U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_MASK (0x18U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_SHIFT (3U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_CSI0.I2C0.SCL
 *  0b011..LSIO.GPIO1.IO25
 */
#define IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_CSI0_I2C0_SDA - MIPI_CSI0_I2C0_SDA */
/*! @{ */
#define IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_MASK       (0x7U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_SHIFT      (0U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_MASK (0x18U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_SHIFT (3U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_CSI0.I2C0.SDA
 *  0b011..LSIO.GPIO1.IO26
 */
#define IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_MASK)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_CSI0_GPIO0_00 - MIPI_CSI0_GPIO0_00 */
/*! @{ */
#define IOMUXD_MIPI_CSI0_GPIO0_00_DSE_MASK       (0x7U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_DSE_SHIFT      (0U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_DSE_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_MASK (0x18U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_SHIFT (3U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_00_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_PULL_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_CSI0_GPIO0_00_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_CSI0_GPIO0_00_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_CSI0.GPIO0.IO00
 *  0b001..DMA.I2C0.SCL
 *  0b010..MIPI_CSI1.I2C0.SCL
 *  0b011..LSIO.GPIO1.IO27
 */
#define IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_CSI0_GPIO0_01 - MIPI_CSI0_GPIO0_01 */
/*! @{ */
#define IOMUXD_MIPI_CSI0_GPIO0_01_DSE_MASK       (0x7U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_DSE_SHIFT      (0U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_DSE_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_MASK (0x18U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_SHIFT (3U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_01_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_PULL_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_CSI0_GPIO0_01_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_CSI0_GPIO0_01_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_CSI0.GPIO0.IO01
 *  0b001..DMA.I2C0.SDA
 *  0b010..MIPI_CSI1.I2C0.SDA
 *  0b011..LSIO.GPIO1.IO28
 */
#define IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_MASK)
#define IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_CSI1_MCLK_OUT - MIPI_CSI1_MCLK_OUT */
/*! @{ */
#define IOMUXD_MIPI_CSI1_MCLK_OUT_DSE_MASK       (0x7U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_DSE_SHIFT      (0U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_MCLK_OUT_DSE_SHIFT)) & IOMUXD_MIPI_CSI1_MCLK_OUT_DSE_MASK)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_MCLK_OUT_reserved_3_4_MASK (0x18U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_MCLK_OUT_reserved_3_4_SHIFT (3U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_MCLK_OUT_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_MCLK_OUT_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_MCLK_OUT_reserved_3_4_MASK)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_MCLK_OUT_PULL_SHIFT)) & IOMUXD_MIPI_CSI1_MCLK_OUT_PULL_MASK)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_MCLK_OUT_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_MCLK_OUT_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_MCLK_OUT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_MCLK_OUT_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_MCLK_OUT_reserved_7_18_MASK)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_CSI1_MCLK_OUT_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_MCLK_OUT_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI1_MCLK_OUT_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_MCLK_OUT_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI1_MCLK_OUT_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_CSI1_MCLK_OUT_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_MCLK_OUT_lp_config_SHIFT)) & IOMUXD_MIPI_CSI1_MCLK_OUT_lp_config_MASK)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_CSI1_MCLK_OUT_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_MCLK_OUT_sw_config_SHIFT)) & IOMUXD_MIPI_CSI1_MCLK_OUT_sw_config_MASK)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_CSI1.ACM.MCLK_OUT
 *  0b011..LSIO.GPIO1.IO29
 */
#define IOMUXD_MIPI_CSI1_MCLK_OUT_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_MCLK_OUT_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI1_MCLK_OUT_mux_mode_MASK)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_MCLK_OUT_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI1_MCLK_OUT_update_pad_ctl_MASK)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_CSI1_MCLK_OUT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_MCLK_OUT_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI1_MCLK_OUT_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_CSI1_GPIO0_00 - MIPI_CSI1_GPIO0_00 */
/*! @{ */
#define IOMUXD_MIPI_CSI1_GPIO0_00_DSE_MASK       (0x7U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_DSE_SHIFT      (0U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_00_DSE_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_00_DSE_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_00_reserved_3_4_MASK (0x18U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_00_reserved_3_4_SHIFT (3U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_00_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_00_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_00_reserved_3_4_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_00_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_00_PULL_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_00_PULL_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_00_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_00_reserved_7_18_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_CSI1_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_00_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_00_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_00_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_00_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_CSI1_GPIO0_00_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_00_lp_config_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_00_lp_config_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_00_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_CSI1_GPIO0_00_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_00_sw_config_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_00_sw_config_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_00_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_CSI1.GPIO0.IO00
 *  0b001..DMA.UART4.RX
 *  0b011..LSIO.GPIO1.IO30
 */
#define IOMUXD_MIPI_CSI1_GPIO0_00_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_00_mux_mode_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_00_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_00_update_pad_ctl_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_00_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_CSI1_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_00_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_CSI1_GPIO0_01 - MIPI_CSI1_GPIO0_01 */
/*! @{ */
#define IOMUXD_MIPI_CSI1_GPIO0_01_DSE_MASK       (0x7U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_DSE_SHIFT      (0U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_01_DSE_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_01_DSE_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_01_reserved_3_4_MASK (0x18U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_01_reserved_3_4_SHIFT (3U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_01_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_01_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_01_reserved_3_4_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_01_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_01_PULL_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_01_PULL_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_01_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_01_reserved_7_18_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_CSI1_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_01_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_01_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_01_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_01_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_CSI1_GPIO0_01_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_01_lp_config_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_01_lp_config_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_01_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_CSI1_GPIO0_01_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_01_sw_config_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_01_sw_config_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_01_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_CSI1.GPIO0.IO01
 *  0b001..DMA.UART4.TX
 *  0b011..LSIO.GPIO1.IO31
 */
#define IOMUXD_MIPI_CSI1_GPIO0_01_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_01_mux_mode_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_01_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_01_update_pad_ctl_MASK)
#define IOMUXD_MIPI_CSI1_GPIO0_01_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_CSI1_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI1_GPIO0_01_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_CSI1_I2C0_SCL - MIPI_CSI1_I2C0_SCL */
/*! @{ */
#define IOMUXD_MIPI_CSI1_I2C0_SCL_DSE_MASK       (0x7U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_DSE_SHIFT      (0U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SCL_DSE_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SCL_DSE_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL_reserved_3_4_MASK (0x18U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL_reserved_3_4_SHIFT (3U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL_reserved_3_4_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SCL_PULL_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SCL_PULL_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL_reserved_7_18_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_CSI1_I2C0_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SCL_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SCL_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_CSI1_I2C0_SCL_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SCL_lp_config_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_CSI1_I2C0_SCL_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SCL_sw_config_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_CSI1.I2C0.SCL
 *  0b011..LSIO.GPIO2.IO00
 */
#define IOMUXD_MIPI_CSI1_I2C0_SCL_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SCL_mux_mode_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SCL_update_pad_ctl_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_CSI1_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SCL_update_mux_mode_MASK)
/*! @} */

/*! @name MIPI_CSI1_I2C0_SDA - MIPI_CSI1_I2C0_SDA */
/*! @{ */
#define IOMUXD_MIPI_CSI1_I2C0_SDA_DSE_MASK       (0x7U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_DSE_SHIFT      (0U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_DSE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SDA_DSE_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SDA_DSE_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA_reserved_3_4_MASK (0x18U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA_reserved_3_4_SHIFT (3U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA_reserved_3_4_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_PULL_MASK      (0x60U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_PULL_SHIFT     (5U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SDA_PULL_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SDA_PULL_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA_reserved_7_18_SHIFT (7U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA_reserved_7_18_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MIPI_CSI1_I2C0_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SDA_WAKEUP_CTRL_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SDA_WAKEUP_MASK_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_lp_config_MASK (0x1800000U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MIPI_CSI1_I2C0_SDA_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SDA_lp_config_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_sw_config_MASK (0x6000000U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MIPI_CSI1_I2C0_SDA_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SDA_sw_config_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_mux_mode_MASK  (0x38000000U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..MIPI_CSI1.I2C0.SDA
 *  0b011..LSIO.GPIO2.IO01
 */
#define IOMUXD_MIPI_CSI1_I2C0_SDA_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SDA_mux_mode_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_update_pad_ctl_SHIFT (30U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SDA_update_pad_ctl_MASK)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_update_mux_mode_SHIFT (31U)
#define IOMUXD_MIPI_CSI1_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI1_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI1_I2C0_SDA_update_mux_mode_MASK)
/*! @} */

/*! @name HDMI_TX0_TS_SCL - HDMI_TX0_TS_SCL */
/*! @{ */
#define IOMUXD_HDMI_TX0_TS_SCL_DSE_MASK          (0x3U)
#define IOMUXD_HDMI_TX0_TS_SCL_DSE_SHIFT         (0U)
#define IOMUXD_HDMI_TX0_TS_SCL_DSE(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SCL_DSE_SHIFT)) & IOMUXD_HDMI_TX0_TS_SCL_DSE_MASK)
#define IOMUXD_HDMI_TX0_TS_SCL_HDMI_TX0_TS_SCL_reserved_2_4_MASK (0x1CU)
#define IOMUXD_HDMI_TX0_TS_SCL_HDMI_TX0_TS_SCL_reserved_2_4_SHIFT (2U)
#define IOMUXD_HDMI_TX0_TS_SCL_HDMI_TX0_TS_SCL_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SCL_HDMI_TX0_TS_SCL_reserved_2_4_SHIFT)) & IOMUXD_HDMI_TX0_TS_SCL_HDMI_TX0_TS_SCL_reserved_2_4_MASK)
#define IOMUXD_HDMI_TX0_TS_SCL_PULL_MASK         (0x60U)
#define IOMUXD_HDMI_TX0_TS_SCL_PULL_SHIFT        (5U)
#define IOMUXD_HDMI_TX0_TS_SCL_PULL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SCL_PULL_SHIFT)) & IOMUXD_HDMI_TX0_TS_SCL_PULL_MASK)
#define IOMUXD_HDMI_TX0_TS_SCL_HDMI_TX0_TS_SCL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_HDMI_TX0_TS_SCL_HDMI_TX0_TS_SCL_reserved_7_18_SHIFT (7U)
#define IOMUXD_HDMI_TX0_TS_SCL_HDMI_TX0_TS_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SCL_HDMI_TX0_TS_SCL_reserved_7_18_SHIFT)) & IOMUXD_HDMI_TX0_TS_SCL_HDMI_TX0_TS_SCL_reserved_7_18_MASK)
#define IOMUXD_HDMI_TX0_TS_SCL_WAKEUP_CTRL_MASK  (0x380000U)
#define IOMUXD_HDMI_TX0_TS_SCL_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_HDMI_TX0_TS_SCL_WAKEUP_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_HDMI_TX0_TS_SCL_WAKEUP_CTRL_MASK)
#define IOMUXD_HDMI_TX0_TS_SCL_WAKEUP_MASK_MASK  (0x400000U)
#define IOMUXD_HDMI_TX0_TS_SCL_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_HDMI_TX0_TS_SCL_WAKEUP_MASK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_HDMI_TX0_TS_SCL_WAKEUP_MASK_MASK)
#define IOMUXD_HDMI_TX0_TS_SCL_lp_config_MASK    (0x1800000U)
#define IOMUXD_HDMI_TX0_TS_SCL_lp_config_SHIFT   (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_HDMI_TX0_TS_SCL_lp_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SCL_lp_config_SHIFT)) & IOMUXD_HDMI_TX0_TS_SCL_lp_config_MASK)
#define IOMUXD_HDMI_TX0_TS_SCL_sw_config_MASK    (0x6000000U)
#define IOMUXD_HDMI_TX0_TS_SCL_sw_config_SHIFT   (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_HDMI_TX0_TS_SCL_sw_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SCL_sw_config_SHIFT)) & IOMUXD_HDMI_TX0_TS_SCL_sw_config_MASK)
#define IOMUXD_HDMI_TX0_TS_SCL_mux_mode_MASK     (0x38000000U)
#define IOMUXD_HDMI_TX0_TS_SCL_mux_mode_SHIFT    (27U)
/*! mux_mode - mux_mode
 *  0b000..HDMI_TX0.I2C0.SCL
 *  0b001..DMA.I2C0.SCL
 *  0b011..LSIO.GPIO2.IO02
 */
#define IOMUXD_HDMI_TX0_TS_SCL_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SCL_mux_mode_SHIFT)) & IOMUXD_HDMI_TX0_TS_SCL_mux_mode_MASK)
#define IOMUXD_HDMI_TX0_TS_SCL_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_HDMI_TX0_TS_SCL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_HDMI_TX0_TS_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SCL_update_pad_ctl_SHIFT)) & IOMUXD_HDMI_TX0_TS_SCL_update_pad_ctl_MASK)
#define IOMUXD_HDMI_TX0_TS_SCL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_HDMI_TX0_TS_SCL_update_mux_mode_SHIFT (31U)
#define IOMUXD_HDMI_TX0_TS_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SCL_update_mux_mode_SHIFT)) & IOMUXD_HDMI_TX0_TS_SCL_update_mux_mode_MASK)
/*! @} */

/*! @name HDMI_TX0_TS_SDA - HDMI_TX0_TS_SDA */
/*! @{ */
#define IOMUXD_HDMI_TX0_TS_SDA_DSE_MASK          (0x3U)
#define IOMUXD_HDMI_TX0_TS_SDA_DSE_SHIFT         (0U)
#define IOMUXD_HDMI_TX0_TS_SDA_DSE(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SDA_DSE_SHIFT)) & IOMUXD_HDMI_TX0_TS_SDA_DSE_MASK)
#define IOMUXD_HDMI_TX0_TS_SDA_HDMI_TX0_TS_SDA_reserved_2_4_MASK (0x1CU)
#define IOMUXD_HDMI_TX0_TS_SDA_HDMI_TX0_TS_SDA_reserved_2_4_SHIFT (2U)
#define IOMUXD_HDMI_TX0_TS_SDA_HDMI_TX0_TS_SDA_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SDA_HDMI_TX0_TS_SDA_reserved_2_4_SHIFT)) & IOMUXD_HDMI_TX0_TS_SDA_HDMI_TX0_TS_SDA_reserved_2_4_MASK)
#define IOMUXD_HDMI_TX0_TS_SDA_PULL_MASK         (0x60U)
#define IOMUXD_HDMI_TX0_TS_SDA_PULL_SHIFT        (5U)
#define IOMUXD_HDMI_TX0_TS_SDA_PULL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SDA_PULL_SHIFT)) & IOMUXD_HDMI_TX0_TS_SDA_PULL_MASK)
#define IOMUXD_HDMI_TX0_TS_SDA_HDMI_TX0_TS_SDA_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_HDMI_TX0_TS_SDA_HDMI_TX0_TS_SDA_reserved_7_18_SHIFT (7U)
#define IOMUXD_HDMI_TX0_TS_SDA_HDMI_TX0_TS_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SDA_HDMI_TX0_TS_SDA_reserved_7_18_SHIFT)) & IOMUXD_HDMI_TX0_TS_SDA_HDMI_TX0_TS_SDA_reserved_7_18_MASK)
#define IOMUXD_HDMI_TX0_TS_SDA_WAKEUP_CTRL_MASK  (0x380000U)
#define IOMUXD_HDMI_TX0_TS_SDA_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_HDMI_TX0_TS_SDA_WAKEUP_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_HDMI_TX0_TS_SDA_WAKEUP_CTRL_MASK)
#define IOMUXD_HDMI_TX0_TS_SDA_WAKEUP_MASK_MASK  (0x400000U)
#define IOMUXD_HDMI_TX0_TS_SDA_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_HDMI_TX0_TS_SDA_WAKEUP_MASK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_HDMI_TX0_TS_SDA_WAKEUP_MASK_MASK)
#define IOMUXD_HDMI_TX0_TS_SDA_lp_config_MASK    (0x1800000U)
#define IOMUXD_HDMI_TX0_TS_SDA_lp_config_SHIFT   (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_HDMI_TX0_TS_SDA_lp_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SDA_lp_config_SHIFT)) & IOMUXD_HDMI_TX0_TS_SDA_lp_config_MASK)
#define IOMUXD_HDMI_TX0_TS_SDA_sw_config_MASK    (0x6000000U)
#define IOMUXD_HDMI_TX0_TS_SDA_sw_config_SHIFT   (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_HDMI_TX0_TS_SDA_sw_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SDA_sw_config_SHIFT)) & IOMUXD_HDMI_TX0_TS_SDA_sw_config_MASK)
#define IOMUXD_HDMI_TX0_TS_SDA_mux_mode_MASK     (0x38000000U)
#define IOMUXD_HDMI_TX0_TS_SDA_mux_mode_SHIFT    (27U)
/*! mux_mode - mux_mode
 *  0b000..HDMI_TX0.I2C0.SDA
 *  0b001..DMA.I2C0.SDA
 *  0b011..LSIO.GPIO2.IO03
 */
#define IOMUXD_HDMI_TX0_TS_SDA_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SDA_mux_mode_SHIFT)) & IOMUXD_HDMI_TX0_TS_SDA_mux_mode_MASK)
#define IOMUXD_HDMI_TX0_TS_SDA_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_HDMI_TX0_TS_SDA_update_pad_ctl_SHIFT (30U)
#define IOMUXD_HDMI_TX0_TS_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SDA_update_pad_ctl_SHIFT)) & IOMUXD_HDMI_TX0_TS_SDA_update_pad_ctl_MASK)
#define IOMUXD_HDMI_TX0_TS_SDA_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_HDMI_TX0_TS_SDA_update_mux_mode_SHIFT (31U)
#define IOMUXD_HDMI_TX0_TS_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_HDMI_TX0_TS_SDA_update_mux_mode_SHIFT)) & IOMUXD_HDMI_TX0_TS_SDA_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO - IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_reserved_0_22_MASK (0x7FFFFFU)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_reserved_0_22_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_reserved_0_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_reserved_0_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_reserved_0_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_1_1 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_MCLK_OUT_MASK (0x1U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_MCLK_OUT_SHIFT (0U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_MCLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_MCLK_OUT_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_MCLK_OUT_MASK)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_I2C0_SCL_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_I2C0_SCL_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_I2C0_SCL_MASK)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_I2C0_SDA_MASK (0x4U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_I2C0_SDA_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_I2C0_SDA_MASK)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_GPIO0_00_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_GPIO0_00_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_GPIO0_00_MASK)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_GPIO0_01_MASK (0x10U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_GPIO0_01_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI0_GPIO0_01_MASK)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_MCLK_OUT_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_MCLK_OUT_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_MCLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_MCLK_OUT_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_MCLK_OUT_MASK)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_GPIO0_00_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_GPIO0_00_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_GPIO0_00_MASK)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_GPIO0_01_MASK (0x80U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_GPIO0_01_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_GPIO0_01_MASK)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_I2C0_SCL_MASK (0x100U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_I2C0_SCL_SHIFT (8U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_I2C0_SCL_MASK)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_I2C0_SDA_MASK (0x200U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_I2C0_SDA_SHIFT (9U)
#define IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_MIPI_CSI1_I2C0_SDA_MASK)
#define IOMUXD_IOMUXD_GROUP_1_1_HDMI_TX0_TS_SCL_MASK (0x400U)
#define IOMUXD_IOMUXD_GROUP_1_1_HDMI_TX0_TS_SCL_SHIFT (10U)
#define IOMUXD_IOMUXD_GROUP_1_1_HDMI_TX0_TS_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_HDMI_TX0_TS_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_HDMI_TX0_TS_SCL_MASK)
#define IOMUXD_IOMUXD_GROUP_1_1_HDMI_TX0_TS_SDA_MASK (0x800U)
#define IOMUXD_IOMUXD_GROUP_1_1_HDMI_TX0_TS_SDA_SHIFT (11U)
#define IOMUXD_IOMUXD_GROUP_1_1_HDMI_TX0_TS_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_HDMI_TX0_TS_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_HDMI_TX0_TS_SDA_MASK)
#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_31_MASK (0xFFFFF000U)
#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_31_SHIFT (12U)
#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_31_MASK)
/*! @} */

/*! @name ESAI1_FSR - ESAI1_FSR */
/*! @{ */
#define IOMUXD_ESAI1_FSR_PDRV_MASK               (0x1U)
#define IOMUXD_ESAI1_FSR_PDRV_SHIFT              (0U)
#define IOMUXD_ESAI1_FSR_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FSR_PDRV_SHIFT)) & IOMUXD_ESAI1_FSR_PDRV_MASK)
#define IOMUXD_ESAI1_FSR_ESAI1_FSR_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI1_FSR_ESAI1_FSR_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI1_FSR_ESAI1_FSR_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FSR_ESAI1_FSR_reserved_1_4_SHIFT)) & IOMUXD_ESAI1_FSR_ESAI1_FSR_reserved_1_4_MASK)
#define IOMUXD_ESAI1_FSR_PULL_MASK               (0x60U)
#define IOMUXD_ESAI1_FSR_PULL_SHIFT              (5U)
#define IOMUXD_ESAI1_FSR_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FSR_PULL_SHIFT)) & IOMUXD_ESAI1_FSR_PULL_MASK)
#define IOMUXD_ESAI1_FSR_ESAI1_FSR_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI1_FSR_ESAI1_FSR_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI1_FSR_ESAI1_FSR_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FSR_ESAI1_FSR_reserved_7_18_SHIFT)) & IOMUXD_ESAI1_FSR_ESAI1_FSR_reserved_7_18_MASK)
#define IOMUXD_ESAI1_FSR_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_ESAI1_FSR_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI1_FSR_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FSR_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI1_FSR_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI1_FSR_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_ESAI1_FSR_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_ESAI1_FSR_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FSR_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI1_FSR_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI1_FSR_lp_config_MASK          (0x1800000U)
#define IOMUXD_ESAI1_FSR_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI1_FSR_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FSR_lp_config_SHIFT)) & IOMUXD_ESAI1_FSR_lp_config_MASK)
#define IOMUXD_ESAI1_FSR_sw_config_MASK          (0x6000000U)
#define IOMUXD_ESAI1_FSR_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI1_FSR_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FSR_sw_config_SHIFT)) & IOMUXD_ESAI1_FSR_sw_config_MASK)
#define IOMUXD_ESAI1_FSR_mux_mode_MASK           (0x38000000U)
#define IOMUXD_ESAI1_FSR_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI1.FSR
 *  0b011..LSIO.GPIO2.IO04
 */
#define IOMUXD_ESAI1_FSR_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FSR_mux_mode_SHIFT)) & IOMUXD_ESAI1_FSR_mux_mode_MASK)
#define IOMUXD_ESAI1_FSR_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_ESAI1_FSR_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_ESAI1_FSR_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FSR_update_pad_ctl_SHIFT)) & IOMUXD_ESAI1_FSR_update_pad_ctl_MASK)
#define IOMUXD_ESAI1_FSR_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_ESAI1_FSR_update_mux_mode_SHIFT   (31U)
#define IOMUXD_ESAI1_FSR_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FSR_update_mux_mode_SHIFT)) & IOMUXD_ESAI1_FSR_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI1_FST - ESAI1_FST */
/*! @{ */
#define IOMUXD_ESAI1_FST_PDRV_MASK               (0x1U)
#define IOMUXD_ESAI1_FST_PDRV_SHIFT              (0U)
#define IOMUXD_ESAI1_FST_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FST_PDRV_SHIFT)) & IOMUXD_ESAI1_FST_PDRV_MASK)
#define IOMUXD_ESAI1_FST_ESAI1_FST_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI1_FST_ESAI1_FST_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI1_FST_ESAI1_FST_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FST_ESAI1_FST_reserved_1_4_SHIFT)) & IOMUXD_ESAI1_FST_ESAI1_FST_reserved_1_4_MASK)
#define IOMUXD_ESAI1_FST_PULL_MASK               (0x60U)
#define IOMUXD_ESAI1_FST_PULL_SHIFT              (5U)
#define IOMUXD_ESAI1_FST_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FST_PULL_SHIFT)) & IOMUXD_ESAI1_FST_PULL_MASK)
#define IOMUXD_ESAI1_FST_ESAI1_FST_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI1_FST_ESAI1_FST_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI1_FST_ESAI1_FST_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FST_ESAI1_FST_reserved_7_18_SHIFT)) & IOMUXD_ESAI1_FST_ESAI1_FST_reserved_7_18_MASK)
#define IOMUXD_ESAI1_FST_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_ESAI1_FST_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI1_FST_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FST_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI1_FST_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI1_FST_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_ESAI1_FST_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_ESAI1_FST_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FST_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI1_FST_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI1_FST_lp_config_MASK          (0x1800000U)
#define IOMUXD_ESAI1_FST_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI1_FST_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FST_lp_config_SHIFT)) & IOMUXD_ESAI1_FST_lp_config_MASK)
#define IOMUXD_ESAI1_FST_sw_config_MASK          (0x6000000U)
#define IOMUXD_ESAI1_FST_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI1_FST_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FST_sw_config_SHIFT)) & IOMUXD_ESAI1_FST_sw_config_MASK)
#define IOMUXD_ESAI1_FST_mux_mode_MASK           (0x38000000U)
#define IOMUXD_ESAI1_FST_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI1.FST
 *  0b001..AUD.SPDIF0.EXT_CLK
 *  0b011..LSIO.GPIO2.IO05
 */
#define IOMUXD_ESAI1_FST_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FST_mux_mode_SHIFT)) & IOMUXD_ESAI1_FST_mux_mode_MASK)
#define IOMUXD_ESAI1_FST_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_ESAI1_FST_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_ESAI1_FST_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FST_update_pad_ctl_SHIFT)) & IOMUXD_ESAI1_FST_update_pad_ctl_MASK)
#define IOMUXD_ESAI1_FST_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_ESAI1_FST_update_mux_mode_SHIFT   (31U)
#define IOMUXD_ESAI1_FST_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_FST_update_mux_mode_SHIFT)) & IOMUXD_ESAI1_FST_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI1_SCKR - ESAI1_SCKR */
/*! @{ */
#define IOMUXD_ESAI1_SCKR_PDRV_MASK              (0x1U)
#define IOMUXD_ESAI1_SCKR_PDRV_SHIFT             (0U)
#define IOMUXD_ESAI1_SCKR_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKR_PDRV_SHIFT)) & IOMUXD_ESAI1_SCKR_PDRV_MASK)
#define IOMUXD_ESAI1_SCKR_ESAI1_SCKR_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI1_SCKR_ESAI1_SCKR_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI1_SCKR_ESAI1_SCKR_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKR_ESAI1_SCKR_reserved_1_4_SHIFT)) & IOMUXD_ESAI1_SCKR_ESAI1_SCKR_reserved_1_4_MASK)
#define IOMUXD_ESAI1_SCKR_PULL_MASK              (0x60U)
#define IOMUXD_ESAI1_SCKR_PULL_SHIFT             (5U)
#define IOMUXD_ESAI1_SCKR_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKR_PULL_SHIFT)) & IOMUXD_ESAI1_SCKR_PULL_MASK)
#define IOMUXD_ESAI1_SCKR_ESAI1_SCKR_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI1_SCKR_ESAI1_SCKR_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI1_SCKR_ESAI1_SCKR_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKR_ESAI1_SCKR_reserved_7_18_SHIFT)) & IOMUXD_ESAI1_SCKR_ESAI1_SCKR_reserved_7_18_MASK)
#define IOMUXD_ESAI1_SCKR_WAKEUP_CTRL_MASK       (0x380000U)
#define IOMUXD_ESAI1_SCKR_WAKEUP_CTRL_SHIFT      (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI1_SCKR_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKR_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI1_SCKR_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI1_SCKR_WAKEUP_MASK_MASK       (0x400000U)
#define IOMUXD_ESAI1_SCKR_WAKEUP_MASK_SHIFT      (22U)
#define IOMUXD_ESAI1_SCKR_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKR_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI1_SCKR_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI1_SCKR_lp_config_MASK         (0x1800000U)
#define IOMUXD_ESAI1_SCKR_lp_config_SHIFT        (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI1_SCKR_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKR_lp_config_SHIFT)) & IOMUXD_ESAI1_SCKR_lp_config_MASK)
#define IOMUXD_ESAI1_SCKR_sw_config_MASK         (0x6000000U)
#define IOMUXD_ESAI1_SCKR_sw_config_SHIFT        (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI1_SCKR_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKR_sw_config_SHIFT)) & IOMUXD_ESAI1_SCKR_sw_config_MASK)
#define IOMUXD_ESAI1_SCKR_mux_mode_MASK          (0x38000000U)
#define IOMUXD_ESAI1_SCKR_mux_mode_SHIFT         (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI1.SCKR
 *  0b011..LSIO.GPIO2.IO06
 */
#define IOMUXD_ESAI1_SCKR_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKR_mux_mode_SHIFT)) & IOMUXD_ESAI1_SCKR_mux_mode_MASK)
#define IOMUXD_ESAI1_SCKR_update_pad_ctl_MASK    (0x40000000U)
#define IOMUXD_ESAI1_SCKR_update_pad_ctl_SHIFT   (30U)
#define IOMUXD_ESAI1_SCKR_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKR_update_pad_ctl_SHIFT)) & IOMUXD_ESAI1_SCKR_update_pad_ctl_MASK)
#define IOMUXD_ESAI1_SCKR_update_mux_mode_MASK   (0x80000000U)
#define IOMUXD_ESAI1_SCKR_update_mux_mode_SHIFT  (31U)
#define IOMUXD_ESAI1_SCKR_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKR_update_mux_mode_SHIFT)) & IOMUXD_ESAI1_SCKR_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI1_SCKT - ESAI1_SCKT */
/*! @{ */
#define IOMUXD_ESAI1_SCKT_PDRV_MASK              (0x1U)
#define IOMUXD_ESAI1_SCKT_PDRV_SHIFT             (0U)
#define IOMUXD_ESAI1_SCKT_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKT_PDRV_SHIFT)) & IOMUXD_ESAI1_SCKT_PDRV_MASK)
#define IOMUXD_ESAI1_SCKT_ESAI1_SCKT_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI1_SCKT_ESAI1_SCKT_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI1_SCKT_ESAI1_SCKT_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKT_ESAI1_SCKT_reserved_1_4_SHIFT)) & IOMUXD_ESAI1_SCKT_ESAI1_SCKT_reserved_1_4_MASK)
#define IOMUXD_ESAI1_SCKT_PULL_MASK              (0x60U)
#define IOMUXD_ESAI1_SCKT_PULL_SHIFT             (5U)
#define IOMUXD_ESAI1_SCKT_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKT_PULL_SHIFT)) & IOMUXD_ESAI1_SCKT_PULL_MASK)
#define IOMUXD_ESAI1_SCKT_ESAI1_SCKT_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI1_SCKT_ESAI1_SCKT_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI1_SCKT_ESAI1_SCKT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKT_ESAI1_SCKT_reserved_7_18_SHIFT)) & IOMUXD_ESAI1_SCKT_ESAI1_SCKT_reserved_7_18_MASK)
#define IOMUXD_ESAI1_SCKT_WAKEUP_CTRL_MASK       (0x380000U)
#define IOMUXD_ESAI1_SCKT_WAKEUP_CTRL_SHIFT      (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI1_SCKT_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKT_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI1_SCKT_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI1_SCKT_WAKEUP_MASK_MASK       (0x400000U)
#define IOMUXD_ESAI1_SCKT_WAKEUP_MASK_SHIFT      (22U)
#define IOMUXD_ESAI1_SCKT_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKT_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI1_SCKT_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI1_SCKT_lp_config_MASK         (0x1800000U)
#define IOMUXD_ESAI1_SCKT_lp_config_SHIFT        (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI1_SCKT_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKT_lp_config_SHIFT)) & IOMUXD_ESAI1_SCKT_lp_config_MASK)
#define IOMUXD_ESAI1_SCKT_sw_config_MASK         (0x6000000U)
#define IOMUXD_ESAI1_SCKT_sw_config_SHIFT        (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI1_SCKT_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKT_sw_config_SHIFT)) & IOMUXD_ESAI1_SCKT_sw_config_MASK)
#define IOMUXD_ESAI1_SCKT_mux_mode_MASK          (0x38000000U)
#define IOMUXD_ESAI1_SCKT_mux_mode_SHIFT         (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI1.SCKT
 *  0b001..AUD.SAI2.RXC
 *  0b010..AUD.SPDIF0.EXT_CLK
 *  0b011..LSIO.GPIO2.IO07
 */
#define IOMUXD_ESAI1_SCKT_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKT_mux_mode_SHIFT)) & IOMUXD_ESAI1_SCKT_mux_mode_MASK)
#define IOMUXD_ESAI1_SCKT_update_pad_ctl_MASK    (0x40000000U)
#define IOMUXD_ESAI1_SCKT_update_pad_ctl_SHIFT   (30U)
#define IOMUXD_ESAI1_SCKT_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKT_update_pad_ctl_SHIFT)) & IOMUXD_ESAI1_SCKT_update_pad_ctl_MASK)
#define IOMUXD_ESAI1_SCKT_update_mux_mode_MASK   (0x80000000U)
#define IOMUXD_ESAI1_SCKT_update_mux_mode_SHIFT  (31U)
#define IOMUXD_ESAI1_SCKT_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_SCKT_update_mux_mode_SHIFT)) & IOMUXD_ESAI1_SCKT_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI1_TX0 - ESAI1_TX0 */
/*! @{ */
#define IOMUXD_ESAI1_TX0_PDRV_MASK               (0x1U)
#define IOMUXD_ESAI1_TX0_PDRV_SHIFT              (0U)
#define IOMUXD_ESAI1_TX0_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX0_PDRV_SHIFT)) & IOMUXD_ESAI1_TX0_PDRV_MASK)
#define IOMUXD_ESAI1_TX0_ESAI1_TX0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI1_TX0_ESAI1_TX0_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI1_TX0_ESAI1_TX0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX0_ESAI1_TX0_reserved_1_4_SHIFT)) & IOMUXD_ESAI1_TX0_ESAI1_TX0_reserved_1_4_MASK)
#define IOMUXD_ESAI1_TX0_PULL_MASK               (0x60U)
#define IOMUXD_ESAI1_TX0_PULL_SHIFT              (5U)
#define IOMUXD_ESAI1_TX0_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX0_PULL_SHIFT)) & IOMUXD_ESAI1_TX0_PULL_MASK)
#define IOMUXD_ESAI1_TX0_ESAI1_TX0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI1_TX0_ESAI1_TX0_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI1_TX0_ESAI1_TX0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX0_ESAI1_TX0_reserved_7_18_SHIFT)) & IOMUXD_ESAI1_TX0_ESAI1_TX0_reserved_7_18_MASK)
#define IOMUXD_ESAI1_TX0_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_ESAI1_TX0_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI1_TX0_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI1_TX0_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI1_TX0_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_ESAI1_TX0_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_ESAI1_TX0_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX0_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI1_TX0_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI1_TX0_lp_config_MASK          (0x1800000U)
#define IOMUXD_ESAI1_TX0_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI1_TX0_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX0_lp_config_SHIFT)) & IOMUXD_ESAI1_TX0_lp_config_MASK)
#define IOMUXD_ESAI1_TX0_sw_config_MASK          (0x6000000U)
#define IOMUXD_ESAI1_TX0_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI1_TX0_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX0_sw_config_SHIFT)) & IOMUXD_ESAI1_TX0_sw_config_MASK)
#define IOMUXD_ESAI1_TX0_mux_mode_MASK           (0x38000000U)
#define IOMUXD_ESAI1_TX0_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI1.TX0
 *  0b001..AUD.SAI2.RXD
 *  0b010..AUD.SPDIF0.RX
 *  0b011..LSIO.GPIO2.IO08
 */
#define IOMUXD_ESAI1_TX0_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX0_mux_mode_SHIFT)) & IOMUXD_ESAI1_TX0_mux_mode_MASK)
#define IOMUXD_ESAI1_TX0_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_ESAI1_TX0_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_ESAI1_TX0_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX0_update_pad_ctl_SHIFT)) & IOMUXD_ESAI1_TX0_update_pad_ctl_MASK)
#define IOMUXD_ESAI1_TX0_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_ESAI1_TX0_update_mux_mode_SHIFT   (31U)
#define IOMUXD_ESAI1_TX0_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX0_update_mux_mode_SHIFT)) & IOMUXD_ESAI1_TX0_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI1_TX1 - ESAI1_TX1 */
/*! @{ */
#define IOMUXD_ESAI1_TX1_PDRV_MASK               (0x1U)
#define IOMUXD_ESAI1_TX1_PDRV_SHIFT              (0U)
#define IOMUXD_ESAI1_TX1_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX1_PDRV_SHIFT)) & IOMUXD_ESAI1_TX1_PDRV_MASK)
#define IOMUXD_ESAI1_TX1_ESAI1_TX1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI1_TX1_ESAI1_TX1_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI1_TX1_ESAI1_TX1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX1_ESAI1_TX1_reserved_1_4_SHIFT)) & IOMUXD_ESAI1_TX1_ESAI1_TX1_reserved_1_4_MASK)
#define IOMUXD_ESAI1_TX1_PULL_MASK               (0x60U)
#define IOMUXD_ESAI1_TX1_PULL_SHIFT              (5U)
#define IOMUXD_ESAI1_TX1_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX1_PULL_SHIFT)) & IOMUXD_ESAI1_TX1_PULL_MASK)
#define IOMUXD_ESAI1_TX1_ESAI1_TX1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI1_TX1_ESAI1_TX1_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI1_TX1_ESAI1_TX1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX1_ESAI1_TX1_reserved_7_18_SHIFT)) & IOMUXD_ESAI1_TX1_ESAI1_TX1_reserved_7_18_MASK)
#define IOMUXD_ESAI1_TX1_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_ESAI1_TX1_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI1_TX1_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI1_TX1_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI1_TX1_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_ESAI1_TX1_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_ESAI1_TX1_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX1_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI1_TX1_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI1_TX1_lp_config_MASK          (0x1800000U)
#define IOMUXD_ESAI1_TX1_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI1_TX1_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX1_lp_config_SHIFT)) & IOMUXD_ESAI1_TX1_lp_config_MASK)
#define IOMUXD_ESAI1_TX1_sw_config_MASK          (0x6000000U)
#define IOMUXD_ESAI1_TX1_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI1_TX1_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX1_sw_config_SHIFT)) & IOMUXD_ESAI1_TX1_sw_config_MASK)
#define IOMUXD_ESAI1_TX1_mux_mode_MASK           (0x38000000U)
#define IOMUXD_ESAI1_TX1_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI1.TX1
 *  0b001..AUD.SAI2.RXFS
 *  0b010..AUD.SPDIF0.TX
 *  0b011..LSIO.GPIO2.IO09
 */
#define IOMUXD_ESAI1_TX1_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX1_mux_mode_SHIFT)) & IOMUXD_ESAI1_TX1_mux_mode_MASK)
#define IOMUXD_ESAI1_TX1_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_ESAI1_TX1_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_ESAI1_TX1_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX1_update_pad_ctl_SHIFT)) & IOMUXD_ESAI1_TX1_update_pad_ctl_MASK)
#define IOMUXD_ESAI1_TX1_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_ESAI1_TX1_update_mux_mode_SHIFT   (31U)
#define IOMUXD_ESAI1_TX1_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX1_update_mux_mode_SHIFT)) & IOMUXD_ESAI1_TX1_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI1_TX2_RX3 - ESAI1_TX2_RX3 */
/*! @{ */
#define IOMUXD_ESAI1_TX2_RX3_PDRV_MASK           (0x1U)
#define IOMUXD_ESAI1_TX2_RX3_PDRV_SHIFT          (0U)
#define IOMUXD_ESAI1_TX2_RX3_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX2_RX3_PDRV_SHIFT)) & IOMUXD_ESAI1_TX2_RX3_PDRV_MASK)
#define IOMUXD_ESAI1_TX2_RX3_ESAI1_TX2_RX3_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI1_TX2_RX3_ESAI1_TX2_RX3_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI1_TX2_RX3_ESAI1_TX2_RX3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX2_RX3_ESAI1_TX2_RX3_reserved_1_4_SHIFT)) & IOMUXD_ESAI1_TX2_RX3_ESAI1_TX2_RX3_reserved_1_4_MASK)
#define IOMUXD_ESAI1_TX2_RX3_PULL_MASK           (0x60U)
#define IOMUXD_ESAI1_TX2_RX3_PULL_SHIFT          (5U)
#define IOMUXD_ESAI1_TX2_RX3_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX2_RX3_PULL_SHIFT)) & IOMUXD_ESAI1_TX2_RX3_PULL_MASK)
#define IOMUXD_ESAI1_TX2_RX3_ESAI1_TX2_RX3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI1_TX2_RX3_ESAI1_TX2_RX3_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI1_TX2_RX3_ESAI1_TX2_RX3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX2_RX3_ESAI1_TX2_RX3_reserved_7_18_SHIFT)) & IOMUXD_ESAI1_TX2_RX3_ESAI1_TX2_RX3_reserved_7_18_MASK)
#define IOMUXD_ESAI1_TX2_RX3_WAKEUP_CTRL_MASK    (0x380000U)
#define IOMUXD_ESAI1_TX2_RX3_WAKEUP_CTRL_SHIFT   (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI1_TX2_RX3_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX2_RX3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI1_TX2_RX3_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI1_TX2_RX3_WAKEUP_MASK_MASK    (0x400000U)
#define IOMUXD_ESAI1_TX2_RX3_WAKEUP_MASK_SHIFT   (22U)
#define IOMUXD_ESAI1_TX2_RX3_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX2_RX3_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI1_TX2_RX3_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI1_TX2_RX3_lp_config_MASK      (0x1800000U)
#define IOMUXD_ESAI1_TX2_RX3_lp_config_SHIFT     (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI1_TX2_RX3_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX2_RX3_lp_config_SHIFT)) & IOMUXD_ESAI1_TX2_RX3_lp_config_MASK)
#define IOMUXD_ESAI1_TX2_RX3_sw_config_MASK      (0x6000000U)
#define IOMUXD_ESAI1_TX2_RX3_sw_config_SHIFT     (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI1_TX2_RX3_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX2_RX3_sw_config_SHIFT)) & IOMUXD_ESAI1_TX2_RX3_sw_config_MASK)
#define IOMUXD_ESAI1_TX2_RX3_mux_mode_MASK       (0x38000000U)
#define IOMUXD_ESAI1_TX2_RX3_mux_mode_SHIFT      (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI1.TX2_RX3
 *  0b001..AUD.SPDIF0.RX
 *  0b011..LSIO.GPIO2.IO10
 */
#define IOMUXD_ESAI1_TX2_RX3_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX2_RX3_mux_mode_SHIFT)) & IOMUXD_ESAI1_TX2_RX3_mux_mode_MASK)
#define IOMUXD_ESAI1_TX2_RX3_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ESAI1_TX2_RX3_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ESAI1_TX2_RX3_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX2_RX3_update_pad_ctl_SHIFT)) & IOMUXD_ESAI1_TX2_RX3_update_pad_ctl_MASK)
#define IOMUXD_ESAI1_TX2_RX3_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ESAI1_TX2_RX3_update_mux_mode_SHIFT (31U)
#define IOMUXD_ESAI1_TX2_RX3_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX2_RX3_update_mux_mode_SHIFT)) & IOMUXD_ESAI1_TX2_RX3_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI1_TX3_RX2 - ESAI1_TX3_RX2 */
/*! @{ */
#define IOMUXD_ESAI1_TX3_RX2_PDRV_MASK           (0x1U)
#define IOMUXD_ESAI1_TX3_RX2_PDRV_SHIFT          (0U)
#define IOMUXD_ESAI1_TX3_RX2_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX3_RX2_PDRV_SHIFT)) & IOMUXD_ESAI1_TX3_RX2_PDRV_MASK)
#define IOMUXD_ESAI1_TX3_RX2_ESAI1_TX3_RX2_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI1_TX3_RX2_ESAI1_TX3_RX2_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI1_TX3_RX2_ESAI1_TX3_RX2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX3_RX2_ESAI1_TX3_RX2_reserved_1_4_SHIFT)) & IOMUXD_ESAI1_TX3_RX2_ESAI1_TX3_RX2_reserved_1_4_MASK)
#define IOMUXD_ESAI1_TX3_RX2_PULL_MASK           (0x60U)
#define IOMUXD_ESAI1_TX3_RX2_PULL_SHIFT          (5U)
#define IOMUXD_ESAI1_TX3_RX2_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX3_RX2_PULL_SHIFT)) & IOMUXD_ESAI1_TX3_RX2_PULL_MASK)
#define IOMUXD_ESAI1_TX3_RX2_ESAI1_TX3_RX2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI1_TX3_RX2_ESAI1_TX3_RX2_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI1_TX3_RX2_ESAI1_TX3_RX2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX3_RX2_ESAI1_TX3_RX2_reserved_7_18_SHIFT)) & IOMUXD_ESAI1_TX3_RX2_ESAI1_TX3_RX2_reserved_7_18_MASK)
#define IOMUXD_ESAI1_TX3_RX2_WAKEUP_CTRL_MASK    (0x380000U)
#define IOMUXD_ESAI1_TX3_RX2_WAKEUP_CTRL_SHIFT   (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI1_TX3_RX2_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX3_RX2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI1_TX3_RX2_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI1_TX3_RX2_WAKEUP_MASK_MASK    (0x400000U)
#define IOMUXD_ESAI1_TX3_RX2_WAKEUP_MASK_SHIFT   (22U)
#define IOMUXD_ESAI1_TX3_RX2_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX3_RX2_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI1_TX3_RX2_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI1_TX3_RX2_lp_config_MASK      (0x1800000U)
#define IOMUXD_ESAI1_TX3_RX2_lp_config_SHIFT     (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI1_TX3_RX2_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX3_RX2_lp_config_SHIFT)) & IOMUXD_ESAI1_TX3_RX2_lp_config_MASK)
#define IOMUXD_ESAI1_TX3_RX2_sw_config_MASK      (0x6000000U)
#define IOMUXD_ESAI1_TX3_RX2_sw_config_SHIFT     (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI1_TX3_RX2_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX3_RX2_sw_config_SHIFT)) & IOMUXD_ESAI1_TX3_RX2_sw_config_MASK)
#define IOMUXD_ESAI1_TX3_RX2_mux_mode_MASK       (0x38000000U)
#define IOMUXD_ESAI1_TX3_RX2_mux_mode_SHIFT      (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI1.TX3_RX2
 *  0b001..AUD.SPDIF0.TX
 *  0b011..LSIO.GPIO2.IO11
 */
#define IOMUXD_ESAI1_TX3_RX2_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX3_RX2_mux_mode_SHIFT)) & IOMUXD_ESAI1_TX3_RX2_mux_mode_MASK)
#define IOMUXD_ESAI1_TX3_RX2_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ESAI1_TX3_RX2_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ESAI1_TX3_RX2_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX3_RX2_update_pad_ctl_SHIFT)) & IOMUXD_ESAI1_TX3_RX2_update_pad_ctl_MASK)
#define IOMUXD_ESAI1_TX3_RX2_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ESAI1_TX3_RX2_update_mux_mode_SHIFT (31U)
#define IOMUXD_ESAI1_TX3_RX2_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX3_RX2_update_mux_mode_SHIFT)) & IOMUXD_ESAI1_TX3_RX2_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI1_TX4_RX1 - ESAI1_TX4_RX1 */
/*! @{ */
#define IOMUXD_ESAI1_TX4_RX1_PDRV_MASK           (0x1U)
#define IOMUXD_ESAI1_TX4_RX1_PDRV_SHIFT          (0U)
#define IOMUXD_ESAI1_TX4_RX1_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX4_RX1_PDRV_SHIFT)) & IOMUXD_ESAI1_TX4_RX1_PDRV_MASK)
#define IOMUXD_ESAI1_TX4_RX1_ESAI1_TX4_RX1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI1_TX4_RX1_ESAI1_TX4_RX1_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI1_TX4_RX1_ESAI1_TX4_RX1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX4_RX1_ESAI1_TX4_RX1_reserved_1_4_SHIFT)) & IOMUXD_ESAI1_TX4_RX1_ESAI1_TX4_RX1_reserved_1_4_MASK)
#define IOMUXD_ESAI1_TX4_RX1_PULL_MASK           (0x60U)
#define IOMUXD_ESAI1_TX4_RX1_PULL_SHIFT          (5U)
#define IOMUXD_ESAI1_TX4_RX1_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX4_RX1_PULL_SHIFT)) & IOMUXD_ESAI1_TX4_RX1_PULL_MASK)
#define IOMUXD_ESAI1_TX4_RX1_ESAI1_TX4_RX1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI1_TX4_RX1_ESAI1_TX4_RX1_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI1_TX4_RX1_ESAI1_TX4_RX1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX4_RX1_ESAI1_TX4_RX1_reserved_7_18_SHIFT)) & IOMUXD_ESAI1_TX4_RX1_ESAI1_TX4_RX1_reserved_7_18_MASK)
#define IOMUXD_ESAI1_TX4_RX1_WAKEUP_CTRL_MASK    (0x380000U)
#define IOMUXD_ESAI1_TX4_RX1_WAKEUP_CTRL_SHIFT   (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI1_TX4_RX1_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX4_RX1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI1_TX4_RX1_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI1_TX4_RX1_WAKEUP_MASK_MASK    (0x400000U)
#define IOMUXD_ESAI1_TX4_RX1_WAKEUP_MASK_SHIFT   (22U)
#define IOMUXD_ESAI1_TX4_RX1_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX4_RX1_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI1_TX4_RX1_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI1_TX4_RX1_lp_config_MASK      (0x1800000U)
#define IOMUXD_ESAI1_TX4_RX1_lp_config_SHIFT     (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI1_TX4_RX1_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX4_RX1_lp_config_SHIFT)) & IOMUXD_ESAI1_TX4_RX1_lp_config_MASK)
#define IOMUXD_ESAI1_TX4_RX1_sw_config_MASK      (0x6000000U)
#define IOMUXD_ESAI1_TX4_RX1_sw_config_SHIFT     (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI1_TX4_RX1_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX4_RX1_sw_config_SHIFT)) & IOMUXD_ESAI1_TX4_RX1_sw_config_MASK)
#define IOMUXD_ESAI1_TX4_RX1_mux_mode_MASK       (0x38000000U)
#define IOMUXD_ESAI1_TX4_RX1_mux_mode_SHIFT      (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI1.TX4_RX1
 *  0b011..LSIO.GPIO2.IO12
 */
#define IOMUXD_ESAI1_TX4_RX1_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX4_RX1_mux_mode_SHIFT)) & IOMUXD_ESAI1_TX4_RX1_mux_mode_MASK)
#define IOMUXD_ESAI1_TX4_RX1_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ESAI1_TX4_RX1_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ESAI1_TX4_RX1_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX4_RX1_update_pad_ctl_SHIFT)) & IOMUXD_ESAI1_TX4_RX1_update_pad_ctl_MASK)
#define IOMUXD_ESAI1_TX4_RX1_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ESAI1_TX4_RX1_update_mux_mode_SHIFT (31U)
#define IOMUXD_ESAI1_TX4_RX1_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX4_RX1_update_mux_mode_SHIFT)) & IOMUXD_ESAI1_TX4_RX1_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI1_TX5_RX0 - ESAI1_TX5_RX0 */
/*! @{ */
#define IOMUXD_ESAI1_TX5_RX0_PDRV_MASK           (0x1U)
#define IOMUXD_ESAI1_TX5_RX0_PDRV_SHIFT          (0U)
#define IOMUXD_ESAI1_TX5_RX0_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX5_RX0_PDRV_SHIFT)) & IOMUXD_ESAI1_TX5_RX0_PDRV_MASK)
#define IOMUXD_ESAI1_TX5_RX0_ESAI1_TX5_RX0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI1_TX5_RX0_ESAI1_TX5_RX0_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI1_TX5_RX0_ESAI1_TX5_RX0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX5_RX0_ESAI1_TX5_RX0_reserved_1_4_SHIFT)) & IOMUXD_ESAI1_TX5_RX0_ESAI1_TX5_RX0_reserved_1_4_MASK)
#define IOMUXD_ESAI1_TX5_RX0_PULL_MASK           (0x60U)
#define IOMUXD_ESAI1_TX5_RX0_PULL_SHIFT          (5U)
#define IOMUXD_ESAI1_TX5_RX0_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX5_RX0_PULL_SHIFT)) & IOMUXD_ESAI1_TX5_RX0_PULL_MASK)
#define IOMUXD_ESAI1_TX5_RX0_ESAI1_TX5_RX0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI1_TX5_RX0_ESAI1_TX5_RX0_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI1_TX5_RX0_ESAI1_TX5_RX0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX5_RX0_ESAI1_TX5_RX0_reserved_7_18_SHIFT)) & IOMUXD_ESAI1_TX5_RX0_ESAI1_TX5_RX0_reserved_7_18_MASK)
#define IOMUXD_ESAI1_TX5_RX0_WAKEUP_CTRL_MASK    (0x380000U)
#define IOMUXD_ESAI1_TX5_RX0_WAKEUP_CTRL_SHIFT   (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI1_TX5_RX0_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX5_RX0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI1_TX5_RX0_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI1_TX5_RX0_WAKEUP_MASK_MASK    (0x400000U)
#define IOMUXD_ESAI1_TX5_RX0_WAKEUP_MASK_SHIFT   (22U)
#define IOMUXD_ESAI1_TX5_RX0_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX5_RX0_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI1_TX5_RX0_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI1_TX5_RX0_lp_config_MASK      (0x1800000U)
#define IOMUXD_ESAI1_TX5_RX0_lp_config_SHIFT     (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI1_TX5_RX0_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX5_RX0_lp_config_SHIFT)) & IOMUXD_ESAI1_TX5_RX0_lp_config_MASK)
#define IOMUXD_ESAI1_TX5_RX0_sw_config_MASK      (0x6000000U)
#define IOMUXD_ESAI1_TX5_RX0_sw_config_SHIFT     (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI1_TX5_RX0_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX5_RX0_sw_config_SHIFT)) & IOMUXD_ESAI1_TX5_RX0_sw_config_MASK)
#define IOMUXD_ESAI1_TX5_RX0_mux_mode_MASK       (0x38000000U)
#define IOMUXD_ESAI1_TX5_RX0_mux_mode_SHIFT      (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI1.TX5_RX0
 *  0b011..LSIO.GPIO2.IO13
 */
#define IOMUXD_ESAI1_TX5_RX0_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX5_RX0_mux_mode_SHIFT)) & IOMUXD_ESAI1_TX5_RX0_mux_mode_MASK)
#define IOMUXD_ESAI1_TX5_RX0_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ESAI1_TX5_RX0_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ESAI1_TX5_RX0_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX5_RX0_update_pad_ctl_SHIFT)) & IOMUXD_ESAI1_TX5_RX0_update_pad_ctl_MASK)
#define IOMUXD_ESAI1_TX5_RX0_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ESAI1_TX5_RX0_update_mux_mode_SHIFT (31U)
#define IOMUXD_ESAI1_TX5_RX0_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI1_TX5_RX0_update_mux_mode_SHIFT)) & IOMUXD_ESAI1_TX5_RX0_update_mux_mode_MASK)
/*! @} */

/*! @name SPDIF0_RX - SPDIF0_RX */
/*! @{ */
#define IOMUXD_SPDIF0_RX_PDRV_MASK               (0x1U)
#define IOMUXD_SPDIF0_RX_PDRV_SHIFT              (0U)
#define IOMUXD_SPDIF0_RX_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_PDRV_SHIFT)) & IOMUXD_SPDIF0_RX_PDRV_MASK)
#define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_SHIFT)) & IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_MASK)
#define IOMUXD_SPDIF0_RX_PULL_MASK               (0x60U)
#define IOMUXD_SPDIF0_RX_PULL_SHIFT              (5U)
#define IOMUXD_SPDIF0_RX_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_PULL_SHIFT)) & IOMUXD_SPDIF0_RX_PULL_MASK)
#define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_SHIFT)) & IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_MASK)
#define IOMUXD_SPDIF0_RX_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_SPDIF0_RX_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPDIF0_RX_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPDIF0_RX_WAKEUP_CTRL_MASK)
#define IOMUXD_SPDIF0_RX_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_SPDIF0_RX_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_SPDIF0_RX_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_SPDIF0_RX_WAKEUP_MASK_MASK)
#define IOMUXD_SPDIF0_RX_lp_config_MASK          (0x1800000U)
#define IOMUXD_SPDIF0_RX_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPDIF0_RX_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_lp_config_SHIFT)) & IOMUXD_SPDIF0_RX_lp_config_MASK)
#define IOMUXD_SPDIF0_RX_sw_config_MASK          (0x6000000U)
#define IOMUXD_SPDIF0_RX_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPDIF0_RX_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_sw_config_SHIFT)) & IOMUXD_SPDIF0_RX_sw_config_MASK)
#define IOMUXD_SPDIF0_RX_mux_mode_MASK           (0x38000000U)
#define IOMUXD_SPDIF0_RX_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.SPDIF0.RX
 *  0b001..AUD.MQS.R
 *  0b010..AUD.ACM.MCLK_IN1
 *  0b011..LSIO.GPIO2.IO14
 */
#define IOMUXD_SPDIF0_RX_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_mux_mode_SHIFT)) & IOMUXD_SPDIF0_RX_mux_mode_MASK)
#define IOMUXD_SPDIF0_RX_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_SPDIF0_RX_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_SPDIF0_RX_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_update_pad_ctl_SHIFT)) & IOMUXD_SPDIF0_RX_update_pad_ctl_MASK)
#define IOMUXD_SPDIF0_RX_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_SPDIF0_RX_update_mux_mode_SHIFT   (31U)
#define IOMUXD_SPDIF0_RX_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_update_mux_mode_SHIFT)) & IOMUXD_SPDIF0_RX_update_mux_mode_MASK)
/*! @} */

/*! @name SPDIF0_TX - SPDIF0_TX */
/*! @{ */
#define IOMUXD_SPDIF0_TX_PDRV_MASK               (0x1U)
#define IOMUXD_SPDIF0_TX_PDRV_SHIFT              (0U)
#define IOMUXD_SPDIF0_TX_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_PDRV_SHIFT)) & IOMUXD_SPDIF0_TX_PDRV_MASK)
#define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_SHIFT)) & IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_MASK)
#define IOMUXD_SPDIF0_TX_PULL_MASK               (0x60U)
#define IOMUXD_SPDIF0_TX_PULL_SHIFT              (5U)
#define IOMUXD_SPDIF0_TX_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_PULL_SHIFT)) & IOMUXD_SPDIF0_TX_PULL_MASK)
#define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_SHIFT)) & IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_MASK)
#define IOMUXD_SPDIF0_TX_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_SPDIF0_TX_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPDIF0_TX_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPDIF0_TX_WAKEUP_CTRL_MASK)
#define IOMUXD_SPDIF0_TX_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_SPDIF0_TX_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_SPDIF0_TX_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_SPDIF0_TX_WAKEUP_MASK_MASK)
#define IOMUXD_SPDIF0_TX_lp_config_MASK          (0x1800000U)
#define IOMUXD_SPDIF0_TX_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPDIF0_TX_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_lp_config_SHIFT)) & IOMUXD_SPDIF0_TX_lp_config_MASK)
#define IOMUXD_SPDIF0_TX_sw_config_MASK          (0x6000000U)
#define IOMUXD_SPDIF0_TX_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPDIF0_TX_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_sw_config_SHIFT)) & IOMUXD_SPDIF0_TX_sw_config_MASK)
#define IOMUXD_SPDIF0_TX_mux_mode_MASK           (0x38000000U)
#define IOMUXD_SPDIF0_TX_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.SPDIF0.TX
 *  0b001..AUD.MQS.L
 *  0b010..AUD.ACM.MCLK_OUT1
 *  0b011..LSIO.GPIO2.IO15
 */
#define IOMUXD_SPDIF0_TX_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_mux_mode_SHIFT)) & IOMUXD_SPDIF0_TX_mux_mode_MASK)
#define IOMUXD_SPDIF0_TX_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_SPDIF0_TX_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_SPDIF0_TX_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_update_pad_ctl_SHIFT)) & IOMUXD_SPDIF0_TX_update_pad_ctl_MASK)
#define IOMUXD_SPDIF0_TX_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_SPDIF0_TX_update_mux_mode_SHIFT   (31U)
#define IOMUXD_SPDIF0_TX_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_update_mux_mode_SHIFT)) & IOMUXD_SPDIF0_TX_update_mux_mode_MASK)
/*! @} */

/*! @name SPDIF0_EXT_CLK - SPDIF0_EXT_CLK */
/*! @{ */
#define IOMUXD_SPDIF0_EXT_CLK_PDRV_MASK          (0x1U)
#define IOMUXD_SPDIF0_EXT_CLK_PDRV_SHIFT         (0U)
#define IOMUXD_SPDIF0_EXT_CLK_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_PDRV_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_PDRV_MASK)
#define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_MASK)
#define IOMUXD_SPDIF0_EXT_CLK_PULL_MASK          (0x60U)
#define IOMUXD_SPDIF0_EXT_CLK_PULL_SHIFT         (5U)
#define IOMUXD_SPDIF0_EXT_CLK_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_PULL_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_PULL_MASK)
#define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_MASK)
#define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_MASK)
#define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_MASK)
#define IOMUXD_SPDIF0_EXT_CLK_lp_config_MASK     (0x1800000U)
#define IOMUXD_SPDIF0_EXT_CLK_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPDIF0_EXT_CLK_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_lp_config_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_lp_config_MASK)
#define IOMUXD_SPDIF0_EXT_CLK_sw_config_MASK     (0x6000000U)
#define IOMUXD_SPDIF0_EXT_CLK_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPDIF0_EXT_CLK_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_sw_config_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_sw_config_MASK)
#define IOMUXD_SPDIF0_EXT_CLK_mux_mode_MASK      (0x38000000U)
#define IOMUXD_SPDIF0_EXT_CLK_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.SPDIF0.EXT_CLK
 *  0b001..DMA.DMA0.REQ_IN0
 *  0b011..LSIO.GPIO2.IO16
 */
#define IOMUXD_SPDIF0_EXT_CLK_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_mux_mode_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_mux_mode_MASK)
#define IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_SHIFT (30U)
#define IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_MASK)
#define IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_SHIFT (31U)
#define IOMUXD_SPDIF0_EXT_CLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_MASK)
/*! @} */

/*! @name SPI3_SCK - SPI3_SCK */
/*! @{ */
#define IOMUXD_SPI3_SCK_PDRV_MASK                (0x1U)
#define IOMUXD_SPI3_SCK_PDRV_SHIFT               (0U)
#define IOMUXD_SPI3_SCK_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_PDRV_SHIFT)) & IOMUXD_SPI3_SCK_PDRV_MASK)
#define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_SHIFT)) & IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_MASK)
#define IOMUXD_SPI3_SCK_PULL_MASK                (0x60U)
#define IOMUXD_SPI3_SCK_PULL_SHIFT               (5U)
#define IOMUXD_SPI3_SCK_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_PULL_SHIFT)) & IOMUXD_SPI3_SCK_PULL_MASK)
#define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_SHIFT)) & IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_MASK)
#define IOMUXD_SPI3_SCK_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI3_SCK_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI3_SCK_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_SCK_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI3_SCK_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI3_SCK_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI3_SCK_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_SCK_WAKEUP_MASK_MASK)
#define IOMUXD_SPI3_SCK_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI3_SCK_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI3_SCK_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_lp_config_SHIFT)) & IOMUXD_SPI3_SCK_lp_config_MASK)
#define IOMUXD_SPI3_SCK_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI3_SCK_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI3_SCK_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_sw_config_SHIFT)) & IOMUXD_SPI3_SCK_sw_config_MASK)
#define IOMUXD_SPI3_SCK_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI3_SCK_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI3.SCK
 *  0b011..LSIO.GPIO2.IO17
 */
#define IOMUXD_SPI3_SCK_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_mux_mode_SHIFT)) & IOMUXD_SPI3_SCK_mux_mode_MASK)
#define IOMUXD_SPI3_SCK_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI3_SCK_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI3_SCK_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_SCK_update_pad_ctl_MASK)
#define IOMUXD_SPI3_SCK_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI3_SCK_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI3_SCK_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_update_mux_mode_SHIFT)) & IOMUXD_SPI3_SCK_update_mux_mode_MASK)
/*! @} */

/*! @name SPI3_SDO - SPI3_SDO */
/*! @{ */
#define IOMUXD_SPI3_SDO_PDRV_MASK                (0x1U)
#define IOMUXD_SPI3_SDO_PDRV_SHIFT               (0U)
#define IOMUXD_SPI3_SDO_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_PDRV_SHIFT)) & IOMUXD_SPI3_SDO_PDRV_MASK)
#define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_SHIFT)) & IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_MASK)
#define IOMUXD_SPI3_SDO_PULL_MASK                (0x60U)
#define IOMUXD_SPI3_SDO_PULL_SHIFT               (5U)
#define IOMUXD_SPI3_SDO_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_PULL_SHIFT)) & IOMUXD_SPI3_SDO_PULL_MASK)
#define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_SHIFT)) & IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_MASK)
#define IOMUXD_SPI3_SDO_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI3_SDO_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI3_SDO_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_SDO_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI3_SDO_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI3_SDO_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI3_SDO_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_SDO_WAKEUP_MASK_MASK)
#define IOMUXD_SPI3_SDO_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI3_SDO_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI3_SDO_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_lp_config_SHIFT)) & IOMUXD_SPI3_SDO_lp_config_MASK)
#define IOMUXD_SPI3_SDO_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI3_SDO_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI3_SDO_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_sw_config_SHIFT)) & IOMUXD_SPI3_SDO_sw_config_MASK)
#define IOMUXD_SPI3_SDO_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI3_SDO_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI3.SDO
 *  0b001..DMA.FTM.CH0
 *  0b011..LSIO.GPIO2.IO18
 */
#define IOMUXD_SPI3_SDO_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_mux_mode_SHIFT)) & IOMUXD_SPI3_SDO_mux_mode_MASK)
#define IOMUXD_SPI3_SDO_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI3_SDO_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI3_SDO_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_SDO_update_pad_ctl_MASK)
#define IOMUXD_SPI3_SDO_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI3_SDO_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI3_SDO_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_update_mux_mode_SHIFT)) & IOMUXD_SPI3_SDO_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_1_2 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_FSR_MASK   (0x1U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_FSR_SHIFT  (0U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_FSR(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ESAI1_FSR_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ESAI1_FSR_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_FST_MASK   (0x2U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_FST_SHIFT  (1U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_FST(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ESAI1_FST_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ESAI1_FST_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_SCKR_MASK  (0x4U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_SCKR_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_SCKR(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ESAI1_SCKR_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ESAI1_SCKR_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_SCKT_MASK  (0x8U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_SCKT_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_SCKT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ESAI1_SCKT_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ESAI1_SCKT_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX0_MASK   (0x10U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX0_SHIFT  (4U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX0(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX0_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX1_MASK   (0x20U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX1_SHIFT  (5U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX1(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX1_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX2_RX3_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX2_RX3_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX2_RX3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX2_RX3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX2_RX3_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX3_RX2_MASK (0x80U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX3_RX2_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX3_RX2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX3_RX2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX3_RX2_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX4_RX1_MASK (0x100U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX4_RX1_SHIFT (8U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX4_RX1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX4_RX1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX4_RX1_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX5_RX0_MASK (0x200U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX5_RX0_SHIFT (9U)
#define IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX5_RX0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX5_RX0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ESAI1_TX5_RX0_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_RX_MASK   (0x400U)
#define IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_RX_SHIFT  (10U)
#define IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_RX(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_RX_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_TX_MASK   (0x800U)
#define IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_TX_SHIFT  (11U)
#define IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_TX(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_TX_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_EXT_CLK_MASK (0x1000U)
#define IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_EXT_CLK_SHIFT (12U)
#define IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_EXT_CLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_EXT_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_SPDIF0_EXT_CLK_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_SPI3_SCK_MASK    (0x2000U)
#define IOMUXD_IOMUXD_GROUP_1_2_SPI3_SCK_SHIFT   (13U)
#define IOMUXD_IOMUXD_GROUP_1_2_SPI3_SCK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_SPI3_SCK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_SPI3_SCK_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_SPI3_SDO_MASK    (0x4000U)
#define IOMUXD_IOMUXD_GROUP_1_2_SPI3_SDO_SHIFT   (14U)
#define IOMUXD_IOMUXD_GROUP_1_2_SPI3_SDO(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_SPI3_SDO_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_SPI3_SDO_MASK)
#define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_15_31_MASK (0xFFFF8000U)
#define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_15_31_SHIFT (15U)
#define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_15_31_MASK)
/*! @} */

/*! @name SPI3_SDI - SPI3_SDI */
/*! @{ */
#define IOMUXD_SPI3_SDI_PDRV_MASK                (0x1U)
#define IOMUXD_SPI3_SDI_PDRV_SHIFT               (0U)
#define IOMUXD_SPI3_SDI_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_PDRV_SHIFT)) & IOMUXD_SPI3_SDI_PDRV_MASK)
#define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_SHIFT)) & IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_MASK)
#define IOMUXD_SPI3_SDI_PULL_MASK                (0x60U)
#define IOMUXD_SPI3_SDI_PULL_SHIFT               (5U)
#define IOMUXD_SPI3_SDI_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_PULL_SHIFT)) & IOMUXD_SPI3_SDI_PULL_MASK)
#define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_SHIFT)) & IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_MASK)
#define IOMUXD_SPI3_SDI_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI3_SDI_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI3_SDI_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_SDI_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI3_SDI_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI3_SDI_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI3_SDI_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_SDI_WAKEUP_MASK_MASK)
#define IOMUXD_SPI3_SDI_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI3_SDI_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI3_SDI_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_lp_config_SHIFT)) & IOMUXD_SPI3_SDI_lp_config_MASK)
#define IOMUXD_SPI3_SDI_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI3_SDI_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI3_SDI_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_sw_config_SHIFT)) & IOMUXD_SPI3_SDI_sw_config_MASK)
#define IOMUXD_SPI3_SDI_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI3_SDI_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI3.SDI
 *  0b001..DMA.FTM.CH1
 *  0b011..LSIO.GPIO2.IO19
 */
#define IOMUXD_SPI3_SDI_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_mux_mode_SHIFT)) & IOMUXD_SPI3_SDI_mux_mode_MASK)
#define IOMUXD_SPI3_SDI_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI3_SDI_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI3_SDI_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_SDI_update_pad_ctl_MASK)
#define IOMUXD_SPI3_SDI_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI3_SDI_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI3_SDI_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_update_mux_mode_SHIFT)) & IOMUXD_SPI3_SDI_update_mux_mode_MASK)
/*! @} */

/*! @name SPI3_CS0 - SPI3_CS0 */
/*! @{ */
#define IOMUXD_SPI3_CS0_PDRV_MASK                (0x1U)
#define IOMUXD_SPI3_CS0_PDRV_SHIFT               (0U)
#define IOMUXD_SPI3_CS0_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_PDRV_SHIFT)) & IOMUXD_SPI3_CS0_PDRV_MASK)
#define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_SHIFT)) & IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_MASK)
#define IOMUXD_SPI3_CS0_PULL_MASK                (0x60U)
#define IOMUXD_SPI3_CS0_PULL_SHIFT               (5U)
#define IOMUXD_SPI3_CS0_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_PULL_SHIFT)) & IOMUXD_SPI3_CS0_PULL_MASK)
#define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_SHIFT)) & IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_MASK)
#define IOMUXD_SPI3_CS0_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI3_CS0_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI3_CS0_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_CS0_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI3_CS0_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI3_CS0_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI3_CS0_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_CS0_WAKEUP_MASK_MASK)
#define IOMUXD_SPI3_CS0_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI3_CS0_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI3_CS0_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_lp_config_SHIFT)) & IOMUXD_SPI3_CS0_lp_config_MASK)
#define IOMUXD_SPI3_CS0_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI3_CS0_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI3_CS0_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_sw_config_SHIFT)) & IOMUXD_SPI3_CS0_sw_config_MASK)
#define IOMUXD_SPI3_CS0_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI3_CS0_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI3.CS0
 *  0b001..DMA.FTM.CH2
 *  0b011..LSIO.GPIO2.IO20
 */
#define IOMUXD_SPI3_CS0_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_mux_mode_SHIFT)) & IOMUXD_SPI3_CS0_mux_mode_MASK)
#define IOMUXD_SPI3_CS0_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI3_CS0_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI3_CS0_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_CS0_update_pad_ctl_MASK)
#define IOMUXD_SPI3_CS0_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI3_CS0_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI3_CS0_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_update_mux_mode_SHIFT)) & IOMUXD_SPI3_CS0_update_mux_mode_MASK)
/*! @} */

/*! @name SPI3_CS1 - SPI3_CS1 */
/*! @{ */
#define IOMUXD_SPI3_CS1_PDRV_MASK                (0x1U)
#define IOMUXD_SPI3_CS1_PDRV_SHIFT               (0U)
#define IOMUXD_SPI3_CS1_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_PDRV_SHIFT)) & IOMUXD_SPI3_CS1_PDRV_MASK)
#define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_SHIFT)) & IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_MASK)
#define IOMUXD_SPI3_CS1_PULL_MASK                (0x60U)
#define IOMUXD_SPI3_CS1_PULL_SHIFT               (5U)
#define IOMUXD_SPI3_CS1_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_PULL_SHIFT)) & IOMUXD_SPI3_CS1_PULL_MASK)
#define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_SHIFT)) & IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_MASK)
#define IOMUXD_SPI3_CS1_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI3_CS1_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI3_CS1_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_CS1_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI3_CS1_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI3_CS1_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI3_CS1_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_CS1_WAKEUP_MASK_MASK)
#define IOMUXD_SPI3_CS1_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI3_CS1_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI3_CS1_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_lp_config_SHIFT)) & IOMUXD_SPI3_CS1_lp_config_MASK)
#define IOMUXD_SPI3_CS1_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI3_CS1_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI3_CS1_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_sw_config_SHIFT)) & IOMUXD_SPI3_CS1_sw_config_MASK)
#define IOMUXD_SPI3_CS1_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI3_CS1_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI3.CS1
 *  0b011..LSIO.GPIO2.IO21
 */
#define IOMUXD_SPI3_CS1_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_mux_mode_SHIFT)) & IOMUXD_SPI3_CS1_mux_mode_MASK)
#define IOMUXD_SPI3_CS1_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI3_CS1_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI3_CS1_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_CS1_update_pad_ctl_MASK)
#define IOMUXD_SPI3_CS1_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI3_CS1_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI3_CS1_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_update_mux_mode_SHIFT)) & IOMUXD_SPI3_CS1_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI0_FSR - ESAI0_FSR */
/*! @{ */
#define IOMUXD_ESAI0_FSR_PDRV_MASK               (0x1U)
#define IOMUXD_ESAI0_FSR_PDRV_SHIFT              (0U)
#define IOMUXD_ESAI0_FSR_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_PDRV_SHIFT)) & IOMUXD_ESAI0_FSR_PDRV_MASK)
#define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_MASK)
#define IOMUXD_ESAI0_FSR_PULL_MASK               (0x60U)
#define IOMUXD_ESAI0_FSR_PULL_SHIFT              (5U)
#define IOMUXD_ESAI0_FSR_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_PULL_SHIFT)) & IOMUXD_ESAI0_FSR_PULL_MASK)
#define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_MASK)
#define IOMUXD_ESAI0_FSR_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_ESAI0_FSR_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI0_FSR_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_FSR_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI0_FSR_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_ESAI0_FSR_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_ESAI0_FSR_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_FSR_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI0_FSR_lp_config_MASK          (0x1800000U)
#define IOMUXD_ESAI0_FSR_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI0_FSR_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_lp_config_SHIFT)) & IOMUXD_ESAI0_FSR_lp_config_MASK)
#define IOMUXD_ESAI0_FSR_sw_config_MASK          (0x6000000U)
#define IOMUXD_ESAI0_FSR_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI0_FSR_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_sw_config_SHIFT)) & IOMUXD_ESAI0_FSR_sw_config_MASK)
#define IOMUXD_ESAI0_FSR_mux_mode_MASK           (0x38000000U)
#define IOMUXD_ESAI0_FSR_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI0.FSR
 *  0b011..LSIO.GPIO2.IO22
 */
#define IOMUXD_ESAI0_FSR_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_mux_mode_SHIFT)) & IOMUXD_ESAI0_FSR_mux_mode_MASK)
#define IOMUXD_ESAI0_FSR_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_ESAI0_FSR_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_ESAI0_FSR_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_FSR_update_pad_ctl_MASK)
#define IOMUXD_ESAI0_FSR_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_ESAI0_FSR_update_mux_mode_SHIFT   (31U)
#define IOMUXD_ESAI0_FSR_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_FSR_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI0_FST - ESAI0_FST */
/*! @{ */
#define IOMUXD_ESAI0_FST_PDRV_MASK               (0x1U)
#define IOMUXD_ESAI0_FST_PDRV_SHIFT              (0U)
#define IOMUXD_ESAI0_FST_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_PDRV_SHIFT)) & IOMUXD_ESAI0_FST_PDRV_MASK)
#define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_MASK)
#define IOMUXD_ESAI0_FST_PULL_MASK               (0x60U)
#define IOMUXD_ESAI0_FST_PULL_SHIFT              (5U)
#define IOMUXD_ESAI0_FST_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_PULL_SHIFT)) & IOMUXD_ESAI0_FST_PULL_MASK)
#define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_MASK)
#define IOMUXD_ESAI0_FST_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_ESAI0_FST_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI0_FST_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_FST_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI0_FST_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_ESAI0_FST_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_ESAI0_FST_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_FST_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI0_FST_lp_config_MASK          (0x1800000U)
#define IOMUXD_ESAI0_FST_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI0_FST_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_lp_config_SHIFT)) & IOMUXD_ESAI0_FST_lp_config_MASK)
#define IOMUXD_ESAI0_FST_sw_config_MASK          (0x6000000U)
#define IOMUXD_ESAI0_FST_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI0_FST_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_sw_config_SHIFT)) & IOMUXD_ESAI0_FST_sw_config_MASK)
#define IOMUXD_ESAI0_FST_mux_mode_MASK           (0x38000000U)
#define IOMUXD_ESAI0_FST_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI0.FST
 *  0b011..LSIO.GPIO2.IO23
 */
#define IOMUXD_ESAI0_FST_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_mux_mode_SHIFT)) & IOMUXD_ESAI0_FST_mux_mode_MASK)
#define IOMUXD_ESAI0_FST_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_ESAI0_FST_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_ESAI0_FST_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_FST_update_pad_ctl_MASK)
#define IOMUXD_ESAI0_FST_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_ESAI0_FST_update_mux_mode_SHIFT   (31U)
#define IOMUXD_ESAI0_FST_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_FST_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI0_SCKR - ESAI0_SCKR */
/*! @{ */
#define IOMUXD_ESAI0_SCKR_PDRV_MASK              (0x1U)
#define IOMUXD_ESAI0_SCKR_PDRV_SHIFT             (0U)
#define IOMUXD_ESAI0_SCKR_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_PDRV_SHIFT)) & IOMUXD_ESAI0_SCKR_PDRV_MASK)
#define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_MASK)
#define IOMUXD_ESAI0_SCKR_PULL_MASK              (0x60U)
#define IOMUXD_ESAI0_SCKR_PULL_SHIFT             (5U)
#define IOMUXD_ESAI0_SCKR_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_PULL_SHIFT)) & IOMUXD_ESAI0_SCKR_PULL_MASK)
#define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_MASK)
#define IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_MASK       (0x380000U)
#define IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_SHIFT      (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI0_SCKR_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI0_SCKR_WAKEUP_MASK_MASK       (0x400000U)
#define IOMUXD_ESAI0_SCKR_WAKEUP_MASK_SHIFT      (22U)
#define IOMUXD_ESAI0_SCKR_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_SCKR_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI0_SCKR_lp_config_MASK         (0x1800000U)
#define IOMUXD_ESAI0_SCKR_lp_config_SHIFT        (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI0_SCKR_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_lp_config_SHIFT)) & IOMUXD_ESAI0_SCKR_lp_config_MASK)
#define IOMUXD_ESAI0_SCKR_sw_config_MASK         (0x6000000U)
#define IOMUXD_ESAI0_SCKR_sw_config_SHIFT        (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI0_SCKR_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_sw_config_SHIFT)) & IOMUXD_ESAI0_SCKR_sw_config_MASK)
#define IOMUXD_ESAI0_SCKR_mux_mode_MASK          (0x38000000U)
#define IOMUXD_ESAI0_SCKR_mux_mode_SHIFT         (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI0.SCKR
 *  0b011..LSIO.GPIO2.IO24
 */
#define IOMUXD_ESAI0_SCKR_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKR_mux_mode_MASK)
#define IOMUXD_ESAI0_SCKR_update_pad_ctl_MASK    (0x40000000U)
#define IOMUXD_ESAI0_SCKR_update_pad_ctl_SHIFT   (30U)
#define IOMUXD_ESAI0_SCKR_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_SCKR_update_pad_ctl_MASK)
#define IOMUXD_ESAI0_SCKR_update_mux_mode_MASK   (0x80000000U)
#define IOMUXD_ESAI0_SCKR_update_mux_mode_SHIFT  (31U)
#define IOMUXD_ESAI0_SCKR_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKR_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI0_SCKT - ESAI0_SCKT */
/*! @{ */
#define IOMUXD_ESAI0_SCKT_PDRV_MASK              (0x1U)
#define IOMUXD_ESAI0_SCKT_PDRV_SHIFT             (0U)
#define IOMUXD_ESAI0_SCKT_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_PDRV_SHIFT)) & IOMUXD_ESAI0_SCKT_PDRV_MASK)
#define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_MASK)
#define IOMUXD_ESAI0_SCKT_PULL_MASK              (0x60U)
#define IOMUXD_ESAI0_SCKT_PULL_SHIFT             (5U)
#define IOMUXD_ESAI0_SCKT_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_PULL_SHIFT)) & IOMUXD_ESAI0_SCKT_PULL_MASK)
#define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_MASK)
#define IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_MASK       (0x380000U)
#define IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_SHIFT      (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI0_SCKT_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI0_SCKT_WAKEUP_MASK_MASK       (0x400000U)
#define IOMUXD_ESAI0_SCKT_WAKEUP_MASK_SHIFT      (22U)
#define IOMUXD_ESAI0_SCKT_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_SCKT_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI0_SCKT_lp_config_MASK         (0x1800000U)
#define IOMUXD_ESAI0_SCKT_lp_config_SHIFT        (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI0_SCKT_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_lp_config_SHIFT)) & IOMUXD_ESAI0_SCKT_lp_config_MASK)
#define IOMUXD_ESAI0_SCKT_sw_config_MASK         (0x6000000U)
#define IOMUXD_ESAI0_SCKT_sw_config_SHIFT        (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI0_SCKT_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_sw_config_SHIFT)) & IOMUXD_ESAI0_SCKT_sw_config_MASK)
#define IOMUXD_ESAI0_SCKT_mux_mode_MASK          (0x38000000U)
#define IOMUXD_ESAI0_SCKT_mux_mode_SHIFT         (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI0.SCKT
 *  0b011..LSIO.GPIO2.IO25
 */
#define IOMUXD_ESAI0_SCKT_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKT_mux_mode_MASK)
#define IOMUXD_ESAI0_SCKT_update_pad_ctl_MASK    (0x40000000U)
#define IOMUXD_ESAI0_SCKT_update_pad_ctl_SHIFT   (30U)
#define IOMUXD_ESAI0_SCKT_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_SCKT_update_pad_ctl_MASK)
#define IOMUXD_ESAI0_SCKT_update_mux_mode_MASK   (0x80000000U)
#define IOMUXD_ESAI0_SCKT_update_mux_mode_SHIFT  (31U)
#define IOMUXD_ESAI0_SCKT_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKT_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI0_TX0 - ESAI0_TX0 */
/*! @{ */
#define IOMUXD_ESAI0_TX0_PDRV_MASK               (0x1U)
#define IOMUXD_ESAI0_TX0_PDRV_SHIFT              (0U)
#define IOMUXD_ESAI0_TX0_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_PDRV_SHIFT)) & IOMUXD_ESAI0_TX0_PDRV_MASK)
#define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_MASK)
#define IOMUXD_ESAI0_TX0_PULL_MASK               (0x60U)
#define IOMUXD_ESAI0_TX0_PULL_SHIFT              (5U)
#define IOMUXD_ESAI0_TX0_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_PULL_SHIFT)) & IOMUXD_ESAI0_TX0_PULL_MASK)
#define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_MASK)
#define IOMUXD_ESAI0_TX0_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_ESAI0_TX0_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI0_TX0_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX0_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI0_TX0_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_ESAI0_TX0_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_ESAI0_TX0_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX0_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI0_TX0_lp_config_MASK          (0x1800000U)
#define IOMUXD_ESAI0_TX0_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI0_TX0_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_lp_config_SHIFT)) & IOMUXD_ESAI0_TX0_lp_config_MASK)
#define IOMUXD_ESAI0_TX0_sw_config_MASK          (0x6000000U)
#define IOMUXD_ESAI0_TX0_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI0_TX0_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_sw_config_SHIFT)) & IOMUXD_ESAI0_TX0_sw_config_MASK)
#define IOMUXD_ESAI0_TX0_mux_mode_MASK           (0x38000000U)
#define IOMUXD_ESAI0_TX0_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI0.TX0
 *  0b011..LSIO.GPIO2.IO26
 */
#define IOMUXD_ESAI0_TX0_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX0_mux_mode_MASK)
#define IOMUXD_ESAI0_TX0_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_ESAI0_TX0_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_ESAI0_TX0_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX0_update_pad_ctl_MASK)
#define IOMUXD_ESAI0_TX0_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_ESAI0_TX0_update_mux_mode_SHIFT   (31U)
#define IOMUXD_ESAI0_TX0_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX0_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI0_TX1 - ESAI0_TX1 */
/*! @{ */
#define IOMUXD_ESAI0_TX1_PDRV_MASK               (0x1U)
#define IOMUXD_ESAI0_TX1_PDRV_SHIFT              (0U)
#define IOMUXD_ESAI0_TX1_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_PDRV_SHIFT)) & IOMUXD_ESAI0_TX1_PDRV_MASK)
#define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_MASK)
#define IOMUXD_ESAI0_TX1_PULL_MASK               (0x60U)
#define IOMUXD_ESAI0_TX1_PULL_SHIFT              (5U)
#define IOMUXD_ESAI0_TX1_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_PULL_SHIFT)) & IOMUXD_ESAI0_TX1_PULL_MASK)
#define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_MASK)
#define IOMUXD_ESAI0_TX1_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_ESAI0_TX1_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI0_TX1_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX1_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI0_TX1_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_ESAI0_TX1_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_ESAI0_TX1_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX1_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI0_TX1_lp_config_MASK          (0x1800000U)
#define IOMUXD_ESAI0_TX1_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI0_TX1_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_lp_config_SHIFT)) & IOMUXD_ESAI0_TX1_lp_config_MASK)
#define IOMUXD_ESAI0_TX1_sw_config_MASK          (0x6000000U)
#define IOMUXD_ESAI0_TX1_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI0_TX1_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_sw_config_SHIFT)) & IOMUXD_ESAI0_TX1_sw_config_MASK)
#define IOMUXD_ESAI0_TX1_mux_mode_MASK           (0x38000000U)
#define IOMUXD_ESAI0_TX1_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI0.TX1
 *  0b011..LSIO.GPIO2.IO27
 */
#define IOMUXD_ESAI0_TX1_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX1_mux_mode_MASK)
#define IOMUXD_ESAI0_TX1_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_ESAI0_TX1_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_ESAI0_TX1_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX1_update_pad_ctl_MASK)
#define IOMUXD_ESAI0_TX1_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_ESAI0_TX1_update_mux_mode_SHIFT   (31U)
#define IOMUXD_ESAI0_TX1_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX1_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI0_TX2_RX3 - ESAI0_TX2_RX3 */
/*! @{ */
#define IOMUXD_ESAI0_TX2_RX3_PDRV_MASK           (0x1U)
#define IOMUXD_ESAI0_TX2_RX3_PDRV_SHIFT          (0U)
#define IOMUXD_ESAI0_TX2_RX3_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_PDRV_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_PDRV_MASK)
#define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_MASK)
#define IOMUXD_ESAI0_TX2_RX3_PULL_MASK           (0x60U)
#define IOMUXD_ESAI0_TX2_RX3_PULL_SHIFT          (5U)
#define IOMUXD_ESAI0_TX2_RX3_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_PULL_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_PULL_MASK)
#define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_MASK)
#define IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_MASK    (0x380000U)
#define IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_SHIFT   (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_MASK    (0x400000U)
#define IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_SHIFT   (22U)
#define IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI0_TX2_RX3_lp_config_MASK      (0x1800000U)
#define IOMUXD_ESAI0_TX2_RX3_lp_config_SHIFT     (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI0_TX2_RX3_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_lp_config_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_lp_config_MASK)
#define IOMUXD_ESAI0_TX2_RX3_sw_config_MASK      (0x6000000U)
#define IOMUXD_ESAI0_TX2_RX3_sw_config_SHIFT     (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI0_TX2_RX3_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_sw_config_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_sw_config_MASK)
#define IOMUXD_ESAI0_TX2_RX3_mux_mode_MASK       (0x38000000U)
#define IOMUXD_ESAI0_TX2_RX3_mux_mode_SHIFT      (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI0.TX2_RX3
 *  0b011..LSIO.GPIO2.IO28
 */
#define IOMUXD_ESAI0_TX2_RX3_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_mux_mode_MASK)
#define IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ESAI0_TX2_RX3_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_MASK)
#define IOMUXD_ESAI0_TX2_RX3_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ESAI0_TX2_RX3_update_mux_mode_SHIFT (31U)
#define IOMUXD_ESAI0_TX2_RX3_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI0_TX3_RX2 - ESAI0_TX3_RX2 */
/*! @{ */
#define IOMUXD_ESAI0_TX3_RX2_PDRV_MASK           (0x1U)
#define IOMUXD_ESAI0_TX3_RX2_PDRV_SHIFT          (0U)
#define IOMUXD_ESAI0_TX3_RX2_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_PDRV_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_PDRV_MASK)
#define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_MASK)
#define IOMUXD_ESAI0_TX3_RX2_PULL_MASK           (0x60U)
#define IOMUXD_ESAI0_TX3_RX2_PULL_SHIFT          (5U)
#define IOMUXD_ESAI0_TX3_RX2_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_PULL_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_PULL_MASK)
#define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_MASK)
#define IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_MASK    (0x380000U)
#define IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_SHIFT   (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_MASK    (0x400000U)
#define IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_SHIFT   (22U)
#define IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI0_TX3_RX2_lp_config_MASK      (0x1800000U)
#define IOMUXD_ESAI0_TX3_RX2_lp_config_SHIFT     (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI0_TX3_RX2_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_lp_config_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_lp_config_MASK)
#define IOMUXD_ESAI0_TX3_RX2_sw_config_MASK      (0x6000000U)
#define IOMUXD_ESAI0_TX3_RX2_sw_config_SHIFT     (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI0_TX3_RX2_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_sw_config_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_sw_config_MASK)
#define IOMUXD_ESAI0_TX3_RX2_mux_mode_MASK       (0x38000000U)
#define IOMUXD_ESAI0_TX3_RX2_mux_mode_SHIFT      (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI0.TX3_RX2
 *  0b011..LSIO.GPIO2.IO29
 */
#define IOMUXD_ESAI0_TX3_RX2_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_mux_mode_MASK)
#define IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ESAI0_TX3_RX2_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_MASK)
#define IOMUXD_ESAI0_TX3_RX2_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ESAI0_TX3_RX2_update_mux_mode_SHIFT (31U)
#define IOMUXD_ESAI0_TX3_RX2_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI0_TX4_RX1 - ESAI0_TX4_RX1 */
/*! @{ */
#define IOMUXD_ESAI0_TX4_RX1_PDRV_MASK           (0x1U)
#define IOMUXD_ESAI0_TX4_RX1_PDRV_SHIFT          (0U)
#define IOMUXD_ESAI0_TX4_RX1_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_PDRV_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_PDRV_MASK)
#define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_MASK)
#define IOMUXD_ESAI0_TX4_RX1_PULL_MASK           (0x60U)
#define IOMUXD_ESAI0_TX4_RX1_PULL_SHIFT          (5U)
#define IOMUXD_ESAI0_TX4_RX1_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_PULL_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_PULL_MASK)
#define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_MASK)
#define IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_MASK    (0x380000U)
#define IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_SHIFT   (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_MASK    (0x400000U)
#define IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_SHIFT   (22U)
#define IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI0_TX4_RX1_lp_config_MASK      (0x1800000U)
#define IOMUXD_ESAI0_TX4_RX1_lp_config_SHIFT     (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI0_TX4_RX1_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_lp_config_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_lp_config_MASK)
#define IOMUXD_ESAI0_TX4_RX1_sw_config_MASK      (0x6000000U)
#define IOMUXD_ESAI0_TX4_RX1_sw_config_SHIFT     (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI0_TX4_RX1_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_sw_config_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_sw_config_MASK)
#define IOMUXD_ESAI0_TX4_RX1_mux_mode_MASK       (0x38000000U)
#define IOMUXD_ESAI0_TX4_RX1_mux_mode_SHIFT      (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI0.TX4_RX1
 *  0b011..LSIO.GPIO2.IO30
 */
#define IOMUXD_ESAI0_TX4_RX1_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_mux_mode_MASK)
#define IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ESAI0_TX4_RX1_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_MASK)
#define IOMUXD_ESAI0_TX4_RX1_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ESAI0_TX4_RX1_update_mux_mode_SHIFT (31U)
#define IOMUXD_ESAI0_TX4_RX1_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_update_mux_mode_MASK)
/*! @} */

/*! @name ESAI0_TX5_RX0 - ESAI0_TX5_RX0 */
/*! @{ */
#define IOMUXD_ESAI0_TX5_RX0_PDRV_MASK           (0x1U)
#define IOMUXD_ESAI0_TX5_RX0_PDRV_SHIFT          (0U)
#define IOMUXD_ESAI0_TX5_RX0_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_PDRV_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_PDRV_MASK)
#define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_SHIFT (1U)
#define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_MASK)
#define IOMUXD_ESAI0_TX5_RX0_PULL_MASK           (0x60U)
#define IOMUXD_ESAI0_TX5_RX0_PULL_SHIFT          (5U)
#define IOMUXD_ESAI0_TX5_RX0_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_PULL_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_PULL_MASK)
#define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_SHIFT (7U)
#define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_MASK)
#define IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_MASK    (0x380000U)
#define IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_SHIFT   (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_MASK)
#define IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_MASK    (0x400000U)
#define IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_SHIFT   (22U)
#define IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_MASK)
#define IOMUXD_ESAI0_TX5_RX0_lp_config_MASK      (0x1800000U)
#define IOMUXD_ESAI0_TX5_RX0_lp_config_SHIFT     (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ESAI0_TX5_RX0_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_lp_config_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_lp_config_MASK)
#define IOMUXD_ESAI0_TX5_RX0_sw_config_MASK      (0x6000000U)
#define IOMUXD_ESAI0_TX5_RX0_sw_config_SHIFT     (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ESAI0_TX5_RX0_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_sw_config_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_sw_config_MASK)
#define IOMUXD_ESAI0_TX5_RX0_mux_mode_MASK       (0x38000000U)
#define IOMUXD_ESAI0_TX5_RX0_mux_mode_SHIFT      (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ESAI0.TX5_RX0
 *  0b011..LSIO.GPIO2.IO31
 */
#define IOMUXD_ESAI0_TX5_RX0_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_mux_mode_MASK)
#define IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ESAI0_TX5_RX0_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_MASK)
#define IOMUXD_ESAI0_TX5_RX0_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ESAI0_TX5_RX0_update_mux_mode_SHIFT (31U)
#define IOMUXD_ESAI0_TX5_RX0_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_update_mux_mode_MASK)
/*! @} */

/*! @name MCLK_IN0 - MCLK_IN0 */
/*! @{ */
#define IOMUXD_MCLK_IN0_PDRV_MASK                (0x1U)
#define IOMUXD_MCLK_IN0_PDRV_SHIFT               (0U)
#define IOMUXD_MCLK_IN0_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_PDRV_SHIFT)) & IOMUXD_MCLK_IN0_PDRV_MASK)
#define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_SHIFT (1U)
#define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_SHIFT)) & IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_MASK)
#define IOMUXD_MCLK_IN0_PULL_MASK                (0x60U)
#define IOMUXD_MCLK_IN0_PULL_SHIFT               (5U)
#define IOMUXD_MCLK_IN0_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_PULL_SHIFT)) & IOMUXD_MCLK_IN0_PULL_MASK)
#define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_SHIFT (7U)
#define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_SHIFT)) & IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_MASK)
#define IOMUXD_MCLK_IN0_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_MCLK_IN0_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MCLK_IN0_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_WAKEUP_CTRL_SHIFT)) & IOMUXD_MCLK_IN0_WAKEUP_CTRL_MASK)
#define IOMUXD_MCLK_IN0_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_MCLK_IN0_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_MCLK_IN0_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_WAKEUP_MASK_SHIFT)) & IOMUXD_MCLK_IN0_WAKEUP_MASK_MASK)
#define IOMUXD_MCLK_IN0_lp_config_MASK           (0x1800000U)
#define IOMUXD_MCLK_IN0_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MCLK_IN0_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_lp_config_SHIFT)) & IOMUXD_MCLK_IN0_lp_config_MASK)
#define IOMUXD_MCLK_IN0_sw_config_MASK           (0x6000000U)
#define IOMUXD_MCLK_IN0_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MCLK_IN0_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_sw_config_SHIFT)) & IOMUXD_MCLK_IN0_sw_config_MASK)
#define IOMUXD_MCLK_IN0_mux_mode_MASK            (0x38000000U)
#define IOMUXD_MCLK_IN0_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ACM.MCLK_IN0
 *  0b001..AUD.ESAI0.RX_HF_CLK
 *  0b010..AUD.ESAI1.RX_HF_CLK
 *  0b011..LSIO.GPIO3.IO00
 */
#define IOMUXD_MCLK_IN0_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_mux_mode_SHIFT)) & IOMUXD_MCLK_IN0_mux_mode_MASK)
#define IOMUXD_MCLK_IN0_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_MCLK_IN0_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_MCLK_IN0_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_update_pad_ctl_SHIFT)) & IOMUXD_MCLK_IN0_update_pad_ctl_MASK)
#define IOMUXD_MCLK_IN0_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_MCLK_IN0_update_mux_mode_SHIFT    (31U)
#define IOMUXD_MCLK_IN0_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_update_mux_mode_SHIFT)) & IOMUXD_MCLK_IN0_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_1_3 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_1_3_SPI3_SDI_MASK    (0x1U)
#define IOMUXD_IOMUXD_GROUP_1_3_SPI3_SDI_SHIFT   (0U)
#define IOMUXD_IOMUXD_GROUP_1_3_SPI3_SDI(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_SPI3_SDI_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_SPI3_SDI_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_SPI3_CS0_MASK    (0x2U)
#define IOMUXD_IOMUXD_GROUP_1_3_SPI3_CS0_SHIFT   (1U)
#define IOMUXD_IOMUXD_GROUP_1_3_SPI3_CS0(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_SPI3_CS0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_SPI3_CS0_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_SPI3_CS1_MASK    (0x4U)
#define IOMUXD_IOMUXD_GROUP_1_3_SPI3_CS1_SHIFT   (2U)
#define IOMUXD_IOMUXD_GROUP_1_3_SPI3_CS1(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_SPI3_CS1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_SPI3_CS1_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_3_3_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_3_3_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_3_3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_3_3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_3_3_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_MASK   (0x10U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_SHIFT  (4U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_MASK   (0x20U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_SHIFT  (5U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_MASK  (0x40U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_MASK  (0x80U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_MASK   (0x100U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_SHIFT  (8U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_MASK   (0x200U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_SHIFT  (9U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_MASK (0x400U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_SHIFT (10U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_MASK (0x800U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_SHIFT (11U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_MASK (0x1000U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_SHIFT (12U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_MASK (0x2000U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_SHIFT (13U)
#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_MCLK_IN0_MASK    (0x4000U)
#define IOMUXD_IOMUXD_GROUP_1_3_MCLK_IN0_SHIFT   (14U)
#define IOMUXD_IOMUXD_GROUP_1_3_MCLK_IN0(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_MCLK_IN0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_MCLK_IN0_MASK)
#define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_MASK (0xFFFF8000U)
#define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_SHIFT (15U)
#define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_MASK)
/*! @} */

/*! @name MCLK_OUT0 - MCLK_OUT0 */
/*! @{ */
#define IOMUXD_MCLK_OUT0_PDRV_MASK               (0x1U)
#define IOMUXD_MCLK_OUT0_PDRV_SHIFT              (0U)
#define IOMUXD_MCLK_OUT0_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_PDRV_SHIFT)) & IOMUXD_MCLK_OUT0_PDRV_MASK)
#define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_SHIFT (1U)
#define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_SHIFT)) & IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_MASK)
#define IOMUXD_MCLK_OUT0_PULL_MASK               (0x60U)
#define IOMUXD_MCLK_OUT0_PULL_SHIFT              (5U)
#define IOMUXD_MCLK_OUT0_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_PULL_SHIFT)) & IOMUXD_MCLK_OUT0_PULL_MASK)
#define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_SHIFT (7U)
#define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_SHIFT)) & IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_MASK)
#define IOMUXD_MCLK_OUT0_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_MCLK_OUT0_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MCLK_OUT0_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_WAKEUP_CTRL_SHIFT)) & IOMUXD_MCLK_OUT0_WAKEUP_CTRL_MASK)
#define IOMUXD_MCLK_OUT0_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_MCLK_OUT0_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_MCLK_OUT0_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_WAKEUP_MASK_SHIFT)) & IOMUXD_MCLK_OUT0_WAKEUP_MASK_MASK)
#define IOMUXD_MCLK_OUT0_lp_config_MASK          (0x1800000U)
#define IOMUXD_MCLK_OUT0_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MCLK_OUT0_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_lp_config_SHIFT)) & IOMUXD_MCLK_OUT0_lp_config_MASK)
#define IOMUXD_MCLK_OUT0_sw_config_MASK          (0x6000000U)
#define IOMUXD_MCLK_OUT0_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MCLK_OUT0_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_sw_config_SHIFT)) & IOMUXD_MCLK_OUT0_sw_config_MASK)
#define IOMUXD_MCLK_OUT0_mux_mode_MASK           (0x38000000U)
#define IOMUXD_MCLK_OUT0_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.ACM.MCLK_OUT0
 *  0b001..AUD.ESAI0.TX_HF_CLK
 *  0b010..AUD.ESAI1.TX_HF_CLK
 *  0b011..LSIO.GPIO3.IO01
 */
#define IOMUXD_MCLK_OUT0_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_mux_mode_SHIFT)) & IOMUXD_MCLK_OUT0_mux_mode_MASK)
#define IOMUXD_MCLK_OUT0_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_MCLK_OUT0_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_MCLK_OUT0_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_update_pad_ctl_SHIFT)) & IOMUXD_MCLK_OUT0_update_pad_ctl_MASK)
#define IOMUXD_MCLK_OUT0_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_MCLK_OUT0_update_mux_mode_SHIFT   (31U)
#define IOMUXD_MCLK_OUT0_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_update_mux_mode_SHIFT)) & IOMUXD_MCLK_OUT0_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC_update_mux_mode_MASK)
/*! @} */

/*! @name SPI0_SCK - SPI0_SCK */
/*! @{ */
#define IOMUXD_SPI0_SCK_PDRV_MASK                (0x1U)
#define IOMUXD_SPI0_SCK_PDRV_SHIFT               (0U)
#define IOMUXD_SPI0_SCK_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_PDRV_SHIFT)) & IOMUXD_SPI0_SCK_PDRV_MASK)
#define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_SHIFT)) & IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_MASK)
#define IOMUXD_SPI0_SCK_PULL_MASK                (0x60U)
#define IOMUXD_SPI0_SCK_PULL_SHIFT               (5U)
#define IOMUXD_SPI0_SCK_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_PULL_SHIFT)) & IOMUXD_SPI0_SCK_PULL_MASK)
#define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_SHIFT)) & IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_MASK)
#define IOMUXD_SPI0_SCK_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI0_SCK_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI0_SCK_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_SCK_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI0_SCK_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI0_SCK_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI0_SCK_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_SCK_WAKEUP_MASK_MASK)
#define IOMUXD_SPI0_SCK_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI0_SCK_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI0_SCK_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_lp_config_SHIFT)) & IOMUXD_SPI0_SCK_lp_config_MASK)
#define IOMUXD_SPI0_SCK_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI0_SCK_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI0_SCK_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_sw_config_SHIFT)) & IOMUXD_SPI0_SCK_sw_config_MASK)
#define IOMUXD_SPI0_SCK_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI0_SCK_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI0.SCK
 *  0b001..AUD.SAI0.RXC
 *  0b011..LSIO.GPIO3.IO02
 */
#define IOMUXD_SPI0_SCK_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_mux_mode_SHIFT)) & IOMUXD_SPI0_SCK_mux_mode_MASK)
#define IOMUXD_SPI0_SCK_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI0_SCK_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI0_SCK_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_SCK_update_pad_ctl_MASK)
#define IOMUXD_SPI0_SCK_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI0_SCK_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI0_SCK_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_update_mux_mode_SHIFT)) & IOMUXD_SPI0_SCK_update_mux_mode_MASK)
/*! @} */

/*! @name SPI0_SDO - SPI0_SDO */
/*! @{ */
#define IOMUXD_SPI0_SDO_PDRV_MASK                (0x1U)
#define IOMUXD_SPI0_SDO_PDRV_SHIFT               (0U)
#define IOMUXD_SPI0_SDO_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_PDRV_SHIFT)) & IOMUXD_SPI0_SDO_PDRV_MASK)
#define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_SHIFT)) & IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_MASK)
#define IOMUXD_SPI0_SDO_PULL_MASK                (0x60U)
#define IOMUXD_SPI0_SDO_PULL_SHIFT               (5U)
#define IOMUXD_SPI0_SDO_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_PULL_SHIFT)) & IOMUXD_SPI0_SDO_PULL_MASK)
#define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_SHIFT)) & IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_MASK)
#define IOMUXD_SPI0_SDO_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI0_SDO_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI0_SDO_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_SDO_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI0_SDO_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI0_SDO_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI0_SDO_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_SDO_WAKEUP_MASK_MASK)
#define IOMUXD_SPI0_SDO_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI0_SDO_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI0_SDO_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_lp_config_SHIFT)) & IOMUXD_SPI0_SDO_lp_config_MASK)
#define IOMUXD_SPI0_SDO_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI0_SDO_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI0_SDO_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_sw_config_SHIFT)) & IOMUXD_SPI0_SDO_sw_config_MASK)
#define IOMUXD_SPI0_SDO_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI0_SDO_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI0.SDO
 *  0b001..AUD.SAI0.TXD
 *  0b011..LSIO.GPIO3.IO03
 */
#define IOMUXD_SPI0_SDO_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_mux_mode_SHIFT)) & IOMUXD_SPI0_SDO_mux_mode_MASK)
#define IOMUXD_SPI0_SDO_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI0_SDO_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI0_SDO_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_SDO_update_pad_ctl_MASK)
#define IOMUXD_SPI0_SDO_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI0_SDO_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI0_SDO_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_update_mux_mode_SHIFT)) & IOMUXD_SPI0_SDO_update_mux_mode_MASK)
/*! @} */

/*! @name SPI0_SDI - SPI0_SDI */
/*! @{ */
#define IOMUXD_SPI0_SDI_PDRV_MASK                (0x1U)
#define IOMUXD_SPI0_SDI_PDRV_SHIFT               (0U)
#define IOMUXD_SPI0_SDI_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_PDRV_SHIFT)) & IOMUXD_SPI0_SDI_PDRV_MASK)
#define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_SHIFT)) & IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_MASK)
#define IOMUXD_SPI0_SDI_PULL_MASK                (0x60U)
#define IOMUXD_SPI0_SDI_PULL_SHIFT               (5U)
#define IOMUXD_SPI0_SDI_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_PULL_SHIFT)) & IOMUXD_SPI0_SDI_PULL_MASK)
#define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_SHIFT)) & IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_MASK)
#define IOMUXD_SPI0_SDI_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI0_SDI_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI0_SDI_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_SDI_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI0_SDI_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI0_SDI_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI0_SDI_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_SDI_WAKEUP_MASK_MASK)
#define IOMUXD_SPI0_SDI_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI0_SDI_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI0_SDI_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_lp_config_SHIFT)) & IOMUXD_SPI0_SDI_lp_config_MASK)
#define IOMUXD_SPI0_SDI_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI0_SDI_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI0_SDI_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_sw_config_SHIFT)) & IOMUXD_SPI0_SDI_sw_config_MASK)
#define IOMUXD_SPI0_SDI_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI0_SDI_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI0.SDI
 *  0b001..AUD.SAI0.RXD
 *  0b011..LSIO.GPIO3.IO04
 */
#define IOMUXD_SPI0_SDI_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_mux_mode_SHIFT)) & IOMUXD_SPI0_SDI_mux_mode_MASK)
#define IOMUXD_SPI0_SDI_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI0_SDI_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI0_SDI_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_SDI_update_pad_ctl_MASK)
#define IOMUXD_SPI0_SDI_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI0_SDI_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI0_SDI_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_update_mux_mode_SHIFT)) & IOMUXD_SPI0_SDI_update_mux_mode_MASK)
/*! @} */

/*! @name SPI0_CS0 - SPI0_CS0 */
/*! @{ */
#define IOMUXD_SPI0_CS0_PDRV_MASK                (0x1U)
#define IOMUXD_SPI0_CS0_PDRV_SHIFT               (0U)
#define IOMUXD_SPI0_CS0_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_PDRV_SHIFT)) & IOMUXD_SPI0_CS0_PDRV_MASK)
#define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_SHIFT)) & IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_MASK)
#define IOMUXD_SPI0_CS0_PULL_MASK                (0x60U)
#define IOMUXD_SPI0_CS0_PULL_SHIFT               (5U)
#define IOMUXD_SPI0_CS0_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_PULL_SHIFT)) & IOMUXD_SPI0_CS0_PULL_MASK)
#define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_SHIFT)) & IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_MASK)
#define IOMUXD_SPI0_CS0_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI0_CS0_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI0_CS0_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_CS0_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI0_CS0_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI0_CS0_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI0_CS0_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_CS0_WAKEUP_MASK_MASK)
#define IOMUXD_SPI0_CS0_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI0_CS0_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI0_CS0_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_lp_config_SHIFT)) & IOMUXD_SPI0_CS0_lp_config_MASK)
#define IOMUXD_SPI0_CS0_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI0_CS0_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI0_CS0_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_sw_config_SHIFT)) & IOMUXD_SPI0_CS0_sw_config_MASK)
#define IOMUXD_SPI0_CS0_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI0_CS0_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI0.CS0
 *  0b001..AUD.SAI0.RXFS
 *  0b011..LSIO.GPIO3.IO05
 */
#define IOMUXD_SPI0_CS0_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_mux_mode_SHIFT)) & IOMUXD_SPI0_CS0_mux_mode_MASK)
#define IOMUXD_SPI0_CS0_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI0_CS0_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI0_CS0_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_CS0_update_pad_ctl_MASK)
#define IOMUXD_SPI0_CS0_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI0_CS0_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI0_CS0_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_update_mux_mode_SHIFT)) & IOMUXD_SPI0_CS0_update_mux_mode_MASK)
/*! @} */

/*! @name SPI0_CS1 - SPI0_CS1 */
/*! @{ */
#define IOMUXD_SPI0_CS1_PDRV_MASK                (0x1U)
#define IOMUXD_SPI0_CS1_PDRV_SHIFT               (0U)
#define IOMUXD_SPI0_CS1_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_PDRV_SHIFT)) & IOMUXD_SPI0_CS1_PDRV_MASK)
#define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_SHIFT)) & IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_MASK)
#define IOMUXD_SPI0_CS1_PULL_MASK                (0x60U)
#define IOMUXD_SPI0_CS1_PULL_SHIFT               (5U)
#define IOMUXD_SPI0_CS1_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_PULL_SHIFT)) & IOMUXD_SPI0_CS1_PULL_MASK)
#define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_SHIFT)) & IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_MASK)
#define IOMUXD_SPI0_CS1_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI0_CS1_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI0_CS1_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_CS1_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI0_CS1_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI0_CS1_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI0_CS1_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_CS1_WAKEUP_MASK_MASK)
#define IOMUXD_SPI0_CS1_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI0_CS1_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI0_CS1_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_lp_config_SHIFT)) & IOMUXD_SPI0_CS1_lp_config_MASK)
#define IOMUXD_SPI0_CS1_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI0_CS1_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI0_CS1_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_sw_config_SHIFT)) & IOMUXD_SPI0_CS1_sw_config_MASK)
#define IOMUXD_SPI0_CS1_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI0_CS1_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI0.CS1
 *  0b001..AUD.SAI0.TXC
 *  0b011..LSIO.GPIO3.IO06
 */
#define IOMUXD_SPI0_CS1_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_mux_mode_SHIFT)) & IOMUXD_SPI0_CS1_mux_mode_MASK)
#define IOMUXD_SPI0_CS1_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI0_CS1_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI0_CS1_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_CS1_update_pad_ctl_MASK)
#define IOMUXD_SPI0_CS1_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI0_CS1_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI0_CS1_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_update_mux_mode_SHIFT)) & IOMUXD_SPI0_CS1_update_mux_mode_MASK)
/*! @} */

/*! @name SPI2_SCK - SPI2_SCK */
/*! @{ */
#define IOMUXD_SPI2_SCK_PDRV_MASK                (0x1U)
#define IOMUXD_SPI2_SCK_PDRV_SHIFT               (0U)
#define IOMUXD_SPI2_SCK_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_PDRV_SHIFT)) & IOMUXD_SPI2_SCK_PDRV_MASK)
#define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_SHIFT)) & IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_MASK)
#define IOMUXD_SPI2_SCK_PULL_MASK                (0x60U)
#define IOMUXD_SPI2_SCK_PULL_SHIFT               (5U)
#define IOMUXD_SPI2_SCK_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_PULL_SHIFT)) & IOMUXD_SPI2_SCK_PULL_MASK)
#define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_SHIFT)) & IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_MASK)
#define IOMUXD_SPI2_SCK_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI2_SCK_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI2_SCK_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_SCK_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI2_SCK_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI2_SCK_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI2_SCK_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_SCK_WAKEUP_MASK_MASK)
#define IOMUXD_SPI2_SCK_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI2_SCK_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI2_SCK_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_lp_config_SHIFT)) & IOMUXD_SPI2_SCK_lp_config_MASK)
#define IOMUXD_SPI2_SCK_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI2_SCK_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI2_SCK_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_sw_config_SHIFT)) & IOMUXD_SPI2_SCK_sw_config_MASK)
#define IOMUXD_SPI2_SCK_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI2_SCK_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI2.SCK
 *  0b011..LSIO.GPIO3.IO07
 */
#define IOMUXD_SPI2_SCK_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_mux_mode_SHIFT)) & IOMUXD_SPI2_SCK_mux_mode_MASK)
#define IOMUXD_SPI2_SCK_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI2_SCK_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI2_SCK_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_SCK_update_pad_ctl_MASK)
#define IOMUXD_SPI2_SCK_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI2_SCK_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI2_SCK_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_update_mux_mode_SHIFT)) & IOMUXD_SPI2_SCK_update_mux_mode_MASK)
/*! @} */

/*! @name SPI2_SDO - SPI2_SDO */
/*! @{ */
#define IOMUXD_SPI2_SDO_PDRV_MASK                (0x1U)
#define IOMUXD_SPI2_SDO_PDRV_SHIFT               (0U)
#define IOMUXD_SPI2_SDO_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_PDRV_SHIFT)) & IOMUXD_SPI2_SDO_PDRV_MASK)
#define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_SHIFT)) & IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_MASK)
#define IOMUXD_SPI2_SDO_PULL_MASK                (0x60U)
#define IOMUXD_SPI2_SDO_PULL_SHIFT               (5U)
#define IOMUXD_SPI2_SDO_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_PULL_SHIFT)) & IOMUXD_SPI2_SDO_PULL_MASK)
#define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_SHIFT)) & IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_MASK)
#define IOMUXD_SPI2_SDO_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI2_SDO_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI2_SDO_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_SDO_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI2_SDO_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI2_SDO_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI2_SDO_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_SDO_WAKEUP_MASK_MASK)
#define IOMUXD_SPI2_SDO_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI2_SDO_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI2_SDO_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_lp_config_SHIFT)) & IOMUXD_SPI2_SDO_lp_config_MASK)
#define IOMUXD_SPI2_SDO_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI2_SDO_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI2_SDO_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_sw_config_SHIFT)) & IOMUXD_SPI2_SDO_sw_config_MASK)
#define IOMUXD_SPI2_SDO_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI2_SDO_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI2.SDO
 *  0b011..LSIO.GPIO3.IO08
 */
#define IOMUXD_SPI2_SDO_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_mux_mode_SHIFT)) & IOMUXD_SPI2_SDO_mux_mode_MASK)
#define IOMUXD_SPI2_SDO_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI2_SDO_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI2_SDO_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_SDO_update_pad_ctl_MASK)
#define IOMUXD_SPI2_SDO_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI2_SDO_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI2_SDO_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_update_mux_mode_SHIFT)) & IOMUXD_SPI2_SDO_update_mux_mode_MASK)
/*! @} */

/*! @name SPI2_SDI - SPI2_SDI */
/*! @{ */
#define IOMUXD_SPI2_SDI_PDRV_MASK                (0x1U)
#define IOMUXD_SPI2_SDI_PDRV_SHIFT               (0U)
#define IOMUXD_SPI2_SDI_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_PDRV_SHIFT)) & IOMUXD_SPI2_SDI_PDRV_MASK)
#define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_SHIFT)) & IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_MASK)
#define IOMUXD_SPI2_SDI_PULL_MASK                (0x60U)
#define IOMUXD_SPI2_SDI_PULL_SHIFT               (5U)
#define IOMUXD_SPI2_SDI_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_PULL_SHIFT)) & IOMUXD_SPI2_SDI_PULL_MASK)
#define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_SHIFT)) & IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_MASK)
#define IOMUXD_SPI2_SDI_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI2_SDI_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI2_SDI_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_SDI_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI2_SDI_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI2_SDI_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI2_SDI_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_SDI_WAKEUP_MASK_MASK)
#define IOMUXD_SPI2_SDI_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI2_SDI_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI2_SDI_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_lp_config_SHIFT)) & IOMUXD_SPI2_SDI_lp_config_MASK)
#define IOMUXD_SPI2_SDI_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI2_SDI_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI2_SDI_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_sw_config_SHIFT)) & IOMUXD_SPI2_SDI_sw_config_MASK)
#define IOMUXD_SPI2_SDI_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI2_SDI_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI2.SDI
 *  0b011..LSIO.GPIO3.IO09
 */
#define IOMUXD_SPI2_SDI_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_mux_mode_SHIFT)) & IOMUXD_SPI2_SDI_mux_mode_MASK)
#define IOMUXD_SPI2_SDI_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI2_SDI_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI2_SDI_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_SDI_update_pad_ctl_MASK)
#define IOMUXD_SPI2_SDI_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI2_SDI_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI2_SDI_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_update_mux_mode_SHIFT)) & IOMUXD_SPI2_SDI_update_mux_mode_MASK)
/*! @} */

/*! @name SPI2_CS0 - SPI2_CS0 */
/*! @{ */
#define IOMUXD_SPI2_CS0_PDRV_MASK                (0x1U)
#define IOMUXD_SPI2_CS0_PDRV_SHIFT               (0U)
#define IOMUXD_SPI2_CS0_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_PDRV_SHIFT)) & IOMUXD_SPI2_CS0_PDRV_MASK)
#define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_SHIFT)) & IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_MASK)
#define IOMUXD_SPI2_CS0_PULL_MASK                (0x60U)
#define IOMUXD_SPI2_CS0_PULL_SHIFT               (5U)
#define IOMUXD_SPI2_CS0_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_PULL_SHIFT)) & IOMUXD_SPI2_CS0_PULL_MASK)
#define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_SHIFT)) & IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_MASK)
#define IOMUXD_SPI2_CS0_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI2_CS0_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI2_CS0_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_CS0_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI2_CS0_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI2_CS0_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI2_CS0_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_CS0_WAKEUP_MASK_MASK)
#define IOMUXD_SPI2_CS0_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI2_CS0_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI2_CS0_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_lp_config_SHIFT)) & IOMUXD_SPI2_CS0_lp_config_MASK)
#define IOMUXD_SPI2_CS0_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI2_CS0_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI2_CS0_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_sw_config_SHIFT)) & IOMUXD_SPI2_CS0_sw_config_MASK)
#define IOMUXD_SPI2_CS0_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI2_CS0_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI2.CS0
 *  0b011..LSIO.GPIO3.IO10
 */
#define IOMUXD_SPI2_CS0_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_mux_mode_SHIFT)) & IOMUXD_SPI2_CS0_mux_mode_MASK)
#define IOMUXD_SPI2_CS0_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI2_CS0_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI2_CS0_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_CS0_update_pad_ctl_MASK)
#define IOMUXD_SPI2_CS0_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI2_CS0_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI2_CS0_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_update_mux_mode_SHIFT)) & IOMUXD_SPI2_CS0_update_mux_mode_MASK)
/*! @} */

/*! @name SPI2_CS1 - SPI2_CS1 */
/*! @{ */
#define IOMUXD_SPI2_CS1_PDRV_MASK                (0x1U)
#define IOMUXD_SPI2_CS1_PDRV_SHIFT               (0U)
#define IOMUXD_SPI2_CS1_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS1_PDRV_SHIFT)) & IOMUXD_SPI2_CS1_PDRV_MASK)
#define IOMUXD_SPI2_CS1_SPI2_CS1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SPI2_CS1_SPI2_CS1_reserved_1_4_SHIFT (1U)
#define IOMUXD_SPI2_CS1_SPI2_CS1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS1_SPI2_CS1_reserved_1_4_SHIFT)) & IOMUXD_SPI2_CS1_SPI2_CS1_reserved_1_4_MASK)
#define IOMUXD_SPI2_CS1_PULL_MASK                (0x60U)
#define IOMUXD_SPI2_CS1_PULL_SHIFT               (5U)
#define IOMUXD_SPI2_CS1_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS1_PULL_SHIFT)) & IOMUXD_SPI2_CS1_PULL_MASK)
#define IOMUXD_SPI2_CS1_SPI2_CS1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SPI2_CS1_SPI2_CS1_reserved_7_18_SHIFT (7U)
#define IOMUXD_SPI2_CS1_SPI2_CS1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS1_SPI2_CS1_reserved_7_18_SHIFT)) & IOMUXD_SPI2_CS1_SPI2_CS1_reserved_7_18_MASK)
#define IOMUXD_SPI2_CS1_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SPI2_CS1_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SPI2_CS1_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS1_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_CS1_WAKEUP_CTRL_MASK)
#define IOMUXD_SPI2_CS1_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SPI2_CS1_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SPI2_CS1_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS1_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_CS1_WAKEUP_MASK_MASK)
#define IOMUXD_SPI2_CS1_lp_config_MASK           (0x1800000U)
#define IOMUXD_SPI2_CS1_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SPI2_CS1_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS1_lp_config_SHIFT)) & IOMUXD_SPI2_CS1_lp_config_MASK)
#define IOMUXD_SPI2_CS1_sw_config_MASK           (0x6000000U)
#define IOMUXD_SPI2_CS1_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SPI2_CS1_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS1_sw_config_SHIFT)) & IOMUXD_SPI2_CS1_sw_config_MASK)
#define IOMUXD_SPI2_CS1_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SPI2_CS1_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.SPI2.CS1
 *  0b001..AUD.SAI0.TXFS
 *  0b011..LSIO.GPIO3.IO11
 */
#define IOMUXD_SPI2_CS1_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS1_mux_mode_SHIFT)) & IOMUXD_SPI2_CS1_mux_mode_MASK)
#define IOMUXD_SPI2_CS1_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SPI2_CS1_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SPI2_CS1_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS1_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_CS1_update_pad_ctl_MASK)
#define IOMUXD_SPI2_CS1_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SPI2_CS1_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SPI2_CS1_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS1_update_mux_mode_SHIFT)) & IOMUXD_SPI2_CS1_update_mux_mode_MASK)
/*! @} */

/*! @name SAI1_RXC - SAI1_RXC */
/*! @{ */
#define IOMUXD_SAI1_RXC_PDRV_MASK                (0x1U)
#define IOMUXD_SAI1_RXC_PDRV_SHIFT               (0U)
#define IOMUXD_SAI1_RXC_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_PDRV_SHIFT)) & IOMUXD_SAI1_RXC_PDRV_MASK)
#define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_SHIFT (1U)
#define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_SHIFT)) & IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_MASK)
#define IOMUXD_SAI1_RXC_PULL_MASK                (0x60U)
#define IOMUXD_SAI1_RXC_PULL_SHIFT               (5U)
#define IOMUXD_SAI1_RXC_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_PULL_SHIFT)) & IOMUXD_SAI1_RXC_PULL_MASK)
#define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_SHIFT (7U)
#define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_SHIFT)) & IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_MASK)
#define IOMUXD_SAI1_RXC_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SAI1_RXC_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SAI1_RXC_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_RXC_WAKEUP_CTRL_MASK)
#define IOMUXD_SAI1_RXC_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SAI1_RXC_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SAI1_RXC_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_RXC_WAKEUP_MASK_MASK)
#define IOMUXD_SAI1_RXC_lp_config_MASK           (0x1800000U)
#define IOMUXD_SAI1_RXC_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SAI1_RXC_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_lp_config_SHIFT)) & IOMUXD_SAI1_RXC_lp_config_MASK)
#define IOMUXD_SAI1_RXC_sw_config_MASK           (0x6000000U)
#define IOMUXD_SAI1_RXC_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SAI1_RXC_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_sw_config_SHIFT)) & IOMUXD_SAI1_RXC_sw_config_MASK)
#define IOMUXD_SAI1_RXC_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SAI1_RXC_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.SAI1.RXC
 *  0b001..AUD.SAI0.TXD
 *  0b011..LSIO.GPIO3.IO12
 */
#define IOMUXD_SAI1_RXC_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_mux_mode_SHIFT)) & IOMUXD_SAI1_RXC_mux_mode_MASK)
#define IOMUXD_SAI1_RXC_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SAI1_RXC_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SAI1_RXC_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_RXC_update_pad_ctl_MASK)
#define IOMUXD_SAI1_RXC_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SAI1_RXC_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SAI1_RXC_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_update_mux_mode_SHIFT)) & IOMUXD_SAI1_RXC_update_mux_mode_MASK)
/*! @} */

/*! @name SAI1_RXD - SAI1_RXD */
/*! @{ */
#define IOMUXD_SAI1_RXD_PDRV_MASK                (0x1U)
#define IOMUXD_SAI1_RXD_PDRV_SHIFT               (0U)
#define IOMUXD_SAI1_RXD_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_PDRV_SHIFT)) & IOMUXD_SAI1_RXD_PDRV_MASK)
#define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_SHIFT (1U)
#define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_SHIFT)) & IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_MASK)
#define IOMUXD_SAI1_RXD_PULL_MASK                (0x60U)
#define IOMUXD_SAI1_RXD_PULL_SHIFT               (5U)
#define IOMUXD_SAI1_RXD_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_PULL_SHIFT)) & IOMUXD_SAI1_RXD_PULL_MASK)
#define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_SHIFT (7U)
#define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_SHIFT)) & IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_MASK)
#define IOMUXD_SAI1_RXD_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SAI1_RXD_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SAI1_RXD_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_RXD_WAKEUP_CTRL_MASK)
#define IOMUXD_SAI1_RXD_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SAI1_RXD_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SAI1_RXD_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_RXD_WAKEUP_MASK_MASK)
#define IOMUXD_SAI1_RXD_lp_config_MASK           (0x1800000U)
#define IOMUXD_SAI1_RXD_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SAI1_RXD_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_lp_config_SHIFT)) & IOMUXD_SAI1_RXD_lp_config_MASK)
#define IOMUXD_SAI1_RXD_sw_config_MASK           (0x6000000U)
#define IOMUXD_SAI1_RXD_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SAI1_RXD_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_sw_config_SHIFT)) & IOMUXD_SAI1_RXD_sw_config_MASK)
#define IOMUXD_SAI1_RXD_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SAI1_RXD_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.SAI1.RXD
 *  0b001..AUD.SAI0.TXFS
 *  0b011..LSIO.GPIO3.IO13
 */
#define IOMUXD_SAI1_RXD_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_mux_mode_SHIFT)) & IOMUXD_SAI1_RXD_mux_mode_MASK)
#define IOMUXD_SAI1_RXD_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SAI1_RXD_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SAI1_RXD_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_RXD_update_pad_ctl_MASK)
#define IOMUXD_SAI1_RXD_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SAI1_RXD_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SAI1_RXD_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_update_mux_mode_SHIFT)) & IOMUXD_SAI1_RXD_update_mux_mode_MASK)
/*! @} */

/*! @name SAI1_RXFS - SAI1_RXFS */
/*! @{ */
#define IOMUXD_SAI1_RXFS_PDRV_MASK               (0x1U)
#define IOMUXD_SAI1_RXFS_PDRV_SHIFT              (0U)
#define IOMUXD_SAI1_RXFS_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_PDRV_SHIFT)) & IOMUXD_SAI1_RXFS_PDRV_MASK)
#define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_SHIFT (1U)
#define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_SHIFT)) & IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_MASK)
#define IOMUXD_SAI1_RXFS_PULL_MASK               (0x60U)
#define IOMUXD_SAI1_RXFS_PULL_SHIFT              (5U)
#define IOMUXD_SAI1_RXFS_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_PULL_SHIFT)) & IOMUXD_SAI1_RXFS_PULL_MASK)
#define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_SHIFT (7U)
#define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_SHIFT)) & IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_MASK)
#define IOMUXD_SAI1_RXFS_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_SAI1_RXFS_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SAI1_RXFS_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_RXFS_WAKEUP_CTRL_MASK)
#define IOMUXD_SAI1_RXFS_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_SAI1_RXFS_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_SAI1_RXFS_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_RXFS_WAKEUP_MASK_MASK)
#define IOMUXD_SAI1_RXFS_lp_config_MASK          (0x1800000U)
#define IOMUXD_SAI1_RXFS_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SAI1_RXFS_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_lp_config_SHIFT)) & IOMUXD_SAI1_RXFS_lp_config_MASK)
#define IOMUXD_SAI1_RXFS_sw_config_MASK          (0x6000000U)
#define IOMUXD_SAI1_RXFS_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SAI1_RXFS_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_sw_config_SHIFT)) & IOMUXD_SAI1_RXFS_sw_config_MASK)
#define IOMUXD_SAI1_RXFS_mux_mode_MASK           (0x38000000U)
#define IOMUXD_SAI1_RXFS_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.SAI1.RXFS
 *  0b001..AUD.SAI0.RXD
 *  0b011..LSIO.GPIO3.IO14
 */
#define IOMUXD_SAI1_RXFS_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_mux_mode_SHIFT)) & IOMUXD_SAI1_RXFS_mux_mode_MASK)
#define IOMUXD_SAI1_RXFS_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_SAI1_RXFS_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_SAI1_RXFS_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_RXFS_update_pad_ctl_MASK)
#define IOMUXD_SAI1_RXFS_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_SAI1_RXFS_update_mux_mode_SHIFT   (31U)
#define IOMUXD_SAI1_RXFS_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_update_mux_mode_SHIFT)) & IOMUXD_SAI1_RXFS_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_1_4 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_MASK   (0x1U)
#define IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_SHIFT  (0U)
#define IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_SCK_MASK    (0x4U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_SCK_SHIFT   (2U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_SCK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI0_SCK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI0_SCK_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_SDO_MASK    (0x8U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_SDO_SHIFT   (3U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_SDO(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI0_SDO_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI0_SDO_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_SDI_MASK    (0x10U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_SDI_SHIFT   (4U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_SDI(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI0_SDI_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI0_SDI_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_CS0_MASK    (0x20U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_CS0_SHIFT   (5U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_CS0(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI0_CS0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI0_CS0_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_CS1_MASK    (0x40U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_CS1_SHIFT   (6U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI0_CS1(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI0_CS1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI0_CS1_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_SCK_MASK    (0x80U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_SCK_SHIFT   (7U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_SCK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI2_SCK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI2_SCK_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_SDO_MASK    (0x100U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_SDO_SHIFT   (8U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_SDO(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI2_SDO_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI2_SDO_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_SDI_MASK    (0x200U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_SDI_SHIFT   (9U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_SDI(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI2_SDI_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI2_SDI_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_CS0_MASK    (0x400U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_CS0_SHIFT   (10U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_CS0(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI2_CS0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI2_CS0_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_CS1_MASK    (0x800U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_CS1_SHIFT   (11U)
#define IOMUXD_IOMUXD_GROUP_1_4_SPI2_CS1(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI2_CS1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI2_CS1_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXC_MASK    (0x1000U)
#define IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXC_SHIFT   (12U)
#define IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXC(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXC_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXD_MASK    (0x2000U)
#define IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXD_SHIFT   (13U)
#define IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXD(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXD_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXD_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXFS_MASK   (0x4000U)
#define IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXFS_SHIFT  (14U)
#define IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXFS(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXFS_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SAI1_RXFS_MASK)
#define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_15_31_MASK (0xFFFF8000U)
#define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_15_31_SHIFT (15U)
#define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_15_31_MASK)
/*! @} */

/*! @name SAI1_TXC - SAI1_TXC */
/*! @{ */
#define IOMUXD_SAI1_TXC_PDRV_MASK                (0x1U)
#define IOMUXD_SAI1_TXC_PDRV_SHIFT               (0U)
#define IOMUXD_SAI1_TXC_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXC_PDRV_SHIFT)) & IOMUXD_SAI1_TXC_PDRV_MASK)
#define IOMUXD_SAI1_TXC_SAI1_TXC_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SAI1_TXC_SAI1_TXC_reserved_1_4_SHIFT (1U)
#define IOMUXD_SAI1_TXC_SAI1_TXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXC_SAI1_TXC_reserved_1_4_SHIFT)) & IOMUXD_SAI1_TXC_SAI1_TXC_reserved_1_4_MASK)
#define IOMUXD_SAI1_TXC_PULL_MASK                (0x60U)
#define IOMUXD_SAI1_TXC_PULL_SHIFT               (5U)
#define IOMUXD_SAI1_TXC_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXC_PULL_SHIFT)) & IOMUXD_SAI1_TXC_PULL_MASK)
#define IOMUXD_SAI1_TXC_SAI1_TXC_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SAI1_TXC_SAI1_TXC_reserved_7_18_SHIFT (7U)
#define IOMUXD_SAI1_TXC_SAI1_TXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXC_SAI1_TXC_reserved_7_18_SHIFT)) & IOMUXD_SAI1_TXC_SAI1_TXC_reserved_7_18_MASK)
#define IOMUXD_SAI1_TXC_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SAI1_TXC_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SAI1_TXC_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_TXC_WAKEUP_CTRL_MASK)
#define IOMUXD_SAI1_TXC_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SAI1_TXC_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SAI1_TXC_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXC_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_TXC_WAKEUP_MASK_MASK)
#define IOMUXD_SAI1_TXC_lp_config_MASK           (0x1800000U)
#define IOMUXD_SAI1_TXC_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SAI1_TXC_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXC_lp_config_SHIFT)) & IOMUXD_SAI1_TXC_lp_config_MASK)
#define IOMUXD_SAI1_TXC_sw_config_MASK           (0x6000000U)
#define IOMUXD_SAI1_TXC_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SAI1_TXC_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXC_sw_config_SHIFT)) & IOMUXD_SAI1_TXC_sw_config_MASK)
#define IOMUXD_SAI1_TXC_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SAI1_TXC_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.SAI1.TXC
 *  0b001..AUD.SAI0.TXC
 *  0b011..LSIO.GPIO3.IO15
 */
#define IOMUXD_SAI1_TXC_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXC_mux_mode_SHIFT)) & IOMUXD_SAI1_TXC_mux_mode_MASK)
#define IOMUXD_SAI1_TXC_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SAI1_TXC_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SAI1_TXC_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXC_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_TXC_update_pad_ctl_MASK)
#define IOMUXD_SAI1_TXC_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SAI1_TXC_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SAI1_TXC_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXC_update_mux_mode_SHIFT)) & IOMUXD_SAI1_TXC_update_mux_mode_MASK)
/*! @} */

/*! @name SAI1_TXD - SAI1_TXD */
/*! @{ */
#define IOMUXD_SAI1_TXD_PDRV_MASK                (0x1U)
#define IOMUXD_SAI1_TXD_PDRV_SHIFT               (0U)
#define IOMUXD_SAI1_TXD_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXD_PDRV_SHIFT)) & IOMUXD_SAI1_TXD_PDRV_MASK)
#define IOMUXD_SAI1_TXD_SAI1_TXD_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SAI1_TXD_SAI1_TXD_reserved_1_4_SHIFT (1U)
#define IOMUXD_SAI1_TXD_SAI1_TXD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXD_SAI1_TXD_reserved_1_4_SHIFT)) & IOMUXD_SAI1_TXD_SAI1_TXD_reserved_1_4_MASK)
#define IOMUXD_SAI1_TXD_PULL_MASK                (0x60U)
#define IOMUXD_SAI1_TXD_PULL_SHIFT               (5U)
#define IOMUXD_SAI1_TXD_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXD_PULL_SHIFT)) & IOMUXD_SAI1_TXD_PULL_MASK)
#define IOMUXD_SAI1_TXD_SAI1_TXD_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SAI1_TXD_SAI1_TXD_reserved_7_18_SHIFT (7U)
#define IOMUXD_SAI1_TXD_SAI1_TXD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXD_SAI1_TXD_reserved_7_18_SHIFT)) & IOMUXD_SAI1_TXD_SAI1_TXD_reserved_7_18_MASK)
#define IOMUXD_SAI1_TXD_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_SAI1_TXD_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SAI1_TXD_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXD_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_TXD_WAKEUP_CTRL_MASK)
#define IOMUXD_SAI1_TXD_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_SAI1_TXD_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_SAI1_TXD_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXD_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_TXD_WAKEUP_MASK_MASK)
#define IOMUXD_SAI1_TXD_lp_config_MASK           (0x1800000U)
#define IOMUXD_SAI1_TXD_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SAI1_TXD_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXD_lp_config_SHIFT)) & IOMUXD_SAI1_TXD_lp_config_MASK)
#define IOMUXD_SAI1_TXD_sw_config_MASK           (0x6000000U)
#define IOMUXD_SAI1_TXD_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SAI1_TXD_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXD_sw_config_SHIFT)) & IOMUXD_SAI1_TXD_sw_config_MASK)
#define IOMUXD_SAI1_TXD_mux_mode_MASK            (0x38000000U)
#define IOMUXD_SAI1_TXD_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.SAI1.TXD
 *  0b001..AUD.SAI1.RXC
 *  0b011..LSIO.GPIO3.IO16
 */
#define IOMUXD_SAI1_TXD_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXD_mux_mode_SHIFT)) & IOMUXD_SAI1_TXD_mux_mode_MASK)
#define IOMUXD_SAI1_TXD_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_SAI1_TXD_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_SAI1_TXD_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXD_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_TXD_update_pad_ctl_MASK)
#define IOMUXD_SAI1_TXD_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_SAI1_TXD_update_mux_mode_SHIFT    (31U)
#define IOMUXD_SAI1_TXD_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXD_update_mux_mode_SHIFT)) & IOMUXD_SAI1_TXD_update_mux_mode_MASK)
/*! @} */

/*! @name SAI1_TXFS - SAI1_TXFS */
/*! @{ */
#define IOMUXD_SAI1_TXFS_PDRV_MASK               (0x1U)
#define IOMUXD_SAI1_TXFS_PDRV_SHIFT              (0U)
#define IOMUXD_SAI1_TXFS_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXFS_PDRV_SHIFT)) & IOMUXD_SAI1_TXFS_PDRV_MASK)
#define IOMUXD_SAI1_TXFS_SAI1_TXFS_reserved_1_4_MASK (0x1EU)
#define IOMUXD_SAI1_TXFS_SAI1_TXFS_reserved_1_4_SHIFT (1U)
#define IOMUXD_SAI1_TXFS_SAI1_TXFS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXFS_SAI1_TXFS_reserved_1_4_SHIFT)) & IOMUXD_SAI1_TXFS_SAI1_TXFS_reserved_1_4_MASK)
#define IOMUXD_SAI1_TXFS_PULL_MASK               (0x60U)
#define IOMUXD_SAI1_TXFS_PULL_SHIFT              (5U)
#define IOMUXD_SAI1_TXFS_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXFS_PULL_SHIFT)) & IOMUXD_SAI1_TXFS_PULL_MASK)
#define IOMUXD_SAI1_TXFS_SAI1_TXFS_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_SAI1_TXFS_SAI1_TXFS_reserved_7_18_SHIFT (7U)
#define IOMUXD_SAI1_TXFS_SAI1_TXFS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXFS_SAI1_TXFS_reserved_7_18_SHIFT)) & IOMUXD_SAI1_TXFS_SAI1_TXFS_reserved_7_18_MASK)
#define IOMUXD_SAI1_TXFS_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_SAI1_TXFS_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_SAI1_TXFS_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXFS_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_TXFS_WAKEUP_CTRL_MASK)
#define IOMUXD_SAI1_TXFS_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_SAI1_TXFS_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_SAI1_TXFS_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXFS_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_TXFS_WAKEUP_MASK_MASK)
#define IOMUXD_SAI1_TXFS_lp_config_MASK          (0x1800000U)
#define IOMUXD_SAI1_TXFS_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_SAI1_TXFS_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXFS_lp_config_SHIFT)) & IOMUXD_SAI1_TXFS_lp_config_MASK)
#define IOMUXD_SAI1_TXFS_sw_config_MASK          (0x6000000U)
#define IOMUXD_SAI1_TXFS_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_SAI1_TXFS_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXFS_sw_config_SHIFT)) & IOMUXD_SAI1_TXFS_sw_config_MASK)
#define IOMUXD_SAI1_TXFS_mux_mode_MASK           (0x38000000U)
#define IOMUXD_SAI1_TXFS_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..AUD.SAI1.TXFS
 *  0b001..AUD.SAI1.RXFS
 *  0b011..LSIO.GPIO3.IO17
 */
#define IOMUXD_SAI1_TXFS_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXFS_mux_mode_SHIFT)) & IOMUXD_SAI1_TXFS_mux_mode_MASK)
#define IOMUXD_SAI1_TXFS_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_SAI1_TXFS_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_SAI1_TXFS_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXFS_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_TXFS_update_pad_ctl_MASK)
#define IOMUXD_SAI1_TXFS_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_SAI1_TXFS_update_mux_mode_SHIFT   (31U)
#define IOMUXD_SAI1_TXFS_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_TXFS_update_mux_mode_SHIFT)) & IOMUXD_SAI1_TXFS_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_MASK)
/*! @} */

/*! @name ADC_IN7 - ADC_IN7 */
/*! @{ */
#define IOMUXD_ADC_IN7_DSE_MASK                  (0x7U)
#define IOMUXD_ADC_IN7_DSE_SHIFT                 (0U)
#define IOMUXD_ADC_IN7_DSE(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN7_DSE_SHIFT)) & IOMUXD_ADC_IN7_DSE_MASK)
#define IOMUXD_ADC_IN7_ADC_IN7_reserved_3_4_MASK (0x18U)
#define IOMUXD_ADC_IN7_ADC_IN7_reserved_3_4_SHIFT (3U)
#define IOMUXD_ADC_IN7_ADC_IN7_reserved_3_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN7_ADC_IN7_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN7_ADC_IN7_reserved_3_4_MASK)
#define IOMUXD_ADC_IN7_PULL_MASK                 (0x60U)
#define IOMUXD_ADC_IN7_PULL_SHIFT                (5U)
#define IOMUXD_ADC_IN7_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN7_PULL_SHIFT)) & IOMUXD_ADC_IN7_PULL_MASK)
#define IOMUXD_ADC_IN7_ADC_IN7_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ADC_IN7_ADC_IN7_reserved_7_18_SHIFT (7U)
#define IOMUXD_ADC_IN7_ADC_IN7_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN7_ADC_IN7_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN7_ADC_IN7_reserved_7_18_MASK)
#define IOMUXD_ADC_IN7_WAKEUP_CTRL_MASK          (0x380000U)
#define IOMUXD_ADC_IN7_WAKEUP_CTRL_SHIFT         (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ADC_IN7_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN7_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN7_WAKEUP_CTRL_MASK)
#define IOMUXD_ADC_IN7_WAKEUP_MASK_MASK          (0x400000U)
#define IOMUXD_ADC_IN7_WAKEUP_MASK_SHIFT         (22U)
#define IOMUXD_ADC_IN7_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN7_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN7_WAKEUP_MASK_MASK)
#define IOMUXD_ADC_IN7_lp_config_MASK            (0x1800000U)
#define IOMUXD_ADC_IN7_lp_config_SHIFT           (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ADC_IN7_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN7_lp_config_SHIFT)) & IOMUXD_ADC_IN7_lp_config_MASK)
#define IOMUXD_ADC_IN7_sw_config_MASK            (0x6000000U)
#define IOMUXD_ADC_IN7_sw_config_SHIFT           (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ADC_IN7_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN7_sw_config_SHIFT)) & IOMUXD_ADC_IN7_sw_config_MASK)
#define IOMUXD_ADC_IN7_mux_mode_MASK             (0x38000000U)
#define IOMUXD_ADC_IN7_mux_mode_SHIFT            (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.ADC1.IN3
 *  0b001..DMA.SPI1.CS1
 *  0b010..LSIO.KPP0.ROW3
 *  0b011..LSIO.GPIO3.IO25
 */
#define IOMUXD_ADC_IN7_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN7_mux_mode_SHIFT)) & IOMUXD_ADC_IN7_mux_mode_MASK)
#define IOMUXD_ADC_IN7_update_pad_ctl_MASK       (0x40000000U)
#define IOMUXD_ADC_IN7_update_pad_ctl_SHIFT      (30U)
#define IOMUXD_ADC_IN7_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN7_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN7_update_pad_ctl_MASK)
#define IOMUXD_ADC_IN7_update_mux_mode_MASK      (0x80000000U)
#define IOMUXD_ADC_IN7_update_mux_mode_SHIFT     (31U)
#define IOMUXD_ADC_IN7_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN7_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN7_update_mux_mode_MASK)
/*! @} */

/*! @name ADC_IN6 - ADC_IN6 */
/*! @{ */
#define IOMUXD_ADC_IN6_DSE_MASK                  (0x7U)
#define IOMUXD_ADC_IN6_DSE_SHIFT                 (0U)
#define IOMUXD_ADC_IN6_DSE(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN6_DSE_SHIFT)) & IOMUXD_ADC_IN6_DSE_MASK)
#define IOMUXD_ADC_IN6_ADC_IN6_reserved_3_4_MASK (0x18U)
#define IOMUXD_ADC_IN6_ADC_IN6_reserved_3_4_SHIFT (3U)
#define IOMUXD_ADC_IN6_ADC_IN6_reserved_3_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN6_ADC_IN6_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN6_ADC_IN6_reserved_3_4_MASK)
#define IOMUXD_ADC_IN6_PULL_MASK                 (0x60U)
#define IOMUXD_ADC_IN6_PULL_SHIFT                (5U)
#define IOMUXD_ADC_IN6_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN6_PULL_SHIFT)) & IOMUXD_ADC_IN6_PULL_MASK)
#define IOMUXD_ADC_IN6_ADC_IN6_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ADC_IN6_ADC_IN6_reserved_7_18_SHIFT (7U)
#define IOMUXD_ADC_IN6_ADC_IN6_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN6_ADC_IN6_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN6_ADC_IN6_reserved_7_18_MASK)
#define IOMUXD_ADC_IN6_WAKEUP_CTRL_MASK          (0x380000U)
#define IOMUXD_ADC_IN6_WAKEUP_CTRL_SHIFT         (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ADC_IN6_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN6_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN6_WAKEUP_CTRL_MASK)
#define IOMUXD_ADC_IN6_WAKEUP_MASK_MASK          (0x400000U)
#define IOMUXD_ADC_IN6_WAKEUP_MASK_SHIFT         (22U)
#define IOMUXD_ADC_IN6_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN6_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN6_WAKEUP_MASK_MASK)
#define IOMUXD_ADC_IN6_lp_config_MASK            (0x1800000U)
#define IOMUXD_ADC_IN6_lp_config_SHIFT           (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ADC_IN6_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN6_lp_config_SHIFT)) & IOMUXD_ADC_IN6_lp_config_MASK)
#define IOMUXD_ADC_IN6_sw_config_MASK            (0x6000000U)
#define IOMUXD_ADC_IN6_sw_config_SHIFT           (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ADC_IN6_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN6_sw_config_SHIFT)) & IOMUXD_ADC_IN6_sw_config_MASK)
#define IOMUXD_ADC_IN6_mux_mode_MASK             (0x38000000U)
#define IOMUXD_ADC_IN6_mux_mode_SHIFT            (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.ADC1.IN2
 *  0b001..DMA.SPI1.CS0
 *  0b010..LSIO.KPP0.ROW2
 *  0b011..LSIO.GPIO3.IO24
 */
#define IOMUXD_ADC_IN6_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN6_mux_mode_SHIFT)) & IOMUXD_ADC_IN6_mux_mode_MASK)
#define IOMUXD_ADC_IN6_update_pad_ctl_MASK       (0x40000000U)
#define IOMUXD_ADC_IN6_update_pad_ctl_SHIFT      (30U)
#define IOMUXD_ADC_IN6_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN6_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN6_update_pad_ctl_MASK)
#define IOMUXD_ADC_IN6_update_mux_mode_MASK      (0x80000000U)
#define IOMUXD_ADC_IN6_update_mux_mode_SHIFT     (31U)
#define IOMUXD_ADC_IN6_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN6_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN6_update_mux_mode_MASK)
/*! @} */

/*! @name ADC_IN5 - ADC_IN5 */
/*! @{ */
#define IOMUXD_ADC_IN5_DSE_MASK                  (0x7U)
#define IOMUXD_ADC_IN5_DSE_SHIFT                 (0U)
#define IOMUXD_ADC_IN5_DSE(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_DSE_SHIFT)) & IOMUXD_ADC_IN5_DSE_MASK)
#define IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_MASK (0x18U)
#define IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_SHIFT (3U)
#define IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_MASK)
#define IOMUXD_ADC_IN5_PULL_MASK                 (0x60U)
#define IOMUXD_ADC_IN5_PULL_SHIFT                (5U)
#define IOMUXD_ADC_IN5_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_PULL_SHIFT)) & IOMUXD_ADC_IN5_PULL_MASK)
#define IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_SHIFT (7U)
#define IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_MASK)
#define IOMUXD_ADC_IN5_WAKEUP_CTRL_MASK          (0x380000U)
#define IOMUXD_ADC_IN5_WAKEUP_CTRL_SHIFT         (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ADC_IN5_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN5_WAKEUP_CTRL_MASK)
#define IOMUXD_ADC_IN5_WAKEUP_MASK_MASK          (0x400000U)
#define IOMUXD_ADC_IN5_WAKEUP_MASK_SHIFT         (22U)
#define IOMUXD_ADC_IN5_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN5_WAKEUP_MASK_MASK)
#define IOMUXD_ADC_IN5_lp_config_MASK            (0x1800000U)
#define IOMUXD_ADC_IN5_lp_config_SHIFT           (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ADC_IN5_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_lp_config_SHIFT)) & IOMUXD_ADC_IN5_lp_config_MASK)
#define IOMUXD_ADC_IN5_sw_config_MASK            (0x6000000U)
#define IOMUXD_ADC_IN5_sw_config_SHIFT           (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ADC_IN5_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_sw_config_SHIFT)) & IOMUXD_ADC_IN5_sw_config_MASK)
#define IOMUXD_ADC_IN5_mux_mode_MASK             (0x38000000U)
#define IOMUXD_ADC_IN5_mux_mode_SHIFT            (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.ADC1.IN1
 *  0b001..DMA.SPI1.SDI
 *  0b010..LSIO.KPP0.ROW1
 *  0b011..LSIO.GPIO3.IO23
 */
#define IOMUXD_ADC_IN5_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_mux_mode_SHIFT)) & IOMUXD_ADC_IN5_mux_mode_MASK)
#define IOMUXD_ADC_IN5_update_pad_ctl_MASK       (0x40000000U)
#define IOMUXD_ADC_IN5_update_pad_ctl_SHIFT      (30U)
#define IOMUXD_ADC_IN5_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN5_update_pad_ctl_MASK)
#define IOMUXD_ADC_IN5_update_mux_mode_MASK      (0x80000000U)
#define IOMUXD_ADC_IN5_update_mux_mode_SHIFT     (31U)
#define IOMUXD_ADC_IN5_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN5_update_mux_mode_MASK)
/*! @} */

/*! @name ADC_IN4 - ADC_IN4 */
/*! @{ */
#define IOMUXD_ADC_IN4_DSE_MASK                  (0x7U)
#define IOMUXD_ADC_IN4_DSE_SHIFT                 (0U)
#define IOMUXD_ADC_IN4_DSE(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_DSE_SHIFT)) & IOMUXD_ADC_IN4_DSE_MASK)
#define IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_MASK (0x18U)
#define IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_SHIFT (3U)
#define IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_MASK)
#define IOMUXD_ADC_IN4_PULL_MASK                 (0x60U)
#define IOMUXD_ADC_IN4_PULL_SHIFT                (5U)
#define IOMUXD_ADC_IN4_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_PULL_SHIFT)) & IOMUXD_ADC_IN4_PULL_MASK)
#define IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_SHIFT (7U)
#define IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_MASK)
#define IOMUXD_ADC_IN4_WAKEUP_CTRL_MASK          (0x380000U)
#define IOMUXD_ADC_IN4_WAKEUP_CTRL_SHIFT         (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ADC_IN4_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN4_WAKEUP_CTRL_MASK)
#define IOMUXD_ADC_IN4_WAKEUP_MASK_MASK          (0x400000U)
#define IOMUXD_ADC_IN4_WAKEUP_MASK_SHIFT         (22U)
#define IOMUXD_ADC_IN4_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN4_WAKEUP_MASK_MASK)
#define IOMUXD_ADC_IN4_lp_config_MASK            (0x1800000U)
#define IOMUXD_ADC_IN4_lp_config_SHIFT           (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ADC_IN4_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_lp_config_SHIFT)) & IOMUXD_ADC_IN4_lp_config_MASK)
#define IOMUXD_ADC_IN4_sw_config_MASK            (0x6000000U)
#define IOMUXD_ADC_IN4_sw_config_SHIFT           (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ADC_IN4_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_sw_config_SHIFT)) & IOMUXD_ADC_IN4_sw_config_MASK)
#define IOMUXD_ADC_IN4_mux_mode_MASK             (0x38000000U)
#define IOMUXD_ADC_IN4_mux_mode_SHIFT            (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.ADC1.IN0
 *  0b001..DMA.SPI1.SDO
 *  0b010..LSIO.KPP0.ROW0
 *  0b011..LSIO.GPIO3.IO22
 */
#define IOMUXD_ADC_IN4_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_mux_mode_SHIFT)) & IOMUXD_ADC_IN4_mux_mode_MASK)
#define IOMUXD_ADC_IN4_update_pad_ctl_MASK       (0x40000000U)
#define IOMUXD_ADC_IN4_update_pad_ctl_SHIFT      (30U)
#define IOMUXD_ADC_IN4_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN4_update_pad_ctl_MASK)
#define IOMUXD_ADC_IN4_update_mux_mode_MASK      (0x80000000U)
#define IOMUXD_ADC_IN4_update_mux_mode_SHIFT     (31U)
#define IOMUXD_ADC_IN4_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN4_update_mux_mode_MASK)
/*! @} */

/*! @name ADC_IN3 - ADC_IN3 */
/*! @{ */
#define IOMUXD_ADC_IN3_DSE_MASK                  (0x7U)
#define IOMUXD_ADC_IN3_DSE_SHIFT                 (0U)
#define IOMUXD_ADC_IN3_DSE(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_DSE_SHIFT)) & IOMUXD_ADC_IN3_DSE_MASK)
#define IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_MASK (0x18U)
#define IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_SHIFT (3U)
#define IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_MASK)
#define IOMUXD_ADC_IN3_PULL_MASK                 (0x60U)
#define IOMUXD_ADC_IN3_PULL_SHIFT                (5U)
#define IOMUXD_ADC_IN3_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_PULL_SHIFT)) & IOMUXD_ADC_IN3_PULL_MASK)
#define IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_SHIFT (7U)
#define IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_MASK)
#define IOMUXD_ADC_IN3_WAKEUP_CTRL_MASK          (0x380000U)
#define IOMUXD_ADC_IN3_WAKEUP_CTRL_SHIFT         (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ADC_IN3_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN3_WAKEUP_CTRL_MASK)
#define IOMUXD_ADC_IN3_WAKEUP_MASK_MASK          (0x400000U)
#define IOMUXD_ADC_IN3_WAKEUP_MASK_SHIFT         (22U)
#define IOMUXD_ADC_IN3_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN3_WAKEUP_MASK_MASK)
#define IOMUXD_ADC_IN3_lp_config_MASK            (0x1800000U)
#define IOMUXD_ADC_IN3_lp_config_SHIFT           (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ADC_IN3_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_lp_config_SHIFT)) & IOMUXD_ADC_IN3_lp_config_MASK)
#define IOMUXD_ADC_IN3_sw_config_MASK            (0x6000000U)
#define IOMUXD_ADC_IN3_sw_config_SHIFT           (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ADC_IN3_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_sw_config_SHIFT)) & IOMUXD_ADC_IN3_sw_config_MASK)
#define IOMUXD_ADC_IN3_mux_mode_MASK             (0x38000000U)
#define IOMUXD_ADC_IN3_mux_mode_SHIFT            (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.ADC0.IN3
 *  0b001..DMA.SPI1.SCK
 *  0b010..LSIO.KPP0.COL3
 *  0b011..LSIO.GPIO3.IO21
 */
#define IOMUXD_ADC_IN3_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_mux_mode_SHIFT)) & IOMUXD_ADC_IN3_mux_mode_MASK)
#define IOMUXD_ADC_IN3_update_pad_ctl_MASK       (0x40000000U)
#define IOMUXD_ADC_IN3_update_pad_ctl_SHIFT      (30U)
#define IOMUXD_ADC_IN3_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN3_update_pad_ctl_MASK)
#define IOMUXD_ADC_IN3_update_mux_mode_MASK      (0x80000000U)
#define IOMUXD_ADC_IN3_update_mux_mode_SHIFT     (31U)
#define IOMUXD_ADC_IN3_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN3_update_mux_mode_MASK)
/*! @} */

/*! @name ADC_IN2 - ADC_IN2 */
/*! @{ */
#define IOMUXD_ADC_IN2_DSE_MASK                  (0x7U)
#define IOMUXD_ADC_IN2_DSE_SHIFT                 (0U)
#define IOMUXD_ADC_IN2_DSE(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_DSE_SHIFT)) & IOMUXD_ADC_IN2_DSE_MASK)
#define IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_MASK (0x18U)
#define IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_SHIFT (3U)
#define IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_MASK)
#define IOMUXD_ADC_IN2_PULL_MASK                 (0x60U)
#define IOMUXD_ADC_IN2_PULL_SHIFT                (5U)
#define IOMUXD_ADC_IN2_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_PULL_SHIFT)) & IOMUXD_ADC_IN2_PULL_MASK)
#define IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_SHIFT (7U)
#define IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_MASK)
#define IOMUXD_ADC_IN2_WAKEUP_CTRL_MASK          (0x380000U)
#define IOMUXD_ADC_IN2_WAKEUP_CTRL_SHIFT         (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ADC_IN2_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN2_WAKEUP_CTRL_MASK)
#define IOMUXD_ADC_IN2_WAKEUP_MASK_MASK          (0x400000U)
#define IOMUXD_ADC_IN2_WAKEUP_MASK_SHIFT         (22U)
#define IOMUXD_ADC_IN2_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN2_WAKEUP_MASK_MASK)
#define IOMUXD_ADC_IN2_lp_config_MASK            (0x1800000U)
#define IOMUXD_ADC_IN2_lp_config_SHIFT           (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ADC_IN2_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_lp_config_SHIFT)) & IOMUXD_ADC_IN2_lp_config_MASK)
#define IOMUXD_ADC_IN2_sw_config_MASK            (0x6000000U)
#define IOMUXD_ADC_IN2_sw_config_SHIFT           (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ADC_IN2_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_sw_config_SHIFT)) & IOMUXD_ADC_IN2_sw_config_MASK)
#define IOMUXD_ADC_IN2_mux_mode_MASK             (0x38000000U)
#define IOMUXD_ADC_IN2_mux_mode_SHIFT            (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.ADC0.IN2
 *  0b010..LSIO.KPP0.COL2
 *  0b011..LSIO.GPIO3.IO20
 */
#define IOMUXD_ADC_IN2_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_mux_mode_SHIFT)) & IOMUXD_ADC_IN2_mux_mode_MASK)
#define IOMUXD_ADC_IN2_update_pad_ctl_MASK       (0x40000000U)
#define IOMUXD_ADC_IN2_update_pad_ctl_SHIFT      (30U)
#define IOMUXD_ADC_IN2_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN2_update_pad_ctl_MASK)
#define IOMUXD_ADC_IN2_update_mux_mode_MASK      (0x80000000U)
#define IOMUXD_ADC_IN2_update_mux_mode_SHIFT     (31U)
#define IOMUXD_ADC_IN2_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN2_update_mux_mode_MASK)
/*! @} */

/*! @name ADC_IN1 - ADC_IN1 */
/*! @{ */
#define IOMUXD_ADC_IN1_DSE_MASK                  (0x7U)
#define IOMUXD_ADC_IN1_DSE_SHIFT                 (0U)
#define IOMUXD_ADC_IN1_DSE(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_DSE_SHIFT)) & IOMUXD_ADC_IN1_DSE_MASK)
#define IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_MASK (0x18U)
#define IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_SHIFT (3U)
#define IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_MASK)
#define IOMUXD_ADC_IN1_PULL_MASK                 (0x60U)
#define IOMUXD_ADC_IN1_PULL_SHIFT                (5U)
#define IOMUXD_ADC_IN1_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_PULL_SHIFT)) & IOMUXD_ADC_IN1_PULL_MASK)
#define IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_SHIFT (7U)
#define IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_MASK)
#define IOMUXD_ADC_IN1_WAKEUP_CTRL_MASK          (0x380000U)
#define IOMUXD_ADC_IN1_WAKEUP_CTRL_SHIFT         (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ADC_IN1_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN1_WAKEUP_CTRL_MASK)
#define IOMUXD_ADC_IN1_WAKEUP_MASK_MASK          (0x400000U)
#define IOMUXD_ADC_IN1_WAKEUP_MASK_SHIFT         (22U)
#define IOMUXD_ADC_IN1_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN1_WAKEUP_MASK_MASK)
#define IOMUXD_ADC_IN1_lp_config_MASK            (0x1800000U)
#define IOMUXD_ADC_IN1_lp_config_SHIFT           (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ADC_IN1_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_lp_config_SHIFT)) & IOMUXD_ADC_IN1_lp_config_MASK)
#define IOMUXD_ADC_IN1_sw_config_MASK            (0x6000000U)
#define IOMUXD_ADC_IN1_sw_config_SHIFT           (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ADC_IN1_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_sw_config_SHIFT)) & IOMUXD_ADC_IN1_sw_config_MASK)
#define IOMUXD_ADC_IN1_mux_mode_MASK             (0x38000000U)
#define IOMUXD_ADC_IN1_mux_mode_SHIFT            (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.ADC0.IN1
 *  0b010..LSIO.KPP0.COL1
 *  0b011..LSIO.GPIO3.IO19
 */
#define IOMUXD_ADC_IN1_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_mux_mode_SHIFT)) & IOMUXD_ADC_IN1_mux_mode_MASK)
#define IOMUXD_ADC_IN1_update_pad_ctl_MASK       (0x40000000U)
#define IOMUXD_ADC_IN1_update_pad_ctl_SHIFT      (30U)
#define IOMUXD_ADC_IN1_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN1_update_pad_ctl_MASK)
#define IOMUXD_ADC_IN1_update_mux_mode_MASK      (0x80000000U)
#define IOMUXD_ADC_IN1_update_mux_mode_SHIFT     (31U)
#define IOMUXD_ADC_IN1_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN1_update_mux_mode_MASK)
/*! @} */

/*! @name ADC_IN0 - ADC_IN0 */
/*! @{ */
#define IOMUXD_ADC_IN0_DSE_MASK                  (0x7U)
#define IOMUXD_ADC_IN0_DSE_SHIFT                 (0U)
#define IOMUXD_ADC_IN0_DSE(x)                    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_DSE_SHIFT)) & IOMUXD_ADC_IN0_DSE_MASK)
#define IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_MASK (0x18U)
#define IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_SHIFT (3U)
#define IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_MASK)
#define IOMUXD_ADC_IN0_PULL_MASK                 (0x60U)
#define IOMUXD_ADC_IN0_PULL_SHIFT                (5U)
#define IOMUXD_ADC_IN0_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_PULL_SHIFT)) & IOMUXD_ADC_IN0_PULL_MASK)
#define IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_SHIFT (7U)
#define IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_MASK)
#define IOMUXD_ADC_IN0_WAKEUP_CTRL_MASK          (0x380000U)
#define IOMUXD_ADC_IN0_WAKEUP_CTRL_SHIFT         (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ADC_IN0_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN0_WAKEUP_CTRL_MASK)
#define IOMUXD_ADC_IN0_WAKEUP_MASK_MASK          (0x400000U)
#define IOMUXD_ADC_IN0_WAKEUP_MASK_SHIFT         (22U)
#define IOMUXD_ADC_IN0_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN0_WAKEUP_MASK_MASK)
#define IOMUXD_ADC_IN0_lp_config_MASK            (0x1800000U)
#define IOMUXD_ADC_IN0_lp_config_SHIFT           (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ADC_IN0_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_lp_config_SHIFT)) & IOMUXD_ADC_IN0_lp_config_MASK)
#define IOMUXD_ADC_IN0_sw_config_MASK            (0x6000000U)
#define IOMUXD_ADC_IN0_sw_config_SHIFT           (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ADC_IN0_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_sw_config_SHIFT)) & IOMUXD_ADC_IN0_sw_config_MASK)
#define IOMUXD_ADC_IN0_mux_mode_MASK             (0x38000000U)
#define IOMUXD_ADC_IN0_mux_mode_SHIFT            (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.ADC0.IN0
 *  0b010..LSIO.KPP0.COL0
 *  0b011..LSIO.GPIO3.IO18
 */
#define IOMUXD_ADC_IN0_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_mux_mode_SHIFT)) & IOMUXD_ADC_IN0_mux_mode_MASK)
#define IOMUXD_ADC_IN0_update_pad_ctl_MASK       (0x40000000U)
#define IOMUXD_ADC_IN0_update_pad_ctl_SHIFT      (30U)
#define IOMUXD_ADC_IN0_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN0_update_pad_ctl_MASK)
#define IOMUXD_ADC_IN0_update_mux_mode_MASK      (0x80000000U)
#define IOMUXD_ADC_IN0_update_mux_mode_SHIFT     (31U)
#define IOMUXD_ADC_IN0_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN0_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_1_5 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXC_MASK    (0x1U)
#define IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXC_SHIFT   (0U)
#define IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXC(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXC_MASK)
#define IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXD_MASK    (0x2U)
#define IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXD_SHIFT   (1U)
#define IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXD(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXD_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXD_MASK)
#define IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXFS_MASK   (0x4U)
#define IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXFS_SHIFT  (2U)
#define IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXFS(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXFS_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_5_SAI1_TXFS_MASK)
#define IOMUXD_IOMUXD_GROUP_1_5_iomuxd_group_1_5_reserved_3_3_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_1_5_iomuxd_group_1_5_reserved_3_3_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_1_5_iomuxd_group_1_5_reserved_3_3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_5_iomuxd_group_1_5_reserved_3_3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_5_iomuxd_group_1_5_reserved_3_3_MASK)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN7_MASK     (0x10U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN7_SHIFT    (4U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN7(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_5_ADC_IN7_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_5_ADC_IN7_MASK)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN6_MASK     (0x20U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN6_SHIFT    (5U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN6(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_5_ADC_IN6_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_5_ADC_IN6_MASK)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN5_MASK     (0x40U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN5_SHIFT    (6U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN5(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_5_ADC_IN5_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_5_ADC_IN5_MASK)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN4_MASK     (0x80U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN4_SHIFT    (7U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN4(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_5_ADC_IN4_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_5_ADC_IN4_MASK)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN3_MASK     (0x100U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN3_SHIFT    (8U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN3(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_5_ADC_IN3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_5_ADC_IN3_MASK)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN2_MASK     (0x200U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN2_SHIFT    (9U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN2(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_5_ADC_IN2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_5_ADC_IN2_MASK)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN1_MASK     (0x400U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN1_SHIFT    (10U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN1(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_5_ADC_IN1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_5_ADC_IN1_MASK)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN0_MASK     (0x800U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN0_SHIFT    (11U)
#define IOMUXD_IOMUXD_GROUP_1_5_ADC_IN0(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_5_ADC_IN0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_5_ADC_IN0_MASK)
#define IOMUXD_IOMUXD_GROUP_1_5_iomuxd_group_1_5_reserved_12_31_MASK (0xFFFFF000U)
#define IOMUXD_IOMUXD_GROUP_1_5_iomuxd_group_1_5_reserved_12_31_SHIFT (12U)
#define IOMUXD_IOMUXD_GROUP_1_5_iomuxd_group_1_5_reserved_12_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_5_iomuxd_group_1_5_reserved_12_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_5_iomuxd_group_1_5_reserved_12_31_MASK)
/*! @} */

/*! @name MLB_SIG - MLB_SIG */
/*! @{ */
#define IOMUXD_MLB_SIG_PDRV_MASK                 (0x1U)
#define IOMUXD_MLB_SIG_PDRV_SHIFT                (0U)
#define IOMUXD_MLB_SIG_PDRV(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_SIG_PDRV_SHIFT)) & IOMUXD_MLB_SIG_PDRV_MASK)
#define IOMUXD_MLB_SIG_MLB_SIG_reserved_1_4_MASK (0x1EU)
#define IOMUXD_MLB_SIG_MLB_SIG_reserved_1_4_SHIFT (1U)
#define IOMUXD_MLB_SIG_MLB_SIG_reserved_1_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_SIG_MLB_SIG_reserved_1_4_SHIFT)) & IOMUXD_MLB_SIG_MLB_SIG_reserved_1_4_MASK)
#define IOMUXD_MLB_SIG_PULL_MASK                 (0x60U)
#define IOMUXD_MLB_SIG_PULL_SHIFT                (5U)
#define IOMUXD_MLB_SIG_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_SIG_PULL_SHIFT)) & IOMUXD_MLB_SIG_PULL_MASK)
#define IOMUXD_MLB_SIG_MLB_SIG_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MLB_SIG_MLB_SIG_reserved_7_18_SHIFT (7U)
#define IOMUXD_MLB_SIG_MLB_SIG_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_SIG_MLB_SIG_reserved_7_18_SHIFT)) & IOMUXD_MLB_SIG_MLB_SIG_reserved_7_18_MASK)
#define IOMUXD_MLB_SIG_WAKEUP_CTRL_MASK          (0x380000U)
#define IOMUXD_MLB_SIG_WAKEUP_CTRL_SHIFT         (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MLB_SIG_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_SIG_WAKEUP_CTRL_SHIFT)) & IOMUXD_MLB_SIG_WAKEUP_CTRL_MASK)
#define IOMUXD_MLB_SIG_WAKEUP_MASK_MASK          (0x400000U)
#define IOMUXD_MLB_SIG_WAKEUP_MASK_SHIFT         (22U)
#define IOMUXD_MLB_SIG_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_SIG_WAKEUP_MASK_SHIFT)) & IOMUXD_MLB_SIG_WAKEUP_MASK_MASK)
#define IOMUXD_MLB_SIG_lp_config_MASK            (0x1800000U)
#define IOMUXD_MLB_SIG_lp_config_SHIFT           (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MLB_SIG_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_SIG_lp_config_SHIFT)) & IOMUXD_MLB_SIG_lp_config_MASK)
#define IOMUXD_MLB_SIG_sw_config_MASK            (0x6000000U)
#define IOMUXD_MLB_SIG_sw_config_SHIFT           (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MLB_SIG_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_SIG_sw_config_SHIFT)) & IOMUXD_MLB_SIG_sw_config_MASK)
#define IOMUXD_MLB_SIG_mux_mode_MASK             (0x38000000U)
#define IOMUXD_MLB_SIG_mux_mode_SHIFT            (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.MLB.SIG
 *  0b001..AUD.SAI3.RXC
 *  0b011..LSIO.GPIO3.IO26
 */
#define IOMUXD_MLB_SIG_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_SIG_mux_mode_SHIFT)) & IOMUXD_MLB_SIG_mux_mode_MASK)
#define IOMUXD_MLB_SIG_update_pad_ctl_MASK       (0x40000000U)
#define IOMUXD_MLB_SIG_update_pad_ctl_SHIFT      (30U)
#define IOMUXD_MLB_SIG_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_SIG_update_pad_ctl_SHIFT)) & IOMUXD_MLB_SIG_update_pad_ctl_MASK)
#define IOMUXD_MLB_SIG_update_mux_mode_MASK      (0x80000000U)
#define IOMUXD_MLB_SIG_update_mux_mode_SHIFT     (31U)
#define IOMUXD_MLB_SIG_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_SIG_update_mux_mode_SHIFT)) & IOMUXD_MLB_SIG_update_mux_mode_MASK)
/*! @} */

/*! @name MLB_CLK - MLB_CLK */
/*! @{ */
#define IOMUXD_MLB_CLK_PDRV_MASK                 (0x1U)
#define IOMUXD_MLB_CLK_PDRV_SHIFT                (0U)
#define IOMUXD_MLB_CLK_PDRV(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_CLK_PDRV_SHIFT)) & IOMUXD_MLB_CLK_PDRV_MASK)
#define IOMUXD_MLB_CLK_MLB_CLK_reserved_1_4_MASK (0x1EU)
#define IOMUXD_MLB_CLK_MLB_CLK_reserved_1_4_SHIFT (1U)
#define IOMUXD_MLB_CLK_MLB_CLK_reserved_1_4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_CLK_MLB_CLK_reserved_1_4_SHIFT)) & IOMUXD_MLB_CLK_MLB_CLK_reserved_1_4_MASK)
#define IOMUXD_MLB_CLK_PULL_MASK                 (0x60U)
#define IOMUXD_MLB_CLK_PULL_SHIFT                (5U)
#define IOMUXD_MLB_CLK_PULL(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_CLK_PULL_SHIFT)) & IOMUXD_MLB_CLK_PULL_MASK)
#define IOMUXD_MLB_CLK_MLB_CLK_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MLB_CLK_MLB_CLK_reserved_7_18_SHIFT (7U)
#define IOMUXD_MLB_CLK_MLB_CLK_reserved_7_18(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_CLK_MLB_CLK_reserved_7_18_SHIFT)) & IOMUXD_MLB_CLK_MLB_CLK_reserved_7_18_MASK)
#define IOMUXD_MLB_CLK_WAKEUP_CTRL_MASK          (0x380000U)
#define IOMUXD_MLB_CLK_WAKEUP_CTRL_SHIFT         (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MLB_CLK_WAKEUP_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_MLB_CLK_WAKEUP_CTRL_MASK)
#define IOMUXD_MLB_CLK_WAKEUP_MASK_MASK          (0x400000U)
#define IOMUXD_MLB_CLK_WAKEUP_MASK_SHIFT         (22U)
#define IOMUXD_MLB_CLK_WAKEUP_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_MLB_CLK_WAKEUP_MASK_MASK)
#define IOMUXD_MLB_CLK_lp_config_MASK            (0x1800000U)
#define IOMUXD_MLB_CLK_lp_config_SHIFT           (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MLB_CLK_lp_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_CLK_lp_config_SHIFT)) & IOMUXD_MLB_CLK_lp_config_MASK)
#define IOMUXD_MLB_CLK_sw_config_MASK            (0x6000000U)
#define IOMUXD_MLB_CLK_sw_config_SHIFT           (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MLB_CLK_sw_config(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_CLK_sw_config_SHIFT)) & IOMUXD_MLB_CLK_sw_config_MASK)
#define IOMUXD_MLB_CLK_mux_mode_MASK             (0x38000000U)
#define IOMUXD_MLB_CLK_mux_mode_SHIFT            (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.MLB.CLK
 *  0b001..AUD.SAI3.RXFS
 *  0b011..LSIO.GPIO3.IO27
 */
#define IOMUXD_MLB_CLK_mux_mode(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_CLK_mux_mode_SHIFT)) & IOMUXD_MLB_CLK_mux_mode_MASK)
#define IOMUXD_MLB_CLK_update_pad_ctl_MASK       (0x40000000U)
#define IOMUXD_MLB_CLK_update_pad_ctl_SHIFT      (30U)
#define IOMUXD_MLB_CLK_update_pad_ctl(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_CLK_update_pad_ctl_SHIFT)) & IOMUXD_MLB_CLK_update_pad_ctl_MASK)
#define IOMUXD_MLB_CLK_update_mux_mode_MASK      (0x80000000U)
#define IOMUXD_MLB_CLK_update_mux_mode_SHIFT     (31U)
#define IOMUXD_MLB_CLK_update_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_CLK_update_mux_mode_SHIFT)) & IOMUXD_MLB_CLK_update_mux_mode_MASK)
/*! @} */

/*! @name MLB_DATA - MLB_DATA */
/*! @{ */
#define IOMUXD_MLB_DATA_PDRV_MASK                (0x1U)
#define IOMUXD_MLB_DATA_PDRV_SHIFT               (0U)
#define IOMUXD_MLB_DATA_PDRV(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_DATA_PDRV_SHIFT)) & IOMUXD_MLB_DATA_PDRV_MASK)
#define IOMUXD_MLB_DATA_MLB_DATA_reserved_1_4_MASK (0x1EU)
#define IOMUXD_MLB_DATA_MLB_DATA_reserved_1_4_SHIFT (1U)
#define IOMUXD_MLB_DATA_MLB_DATA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_DATA_MLB_DATA_reserved_1_4_SHIFT)) & IOMUXD_MLB_DATA_MLB_DATA_reserved_1_4_MASK)
#define IOMUXD_MLB_DATA_PULL_MASK                (0x60U)
#define IOMUXD_MLB_DATA_PULL_SHIFT               (5U)
#define IOMUXD_MLB_DATA_PULL(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_DATA_PULL_SHIFT)) & IOMUXD_MLB_DATA_PULL_MASK)
#define IOMUXD_MLB_DATA_MLB_DATA_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_MLB_DATA_MLB_DATA_reserved_7_18_SHIFT (7U)
#define IOMUXD_MLB_DATA_MLB_DATA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_DATA_MLB_DATA_reserved_7_18_SHIFT)) & IOMUXD_MLB_DATA_MLB_DATA_reserved_7_18_MASK)
#define IOMUXD_MLB_DATA_WAKEUP_CTRL_MASK         (0x380000U)
#define IOMUXD_MLB_DATA_WAKEUP_CTRL_SHIFT        (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_MLB_DATA_WAKEUP_CTRL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_DATA_WAKEUP_CTRL_SHIFT)) & IOMUXD_MLB_DATA_WAKEUP_CTRL_MASK)
#define IOMUXD_MLB_DATA_WAKEUP_MASK_MASK         (0x400000U)
#define IOMUXD_MLB_DATA_WAKEUP_MASK_SHIFT        (22U)
#define IOMUXD_MLB_DATA_WAKEUP_MASK(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_DATA_WAKEUP_MASK_SHIFT)) & IOMUXD_MLB_DATA_WAKEUP_MASK_MASK)
#define IOMUXD_MLB_DATA_lp_config_MASK           (0x1800000U)
#define IOMUXD_MLB_DATA_lp_config_SHIFT          (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_MLB_DATA_lp_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_DATA_lp_config_SHIFT)) & IOMUXD_MLB_DATA_lp_config_MASK)
#define IOMUXD_MLB_DATA_sw_config_MASK           (0x6000000U)
#define IOMUXD_MLB_DATA_sw_config_SHIFT          (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_MLB_DATA_sw_config(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_DATA_sw_config_SHIFT)) & IOMUXD_MLB_DATA_sw_config_MASK)
#define IOMUXD_MLB_DATA_mux_mode_MASK            (0x38000000U)
#define IOMUXD_MLB_DATA_mux_mode_SHIFT           (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.MLB.DATA
 *  0b001..AUD.SAI3.RXD
 *  0b011..LSIO.GPIO3.IO28
 */
#define IOMUXD_MLB_DATA_mux_mode(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_DATA_mux_mode_SHIFT)) & IOMUXD_MLB_DATA_mux_mode_MASK)
#define IOMUXD_MLB_DATA_update_pad_ctl_MASK      (0x40000000U)
#define IOMUXD_MLB_DATA_update_pad_ctl_SHIFT     (30U)
#define IOMUXD_MLB_DATA_update_pad_ctl(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_DATA_update_pad_ctl_SHIFT)) & IOMUXD_MLB_DATA_update_pad_ctl_MASK)
#define IOMUXD_MLB_DATA_update_mux_mode_MASK     (0x80000000U)
#define IOMUXD_MLB_DATA_update_mux_mode_SHIFT    (31U)
#define IOMUXD_MLB_DATA_update_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_MLB_DATA_update_mux_mode_SHIFT)) & IOMUXD_MLB_DATA_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_update_mux_mode_MASK)
/*! @} */

/*! @name FLEXCAN0_RX - FLEXCAN0_RX */
/*! @{ */
#define IOMUXD_FLEXCAN0_RX_PDRV_MASK             (0x1U)
#define IOMUXD_FLEXCAN0_RX_PDRV_SHIFT            (0U)
#define IOMUXD_FLEXCAN0_RX_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_PDRV_SHIFT)) & IOMUXD_FLEXCAN0_RX_PDRV_MASK)
#define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_MASK (0x1EU)
#define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_SHIFT (1U)
#define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_MASK)
#define IOMUXD_FLEXCAN0_RX_PULL_MASK             (0x60U)
#define IOMUXD_FLEXCAN0_RX_PULL_SHIFT            (5U)
#define IOMUXD_FLEXCAN0_RX_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_PULL_SHIFT)) & IOMUXD_FLEXCAN0_RX_PULL_MASK)
#define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_SHIFT (7U)
#define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_MASK)
#define IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_MASK)
#define IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_FLEXCAN0_RX_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_MASK)
#define IOMUXD_FLEXCAN0_RX_lp_config_MASK        (0x1800000U)
#define IOMUXD_FLEXCAN0_RX_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_FLEXCAN0_RX_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_lp_config_SHIFT)) & IOMUXD_FLEXCAN0_RX_lp_config_MASK)
#define IOMUXD_FLEXCAN0_RX_sw_config_MASK        (0x6000000U)
#define IOMUXD_FLEXCAN0_RX_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_FLEXCAN0_RX_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_sw_config_SHIFT)) & IOMUXD_FLEXCAN0_RX_sw_config_MASK)
#define IOMUXD_FLEXCAN0_RX_mux_mode_MASK         (0x38000000U)
#define IOMUXD_FLEXCAN0_RX_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.FLEXCAN0.RX
 *  0b011..LSIO.GPIO3.IO29
 */
#define IOMUXD_FLEXCAN0_RX_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_RX_mux_mode_MASK)
#define IOMUXD_FLEXCAN0_RX_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_FLEXCAN0_RX_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_FLEXCAN0_RX_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN0_RX_update_pad_ctl_MASK)
#define IOMUXD_FLEXCAN0_RX_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_FLEXCAN0_RX_update_mux_mode_SHIFT (31U)
#define IOMUXD_FLEXCAN0_RX_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_RX_update_mux_mode_MASK)
/*! @} */

/*! @name FLEXCAN0_TX - FLEXCAN0_TX */
/*! @{ */
#define IOMUXD_FLEXCAN0_TX_PDRV_MASK             (0x1U)
#define IOMUXD_FLEXCAN0_TX_PDRV_SHIFT            (0U)
#define IOMUXD_FLEXCAN0_TX_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_PDRV_SHIFT)) & IOMUXD_FLEXCAN0_TX_PDRV_MASK)
#define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_MASK (0x1EU)
#define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_SHIFT (1U)
#define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_MASK)
#define IOMUXD_FLEXCAN0_TX_PULL_MASK             (0x60U)
#define IOMUXD_FLEXCAN0_TX_PULL_SHIFT            (5U)
#define IOMUXD_FLEXCAN0_TX_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_PULL_SHIFT)) & IOMUXD_FLEXCAN0_TX_PULL_MASK)
#define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_SHIFT (7U)
#define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_MASK)
#define IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_MASK)
#define IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_FLEXCAN0_TX_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_MASK)
#define IOMUXD_FLEXCAN0_TX_lp_config_MASK        (0x1800000U)
#define IOMUXD_FLEXCAN0_TX_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_FLEXCAN0_TX_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_lp_config_SHIFT)) & IOMUXD_FLEXCAN0_TX_lp_config_MASK)
#define IOMUXD_FLEXCAN0_TX_sw_config_MASK        (0x6000000U)
#define IOMUXD_FLEXCAN0_TX_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_FLEXCAN0_TX_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_sw_config_SHIFT)) & IOMUXD_FLEXCAN0_TX_sw_config_MASK)
#define IOMUXD_FLEXCAN0_TX_mux_mode_MASK         (0x38000000U)
#define IOMUXD_FLEXCAN0_TX_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.FLEXCAN0.TX
 *  0b011..LSIO.GPIO3.IO30
 */
#define IOMUXD_FLEXCAN0_TX_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_TX_mux_mode_MASK)
#define IOMUXD_FLEXCAN0_TX_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_FLEXCAN0_TX_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_FLEXCAN0_TX_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN0_TX_update_pad_ctl_MASK)
#define IOMUXD_FLEXCAN0_TX_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_FLEXCAN0_TX_update_mux_mode_SHIFT (31U)
#define IOMUXD_FLEXCAN0_TX_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_TX_update_mux_mode_MASK)
/*! @} */

/*! @name FLEXCAN1_RX - FLEXCAN1_RX */
/*! @{ */
#define IOMUXD_FLEXCAN1_RX_PDRV_MASK             (0x1U)
#define IOMUXD_FLEXCAN1_RX_PDRV_SHIFT            (0U)
#define IOMUXD_FLEXCAN1_RX_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_PDRV_SHIFT)) & IOMUXD_FLEXCAN1_RX_PDRV_MASK)
#define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_MASK (0x1EU)
#define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_SHIFT (1U)
#define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_MASK)
#define IOMUXD_FLEXCAN1_RX_PULL_MASK             (0x60U)
#define IOMUXD_FLEXCAN1_RX_PULL_SHIFT            (5U)
#define IOMUXD_FLEXCAN1_RX_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_PULL_SHIFT)) & IOMUXD_FLEXCAN1_RX_PULL_MASK)
#define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_SHIFT (7U)
#define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_MASK)
#define IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_MASK)
#define IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_FLEXCAN1_RX_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_MASK)
#define IOMUXD_FLEXCAN1_RX_lp_config_MASK        (0x1800000U)
#define IOMUXD_FLEXCAN1_RX_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_FLEXCAN1_RX_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_lp_config_SHIFT)) & IOMUXD_FLEXCAN1_RX_lp_config_MASK)
#define IOMUXD_FLEXCAN1_RX_sw_config_MASK        (0x6000000U)
#define IOMUXD_FLEXCAN1_RX_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_FLEXCAN1_RX_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_sw_config_SHIFT)) & IOMUXD_FLEXCAN1_RX_sw_config_MASK)
#define IOMUXD_FLEXCAN1_RX_mux_mode_MASK         (0x38000000U)
#define IOMUXD_FLEXCAN1_RX_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.FLEXCAN1.RX
 *  0b011..LSIO.GPIO3.IO31
 */
#define IOMUXD_FLEXCAN1_RX_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_RX_mux_mode_MASK)
#define IOMUXD_FLEXCAN1_RX_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_FLEXCAN1_RX_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_FLEXCAN1_RX_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN1_RX_update_pad_ctl_MASK)
#define IOMUXD_FLEXCAN1_RX_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_FLEXCAN1_RX_update_mux_mode_SHIFT (31U)
#define IOMUXD_FLEXCAN1_RX_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_RX_update_mux_mode_MASK)
/*! @} */

/*! @name FLEXCAN1_TX - FLEXCAN1_TX */
/*! @{ */
#define IOMUXD_FLEXCAN1_TX_PDRV_MASK             (0x1U)
#define IOMUXD_FLEXCAN1_TX_PDRV_SHIFT            (0U)
#define IOMUXD_FLEXCAN1_TX_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_PDRV_SHIFT)) & IOMUXD_FLEXCAN1_TX_PDRV_MASK)
#define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_MASK (0x1EU)
#define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_SHIFT (1U)
#define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_MASK)
#define IOMUXD_FLEXCAN1_TX_PULL_MASK             (0x60U)
#define IOMUXD_FLEXCAN1_TX_PULL_SHIFT            (5U)
#define IOMUXD_FLEXCAN1_TX_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_PULL_SHIFT)) & IOMUXD_FLEXCAN1_TX_PULL_MASK)
#define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_SHIFT (7U)
#define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_MASK)
#define IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_MASK)
#define IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_FLEXCAN1_TX_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_MASK)
#define IOMUXD_FLEXCAN1_TX_lp_config_MASK        (0x1800000U)
#define IOMUXD_FLEXCAN1_TX_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_FLEXCAN1_TX_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_lp_config_SHIFT)) & IOMUXD_FLEXCAN1_TX_lp_config_MASK)
#define IOMUXD_FLEXCAN1_TX_sw_config_MASK        (0x6000000U)
#define IOMUXD_FLEXCAN1_TX_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_FLEXCAN1_TX_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_sw_config_SHIFT)) & IOMUXD_FLEXCAN1_TX_sw_config_MASK)
#define IOMUXD_FLEXCAN1_TX_mux_mode_MASK         (0x38000000U)
#define IOMUXD_FLEXCAN1_TX_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.FLEXCAN1.TX
 *  0b011..LSIO.GPIO4.IO00
 */
#define IOMUXD_FLEXCAN1_TX_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_TX_mux_mode_MASK)
#define IOMUXD_FLEXCAN1_TX_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_FLEXCAN1_TX_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_FLEXCAN1_TX_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN1_TX_update_pad_ctl_MASK)
#define IOMUXD_FLEXCAN1_TX_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_FLEXCAN1_TX_update_mux_mode_SHIFT (31U)
#define IOMUXD_FLEXCAN1_TX_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_TX_update_mux_mode_MASK)
/*! @} */

/*! @name FLEXCAN2_RX - FLEXCAN2_RX */
/*! @{ */
#define IOMUXD_FLEXCAN2_RX_PDRV_MASK             (0x1U)
#define IOMUXD_FLEXCAN2_RX_PDRV_SHIFT            (0U)
#define IOMUXD_FLEXCAN2_RX_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_PDRV_SHIFT)) & IOMUXD_FLEXCAN2_RX_PDRV_MASK)
#define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_MASK (0x1EU)
#define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_SHIFT (1U)
#define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_MASK)
#define IOMUXD_FLEXCAN2_RX_PULL_MASK             (0x60U)
#define IOMUXD_FLEXCAN2_RX_PULL_SHIFT            (5U)
#define IOMUXD_FLEXCAN2_RX_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_PULL_SHIFT)) & IOMUXD_FLEXCAN2_RX_PULL_MASK)
#define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_SHIFT (7U)
#define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_MASK)
#define IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_MASK)
#define IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_FLEXCAN2_RX_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_MASK)
#define IOMUXD_FLEXCAN2_RX_lp_config_MASK        (0x1800000U)
#define IOMUXD_FLEXCAN2_RX_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_FLEXCAN2_RX_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_lp_config_SHIFT)) & IOMUXD_FLEXCAN2_RX_lp_config_MASK)
#define IOMUXD_FLEXCAN2_RX_sw_config_MASK        (0x6000000U)
#define IOMUXD_FLEXCAN2_RX_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_FLEXCAN2_RX_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_sw_config_SHIFT)) & IOMUXD_FLEXCAN2_RX_sw_config_MASK)
#define IOMUXD_FLEXCAN2_RX_mux_mode_MASK         (0x38000000U)
#define IOMUXD_FLEXCAN2_RX_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.FLEXCAN2.RX
 *  0b011..LSIO.GPIO4.IO01
 */
#define IOMUXD_FLEXCAN2_RX_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_RX_mux_mode_MASK)
#define IOMUXD_FLEXCAN2_RX_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_FLEXCAN2_RX_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_FLEXCAN2_RX_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN2_RX_update_pad_ctl_MASK)
#define IOMUXD_FLEXCAN2_RX_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_FLEXCAN2_RX_update_mux_mode_SHIFT (31U)
#define IOMUXD_FLEXCAN2_RX_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_RX_update_mux_mode_MASK)
/*! @} */

/*! @name FLEXCAN2_TX - FLEXCAN2_TX */
/*! @{ */
#define IOMUXD_FLEXCAN2_TX_PDRV_MASK             (0x1U)
#define IOMUXD_FLEXCAN2_TX_PDRV_SHIFT            (0U)
#define IOMUXD_FLEXCAN2_TX_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_PDRV_SHIFT)) & IOMUXD_FLEXCAN2_TX_PDRV_MASK)
#define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_MASK (0x1EU)
#define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_SHIFT (1U)
#define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_MASK)
#define IOMUXD_FLEXCAN2_TX_PULL_MASK             (0x60U)
#define IOMUXD_FLEXCAN2_TX_PULL_SHIFT            (5U)
#define IOMUXD_FLEXCAN2_TX_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_PULL_SHIFT)) & IOMUXD_FLEXCAN2_TX_PULL_MASK)
#define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_SHIFT (7U)
#define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_MASK)
#define IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_MASK)
#define IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_FLEXCAN2_TX_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_MASK)
#define IOMUXD_FLEXCAN2_TX_lp_config_MASK        (0x1800000U)
#define IOMUXD_FLEXCAN2_TX_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_FLEXCAN2_TX_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_lp_config_SHIFT)) & IOMUXD_FLEXCAN2_TX_lp_config_MASK)
#define IOMUXD_FLEXCAN2_TX_sw_config_MASK        (0x6000000U)
#define IOMUXD_FLEXCAN2_TX_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_FLEXCAN2_TX_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_sw_config_SHIFT)) & IOMUXD_FLEXCAN2_TX_sw_config_MASK)
#define IOMUXD_FLEXCAN2_TX_mux_mode_MASK         (0x38000000U)
#define IOMUXD_FLEXCAN2_TX_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.FLEXCAN2.TX
 *  0b011..LSIO.GPIO4.IO02
 */
#define IOMUXD_FLEXCAN2_TX_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_TX_mux_mode_MASK)
#define IOMUXD_FLEXCAN2_TX_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_FLEXCAN2_TX_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_FLEXCAN2_TX_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN2_TX_update_pad_ctl_MASK)
#define IOMUXD_FLEXCAN2_TX_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_FLEXCAN2_TX_update_mux_mode_SHIFT (31U)
#define IOMUXD_FLEXCAN2_TX_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_TX_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_update_mux_mode_MASK)
/*! @} */

/*! @name USB_SS3_TC0 - USB_SS3_TC0 */
/*! @{ */
#define IOMUXD_USB_SS3_TC0_DSE_MASK              (0x3U)
#define IOMUXD_USB_SS3_TC0_DSE_SHIFT             (0U)
#define IOMUXD_USB_SS3_TC0_DSE(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_DSE_SHIFT)) & IOMUXD_USB_SS3_TC0_DSE_MASK)
#define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_MASK (0x1CU)
#define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_SHIFT (2U)
#define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_MASK)
#define IOMUXD_USB_SS3_TC0_PULL_MASK             (0x60U)
#define IOMUXD_USB_SS3_TC0_PULL_SHIFT            (5U)
#define IOMUXD_USB_SS3_TC0_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_PULL_SHIFT)) & IOMUXD_USB_SS3_TC0_PULL_MASK)
#define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_SHIFT (7U)
#define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_MASK)
#define IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USB_SS3_TC0_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_MASK)
#define IOMUXD_USB_SS3_TC0_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_USB_SS3_TC0_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_USB_SS3_TC0_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC0_WAKEUP_MASK_MASK)
#define IOMUXD_USB_SS3_TC0_lp_config_MASK        (0x1800000U)
#define IOMUXD_USB_SS3_TC0_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USB_SS3_TC0_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC0_lp_config_MASK)
#define IOMUXD_USB_SS3_TC0_sw_config_MASK        (0x6000000U)
#define IOMUXD_USB_SS3_TC0_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USB_SS3_TC0_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC0_sw_config_MASK)
#define IOMUXD_USB_SS3_TC0_mux_mode_MASK         (0x38000000U)
#define IOMUXD_USB_SS3_TC0_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.I2C1.SCL
 *  0b001..CONN.USB_OTG1.PWR
 *  0b011..LSIO.GPIO4.IO03
 */
#define IOMUXD_USB_SS3_TC0_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC0_mux_mode_MASK)
#define IOMUXD_USB_SS3_TC0_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_USB_SS3_TC0_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_USB_SS3_TC0_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC0_update_pad_ctl_MASK)
#define IOMUXD_USB_SS3_TC0_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_USB_SS3_TC0_update_mux_mode_SHIFT (31U)
#define IOMUXD_USB_SS3_TC0_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC0_update_mux_mode_MASK)
/*! @} */

/*! @name USB_SS3_TC1 - USB_SS3_TC1 */
/*! @{ */
#define IOMUXD_USB_SS3_TC1_DSE_MASK              (0x3U)
#define IOMUXD_USB_SS3_TC1_DSE_SHIFT             (0U)
#define IOMUXD_USB_SS3_TC1_DSE(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_DSE_SHIFT)) & IOMUXD_USB_SS3_TC1_DSE_MASK)
#define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_MASK (0x1CU)
#define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_SHIFT (2U)
#define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_MASK)
#define IOMUXD_USB_SS3_TC1_PULL_MASK             (0x60U)
#define IOMUXD_USB_SS3_TC1_PULL_SHIFT            (5U)
#define IOMUXD_USB_SS3_TC1_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_PULL_SHIFT)) & IOMUXD_USB_SS3_TC1_PULL_MASK)
#define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_SHIFT (7U)
#define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_MASK)
#define IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USB_SS3_TC1_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_MASK)
#define IOMUXD_USB_SS3_TC1_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_USB_SS3_TC1_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_USB_SS3_TC1_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC1_WAKEUP_MASK_MASK)
#define IOMUXD_USB_SS3_TC1_lp_config_MASK        (0x1800000U)
#define IOMUXD_USB_SS3_TC1_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USB_SS3_TC1_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC1_lp_config_MASK)
#define IOMUXD_USB_SS3_TC1_sw_config_MASK        (0x6000000U)
#define IOMUXD_USB_SS3_TC1_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USB_SS3_TC1_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC1_sw_config_MASK)
#define IOMUXD_USB_SS3_TC1_mux_mode_MASK         (0x38000000U)
#define IOMUXD_USB_SS3_TC1_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.I2C1.SCL
 *  0b001..CONN.USB_OTG2.PWR
 *  0b011..LSIO.GPIO4.IO04
 */
#define IOMUXD_USB_SS3_TC1_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC1_mux_mode_MASK)
#define IOMUXD_USB_SS3_TC1_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_USB_SS3_TC1_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_USB_SS3_TC1_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC1_update_pad_ctl_MASK)
#define IOMUXD_USB_SS3_TC1_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_USB_SS3_TC1_update_mux_mode_SHIFT (31U)
#define IOMUXD_USB_SS3_TC1_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC1_update_mux_mode_MASK)
/*! @} */

/*! @name USB_SS3_TC2 - USB_SS3_TC2 */
/*! @{ */
#define IOMUXD_USB_SS3_TC2_DSE_MASK              (0x3U)
#define IOMUXD_USB_SS3_TC2_DSE_SHIFT             (0U)
#define IOMUXD_USB_SS3_TC2_DSE(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_DSE_SHIFT)) & IOMUXD_USB_SS3_TC2_DSE_MASK)
#define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_MASK (0x1CU)
#define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_SHIFT (2U)
#define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_MASK)
#define IOMUXD_USB_SS3_TC2_PULL_MASK             (0x60U)
#define IOMUXD_USB_SS3_TC2_PULL_SHIFT            (5U)
#define IOMUXD_USB_SS3_TC2_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_PULL_SHIFT)) & IOMUXD_USB_SS3_TC2_PULL_MASK)
#define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_SHIFT (7U)
#define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_MASK)
#define IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USB_SS3_TC2_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_MASK)
#define IOMUXD_USB_SS3_TC2_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_USB_SS3_TC2_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_USB_SS3_TC2_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC2_WAKEUP_MASK_MASK)
#define IOMUXD_USB_SS3_TC2_lp_config_MASK        (0x1800000U)
#define IOMUXD_USB_SS3_TC2_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USB_SS3_TC2_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC2_lp_config_MASK)
#define IOMUXD_USB_SS3_TC2_sw_config_MASK        (0x6000000U)
#define IOMUXD_USB_SS3_TC2_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USB_SS3_TC2_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC2_sw_config_MASK)
#define IOMUXD_USB_SS3_TC2_mux_mode_MASK         (0x38000000U)
#define IOMUXD_USB_SS3_TC2_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.I2C1.SDA
 *  0b001..CONN.USB_OTG1.OC
 *  0b011..LSIO.GPIO4.IO05
 */
#define IOMUXD_USB_SS3_TC2_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC2_mux_mode_MASK)
#define IOMUXD_USB_SS3_TC2_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_USB_SS3_TC2_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_USB_SS3_TC2_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC2_update_pad_ctl_MASK)
#define IOMUXD_USB_SS3_TC2_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_USB_SS3_TC2_update_mux_mode_SHIFT (31U)
#define IOMUXD_USB_SS3_TC2_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC2_update_mux_mode_MASK)
/*! @} */

/*! @name USB_SS3_TC3 - USB_SS3_TC3 */
/*! @{ */
#define IOMUXD_USB_SS3_TC3_DSE_MASK              (0x3U)
#define IOMUXD_USB_SS3_TC3_DSE_SHIFT             (0U)
#define IOMUXD_USB_SS3_TC3_DSE(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_DSE_SHIFT)) & IOMUXD_USB_SS3_TC3_DSE_MASK)
#define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_MASK (0x1CU)
#define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_SHIFT (2U)
#define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_MASK)
#define IOMUXD_USB_SS3_TC3_PULL_MASK             (0x60U)
#define IOMUXD_USB_SS3_TC3_PULL_SHIFT            (5U)
#define IOMUXD_USB_SS3_TC3_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_PULL_SHIFT)) & IOMUXD_USB_SS3_TC3_PULL_MASK)
#define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_SHIFT (7U)
#define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_MASK)
#define IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USB_SS3_TC3_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_MASK)
#define IOMUXD_USB_SS3_TC3_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_USB_SS3_TC3_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_USB_SS3_TC3_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC3_WAKEUP_MASK_MASK)
#define IOMUXD_USB_SS3_TC3_lp_config_MASK        (0x1800000U)
#define IOMUXD_USB_SS3_TC3_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USB_SS3_TC3_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC3_lp_config_MASK)
#define IOMUXD_USB_SS3_TC3_sw_config_MASK        (0x6000000U)
#define IOMUXD_USB_SS3_TC3_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USB_SS3_TC3_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC3_sw_config_MASK)
#define IOMUXD_USB_SS3_TC3_mux_mode_MASK         (0x38000000U)
#define IOMUXD_USB_SS3_TC3_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..DMA.I2C1.SDA
 *  0b001..CONN.USB_OTG2.OC
 *  0b011..LSIO.GPIO4.IO06
 */
#define IOMUXD_USB_SS3_TC3_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC3_mux_mode_MASK)
#define IOMUXD_USB_SS3_TC3_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_USB_SS3_TC3_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_USB_SS3_TC3_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC3_update_pad_ctl_MASK)
#define IOMUXD_USB_SS3_TC3_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_USB_SS3_TC3_update_mux_mode_SHIFT (31U)
#define IOMUXD_USB_SS3_TC3_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC3_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_3V3_USB3IO - IOMUXD_COMP_CTL_GPIO_3V3_USB3IO */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_MASK (0x7FFFFFU)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_2_0 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_2_0_MLB_SIG_MASK     (0x1U)
#define IOMUXD_IOMUXD_GROUP_2_0_MLB_SIG_SHIFT    (0U)
#define IOMUXD_IOMUXD_GROUP_2_0_MLB_SIG(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_MLB_SIG_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_MLB_SIG_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_MLB_CLK_MASK     (0x2U)
#define IOMUXD_IOMUXD_GROUP_2_0_MLB_CLK_SHIFT    (1U)
#define IOMUXD_IOMUXD_GROUP_2_0_MLB_CLK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_MLB_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_MLB_CLK_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_MLB_DATA_MASK    (0x4U)
#define IOMUXD_IOMUXD_GROUP_2_0_MLB_DATA_SHIFT   (2U)
#define IOMUXD_IOMUXD_GROUP_2_0_MLB_DATA(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_MLB_DATA_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_MLB_DATA_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_3_3_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_3_3_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_3_3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_3_3_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_3_3_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN0_RX_MASK (0x10U)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN0_RX_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN0_RX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN0_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN0_RX_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN0_TX_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN0_TX_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN0_TX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN0_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN0_TX_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN1_RX_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN1_RX_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN1_RX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN1_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN1_RX_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN1_TX_MASK (0x80U)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN1_TX_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN1_TX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN1_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN1_TX_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN2_RX_MASK (0x100U)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN2_RX_SHIFT (8U)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN2_RX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN2_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN2_RX_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN2_TX_MASK (0x200U)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN2_TX_SHIFT (9U)
#define IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN2_TX(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN2_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_FLEXCAN2_TX_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_10_10_MASK (0x400U)
#define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_10_10_SHIFT (10U)
#define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_10_10_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_10_10_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC0_MASK (0x800U)
#define IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC0_SHIFT (11U)
#define IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC0(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC0_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC1_MASK (0x1000U)
#define IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC1_SHIFT (12U)
#define IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC1(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC1_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC2_MASK (0x2000U)
#define IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC2_SHIFT (13U)
#define IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC2(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC2_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC2_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC3_MASK (0x4000U)
#define IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC3_SHIFT (14U)
#define IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC3(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC3_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_USB_SS3_TC3_MASK)
#define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_MASK (0xFFFF8000U)
#define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_SHIFT (15U)
#define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_MASK)
/*! @} */

/*! @name USDHC1_RESET_B - USDHC1_RESET_B */
/*! @{ */
#define IOMUXD_USDHC1_RESET_B_PDRV_MASK          (0x1U)
#define IOMUXD_USDHC1_RESET_B_PDRV_SHIFT         (0U)
#define IOMUXD_USDHC1_RESET_B_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_PDRV_SHIFT)) & IOMUXD_USDHC1_RESET_B_PDRV_MASK)
#define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_MASK)
#define IOMUXD_USDHC1_RESET_B_PULL_MASK          (0x60U)
#define IOMUXD_USDHC1_RESET_B_PULL_SHIFT         (5U)
#define IOMUXD_USDHC1_RESET_B_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_PULL_SHIFT)) & IOMUXD_USDHC1_RESET_B_PULL_MASK)
#define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_MASK)
#define IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_USDHC1_RESET_B_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC1_RESET_B_lp_config_MASK     (0x1800000U)
#define IOMUXD_USDHC1_RESET_B_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC1_RESET_B_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_lp_config_SHIFT)) & IOMUXD_USDHC1_RESET_B_lp_config_MASK)
#define IOMUXD_USDHC1_RESET_B_sw_config_MASK     (0x6000000U)
#define IOMUXD_USDHC1_RESET_B_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC1_RESET_B_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_sw_config_SHIFT)) & IOMUXD_USDHC1_RESET_B_sw_config_MASK)
#define IOMUXD_USDHC1_RESET_B_mux_mode_MASK      (0x38000000U)
#define IOMUXD_USDHC1_RESET_B_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC1.RESET_B
 *  0b011..LSIO.GPIO4.IO07
 */
#define IOMUXD_USDHC1_RESET_B_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_mux_mode_SHIFT)) & IOMUXD_USDHC1_RESET_B_mux_mode_MASK)
#define IOMUXD_USDHC1_RESET_B_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_USDHC1_RESET_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC1_RESET_B_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_RESET_B_update_pad_ctl_MASK)
#define IOMUXD_USDHC1_RESET_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC1_RESET_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC1_RESET_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_RESET_B_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC1_VSELECT - USDHC1_VSELECT */
/*! @{ */
#define IOMUXD_USDHC1_VSELECT_PDRV_MASK          (0x1U)
#define IOMUXD_USDHC1_VSELECT_PDRV_SHIFT         (0U)
#define IOMUXD_USDHC1_VSELECT_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_PDRV_SHIFT)) & IOMUXD_USDHC1_VSELECT_PDRV_MASK)
#define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_MASK)
#define IOMUXD_USDHC1_VSELECT_PULL_MASK          (0x60U)
#define IOMUXD_USDHC1_VSELECT_PULL_SHIFT         (5U)
#define IOMUXD_USDHC1_VSELECT_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_PULL_SHIFT)) & IOMUXD_USDHC1_VSELECT_PULL_MASK)
#define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_MASK)
#define IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_USDHC1_VSELECT_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC1_VSELECT_lp_config_MASK     (0x1800000U)
#define IOMUXD_USDHC1_VSELECT_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC1_VSELECT_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_lp_config_SHIFT)) & IOMUXD_USDHC1_VSELECT_lp_config_MASK)
#define IOMUXD_USDHC1_VSELECT_sw_config_MASK     (0x6000000U)
#define IOMUXD_USDHC1_VSELECT_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC1_VSELECT_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_sw_config_SHIFT)) & IOMUXD_USDHC1_VSELECT_sw_config_MASK)
#define IOMUXD_USDHC1_VSELECT_mux_mode_MASK      (0x38000000U)
#define IOMUXD_USDHC1_VSELECT_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC1.VSELECT
 *  0b011..LSIO.GPIO4.IO08
 */
#define IOMUXD_USDHC1_VSELECT_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_mux_mode_SHIFT)) & IOMUXD_USDHC1_VSELECT_mux_mode_MASK)
#define IOMUXD_USDHC1_VSELECT_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_USDHC1_VSELECT_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC1_VSELECT_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_VSELECT_update_pad_ctl_MASK)
#define IOMUXD_USDHC1_VSELECT_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC1_VSELECT_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC1_VSELECT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_VSELECT_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC2_RESET_B - USDHC2_RESET_B */
/*! @{ */
#define IOMUXD_USDHC2_RESET_B_PDRV_MASK          (0x1U)
#define IOMUXD_USDHC2_RESET_B_PDRV_SHIFT         (0U)
#define IOMUXD_USDHC2_RESET_B_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_RESET_B_PDRV_SHIFT)) & IOMUXD_USDHC2_RESET_B_PDRV_MASK)
#define IOMUXD_USDHC2_RESET_B_USDHC2_RESET_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC2_RESET_B_USDHC2_RESET_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC2_RESET_B_USDHC2_RESET_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_RESET_B_USDHC2_RESET_B_reserved_1_4_SHIFT)) & IOMUXD_USDHC2_RESET_B_USDHC2_RESET_B_reserved_1_4_MASK)
#define IOMUXD_USDHC2_RESET_B_PULL_MASK          (0x60U)
#define IOMUXD_USDHC2_RESET_B_PULL_SHIFT         (5U)
#define IOMUXD_USDHC2_RESET_B_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_RESET_B_PULL_SHIFT)) & IOMUXD_USDHC2_RESET_B_PULL_MASK)
#define IOMUXD_USDHC2_RESET_B_USDHC2_RESET_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC2_RESET_B_USDHC2_RESET_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC2_RESET_B_USDHC2_RESET_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_RESET_B_USDHC2_RESET_B_reserved_7_18_SHIFT)) & IOMUXD_USDHC2_RESET_B_USDHC2_RESET_B_reserved_7_18_MASK)
#define IOMUXD_USDHC2_RESET_B_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_USDHC2_RESET_B_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC2_RESET_B_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_RESET_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC2_RESET_B_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC2_RESET_B_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_USDHC2_RESET_B_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_USDHC2_RESET_B_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_RESET_B_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC2_RESET_B_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC2_RESET_B_lp_config_MASK     (0x1800000U)
#define IOMUXD_USDHC2_RESET_B_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC2_RESET_B_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_RESET_B_lp_config_SHIFT)) & IOMUXD_USDHC2_RESET_B_lp_config_MASK)
#define IOMUXD_USDHC2_RESET_B_sw_config_MASK     (0x6000000U)
#define IOMUXD_USDHC2_RESET_B_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC2_RESET_B_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_RESET_B_sw_config_SHIFT)) & IOMUXD_USDHC2_RESET_B_sw_config_MASK)
#define IOMUXD_USDHC2_RESET_B_mux_mode_MASK      (0x38000000U)
#define IOMUXD_USDHC2_RESET_B_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC2.RESET_B
 *  0b011..LSIO.GPIO4.IO09
 */
#define IOMUXD_USDHC2_RESET_B_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_RESET_B_mux_mode_SHIFT)) & IOMUXD_USDHC2_RESET_B_mux_mode_MASK)
#define IOMUXD_USDHC2_RESET_B_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_USDHC2_RESET_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC2_RESET_B_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_RESET_B_update_pad_ctl_SHIFT)) & IOMUXD_USDHC2_RESET_B_update_pad_ctl_MASK)
#define IOMUXD_USDHC2_RESET_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC2_RESET_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC2_RESET_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_RESET_B_update_mux_mode_SHIFT)) & IOMUXD_USDHC2_RESET_B_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC2_VSELECT - USDHC2_VSELECT */
/*! @{ */
#define IOMUXD_USDHC2_VSELECT_PDRV_MASK          (0x1U)
#define IOMUXD_USDHC2_VSELECT_PDRV_SHIFT         (0U)
#define IOMUXD_USDHC2_VSELECT_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_VSELECT_PDRV_SHIFT)) & IOMUXD_USDHC2_VSELECT_PDRV_MASK)
#define IOMUXD_USDHC2_VSELECT_USDHC2_VSELECT_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC2_VSELECT_USDHC2_VSELECT_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC2_VSELECT_USDHC2_VSELECT_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_VSELECT_USDHC2_VSELECT_reserved_1_4_SHIFT)) & IOMUXD_USDHC2_VSELECT_USDHC2_VSELECT_reserved_1_4_MASK)
#define IOMUXD_USDHC2_VSELECT_PULL_MASK          (0x60U)
#define IOMUXD_USDHC2_VSELECT_PULL_SHIFT         (5U)
#define IOMUXD_USDHC2_VSELECT_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_VSELECT_PULL_SHIFT)) & IOMUXD_USDHC2_VSELECT_PULL_MASK)
#define IOMUXD_USDHC2_VSELECT_USDHC2_VSELECT_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC2_VSELECT_USDHC2_VSELECT_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC2_VSELECT_USDHC2_VSELECT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_VSELECT_USDHC2_VSELECT_reserved_7_18_SHIFT)) & IOMUXD_USDHC2_VSELECT_USDHC2_VSELECT_reserved_7_18_MASK)
#define IOMUXD_USDHC2_VSELECT_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_USDHC2_VSELECT_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC2_VSELECT_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_VSELECT_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC2_VSELECT_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC2_VSELECT_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_USDHC2_VSELECT_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_USDHC2_VSELECT_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_VSELECT_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC2_VSELECT_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC2_VSELECT_lp_config_MASK     (0x1800000U)
#define IOMUXD_USDHC2_VSELECT_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC2_VSELECT_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_VSELECT_lp_config_SHIFT)) & IOMUXD_USDHC2_VSELECT_lp_config_MASK)
#define IOMUXD_USDHC2_VSELECT_sw_config_MASK     (0x6000000U)
#define IOMUXD_USDHC2_VSELECT_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC2_VSELECT_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_VSELECT_sw_config_SHIFT)) & IOMUXD_USDHC2_VSELECT_sw_config_MASK)
#define IOMUXD_USDHC2_VSELECT_mux_mode_MASK      (0x38000000U)
#define IOMUXD_USDHC2_VSELECT_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC2.VSELECT
 *  0b011..LSIO.GPIO4.IO10
 */
#define IOMUXD_USDHC2_VSELECT_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_VSELECT_mux_mode_SHIFT)) & IOMUXD_USDHC2_VSELECT_mux_mode_MASK)
#define IOMUXD_USDHC2_VSELECT_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_USDHC2_VSELECT_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC2_VSELECT_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_VSELECT_update_pad_ctl_SHIFT)) & IOMUXD_USDHC2_VSELECT_update_pad_ctl_MASK)
#define IOMUXD_USDHC2_VSELECT_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC2_VSELECT_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC2_VSELECT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_VSELECT_update_mux_mode_SHIFT)) & IOMUXD_USDHC2_VSELECT_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC2_WP - USDHC2_WP */
/*! @{ */
#define IOMUXD_USDHC2_WP_PDRV_MASK               (0x1U)
#define IOMUXD_USDHC2_WP_PDRV_SHIFT              (0U)
#define IOMUXD_USDHC2_WP_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_WP_PDRV_SHIFT)) & IOMUXD_USDHC2_WP_PDRV_MASK)
#define IOMUXD_USDHC2_WP_USDHC2_WP_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC2_WP_USDHC2_WP_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC2_WP_USDHC2_WP_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_WP_USDHC2_WP_reserved_1_4_SHIFT)) & IOMUXD_USDHC2_WP_USDHC2_WP_reserved_1_4_MASK)
#define IOMUXD_USDHC2_WP_PULL_MASK               (0x60U)
#define IOMUXD_USDHC2_WP_PULL_SHIFT              (5U)
#define IOMUXD_USDHC2_WP_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_WP_PULL_SHIFT)) & IOMUXD_USDHC2_WP_PULL_MASK)
#define IOMUXD_USDHC2_WP_USDHC2_WP_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC2_WP_USDHC2_WP_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC2_WP_USDHC2_WP_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_WP_USDHC2_WP_reserved_7_18_SHIFT)) & IOMUXD_USDHC2_WP_USDHC2_WP_reserved_7_18_MASK)
#define IOMUXD_USDHC2_WP_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_USDHC2_WP_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC2_WP_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_WP_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC2_WP_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC2_WP_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_USDHC2_WP_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_USDHC2_WP_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_WP_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC2_WP_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC2_WP_lp_config_MASK          (0x1800000U)
#define IOMUXD_USDHC2_WP_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC2_WP_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_WP_lp_config_SHIFT)) & IOMUXD_USDHC2_WP_lp_config_MASK)
#define IOMUXD_USDHC2_WP_sw_config_MASK          (0x6000000U)
#define IOMUXD_USDHC2_WP_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC2_WP_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_WP_sw_config_SHIFT)) & IOMUXD_USDHC2_WP_sw_config_MASK)
#define IOMUXD_USDHC2_WP_mux_mode_MASK           (0x38000000U)
#define IOMUXD_USDHC2_WP_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC2.WP
 *  0b011..LSIO.GPIO4.IO11
 */
#define IOMUXD_USDHC2_WP_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_WP_mux_mode_SHIFT)) & IOMUXD_USDHC2_WP_mux_mode_MASK)
#define IOMUXD_USDHC2_WP_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_USDHC2_WP_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_USDHC2_WP_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_WP_update_pad_ctl_SHIFT)) & IOMUXD_USDHC2_WP_update_pad_ctl_MASK)
#define IOMUXD_USDHC2_WP_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_USDHC2_WP_update_mux_mode_SHIFT   (31U)
#define IOMUXD_USDHC2_WP_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_WP_update_mux_mode_SHIFT)) & IOMUXD_USDHC2_WP_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC2_CD_B - USDHC2_CD_B */
/*! @{ */
#define IOMUXD_USDHC2_CD_B_PDRV_MASK             (0x1U)
#define IOMUXD_USDHC2_CD_B_PDRV_SHIFT            (0U)
#define IOMUXD_USDHC2_CD_B_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CD_B_PDRV_SHIFT)) & IOMUXD_USDHC2_CD_B_PDRV_MASK)
#define IOMUXD_USDHC2_CD_B_USDHC2_CD_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC2_CD_B_USDHC2_CD_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC2_CD_B_USDHC2_CD_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CD_B_USDHC2_CD_B_reserved_1_4_SHIFT)) & IOMUXD_USDHC2_CD_B_USDHC2_CD_B_reserved_1_4_MASK)
#define IOMUXD_USDHC2_CD_B_PULL_MASK             (0x60U)
#define IOMUXD_USDHC2_CD_B_PULL_SHIFT            (5U)
#define IOMUXD_USDHC2_CD_B_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CD_B_PULL_SHIFT)) & IOMUXD_USDHC2_CD_B_PULL_MASK)
#define IOMUXD_USDHC2_CD_B_USDHC2_CD_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC2_CD_B_USDHC2_CD_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC2_CD_B_USDHC2_CD_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CD_B_USDHC2_CD_B_reserved_7_18_SHIFT)) & IOMUXD_USDHC2_CD_B_USDHC2_CD_B_reserved_7_18_MASK)
#define IOMUXD_USDHC2_CD_B_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_USDHC2_CD_B_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC2_CD_B_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CD_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC2_CD_B_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC2_CD_B_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_USDHC2_CD_B_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_USDHC2_CD_B_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CD_B_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC2_CD_B_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC2_CD_B_lp_config_MASK        (0x1800000U)
#define IOMUXD_USDHC2_CD_B_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC2_CD_B_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CD_B_lp_config_SHIFT)) & IOMUXD_USDHC2_CD_B_lp_config_MASK)
#define IOMUXD_USDHC2_CD_B_sw_config_MASK        (0x6000000U)
#define IOMUXD_USDHC2_CD_B_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC2_CD_B_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CD_B_sw_config_SHIFT)) & IOMUXD_USDHC2_CD_B_sw_config_MASK)
#define IOMUXD_USDHC2_CD_B_mux_mode_MASK         (0x38000000U)
#define IOMUXD_USDHC2_CD_B_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC2.CD_B
 *  0b011..LSIO.GPIO4.IO12
 */
#define IOMUXD_USDHC2_CD_B_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CD_B_mux_mode_SHIFT)) & IOMUXD_USDHC2_CD_B_mux_mode_MASK)
#define IOMUXD_USDHC2_CD_B_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_USDHC2_CD_B_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_USDHC2_CD_B_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CD_B_update_pad_ctl_SHIFT)) & IOMUXD_USDHC2_CD_B_update_pad_ctl_MASK)
#define IOMUXD_USDHC2_CD_B_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_USDHC2_CD_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC2_CD_B_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CD_B_update_mux_mode_SHIFT)) & IOMUXD_USDHC2_CD_B_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP - IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_MDIO - ENET0_MDIO */
/*! @{ */
#define IOMUXD_ENET0_MDIO_PDRV_MASK              (0x1U)
#define IOMUXD_ENET0_MDIO_PDRV_SHIFT             (0U)
#define IOMUXD_ENET0_MDIO_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_PDRV_SHIFT)) & IOMUXD_ENET0_MDIO_PDRV_MASK)
#define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_SHIFT)) & IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_MASK)
#define IOMUXD_ENET0_MDIO_PULL_MASK              (0x60U)
#define IOMUXD_ENET0_MDIO_PULL_SHIFT             (5U)
#define IOMUXD_ENET0_MDIO_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_PULL_SHIFT)) & IOMUXD_ENET0_MDIO_PULL_MASK)
#define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_SHIFT)) & IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_MASK)
#define IOMUXD_ENET0_MDIO_WAKEUP_CTRL_MASK       (0x380000U)
#define IOMUXD_ENET0_MDIO_WAKEUP_CTRL_SHIFT      (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_MDIO_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_MDIO_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_MDIO_WAKEUP_MASK_MASK       (0x400000U)
#define IOMUXD_ENET0_MDIO_WAKEUP_MASK_SHIFT      (22U)
#define IOMUXD_ENET0_MDIO_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_MDIO_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_MDIO_lp_config_MASK         (0x1800000U)
#define IOMUXD_ENET0_MDIO_lp_config_SHIFT        (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_MDIO_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_lp_config_SHIFT)) & IOMUXD_ENET0_MDIO_lp_config_MASK)
#define IOMUXD_ENET0_MDIO_sw_config_MASK         (0x6000000U)
#define IOMUXD_ENET0_MDIO_sw_config_SHIFT        (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_MDIO_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_sw_config_SHIFT)) & IOMUXD_ENET0_MDIO_sw_config_MASK)
#define IOMUXD_ENET0_MDIO_mux_mode_MASK          (0x38000000U)
#define IOMUXD_ENET0_MDIO_mux_mode_SHIFT         (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.MDIO
 *  0b001..DMA.I2C4.SDA
 *  0b011..LSIO.GPIO4.IO13
 */
#define IOMUXD_ENET0_MDIO_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_mux_mode_SHIFT)) & IOMUXD_ENET0_MDIO_mux_mode_MASK)
#define IOMUXD_ENET0_MDIO_update_pad_ctl_MASK    (0x40000000U)
#define IOMUXD_ENET0_MDIO_update_pad_ctl_SHIFT   (30U)
#define IOMUXD_ENET0_MDIO_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_MDIO_update_pad_ctl_MASK)
#define IOMUXD_ENET0_MDIO_update_mux_mode_MASK   (0x80000000U)
#define IOMUXD_ENET0_MDIO_update_mux_mode_SHIFT  (31U)
#define IOMUXD_ENET0_MDIO_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_update_mux_mode_SHIFT)) & IOMUXD_ENET0_MDIO_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_MDC - ENET0_MDC */
/*! @{ */
#define IOMUXD_ENET0_MDC_PDRV_MASK               (0x1U)
#define IOMUXD_ENET0_MDC_PDRV_SHIFT              (0U)
#define IOMUXD_ENET0_MDC_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_PDRV_SHIFT)) & IOMUXD_ENET0_MDC_PDRV_MASK)
#define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_SHIFT)) & IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_MASK)
#define IOMUXD_ENET0_MDC_PULL_MASK               (0x60U)
#define IOMUXD_ENET0_MDC_PULL_SHIFT              (5U)
#define IOMUXD_ENET0_MDC_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_PULL_SHIFT)) & IOMUXD_ENET0_MDC_PULL_MASK)
#define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_SHIFT)) & IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_MASK)
#define IOMUXD_ENET0_MDC_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_ENET0_MDC_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_MDC_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_MDC_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_MDC_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_ENET0_MDC_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_ENET0_MDC_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_MDC_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_MDC_lp_config_MASK          (0x1800000U)
#define IOMUXD_ENET0_MDC_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_MDC_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_lp_config_SHIFT)) & IOMUXD_ENET0_MDC_lp_config_MASK)
#define IOMUXD_ENET0_MDC_sw_config_MASK          (0x6000000U)
#define IOMUXD_ENET0_MDC_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_MDC_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_sw_config_SHIFT)) & IOMUXD_ENET0_MDC_sw_config_MASK)
#define IOMUXD_ENET0_MDC_mux_mode_MASK           (0x38000000U)
#define IOMUXD_ENET0_MDC_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.MDC
 *  0b001..DMA.I2C4.SCL
 *  0b011..LSIO.GPIO4.IO14
 */
#define IOMUXD_ENET0_MDC_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_mux_mode_SHIFT)) & IOMUXD_ENET0_MDC_mux_mode_MASK)
#define IOMUXD_ENET0_MDC_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_ENET0_MDC_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_ENET0_MDC_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_MDC_update_pad_ctl_MASK)
#define IOMUXD_ENET0_MDC_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_ENET0_MDC_update_mux_mode_SHIFT   (31U)
#define IOMUXD_ENET0_MDC_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_update_mux_mode_SHIFT)) & IOMUXD_ENET0_MDC_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_REFCLK_125M_25M - ENET0_REFCLK_125M_25M */
/*! @{ */
#define IOMUXD_ENET0_REFCLK_125M_25M_PDRV_MASK   (0x1U)
#define IOMUXD_ENET0_REFCLK_125M_25M_PDRV_SHIFT  (0U)
#define IOMUXD_ENET0_REFCLK_125M_25M_PDRV(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_PDRV_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_PDRV_MASK)
#define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_MASK)
#define IOMUXD_ENET0_REFCLK_125M_25M_PULL_MASK   (0x60U)
#define IOMUXD_ENET0_REFCLK_125M_25M_PULL_SHIFT  (5U)
#define IOMUXD_ENET0_REFCLK_125M_25M_PULL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_PULL_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_PULL_MASK)
#define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_MASK)
#define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_REFCLK_125M_25M_lp_config_MASK (0x1800000U)
#define IOMUXD_ENET0_REFCLK_125M_25M_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_REFCLK_125M_25M_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_lp_config_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_lp_config_MASK)
#define IOMUXD_ENET0_REFCLK_125M_25M_sw_config_MASK (0x6000000U)
#define IOMUXD_ENET0_REFCLK_125M_25M_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_REFCLK_125M_25M_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_sw_config_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_sw_config_MASK)
#define IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_MASK (0x38000000U)
#define IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.REFCLK_125M_25M
 *  0b001..CONN.ENET0.PPS
 *  0b011..LSIO.GPIO4.IO15
 */
#define IOMUXD_ENET0_REFCLK_125M_25M_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_MASK)
#define IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_MASK)
#define IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_MASK)
/*! @} */

/*! @name ENET1_REFCLK_125M_25M - ENET1_REFCLK_125M_25M */
/*! @{ */
#define IOMUXD_ENET1_REFCLK_125M_25M_PDRV_MASK   (0x1U)
#define IOMUXD_ENET1_REFCLK_125M_25M_PDRV_SHIFT  (0U)
#define IOMUXD_ENET1_REFCLK_125M_25M_PDRV(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_REFCLK_125M_25M_PDRV_SHIFT)) & IOMUXD_ENET1_REFCLK_125M_25M_PDRV_MASK)
#define IOMUXD_ENET1_REFCLK_125M_25M_ENET1_REFCLK_125M_25M_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_REFCLK_125M_25M_ENET1_REFCLK_125M_25M_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_REFCLK_125M_25M_ENET1_REFCLK_125M_25M_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_REFCLK_125M_25M_ENET1_REFCLK_125M_25M_reserved_1_4_SHIFT)) & IOMUXD_ENET1_REFCLK_125M_25M_ENET1_REFCLK_125M_25M_reserved_1_4_MASK)
#define IOMUXD_ENET1_REFCLK_125M_25M_PULL_MASK   (0x60U)
#define IOMUXD_ENET1_REFCLK_125M_25M_PULL_SHIFT  (5U)
#define IOMUXD_ENET1_REFCLK_125M_25M_PULL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_REFCLK_125M_25M_PULL_SHIFT)) & IOMUXD_ENET1_REFCLK_125M_25M_PULL_MASK)
#define IOMUXD_ENET1_REFCLK_125M_25M_ENET1_REFCLK_125M_25M_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_REFCLK_125M_25M_ENET1_REFCLK_125M_25M_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_REFCLK_125M_25M_ENET1_REFCLK_125M_25M_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_REFCLK_125M_25M_ENET1_REFCLK_125M_25M_reserved_7_18_SHIFT)) & IOMUXD_ENET1_REFCLK_125M_25M_ENET1_REFCLK_125M_25M_reserved_7_18_MASK)
#define IOMUXD_ENET1_REFCLK_125M_25M_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET1_REFCLK_125M_25M_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_REFCLK_125M_25M_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_REFCLK_125M_25M_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_REFCLK_125M_25M_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_REFCLK_125M_25M_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET1_REFCLK_125M_25M_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET1_REFCLK_125M_25M_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_REFCLK_125M_25M_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_REFCLK_125M_25M_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_REFCLK_125M_25M_lp_config_MASK (0x1800000U)
#define IOMUXD_ENET1_REFCLK_125M_25M_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_REFCLK_125M_25M_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_REFCLK_125M_25M_lp_config_SHIFT)) & IOMUXD_ENET1_REFCLK_125M_25M_lp_config_MASK)
#define IOMUXD_ENET1_REFCLK_125M_25M_sw_config_MASK (0x6000000U)
#define IOMUXD_ENET1_REFCLK_125M_25M_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_REFCLK_125M_25M_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_REFCLK_125M_25M_sw_config_SHIFT)) & IOMUXD_ENET1_REFCLK_125M_25M_sw_config_MASK)
#define IOMUXD_ENET1_REFCLK_125M_25M_mux_mode_MASK (0x38000000U)
#define IOMUXD_ENET1_REFCLK_125M_25M_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.REFCLK_125M_25M
 *  0b001..CONN.ENET1.PPS
 *  0b011..LSIO.GPIO4.IO16
 */
#define IOMUXD_ENET1_REFCLK_125M_25M_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_REFCLK_125M_25M_mux_mode_SHIFT)) & IOMUXD_ENET1_REFCLK_125M_25M_mux_mode_MASK)
#define IOMUXD_ENET1_REFCLK_125M_25M_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET1_REFCLK_125M_25M_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET1_REFCLK_125M_25M_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_REFCLK_125M_25M_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_REFCLK_125M_25M_update_pad_ctl_MASK)
#define IOMUXD_ENET1_REFCLK_125M_25M_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET1_REFCLK_125M_25M_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET1_REFCLK_125M_25M_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_REFCLK_125M_25M_update_mux_mode_SHIFT)) & IOMUXD_ENET1_REFCLK_125M_25M_update_mux_mode_MASK)
/*! @} */

/*! @name ENET1_MDIO - ENET1_MDIO */
/*! @{ */
#define IOMUXD_ENET1_MDIO_PDRV_MASK              (0x1U)
#define IOMUXD_ENET1_MDIO_PDRV_SHIFT             (0U)
#define IOMUXD_ENET1_MDIO_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDIO_PDRV_SHIFT)) & IOMUXD_ENET1_MDIO_PDRV_MASK)
#define IOMUXD_ENET1_MDIO_ENET1_MDIO_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_MDIO_ENET1_MDIO_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_MDIO_ENET1_MDIO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDIO_ENET1_MDIO_reserved_1_4_SHIFT)) & IOMUXD_ENET1_MDIO_ENET1_MDIO_reserved_1_4_MASK)
#define IOMUXD_ENET1_MDIO_PULL_MASK              (0x60U)
#define IOMUXD_ENET1_MDIO_PULL_SHIFT             (5U)
#define IOMUXD_ENET1_MDIO_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDIO_PULL_SHIFT)) & IOMUXD_ENET1_MDIO_PULL_MASK)
#define IOMUXD_ENET1_MDIO_ENET1_MDIO_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_MDIO_ENET1_MDIO_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_MDIO_ENET1_MDIO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDIO_ENET1_MDIO_reserved_7_18_SHIFT)) & IOMUXD_ENET1_MDIO_ENET1_MDIO_reserved_7_18_MASK)
#define IOMUXD_ENET1_MDIO_WAKEUP_CTRL_MASK       (0x380000U)
#define IOMUXD_ENET1_MDIO_WAKEUP_CTRL_SHIFT      (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_MDIO_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDIO_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_MDIO_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_MDIO_WAKEUP_MASK_MASK       (0x400000U)
#define IOMUXD_ENET1_MDIO_WAKEUP_MASK_SHIFT      (22U)
#define IOMUXD_ENET1_MDIO_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDIO_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_MDIO_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_MDIO_lp_config_MASK         (0x1800000U)
#define IOMUXD_ENET1_MDIO_lp_config_SHIFT        (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_MDIO_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDIO_lp_config_SHIFT)) & IOMUXD_ENET1_MDIO_lp_config_MASK)
#define IOMUXD_ENET1_MDIO_sw_config_MASK         (0x6000000U)
#define IOMUXD_ENET1_MDIO_sw_config_SHIFT        (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_MDIO_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDIO_sw_config_SHIFT)) & IOMUXD_ENET1_MDIO_sw_config_MASK)
#define IOMUXD_ENET1_MDIO_mux_mode_MASK          (0x38000000U)
#define IOMUXD_ENET1_MDIO_mux_mode_SHIFT         (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.MDIO
 *  0b001..DMA.I2C4.SDA
 *  0b011..LSIO.GPIO4.IO17
 */
#define IOMUXD_ENET1_MDIO_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDIO_mux_mode_SHIFT)) & IOMUXD_ENET1_MDIO_mux_mode_MASK)
#define IOMUXD_ENET1_MDIO_update_pad_ctl_MASK    (0x40000000U)
#define IOMUXD_ENET1_MDIO_update_pad_ctl_SHIFT   (30U)
#define IOMUXD_ENET1_MDIO_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDIO_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_MDIO_update_pad_ctl_MASK)
#define IOMUXD_ENET1_MDIO_update_mux_mode_MASK   (0x80000000U)
#define IOMUXD_ENET1_MDIO_update_mux_mode_SHIFT  (31U)
#define IOMUXD_ENET1_MDIO_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDIO_update_mux_mode_SHIFT)) & IOMUXD_ENET1_MDIO_update_mux_mode_MASK)
/*! @} */

/*! @name ENET1_MDC - ENET1_MDC */
/*! @{ */
#define IOMUXD_ENET1_MDC_PDRV_MASK               (0x1U)
#define IOMUXD_ENET1_MDC_PDRV_SHIFT              (0U)
#define IOMUXD_ENET1_MDC_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDC_PDRV_SHIFT)) & IOMUXD_ENET1_MDC_PDRV_MASK)
#define IOMUXD_ENET1_MDC_ENET1_MDC_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_MDC_ENET1_MDC_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_MDC_ENET1_MDC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDC_ENET1_MDC_reserved_1_4_SHIFT)) & IOMUXD_ENET1_MDC_ENET1_MDC_reserved_1_4_MASK)
#define IOMUXD_ENET1_MDC_PULL_MASK               (0x60U)
#define IOMUXD_ENET1_MDC_PULL_SHIFT              (5U)
#define IOMUXD_ENET1_MDC_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDC_PULL_SHIFT)) & IOMUXD_ENET1_MDC_PULL_MASK)
#define IOMUXD_ENET1_MDC_ENET1_MDC_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_MDC_ENET1_MDC_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_MDC_ENET1_MDC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDC_ENET1_MDC_reserved_7_18_SHIFT)) & IOMUXD_ENET1_MDC_ENET1_MDC_reserved_7_18_MASK)
#define IOMUXD_ENET1_MDC_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_ENET1_MDC_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_MDC_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_MDC_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_MDC_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_ENET1_MDC_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_ENET1_MDC_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_MDC_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_MDC_lp_config_MASK          (0x1800000U)
#define IOMUXD_ENET1_MDC_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_MDC_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDC_lp_config_SHIFT)) & IOMUXD_ENET1_MDC_lp_config_MASK)
#define IOMUXD_ENET1_MDC_sw_config_MASK          (0x6000000U)
#define IOMUXD_ENET1_MDC_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_MDC_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDC_sw_config_SHIFT)) & IOMUXD_ENET1_MDC_sw_config_MASK)
#define IOMUXD_ENET1_MDC_mux_mode_MASK           (0x38000000U)
#define IOMUXD_ENET1_MDC_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.MDC
 *  0b001..DMA.I2C4.SCL
 *  0b011..LSIO.GPIO4.IO18
 */
#define IOMUXD_ENET1_MDC_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDC_mux_mode_SHIFT)) & IOMUXD_ENET1_MDC_mux_mode_MASK)
#define IOMUXD_ENET1_MDC_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_ENET1_MDC_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_ENET1_MDC_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDC_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_MDC_update_pad_ctl_MASK)
#define IOMUXD_ENET1_MDC_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_ENET1_MDC_update_mux_mode_SHIFT   (31U)
#define IOMUXD_ENET1_MDC_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_MDC_update_mux_mode_SHIFT)) & IOMUXD_ENET1_MDC_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI1A_SS0_B - QSPI1A_SS0_B */
/*! @{ */
#define IOMUXD_QSPI1A_SS0_B_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI1A_SS0_B_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI1A_SS0_B_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS0_B_PDRV_SHIFT)) & IOMUXD_QSPI1A_SS0_B_PDRV_MASK)
#define IOMUXD_QSPI1A_SS0_B_QSPI1A_SS0_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI1A_SS0_B_QSPI1A_SS0_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI1A_SS0_B_QSPI1A_SS0_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS0_B_QSPI1A_SS0_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI1A_SS0_B_QSPI1A_SS0_B_reserved_1_4_MASK)
#define IOMUXD_QSPI1A_SS0_B_PULL_MASK            (0x60U)
#define IOMUXD_QSPI1A_SS0_B_PULL_SHIFT           (5U)
#define IOMUXD_QSPI1A_SS0_B_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS0_B_PULL_SHIFT)) & IOMUXD_QSPI1A_SS0_B_PULL_MASK)
#define IOMUXD_QSPI1A_SS0_B_QSPI1A_SS0_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI1A_SS0_B_QSPI1A_SS0_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI1A_SS0_B_QSPI1A_SS0_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS0_B_QSPI1A_SS0_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI1A_SS0_B_QSPI1A_SS0_B_reserved_7_18_MASK)
#define IOMUXD_QSPI1A_SS0_B_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI1A_SS0_B_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI1A_SS0_B_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS0_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI1A_SS0_B_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI1A_SS0_B_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI1A_SS0_B_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI1A_SS0_B_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS0_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI1A_SS0_B_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI1A_SS0_B_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI1A_SS0_B_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI1A_SS0_B_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS0_B_lp_config_SHIFT)) & IOMUXD_QSPI1A_SS0_B_lp_config_MASK)
#define IOMUXD_QSPI1A_SS0_B_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI1A_SS0_B_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI1A_SS0_B_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS0_B_sw_config_SHIFT)) & IOMUXD_QSPI1A_SS0_B_sw_config_MASK)
#define IOMUXD_QSPI1A_SS0_B_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI1A_SS0_B_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI1A.SS0_B
 *  0b011..LSIO.GPIO4.IO19
 */
#define IOMUXD_QSPI1A_SS0_B_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS0_B_mux_mode_SHIFT)) & IOMUXD_QSPI1A_SS0_B_mux_mode_MASK)
#define IOMUXD_QSPI1A_SS0_B_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI1A_SS0_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI1A_SS0_B_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS0_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI1A_SS0_B_update_pad_ctl_MASK)
#define IOMUXD_QSPI1A_SS0_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI1A_SS0_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI1A_SS0_B_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS0_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI1A_SS0_B_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_2_1 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC1_RESET_B_MASK (0x1U)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC1_RESET_B_SHIFT (0U)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC1_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_USDHC1_RESET_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_USDHC1_RESET_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC1_VSELECT_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC1_VSELECT_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC1_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_USDHC1_VSELECT_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_USDHC1_VSELECT_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC2_RESET_B_MASK (0x4U)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC2_RESET_B_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC2_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_USDHC2_RESET_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_USDHC2_RESET_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC2_VSELECT_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC2_VSELECT_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC2_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_USDHC2_VSELECT_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_USDHC2_VSELECT_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC2_WP_MASK   (0x10U)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC2_WP_SHIFT  (4U)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC2_WP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_USDHC2_WP_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_USDHC2_WP_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC2_CD_B_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC2_CD_B_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_2_1_USDHC2_CD_B(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_USDHC2_CD_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_USDHC2_CD_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_6_6_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_6_6_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_6_6_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_6_6_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET0_MDIO_MASK  (0x80U)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET0_MDIO_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET0_MDIO(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ENET0_MDIO_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ENET0_MDIO_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET0_MDC_MASK   (0x100U)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET0_MDC_SHIFT  (8U)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET0_MDC(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ENET0_MDC_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ENET0_MDC_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET0_REFCLK_125M_25M_MASK (0x200U)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET0_REFCLK_125M_25M_SHIFT (9U)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET0_REFCLK_125M_25M(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ENET0_REFCLK_125M_25M_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ENET0_REFCLK_125M_25M_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET1_REFCLK_125M_25M_MASK (0x400U)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET1_REFCLK_125M_25M_SHIFT (10U)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET1_REFCLK_125M_25M(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ENET1_REFCLK_125M_25M_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ENET1_REFCLK_125M_25M_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET1_MDIO_MASK  (0x800U)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET1_MDIO_SHIFT (11U)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET1_MDIO(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ENET1_MDIO_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ENET1_MDIO_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET1_MDC_MASK   (0x1000U)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET1_MDC_SHIFT  (12U)
#define IOMUXD_IOMUXD_GROUP_2_1_ENET1_MDC(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ENET1_MDC_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ENET1_MDC_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_13_13_MASK (0x2000U)
#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_13_13_SHIFT (13U)
#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_13_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_13_13_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_13_13_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_QSPI1A_SS0_B_MASK (0x4000U)
#define IOMUXD_IOMUXD_GROUP_2_1_QSPI1A_SS0_B_SHIFT (14U)
#define IOMUXD_IOMUXD_GROUP_2_1_QSPI1A_SS0_B(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_QSPI1A_SS0_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_QSPI1A_SS0_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_MASK (0xFFFF8000U)
#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_SHIFT (15U)
#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_MASK)
/*! @} */

/*! @name QSPI1A_SS1_B - QSPI1A_SS1_B */
/*! @{ */
#define IOMUXD_QSPI1A_SS1_B_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI1A_SS1_B_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI1A_SS1_B_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_PDRV_SHIFT)) & IOMUXD_QSPI1A_SS1_B_PDRV_MASK)
#define IOMUXD_QSPI1A_SS1_B_QSPI1A_SS1_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI1A_SS1_B_QSPI1A_SS1_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI1A_SS1_B_QSPI1A_SS1_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_QSPI1A_SS1_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI1A_SS1_B_QSPI1A_SS1_B_reserved_1_4_MASK)
#define IOMUXD_QSPI1A_SS1_B_PULL_MASK            (0x60U)
#define IOMUXD_QSPI1A_SS1_B_PULL_SHIFT           (5U)
#define IOMUXD_QSPI1A_SS1_B_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_PULL_SHIFT)) & IOMUXD_QSPI1A_SS1_B_PULL_MASK)
#define IOMUXD_QSPI1A_SS1_B_QSPI1A_SS1_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI1A_SS1_B_QSPI1A_SS1_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI1A_SS1_B_QSPI1A_SS1_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_QSPI1A_SS1_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI1A_SS1_B_QSPI1A_SS1_B_reserved_7_18_MASK)
#define IOMUXD_QSPI1A_SS1_B_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI1A_SS1_B_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI1A_SS1_B_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI1A_SS1_B_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI1A_SS1_B_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI1A_SS1_B_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI1A_SS1_B_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI1A_SS1_B_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI1A_SS1_B_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI1A_SS1_B_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI1A_SS1_B_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_lp_config_SHIFT)) & IOMUXD_QSPI1A_SS1_B_lp_config_MASK)
#define IOMUXD_QSPI1A_SS1_B_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI1A_SS1_B_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI1A_SS1_B_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_sw_config_SHIFT)) & IOMUXD_QSPI1A_SS1_B_sw_config_MASK)
#define IOMUXD_QSPI1A_SS1_B_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI1A_SS1_B_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI1A.SS1_B
 *  0b001..LSIO.QSPI1A.SCLK2
 *  0b011..LSIO.GPIO4.IO20
 */
#define IOMUXD_QSPI1A_SS1_B_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_mux_mode_SHIFT)) & IOMUXD_QSPI1A_SS1_B_mux_mode_MASK)
#define IOMUXD_QSPI1A_SS1_B_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI1A_SS1_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI1A_SS1_B_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI1A_SS1_B_update_pad_ctl_MASK)
#define IOMUXD_QSPI1A_SS1_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI1A_SS1_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI1A_SS1_B_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI1A_SS1_B_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI1A_SCLK - QSPI1A_SCLK */
/*! @{ */
#define IOMUXD_QSPI1A_SCLK_PDRV_MASK             (0x1U)
#define IOMUXD_QSPI1A_SCLK_PDRV_SHIFT            (0U)
#define IOMUXD_QSPI1A_SCLK_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SCLK_PDRV_SHIFT)) & IOMUXD_QSPI1A_SCLK_PDRV_MASK)
#define IOMUXD_QSPI1A_SCLK_QSPI1A_SCLK_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI1A_SCLK_QSPI1A_SCLK_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI1A_SCLK_QSPI1A_SCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SCLK_QSPI1A_SCLK_reserved_1_4_SHIFT)) & IOMUXD_QSPI1A_SCLK_QSPI1A_SCLK_reserved_1_4_MASK)
#define IOMUXD_QSPI1A_SCLK_PULL_MASK             (0x60U)
#define IOMUXD_QSPI1A_SCLK_PULL_SHIFT            (5U)
#define IOMUXD_QSPI1A_SCLK_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SCLK_PULL_SHIFT)) & IOMUXD_QSPI1A_SCLK_PULL_MASK)
#define IOMUXD_QSPI1A_SCLK_QSPI1A_SCLK_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI1A_SCLK_QSPI1A_SCLK_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI1A_SCLK_QSPI1A_SCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SCLK_QSPI1A_SCLK_reserved_7_18_SHIFT)) & IOMUXD_QSPI1A_SCLK_QSPI1A_SCLK_reserved_7_18_MASK)
#define IOMUXD_QSPI1A_SCLK_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_QSPI1A_SCLK_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI1A_SCLK_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI1A_SCLK_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI1A_SCLK_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_QSPI1A_SCLK_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_QSPI1A_SCLK_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI1A_SCLK_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI1A_SCLK_lp_config_MASK        (0x1800000U)
#define IOMUXD_QSPI1A_SCLK_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI1A_SCLK_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SCLK_lp_config_SHIFT)) & IOMUXD_QSPI1A_SCLK_lp_config_MASK)
#define IOMUXD_QSPI1A_SCLK_sw_config_MASK        (0x6000000U)
#define IOMUXD_QSPI1A_SCLK_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI1A_SCLK_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SCLK_sw_config_SHIFT)) & IOMUXD_QSPI1A_SCLK_sw_config_MASK)
#define IOMUXD_QSPI1A_SCLK_mux_mode_MASK         (0x38000000U)
#define IOMUXD_QSPI1A_SCLK_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI1A.SCLK
 *  0b011..LSIO.GPIO4.IO21
 */
#define IOMUXD_QSPI1A_SCLK_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SCLK_mux_mode_SHIFT)) & IOMUXD_QSPI1A_SCLK_mux_mode_MASK)
#define IOMUXD_QSPI1A_SCLK_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_QSPI1A_SCLK_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_QSPI1A_SCLK_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SCLK_update_pad_ctl_SHIFT)) & IOMUXD_QSPI1A_SCLK_update_pad_ctl_MASK)
#define IOMUXD_QSPI1A_SCLK_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_QSPI1A_SCLK_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI1A_SCLK_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SCLK_update_mux_mode_SHIFT)) & IOMUXD_QSPI1A_SCLK_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI1A_DQS - QSPI1A_DQS */
/*! @{ */
#define IOMUXD_QSPI1A_DQS_PDRV_MASK              (0x1U)
#define IOMUXD_QSPI1A_DQS_PDRV_SHIFT             (0U)
#define IOMUXD_QSPI1A_DQS_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_PDRV_SHIFT)) & IOMUXD_QSPI1A_DQS_PDRV_MASK)
#define IOMUXD_QSPI1A_DQS_QSPI1A_DQS_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI1A_DQS_QSPI1A_DQS_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI1A_DQS_QSPI1A_DQS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_QSPI1A_DQS_reserved_1_4_SHIFT)) & IOMUXD_QSPI1A_DQS_QSPI1A_DQS_reserved_1_4_MASK)
#define IOMUXD_QSPI1A_DQS_PULL_MASK              (0x60U)
#define IOMUXD_QSPI1A_DQS_PULL_SHIFT             (5U)
#define IOMUXD_QSPI1A_DQS_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_PULL_SHIFT)) & IOMUXD_QSPI1A_DQS_PULL_MASK)
#define IOMUXD_QSPI1A_DQS_QSPI1A_DQS_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI1A_DQS_QSPI1A_DQS_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI1A_DQS_QSPI1A_DQS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_QSPI1A_DQS_reserved_7_18_SHIFT)) & IOMUXD_QSPI1A_DQS_QSPI1A_DQS_reserved_7_18_MASK)
#define IOMUXD_QSPI1A_DQS_WAKEUP_CTRL_MASK       (0x380000U)
#define IOMUXD_QSPI1A_DQS_WAKEUP_CTRL_SHIFT      (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI1A_DQS_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI1A_DQS_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI1A_DQS_WAKEUP_MASK_MASK       (0x400000U)
#define IOMUXD_QSPI1A_DQS_WAKEUP_MASK_SHIFT      (22U)
#define IOMUXD_QSPI1A_DQS_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI1A_DQS_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI1A_DQS_lp_config_MASK         (0x1800000U)
#define IOMUXD_QSPI1A_DQS_lp_config_SHIFT        (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI1A_DQS_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_lp_config_SHIFT)) & IOMUXD_QSPI1A_DQS_lp_config_MASK)
#define IOMUXD_QSPI1A_DQS_sw_config_MASK         (0x6000000U)
#define IOMUXD_QSPI1A_DQS_sw_config_SHIFT        (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI1A_DQS_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_sw_config_SHIFT)) & IOMUXD_QSPI1A_DQS_sw_config_MASK)
#define IOMUXD_QSPI1A_DQS_mux_mode_MASK          (0x38000000U)
#define IOMUXD_QSPI1A_DQS_mux_mode_SHIFT         (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI1A.DQS
 *  0b011..LSIO.GPIO4.IO22
 */
#define IOMUXD_QSPI1A_DQS_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_mux_mode_SHIFT)) & IOMUXD_QSPI1A_DQS_mux_mode_MASK)
#define IOMUXD_QSPI1A_DQS_update_pad_ctl_MASK    (0x40000000U)
#define IOMUXD_QSPI1A_DQS_update_pad_ctl_SHIFT   (30U)
#define IOMUXD_QSPI1A_DQS_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_update_pad_ctl_SHIFT)) & IOMUXD_QSPI1A_DQS_update_pad_ctl_MASK)
#define IOMUXD_QSPI1A_DQS_update_mux_mode_MASK   (0x80000000U)
#define IOMUXD_QSPI1A_DQS_update_mux_mode_SHIFT  (31U)
#define IOMUXD_QSPI1A_DQS_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_update_mux_mode_SHIFT)) & IOMUXD_QSPI1A_DQS_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI1A_DATA3 - QSPI1A_DATA3 */
/*! @{ */
#define IOMUXD_QSPI1A_DATA3_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI1A_DATA3_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI1A_DATA3_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA3_PDRV_SHIFT)) & IOMUXD_QSPI1A_DATA3_PDRV_MASK)
#define IOMUXD_QSPI1A_DATA3_QSPI1A_DATA3_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI1A_DATA3_QSPI1A_DATA3_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI1A_DATA3_QSPI1A_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA3_QSPI1A_DATA3_reserved_1_4_SHIFT)) & IOMUXD_QSPI1A_DATA3_QSPI1A_DATA3_reserved_1_4_MASK)
#define IOMUXD_QSPI1A_DATA3_PULL_MASK            (0x60U)
#define IOMUXD_QSPI1A_DATA3_PULL_SHIFT           (5U)
#define IOMUXD_QSPI1A_DATA3_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA3_PULL_SHIFT)) & IOMUXD_QSPI1A_DATA3_PULL_MASK)
#define IOMUXD_QSPI1A_DATA3_QSPI1A_DATA3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI1A_DATA3_QSPI1A_DATA3_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI1A_DATA3_QSPI1A_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA3_QSPI1A_DATA3_reserved_7_18_SHIFT)) & IOMUXD_QSPI1A_DATA3_QSPI1A_DATA3_reserved_7_18_MASK)
#define IOMUXD_QSPI1A_DATA3_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI1A_DATA3_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI1A_DATA3_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI1A_DATA3_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI1A_DATA3_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI1A_DATA3_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI1A_DATA3_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI1A_DATA3_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI1A_DATA3_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI1A_DATA3_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI1A_DATA3_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA3_lp_config_SHIFT)) & IOMUXD_QSPI1A_DATA3_lp_config_MASK)
#define IOMUXD_QSPI1A_DATA3_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI1A_DATA3_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI1A_DATA3_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA3_sw_config_SHIFT)) & IOMUXD_QSPI1A_DATA3_sw_config_MASK)
#define IOMUXD_QSPI1A_DATA3_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI1A_DATA3_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI1A.DATA3
 *  0b001..DMA.I2C1.SDA
 *  0b010..CONN.USB_OTG1.OC
 *  0b011..LSIO.GPIO4.IO23
 */
#define IOMUXD_QSPI1A_DATA3_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA3_mux_mode_SHIFT)) & IOMUXD_QSPI1A_DATA3_mux_mode_MASK)
#define IOMUXD_QSPI1A_DATA3_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI1A_DATA3_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI1A_DATA3_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_QSPI1A_DATA3_update_pad_ctl_MASK)
#define IOMUXD_QSPI1A_DATA3_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI1A_DATA3_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI1A_DATA3_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA3_update_mux_mode_SHIFT)) & IOMUXD_QSPI1A_DATA3_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI1A_DATA2 - QSPI1A_DATA2 */
/*! @{ */
#define IOMUXD_QSPI1A_DATA2_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI1A_DATA2_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI1A_DATA2_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA2_PDRV_SHIFT)) & IOMUXD_QSPI1A_DATA2_PDRV_MASK)
#define IOMUXD_QSPI1A_DATA2_QSPI1A_DATA2_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI1A_DATA2_QSPI1A_DATA2_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI1A_DATA2_QSPI1A_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA2_QSPI1A_DATA2_reserved_1_4_SHIFT)) & IOMUXD_QSPI1A_DATA2_QSPI1A_DATA2_reserved_1_4_MASK)
#define IOMUXD_QSPI1A_DATA2_PULL_MASK            (0x60U)
#define IOMUXD_QSPI1A_DATA2_PULL_SHIFT           (5U)
#define IOMUXD_QSPI1A_DATA2_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA2_PULL_SHIFT)) & IOMUXD_QSPI1A_DATA2_PULL_MASK)
#define IOMUXD_QSPI1A_DATA2_QSPI1A_DATA2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI1A_DATA2_QSPI1A_DATA2_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI1A_DATA2_QSPI1A_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA2_QSPI1A_DATA2_reserved_7_18_SHIFT)) & IOMUXD_QSPI1A_DATA2_QSPI1A_DATA2_reserved_7_18_MASK)
#define IOMUXD_QSPI1A_DATA2_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI1A_DATA2_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI1A_DATA2_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI1A_DATA2_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI1A_DATA2_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI1A_DATA2_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI1A_DATA2_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI1A_DATA2_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI1A_DATA2_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI1A_DATA2_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI1A_DATA2_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA2_lp_config_SHIFT)) & IOMUXD_QSPI1A_DATA2_lp_config_MASK)
#define IOMUXD_QSPI1A_DATA2_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI1A_DATA2_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI1A_DATA2_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA2_sw_config_SHIFT)) & IOMUXD_QSPI1A_DATA2_sw_config_MASK)
#define IOMUXD_QSPI1A_DATA2_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI1A_DATA2_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI1A.DATA2
 *  0b001..DMA.I2C1.SCL
 *  0b010..CONN.USB_OTG2.PWR
 *  0b011..LSIO.GPIO4.IO24
 */
#define IOMUXD_QSPI1A_DATA2_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA2_mux_mode_SHIFT)) & IOMUXD_QSPI1A_DATA2_mux_mode_MASK)
#define IOMUXD_QSPI1A_DATA2_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI1A_DATA2_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI1A_DATA2_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_QSPI1A_DATA2_update_pad_ctl_MASK)
#define IOMUXD_QSPI1A_DATA2_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI1A_DATA2_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI1A_DATA2_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA2_update_mux_mode_SHIFT)) & IOMUXD_QSPI1A_DATA2_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI1A_DATA1 - QSPI1A_DATA1 */
/*! @{ */
#define IOMUXD_QSPI1A_DATA1_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI1A_DATA1_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI1A_DATA1_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA1_PDRV_SHIFT)) & IOMUXD_QSPI1A_DATA1_PDRV_MASK)
#define IOMUXD_QSPI1A_DATA1_QSPI1A_DATA1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI1A_DATA1_QSPI1A_DATA1_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI1A_DATA1_QSPI1A_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA1_QSPI1A_DATA1_reserved_1_4_SHIFT)) & IOMUXD_QSPI1A_DATA1_QSPI1A_DATA1_reserved_1_4_MASK)
#define IOMUXD_QSPI1A_DATA1_PULL_MASK            (0x60U)
#define IOMUXD_QSPI1A_DATA1_PULL_SHIFT           (5U)
#define IOMUXD_QSPI1A_DATA1_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA1_PULL_SHIFT)) & IOMUXD_QSPI1A_DATA1_PULL_MASK)
#define IOMUXD_QSPI1A_DATA1_QSPI1A_DATA1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI1A_DATA1_QSPI1A_DATA1_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI1A_DATA1_QSPI1A_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA1_QSPI1A_DATA1_reserved_7_18_SHIFT)) & IOMUXD_QSPI1A_DATA1_QSPI1A_DATA1_reserved_7_18_MASK)
#define IOMUXD_QSPI1A_DATA1_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI1A_DATA1_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI1A_DATA1_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI1A_DATA1_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI1A_DATA1_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI1A_DATA1_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI1A_DATA1_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI1A_DATA1_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI1A_DATA1_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI1A_DATA1_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI1A_DATA1_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA1_lp_config_SHIFT)) & IOMUXD_QSPI1A_DATA1_lp_config_MASK)
#define IOMUXD_QSPI1A_DATA1_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI1A_DATA1_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI1A_DATA1_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA1_sw_config_SHIFT)) & IOMUXD_QSPI1A_DATA1_sw_config_MASK)
#define IOMUXD_QSPI1A_DATA1_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI1A_DATA1_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI1A.DATA1
 *  0b001..DMA.I2C1.SDA
 *  0b010..CONN.USB_OTG2.OC
 *  0b011..LSIO.GPIO4.IO25
 */
#define IOMUXD_QSPI1A_DATA1_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA1_mux_mode_SHIFT)) & IOMUXD_QSPI1A_DATA1_mux_mode_MASK)
#define IOMUXD_QSPI1A_DATA1_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI1A_DATA1_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI1A_DATA1_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_QSPI1A_DATA1_update_pad_ctl_MASK)
#define IOMUXD_QSPI1A_DATA1_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI1A_DATA1_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI1A_DATA1_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA1_update_mux_mode_SHIFT)) & IOMUXD_QSPI1A_DATA1_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI1A_DATA0 - QSPI1A_DATA0 */
/*! @{ */
#define IOMUXD_QSPI1A_DATA0_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI1A_DATA0_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI1A_DATA0_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA0_PDRV_SHIFT)) & IOMUXD_QSPI1A_DATA0_PDRV_MASK)
#define IOMUXD_QSPI1A_DATA0_QSPI1A_DATA0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI1A_DATA0_QSPI1A_DATA0_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI1A_DATA0_QSPI1A_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA0_QSPI1A_DATA0_reserved_1_4_SHIFT)) & IOMUXD_QSPI1A_DATA0_QSPI1A_DATA0_reserved_1_4_MASK)
#define IOMUXD_QSPI1A_DATA0_PULL_MASK            (0x60U)
#define IOMUXD_QSPI1A_DATA0_PULL_SHIFT           (5U)
#define IOMUXD_QSPI1A_DATA0_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA0_PULL_SHIFT)) & IOMUXD_QSPI1A_DATA0_PULL_MASK)
#define IOMUXD_QSPI1A_DATA0_QSPI1A_DATA0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI1A_DATA0_QSPI1A_DATA0_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI1A_DATA0_QSPI1A_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA0_QSPI1A_DATA0_reserved_7_18_SHIFT)) & IOMUXD_QSPI1A_DATA0_QSPI1A_DATA0_reserved_7_18_MASK)
#define IOMUXD_QSPI1A_DATA0_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI1A_DATA0_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI1A_DATA0_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI1A_DATA0_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI1A_DATA0_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI1A_DATA0_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI1A_DATA0_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI1A_DATA0_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI1A_DATA0_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI1A_DATA0_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI1A_DATA0_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA0_lp_config_SHIFT)) & IOMUXD_QSPI1A_DATA0_lp_config_MASK)
#define IOMUXD_QSPI1A_DATA0_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI1A_DATA0_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI1A_DATA0_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA0_sw_config_SHIFT)) & IOMUXD_QSPI1A_DATA0_sw_config_MASK)
#define IOMUXD_QSPI1A_DATA0_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI1A_DATA0_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI1A.DATA0
 *  0b011..LSIO.GPIO4.IO26
 */
#define IOMUXD_QSPI1A_DATA0_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA0_mux_mode_SHIFT)) & IOMUXD_QSPI1A_DATA0_mux_mode_MASK)
#define IOMUXD_QSPI1A_DATA0_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI1A_DATA0_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI1A_DATA0_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_QSPI1A_DATA0_update_pad_ctl_MASK)
#define IOMUXD_QSPI1A_DATA0_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI1A_DATA0_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI1A_DATA0_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DATA0_update_mux_mode_SHIFT)) & IOMUXD_QSPI1A_DATA0_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1 */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_2_2 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_SS1_B_MASK (0x1U)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_SS1_B_SHIFT (0U)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_SS1_B(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_SS1_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_SS1_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_SCLK_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_SCLK_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_SCLK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_SCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_SCLK_MASK)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DQS_MASK  (0x4U)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DQS_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DQS(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DQS_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DQS_MASK)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA3_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA3_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA3(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA3_MASK)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA2_MASK (0x10U)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA2_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA2(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA2_MASK)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA1_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA1_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA1(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA1_MASK)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA0_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA0_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA0(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_QSPI1A_DATA0_MASK)
#define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_7_31_MASK (0xFFFFFF80U)
#define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_7_31_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_7_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_7_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_7_31_MASK)
/*! @} */

/*! @name QSPI0A_DATA0 - QSPI0A_DATA0 */
/*! @{ */
#define IOMUXD_QSPI0A_DATA0_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI0A_DATA0_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI0A_DATA0_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA0_PDRV_MASK)
#define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_MASK)
#define IOMUXD_QSPI0A_DATA0_PULL_MASK            (0x60U)
#define IOMUXD_QSPI0A_DATA0_PULL_SHIFT           (5U)
#define IOMUXD_QSPI0A_DATA0_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA0_PULL_MASK)
#define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_MASK)
#define IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI0A_DATA0_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0A_DATA0_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI0A_DATA0_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0A_DATA0_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA0_lp_config_MASK)
#define IOMUXD_QSPI0A_DATA0_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI0A_DATA0_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0A_DATA0_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA0_sw_config_MASK)
#define IOMUXD_QSPI0A_DATA0_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI0A_DATA0_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0A.DATA0
 */
#define IOMUXD_QSPI0A_DATA0_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA0_mux_mode_MASK)
#define IOMUXD_QSPI0A_DATA0_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI0A_DATA0_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI0A_DATA0_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA0_update_pad_ctl_MASK)
#define IOMUXD_QSPI0A_DATA0_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI0A_DATA0_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI0A_DATA0_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA0_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI0A_DATA1 - QSPI0A_DATA1 */
/*! @{ */
#define IOMUXD_QSPI0A_DATA1_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI0A_DATA1_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI0A_DATA1_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA1_PDRV_MASK)
#define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_MASK)
#define IOMUXD_QSPI0A_DATA1_PULL_MASK            (0x60U)
#define IOMUXD_QSPI0A_DATA1_PULL_SHIFT           (5U)
#define IOMUXD_QSPI0A_DATA1_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA1_PULL_MASK)
#define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_MASK)
#define IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI0A_DATA1_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0A_DATA1_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI0A_DATA1_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0A_DATA1_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA1_lp_config_MASK)
#define IOMUXD_QSPI0A_DATA1_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI0A_DATA1_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0A_DATA1_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA1_sw_config_MASK)
#define IOMUXD_QSPI0A_DATA1_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI0A_DATA1_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0A.DATA1
 */
#define IOMUXD_QSPI0A_DATA1_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA1_mux_mode_MASK)
#define IOMUXD_QSPI0A_DATA1_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI0A_DATA1_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI0A_DATA1_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA1_update_pad_ctl_MASK)
#define IOMUXD_QSPI0A_DATA1_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI0A_DATA1_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI0A_DATA1_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA1_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI0A_DATA2 - QSPI0A_DATA2 */
/*! @{ */
#define IOMUXD_QSPI0A_DATA2_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI0A_DATA2_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI0A_DATA2_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA2_PDRV_MASK)
#define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_MASK)
#define IOMUXD_QSPI0A_DATA2_PULL_MASK            (0x60U)
#define IOMUXD_QSPI0A_DATA2_PULL_SHIFT           (5U)
#define IOMUXD_QSPI0A_DATA2_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA2_PULL_MASK)
#define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_MASK)
#define IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI0A_DATA2_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0A_DATA2_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI0A_DATA2_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0A_DATA2_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA2_lp_config_MASK)
#define IOMUXD_QSPI0A_DATA2_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI0A_DATA2_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0A_DATA2_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA2_sw_config_MASK)
#define IOMUXD_QSPI0A_DATA2_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI0A_DATA2_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0A.DATA2
 */
#define IOMUXD_QSPI0A_DATA2_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA2_mux_mode_MASK)
#define IOMUXD_QSPI0A_DATA2_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI0A_DATA2_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI0A_DATA2_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA2_update_pad_ctl_MASK)
#define IOMUXD_QSPI0A_DATA2_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI0A_DATA2_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI0A_DATA2_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA2_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI0A_DATA3 - QSPI0A_DATA3 */
/*! @{ */
#define IOMUXD_QSPI0A_DATA3_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI0A_DATA3_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI0A_DATA3_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA3_PDRV_MASK)
#define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_MASK)
#define IOMUXD_QSPI0A_DATA3_PULL_MASK            (0x60U)
#define IOMUXD_QSPI0A_DATA3_PULL_SHIFT           (5U)
#define IOMUXD_QSPI0A_DATA3_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA3_PULL_MASK)
#define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_MASK)
#define IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI0A_DATA3_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0A_DATA3_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI0A_DATA3_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0A_DATA3_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA3_lp_config_MASK)
#define IOMUXD_QSPI0A_DATA3_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI0A_DATA3_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0A_DATA3_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA3_sw_config_MASK)
#define IOMUXD_QSPI0A_DATA3_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI0A_DATA3_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0A.DATA3
 */
#define IOMUXD_QSPI0A_DATA3_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA3_mux_mode_MASK)
#define IOMUXD_QSPI0A_DATA3_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI0A_DATA3_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI0A_DATA3_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA3_update_pad_ctl_MASK)
#define IOMUXD_QSPI0A_DATA3_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI0A_DATA3_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI0A_DATA3_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA3_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI0A_DQS - QSPI0A_DQS */
/*! @{ */
#define IOMUXD_QSPI0A_DQS_PDRV_MASK              (0x1U)
#define IOMUXD_QSPI0A_DQS_PDRV_SHIFT             (0U)
#define IOMUXD_QSPI0A_DQS_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_PDRV_SHIFT)) & IOMUXD_QSPI0A_DQS_PDRV_MASK)
#define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_MASK)
#define IOMUXD_QSPI0A_DQS_PULL_MASK              (0x60U)
#define IOMUXD_QSPI0A_DQS_PULL_SHIFT             (5U)
#define IOMUXD_QSPI0A_DQS_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_PULL_SHIFT)) & IOMUXD_QSPI0A_DQS_PULL_MASK)
#define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_MASK)
#define IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_MASK       (0x380000U)
#define IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_SHIFT      (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0A_DQS_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0A_DQS_WAKEUP_MASK_MASK       (0x400000U)
#define IOMUXD_QSPI0A_DQS_WAKEUP_MASK_SHIFT      (22U)
#define IOMUXD_QSPI0A_DQS_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DQS_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0A_DQS_lp_config_MASK         (0x1800000U)
#define IOMUXD_QSPI0A_DQS_lp_config_SHIFT        (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0A_DQS_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_lp_config_SHIFT)) & IOMUXD_QSPI0A_DQS_lp_config_MASK)
#define IOMUXD_QSPI0A_DQS_sw_config_MASK         (0x6000000U)
#define IOMUXD_QSPI0A_DQS_sw_config_SHIFT        (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0A_DQS_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_sw_config_SHIFT)) & IOMUXD_QSPI0A_DQS_sw_config_MASK)
#define IOMUXD_QSPI0A_DQS_mux_mode_MASK          (0x38000000U)
#define IOMUXD_QSPI0A_DQS_mux_mode_SHIFT         (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0A.DQS
 */
#define IOMUXD_QSPI0A_DQS_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DQS_mux_mode_MASK)
#define IOMUXD_QSPI0A_DQS_update_pad_ctl_MASK    (0x40000000U)
#define IOMUXD_QSPI0A_DQS_update_pad_ctl_SHIFT   (30U)
#define IOMUXD_QSPI0A_DQS_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DQS_update_pad_ctl_MASK)
#define IOMUXD_QSPI0A_DQS_update_mux_mode_MASK   (0x80000000U)
#define IOMUXD_QSPI0A_DQS_update_mux_mode_SHIFT  (31U)
#define IOMUXD_QSPI0A_DQS_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DQS_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI0A_SS0_B - QSPI0A_SS0_B */
/*! @{ */
#define IOMUXD_QSPI0A_SS0_B_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI0A_SS0_B_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI0A_SS0_B_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_PDRV_SHIFT)) & IOMUXD_QSPI0A_SS0_B_PDRV_MASK)
#define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_MASK)
#define IOMUXD_QSPI0A_SS0_B_PULL_MASK            (0x60U)
#define IOMUXD_QSPI0A_SS0_B_PULL_SHIFT           (5U)
#define IOMUXD_QSPI0A_SS0_B_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_PULL_SHIFT)) & IOMUXD_QSPI0A_SS0_B_PULL_MASK)
#define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_MASK)
#define IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0A_SS0_B_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI0A_SS0_B_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0A_SS0_B_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_lp_config_SHIFT)) & IOMUXD_QSPI0A_SS0_B_lp_config_MASK)
#define IOMUXD_QSPI0A_SS0_B_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI0A_SS0_B_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0A_SS0_B_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_sw_config_SHIFT)) & IOMUXD_QSPI0A_SS0_B_sw_config_MASK)
#define IOMUXD_QSPI0A_SS0_B_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI0A_SS0_B_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0A.SS0_B
 */
#define IOMUXD_QSPI0A_SS0_B_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS0_B_mux_mode_MASK)
#define IOMUXD_QSPI0A_SS0_B_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI0A_SS0_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI0A_SS0_B_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_SS0_B_update_pad_ctl_MASK)
#define IOMUXD_QSPI0A_SS0_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI0A_SS0_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI0A_SS0_B_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS0_B_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI0A_SS1_B - QSPI0A_SS1_B */
/*! @{ */
#define IOMUXD_QSPI0A_SS1_B_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI0A_SS1_B_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI0A_SS1_B_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_PDRV_SHIFT)) & IOMUXD_QSPI0A_SS1_B_PDRV_MASK)
#define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_MASK)
#define IOMUXD_QSPI0A_SS1_B_PULL_MASK            (0x60U)
#define IOMUXD_QSPI0A_SS1_B_PULL_SHIFT           (5U)
#define IOMUXD_QSPI0A_SS1_B_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_PULL_SHIFT)) & IOMUXD_QSPI0A_SS1_B_PULL_MASK)
#define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_MASK)
#define IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0A_SS1_B_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI0A_SS1_B_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0A_SS1_B_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_lp_config_SHIFT)) & IOMUXD_QSPI0A_SS1_B_lp_config_MASK)
#define IOMUXD_QSPI0A_SS1_B_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI0A_SS1_B_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0A_SS1_B_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_sw_config_SHIFT)) & IOMUXD_QSPI0A_SS1_B_sw_config_MASK)
#define IOMUXD_QSPI0A_SS1_B_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI0A_SS1_B_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0A.SS1_B
 *  0b001..LSIO.QSPI0A.SCLK2
 */
#define IOMUXD_QSPI0A_SS1_B_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS1_B_mux_mode_MASK)
#define IOMUXD_QSPI0A_SS1_B_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI0A_SS1_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI0A_SS1_B_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_SS1_B_update_pad_ctl_MASK)
#define IOMUXD_QSPI0A_SS1_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI0A_SS1_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI0A_SS1_B_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS1_B_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI0A_SCLK - QSPI0A_SCLK */
/*! @{ */
#define IOMUXD_QSPI0A_SCLK_PDRV_MASK             (0x1U)
#define IOMUXD_QSPI0A_SCLK_PDRV_SHIFT            (0U)
#define IOMUXD_QSPI0A_SCLK_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_PDRV_SHIFT)) & IOMUXD_QSPI0A_SCLK_PDRV_MASK)
#define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_MASK)
#define IOMUXD_QSPI0A_SCLK_PULL_MASK             (0x60U)
#define IOMUXD_QSPI0A_SCLK_PULL_SHIFT            (5U)
#define IOMUXD_QSPI0A_SCLK_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_PULL_SHIFT)) & IOMUXD_QSPI0A_SCLK_PULL_MASK)
#define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_MASK)
#define IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_QSPI0A_SCLK_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0A_SCLK_lp_config_MASK        (0x1800000U)
#define IOMUXD_QSPI0A_SCLK_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0A_SCLK_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_lp_config_SHIFT)) & IOMUXD_QSPI0A_SCLK_lp_config_MASK)
#define IOMUXD_QSPI0A_SCLK_sw_config_MASK        (0x6000000U)
#define IOMUXD_QSPI0A_SCLK_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0A_SCLK_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_sw_config_SHIFT)) & IOMUXD_QSPI0A_SCLK_sw_config_MASK)
#define IOMUXD_QSPI0A_SCLK_mux_mode_MASK         (0x38000000U)
#define IOMUXD_QSPI0A_SCLK_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0A.SCLK
 */
#define IOMUXD_QSPI0A_SCLK_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SCLK_mux_mode_MASK)
#define IOMUXD_QSPI0A_SCLK_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_QSPI0A_SCLK_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_QSPI0A_SCLK_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_SCLK_update_pad_ctl_MASK)
#define IOMUXD_QSPI0A_SCLK_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_QSPI0A_SCLK_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI0A_SCLK_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SCLK_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI0B_SCLK - QSPI0B_SCLK */
/*! @{ */
#define IOMUXD_QSPI0B_SCLK_PDRV_MASK             (0x1U)
#define IOMUXD_QSPI0B_SCLK_PDRV_SHIFT            (0U)
#define IOMUXD_QSPI0B_SCLK_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_PDRV_SHIFT)) & IOMUXD_QSPI0B_SCLK_PDRV_MASK)
#define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_MASK)
#define IOMUXD_QSPI0B_SCLK_PULL_MASK             (0x60U)
#define IOMUXD_QSPI0B_SCLK_PULL_SHIFT            (5U)
#define IOMUXD_QSPI0B_SCLK_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_PULL_SHIFT)) & IOMUXD_QSPI0B_SCLK_PULL_MASK)
#define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_MASK)
#define IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_QSPI0B_SCLK_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0B_SCLK_lp_config_MASK        (0x1800000U)
#define IOMUXD_QSPI0B_SCLK_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0B_SCLK_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_lp_config_SHIFT)) & IOMUXD_QSPI0B_SCLK_lp_config_MASK)
#define IOMUXD_QSPI0B_SCLK_sw_config_MASK        (0x6000000U)
#define IOMUXD_QSPI0B_SCLK_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0B_SCLK_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_sw_config_SHIFT)) & IOMUXD_QSPI0B_SCLK_sw_config_MASK)
#define IOMUXD_QSPI0B_SCLK_mux_mode_MASK         (0x38000000U)
#define IOMUXD_QSPI0B_SCLK_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0B.SCLK
 */
#define IOMUXD_QSPI0B_SCLK_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SCLK_mux_mode_MASK)
#define IOMUXD_QSPI0B_SCLK_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_QSPI0B_SCLK_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_QSPI0B_SCLK_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_SCLK_update_pad_ctl_MASK)
#define IOMUXD_QSPI0B_SCLK_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_QSPI0B_SCLK_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI0B_SCLK_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SCLK_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI0B_DATA0 - QSPI0B_DATA0 */
/*! @{ */
#define IOMUXD_QSPI0B_DATA0_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI0B_DATA0_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI0B_DATA0_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA0_PDRV_MASK)
#define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_MASK)
#define IOMUXD_QSPI0B_DATA0_PULL_MASK            (0x60U)
#define IOMUXD_QSPI0B_DATA0_PULL_SHIFT           (5U)
#define IOMUXD_QSPI0B_DATA0_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA0_PULL_MASK)
#define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_MASK)
#define IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI0B_DATA0_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0B_DATA0_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI0B_DATA0_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0B_DATA0_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA0_lp_config_MASK)
#define IOMUXD_QSPI0B_DATA0_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI0B_DATA0_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0B_DATA0_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA0_sw_config_MASK)
#define IOMUXD_QSPI0B_DATA0_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI0B_DATA0_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0B.DATA0
 */
#define IOMUXD_QSPI0B_DATA0_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA0_mux_mode_MASK)
#define IOMUXD_QSPI0B_DATA0_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI0B_DATA0_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI0B_DATA0_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA0_update_pad_ctl_MASK)
#define IOMUXD_QSPI0B_DATA0_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI0B_DATA0_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI0B_DATA0_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA0_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI0B_DATA1 - QSPI0B_DATA1 */
/*! @{ */
#define IOMUXD_QSPI0B_DATA1_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI0B_DATA1_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI0B_DATA1_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA1_PDRV_MASK)
#define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_MASK)
#define IOMUXD_QSPI0B_DATA1_PULL_MASK            (0x60U)
#define IOMUXD_QSPI0B_DATA1_PULL_SHIFT           (5U)
#define IOMUXD_QSPI0B_DATA1_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA1_PULL_MASK)
#define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_MASK)
#define IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI0B_DATA1_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0B_DATA1_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI0B_DATA1_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0B_DATA1_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA1_lp_config_MASK)
#define IOMUXD_QSPI0B_DATA1_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI0B_DATA1_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0B_DATA1_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA1_sw_config_MASK)
#define IOMUXD_QSPI0B_DATA1_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI0B_DATA1_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0B.DATA1
 */
#define IOMUXD_QSPI0B_DATA1_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA1_mux_mode_MASK)
#define IOMUXD_QSPI0B_DATA1_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI0B_DATA1_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI0B_DATA1_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA1_update_pad_ctl_MASK)
#define IOMUXD_QSPI0B_DATA1_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI0B_DATA1_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI0B_DATA1_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA1_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI0B_DATA2 - QSPI0B_DATA2 */
/*! @{ */
#define IOMUXD_QSPI0B_DATA2_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI0B_DATA2_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI0B_DATA2_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA2_PDRV_MASK)
#define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_MASK)
#define IOMUXD_QSPI0B_DATA2_PULL_MASK            (0x60U)
#define IOMUXD_QSPI0B_DATA2_PULL_SHIFT           (5U)
#define IOMUXD_QSPI0B_DATA2_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA2_PULL_MASK)
#define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_MASK)
#define IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI0B_DATA2_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0B_DATA2_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI0B_DATA2_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0B_DATA2_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA2_lp_config_MASK)
#define IOMUXD_QSPI0B_DATA2_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI0B_DATA2_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0B_DATA2_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA2_sw_config_MASK)
#define IOMUXD_QSPI0B_DATA2_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI0B_DATA2_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0B.DATA2
 */
#define IOMUXD_QSPI0B_DATA2_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA2_mux_mode_MASK)
#define IOMUXD_QSPI0B_DATA2_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI0B_DATA2_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI0B_DATA2_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA2_update_pad_ctl_MASK)
#define IOMUXD_QSPI0B_DATA2_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI0B_DATA2_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI0B_DATA2_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA2_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI0B_DATA3 - QSPI0B_DATA3 */
/*! @{ */
#define IOMUXD_QSPI0B_DATA3_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI0B_DATA3_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI0B_DATA3_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA3_PDRV_MASK)
#define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_MASK)
#define IOMUXD_QSPI0B_DATA3_PULL_MASK            (0x60U)
#define IOMUXD_QSPI0B_DATA3_PULL_SHIFT           (5U)
#define IOMUXD_QSPI0B_DATA3_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA3_PULL_MASK)
#define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_MASK)
#define IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI0B_DATA3_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0B_DATA3_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI0B_DATA3_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0B_DATA3_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA3_lp_config_MASK)
#define IOMUXD_QSPI0B_DATA3_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI0B_DATA3_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0B_DATA3_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA3_sw_config_MASK)
#define IOMUXD_QSPI0B_DATA3_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI0B_DATA3_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0B.DATA3
 */
#define IOMUXD_QSPI0B_DATA3_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA3_mux_mode_MASK)
#define IOMUXD_QSPI0B_DATA3_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI0B_DATA3_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI0B_DATA3_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA3_update_pad_ctl_MASK)
#define IOMUXD_QSPI0B_DATA3_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI0B_DATA3_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI0B_DATA3_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA3_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI0B_DQS - QSPI0B_DQS */
/*! @{ */
#define IOMUXD_QSPI0B_DQS_PDRV_MASK              (0x1U)
#define IOMUXD_QSPI0B_DQS_PDRV_SHIFT             (0U)
#define IOMUXD_QSPI0B_DQS_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_PDRV_SHIFT)) & IOMUXD_QSPI0B_DQS_PDRV_MASK)
#define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_MASK)
#define IOMUXD_QSPI0B_DQS_PULL_MASK              (0x60U)
#define IOMUXD_QSPI0B_DQS_PULL_SHIFT             (5U)
#define IOMUXD_QSPI0B_DQS_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_PULL_SHIFT)) & IOMUXD_QSPI0B_DQS_PULL_MASK)
#define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_MASK)
#define IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_MASK       (0x380000U)
#define IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_SHIFT      (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0B_DQS_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0B_DQS_WAKEUP_MASK_MASK       (0x400000U)
#define IOMUXD_QSPI0B_DQS_WAKEUP_MASK_SHIFT      (22U)
#define IOMUXD_QSPI0B_DQS_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DQS_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0B_DQS_lp_config_MASK         (0x1800000U)
#define IOMUXD_QSPI0B_DQS_lp_config_SHIFT        (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0B_DQS_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_lp_config_SHIFT)) & IOMUXD_QSPI0B_DQS_lp_config_MASK)
#define IOMUXD_QSPI0B_DQS_sw_config_MASK         (0x6000000U)
#define IOMUXD_QSPI0B_DQS_sw_config_SHIFT        (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0B_DQS_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_sw_config_SHIFT)) & IOMUXD_QSPI0B_DQS_sw_config_MASK)
#define IOMUXD_QSPI0B_DQS_mux_mode_MASK          (0x38000000U)
#define IOMUXD_QSPI0B_DQS_mux_mode_SHIFT         (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0B.DQS
 */
#define IOMUXD_QSPI0B_DQS_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DQS_mux_mode_MASK)
#define IOMUXD_QSPI0B_DQS_update_pad_ctl_MASK    (0x40000000U)
#define IOMUXD_QSPI0B_DQS_update_pad_ctl_SHIFT   (30U)
#define IOMUXD_QSPI0B_DQS_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DQS_update_pad_ctl_MASK)
#define IOMUXD_QSPI0B_DQS_update_mux_mode_MASK   (0x80000000U)
#define IOMUXD_QSPI0B_DQS_update_mux_mode_SHIFT  (31U)
#define IOMUXD_QSPI0B_DQS_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DQS_update_mux_mode_MASK)
/*! @} */

/*! @name QSPI0B_SS0_B - QSPI0B_SS0_B */
/*! @{ */
#define IOMUXD_QSPI0B_SS0_B_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI0B_SS0_B_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI0B_SS0_B_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_PDRV_SHIFT)) & IOMUXD_QSPI0B_SS0_B_PDRV_MASK)
#define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_MASK)
#define IOMUXD_QSPI0B_SS0_B_PULL_MASK            (0x60U)
#define IOMUXD_QSPI0B_SS0_B_PULL_SHIFT           (5U)
#define IOMUXD_QSPI0B_SS0_B_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_PULL_SHIFT)) & IOMUXD_QSPI0B_SS0_B_PULL_MASK)
#define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_MASK)
#define IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0B_SS0_B_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI0B_SS0_B_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0B_SS0_B_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_lp_config_SHIFT)) & IOMUXD_QSPI0B_SS0_B_lp_config_MASK)
#define IOMUXD_QSPI0B_SS0_B_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI0B_SS0_B_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0B_SS0_B_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_sw_config_SHIFT)) & IOMUXD_QSPI0B_SS0_B_sw_config_MASK)
#define IOMUXD_QSPI0B_SS0_B_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI0B_SS0_B_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0B.SS0_B
 */
#define IOMUXD_QSPI0B_SS0_B_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS0_B_mux_mode_MASK)
#define IOMUXD_QSPI0B_SS0_B_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI0B_SS0_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI0B_SS0_B_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_SS0_B_update_pad_ctl_MASK)
#define IOMUXD_QSPI0B_SS0_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI0B_SS0_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI0B_SS0_B_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS0_B_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_2_3 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA0_MASK (0x1U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA0_SHIFT (0U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA0(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA0_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA1_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA1_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA1(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA1_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA2_MASK (0x4U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA2_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA2(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA2_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA3_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA3_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA3(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DATA3_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DQS_MASK  (0x10U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DQS_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DQS(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DQS_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_DQS_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SS0_B_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SS0_B_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SS0_B(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SS0_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SS0_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SS1_B_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SS1_B_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SS1_B(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SS1_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SS1_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SCLK_MASK (0x80U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SCLK_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SCLK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0A_SCLK_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_SCLK_MASK (0x100U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_SCLK_SHIFT (8U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_SCLK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_SCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_SCLK_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA0_MASK (0x200U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA0_SHIFT (9U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA0(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA0_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA1_MASK (0x400U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA1_SHIFT (10U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA1(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA1_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA2_MASK (0x800U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA2_SHIFT (11U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA2(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA2_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA3_MASK (0x1000U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA3_SHIFT (12U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA3(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DATA3_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DQS_MASK  (0x2000U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DQS_SHIFT (13U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DQS(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DQS_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_DQS_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_SS0_B_MASK (0x4000U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_SS0_B_SHIFT (14U)
#define IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_SS0_B(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_SS0_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_QSPI0B_SS0_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_MASK (0xFFFF8000U)
#define IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_SHIFT (15U)
#define IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_MASK)
/*! @} */

/*! @name QSPI0B_SS1_B - QSPI0B_SS1_B */
/*! @{ */
#define IOMUXD_QSPI0B_SS1_B_PDRV_MASK            (0x1U)
#define IOMUXD_QSPI0B_SS1_B_PDRV_SHIFT           (0U)
#define IOMUXD_QSPI0B_SS1_B_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_PDRV_SHIFT)) & IOMUXD_QSPI0B_SS1_B_PDRV_MASK)
#define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_MASK)
#define IOMUXD_QSPI0B_SS1_B_PULL_MASK            (0x60U)
#define IOMUXD_QSPI0B_SS1_B_PULL_SHIFT           (5U)
#define IOMUXD_QSPI0B_SS1_B_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_PULL_SHIFT)) & IOMUXD_QSPI0B_SS1_B_PULL_MASK)
#define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_MASK)
#define IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_MASK)
#define IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_MASK)
#define IOMUXD_QSPI0B_SS1_B_lp_config_MASK       (0x1800000U)
#define IOMUXD_QSPI0B_SS1_B_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_QSPI0B_SS1_B_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_lp_config_SHIFT)) & IOMUXD_QSPI0B_SS1_B_lp_config_MASK)
#define IOMUXD_QSPI0B_SS1_B_sw_config_MASK       (0x6000000U)
#define IOMUXD_QSPI0B_SS1_B_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_QSPI0B_SS1_B_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_sw_config_SHIFT)) & IOMUXD_QSPI0B_SS1_B_sw_config_MASK)
#define IOMUXD_QSPI0B_SS1_B_mux_mode_MASK        (0x38000000U)
#define IOMUXD_QSPI0B_SS1_B_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..LSIO.QSPI0B.SS1_B
 *  0b001..LSIO.QSPI0B.SCLK2
 */
#define IOMUXD_QSPI0B_SS1_B_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS1_B_mux_mode_MASK)
#define IOMUXD_QSPI0B_SS1_B_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_QSPI0B_SS1_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_QSPI0B_SS1_B_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_SS1_B_update_pad_ctl_MASK)
#define IOMUXD_QSPI0B_SS1_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_QSPI0B_SS1_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_QSPI0B_SS1_B_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS1_B_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0 */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0_update_mux_mode_MASK)
/*! @} */

/*! @name PCIE_CTRL0_CLKREQ_B - PCIE_CTRL0_CLKREQ_B */
/*! @{ */
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_MASK     (0x1U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_SHIFT    (0U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_MASK)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_MASK)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_MASK     (0x60U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_SHIFT    (5U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_MASK)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_MASK)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_MASK)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_MASK)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_MASK (0x1800000U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_MASK)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_MASK (0x6000000U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_MASK)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_MASK (0x38000000U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..HSIO.PCIE0.CLKREQ_B
 *  0b011..LSIO.GPIO4.IO27
 */
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_MASK)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_MASK)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_MASK)
/*! @} */

/*! @name PCIE_CTRL0_WAKE_B - PCIE_CTRL0_WAKE_B */
/*! @{ */
#define IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_MASK       (0x1U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_SHIFT      (0U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_PDRV(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_MASK)
#define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_MASK)
#define IOMUXD_PCIE_CTRL0_WAKE_B_PULL_MASK       (0x60U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_PULL_SHIFT      (5U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_PULL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PULL_MASK)
#define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_MASK)
#define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_MASK)
#define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_MASK)
#define IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_MASK  (0x1800000U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_PCIE_CTRL0_WAKE_B_lp_config(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_MASK)
#define IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_MASK  (0x6000000U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_PCIE_CTRL0_WAKE_B_sw_config(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_MASK)
#define IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_MASK   (0x38000000U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_SHIFT  (27U)
/*! mux_mode - mux_mode
 *  0b000..HSIO.PCIE0.WAKE_B
 *  0b011..LSIO.GPIO4.IO28
 */
#define IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_MASK)
#define IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_MASK)
#define IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_MASK)
/*! @} */

/*! @name PCIE_CTRL0_PERST_B - PCIE_CTRL0_PERST_B */
/*! @{ */
#define IOMUXD_PCIE_CTRL0_PERST_B_PDRV_MASK      (0x1U)
#define IOMUXD_PCIE_CTRL0_PERST_B_PDRV_SHIFT     (0U)
#define IOMUXD_PCIE_CTRL0_PERST_B_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PDRV_MASK)
#define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_MASK)
#define IOMUXD_PCIE_CTRL0_PERST_B_PULL_MASK      (0x60U)
#define IOMUXD_PCIE_CTRL0_PERST_B_PULL_SHIFT     (5U)
#define IOMUXD_PCIE_CTRL0_PERST_B_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PULL_MASK)
#define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_MASK)
#define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_MASK)
#define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_MASK)
#define IOMUXD_PCIE_CTRL0_PERST_B_lp_config_MASK (0x1800000U)
#define IOMUXD_PCIE_CTRL0_PERST_B_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_PCIE_CTRL0_PERST_B_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_lp_config_MASK)
#define IOMUXD_PCIE_CTRL0_PERST_B_sw_config_MASK (0x6000000U)
#define IOMUXD_PCIE_CTRL0_PERST_B_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_PCIE_CTRL0_PERST_B_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_sw_config_MASK)
#define IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_MASK  (0x38000000U)
#define IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..HSIO.PCIE0.PERST_B
 *  0b011..LSIO.GPIO4.IO29
 */
#define IOMUXD_PCIE_CTRL0_PERST_B_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_MASK)
#define IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_MASK)
#define IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_MASK)
/*! @} */

/*! @name PCIE_CTRL1_CLKREQ_B - PCIE_CTRL1_CLKREQ_B */
/*! @{ */
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_PDRV_MASK     (0x1U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_PDRV_SHIFT    (0U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_PDRV(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_CLKREQ_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL1_CLKREQ_B_PDRV_MASK)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_PCIE_CTRL1_CLKREQ_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_PCIE_CTRL1_CLKREQ_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_PCIE_CTRL1_CLKREQ_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_CLKREQ_B_PCIE_CTRL1_CLKREQ_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL1_CLKREQ_B_PCIE_CTRL1_CLKREQ_B_reserved_1_4_MASK)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_PULL_MASK     (0x60U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_PULL_SHIFT    (5U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_PULL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_CLKREQ_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL1_CLKREQ_B_PULL_MASK)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_PCIE_CTRL1_CLKREQ_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_PCIE_CTRL1_CLKREQ_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_PCIE_CTRL1_CLKREQ_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_CLKREQ_B_PCIE_CTRL1_CLKREQ_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL1_CLKREQ_B_PCIE_CTRL1_CLKREQ_B_reserved_7_18_MASK)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_CLKREQ_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL1_CLKREQ_B_WAKEUP_CTRL_MASK)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_CLKREQ_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL1_CLKREQ_B_WAKEUP_MASK_MASK)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_lp_config_MASK (0x1800000U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_lp_config(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_CLKREQ_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL1_CLKREQ_B_lp_config_MASK)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_sw_config_MASK (0x6000000U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_sw_config(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_CLKREQ_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL1_CLKREQ_B_sw_config_MASK)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_mux_mode_MASK (0x38000000U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..HSIO.PCIE1.CLKREQ_B
 *  0b001..DMA.I2C1.SDA
 *  0b010..CONN.USB_OTG2.OC
 *  0b011..LSIO.GPIO4.IO30
 */
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_CLKREQ_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL1_CLKREQ_B_mux_mode_MASK)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_CLKREQ_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL1_CLKREQ_B_update_pad_ctl_MASK)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_PCIE_CTRL1_CLKREQ_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_CLKREQ_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL1_CLKREQ_B_update_mux_mode_MASK)
/*! @} */

/*! @name PCIE_CTRL1_WAKE_B - PCIE_CTRL1_WAKE_B */
/*! @{ */
#define IOMUXD_PCIE_CTRL1_WAKE_B_PDRV_MASK       (0x1U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_PDRV_SHIFT      (0U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_PDRV(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_WAKE_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL1_WAKE_B_PDRV_MASK)
#define IOMUXD_PCIE_CTRL1_WAKE_B_PCIE_CTRL1_WAKE_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_PCIE_CTRL1_WAKE_B_PCIE_CTRL1_WAKE_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_PCIE_CTRL1_WAKE_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_WAKE_B_PCIE_CTRL1_WAKE_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL1_WAKE_B_PCIE_CTRL1_WAKE_B_reserved_1_4_MASK)
#define IOMUXD_PCIE_CTRL1_WAKE_B_PULL_MASK       (0x60U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_PULL_SHIFT      (5U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_PULL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_WAKE_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL1_WAKE_B_PULL_MASK)
#define IOMUXD_PCIE_CTRL1_WAKE_B_PCIE_CTRL1_WAKE_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_PCIE_CTRL1_WAKE_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_PCIE_CTRL1_WAKE_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_WAKE_B_PCIE_CTRL1_WAKE_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL1_WAKE_B_PCIE_CTRL1_WAKE_B_reserved_7_18_MASK)
#define IOMUXD_PCIE_CTRL1_WAKE_B_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_PCIE_CTRL1_WAKE_B_WAKEUP_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_WAKE_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL1_WAKE_B_WAKEUP_CTRL_MASK)
#define IOMUXD_PCIE_CTRL1_WAKE_B_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_WAKEUP_MASK(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_WAKE_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL1_WAKE_B_WAKEUP_MASK_MASK)
#define IOMUXD_PCIE_CTRL1_WAKE_B_lp_config_MASK  (0x1800000U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_PCIE_CTRL1_WAKE_B_lp_config(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_WAKE_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL1_WAKE_B_lp_config_MASK)
#define IOMUXD_PCIE_CTRL1_WAKE_B_sw_config_MASK  (0x6000000U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_PCIE_CTRL1_WAKE_B_sw_config(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_WAKE_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL1_WAKE_B_sw_config_MASK)
#define IOMUXD_PCIE_CTRL1_WAKE_B_mux_mode_MASK   (0x38000000U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_mux_mode_SHIFT  (27U)
/*! mux_mode - mux_mode
 *  0b000..HSIO.PCIE1.WAKE_B
 *  0b001..DMA.I2C1.SCL
 *  0b010..CONN.USB_OTG2.PWR
 *  0b011..LSIO.GPIO4.IO31
 */
#define IOMUXD_PCIE_CTRL1_WAKE_B_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_WAKE_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL1_WAKE_B_mux_mode_MASK)
#define IOMUXD_PCIE_CTRL1_WAKE_B_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_WAKE_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL1_WAKE_B_update_pad_ctl_MASK)
#define IOMUXD_PCIE_CTRL1_WAKE_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_PCIE_CTRL1_WAKE_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_WAKE_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL1_WAKE_B_update_mux_mode_MASK)
/*! @} */

/*! @name PCIE_CTRL1_PERST_B - PCIE_CTRL1_PERST_B */
/*! @{ */
#define IOMUXD_PCIE_CTRL1_PERST_B_PDRV_MASK      (0x1U)
#define IOMUXD_PCIE_CTRL1_PERST_B_PDRV_SHIFT     (0U)
#define IOMUXD_PCIE_CTRL1_PERST_B_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_PERST_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL1_PERST_B_PDRV_MASK)
#define IOMUXD_PCIE_CTRL1_PERST_B_PCIE_CTRL1_PERST_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_PCIE_CTRL1_PERST_B_PCIE_CTRL1_PERST_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_PCIE_CTRL1_PERST_B_PCIE_CTRL1_PERST_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_PERST_B_PCIE_CTRL1_PERST_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL1_PERST_B_PCIE_CTRL1_PERST_B_reserved_1_4_MASK)
#define IOMUXD_PCIE_CTRL1_PERST_B_PULL_MASK      (0x60U)
#define IOMUXD_PCIE_CTRL1_PERST_B_PULL_SHIFT     (5U)
#define IOMUXD_PCIE_CTRL1_PERST_B_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_PERST_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL1_PERST_B_PULL_MASK)
#define IOMUXD_PCIE_CTRL1_PERST_B_PCIE_CTRL1_PERST_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_PCIE_CTRL1_PERST_B_PCIE_CTRL1_PERST_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_PCIE_CTRL1_PERST_B_PCIE_CTRL1_PERST_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_PERST_B_PCIE_CTRL1_PERST_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL1_PERST_B_PCIE_CTRL1_PERST_B_reserved_7_18_MASK)
#define IOMUXD_PCIE_CTRL1_PERST_B_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_PCIE_CTRL1_PERST_B_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_PCIE_CTRL1_PERST_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_PERST_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL1_PERST_B_WAKEUP_CTRL_MASK)
#define IOMUXD_PCIE_CTRL1_PERST_B_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_PCIE_CTRL1_PERST_B_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_PCIE_CTRL1_PERST_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_PERST_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL1_PERST_B_WAKEUP_MASK_MASK)
#define IOMUXD_PCIE_CTRL1_PERST_B_lp_config_MASK (0x1800000U)
#define IOMUXD_PCIE_CTRL1_PERST_B_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_PCIE_CTRL1_PERST_B_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_PERST_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL1_PERST_B_lp_config_MASK)
#define IOMUXD_PCIE_CTRL1_PERST_B_sw_config_MASK (0x6000000U)
#define IOMUXD_PCIE_CTRL1_PERST_B_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_PCIE_CTRL1_PERST_B_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_PERST_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL1_PERST_B_sw_config_MASK)
#define IOMUXD_PCIE_CTRL1_PERST_B_mux_mode_MASK  (0x38000000U)
#define IOMUXD_PCIE_CTRL1_PERST_B_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..HSIO.PCIE1.PERST_B
 *  0b001..DMA.I2C1.SCL
 *  0b010..CONN.USB_OTG1.PWR
 *  0b011..LSIO.GPIO5.IO00
 */
#define IOMUXD_PCIE_CTRL1_PERST_B_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_PERST_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL1_PERST_B_mux_mode_MASK)
#define IOMUXD_PCIE_CTRL1_PERST_B_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_PCIE_CTRL1_PERST_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_PCIE_CTRL1_PERST_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_PERST_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL1_PERST_B_update_pad_ctl_MASK)
#define IOMUXD_PCIE_CTRL1_PERST_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_PCIE_CTRL1_PERST_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_PCIE_CTRL1_PERST_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL1_PERST_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL1_PERST_B_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP - IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_2_4 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_2_4_QSPI0B_SS1_B_MASK (0x1U)
#define IOMUXD_IOMUXD_GROUP_2_4_QSPI0B_SS1_B_SHIFT (0U)
#define IOMUXD_IOMUXD_GROUP_2_4_QSPI0B_SS1_B(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_QSPI0B_SS1_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_QSPI0B_SS1_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_1_1_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_1_1_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_1_1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_1_1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_1_1_MASK)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_CLKREQ_B_MASK (0x4U)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_CLKREQ_B_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_CLKREQ_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_CLKREQ_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_CLKREQ_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_WAKE_B_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_WAKE_B_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_WAKE_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_WAKE_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_WAKE_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_PERST_B_MASK (0x10U)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_PERST_B_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_PERST_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_PERST_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL0_PERST_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_CLKREQ_B_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_CLKREQ_B_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_CLKREQ_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_CLKREQ_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_CLKREQ_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_WAKE_B_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_WAKE_B_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_WAKE_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_WAKE_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_WAKE_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_PERST_B_MASK (0x80U)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_PERST_B_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_PERST_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_PERST_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_PCIE_CTRL1_PERST_B_MASK)
#define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_31_MASK (0xFFFFFF00U)
#define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_31_SHIFT (8U)
#define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_31_MASK)
/*! @} */

/*! @name USB_HSIC0_DATA - USB_HSIC0_DATA */
/*! @{ */
#define IOMUXD_USB_HSIC0_DATA_DSE_MASK           (0x7U)
#define IOMUXD_USB_HSIC0_DATA_DSE_SHIFT          (0U)
#define IOMUXD_USB_HSIC0_DATA_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_DATA_DSE_SHIFT)) & IOMUXD_USB_HSIC0_DATA_DSE_MASK)
#define IOMUXD_USB_HSIC0_DATA_HYS_MASK           (0x8U)
#define IOMUXD_USB_HSIC0_DATA_HYS_SHIFT          (3U)
#define IOMUXD_USB_HSIC0_DATA_HYS(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_DATA_HYS_SHIFT)) & IOMUXD_USB_HSIC0_DATA_HYS_MASK)
#define IOMUXD_USB_HSIC0_DATA_PS_MASK            (0x30U)
#define IOMUXD_USB_HSIC0_DATA_PS_SHIFT           (4U)
#define IOMUXD_USB_HSIC0_DATA_PS(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_DATA_PS_SHIFT)) & IOMUXD_USB_HSIC0_DATA_PS_MASK)
#define IOMUXD_USB_HSIC0_DATA_PKE_MASK           (0x40U)
#define IOMUXD_USB_HSIC0_DATA_PKE_SHIFT          (6U)
#define IOMUXD_USB_HSIC0_DATA_PKE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_DATA_PKE_SHIFT)) & IOMUXD_USB_HSIC0_DATA_PKE_MASK)
#define IOMUXD_USB_HSIC0_DATA_PE_MASK            (0x80U)
#define IOMUXD_USB_HSIC0_DATA_PE_SHIFT           (7U)
#define IOMUXD_USB_HSIC0_DATA_PE(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_DATA_PE_SHIFT)) & IOMUXD_USB_HSIC0_DATA_PE_MASK)
#define IOMUXD_USB_HSIC0_DATA_USB_HSIC0_DATA_reserved_8_18_MASK (0x7FF00U)
#define IOMUXD_USB_HSIC0_DATA_USB_HSIC0_DATA_reserved_8_18_SHIFT (8U)
#define IOMUXD_USB_HSIC0_DATA_USB_HSIC0_DATA_reserved_8_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_DATA_USB_HSIC0_DATA_reserved_8_18_SHIFT)) & IOMUXD_USB_HSIC0_DATA_USB_HSIC0_DATA_reserved_8_18_MASK)
#define IOMUXD_USB_HSIC0_DATA_WAKEUP_CTRL_MASK   (0x380000U)
#define IOMUXD_USB_HSIC0_DATA_WAKEUP_CTRL_SHIFT  (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USB_HSIC0_DATA_WAKEUP_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_DATA_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_HSIC0_DATA_WAKEUP_CTRL_MASK)
#define IOMUXD_USB_HSIC0_DATA_WAKEUP_MASK_MASK   (0x400000U)
#define IOMUXD_USB_HSIC0_DATA_WAKEUP_MASK_SHIFT  (22U)
#define IOMUXD_USB_HSIC0_DATA_WAKEUP_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_DATA_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_HSIC0_DATA_WAKEUP_MASK_MASK)
#define IOMUXD_USB_HSIC0_DATA_lp_config_MASK     (0x1800000U)
#define IOMUXD_USB_HSIC0_DATA_lp_config_SHIFT    (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USB_HSIC0_DATA_lp_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_DATA_lp_config_SHIFT)) & IOMUXD_USB_HSIC0_DATA_lp_config_MASK)
#define IOMUXD_USB_HSIC0_DATA_sw_config_MASK     (0x6000000U)
#define IOMUXD_USB_HSIC0_DATA_sw_config_SHIFT    (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USB_HSIC0_DATA_sw_config(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_DATA_sw_config_SHIFT)) & IOMUXD_USB_HSIC0_DATA_sw_config_MASK)
#define IOMUXD_USB_HSIC0_DATA_mux_mode_MASK      (0x38000000U)
#define IOMUXD_USB_HSIC0_DATA_mux_mode_SHIFT     (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USB_HSIC0.DATA
 *  0b001..DMA.I2C1.SDA
 *  0b011..LSIO.GPIO5.IO01
 */
#define IOMUXD_USB_HSIC0_DATA_mux_mode(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_DATA_mux_mode_SHIFT)) & IOMUXD_USB_HSIC0_DATA_mux_mode_MASK)
#define IOMUXD_USB_HSIC0_DATA_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_USB_HSIC0_DATA_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USB_HSIC0_DATA_update_pad_ctl(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_DATA_update_pad_ctl_SHIFT)) & IOMUXD_USB_HSIC0_DATA_update_pad_ctl_MASK)
#define IOMUXD_USB_HSIC0_DATA_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USB_HSIC0_DATA_update_mux_mode_SHIFT (31U)
#define IOMUXD_USB_HSIC0_DATA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_DATA_update_mux_mode_SHIFT)) & IOMUXD_USB_HSIC0_DATA_update_mux_mode_MASK)
/*! @} */

/*! @name USB_HSIC0_STROBE - USB_HSIC0_STROBE */
/*! @{ */
#define IOMUXD_USB_HSIC0_STROBE_DSE_MASK         (0x7U)
#define IOMUXD_USB_HSIC0_STROBE_DSE_SHIFT        (0U)
#define IOMUXD_USB_HSIC0_STROBE_DSE(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_STROBE_DSE_SHIFT)) & IOMUXD_USB_HSIC0_STROBE_DSE_MASK)
#define IOMUXD_USB_HSIC0_STROBE_HYS_MASK         (0x8U)
#define IOMUXD_USB_HSIC0_STROBE_HYS_SHIFT        (3U)
#define IOMUXD_USB_HSIC0_STROBE_HYS(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_STROBE_HYS_SHIFT)) & IOMUXD_USB_HSIC0_STROBE_HYS_MASK)
#define IOMUXD_USB_HSIC0_STROBE_PS_MASK          (0x30U)
#define IOMUXD_USB_HSIC0_STROBE_PS_SHIFT         (4U)
#define IOMUXD_USB_HSIC0_STROBE_PS(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_STROBE_PS_SHIFT)) & IOMUXD_USB_HSIC0_STROBE_PS_MASK)
#define IOMUXD_USB_HSIC0_STROBE_PKE_MASK         (0x40U)
#define IOMUXD_USB_HSIC0_STROBE_PKE_SHIFT        (6U)
#define IOMUXD_USB_HSIC0_STROBE_PKE(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_STROBE_PKE_SHIFT)) & IOMUXD_USB_HSIC0_STROBE_PKE_MASK)
#define IOMUXD_USB_HSIC0_STROBE_PE_MASK          (0x80U)
#define IOMUXD_USB_HSIC0_STROBE_PE_SHIFT         (7U)
#define IOMUXD_USB_HSIC0_STROBE_PE(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_STROBE_PE_SHIFT)) & IOMUXD_USB_HSIC0_STROBE_PE_MASK)
#define IOMUXD_USB_HSIC0_STROBE_USB_HSIC0_STROBE_reserved_8_18_MASK (0x7FF00U)
#define IOMUXD_USB_HSIC0_STROBE_USB_HSIC0_STROBE_reserved_8_18_SHIFT (8U)
#define IOMUXD_USB_HSIC0_STROBE_USB_HSIC0_STROBE_reserved_8_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_STROBE_USB_HSIC0_STROBE_reserved_8_18_SHIFT)) & IOMUXD_USB_HSIC0_STROBE_USB_HSIC0_STROBE_reserved_8_18_MASK)
#define IOMUXD_USB_HSIC0_STROBE_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_USB_HSIC0_STROBE_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USB_HSIC0_STROBE_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_STROBE_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_HSIC0_STROBE_WAKEUP_CTRL_MASK)
#define IOMUXD_USB_HSIC0_STROBE_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_USB_HSIC0_STROBE_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_USB_HSIC0_STROBE_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_STROBE_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_HSIC0_STROBE_WAKEUP_MASK_MASK)
#define IOMUXD_USB_HSIC0_STROBE_lp_config_MASK   (0x1800000U)
#define IOMUXD_USB_HSIC0_STROBE_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USB_HSIC0_STROBE_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_STROBE_lp_config_SHIFT)) & IOMUXD_USB_HSIC0_STROBE_lp_config_MASK)
#define IOMUXD_USB_HSIC0_STROBE_sw_config_MASK   (0x6000000U)
#define IOMUXD_USB_HSIC0_STROBE_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USB_HSIC0_STROBE_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_STROBE_sw_config_SHIFT)) & IOMUXD_USB_HSIC0_STROBE_sw_config_MASK)
#define IOMUXD_USB_HSIC0_STROBE_mux_mode_MASK    (0x38000000U)
#define IOMUXD_USB_HSIC0_STROBE_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USB_HSIC0.STROBE
 *  0b001..DMA.I2C1.SCL
 *  0b011..LSIO.GPIO5.IO02
 */
#define IOMUXD_USB_HSIC0_STROBE_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_STROBE_mux_mode_SHIFT)) & IOMUXD_USB_HSIC0_STROBE_mux_mode_MASK)
#define IOMUXD_USB_HSIC0_STROBE_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_USB_HSIC0_STROBE_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USB_HSIC0_STROBE_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_STROBE_update_pad_ctl_SHIFT)) & IOMUXD_USB_HSIC0_STROBE_update_pad_ctl_MASK)
#define IOMUXD_USB_HSIC0_STROBE_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USB_HSIC0_STROBE_update_mux_mode_SHIFT (31U)
#define IOMUXD_USB_HSIC0_STROBE_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_HSIC0_STROBE_update_mux_mode_SHIFT)) & IOMUXD_USB_HSIC0_STROBE_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_CALIBRATION_0_HSIC - IOMUXD_CALIBRATION_0_HSIC */
/*! @{ */
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_VOH_MASK (0x1FU)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_VOH_SHIFT (0U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_VOH(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CALIBRATION_0_HSIC_VOH_SHIFT)) & IOMUXD_IOMUXD_CALIBRATION_0_HSIC_VOH_MASK)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_VOH_M1_MASK (0x3E0U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_VOH_M1_SHIFT (5U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_VOH_M1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CALIBRATION_0_HSIC_VOH_M1_SHIFT)) & IOMUXD_IOMUXD_CALIBRATION_0_HSIC_VOH_M1_MASK)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_COMPARE_MASK (0x400U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_COMPARE_SHIFT (10U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CALIBRATION_0_HSIC_COMPARE_SHIFT)) & IOMUXD_IOMUXD_CALIBRATION_0_HSIC_COMPARE_MASK)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_PU_PD_SEL_MASK (0x800U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_PU_PD_SEL_SHIFT (11U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_PU_PD_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CALIBRATION_0_HSIC_PU_PD_SEL_SHIFT)) & IOMUXD_IOMUXD_CALIBRATION_0_HSIC_PU_PD_SEL_MASK)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_CALIBRATION_EN_MASK (0x1000U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_CALIBRATION_EN_SHIFT (12U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_CALIBRATION_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CALIBRATION_0_HSIC_CALIBRATION_EN_SHIFT)) & IOMUXD_IOMUXD_CALIBRATION_0_HSIC_CALIBRATION_EN_MASK)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_IOMUXD_CALIBRATION_0_HSIC_reserved_13_29_MASK (0x3FFFE000U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_IOMUXD_CALIBRATION_0_HSIC_reserved_13_29_SHIFT (13U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_IOMUXD_CALIBRATION_0_HSIC_reserved_13_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CALIBRATION_0_HSIC_IOMUXD_CALIBRATION_0_HSIC_reserved_13_29_SHIFT)) & IOMUXD_IOMUXD_CALIBRATION_0_HSIC_IOMUXD_CALIBRATION_0_HSIC_reserved_13_29_MASK)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CALIBRATION_0_HSIC_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_CALIBRATION_0_HSIC_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_CALIBRATION_0_HSIC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CALIBRATION_0_HSIC_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_CALIBRATION_0_HSIC_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_CALIBRATION_1_HSIC - IOMUXD_CALIBRATION_1_HSIC */
/*! @{ */
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_VOL_MASK (0x1FU)
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_VOL_SHIFT (0U)
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_VOL(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CALIBRATION_1_HSIC_VOL_SHIFT)) & IOMUXD_IOMUXD_CALIBRATION_1_HSIC_VOL_MASK)
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_VOL_M1_MASK (0x3E0U)
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_VOL_M1_SHIFT (5U)
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_VOL_M1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CALIBRATION_1_HSIC_VOL_M1_SHIFT)) & IOMUXD_IOMUXD_CALIBRATION_1_HSIC_VOL_M1_MASK)
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_IOMUXD_CALIBRATION_1_HSIC_reserved_10_29_MASK (0x3FFFFC00U)
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_IOMUXD_CALIBRATION_1_HSIC_reserved_10_29_SHIFT (10U)
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_IOMUXD_CALIBRATION_1_HSIC_reserved_10_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CALIBRATION_1_HSIC_IOMUXD_CALIBRATION_1_HSIC_reserved_10_29_SHIFT)) & IOMUXD_IOMUXD_CALIBRATION_1_HSIC_IOMUXD_CALIBRATION_1_HSIC_reserved_10_29_MASK)
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CALIBRATION_1_HSIC_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_CALIBRATION_1_HSIC_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_CALIBRATION_1_HSIC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CALIBRATION_1_HSIC_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_CALIBRATION_1_HSIC_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_2_5 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_2_5_USB_HSIC0_DATA_MASK (0x1U)
#define IOMUXD_IOMUXD_GROUP_2_5_USB_HSIC0_DATA_SHIFT (0U)
#define IOMUXD_IOMUXD_GROUP_2_5_USB_HSIC0_DATA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_5_USB_HSIC0_DATA_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_5_USB_HSIC0_DATA_MASK)
#define IOMUXD_IOMUXD_GROUP_2_5_USB_HSIC0_STROBE_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_2_5_USB_HSIC0_STROBE_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_2_5_USB_HSIC0_STROBE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_5_USB_HSIC0_STROBE_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_5_USB_HSIC0_STROBE_MASK)
#define IOMUXD_IOMUXD_GROUP_2_5_iomuxd_group_2_5_reserved_2_31_MASK (0xFFFFFFFCU)
#define IOMUXD_IOMUXD_GROUP_2_5_iomuxd_group_2_5_reserved_2_31_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_2_5_iomuxd_group_2_5_reserved_2_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_5_iomuxd_group_2_5_reserved_2_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_5_iomuxd_group_2_5_reserved_2_31_MASK)
/*! @} */

/*! @name EMMC0_CLK - EMMC0_CLK */
/*! @{ */
#define IOMUXD_EMMC0_CLK_PDRV_MASK               (0x1U)
#define IOMUXD_EMMC0_CLK_PDRV_SHIFT              (0U)
#define IOMUXD_EMMC0_CLK_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_PDRV_SHIFT)) & IOMUXD_EMMC0_CLK_PDRV_MASK)
#define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_MASK (0x1EU)
#define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_SHIFT (1U)
#define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_MASK)
#define IOMUXD_EMMC0_CLK_PULL_MASK               (0x60U)
#define IOMUXD_EMMC0_CLK_PULL_SHIFT              (5U)
#define IOMUXD_EMMC0_CLK_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_PULL_SHIFT)) & IOMUXD_EMMC0_CLK_PULL_MASK)
#define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_SHIFT (7U)
#define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_MASK)
#define IOMUXD_EMMC0_CLK_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_EMMC0_CLK_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_EMMC0_CLK_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_CLK_WAKEUP_CTRL_MASK)
#define IOMUXD_EMMC0_CLK_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_EMMC0_CLK_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_EMMC0_CLK_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_CLK_WAKEUP_MASK_MASK)
#define IOMUXD_EMMC0_CLK_lp_config_MASK          (0x1800000U)
#define IOMUXD_EMMC0_CLK_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_EMMC0_CLK_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_lp_config_SHIFT)) & IOMUXD_EMMC0_CLK_lp_config_MASK)
#define IOMUXD_EMMC0_CLK_sw_config_MASK          (0x6000000U)
#define IOMUXD_EMMC0_CLK_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_EMMC0_CLK_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_sw_config_SHIFT)) & IOMUXD_EMMC0_CLK_sw_config_MASK)
#define IOMUXD_EMMC0_CLK_mux_mode_MASK           (0x38000000U)
#define IOMUXD_EMMC0_CLK_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.EMMC0.CLK
 *  0b001..CONN.NAND.READY_B
 */
#define IOMUXD_EMMC0_CLK_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_mux_mode_SHIFT)) & IOMUXD_EMMC0_CLK_mux_mode_MASK)
#define IOMUXD_EMMC0_CLK_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_EMMC0_CLK_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_EMMC0_CLK_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_CLK_update_pad_ctl_MASK)
#define IOMUXD_EMMC0_CLK_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_EMMC0_CLK_update_mux_mode_SHIFT   (31U)
#define IOMUXD_EMMC0_CLK_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_CLK_update_mux_mode_MASK)
/*! @} */

/*! @name EMMC0_CMD - EMMC0_CMD */
/*! @{ */
#define IOMUXD_EMMC0_CMD_PDRV_MASK               (0x1U)
#define IOMUXD_EMMC0_CMD_PDRV_SHIFT              (0U)
#define IOMUXD_EMMC0_CMD_PDRV(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_PDRV_SHIFT)) & IOMUXD_EMMC0_CMD_PDRV_MASK)
#define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_MASK (0x1EU)
#define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_SHIFT (1U)
#define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_MASK)
#define IOMUXD_EMMC0_CMD_PULL_MASK               (0x60U)
#define IOMUXD_EMMC0_CMD_PULL_SHIFT              (5U)
#define IOMUXD_EMMC0_CMD_PULL(x)                 (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_PULL_SHIFT)) & IOMUXD_EMMC0_CMD_PULL_MASK)
#define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_SHIFT (7U)
#define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_MASK)
#define IOMUXD_EMMC0_CMD_WAKEUP_CTRL_MASK        (0x380000U)
#define IOMUXD_EMMC0_CMD_WAKEUP_CTRL_SHIFT       (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_EMMC0_CMD_WAKEUP_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_CMD_WAKEUP_CTRL_MASK)
#define IOMUXD_EMMC0_CMD_WAKEUP_MASK_MASK        (0x400000U)
#define IOMUXD_EMMC0_CMD_WAKEUP_MASK_SHIFT       (22U)
#define IOMUXD_EMMC0_CMD_WAKEUP_MASK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_CMD_WAKEUP_MASK_MASK)
#define IOMUXD_EMMC0_CMD_lp_config_MASK          (0x1800000U)
#define IOMUXD_EMMC0_CMD_lp_config_SHIFT         (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_EMMC0_CMD_lp_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_lp_config_SHIFT)) & IOMUXD_EMMC0_CMD_lp_config_MASK)
#define IOMUXD_EMMC0_CMD_sw_config_MASK          (0x6000000U)
#define IOMUXD_EMMC0_CMD_sw_config_SHIFT         (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_EMMC0_CMD_sw_config(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_sw_config_SHIFT)) & IOMUXD_EMMC0_CMD_sw_config_MASK)
#define IOMUXD_EMMC0_CMD_mux_mode_MASK           (0x38000000U)
#define IOMUXD_EMMC0_CMD_mux_mode_SHIFT          (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.EMMC0.CMD
 *  0b001..CONN.NAND.DQS
 *  0b010..AUD.MQS.R
 *  0b011..LSIO.GPIO5.IO03
 */
#define IOMUXD_EMMC0_CMD_mux_mode(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_mux_mode_SHIFT)) & IOMUXD_EMMC0_CMD_mux_mode_MASK)
#define IOMUXD_EMMC0_CMD_update_pad_ctl_MASK     (0x40000000U)
#define IOMUXD_EMMC0_CMD_update_pad_ctl_SHIFT    (30U)
#define IOMUXD_EMMC0_CMD_update_pad_ctl(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_CMD_update_pad_ctl_MASK)
#define IOMUXD_EMMC0_CMD_update_mux_mode_MASK    (0x80000000U)
#define IOMUXD_EMMC0_CMD_update_mux_mode_SHIFT   (31U)
#define IOMUXD_EMMC0_CMD_update_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_CMD_update_mux_mode_MASK)
/*! @} */

/*! @name EMMC0_DATA0 - EMMC0_DATA0 */
/*! @{ */
#define IOMUXD_EMMC0_DATA0_PDRV_MASK             (0x1U)
#define IOMUXD_EMMC0_DATA0_PDRV_SHIFT            (0U)
#define IOMUXD_EMMC0_DATA0_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA0_PDRV_MASK)
#define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_SHIFT (1U)
#define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_MASK)
#define IOMUXD_EMMC0_DATA0_PULL_MASK             (0x60U)
#define IOMUXD_EMMC0_DATA0_PULL_SHIFT            (5U)
#define IOMUXD_EMMC0_DATA0_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_PULL_SHIFT)) & IOMUXD_EMMC0_DATA0_PULL_MASK)
#define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_SHIFT (7U)
#define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_MASK)
#define IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_EMMC0_DATA0_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_MASK)
#define IOMUXD_EMMC0_DATA0_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_EMMC0_DATA0_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_EMMC0_DATA0_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA0_WAKEUP_MASK_MASK)
#define IOMUXD_EMMC0_DATA0_lp_config_MASK        (0x1800000U)
#define IOMUXD_EMMC0_DATA0_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_EMMC0_DATA0_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA0_lp_config_MASK)
#define IOMUXD_EMMC0_DATA0_sw_config_MASK        (0x6000000U)
#define IOMUXD_EMMC0_DATA0_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_EMMC0_DATA0_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA0_sw_config_MASK)
#define IOMUXD_EMMC0_DATA0_mux_mode_MASK         (0x38000000U)
#define IOMUXD_EMMC0_DATA0_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.EMMC0.DATA0
 *  0b001..CONN.NAND.DATA00
 *  0b011..LSIO.GPIO5.IO04
 */
#define IOMUXD_EMMC0_DATA0_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA0_mux_mode_MASK)
#define IOMUXD_EMMC0_DATA0_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_EMMC0_DATA0_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_EMMC0_DATA0_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA0_update_pad_ctl_MASK)
#define IOMUXD_EMMC0_DATA0_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_EMMC0_DATA0_update_mux_mode_SHIFT (31U)
#define IOMUXD_EMMC0_DATA0_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA0_update_mux_mode_MASK)
/*! @} */

/*! @name EMMC0_DATA1 - EMMC0_DATA1 */
/*! @{ */
#define IOMUXD_EMMC0_DATA1_PDRV_MASK             (0x1U)
#define IOMUXD_EMMC0_DATA1_PDRV_SHIFT            (0U)
#define IOMUXD_EMMC0_DATA1_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA1_PDRV_MASK)
#define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_SHIFT (1U)
#define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_MASK)
#define IOMUXD_EMMC0_DATA1_PULL_MASK             (0x60U)
#define IOMUXD_EMMC0_DATA1_PULL_SHIFT            (5U)
#define IOMUXD_EMMC0_DATA1_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_PULL_SHIFT)) & IOMUXD_EMMC0_DATA1_PULL_MASK)
#define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_SHIFT (7U)
#define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_MASK)
#define IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_EMMC0_DATA1_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_MASK)
#define IOMUXD_EMMC0_DATA1_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_EMMC0_DATA1_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_EMMC0_DATA1_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA1_WAKEUP_MASK_MASK)
#define IOMUXD_EMMC0_DATA1_lp_config_MASK        (0x1800000U)
#define IOMUXD_EMMC0_DATA1_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_EMMC0_DATA1_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA1_lp_config_MASK)
#define IOMUXD_EMMC0_DATA1_sw_config_MASK        (0x6000000U)
#define IOMUXD_EMMC0_DATA1_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_EMMC0_DATA1_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA1_sw_config_MASK)
#define IOMUXD_EMMC0_DATA1_mux_mode_MASK         (0x38000000U)
#define IOMUXD_EMMC0_DATA1_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.EMMC0.DATA1
 *  0b001..CONN.NAND.DATA01
 *  0b011..LSIO.GPIO5.IO05
 */
#define IOMUXD_EMMC0_DATA1_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA1_mux_mode_MASK)
#define IOMUXD_EMMC0_DATA1_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_EMMC0_DATA1_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_EMMC0_DATA1_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA1_update_pad_ctl_MASK)
#define IOMUXD_EMMC0_DATA1_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_EMMC0_DATA1_update_mux_mode_SHIFT (31U)
#define IOMUXD_EMMC0_DATA1_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA1_update_mux_mode_MASK)
/*! @} */

/*! @name EMMC0_DATA2 - EMMC0_DATA2 */
/*! @{ */
#define IOMUXD_EMMC0_DATA2_PDRV_MASK             (0x1U)
#define IOMUXD_EMMC0_DATA2_PDRV_SHIFT            (0U)
#define IOMUXD_EMMC0_DATA2_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA2_PDRV_MASK)
#define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_MASK (0x1EU)
#define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_SHIFT (1U)
#define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_MASK)
#define IOMUXD_EMMC0_DATA2_PULL_MASK             (0x60U)
#define IOMUXD_EMMC0_DATA2_PULL_SHIFT            (5U)
#define IOMUXD_EMMC0_DATA2_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_PULL_SHIFT)) & IOMUXD_EMMC0_DATA2_PULL_MASK)
#define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_SHIFT (7U)
#define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_MASK)
#define IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_EMMC0_DATA2_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_MASK)
#define IOMUXD_EMMC0_DATA2_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_EMMC0_DATA2_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_EMMC0_DATA2_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA2_WAKEUP_MASK_MASK)
#define IOMUXD_EMMC0_DATA2_lp_config_MASK        (0x1800000U)
#define IOMUXD_EMMC0_DATA2_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_EMMC0_DATA2_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA2_lp_config_MASK)
#define IOMUXD_EMMC0_DATA2_sw_config_MASK        (0x6000000U)
#define IOMUXD_EMMC0_DATA2_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_EMMC0_DATA2_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA2_sw_config_MASK)
#define IOMUXD_EMMC0_DATA2_mux_mode_MASK         (0x38000000U)
#define IOMUXD_EMMC0_DATA2_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.EMMC0.DATA2
 *  0b001..CONN.NAND.DATA02
 *  0b011..LSIO.GPIO5.IO06
 */
#define IOMUXD_EMMC0_DATA2_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA2_mux_mode_MASK)
#define IOMUXD_EMMC0_DATA2_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_EMMC0_DATA2_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_EMMC0_DATA2_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA2_update_pad_ctl_MASK)
#define IOMUXD_EMMC0_DATA2_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_EMMC0_DATA2_update_mux_mode_SHIFT (31U)
#define IOMUXD_EMMC0_DATA2_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA2_update_mux_mode_MASK)
/*! @} */

/*! @name EMMC0_DATA3 - EMMC0_DATA3 */
/*! @{ */
#define IOMUXD_EMMC0_DATA3_PDRV_MASK             (0x1U)
#define IOMUXD_EMMC0_DATA3_PDRV_SHIFT            (0U)
#define IOMUXD_EMMC0_DATA3_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA3_PDRV_MASK)
#define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_MASK (0x1EU)
#define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_SHIFT (1U)
#define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_MASK)
#define IOMUXD_EMMC0_DATA3_PULL_MASK             (0x60U)
#define IOMUXD_EMMC0_DATA3_PULL_SHIFT            (5U)
#define IOMUXD_EMMC0_DATA3_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_PULL_SHIFT)) & IOMUXD_EMMC0_DATA3_PULL_MASK)
#define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_SHIFT (7U)
#define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_MASK)
#define IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_EMMC0_DATA3_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_MASK)
#define IOMUXD_EMMC0_DATA3_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_EMMC0_DATA3_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_EMMC0_DATA3_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA3_WAKEUP_MASK_MASK)
#define IOMUXD_EMMC0_DATA3_lp_config_MASK        (0x1800000U)
#define IOMUXD_EMMC0_DATA3_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_EMMC0_DATA3_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA3_lp_config_MASK)
#define IOMUXD_EMMC0_DATA3_sw_config_MASK        (0x6000000U)
#define IOMUXD_EMMC0_DATA3_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_EMMC0_DATA3_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA3_sw_config_MASK)
#define IOMUXD_EMMC0_DATA3_mux_mode_MASK         (0x38000000U)
#define IOMUXD_EMMC0_DATA3_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.EMMC0.DATA3
 *  0b001..CONN.NAND.DATA03
 *  0b011..LSIO.GPIO5.IO07
 */
#define IOMUXD_EMMC0_DATA3_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA3_mux_mode_MASK)
#define IOMUXD_EMMC0_DATA3_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_EMMC0_DATA3_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_EMMC0_DATA3_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA3_update_pad_ctl_MASK)
#define IOMUXD_EMMC0_DATA3_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_EMMC0_DATA3_update_mux_mode_SHIFT (31U)
#define IOMUXD_EMMC0_DATA3_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA3_update_mux_mode_MASK)
/*! @} */

/*! @name EMMC0_DATA4 - EMMC0_DATA4 */
/*! @{ */
#define IOMUXD_EMMC0_DATA4_PDRV_MASK             (0x1U)
#define IOMUXD_EMMC0_DATA4_PDRV_SHIFT            (0U)
#define IOMUXD_EMMC0_DATA4_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA4_PDRV_MASK)
#define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_MASK (0x1EU)
#define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_SHIFT (1U)
#define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_MASK)
#define IOMUXD_EMMC0_DATA4_PULL_MASK             (0x60U)
#define IOMUXD_EMMC0_DATA4_PULL_SHIFT            (5U)
#define IOMUXD_EMMC0_DATA4_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_PULL_SHIFT)) & IOMUXD_EMMC0_DATA4_PULL_MASK)
#define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_SHIFT (7U)
#define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_MASK)
#define IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_EMMC0_DATA4_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_MASK)
#define IOMUXD_EMMC0_DATA4_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_EMMC0_DATA4_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_EMMC0_DATA4_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA4_WAKEUP_MASK_MASK)
#define IOMUXD_EMMC0_DATA4_lp_config_MASK        (0x1800000U)
#define IOMUXD_EMMC0_DATA4_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_EMMC0_DATA4_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA4_lp_config_MASK)
#define IOMUXD_EMMC0_DATA4_sw_config_MASK        (0x6000000U)
#define IOMUXD_EMMC0_DATA4_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_EMMC0_DATA4_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA4_sw_config_MASK)
#define IOMUXD_EMMC0_DATA4_mux_mode_MASK         (0x38000000U)
#define IOMUXD_EMMC0_DATA4_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.EMMC0.DATA4
 *  0b001..CONN.NAND.DATA04
 *  0b011..LSIO.GPIO5.IO08
 */
#define IOMUXD_EMMC0_DATA4_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA4_mux_mode_MASK)
#define IOMUXD_EMMC0_DATA4_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_EMMC0_DATA4_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_EMMC0_DATA4_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA4_update_pad_ctl_MASK)
#define IOMUXD_EMMC0_DATA4_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_EMMC0_DATA4_update_mux_mode_SHIFT (31U)
#define IOMUXD_EMMC0_DATA4_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA4_update_mux_mode_MASK)
/*! @} */

/*! @name EMMC0_DATA5 - EMMC0_DATA5 */
/*! @{ */
#define IOMUXD_EMMC0_DATA5_PDRV_MASK             (0x1U)
#define IOMUXD_EMMC0_DATA5_PDRV_SHIFT            (0U)
#define IOMUXD_EMMC0_DATA5_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA5_PDRV_MASK)
#define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_MASK (0x1EU)
#define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_SHIFT (1U)
#define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_MASK)
#define IOMUXD_EMMC0_DATA5_PULL_MASK             (0x60U)
#define IOMUXD_EMMC0_DATA5_PULL_SHIFT            (5U)
#define IOMUXD_EMMC0_DATA5_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_PULL_SHIFT)) & IOMUXD_EMMC0_DATA5_PULL_MASK)
#define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_SHIFT (7U)
#define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_MASK)
#define IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_EMMC0_DATA5_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_MASK)
#define IOMUXD_EMMC0_DATA5_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_EMMC0_DATA5_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_EMMC0_DATA5_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA5_WAKEUP_MASK_MASK)
#define IOMUXD_EMMC0_DATA5_lp_config_MASK        (0x1800000U)
#define IOMUXD_EMMC0_DATA5_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_EMMC0_DATA5_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA5_lp_config_MASK)
#define IOMUXD_EMMC0_DATA5_sw_config_MASK        (0x6000000U)
#define IOMUXD_EMMC0_DATA5_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_EMMC0_DATA5_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA5_sw_config_MASK)
#define IOMUXD_EMMC0_DATA5_mux_mode_MASK         (0x38000000U)
#define IOMUXD_EMMC0_DATA5_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.EMMC0.DATA5
 *  0b001..CONN.NAND.DATA05
 *  0b011..LSIO.GPIO5.IO09
 */
#define IOMUXD_EMMC0_DATA5_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA5_mux_mode_MASK)
#define IOMUXD_EMMC0_DATA5_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_EMMC0_DATA5_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_EMMC0_DATA5_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA5_update_pad_ctl_MASK)
#define IOMUXD_EMMC0_DATA5_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_EMMC0_DATA5_update_mux_mode_SHIFT (31U)
#define IOMUXD_EMMC0_DATA5_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA5_update_mux_mode_MASK)
/*! @} */

/*! @name EMMC0_DATA6 - EMMC0_DATA6 */
/*! @{ */
#define IOMUXD_EMMC0_DATA6_PDRV_MASK             (0x1U)
#define IOMUXD_EMMC0_DATA6_PDRV_SHIFT            (0U)
#define IOMUXD_EMMC0_DATA6_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA6_PDRV_MASK)
#define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_MASK (0x1EU)
#define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_SHIFT (1U)
#define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_MASK)
#define IOMUXD_EMMC0_DATA6_PULL_MASK             (0x60U)
#define IOMUXD_EMMC0_DATA6_PULL_SHIFT            (5U)
#define IOMUXD_EMMC0_DATA6_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_PULL_SHIFT)) & IOMUXD_EMMC0_DATA6_PULL_MASK)
#define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_SHIFT (7U)
#define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_MASK)
#define IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_EMMC0_DATA6_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_MASK)
#define IOMUXD_EMMC0_DATA6_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_EMMC0_DATA6_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_EMMC0_DATA6_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA6_WAKEUP_MASK_MASK)
#define IOMUXD_EMMC0_DATA6_lp_config_MASK        (0x1800000U)
#define IOMUXD_EMMC0_DATA6_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_EMMC0_DATA6_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA6_lp_config_MASK)
#define IOMUXD_EMMC0_DATA6_sw_config_MASK        (0x6000000U)
#define IOMUXD_EMMC0_DATA6_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_EMMC0_DATA6_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA6_sw_config_MASK)
#define IOMUXD_EMMC0_DATA6_mux_mode_MASK         (0x38000000U)
#define IOMUXD_EMMC0_DATA6_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.EMMC0.DATA6
 *  0b001..CONN.NAND.DATA06
 *  0b011..LSIO.GPIO5.IO10
 */
#define IOMUXD_EMMC0_DATA6_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA6_mux_mode_MASK)
#define IOMUXD_EMMC0_DATA6_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_EMMC0_DATA6_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_EMMC0_DATA6_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA6_update_pad_ctl_MASK)
#define IOMUXD_EMMC0_DATA6_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_EMMC0_DATA6_update_mux_mode_SHIFT (31U)
#define IOMUXD_EMMC0_DATA6_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA6_update_mux_mode_MASK)
/*! @} */

/*! @name EMMC0_DATA7 - EMMC0_DATA7 */
/*! @{ */
#define IOMUXD_EMMC0_DATA7_PDRV_MASK             (0x1U)
#define IOMUXD_EMMC0_DATA7_PDRV_SHIFT            (0U)
#define IOMUXD_EMMC0_DATA7_PDRV(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA7_PDRV_MASK)
#define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_MASK (0x1EU)
#define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_SHIFT (1U)
#define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_MASK)
#define IOMUXD_EMMC0_DATA7_PULL_MASK             (0x60U)
#define IOMUXD_EMMC0_DATA7_PULL_SHIFT            (5U)
#define IOMUXD_EMMC0_DATA7_PULL(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_PULL_SHIFT)) & IOMUXD_EMMC0_DATA7_PULL_MASK)
#define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_SHIFT (7U)
#define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_MASK)
#define IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_MASK      (0x380000U)
#define IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_SHIFT     (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_EMMC0_DATA7_WAKEUP_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_MASK)
#define IOMUXD_EMMC0_DATA7_WAKEUP_MASK_MASK      (0x400000U)
#define IOMUXD_EMMC0_DATA7_WAKEUP_MASK_SHIFT     (22U)
#define IOMUXD_EMMC0_DATA7_WAKEUP_MASK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA7_WAKEUP_MASK_MASK)
#define IOMUXD_EMMC0_DATA7_lp_config_MASK        (0x1800000U)
#define IOMUXD_EMMC0_DATA7_lp_config_SHIFT       (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_EMMC0_DATA7_lp_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA7_lp_config_MASK)
#define IOMUXD_EMMC0_DATA7_sw_config_MASK        (0x6000000U)
#define IOMUXD_EMMC0_DATA7_sw_config_SHIFT       (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_EMMC0_DATA7_sw_config(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA7_sw_config_MASK)
#define IOMUXD_EMMC0_DATA7_mux_mode_MASK         (0x38000000U)
#define IOMUXD_EMMC0_DATA7_mux_mode_SHIFT        (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.EMMC0.DATA7
 *  0b001..CONN.NAND.DATA07
 *  0b011..LSIO.GPIO5.IO11
 */
#define IOMUXD_EMMC0_DATA7_mux_mode(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA7_mux_mode_MASK)
#define IOMUXD_EMMC0_DATA7_update_pad_ctl_MASK   (0x40000000U)
#define IOMUXD_EMMC0_DATA7_update_pad_ctl_SHIFT  (30U)
#define IOMUXD_EMMC0_DATA7_update_pad_ctl(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA7_update_pad_ctl_MASK)
#define IOMUXD_EMMC0_DATA7_update_mux_mode_MASK  (0x80000000U)
#define IOMUXD_EMMC0_DATA7_update_mux_mode_SHIFT (31U)
#define IOMUXD_EMMC0_DATA7_update_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA7_update_mux_mode_MASK)
/*! @} */

/*! @name EMMC0_STROBE - EMMC0_STROBE */
/*! @{ */
#define IOMUXD_EMMC0_STROBE_PDRV_MASK            (0x1U)
#define IOMUXD_EMMC0_STROBE_PDRV_SHIFT           (0U)
#define IOMUXD_EMMC0_STROBE_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_PDRV_SHIFT)) & IOMUXD_EMMC0_STROBE_PDRV_MASK)
#define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_MASK (0x1EU)
#define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_SHIFT (1U)
#define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_MASK)
#define IOMUXD_EMMC0_STROBE_PULL_MASK            (0x60U)
#define IOMUXD_EMMC0_STROBE_PULL_SHIFT           (5U)
#define IOMUXD_EMMC0_STROBE_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_PULL_SHIFT)) & IOMUXD_EMMC0_STROBE_PULL_MASK)
#define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_SHIFT (7U)
#define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_MASK)
#define IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_EMMC0_STROBE_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_MASK)
#define IOMUXD_EMMC0_STROBE_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_EMMC0_STROBE_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_EMMC0_STROBE_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_STROBE_WAKEUP_MASK_MASK)
#define IOMUXD_EMMC0_STROBE_lp_config_MASK       (0x1800000U)
#define IOMUXD_EMMC0_STROBE_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_EMMC0_STROBE_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_lp_config_SHIFT)) & IOMUXD_EMMC0_STROBE_lp_config_MASK)
#define IOMUXD_EMMC0_STROBE_sw_config_MASK       (0x6000000U)
#define IOMUXD_EMMC0_STROBE_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_EMMC0_STROBE_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_sw_config_SHIFT)) & IOMUXD_EMMC0_STROBE_sw_config_MASK)
#define IOMUXD_EMMC0_STROBE_mux_mode_MASK        (0x38000000U)
#define IOMUXD_EMMC0_STROBE_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.EMMC0.STROBE
 *  0b001..CONN.NAND.CLE
 *  0b011..LSIO.GPIO5.IO12
 */
#define IOMUXD_EMMC0_STROBE_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_mux_mode_SHIFT)) & IOMUXD_EMMC0_STROBE_mux_mode_MASK)
#define IOMUXD_EMMC0_STROBE_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_EMMC0_STROBE_update_pad_ctl_SHIFT (30U)
#define IOMUXD_EMMC0_STROBE_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_STROBE_update_pad_ctl_MASK)
#define IOMUXD_EMMC0_STROBE_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_EMMC0_STROBE_update_mux_mode_SHIFT (31U)
#define IOMUXD_EMMC0_STROBE_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_STROBE_update_mux_mode_MASK)
/*! @} */

/*! @name EMMC0_RESET_B - EMMC0_RESET_B */
/*! @{ */
#define IOMUXD_EMMC0_RESET_B_PDRV_MASK           (0x1U)
#define IOMUXD_EMMC0_RESET_B_PDRV_SHIFT          (0U)
#define IOMUXD_EMMC0_RESET_B_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_PDRV_SHIFT)) & IOMUXD_EMMC0_RESET_B_PDRV_MASK)
#define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_MASK (0x1EU)
#define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_SHIFT (1U)
#define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_MASK)
#define IOMUXD_EMMC0_RESET_B_PULL_MASK           (0x60U)
#define IOMUXD_EMMC0_RESET_B_PULL_SHIFT          (5U)
#define IOMUXD_EMMC0_RESET_B_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_PULL_SHIFT)) & IOMUXD_EMMC0_RESET_B_PULL_MASK)
#define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_SHIFT (7U)
#define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_MASK)
#define IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_MASK    (0x380000U)
#define IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_SHIFT   (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_MASK)
#define IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_MASK    (0x400000U)
#define IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_SHIFT   (22U)
#define IOMUXD_EMMC0_RESET_B_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_MASK)
#define IOMUXD_EMMC0_RESET_B_lp_config_MASK      (0x1800000U)
#define IOMUXD_EMMC0_RESET_B_lp_config_SHIFT     (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_EMMC0_RESET_B_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_lp_config_SHIFT)) & IOMUXD_EMMC0_RESET_B_lp_config_MASK)
#define IOMUXD_EMMC0_RESET_B_sw_config_MASK      (0x6000000U)
#define IOMUXD_EMMC0_RESET_B_sw_config_SHIFT     (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_EMMC0_RESET_B_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_sw_config_SHIFT)) & IOMUXD_EMMC0_RESET_B_sw_config_MASK)
#define IOMUXD_EMMC0_RESET_B_mux_mode_MASK       (0x38000000U)
#define IOMUXD_EMMC0_RESET_B_mux_mode_SHIFT      (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.EMMC0.RESET_B
 *  0b001..CONN.NAND.WP_B
 *  0b010..CONN.USDHC1.VSELECT
 *  0b011..LSIO.GPIO5.IO13
 */
#define IOMUXD_EMMC0_RESET_B_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_mux_mode_SHIFT)) & IOMUXD_EMMC0_RESET_B_mux_mode_MASK)
#define IOMUXD_EMMC0_RESET_B_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_EMMC0_RESET_B_update_pad_ctl_SHIFT (30U)
#define IOMUXD_EMMC0_RESET_B_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_RESET_B_update_pad_ctl_MASK)
#define IOMUXD_EMMC0_RESET_B_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_EMMC0_RESET_B_update_mux_mode_SHIFT (31U)
#define IOMUXD_EMMC0_RESET_B_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_RESET_B_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX - IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC1_CLK - USDHC1_CLK */
/*! @{ */
#define IOMUXD_USDHC1_CLK_PDRV_MASK              (0x1U)
#define IOMUXD_USDHC1_CLK_PDRV_SHIFT             (0U)
#define IOMUXD_USDHC1_CLK_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_PDRV_SHIFT)) & IOMUXD_USDHC1_CLK_PDRV_MASK)
#define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_MASK)
#define IOMUXD_USDHC1_CLK_PULL_MASK              (0x60U)
#define IOMUXD_USDHC1_CLK_PULL_SHIFT             (5U)
#define IOMUXD_USDHC1_CLK_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_PULL_SHIFT)) & IOMUXD_USDHC1_CLK_PULL_MASK)
#define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_MASK)
#define IOMUXD_USDHC1_CLK_WAKEUP_CTRL_MASK       (0x380000U)
#define IOMUXD_USDHC1_CLK_WAKEUP_CTRL_SHIFT      (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC1_CLK_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_CLK_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC1_CLK_WAKEUP_MASK_MASK       (0x400000U)
#define IOMUXD_USDHC1_CLK_WAKEUP_MASK_SHIFT      (22U)
#define IOMUXD_USDHC1_CLK_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_CLK_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC1_CLK_lp_config_MASK         (0x1800000U)
#define IOMUXD_USDHC1_CLK_lp_config_SHIFT        (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC1_CLK_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_lp_config_SHIFT)) & IOMUXD_USDHC1_CLK_lp_config_MASK)
#define IOMUXD_USDHC1_CLK_sw_config_MASK         (0x6000000U)
#define IOMUXD_USDHC1_CLK_sw_config_SHIFT        (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC1_CLK_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_sw_config_SHIFT)) & IOMUXD_USDHC1_CLK_sw_config_MASK)
#define IOMUXD_USDHC1_CLK_mux_mode_MASK          (0x38000000U)
#define IOMUXD_USDHC1_CLK_mux_mode_SHIFT         (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC1.CLK
 *  0b001..AUD.MQS.R
 */
#define IOMUXD_USDHC1_CLK_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_mux_mode_SHIFT)) & IOMUXD_USDHC1_CLK_mux_mode_MASK)
#define IOMUXD_USDHC1_CLK_update_pad_ctl_MASK    (0x40000000U)
#define IOMUXD_USDHC1_CLK_update_pad_ctl_SHIFT   (30U)
#define IOMUXD_USDHC1_CLK_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_CLK_update_pad_ctl_MASK)
#define IOMUXD_USDHC1_CLK_update_mux_mode_MASK   (0x80000000U)
#define IOMUXD_USDHC1_CLK_update_mux_mode_SHIFT  (31U)
#define IOMUXD_USDHC1_CLK_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_CLK_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC1_CMD - USDHC1_CMD */
/*! @{ */
#define IOMUXD_USDHC1_CMD_PDRV_MASK              (0x1U)
#define IOMUXD_USDHC1_CMD_PDRV_SHIFT             (0U)
#define IOMUXD_USDHC1_CMD_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_PDRV_SHIFT)) & IOMUXD_USDHC1_CMD_PDRV_MASK)
#define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_MASK)
#define IOMUXD_USDHC1_CMD_PULL_MASK              (0x60U)
#define IOMUXD_USDHC1_CMD_PULL_SHIFT             (5U)
#define IOMUXD_USDHC1_CMD_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_PULL_SHIFT)) & IOMUXD_USDHC1_CMD_PULL_MASK)
#define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_MASK)
#define IOMUXD_USDHC1_CMD_WAKEUP_CTRL_MASK       (0x380000U)
#define IOMUXD_USDHC1_CMD_WAKEUP_CTRL_SHIFT      (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC1_CMD_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_CMD_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC1_CMD_WAKEUP_MASK_MASK       (0x400000U)
#define IOMUXD_USDHC1_CMD_WAKEUP_MASK_SHIFT      (22U)
#define IOMUXD_USDHC1_CMD_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_CMD_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC1_CMD_lp_config_MASK         (0x1800000U)
#define IOMUXD_USDHC1_CMD_lp_config_SHIFT        (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC1_CMD_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_lp_config_SHIFT)) & IOMUXD_USDHC1_CMD_lp_config_MASK)
#define IOMUXD_USDHC1_CMD_sw_config_MASK         (0x6000000U)
#define IOMUXD_USDHC1_CMD_sw_config_SHIFT        (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC1_CMD_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_sw_config_SHIFT)) & IOMUXD_USDHC1_CMD_sw_config_MASK)
#define IOMUXD_USDHC1_CMD_mux_mode_MASK          (0x38000000U)
#define IOMUXD_USDHC1_CMD_mux_mode_SHIFT         (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC1.CMD
 *  0b001..AUD.MQS.L
 *  0b011..LSIO.GPIO5.IO14
 */
#define IOMUXD_USDHC1_CMD_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_mux_mode_SHIFT)) & IOMUXD_USDHC1_CMD_mux_mode_MASK)
#define IOMUXD_USDHC1_CMD_update_pad_ctl_MASK    (0x40000000U)
#define IOMUXD_USDHC1_CMD_update_pad_ctl_SHIFT   (30U)
#define IOMUXD_USDHC1_CMD_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_CMD_update_pad_ctl_MASK)
#define IOMUXD_USDHC1_CMD_update_mux_mode_MASK   (0x80000000U)
#define IOMUXD_USDHC1_CMD_update_mux_mode_SHIFT  (31U)
#define IOMUXD_USDHC1_CMD_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_CMD_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC1_DATA0 - USDHC1_DATA0 */
/*! @{ */
#define IOMUXD_USDHC1_DATA0_PDRV_MASK            (0x1U)
#define IOMUXD_USDHC1_DATA0_PDRV_SHIFT           (0U)
#define IOMUXD_USDHC1_DATA0_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA0_PDRV_MASK)
#define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_MASK)
#define IOMUXD_USDHC1_DATA0_PULL_MASK            (0x60U)
#define IOMUXD_USDHC1_DATA0_PULL_SHIFT           (5U)
#define IOMUXD_USDHC1_DATA0_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_PULL_SHIFT)) & IOMUXD_USDHC1_DATA0_PULL_MASK)
#define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_MASK)
#define IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC1_DATA0_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC1_DATA0_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_USDHC1_DATA0_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_USDHC1_DATA0_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA0_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC1_DATA0_lp_config_MASK       (0x1800000U)
#define IOMUXD_USDHC1_DATA0_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC1_DATA0_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA0_lp_config_MASK)
#define IOMUXD_USDHC1_DATA0_sw_config_MASK       (0x6000000U)
#define IOMUXD_USDHC1_DATA0_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC1_DATA0_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA0_sw_config_MASK)
#define IOMUXD_USDHC1_DATA0_mux_mode_MASK        (0x38000000U)
#define IOMUXD_USDHC1_DATA0_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC1.DATA0
 *  0b001..CONN.NAND.RE_N
 *  0b011..LSIO.GPIO5.IO15
 */
#define IOMUXD_USDHC1_DATA0_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA0_mux_mode_MASK)
#define IOMUXD_USDHC1_DATA0_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_USDHC1_DATA0_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC1_DATA0_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA0_update_pad_ctl_MASK)
#define IOMUXD_USDHC1_DATA0_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC1_DATA0_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC1_DATA0_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA0_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_3_0 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_CLK_MASK   (0x1U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_CLK_SHIFT  (0U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_CLK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_EMMC0_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_EMMC0_CLK_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_CMD_MASK   (0x2U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_CMD_SHIFT  (1U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_CMD(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_EMMC0_CMD_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_EMMC0_CMD_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA0_MASK (0x4U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA0_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA0(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA0_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA1_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA1_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA1(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA1_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA2_MASK (0x10U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA2_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA2(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA2_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA3_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA3_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA3(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA3_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA4_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA4_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA4(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA4_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA4_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA5_MASK (0x80U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA5_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA5(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA5_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA5_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA6_MASK (0x100U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA6_SHIFT (8U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA6(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA6_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA6_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA7_MASK (0x200U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA7_SHIFT (9U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA7(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA7_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_EMMC0_DATA7_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_STROBE_MASK (0x400U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_STROBE_SHIFT (10U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_STROBE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_EMMC0_STROBE_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_EMMC0_STROBE_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_RESET_B_MASK (0x800U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_RESET_B_SHIFT (11U)
#define IOMUXD_IOMUXD_GROUP_3_0_EMMC0_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_EMMC0_RESET_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_EMMC0_RESET_B_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_12_12_MASK (0x1000U)
#define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_12_12_SHIFT (12U)
#define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_12_12_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_12_12_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_USDHC1_CLK_MASK  (0x2000U)
#define IOMUXD_IOMUXD_GROUP_3_0_USDHC1_CLK_SHIFT (13U)
#define IOMUXD_IOMUXD_GROUP_3_0_USDHC1_CLK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_USDHC1_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_USDHC1_CLK_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_USDHC1_CMD_MASK  (0x4000U)
#define IOMUXD_IOMUXD_GROUP_3_0_USDHC1_CMD_SHIFT (14U)
#define IOMUXD_IOMUXD_GROUP_3_0_USDHC1_CMD(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_USDHC1_CMD_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_USDHC1_CMD_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_USDHC1_DATA0_MASK (0x8000U)
#define IOMUXD_IOMUXD_GROUP_3_0_USDHC1_DATA0_SHIFT (15U)
#define IOMUXD_IOMUXD_GROUP_3_0_USDHC1_DATA0(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_USDHC1_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_USDHC1_DATA0_MASK)
#define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_16_31_MASK (0xFFFF0000U)
#define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_16_31_SHIFT (16U)
#define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_16_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_16_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_16_31_MASK)
/*! @} */

/*! @name USDHC1_DATA1 - USDHC1_DATA1 */
/*! @{ */
#define IOMUXD_USDHC1_DATA1_PDRV_MASK            (0x1U)
#define IOMUXD_USDHC1_DATA1_PDRV_SHIFT           (0U)
#define IOMUXD_USDHC1_DATA1_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA1_PDRV_MASK)
#define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_MASK)
#define IOMUXD_USDHC1_DATA1_PULL_MASK            (0x60U)
#define IOMUXD_USDHC1_DATA1_PULL_SHIFT           (5U)
#define IOMUXD_USDHC1_DATA1_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_PULL_SHIFT)) & IOMUXD_USDHC1_DATA1_PULL_MASK)
#define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_MASK)
#define IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC1_DATA1_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC1_DATA1_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_USDHC1_DATA1_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_USDHC1_DATA1_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA1_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC1_DATA1_lp_config_MASK       (0x1800000U)
#define IOMUXD_USDHC1_DATA1_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC1_DATA1_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA1_lp_config_MASK)
#define IOMUXD_USDHC1_DATA1_sw_config_MASK       (0x6000000U)
#define IOMUXD_USDHC1_DATA1_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC1_DATA1_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA1_sw_config_MASK)
#define IOMUXD_USDHC1_DATA1_mux_mode_MASK        (0x38000000U)
#define IOMUXD_USDHC1_DATA1_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC1.DATA1
 *  0b001..CONN.NAND.RE_P
 *  0b011..LSIO.GPIO5.IO16
 */
#define IOMUXD_USDHC1_DATA1_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA1_mux_mode_MASK)
#define IOMUXD_USDHC1_DATA1_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_USDHC1_DATA1_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC1_DATA1_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA1_update_pad_ctl_MASK)
#define IOMUXD_USDHC1_DATA1_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC1_DATA1_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC1_DATA1_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA1_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_CTL_NAND_RE_P_N - IOMUXD_CTL_NAND_RE_P_N */
/*! @{ */
#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_MASK (0x1U)
#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_SHIFT (0U)
#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_MASK)
#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_MASK (0x3FFFFFFEU)
#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_SHIFT (1U)
#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_MASK)
#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC1_DATA2 - USDHC1_DATA2 */
/*! @{ */
#define IOMUXD_USDHC1_DATA2_PDRV_MASK            (0x1U)
#define IOMUXD_USDHC1_DATA2_PDRV_SHIFT           (0U)
#define IOMUXD_USDHC1_DATA2_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA2_PDRV_MASK)
#define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_MASK)
#define IOMUXD_USDHC1_DATA2_PULL_MASK            (0x60U)
#define IOMUXD_USDHC1_DATA2_PULL_SHIFT           (5U)
#define IOMUXD_USDHC1_DATA2_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_PULL_SHIFT)) & IOMUXD_USDHC1_DATA2_PULL_MASK)
#define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_MASK)
#define IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC1_DATA2_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC1_DATA2_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_USDHC1_DATA2_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_USDHC1_DATA2_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA2_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC1_DATA2_lp_config_MASK       (0x1800000U)
#define IOMUXD_USDHC1_DATA2_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC1_DATA2_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA2_lp_config_MASK)
#define IOMUXD_USDHC1_DATA2_sw_config_MASK       (0x6000000U)
#define IOMUXD_USDHC1_DATA2_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC1_DATA2_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA2_sw_config_MASK)
#define IOMUXD_USDHC1_DATA2_mux_mode_MASK        (0x38000000U)
#define IOMUXD_USDHC1_DATA2_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC1.DATA2
 *  0b001..CONN.NAND.DQS_N
 *  0b011..LSIO.GPIO5.IO17
 */
#define IOMUXD_USDHC1_DATA2_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA2_mux_mode_MASK)
#define IOMUXD_USDHC1_DATA2_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_USDHC1_DATA2_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC1_DATA2_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA2_update_pad_ctl_MASK)
#define IOMUXD_USDHC1_DATA2_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC1_DATA2_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC1_DATA2_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA2_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC1_DATA3 - USDHC1_DATA3 */
/*! @{ */
#define IOMUXD_USDHC1_DATA3_PDRV_MASK            (0x1U)
#define IOMUXD_USDHC1_DATA3_PDRV_SHIFT           (0U)
#define IOMUXD_USDHC1_DATA3_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA3_PDRV_MASK)
#define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_MASK)
#define IOMUXD_USDHC1_DATA3_PULL_MASK            (0x60U)
#define IOMUXD_USDHC1_DATA3_PULL_SHIFT           (5U)
#define IOMUXD_USDHC1_DATA3_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_PULL_SHIFT)) & IOMUXD_USDHC1_DATA3_PULL_MASK)
#define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_MASK)
#define IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC1_DATA3_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC1_DATA3_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_USDHC1_DATA3_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_USDHC1_DATA3_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA3_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC1_DATA3_lp_config_MASK       (0x1800000U)
#define IOMUXD_USDHC1_DATA3_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC1_DATA3_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA3_lp_config_MASK)
#define IOMUXD_USDHC1_DATA3_sw_config_MASK       (0x6000000U)
#define IOMUXD_USDHC1_DATA3_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC1_DATA3_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA3_sw_config_MASK)
#define IOMUXD_USDHC1_DATA3_mux_mode_MASK        (0x38000000U)
#define IOMUXD_USDHC1_DATA3_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC1.DATA3
 *  0b001..CONN.NAND.DQS_P
 *  0b011..LSIO.GPIO5.IO18
 */
#define IOMUXD_USDHC1_DATA3_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA3_mux_mode_MASK)
#define IOMUXD_USDHC1_DATA3_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_USDHC1_DATA3_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC1_DATA3_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA3_update_pad_ctl_MASK)
#define IOMUXD_USDHC1_DATA3_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC1_DATA3_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC1_DATA3_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA3_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_CTL_NAND_DQS_P_N - IOMUXD_CTL_NAND_DQS_P_N */
/*! @{ */
#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_MASK (0x1U)
#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_SHIFT (0U)
#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_MASK)
#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_MASK (0x3FFFFFFEU)
#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_SHIFT (1U)
#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_MASK)
#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC1_DATA4 - USDHC1_DATA4 */
/*! @{ */
#define IOMUXD_USDHC1_DATA4_PDRV_MASK            (0x1U)
#define IOMUXD_USDHC1_DATA4_PDRV_SHIFT           (0U)
#define IOMUXD_USDHC1_DATA4_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA4_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA4_PDRV_MASK)
#define IOMUXD_USDHC1_DATA4_USDHC1_DATA4_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC1_DATA4_USDHC1_DATA4_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC1_DATA4_USDHC1_DATA4_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA4_USDHC1_DATA4_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA4_USDHC1_DATA4_reserved_1_4_MASK)
#define IOMUXD_USDHC1_DATA4_PULL_MASK            (0x60U)
#define IOMUXD_USDHC1_DATA4_PULL_SHIFT           (5U)
#define IOMUXD_USDHC1_DATA4_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA4_PULL_SHIFT)) & IOMUXD_USDHC1_DATA4_PULL_MASK)
#define IOMUXD_USDHC1_DATA4_USDHC1_DATA4_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC1_DATA4_USDHC1_DATA4_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC1_DATA4_USDHC1_DATA4_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA4_USDHC1_DATA4_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA4_USDHC1_DATA4_reserved_7_18_MASK)
#define IOMUXD_USDHC1_DATA4_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_USDHC1_DATA4_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC1_DATA4_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA4_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA4_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC1_DATA4_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_USDHC1_DATA4_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_USDHC1_DATA4_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA4_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA4_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC1_DATA4_lp_config_MASK       (0x1800000U)
#define IOMUXD_USDHC1_DATA4_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC1_DATA4_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA4_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA4_lp_config_MASK)
#define IOMUXD_USDHC1_DATA4_sw_config_MASK       (0x6000000U)
#define IOMUXD_USDHC1_DATA4_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC1_DATA4_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA4_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA4_sw_config_MASK)
#define IOMUXD_USDHC1_DATA4_mux_mode_MASK        (0x38000000U)
#define IOMUXD_USDHC1_DATA4_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC1.DATA4
 *  0b001..CONN.NAND.CE0_B
 *  0b010..AUD.MQS.R
 *  0b011..LSIO.GPIO5.IO19
 */
#define IOMUXD_USDHC1_DATA4_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA4_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA4_mux_mode_MASK)
#define IOMUXD_USDHC1_DATA4_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_USDHC1_DATA4_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC1_DATA4_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA4_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA4_update_pad_ctl_MASK)
#define IOMUXD_USDHC1_DATA4_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC1_DATA4_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC1_DATA4_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA4_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA4_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC1_DATA5 - USDHC1_DATA5 */
/*! @{ */
#define IOMUXD_USDHC1_DATA5_PDRV_MASK            (0x1U)
#define IOMUXD_USDHC1_DATA5_PDRV_SHIFT           (0U)
#define IOMUXD_USDHC1_DATA5_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA5_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA5_PDRV_MASK)
#define IOMUXD_USDHC1_DATA5_USDHC1_DATA5_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC1_DATA5_USDHC1_DATA5_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC1_DATA5_USDHC1_DATA5_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA5_USDHC1_DATA5_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA5_USDHC1_DATA5_reserved_1_4_MASK)
#define IOMUXD_USDHC1_DATA5_PULL_MASK            (0x60U)
#define IOMUXD_USDHC1_DATA5_PULL_SHIFT           (5U)
#define IOMUXD_USDHC1_DATA5_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA5_PULL_SHIFT)) & IOMUXD_USDHC1_DATA5_PULL_MASK)
#define IOMUXD_USDHC1_DATA5_USDHC1_DATA5_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC1_DATA5_USDHC1_DATA5_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC1_DATA5_USDHC1_DATA5_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA5_USDHC1_DATA5_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA5_USDHC1_DATA5_reserved_7_18_MASK)
#define IOMUXD_USDHC1_DATA5_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_USDHC1_DATA5_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC1_DATA5_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA5_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA5_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC1_DATA5_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_USDHC1_DATA5_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_USDHC1_DATA5_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA5_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA5_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC1_DATA5_lp_config_MASK       (0x1800000U)
#define IOMUXD_USDHC1_DATA5_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC1_DATA5_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA5_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA5_lp_config_MASK)
#define IOMUXD_USDHC1_DATA5_sw_config_MASK       (0x6000000U)
#define IOMUXD_USDHC1_DATA5_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC1_DATA5_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA5_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA5_sw_config_MASK)
#define IOMUXD_USDHC1_DATA5_mux_mode_MASK        (0x38000000U)
#define IOMUXD_USDHC1_DATA5_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC1.DATA5
 *  0b001..CONN.NAND.RE_B
 *  0b010..AUD.MQS.L
 *  0b011..LSIO.GPIO5.IO20
 */
#define IOMUXD_USDHC1_DATA5_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA5_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA5_mux_mode_MASK)
#define IOMUXD_USDHC1_DATA5_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_USDHC1_DATA5_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC1_DATA5_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA5_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA5_update_pad_ctl_MASK)
#define IOMUXD_USDHC1_DATA5_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC1_DATA5_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC1_DATA5_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA5_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA5_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC1_DATA6 - USDHC1_DATA6 */
/*! @{ */
#define IOMUXD_USDHC1_DATA6_PDRV_MASK            (0x1U)
#define IOMUXD_USDHC1_DATA6_PDRV_SHIFT           (0U)
#define IOMUXD_USDHC1_DATA6_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA6_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA6_PDRV_MASK)
#define IOMUXD_USDHC1_DATA6_USDHC1_DATA6_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC1_DATA6_USDHC1_DATA6_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC1_DATA6_USDHC1_DATA6_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA6_USDHC1_DATA6_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA6_USDHC1_DATA6_reserved_1_4_MASK)
#define IOMUXD_USDHC1_DATA6_PULL_MASK            (0x60U)
#define IOMUXD_USDHC1_DATA6_PULL_SHIFT           (5U)
#define IOMUXD_USDHC1_DATA6_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA6_PULL_SHIFT)) & IOMUXD_USDHC1_DATA6_PULL_MASK)
#define IOMUXD_USDHC1_DATA6_USDHC1_DATA6_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC1_DATA6_USDHC1_DATA6_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC1_DATA6_USDHC1_DATA6_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA6_USDHC1_DATA6_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA6_USDHC1_DATA6_reserved_7_18_MASK)
#define IOMUXD_USDHC1_DATA6_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_USDHC1_DATA6_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC1_DATA6_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA6_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA6_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC1_DATA6_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_USDHC1_DATA6_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_USDHC1_DATA6_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA6_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA6_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC1_DATA6_lp_config_MASK       (0x1800000U)
#define IOMUXD_USDHC1_DATA6_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC1_DATA6_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA6_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA6_lp_config_MASK)
#define IOMUXD_USDHC1_DATA6_sw_config_MASK       (0x6000000U)
#define IOMUXD_USDHC1_DATA6_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC1_DATA6_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA6_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA6_sw_config_MASK)
#define IOMUXD_USDHC1_DATA6_mux_mode_MASK        (0x38000000U)
#define IOMUXD_USDHC1_DATA6_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC1.DATA6
 *  0b001..CONN.NAND.WE_B
 *  0b010..CONN.USDHC1.WP
 *  0b011..LSIO.GPIO5.IO21
 */
#define IOMUXD_USDHC1_DATA6_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA6_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA6_mux_mode_MASK)
#define IOMUXD_USDHC1_DATA6_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_USDHC1_DATA6_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC1_DATA6_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA6_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA6_update_pad_ctl_MASK)
#define IOMUXD_USDHC1_DATA6_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC1_DATA6_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC1_DATA6_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA6_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA6_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC1_DATA7 - USDHC1_DATA7 */
/*! @{ */
#define IOMUXD_USDHC1_DATA7_PDRV_MASK            (0x1U)
#define IOMUXD_USDHC1_DATA7_PDRV_SHIFT           (0U)
#define IOMUXD_USDHC1_DATA7_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA7_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA7_PDRV_MASK)
#define IOMUXD_USDHC1_DATA7_USDHC1_DATA7_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC1_DATA7_USDHC1_DATA7_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC1_DATA7_USDHC1_DATA7_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA7_USDHC1_DATA7_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA7_USDHC1_DATA7_reserved_1_4_MASK)
#define IOMUXD_USDHC1_DATA7_PULL_MASK            (0x60U)
#define IOMUXD_USDHC1_DATA7_PULL_SHIFT           (5U)
#define IOMUXD_USDHC1_DATA7_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA7_PULL_SHIFT)) & IOMUXD_USDHC1_DATA7_PULL_MASK)
#define IOMUXD_USDHC1_DATA7_USDHC1_DATA7_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC1_DATA7_USDHC1_DATA7_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC1_DATA7_USDHC1_DATA7_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA7_USDHC1_DATA7_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA7_USDHC1_DATA7_reserved_7_18_MASK)
#define IOMUXD_USDHC1_DATA7_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_USDHC1_DATA7_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC1_DATA7_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA7_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA7_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC1_DATA7_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_USDHC1_DATA7_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_USDHC1_DATA7_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA7_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA7_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC1_DATA7_lp_config_MASK       (0x1800000U)
#define IOMUXD_USDHC1_DATA7_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC1_DATA7_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA7_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA7_lp_config_MASK)
#define IOMUXD_USDHC1_DATA7_sw_config_MASK       (0x6000000U)
#define IOMUXD_USDHC1_DATA7_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC1_DATA7_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA7_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA7_sw_config_MASK)
#define IOMUXD_USDHC1_DATA7_mux_mode_MASK        (0x38000000U)
#define IOMUXD_USDHC1_DATA7_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC1.DATA7
 *  0b001..CONN.NAND.ALE
 *  0b010..CONN.USDHC1.CD_B
 *  0b011..LSIO.GPIO5.IO22
 */
#define IOMUXD_USDHC1_DATA7_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA7_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA7_mux_mode_MASK)
#define IOMUXD_USDHC1_DATA7_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_USDHC1_DATA7_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC1_DATA7_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA7_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA7_update_pad_ctl_MASK)
#define IOMUXD_USDHC1_DATA7_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC1_DATA7_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC1_DATA7_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA7_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA7_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC1_STROBE - USDHC1_STROBE */
/*! @{ */
#define IOMUXD_USDHC1_STROBE_PDRV_MASK           (0x1U)
#define IOMUXD_USDHC1_STROBE_PDRV_SHIFT          (0U)
#define IOMUXD_USDHC1_STROBE_PDRV(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_STROBE_PDRV_SHIFT)) & IOMUXD_USDHC1_STROBE_PDRV_MASK)
#define IOMUXD_USDHC1_STROBE_USDHC1_STROBE_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC1_STROBE_USDHC1_STROBE_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC1_STROBE_USDHC1_STROBE_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_STROBE_USDHC1_STROBE_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_STROBE_USDHC1_STROBE_reserved_1_4_MASK)
#define IOMUXD_USDHC1_STROBE_PULL_MASK           (0x60U)
#define IOMUXD_USDHC1_STROBE_PULL_SHIFT          (5U)
#define IOMUXD_USDHC1_STROBE_PULL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_STROBE_PULL_SHIFT)) & IOMUXD_USDHC1_STROBE_PULL_MASK)
#define IOMUXD_USDHC1_STROBE_USDHC1_STROBE_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC1_STROBE_USDHC1_STROBE_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC1_STROBE_USDHC1_STROBE_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_STROBE_USDHC1_STROBE_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_STROBE_USDHC1_STROBE_reserved_7_18_MASK)
#define IOMUXD_USDHC1_STROBE_WAKEUP_CTRL_MASK    (0x380000U)
#define IOMUXD_USDHC1_STROBE_WAKEUP_CTRL_SHIFT   (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC1_STROBE_WAKEUP_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_STROBE_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_STROBE_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC1_STROBE_WAKEUP_MASK_MASK    (0x400000U)
#define IOMUXD_USDHC1_STROBE_WAKEUP_MASK_SHIFT   (22U)
#define IOMUXD_USDHC1_STROBE_WAKEUP_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_STROBE_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_STROBE_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC1_STROBE_lp_config_MASK      (0x1800000U)
#define IOMUXD_USDHC1_STROBE_lp_config_SHIFT     (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC1_STROBE_lp_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_STROBE_lp_config_SHIFT)) & IOMUXD_USDHC1_STROBE_lp_config_MASK)
#define IOMUXD_USDHC1_STROBE_sw_config_MASK      (0x6000000U)
#define IOMUXD_USDHC1_STROBE_sw_config_SHIFT     (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC1_STROBE_sw_config(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_STROBE_sw_config_SHIFT)) & IOMUXD_USDHC1_STROBE_sw_config_MASK)
#define IOMUXD_USDHC1_STROBE_mux_mode_MASK       (0x38000000U)
#define IOMUXD_USDHC1_STROBE_mux_mode_SHIFT      (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC1.STROBE
 *  0b001..CONN.NAND.CE1_B
 *  0b010..CONN.USDHC1.RESET_B
 *  0b011..LSIO.GPIO5.IO23
 */
#define IOMUXD_USDHC1_STROBE_mux_mode(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_STROBE_mux_mode_SHIFT)) & IOMUXD_USDHC1_STROBE_mux_mode_MASK)
#define IOMUXD_USDHC1_STROBE_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_USDHC1_STROBE_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC1_STROBE_update_pad_ctl(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_STROBE_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_STROBE_update_pad_ctl_MASK)
#define IOMUXD_USDHC1_STROBE_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC1_STROBE_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC1_STROBE_update_mux_mode(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_STROBE_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_STROBE_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2 */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC2_CLK - USDHC2_CLK */
/*! @{ */
#define IOMUXD_USDHC2_CLK_PDRV_MASK              (0x1U)
#define IOMUXD_USDHC2_CLK_PDRV_SHIFT             (0U)
#define IOMUXD_USDHC2_CLK_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CLK_PDRV_SHIFT)) & IOMUXD_USDHC2_CLK_PDRV_MASK)
#define IOMUXD_USDHC2_CLK_USDHC2_CLK_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC2_CLK_USDHC2_CLK_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC2_CLK_USDHC2_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CLK_USDHC2_CLK_reserved_1_4_SHIFT)) & IOMUXD_USDHC2_CLK_USDHC2_CLK_reserved_1_4_MASK)
#define IOMUXD_USDHC2_CLK_PULL_MASK              (0x60U)
#define IOMUXD_USDHC2_CLK_PULL_SHIFT             (5U)
#define IOMUXD_USDHC2_CLK_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CLK_PULL_SHIFT)) & IOMUXD_USDHC2_CLK_PULL_MASK)
#define IOMUXD_USDHC2_CLK_USDHC2_CLK_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC2_CLK_USDHC2_CLK_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC2_CLK_USDHC2_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CLK_USDHC2_CLK_reserved_7_18_SHIFT)) & IOMUXD_USDHC2_CLK_USDHC2_CLK_reserved_7_18_MASK)
#define IOMUXD_USDHC2_CLK_WAKEUP_CTRL_MASK       (0x380000U)
#define IOMUXD_USDHC2_CLK_WAKEUP_CTRL_SHIFT      (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC2_CLK_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC2_CLK_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC2_CLK_WAKEUP_MASK_MASK       (0x400000U)
#define IOMUXD_USDHC2_CLK_WAKEUP_MASK_SHIFT      (22U)
#define IOMUXD_USDHC2_CLK_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC2_CLK_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC2_CLK_lp_config_MASK         (0x1800000U)
#define IOMUXD_USDHC2_CLK_lp_config_SHIFT        (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC2_CLK_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CLK_lp_config_SHIFT)) & IOMUXD_USDHC2_CLK_lp_config_MASK)
#define IOMUXD_USDHC2_CLK_sw_config_MASK         (0x6000000U)
#define IOMUXD_USDHC2_CLK_sw_config_SHIFT        (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC2_CLK_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CLK_sw_config_SHIFT)) & IOMUXD_USDHC2_CLK_sw_config_MASK)
#define IOMUXD_USDHC2_CLK_mux_mode_MASK          (0x38000000U)
#define IOMUXD_USDHC2_CLK_mux_mode_SHIFT         (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC2.CLK
 *  0b001..AUD.MQS.R
 *  0b011..LSIO.GPIO5.IO24
 */
#define IOMUXD_USDHC2_CLK_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CLK_mux_mode_SHIFT)) & IOMUXD_USDHC2_CLK_mux_mode_MASK)
#define IOMUXD_USDHC2_CLK_update_pad_ctl_MASK    (0x40000000U)
#define IOMUXD_USDHC2_CLK_update_pad_ctl_SHIFT   (30U)
#define IOMUXD_USDHC2_CLK_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CLK_update_pad_ctl_SHIFT)) & IOMUXD_USDHC2_CLK_update_pad_ctl_MASK)
#define IOMUXD_USDHC2_CLK_update_mux_mode_MASK   (0x80000000U)
#define IOMUXD_USDHC2_CLK_update_mux_mode_SHIFT  (31U)
#define IOMUXD_USDHC2_CLK_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CLK_update_mux_mode_SHIFT)) & IOMUXD_USDHC2_CLK_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC2_CMD - USDHC2_CMD */
/*! @{ */
#define IOMUXD_USDHC2_CMD_PDRV_MASK              (0x1U)
#define IOMUXD_USDHC2_CMD_PDRV_SHIFT             (0U)
#define IOMUXD_USDHC2_CMD_PDRV(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CMD_PDRV_SHIFT)) & IOMUXD_USDHC2_CMD_PDRV_MASK)
#define IOMUXD_USDHC2_CMD_USDHC2_CMD_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC2_CMD_USDHC2_CMD_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC2_CMD_USDHC2_CMD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CMD_USDHC2_CMD_reserved_1_4_SHIFT)) & IOMUXD_USDHC2_CMD_USDHC2_CMD_reserved_1_4_MASK)
#define IOMUXD_USDHC2_CMD_PULL_MASK              (0x60U)
#define IOMUXD_USDHC2_CMD_PULL_SHIFT             (5U)
#define IOMUXD_USDHC2_CMD_PULL(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CMD_PULL_SHIFT)) & IOMUXD_USDHC2_CMD_PULL_MASK)
#define IOMUXD_USDHC2_CMD_USDHC2_CMD_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC2_CMD_USDHC2_CMD_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC2_CMD_USDHC2_CMD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CMD_USDHC2_CMD_reserved_7_18_SHIFT)) & IOMUXD_USDHC2_CMD_USDHC2_CMD_reserved_7_18_MASK)
#define IOMUXD_USDHC2_CMD_WAKEUP_CTRL_MASK       (0x380000U)
#define IOMUXD_USDHC2_CMD_WAKEUP_CTRL_SHIFT      (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC2_CMD_WAKEUP_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CMD_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC2_CMD_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC2_CMD_WAKEUP_MASK_MASK       (0x400000U)
#define IOMUXD_USDHC2_CMD_WAKEUP_MASK_SHIFT      (22U)
#define IOMUXD_USDHC2_CMD_WAKEUP_MASK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CMD_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC2_CMD_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC2_CMD_lp_config_MASK         (0x1800000U)
#define IOMUXD_USDHC2_CMD_lp_config_SHIFT        (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC2_CMD_lp_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CMD_lp_config_SHIFT)) & IOMUXD_USDHC2_CMD_lp_config_MASK)
#define IOMUXD_USDHC2_CMD_sw_config_MASK         (0x6000000U)
#define IOMUXD_USDHC2_CMD_sw_config_SHIFT        (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC2_CMD_sw_config(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CMD_sw_config_SHIFT)) & IOMUXD_USDHC2_CMD_sw_config_MASK)
#define IOMUXD_USDHC2_CMD_mux_mode_MASK          (0x38000000U)
#define IOMUXD_USDHC2_CMD_mux_mode_SHIFT         (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC2.CMD
 *  0b001..AUD.MQS.L
 *  0b011..LSIO.GPIO5.IO25
 */
#define IOMUXD_USDHC2_CMD_mux_mode(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CMD_mux_mode_SHIFT)) & IOMUXD_USDHC2_CMD_mux_mode_MASK)
#define IOMUXD_USDHC2_CMD_update_pad_ctl_MASK    (0x40000000U)
#define IOMUXD_USDHC2_CMD_update_pad_ctl_SHIFT   (30U)
#define IOMUXD_USDHC2_CMD_update_pad_ctl(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CMD_update_pad_ctl_SHIFT)) & IOMUXD_USDHC2_CMD_update_pad_ctl_MASK)
#define IOMUXD_USDHC2_CMD_update_mux_mode_MASK   (0x80000000U)
#define IOMUXD_USDHC2_CMD_update_mux_mode_SHIFT  (31U)
#define IOMUXD_USDHC2_CMD_update_mux_mode(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_CMD_update_mux_mode_SHIFT)) & IOMUXD_USDHC2_CMD_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC2_DATA0 - USDHC2_DATA0 */
/*! @{ */
#define IOMUXD_USDHC2_DATA0_PDRV_MASK            (0x1U)
#define IOMUXD_USDHC2_DATA0_PDRV_SHIFT           (0U)
#define IOMUXD_USDHC2_DATA0_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA0_PDRV_SHIFT)) & IOMUXD_USDHC2_DATA0_PDRV_MASK)
#define IOMUXD_USDHC2_DATA0_USDHC2_DATA0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC2_DATA0_USDHC2_DATA0_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC2_DATA0_USDHC2_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA0_USDHC2_DATA0_reserved_1_4_SHIFT)) & IOMUXD_USDHC2_DATA0_USDHC2_DATA0_reserved_1_4_MASK)
#define IOMUXD_USDHC2_DATA0_PULL_MASK            (0x60U)
#define IOMUXD_USDHC2_DATA0_PULL_SHIFT           (5U)
#define IOMUXD_USDHC2_DATA0_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA0_PULL_SHIFT)) & IOMUXD_USDHC2_DATA0_PULL_MASK)
#define IOMUXD_USDHC2_DATA0_USDHC2_DATA0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC2_DATA0_USDHC2_DATA0_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC2_DATA0_USDHC2_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA0_USDHC2_DATA0_reserved_7_18_SHIFT)) & IOMUXD_USDHC2_DATA0_USDHC2_DATA0_reserved_7_18_MASK)
#define IOMUXD_USDHC2_DATA0_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_USDHC2_DATA0_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC2_DATA0_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC2_DATA0_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC2_DATA0_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_USDHC2_DATA0_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_USDHC2_DATA0_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC2_DATA0_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC2_DATA0_lp_config_MASK       (0x1800000U)
#define IOMUXD_USDHC2_DATA0_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC2_DATA0_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA0_lp_config_SHIFT)) & IOMUXD_USDHC2_DATA0_lp_config_MASK)
#define IOMUXD_USDHC2_DATA0_sw_config_MASK       (0x6000000U)
#define IOMUXD_USDHC2_DATA0_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC2_DATA0_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA0_sw_config_SHIFT)) & IOMUXD_USDHC2_DATA0_sw_config_MASK)
#define IOMUXD_USDHC2_DATA0_mux_mode_MASK        (0x38000000U)
#define IOMUXD_USDHC2_DATA0_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC2.DATA0
 *  0b001..DMA.UART4.RX
 *  0b011..LSIO.GPIO5.IO26
 */
#define IOMUXD_USDHC2_DATA0_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA0_mux_mode_SHIFT)) & IOMUXD_USDHC2_DATA0_mux_mode_MASK)
#define IOMUXD_USDHC2_DATA0_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_USDHC2_DATA0_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC2_DATA0_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_USDHC2_DATA0_update_pad_ctl_MASK)
#define IOMUXD_USDHC2_DATA0_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC2_DATA0_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC2_DATA0_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA0_update_mux_mode_SHIFT)) & IOMUXD_USDHC2_DATA0_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC2_DATA1 - USDHC2_DATA1 */
/*! @{ */
#define IOMUXD_USDHC2_DATA1_PDRV_MASK            (0x1U)
#define IOMUXD_USDHC2_DATA1_PDRV_SHIFT           (0U)
#define IOMUXD_USDHC2_DATA1_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA1_PDRV_SHIFT)) & IOMUXD_USDHC2_DATA1_PDRV_MASK)
#define IOMUXD_USDHC2_DATA1_USDHC2_DATA1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC2_DATA1_USDHC2_DATA1_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC2_DATA1_USDHC2_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA1_USDHC2_DATA1_reserved_1_4_SHIFT)) & IOMUXD_USDHC2_DATA1_USDHC2_DATA1_reserved_1_4_MASK)
#define IOMUXD_USDHC2_DATA1_PULL_MASK            (0x60U)
#define IOMUXD_USDHC2_DATA1_PULL_SHIFT           (5U)
#define IOMUXD_USDHC2_DATA1_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA1_PULL_SHIFT)) & IOMUXD_USDHC2_DATA1_PULL_MASK)
#define IOMUXD_USDHC2_DATA1_USDHC2_DATA1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC2_DATA1_USDHC2_DATA1_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC2_DATA1_USDHC2_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA1_USDHC2_DATA1_reserved_7_18_SHIFT)) & IOMUXD_USDHC2_DATA1_USDHC2_DATA1_reserved_7_18_MASK)
#define IOMUXD_USDHC2_DATA1_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_USDHC2_DATA1_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC2_DATA1_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC2_DATA1_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC2_DATA1_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_USDHC2_DATA1_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_USDHC2_DATA1_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC2_DATA1_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC2_DATA1_lp_config_MASK       (0x1800000U)
#define IOMUXD_USDHC2_DATA1_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC2_DATA1_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA1_lp_config_SHIFT)) & IOMUXD_USDHC2_DATA1_lp_config_MASK)
#define IOMUXD_USDHC2_DATA1_sw_config_MASK       (0x6000000U)
#define IOMUXD_USDHC2_DATA1_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC2_DATA1_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA1_sw_config_SHIFT)) & IOMUXD_USDHC2_DATA1_sw_config_MASK)
#define IOMUXD_USDHC2_DATA1_mux_mode_MASK        (0x38000000U)
#define IOMUXD_USDHC2_DATA1_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC2.DATA1
 *  0b001..DMA.UART4.TX
 *  0b011..LSIO.GPIO5.IO27
 */
#define IOMUXD_USDHC2_DATA1_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA1_mux_mode_SHIFT)) & IOMUXD_USDHC2_DATA1_mux_mode_MASK)
#define IOMUXD_USDHC2_DATA1_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_USDHC2_DATA1_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC2_DATA1_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_USDHC2_DATA1_update_pad_ctl_MASK)
#define IOMUXD_USDHC2_DATA1_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC2_DATA1_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC2_DATA1_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA1_update_mux_mode_SHIFT)) & IOMUXD_USDHC2_DATA1_update_mux_mode_MASK)
/*! @} */

/*! @name USDHC2_DATA2 - USDHC2_DATA2 */
/*! @{ */
#define IOMUXD_USDHC2_DATA2_PDRV_MASK            (0x1U)
#define IOMUXD_USDHC2_DATA2_PDRV_SHIFT           (0U)
#define IOMUXD_USDHC2_DATA2_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA2_PDRV_SHIFT)) & IOMUXD_USDHC2_DATA2_PDRV_MASK)
#define IOMUXD_USDHC2_DATA2_USDHC2_DATA2_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC2_DATA2_USDHC2_DATA2_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC2_DATA2_USDHC2_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA2_USDHC2_DATA2_reserved_1_4_SHIFT)) & IOMUXD_USDHC2_DATA2_USDHC2_DATA2_reserved_1_4_MASK)
#define IOMUXD_USDHC2_DATA2_PULL_MASK            (0x60U)
#define IOMUXD_USDHC2_DATA2_PULL_SHIFT           (5U)
#define IOMUXD_USDHC2_DATA2_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA2_PULL_SHIFT)) & IOMUXD_USDHC2_DATA2_PULL_MASK)
#define IOMUXD_USDHC2_DATA2_USDHC2_DATA2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC2_DATA2_USDHC2_DATA2_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC2_DATA2_USDHC2_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA2_USDHC2_DATA2_reserved_7_18_SHIFT)) & IOMUXD_USDHC2_DATA2_USDHC2_DATA2_reserved_7_18_MASK)
#define IOMUXD_USDHC2_DATA2_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_USDHC2_DATA2_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC2_DATA2_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC2_DATA2_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC2_DATA2_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_USDHC2_DATA2_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_USDHC2_DATA2_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC2_DATA2_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC2_DATA2_lp_config_MASK       (0x1800000U)
#define IOMUXD_USDHC2_DATA2_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC2_DATA2_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA2_lp_config_SHIFT)) & IOMUXD_USDHC2_DATA2_lp_config_MASK)
#define IOMUXD_USDHC2_DATA2_sw_config_MASK       (0x6000000U)
#define IOMUXD_USDHC2_DATA2_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC2_DATA2_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA2_sw_config_SHIFT)) & IOMUXD_USDHC2_DATA2_sw_config_MASK)
#define IOMUXD_USDHC2_DATA2_mux_mode_MASK        (0x38000000U)
#define IOMUXD_USDHC2_DATA2_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC2.DATA2
 *  0b001..DMA.UART4.CTS_B
 *  0b011..LSIO.GPIO5.IO28
 */
#define IOMUXD_USDHC2_DATA2_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA2_mux_mode_SHIFT)) & IOMUXD_USDHC2_DATA2_mux_mode_MASK)
#define IOMUXD_USDHC2_DATA2_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_USDHC2_DATA2_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC2_DATA2_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_USDHC2_DATA2_update_pad_ctl_MASK)
#define IOMUXD_USDHC2_DATA2_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC2_DATA2_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC2_DATA2_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA2_update_mux_mode_SHIFT)) & IOMUXD_USDHC2_DATA2_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_3_1 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA1_MASK (0x1U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA1_SHIFT (0U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA1(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA1_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_1_1_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_1_1_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_1_1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_1_1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_1_1_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA2_MASK (0x4U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA2_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA2(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA2_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA3_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA3_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA3(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA3_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA4_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA4_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA4(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA4_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA4_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA5_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA5_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA5(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA5_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA5_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA6_MASK (0x80U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA6_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA6(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA6_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA6_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA7_MASK (0x100U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA7_SHIFT (8U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA7(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA7_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_USDHC1_DATA7_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_STROBE_MASK (0x200U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_STROBE_SHIFT (9U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC1_STROBE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_USDHC1_STROBE_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_USDHC1_STROBE_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_10_10_MASK (0x400U)
#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_10_10_SHIFT (10U)
#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_10_10_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_10_10_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_CLK_MASK  (0x800U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_CLK_SHIFT (11U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_CLK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_USDHC2_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_USDHC2_CLK_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_CMD_MASK  (0x1000U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_CMD_SHIFT (12U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_CMD(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_USDHC2_CMD_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_USDHC2_CMD_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA0_MASK (0x2000U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA0_SHIFT (13U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA0(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA0_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA1_MASK (0x4000U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA1_SHIFT (14U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA1(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA1_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA2_MASK (0x8000U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA2_SHIFT (15U)
#define IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA2(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_USDHC2_DATA2_MASK)
#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_16_31_MASK (0xFFFF0000U)
#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_16_31_SHIFT (16U)
#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_16_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_16_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_16_31_MASK)
/*! @} */

/*! @name USDHC2_DATA3 - USDHC2_DATA3 */
/*! @{ */
#define IOMUXD_USDHC2_DATA3_PDRV_MASK            (0x1U)
#define IOMUXD_USDHC2_DATA3_PDRV_SHIFT           (0U)
#define IOMUXD_USDHC2_DATA3_PDRV(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA3_PDRV_SHIFT)) & IOMUXD_USDHC2_DATA3_PDRV_MASK)
#define IOMUXD_USDHC2_DATA3_USDHC2_DATA3_reserved_1_4_MASK (0x1EU)
#define IOMUXD_USDHC2_DATA3_USDHC2_DATA3_reserved_1_4_SHIFT (1U)
#define IOMUXD_USDHC2_DATA3_USDHC2_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA3_USDHC2_DATA3_reserved_1_4_SHIFT)) & IOMUXD_USDHC2_DATA3_USDHC2_DATA3_reserved_1_4_MASK)
#define IOMUXD_USDHC2_DATA3_PULL_MASK            (0x60U)
#define IOMUXD_USDHC2_DATA3_PULL_SHIFT           (5U)
#define IOMUXD_USDHC2_DATA3_PULL(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA3_PULL_SHIFT)) & IOMUXD_USDHC2_DATA3_PULL_MASK)
#define IOMUXD_USDHC2_DATA3_USDHC2_DATA3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_USDHC2_DATA3_USDHC2_DATA3_reserved_7_18_SHIFT (7U)
#define IOMUXD_USDHC2_DATA3_USDHC2_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA3_USDHC2_DATA3_reserved_7_18_SHIFT)) & IOMUXD_USDHC2_DATA3_USDHC2_DATA3_reserved_7_18_MASK)
#define IOMUXD_USDHC2_DATA3_WAKEUP_CTRL_MASK     (0x380000U)
#define IOMUXD_USDHC2_DATA3_WAKEUP_CTRL_SHIFT    (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_USDHC2_DATA3_WAKEUP_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC2_DATA3_WAKEUP_CTRL_MASK)
#define IOMUXD_USDHC2_DATA3_WAKEUP_MASK_MASK     (0x400000U)
#define IOMUXD_USDHC2_DATA3_WAKEUP_MASK_SHIFT    (22U)
#define IOMUXD_USDHC2_DATA3_WAKEUP_MASK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC2_DATA3_WAKEUP_MASK_MASK)
#define IOMUXD_USDHC2_DATA3_lp_config_MASK       (0x1800000U)
#define IOMUXD_USDHC2_DATA3_lp_config_SHIFT      (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_USDHC2_DATA3_lp_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA3_lp_config_SHIFT)) & IOMUXD_USDHC2_DATA3_lp_config_MASK)
#define IOMUXD_USDHC2_DATA3_sw_config_MASK       (0x6000000U)
#define IOMUXD_USDHC2_DATA3_sw_config_SHIFT      (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_USDHC2_DATA3_sw_config(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA3_sw_config_SHIFT)) & IOMUXD_USDHC2_DATA3_sw_config_MASK)
#define IOMUXD_USDHC2_DATA3_mux_mode_MASK        (0x38000000U)
#define IOMUXD_USDHC2_DATA3_mux_mode_SHIFT       (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.USDHC2.DATA3
 *  0b001..DMA.UART4.RTS_B
 *  0b011..LSIO.GPIO5.IO29
 */
#define IOMUXD_USDHC2_DATA3_mux_mode(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA3_mux_mode_SHIFT)) & IOMUXD_USDHC2_DATA3_mux_mode_MASK)
#define IOMUXD_USDHC2_DATA3_update_pad_ctl_MASK  (0x40000000U)
#define IOMUXD_USDHC2_DATA3_update_pad_ctl_SHIFT (30U)
#define IOMUXD_USDHC2_DATA3_update_pad_ctl(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_USDHC2_DATA3_update_pad_ctl_MASK)
#define IOMUXD_USDHC2_DATA3_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_USDHC2_DATA3_update_mux_mode_SHIFT (31U)
#define IOMUXD_USDHC2_DATA3_update_mux_mode(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC2_DATA3_update_mux_mode_SHIFT)) & IOMUXD_USDHC2_DATA3_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3 */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_RGMII_TXC - ENET0_RGMII_TXC */
/*! @{ */
#define IOMUXD_ENET0_RGMII_TXC_PDRV_MASK         (0x1U)
#define IOMUXD_ENET0_RGMII_TXC_PDRV_SHIFT        (0U)
#define IOMUXD_ENET0_RGMII_TXC_PDRV(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_PDRV_MASK)
#define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_MASK)
#define IOMUXD_ENET0_RGMII_TXC_PULL_MASK         (0x60U)
#define IOMUXD_ENET0_RGMII_TXC_PULL_SHIFT        (5U)
#define IOMUXD_ENET0_RGMII_TXC_PULL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_PULL_MASK)
#define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_MASK)
#define IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_MASK  (0x380000U)
#define IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_MASK  (0x400000U)
#define IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_RGMII_TXC_lp_config_MASK    (0x1800000U)
#define IOMUXD_ENET0_RGMII_TXC_lp_config_SHIFT   (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_RGMII_TXC_lp_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_lp_config_MASK)
#define IOMUXD_ENET0_RGMII_TXC_sw_config_MASK    (0x6000000U)
#define IOMUXD_ENET0_RGMII_TXC_sw_config_SHIFT   (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_RGMII_TXC_sw_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_sw_config_MASK)
#define IOMUXD_ENET0_RGMII_TXC_mux_mode_MASK     (0x38000000U)
#define IOMUXD_ENET0_RGMII_TXC_mux_mode_SHIFT    (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.RGMII_TXC
 *  0b001..CONN.ENET0.RCLK50M_OUT
 *  0b010..CONN.ENET0.RCLK50M_IN
 *  0b011..LSIO.GPIO5.IO30
 */
#define IOMUXD_ENET0_RGMII_TXC_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_mux_mode_MASK)
#define IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET0_RGMII_TXC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_MASK)
#define IOMUXD_ENET0_RGMII_TXC_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET0_RGMII_TXC_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET0_RGMII_TXC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_RGMII_TX_CTL - ENET0_RGMII_TX_CTL */
/*! @{ */
#define IOMUXD_ENET0_RGMII_TX_CTL_PDRV_MASK      (0x1U)
#define IOMUXD_ENET0_RGMII_TX_CTL_PDRV_SHIFT     (0U)
#define IOMUXD_ENET0_RGMII_TX_CTL_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_PDRV_MASK)
#define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_MASK)
#define IOMUXD_ENET0_RGMII_TX_CTL_PULL_MASK      (0x60U)
#define IOMUXD_ENET0_RGMII_TX_CTL_PULL_SHIFT     (5U)
#define IOMUXD_ENET0_RGMII_TX_CTL_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_PULL_MASK)
#define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_MASK)
#define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_RGMII_TX_CTL_lp_config_MASK (0x1800000U)
#define IOMUXD_ENET0_RGMII_TX_CTL_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_RGMII_TX_CTL_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_lp_config_MASK)
#define IOMUXD_ENET0_RGMII_TX_CTL_sw_config_MASK (0x6000000U)
#define IOMUXD_ENET0_RGMII_TX_CTL_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_RGMII_TX_CTL_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_sw_config_MASK)
#define IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_MASK  (0x38000000U)
#define IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.RGMII_TX_CTL
 *  0b011..LSIO.GPIO5.IO31
 */
#define IOMUXD_ENET0_RGMII_TX_CTL_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_MASK)
#define IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_MASK)
#define IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_RGMII_TXD0 - ENET0_RGMII_TXD0 */
/*! @{ */
#define IOMUXD_ENET0_RGMII_TXD0_PDRV_MASK        (0x1U)
#define IOMUXD_ENET0_RGMII_TXD0_PDRV_SHIFT       (0U)
#define IOMUXD_ENET0_RGMII_TXD0_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_PDRV_MASK)
#define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_MASK)
#define IOMUXD_ENET0_RGMII_TXD0_PULL_MASK        (0x60U)
#define IOMUXD_ENET0_RGMII_TXD0_PULL_SHIFT       (5U)
#define IOMUXD_ENET0_RGMII_TXD0_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_PULL_MASK)
#define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_MASK)
#define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_RGMII_TXD0_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET0_RGMII_TXD0_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_RGMII_TXD0_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_lp_config_MASK)
#define IOMUXD_ENET0_RGMII_TXD0_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET0_RGMII_TXD0_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_RGMII_TXD0_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_sw_config_MASK)
#define IOMUXD_ENET0_RGMII_TXD0_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET0_RGMII_TXD0_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.RGMII_TXD0
 *  0b011..LSIO.GPIO6.IO00
 */
#define IOMUXD_ENET0_RGMII_TXD0_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_mux_mode_MASK)
#define IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_MASK)
#define IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET0_RGMII_TXD0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_RGMII_TXD1 - ENET0_RGMII_TXD1 */
/*! @{ */
#define IOMUXD_ENET0_RGMII_TXD1_PDRV_MASK        (0x1U)
#define IOMUXD_ENET0_RGMII_TXD1_PDRV_SHIFT       (0U)
#define IOMUXD_ENET0_RGMII_TXD1_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_PDRV_MASK)
#define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_MASK)
#define IOMUXD_ENET0_RGMII_TXD1_PULL_MASK        (0x60U)
#define IOMUXD_ENET0_RGMII_TXD1_PULL_SHIFT       (5U)
#define IOMUXD_ENET0_RGMII_TXD1_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_PULL_MASK)
#define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_MASK)
#define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_RGMII_TXD1_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET0_RGMII_TXD1_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_RGMII_TXD1_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_lp_config_MASK)
#define IOMUXD_ENET0_RGMII_TXD1_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET0_RGMII_TXD1_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_RGMII_TXD1_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_sw_config_MASK)
#define IOMUXD_ENET0_RGMII_TXD1_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET0_RGMII_TXD1_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.RGMII_TXD1
 *  0b011..LSIO.GPIO6.IO01
 */
#define IOMUXD_ENET0_RGMII_TXD1_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_mux_mode_MASK)
#define IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_MASK)
#define IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET0_RGMII_TXD1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_RGMII_TXD2 - ENET0_RGMII_TXD2 */
/*! @{ */
#define IOMUXD_ENET0_RGMII_TXD2_PDRV_MASK        (0x1U)
#define IOMUXD_ENET0_RGMII_TXD2_PDRV_SHIFT       (0U)
#define IOMUXD_ENET0_RGMII_TXD2_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_PDRV_MASK)
#define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_MASK)
#define IOMUXD_ENET0_RGMII_TXD2_PULL_MASK        (0x60U)
#define IOMUXD_ENET0_RGMII_TXD2_PULL_SHIFT       (5U)
#define IOMUXD_ENET0_RGMII_TXD2_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_PULL_MASK)
#define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_MASK)
#define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_RGMII_TXD2_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET0_RGMII_TXD2_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_RGMII_TXD2_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_lp_config_MASK)
#define IOMUXD_ENET0_RGMII_TXD2_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET0_RGMII_TXD2_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_RGMII_TXD2_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_sw_config_MASK)
#define IOMUXD_ENET0_RGMII_TXD2_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET0_RGMII_TXD2_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.RGMII_TXD2
 *  0b001..DMA.UART3.TX
 *  0b010..VPU.TSI_S1.VID
 *  0b011..LSIO.GPIO6.IO02
 */
#define IOMUXD_ENET0_RGMII_TXD2_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_mux_mode_MASK)
#define IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_MASK)
#define IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET0_RGMII_TXD2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_RGMII_TXD3 - ENET0_RGMII_TXD3 */
/*! @{ */
#define IOMUXD_ENET0_RGMII_TXD3_PDRV_MASK        (0x1U)
#define IOMUXD_ENET0_RGMII_TXD3_PDRV_SHIFT       (0U)
#define IOMUXD_ENET0_RGMII_TXD3_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_PDRV_MASK)
#define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_MASK)
#define IOMUXD_ENET0_RGMII_TXD3_PULL_MASK        (0x60U)
#define IOMUXD_ENET0_RGMII_TXD3_PULL_SHIFT       (5U)
#define IOMUXD_ENET0_RGMII_TXD3_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_PULL_MASK)
#define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_MASK)
#define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_RGMII_TXD3_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET0_RGMII_TXD3_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_RGMII_TXD3_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_lp_config_MASK)
#define IOMUXD_ENET0_RGMII_TXD3_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET0_RGMII_TXD3_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_RGMII_TXD3_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_sw_config_MASK)
#define IOMUXD_ENET0_RGMII_TXD3_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET0_RGMII_TXD3_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.RGMII_TXD3
 *  0b001..DMA.UART3.RTS_B
 *  0b010..VPU.TSI_S1.SYNC
 *  0b011..LSIO.GPIO6.IO03
 */
#define IOMUXD_ENET0_RGMII_TXD3_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_mux_mode_MASK)
#define IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_MASK)
#define IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET0_RGMII_TXD3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_RGMII_RXC - ENET0_RGMII_RXC */
/*! @{ */
#define IOMUXD_ENET0_RGMII_RXC_PDRV_MASK         (0x1U)
#define IOMUXD_ENET0_RGMII_RXC_PDRV_SHIFT        (0U)
#define IOMUXD_ENET0_RGMII_RXC_PDRV(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_PDRV_MASK)
#define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_MASK)
#define IOMUXD_ENET0_RGMII_RXC_PULL_MASK         (0x60U)
#define IOMUXD_ENET0_RGMII_RXC_PULL_SHIFT        (5U)
#define IOMUXD_ENET0_RGMII_RXC_PULL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_PULL_MASK)
#define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_MASK)
#define IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_MASK  (0x380000U)
#define IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_MASK  (0x400000U)
#define IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_RGMII_RXC_lp_config_MASK    (0x1800000U)
#define IOMUXD_ENET0_RGMII_RXC_lp_config_SHIFT   (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_RGMII_RXC_lp_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_lp_config_MASK)
#define IOMUXD_ENET0_RGMII_RXC_sw_config_MASK    (0x6000000U)
#define IOMUXD_ENET0_RGMII_RXC_sw_config_SHIFT   (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_RGMII_RXC_sw_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_sw_config_MASK)
#define IOMUXD_ENET0_RGMII_RXC_mux_mode_MASK     (0x38000000U)
#define IOMUXD_ENET0_RGMII_RXC_mux_mode_SHIFT    (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.RGMII_RXC
 *  0b001..DMA.UART3.CTS_B
 *  0b010..VPU.TSI_S1.DATA
 *  0b011..LSIO.GPIO6.IO04
 */
#define IOMUXD_ENET0_RGMII_RXC_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_mux_mode_MASK)
#define IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET0_RGMII_RXC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_MASK)
#define IOMUXD_ENET0_RGMII_RXC_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET0_RGMII_RXC_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET0_RGMII_RXC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_RGMII_RX_CTL - ENET0_RGMII_RX_CTL */
/*! @{ */
#define IOMUXD_ENET0_RGMII_RX_CTL_PDRV_MASK      (0x1U)
#define IOMUXD_ENET0_RGMII_RX_CTL_PDRV_SHIFT     (0U)
#define IOMUXD_ENET0_RGMII_RX_CTL_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_PDRV_MASK)
#define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_MASK)
#define IOMUXD_ENET0_RGMII_RX_CTL_PULL_MASK      (0x60U)
#define IOMUXD_ENET0_RGMII_RX_CTL_PULL_SHIFT     (5U)
#define IOMUXD_ENET0_RGMII_RX_CTL_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_PULL_MASK)
#define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_MASK)
#define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_RGMII_RX_CTL_lp_config_MASK (0x1800000U)
#define IOMUXD_ENET0_RGMII_RX_CTL_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_RGMII_RX_CTL_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_lp_config_MASK)
#define IOMUXD_ENET0_RGMII_RX_CTL_sw_config_MASK (0x6000000U)
#define IOMUXD_ENET0_RGMII_RX_CTL_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_RGMII_RX_CTL_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_sw_config_MASK)
#define IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_MASK  (0x38000000U)
#define IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.RGMII_RX_CTL
 *  0b010..VPU.TSI_S0.VID
 *  0b011..LSIO.GPIO6.IO05
 */
#define IOMUXD_ENET0_RGMII_RX_CTL_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_MASK)
#define IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_MASK)
#define IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_RGMII_RXD0 - ENET0_RGMII_RXD0 */
/*! @{ */
#define IOMUXD_ENET0_RGMII_RXD0_PDRV_MASK        (0x1U)
#define IOMUXD_ENET0_RGMII_RXD0_PDRV_SHIFT       (0U)
#define IOMUXD_ENET0_RGMII_RXD0_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_PDRV_MASK)
#define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_MASK)
#define IOMUXD_ENET0_RGMII_RXD0_PULL_MASK        (0x60U)
#define IOMUXD_ENET0_RGMII_RXD0_PULL_SHIFT       (5U)
#define IOMUXD_ENET0_RGMII_RXD0_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_PULL_MASK)
#define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_MASK)
#define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_RGMII_RXD0_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET0_RGMII_RXD0_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_RGMII_RXD0_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_lp_config_MASK)
#define IOMUXD_ENET0_RGMII_RXD0_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET0_RGMII_RXD0_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_RGMII_RXD0_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_sw_config_MASK)
#define IOMUXD_ENET0_RGMII_RXD0_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET0_RGMII_RXD0_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.RGMII_RXD0
 *  0b010..VPU.TSI_S0.SYNC
 *  0b011..LSIO.GPIO6.IO06
 */
#define IOMUXD_ENET0_RGMII_RXD0_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_mux_mode_MASK)
#define IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_MASK)
#define IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET0_RGMII_RXD0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_RGMII_RXD1 - ENET0_RGMII_RXD1 */
/*! @{ */
#define IOMUXD_ENET0_RGMII_RXD1_PDRV_MASK        (0x1U)
#define IOMUXD_ENET0_RGMII_RXD1_PDRV_SHIFT       (0U)
#define IOMUXD_ENET0_RGMII_RXD1_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_PDRV_MASK)
#define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_MASK)
#define IOMUXD_ENET0_RGMII_RXD1_PULL_MASK        (0x60U)
#define IOMUXD_ENET0_RGMII_RXD1_PULL_SHIFT       (5U)
#define IOMUXD_ENET0_RGMII_RXD1_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_PULL_MASK)
#define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_MASK)
#define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_RGMII_RXD1_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET0_RGMII_RXD1_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_RGMII_RXD1_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_lp_config_MASK)
#define IOMUXD_ENET0_RGMII_RXD1_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET0_RGMII_RXD1_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_RGMII_RXD1_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_sw_config_MASK)
#define IOMUXD_ENET0_RGMII_RXD1_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET0_RGMII_RXD1_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.RGMII_RXD1
 *  0b010..VPU.TSI_S0.DATA
 *  0b011..LSIO.GPIO6.IO07
 */
#define IOMUXD_ENET0_RGMII_RXD1_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_mux_mode_MASK)
#define IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_MASK)
#define IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET0_RGMII_RXD1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_RGMII_RXD2 - ENET0_RGMII_RXD2 */
/*! @{ */
#define IOMUXD_ENET0_RGMII_RXD2_PDRV_MASK        (0x1U)
#define IOMUXD_ENET0_RGMII_RXD2_PDRV_SHIFT       (0U)
#define IOMUXD_ENET0_RGMII_RXD2_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_PDRV_MASK)
#define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_MASK)
#define IOMUXD_ENET0_RGMII_RXD2_PULL_MASK        (0x60U)
#define IOMUXD_ENET0_RGMII_RXD2_PULL_SHIFT       (5U)
#define IOMUXD_ENET0_RGMII_RXD2_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_PULL_MASK)
#define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_MASK)
#define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_RGMII_RXD2_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET0_RGMII_RXD2_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_RGMII_RXD2_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_lp_config_MASK)
#define IOMUXD_ENET0_RGMII_RXD2_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET0_RGMII_RXD2_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_RGMII_RXD2_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_sw_config_MASK)
#define IOMUXD_ENET0_RGMII_RXD2_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET0_RGMII_RXD2_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.RGMII_RXD2
 *  0b001..CONN.ENET0.RMII_RX_ER
 *  0b010..VPU.TSI_S0.CLK
 *  0b011..LSIO.GPIO6.IO08
 */
#define IOMUXD_ENET0_RGMII_RXD2_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_mux_mode_MASK)
#define IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_MASK)
#define IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET0_RGMII_RXD2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_MASK)
/*! @} */

/*! @name ENET0_RGMII_RXD3 - ENET0_RGMII_RXD3 */
/*! @{ */
#define IOMUXD_ENET0_RGMII_RXD3_PDRV_MASK        (0x1U)
#define IOMUXD_ENET0_RGMII_RXD3_PDRV_SHIFT       (0U)
#define IOMUXD_ENET0_RGMII_RXD3_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_PDRV_MASK)
#define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_MASK)
#define IOMUXD_ENET0_RGMII_RXD3_PULL_MASK        (0x60U)
#define IOMUXD_ENET0_RGMII_RXD3_PULL_SHIFT       (5U)
#define IOMUXD_ENET0_RGMII_RXD3_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_PULL_MASK)
#define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_MASK)
#define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_MASK)
#define IOMUXD_ENET0_RGMII_RXD3_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET0_RGMII_RXD3_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET0_RGMII_RXD3_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_lp_config_MASK)
#define IOMUXD_ENET0_RGMII_RXD3_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET0_RGMII_RXD3_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET0_RGMII_RXD3_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_sw_config_MASK)
#define IOMUXD_ENET0_RGMII_RXD3_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET0_RGMII_RXD3_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET0.RGMII_RXD3
 *  0b001..DMA.UART3.RX
 *  0b010..VPU.TSI_S1.CLK
 *  0b011..LSIO.GPIO6.IO09
 */
#define IOMUXD_ENET0_RGMII_RXD3_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_mux_mode_MASK)
#define IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_MASK)
#define IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET0_RGMII_RXD3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB - IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PSW_OVR_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PSW_OVR_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PSW_OVR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PSW_OVR_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PSW_OVR_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_update_mux_mode_MASK)
/*! @} */

/*! @name ENET1_RGMII_TXC - ENET1_RGMII_TXC */
/*! @{ */
#define IOMUXD_ENET1_RGMII_TXC_PDRV_MASK         (0x1U)
#define IOMUXD_ENET1_RGMII_TXC_PDRV_SHIFT        (0U)
#define IOMUXD_ENET1_RGMII_TXC_PDRV(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXC_PDRV_SHIFT)) & IOMUXD_ENET1_RGMII_TXC_PDRV_MASK)
#define IOMUXD_ENET1_RGMII_TXC_ENET1_RGMII_TXC_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_RGMII_TXC_ENET1_RGMII_TXC_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_RGMII_TXC_ENET1_RGMII_TXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXC_ENET1_RGMII_TXC_reserved_1_4_SHIFT)) & IOMUXD_ENET1_RGMII_TXC_ENET1_RGMII_TXC_reserved_1_4_MASK)
#define IOMUXD_ENET1_RGMII_TXC_PULL_MASK         (0x60U)
#define IOMUXD_ENET1_RGMII_TXC_PULL_SHIFT        (5U)
#define IOMUXD_ENET1_RGMII_TXC_PULL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXC_PULL_SHIFT)) & IOMUXD_ENET1_RGMII_TXC_PULL_MASK)
#define IOMUXD_ENET1_RGMII_TXC_ENET1_RGMII_TXC_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_RGMII_TXC_ENET1_RGMII_TXC_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_RGMII_TXC_ENET1_RGMII_TXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXC_ENET1_RGMII_TXC_reserved_7_18_SHIFT)) & IOMUXD_ENET1_RGMII_TXC_ENET1_RGMII_TXC_reserved_7_18_MASK)
#define IOMUXD_ENET1_RGMII_TXC_WAKEUP_CTRL_MASK  (0x380000U)
#define IOMUXD_ENET1_RGMII_TXC_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_RGMII_TXC_WAKEUP_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_RGMII_TXC_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_RGMII_TXC_WAKEUP_MASK_MASK  (0x400000U)
#define IOMUXD_ENET1_RGMII_TXC_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET1_RGMII_TXC_WAKEUP_MASK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_RGMII_TXC_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_RGMII_TXC_lp_config_MASK    (0x1800000U)
#define IOMUXD_ENET1_RGMII_TXC_lp_config_SHIFT   (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_RGMII_TXC_lp_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXC_lp_config_SHIFT)) & IOMUXD_ENET1_RGMII_TXC_lp_config_MASK)
#define IOMUXD_ENET1_RGMII_TXC_sw_config_MASK    (0x6000000U)
#define IOMUXD_ENET1_RGMII_TXC_sw_config_SHIFT   (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_RGMII_TXC_sw_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXC_sw_config_SHIFT)) & IOMUXD_ENET1_RGMII_TXC_sw_config_MASK)
#define IOMUXD_ENET1_RGMII_TXC_mux_mode_MASK     (0x38000000U)
#define IOMUXD_ENET1_RGMII_TXC_mux_mode_SHIFT    (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.RGMII_TXC
 *  0b001..CONN.ENET1.RCLK50M_OUT
 *  0b010..CONN.ENET1.RCLK50M_IN
 *  0b011..LSIO.GPIO6.IO10
 */
#define IOMUXD_ENET1_RGMII_TXC_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXC_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_TXC_mux_mode_MASK)
#define IOMUXD_ENET1_RGMII_TXC_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET1_RGMII_TXC_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET1_RGMII_TXC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXC_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_RGMII_TXC_update_pad_ctl_MASK)
#define IOMUXD_ENET1_RGMII_TXC_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET1_RGMII_TXC_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET1_RGMII_TXC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXC_update_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_TXC_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_3_2 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_3_2_USDHC2_DATA3_MASK (0x1U)
#define IOMUXD_IOMUXD_GROUP_3_2_USDHC2_DATA3_SHIFT (0U)
#define IOMUXD_IOMUXD_GROUP_3_2_USDHC2_DATA3(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_USDHC2_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_USDHC2_DATA3_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_1_1_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_1_1_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_1_1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_1_1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_1_1_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXC_MASK (0x4U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXC_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXC_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TX_CTL_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TX_CTL_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TX_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TX_CTL_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TX_CTL_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD0_MASK (0x10U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD0_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD0_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD0_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD1_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD1_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD1_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD2_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD2_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD2_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD2_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD3_MASK (0x80U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD3_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD3_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_TXD3_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXC_MASK (0x100U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXC_SHIFT (8U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXC_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RX_CTL_MASK (0x200U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RX_CTL_SHIFT (9U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RX_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RX_CTL_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RX_CTL_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD0_MASK (0x400U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD0_SHIFT (10U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD0_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD0_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD1_MASK (0x800U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD1_SHIFT (11U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD1_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD2_MASK (0x1000U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD2_SHIFT (12U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD2_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD2_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD3_MASK (0x2000U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD3_SHIFT (13U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD3_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_ENET0_RGMII_RXD3_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_14_14_MASK (0x4000U)
#define IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_14_14_SHIFT (14U)
#define IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_14_14_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_14_14_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET1_RGMII_TXC_MASK (0x8000U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET1_RGMII_TXC_SHIFT (15U)
#define IOMUXD_IOMUXD_GROUP_3_2_ENET1_RGMII_TXC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_ENET1_RGMII_TXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_ENET1_RGMII_TXC_MASK)
#define IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_16_31_MASK (0xFFFF0000U)
#define IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_16_31_SHIFT (16U)
#define IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_16_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_16_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_2_iomuxd_group_3_2_reserved_16_31_MASK)
/*! @} */

/*! @name ENET1_RGMII_TX_CTL - ENET1_RGMII_TX_CTL */
/*! @{ */
#define IOMUXD_ENET1_RGMII_TX_CTL_PDRV_MASK      (0x1U)
#define IOMUXD_ENET1_RGMII_TX_CTL_PDRV_SHIFT     (0U)
#define IOMUXD_ENET1_RGMII_TX_CTL_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TX_CTL_PDRV_SHIFT)) & IOMUXD_ENET1_RGMII_TX_CTL_PDRV_MASK)
#define IOMUXD_ENET1_RGMII_TX_CTL_ENET1_RGMII_TX_CTL_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_RGMII_TX_CTL_ENET1_RGMII_TX_CTL_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_RGMII_TX_CTL_ENET1_RGMII_TX_CTL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TX_CTL_ENET1_RGMII_TX_CTL_reserved_1_4_SHIFT)) & IOMUXD_ENET1_RGMII_TX_CTL_ENET1_RGMII_TX_CTL_reserved_1_4_MASK)
#define IOMUXD_ENET1_RGMII_TX_CTL_PULL_MASK      (0x60U)
#define IOMUXD_ENET1_RGMII_TX_CTL_PULL_SHIFT     (5U)
#define IOMUXD_ENET1_RGMII_TX_CTL_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TX_CTL_PULL_SHIFT)) & IOMUXD_ENET1_RGMII_TX_CTL_PULL_MASK)
#define IOMUXD_ENET1_RGMII_TX_CTL_ENET1_RGMII_TX_CTL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_RGMII_TX_CTL_ENET1_RGMII_TX_CTL_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_RGMII_TX_CTL_ENET1_RGMII_TX_CTL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TX_CTL_ENET1_RGMII_TX_CTL_reserved_7_18_SHIFT)) & IOMUXD_ENET1_RGMII_TX_CTL_ENET1_RGMII_TX_CTL_reserved_7_18_MASK)
#define IOMUXD_ENET1_RGMII_TX_CTL_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET1_RGMII_TX_CTL_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_RGMII_TX_CTL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TX_CTL_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_RGMII_TX_CTL_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_RGMII_TX_CTL_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET1_RGMII_TX_CTL_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET1_RGMII_TX_CTL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TX_CTL_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_RGMII_TX_CTL_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_RGMII_TX_CTL_lp_config_MASK (0x1800000U)
#define IOMUXD_ENET1_RGMII_TX_CTL_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_RGMII_TX_CTL_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TX_CTL_lp_config_SHIFT)) & IOMUXD_ENET1_RGMII_TX_CTL_lp_config_MASK)
#define IOMUXD_ENET1_RGMII_TX_CTL_sw_config_MASK (0x6000000U)
#define IOMUXD_ENET1_RGMII_TX_CTL_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_RGMII_TX_CTL_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TX_CTL_sw_config_SHIFT)) & IOMUXD_ENET1_RGMII_TX_CTL_sw_config_MASK)
#define IOMUXD_ENET1_RGMII_TX_CTL_mux_mode_MASK  (0x38000000U)
#define IOMUXD_ENET1_RGMII_TX_CTL_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.RGMII_TX_CTL
 *  0b011..LSIO.GPIO6.IO11
 */
#define IOMUXD_ENET1_RGMII_TX_CTL_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TX_CTL_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_TX_CTL_mux_mode_MASK)
#define IOMUXD_ENET1_RGMII_TX_CTL_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET1_RGMII_TX_CTL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET1_RGMII_TX_CTL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TX_CTL_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_RGMII_TX_CTL_update_pad_ctl_MASK)
#define IOMUXD_ENET1_RGMII_TX_CTL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET1_RGMII_TX_CTL_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET1_RGMII_TX_CTL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TX_CTL_update_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_TX_CTL_update_mux_mode_MASK)
/*! @} */

/*! @name ENET1_RGMII_TXD0 - ENET1_RGMII_TXD0 */
/*! @{ */
#define IOMUXD_ENET1_RGMII_TXD0_PDRV_MASK        (0x1U)
#define IOMUXD_ENET1_RGMII_TXD0_PDRV_SHIFT       (0U)
#define IOMUXD_ENET1_RGMII_TXD0_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD0_PDRV_SHIFT)) & IOMUXD_ENET1_RGMII_TXD0_PDRV_MASK)
#define IOMUXD_ENET1_RGMII_TXD0_ENET1_RGMII_TXD0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_RGMII_TXD0_ENET1_RGMII_TXD0_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_RGMII_TXD0_ENET1_RGMII_TXD0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD0_ENET1_RGMII_TXD0_reserved_1_4_SHIFT)) & IOMUXD_ENET1_RGMII_TXD0_ENET1_RGMII_TXD0_reserved_1_4_MASK)
#define IOMUXD_ENET1_RGMII_TXD0_PULL_MASK        (0x60U)
#define IOMUXD_ENET1_RGMII_TXD0_PULL_SHIFT       (5U)
#define IOMUXD_ENET1_RGMII_TXD0_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD0_PULL_SHIFT)) & IOMUXD_ENET1_RGMII_TXD0_PULL_MASK)
#define IOMUXD_ENET1_RGMII_TXD0_ENET1_RGMII_TXD0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_RGMII_TXD0_ENET1_RGMII_TXD0_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_RGMII_TXD0_ENET1_RGMII_TXD0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD0_ENET1_RGMII_TXD0_reserved_7_18_SHIFT)) & IOMUXD_ENET1_RGMII_TXD0_ENET1_RGMII_TXD0_reserved_7_18_MASK)
#define IOMUXD_ENET1_RGMII_TXD0_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET1_RGMII_TXD0_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_RGMII_TXD0_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_RGMII_TXD0_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_RGMII_TXD0_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET1_RGMII_TXD0_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET1_RGMII_TXD0_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD0_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_RGMII_TXD0_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_RGMII_TXD0_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET1_RGMII_TXD0_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_RGMII_TXD0_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD0_lp_config_SHIFT)) & IOMUXD_ENET1_RGMII_TXD0_lp_config_MASK)
#define IOMUXD_ENET1_RGMII_TXD0_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET1_RGMII_TXD0_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_RGMII_TXD0_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD0_sw_config_SHIFT)) & IOMUXD_ENET1_RGMII_TXD0_sw_config_MASK)
#define IOMUXD_ENET1_RGMII_TXD0_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET1_RGMII_TXD0_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.RGMII_TXD0
 *  0b011..LSIO.GPIO6.IO12
 */
#define IOMUXD_ENET1_RGMII_TXD0_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD0_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_TXD0_mux_mode_MASK)
#define IOMUXD_ENET1_RGMII_TXD0_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET1_RGMII_TXD0_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET1_RGMII_TXD0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD0_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_RGMII_TXD0_update_pad_ctl_MASK)
#define IOMUXD_ENET1_RGMII_TXD0_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET1_RGMII_TXD0_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET1_RGMII_TXD0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD0_update_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_TXD0_update_mux_mode_MASK)
/*! @} */

/*! @name ENET1_RGMII_TXD1 - ENET1_RGMII_TXD1 */
/*! @{ */
#define IOMUXD_ENET1_RGMII_TXD1_PDRV_MASK        (0x1U)
#define IOMUXD_ENET1_RGMII_TXD1_PDRV_SHIFT       (0U)
#define IOMUXD_ENET1_RGMII_TXD1_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD1_PDRV_SHIFT)) & IOMUXD_ENET1_RGMII_TXD1_PDRV_MASK)
#define IOMUXD_ENET1_RGMII_TXD1_ENET1_RGMII_TXD1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_RGMII_TXD1_ENET1_RGMII_TXD1_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_RGMII_TXD1_ENET1_RGMII_TXD1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD1_ENET1_RGMII_TXD1_reserved_1_4_SHIFT)) & IOMUXD_ENET1_RGMII_TXD1_ENET1_RGMII_TXD1_reserved_1_4_MASK)
#define IOMUXD_ENET1_RGMII_TXD1_PULL_MASK        (0x60U)
#define IOMUXD_ENET1_RGMII_TXD1_PULL_SHIFT       (5U)
#define IOMUXD_ENET1_RGMII_TXD1_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD1_PULL_SHIFT)) & IOMUXD_ENET1_RGMII_TXD1_PULL_MASK)
#define IOMUXD_ENET1_RGMII_TXD1_ENET1_RGMII_TXD1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_RGMII_TXD1_ENET1_RGMII_TXD1_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_RGMII_TXD1_ENET1_RGMII_TXD1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD1_ENET1_RGMII_TXD1_reserved_7_18_SHIFT)) & IOMUXD_ENET1_RGMII_TXD1_ENET1_RGMII_TXD1_reserved_7_18_MASK)
#define IOMUXD_ENET1_RGMII_TXD1_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET1_RGMII_TXD1_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_RGMII_TXD1_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_RGMII_TXD1_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_RGMII_TXD1_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET1_RGMII_TXD1_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET1_RGMII_TXD1_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD1_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_RGMII_TXD1_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_RGMII_TXD1_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET1_RGMII_TXD1_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_RGMII_TXD1_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD1_lp_config_SHIFT)) & IOMUXD_ENET1_RGMII_TXD1_lp_config_MASK)
#define IOMUXD_ENET1_RGMII_TXD1_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET1_RGMII_TXD1_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_RGMII_TXD1_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD1_sw_config_SHIFT)) & IOMUXD_ENET1_RGMII_TXD1_sw_config_MASK)
#define IOMUXD_ENET1_RGMII_TXD1_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET1_RGMII_TXD1_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.RGMII_TXD1
 *  0b011..LSIO.GPIO6.IO13
 */
#define IOMUXD_ENET1_RGMII_TXD1_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD1_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_TXD1_mux_mode_MASK)
#define IOMUXD_ENET1_RGMII_TXD1_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET1_RGMII_TXD1_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET1_RGMII_TXD1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD1_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_RGMII_TXD1_update_pad_ctl_MASK)
#define IOMUXD_ENET1_RGMII_TXD1_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET1_RGMII_TXD1_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET1_RGMII_TXD1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD1_update_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_TXD1_update_mux_mode_MASK)
/*! @} */

/*! @name ENET1_RGMII_TXD2 - ENET1_RGMII_TXD2 */
/*! @{ */
#define IOMUXD_ENET1_RGMII_TXD2_PDRV_MASK        (0x1U)
#define IOMUXD_ENET1_RGMII_TXD2_PDRV_SHIFT       (0U)
#define IOMUXD_ENET1_RGMII_TXD2_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD2_PDRV_SHIFT)) & IOMUXD_ENET1_RGMII_TXD2_PDRV_MASK)
#define IOMUXD_ENET1_RGMII_TXD2_ENET1_RGMII_TXD2_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_RGMII_TXD2_ENET1_RGMII_TXD2_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_RGMII_TXD2_ENET1_RGMII_TXD2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD2_ENET1_RGMII_TXD2_reserved_1_4_SHIFT)) & IOMUXD_ENET1_RGMII_TXD2_ENET1_RGMII_TXD2_reserved_1_4_MASK)
#define IOMUXD_ENET1_RGMII_TXD2_PULL_MASK        (0x60U)
#define IOMUXD_ENET1_RGMII_TXD2_PULL_SHIFT       (5U)
#define IOMUXD_ENET1_RGMII_TXD2_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD2_PULL_SHIFT)) & IOMUXD_ENET1_RGMII_TXD2_PULL_MASK)
#define IOMUXD_ENET1_RGMII_TXD2_ENET1_RGMII_TXD2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_RGMII_TXD2_ENET1_RGMII_TXD2_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_RGMII_TXD2_ENET1_RGMII_TXD2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD2_ENET1_RGMII_TXD2_reserved_7_18_SHIFT)) & IOMUXD_ENET1_RGMII_TXD2_ENET1_RGMII_TXD2_reserved_7_18_MASK)
#define IOMUXD_ENET1_RGMII_TXD2_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET1_RGMII_TXD2_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_RGMII_TXD2_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_RGMII_TXD2_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_RGMII_TXD2_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET1_RGMII_TXD2_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET1_RGMII_TXD2_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD2_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_RGMII_TXD2_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_RGMII_TXD2_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET1_RGMII_TXD2_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_RGMII_TXD2_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD2_lp_config_SHIFT)) & IOMUXD_ENET1_RGMII_TXD2_lp_config_MASK)
#define IOMUXD_ENET1_RGMII_TXD2_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET1_RGMII_TXD2_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_RGMII_TXD2_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD2_sw_config_SHIFT)) & IOMUXD_ENET1_RGMII_TXD2_sw_config_MASK)
#define IOMUXD_ENET1_RGMII_TXD2_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET1_RGMII_TXD2_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.RGMII_TXD2
 *  0b001..DMA.UART3.TX
 *  0b010..VPU.TSI_S1.VID
 *  0b011..LSIO.GPIO6.IO14
 */
#define IOMUXD_ENET1_RGMII_TXD2_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD2_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_TXD2_mux_mode_MASK)
#define IOMUXD_ENET1_RGMII_TXD2_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET1_RGMII_TXD2_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET1_RGMII_TXD2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD2_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_RGMII_TXD2_update_pad_ctl_MASK)
#define IOMUXD_ENET1_RGMII_TXD2_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET1_RGMII_TXD2_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET1_RGMII_TXD2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD2_update_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_TXD2_update_mux_mode_MASK)
/*! @} */

/*! @name ENET1_RGMII_TXD3 - ENET1_RGMII_TXD3 */
/*! @{ */
#define IOMUXD_ENET1_RGMII_TXD3_PDRV_MASK        (0x1U)
#define IOMUXD_ENET1_RGMII_TXD3_PDRV_SHIFT       (0U)
#define IOMUXD_ENET1_RGMII_TXD3_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD3_PDRV_SHIFT)) & IOMUXD_ENET1_RGMII_TXD3_PDRV_MASK)
#define IOMUXD_ENET1_RGMII_TXD3_ENET1_RGMII_TXD3_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_RGMII_TXD3_ENET1_RGMII_TXD3_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_RGMII_TXD3_ENET1_RGMII_TXD3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD3_ENET1_RGMII_TXD3_reserved_1_4_SHIFT)) & IOMUXD_ENET1_RGMII_TXD3_ENET1_RGMII_TXD3_reserved_1_4_MASK)
#define IOMUXD_ENET1_RGMII_TXD3_PULL_MASK        (0x60U)
#define IOMUXD_ENET1_RGMII_TXD3_PULL_SHIFT       (5U)
#define IOMUXD_ENET1_RGMII_TXD3_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD3_PULL_SHIFT)) & IOMUXD_ENET1_RGMII_TXD3_PULL_MASK)
#define IOMUXD_ENET1_RGMII_TXD3_ENET1_RGMII_TXD3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_RGMII_TXD3_ENET1_RGMII_TXD3_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_RGMII_TXD3_ENET1_RGMII_TXD3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD3_ENET1_RGMII_TXD3_reserved_7_18_SHIFT)) & IOMUXD_ENET1_RGMII_TXD3_ENET1_RGMII_TXD3_reserved_7_18_MASK)
#define IOMUXD_ENET1_RGMII_TXD3_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET1_RGMII_TXD3_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_RGMII_TXD3_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_RGMII_TXD3_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_RGMII_TXD3_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET1_RGMII_TXD3_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET1_RGMII_TXD3_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD3_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_RGMII_TXD3_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_RGMII_TXD3_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET1_RGMII_TXD3_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_RGMII_TXD3_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD3_lp_config_SHIFT)) & IOMUXD_ENET1_RGMII_TXD3_lp_config_MASK)
#define IOMUXD_ENET1_RGMII_TXD3_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET1_RGMII_TXD3_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_RGMII_TXD3_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD3_sw_config_SHIFT)) & IOMUXD_ENET1_RGMII_TXD3_sw_config_MASK)
#define IOMUXD_ENET1_RGMII_TXD3_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET1_RGMII_TXD3_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.RGMII_TXD3
 *  0b001..DMA.UART3.RTS_B
 *  0b010..VPU.TSI_S1.SYNC
 *  0b011..LSIO.GPIO6.IO15
 */
#define IOMUXD_ENET1_RGMII_TXD3_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD3_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_TXD3_mux_mode_MASK)
#define IOMUXD_ENET1_RGMII_TXD3_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET1_RGMII_TXD3_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET1_RGMII_TXD3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD3_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_RGMII_TXD3_update_pad_ctl_MASK)
#define IOMUXD_ENET1_RGMII_TXD3_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET1_RGMII_TXD3_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET1_RGMII_TXD3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_TXD3_update_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_TXD3_update_mux_mode_MASK)
/*! @} */

/*! @name ENET1_RGMII_RXC - ENET1_RGMII_RXC */
/*! @{ */
#define IOMUXD_ENET1_RGMII_RXC_PDRV_MASK         (0x1U)
#define IOMUXD_ENET1_RGMII_RXC_PDRV_SHIFT        (0U)
#define IOMUXD_ENET1_RGMII_RXC_PDRV(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXC_PDRV_SHIFT)) & IOMUXD_ENET1_RGMII_RXC_PDRV_MASK)
#define IOMUXD_ENET1_RGMII_RXC_ENET1_RGMII_RXC_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_RGMII_RXC_ENET1_RGMII_RXC_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_RGMII_RXC_ENET1_RGMII_RXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXC_ENET1_RGMII_RXC_reserved_1_4_SHIFT)) & IOMUXD_ENET1_RGMII_RXC_ENET1_RGMII_RXC_reserved_1_4_MASK)
#define IOMUXD_ENET1_RGMII_RXC_PULL_MASK         (0x60U)
#define IOMUXD_ENET1_RGMII_RXC_PULL_SHIFT        (5U)
#define IOMUXD_ENET1_RGMII_RXC_PULL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXC_PULL_SHIFT)) & IOMUXD_ENET1_RGMII_RXC_PULL_MASK)
#define IOMUXD_ENET1_RGMII_RXC_ENET1_RGMII_RXC_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_RGMII_RXC_ENET1_RGMII_RXC_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_RGMII_RXC_ENET1_RGMII_RXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXC_ENET1_RGMII_RXC_reserved_7_18_SHIFT)) & IOMUXD_ENET1_RGMII_RXC_ENET1_RGMII_RXC_reserved_7_18_MASK)
#define IOMUXD_ENET1_RGMII_RXC_WAKEUP_CTRL_MASK  (0x380000U)
#define IOMUXD_ENET1_RGMII_RXC_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_RGMII_RXC_WAKEUP_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_RGMII_RXC_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_RGMII_RXC_WAKEUP_MASK_MASK  (0x400000U)
#define IOMUXD_ENET1_RGMII_RXC_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET1_RGMII_RXC_WAKEUP_MASK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_RGMII_RXC_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_RGMII_RXC_lp_config_MASK    (0x1800000U)
#define IOMUXD_ENET1_RGMII_RXC_lp_config_SHIFT   (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_RGMII_RXC_lp_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXC_lp_config_SHIFT)) & IOMUXD_ENET1_RGMII_RXC_lp_config_MASK)
#define IOMUXD_ENET1_RGMII_RXC_sw_config_MASK    (0x6000000U)
#define IOMUXD_ENET1_RGMII_RXC_sw_config_SHIFT   (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_RGMII_RXC_sw_config(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXC_sw_config_SHIFT)) & IOMUXD_ENET1_RGMII_RXC_sw_config_MASK)
#define IOMUXD_ENET1_RGMII_RXC_mux_mode_MASK     (0x38000000U)
#define IOMUXD_ENET1_RGMII_RXC_mux_mode_SHIFT    (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.RGMII_RXC
 *  0b001..DMA.UART3.CTS_B
 *  0b010..VPU.TSI_S1.DATA
 *  0b011..LSIO.GPIO6.IO16
 */
#define IOMUXD_ENET1_RGMII_RXC_mux_mode(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXC_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_RXC_mux_mode_MASK)
#define IOMUXD_ENET1_RGMII_RXC_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET1_RGMII_RXC_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET1_RGMII_RXC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXC_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_RGMII_RXC_update_pad_ctl_MASK)
#define IOMUXD_ENET1_RGMII_RXC_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET1_RGMII_RXC_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET1_RGMII_RXC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXC_update_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_RXC_update_mux_mode_MASK)
/*! @} */

/*! @name ENET1_RGMII_RX_CTL - ENET1_RGMII_RX_CTL */
/*! @{ */
#define IOMUXD_ENET1_RGMII_RX_CTL_PDRV_MASK      (0x1U)
#define IOMUXD_ENET1_RGMII_RX_CTL_PDRV_SHIFT     (0U)
#define IOMUXD_ENET1_RGMII_RX_CTL_PDRV(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RX_CTL_PDRV_SHIFT)) & IOMUXD_ENET1_RGMII_RX_CTL_PDRV_MASK)
#define IOMUXD_ENET1_RGMII_RX_CTL_ENET1_RGMII_RX_CTL_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_RGMII_RX_CTL_ENET1_RGMII_RX_CTL_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_RGMII_RX_CTL_ENET1_RGMII_RX_CTL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RX_CTL_ENET1_RGMII_RX_CTL_reserved_1_4_SHIFT)) & IOMUXD_ENET1_RGMII_RX_CTL_ENET1_RGMII_RX_CTL_reserved_1_4_MASK)
#define IOMUXD_ENET1_RGMII_RX_CTL_PULL_MASK      (0x60U)
#define IOMUXD_ENET1_RGMII_RX_CTL_PULL_SHIFT     (5U)
#define IOMUXD_ENET1_RGMII_RX_CTL_PULL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RX_CTL_PULL_SHIFT)) & IOMUXD_ENET1_RGMII_RX_CTL_PULL_MASK)
#define IOMUXD_ENET1_RGMII_RX_CTL_ENET1_RGMII_RX_CTL_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_RGMII_RX_CTL_ENET1_RGMII_RX_CTL_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_RGMII_RX_CTL_ENET1_RGMII_RX_CTL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RX_CTL_ENET1_RGMII_RX_CTL_reserved_7_18_SHIFT)) & IOMUXD_ENET1_RGMII_RX_CTL_ENET1_RGMII_RX_CTL_reserved_7_18_MASK)
#define IOMUXD_ENET1_RGMII_RX_CTL_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET1_RGMII_RX_CTL_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_RGMII_RX_CTL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RX_CTL_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_RGMII_RX_CTL_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_RGMII_RX_CTL_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET1_RGMII_RX_CTL_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET1_RGMII_RX_CTL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RX_CTL_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_RGMII_RX_CTL_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_RGMII_RX_CTL_lp_config_MASK (0x1800000U)
#define IOMUXD_ENET1_RGMII_RX_CTL_lp_config_SHIFT (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_RGMII_RX_CTL_lp_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RX_CTL_lp_config_SHIFT)) & IOMUXD_ENET1_RGMII_RX_CTL_lp_config_MASK)
#define IOMUXD_ENET1_RGMII_RX_CTL_sw_config_MASK (0x6000000U)
#define IOMUXD_ENET1_RGMII_RX_CTL_sw_config_SHIFT (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_RGMII_RX_CTL_sw_config(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RX_CTL_sw_config_SHIFT)) & IOMUXD_ENET1_RGMII_RX_CTL_sw_config_MASK)
#define IOMUXD_ENET1_RGMII_RX_CTL_mux_mode_MASK  (0x38000000U)
#define IOMUXD_ENET1_RGMII_RX_CTL_mux_mode_SHIFT (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.RGMII_RX_CTL
 *  0b010..VPU.TSI_S0.VID
 *  0b011..LSIO.GPIO6.IO17
 */
#define IOMUXD_ENET1_RGMII_RX_CTL_mux_mode(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RX_CTL_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_RX_CTL_mux_mode_MASK)
#define IOMUXD_ENET1_RGMII_RX_CTL_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET1_RGMII_RX_CTL_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET1_RGMII_RX_CTL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RX_CTL_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_RGMII_RX_CTL_update_pad_ctl_MASK)
#define IOMUXD_ENET1_RGMII_RX_CTL_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET1_RGMII_RX_CTL_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET1_RGMII_RX_CTL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RX_CTL_update_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_RX_CTL_update_mux_mode_MASK)
/*! @} */

/*! @name ENET1_RGMII_RXD0 - ENET1_RGMII_RXD0 */
/*! @{ */
#define IOMUXD_ENET1_RGMII_RXD0_PDRV_MASK        (0x1U)
#define IOMUXD_ENET1_RGMII_RXD0_PDRV_SHIFT       (0U)
#define IOMUXD_ENET1_RGMII_RXD0_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD0_PDRV_SHIFT)) & IOMUXD_ENET1_RGMII_RXD0_PDRV_MASK)
#define IOMUXD_ENET1_RGMII_RXD0_ENET1_RGMII_RXD0_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_RGMII_RXD0_ENET1_RGMII_RXD0_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_RGMII_RXD0_ENET1_RGMII_RXD0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD0_ENET1_RGMII_RXD0_reserved_1_4_SHIFT)) & IOMUXD_ENET1_RGMII_RXD0_ENET1_RGMII_RXD0_reserved_1_4_MASK)
#define IOMUXD_ENET1_RGMII_RXD0_PULL_MASK        (0x60U)
#define IOMUXD_ENET1_RGMII_RXD0_PULL_SHIFT       (5U)
#define IOMUXD_ENET1_RGMII_RXD0_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD0_PULL_SHIFT)) & IOMUXD_ENET1_RGMII_RXD0_PULL_MASK)
#define IOMUXD_ENET1_RGMII_RXD0_ENET1_RGMII_RXD0_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_RGMII_RXD0_ENET1_RGMII_RXD0_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_RGMII_RXD0_ENET1_RGMII_RXD0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD0_ENET1_RGMII_RXD0_reserved_7_18_SHIFT)) & IOMUXD_ENET1_RGMII_RXD0_ENET1_RGMII_RXD0_reserved_7_18_MASK)
#define IOMUXD_ENET1_RGMII_RXD0_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET1_RGMII_RXD0_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_RGMII_RXD0_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_RGMII_RXD0_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_RGMII_RXD0_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET1_RGMII_RXD0_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET1_RGMII_RXD0_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD0_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_RGMII_RXD0_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_RGMII_RXD0_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET1_RGMII_RXD0_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_RGMII_RXD0_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD0_lp_config_SHIFT)) & IOMUXD_ENET1_RGMII_RXD0_lp_config_MASK)
#define IOMUXD_ENET1_RGMII_RXD0_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET1_RGMII_RXD0_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_RGMII_RXD0_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD0_sw_config_SHIFT)) & IOMUXD_ENET1_RGMII_RXD0_sw_config_MASK)
#define IOMUXD_ENET1_RGMII_RXD0_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET1_RGMII_RXD0_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.RGMII_RXD0
 *  0b010..VPU.TSI_S0.SYNC
 *  0b011..LSIO.GPIO6.IO18
 */
#define IOMUXD_ENET1_RGMII_RXD0_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD0_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_RXD0_mux_mode_MASK)
#define IOMUXD_ENET1_RGMII_RXD0_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET1_RGMII_RXD0_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET1_RGMII_RXD0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD0_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_RGMII_RXD0_update_pad_ctl_MASK)
#define IOMUXD_ENET1_RGMII_RXD0_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET1_RGMII_RXD0_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET1_RGMII_RXD0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD0_update_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_RXD0_update_mux_mode_MASK)
/*! @} */

/*! @name ENET1_RGMII_RXD1 - ENET1_RGMII_RXD1 */
/*! @{ */
#define IOMUXD_ENET1_RGMII_RXD1_PDRV_MASK        (0x1U)
#define IOMUXD_ENET1_RGMII_RXD1_PDRV_SHIFT       (0U)
#define IOMUXD_ENET1_RGMII_RXD1_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD1_PDRV_SHIFT)) & IOMUXD_ENET1_RGMII_RXD1_PDRV_MASK)
#define IOMUXD_ENET1_RGMII_RXD1_ENET1_RGMII_RXD1_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_RGMII_RXD1_ENET1_RGMII_RXD1_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_RGMII_RXD1_ENET1_RGMII_RXD1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD1_ENET1_RGMII_RXD1_reserved_1_4_SHIFT)) & IOMUXD_ENET1_RGMII_RXD1_ENET1_RGMII_RXD1_reserved_1_4_MASK)
#define IOMUXD_ENET1_RGMII_RXD1_PULL_MASK        (0x60U)
#define IOMUXD_ENET1_RGMII_RXD1_PULL_SHIFT       (5U)
#define IOMUXD_ENET1_RGMII_RXD1_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD1_PULL_SHIFT)) & IOMUXD_ENET1_RGMII_RXD1_PULL_MASK)
#define IOMUXD_ENET1_RGMII_RXD1_ENET1_RGMII_RXD1_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_RGMII_RXD1_ENET1_RGMII_RXD1_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_RGMII_RXD1_ENET1_RGMII_RXD1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD1_ENET1_RGMII_RXD1_reserved_7_18_SHIFT)) & IOMUXD_ENET1_RGMII_RXD1_ENET1_RGMII_RXD1_reserved_7_18_MASK)
#define IOMUXD_ENET1_RGMII_RXD1_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET1_RGMII_RXD1_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_RGMII_RXD1_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_RGMII_RXD1_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_RGMII_RXD1_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET1_RGMII_RXD1_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET1_RGMII_RXD1_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD1_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_RGMII_RXD1_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_RGMII_RXD1_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET1_RGMII_RXD1_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_RGMII_RXD1_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD1_lp_config_SHIFT)) & IOMUXD_ENET1_RGMII_RXD1_lp_config_MASK)
#define IOMUXD_ENET1_RGMII_RXD1_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET1_RGMII_RXD1_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_RGMII_RXD1_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD1_sw_config_SHIFT)) & IOMUXD_ENET1_RGMII_RXD1_sw_config_MASK)
#define IOMUXD_ENET1_RGMII_RXD1_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET1_RGMII_RXD1_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.RGMII_RXD1
 *  0b010..VPU.TSI_S0.DATA
 *  0b011..LSIO.GPIO6.IO19
 */
#define IOMUXD_ENET1_RGMII_RXD1_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD1_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_RXD1_mux_mode_MASK)
#define IOMUXD_ENET1_RGMII_RXD1_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET1_RGMII_RXD1_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET1_RGMII_RXD1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD1_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_RGMII_RXD1_update_pad_ctl_MASK)
#define IOMUXD_ENET1_RGMII_RXD1_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET1_RGMII_RXD1_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET1_RGMII_RXD1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD1_update_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_RXD1_update_mux_mode_MASK)
/*! @} */

/*! @name ENET1_RGMII_RXD2 - ENET1_RGMII_RXD2 */
/*! @{ */
#define IOMUXD_ENET1_RGMII_RXD2_PDRV_MASK        (0x1U)
#define IOMUXD_ENET1_RGMII_RXD2_PDRV_SHIFT       (0U)
#define IOMUXD_ENET1_RGMII_RXD2_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD2_PDRV_SHIFT)) & IOMUXD_ENET1_RGMII_RXD2_PDRV_MASK)
#define IOMUXD_ENET1_RGMII_RXD2_ENET1_RGMII_RXD2_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_RGMII_RXD2_ENET1_RGMII_RXD2_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_RGMII_RXD2_ENET1_RGMII_RXD2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD2_ENET1_RGMII_RXD2_reserved_1_4_SHIFT)) & IOMUXD_ENET1_RGMII_RXD2_ENET1_RGMII_RXD2_reserved_1_4_MASK)
#define IOMUXD_ENET1_RGMII_RXD2_PULL_MASK        (0x60U)
#define IOMUXD_ENET1_RGMII_RXD2_PULL_SHIFT       (5U)
#define IOMUXD_ENET1_RGMII_RXD2_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD2_PULL_SHIFT)) & IOMUXD_ENET1_RGMII_RXD2_PULL_MASK)
#define IOMUXD_ENET1_RGMII_RXD2_ENET1_RGMII_RXD2_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_RGMII_RXD2_ENET1_RGMII_RXD2_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_RGMII_RXD2_ENET1_RGMII_RXD2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD2_ENET1_RGMII_RXD2_reserved_7_18_SHIFT)) & IOMUXD_ENET1_RGMII_RXD2_ENET1_RGMII_RXD2_reserved_7_18_MASK)
#define IOMUXD_ENET1_RGMII_RXD2_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET1_RGMII_RXD2_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_RGMII_RXD2_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_RGMII_RXD2_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_RGMII_RXD2_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET1_RGMII_RXD2_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET1_RGMII_RXD2_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD2_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_RGMII_RXD2_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_RGMII_RXD2_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET1_RGMII_RXD2_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_RGMII_RXD2_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD2_lp_config_SHIFT)) & IOMUXD_ENET1_RGMII_RXD2_lp_config_MASK)
#define IOMUXD_ENET1_RGMII_RXD2_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET1_RGMII_RXD2_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_RGMII_RXD2_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD2_sw_config_SHIFT)) & IOMUXD_ENET1_RGMII_RXD2_sw_config_MASK)
#define IOMUXD_ENET1_RGMII_RXD2_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET1_RGMII_RXD2_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.RGMII_RXD2
 *  0b001..CONN.ENET1.RMII_RX_ER
 *  0b010..VPU.TSI_S0.CLK
 *  0b011..LSIO.GPIO6.IO20
 */
#define IOMUXD_ENET1_RGMII_RXD2_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD2_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_RXD2_mux_mode_MASK)
#define IOMUXD_ENET1_RGMII_RXD2_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET1_RGMII_RXD2_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET1_RGMII_RXD2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD2_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_RGMII_RXD2_update_pad_ctl_MASK)
#define IOMUXD_ENET1_RGMII_RXD2_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET1_RGMII_RXD2_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET1_RGMII_RXD2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD2_update_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_RXD2_update_mux_mode_MASK)
/*! @} */

/*! @name ENET1_RGMII_RXD3 - ENET1_RGMII_RXD3 */
/*! @{ */
#define IOMUXD_ENET1_RGMII_RXD3_PDRV_MASK        (0x1U)
#define IOMUXD_ENET1_RGMII_RXD3_PDRV_SHIFT       (0U)
#define IOMUXD_ENET1_RGMII_RXD3_PDRV(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD3_PDRV_SHIFT)) & IOMUXD_ENET1_RGMII_RXD3_PDRV_MASK)
#define IOMUXD_ENET1_RGMII_RXD3_ENET1_RGMII_RXD3_reserved_1_4_MASK (0x1EU)
#define IOMUXD_ENET1_RGMII_RXD3_ENET1_RGMII_RXD3_reserved_1_4_SHIFT (1U)
#define IOMUXD_ENET1_RGMII_RXD3_ENET1_RGMII_RXD3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD3_ENET1_RGMII_RXD3_reserved_1_4_SHIFT)) & IOMUXD_ENET1_RGMII_RXD3_ENET1_RGMII_RXD3_reserved_1_4_MASK)
#define IOMUXD_ENET1_RGMII_RXD3_PULL_MASK        (0x60U)
#define IOMUXD_ENET1_RGMII_RXD3_PULL_SHIFT       (5U)
#define IOMUXD_ENET1_RGMII_RXD3_PULL(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD3_PULL_SHIFT)) & IOMUXD_ENET1_RGMII_RXD3_PULL_MASK)
#define IOMUXD_ENET1_RGMII_RXD3_ENET1_RGMII_RXD3_reserved_7_18_MASK (0x7FF80U)
#define IOMUXD_ENET1_RGMII_RXD3_ENET1_RGMII_RXD3_reserved_7_18_SHIFT (7U)
#define IOMUXD_ENET1_RGMII_RXD3_ENET1_RGMII_RXD3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD3_ENET1_RGMII_RXD3_reserved_7_18_SHIFT)) & IOMUXD_ENET1_RGMII_RXD3_ENET1_RGMII_RXD3_reserved_7_18_MASK)
#define IOMUXD_ENET1_RGMII_RXD3_WAKEUP_CTRL_MASK (0x380000U)
#define IOMUXD_ENET1_RGMII_RXD3_WAKEUP_CTRL_SHIFT (19U)
/*! WAKEUP_CTRL - wakeup control
 *  0b000..OFF
 *  0b001..RESAMPLE
 *  0b100..LOW
 *  0b111..HIGH
 *  0b110..RISE
 *  0b101..FALL
 */
#define IOMUXD_ENET1_RGMII_RXD3_WAKEUP_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET1_RGMII_RXD3_WAKEUP_CTRL_MASK)
#define IOMUXD_ENET1_RGMII_RXD3_WAKEUP_MASK_MASK (0x400000U)
#define IOMUXD_ENET1_RGMII_RXD3_WAKEUP_MASK_SHIFT (22U)
#define IOMUXD_ENET1_RGMII_RXD3_WAKEUP_MASK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD3_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET1_RGMII_RXD3_WAKEUP_MASK_MASK)
#define IOMUXD_ENET1_RGMII_RXD3_lp_config_MASK   (0x1800000U)
#define IOMUXD_ENET1_RGMII_RXD3_lp_config_SHIFT  (23U)
/*! lp_config - lower power configuration
 *  0b01..EARLY_ISO
 *  0b10..LATE_ISO
 *  0b11..LATCH
 *  0b00..PASS
 */
#define IOMUXD_ENET1_RGMII_RXD3_lp_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD3_lp_config_SHIFT)) & IOMUXD_ENET1_RGMII_RXD3_lp_config_MASK)
#define IOMUXD_ENET1_RGMII_RXD3_sw_config_MASK   (0x6000000U)
#define IOMUXD_ENET1_RGMII_RXD3_sw_config_SHIFT  (25U)
/*! sw_config - output and input configuration
 *  0b01..OPEN_DRAIN
 *  0b10..OPEN_DRAIN_INPUT
 *  0b11..INOUT
 *  0b00..DEFAULT
 */
#define IOMUXD_ENET1_RGMII_RXD3_sw_config(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD3_sw_config_SHIFT)) & IOMUXD_ENET1_RGMII_RXD3_sw_config_MASK)
#define IOMUXD_ENET1_RGMII_RXD3_mux_mode_MASK    (0x38000000U)
#define IOMUXD_ENET1_RGMII_RXD3_mux_mode_SHIFT   (27U)
/*! mux_mode - mux_mode
 *  0b000..CONN.ENET1.RGMII_RXD3
 *  0b001..DMA.UART3.RX
 *  0b010..VPU.TSI_S1.CLK
 *  0b011..LSIO.GPIO6.IO21
 */
#define IOMUXD_ENET1_RGMII_RXD3_mux_mode(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD3_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_RXD3_mux_mode_MASK)
#define IOMUXD_ENET1_RGMII_RXD3_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_ENET1_RGMII_RXD3_update_pad_ctl_SHIFT (30U)
#define IOMUXD_ENET1_RGMII_RXD3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD3_update_pad_ctl_SHIFT)) & IOMUXD_ENET1_RGMII_RXD3_update_pad_ctl_MASK)
#define IOMUXD_ENET1_RGMII_RXD3_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_ENET1_RGMII_RXD3_update_mux_mode_SHIFT (31U)
#define IOMUXD_ENET1_RGMII_RXD3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET1_RGMII_RXD3_update_mux_mode_SHIFT)) & IOMUXD_ENET1_RGMII_RXD3_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA - IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA */
/*! @{ */
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_COMP_MASK (0x7U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_COMP_SHIFT (0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_COMP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_FASTFRZ_EN_MASK (0x8U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_FASTFRZ_EN_SHIFT (3U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_FASTFRZ_EN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PSW_OVR_MASK (0x10U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PSW_OVR_SHIFT (4U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PSW_OVR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PSW_OVR_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PSW_OVR_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_RASRCP_MASK (0x1E0U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_RASRCP_SHIFT (5U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_RASRCP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_RASRCN_MASK (0x1E00U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_RASRCN_SHIFT (9U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_RASRCN_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_SELECT_NASRC_MASK (0x2000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_SELECT_NASRC_SHIFT (13U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_SELECT_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_COMPOK_MASK (0x4000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_COMPOK_SHIFT (14U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_COMPOK_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_READ_NASRC_MASK (0x78000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_READ_NASRC_SHIFT (15U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_READ_NASRC_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_reserved_19_22_MASK (0x780000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_reserved_19_22_SHIFT (19U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_reserved_19_22_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_SLEEP_MASK (0x1800000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_SLEEP_SHIFT (23U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_SLEEP_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_reserved_25_29_MASK (0x3E000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_reserved_25_29_SHIFT (25U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_reserved_25_29_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_update_pad_ctl_MASK (0x40000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_update_pad_ctl_SHIFT (30U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_update_pad_ctl_MASK)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_update_mux_mode_MASK (0x80000000U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_update_mux_mode_SHIFT (31U)
#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_update_mux_mode_MASK)
/*! @} */

/*! @name IOMUXD_GROUP_3_3 - na */
/*! @{ */
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TX_CTL_MASK (0x1U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TX_CTL_SHIFT (0U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TX_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TX_CTL_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TX_CTL_MASK)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD0_MASK (0x2U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD0_SHIFT (1U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD0_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD0_MASK)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD1_MASK (0x4U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD1_SHIFT (2U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD1_MASK)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD2_MASK (0x8U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD2_SHIFT (3U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD2_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD2_MASK)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD3_MASK (0x10U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD3_SHIFT (4U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD3_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_TXD3_MASK)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXC_MASK (0x20U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXC_SHIFT (5U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXC_MASK)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RX_CTL_MASK (0x40U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RX_CTL_SHIFT (6U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RX_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RX_CTL_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RX_CTL_MASK)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD0_MASK (0x80U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD0_SHIFT (7U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD0_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD0_MASK)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD1_MASK (0x100U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD1_SHIFT (8U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD1_MASK)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD2_MASK (0x200U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD2_SHIFT (9U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD2_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD2_MASK)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD3_MASK (0x400U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD3_SHIFT (10U)
#define IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD3_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_3_ENET1_RGMII_RXD3_MASK)
#define IOMUXD_IOMUXD_GROUP_3_3_iomuxd_group_3_3_reserved_11_31_MASK (0xFFFFF800U)
#define IOMUXD_IOMUXD_GROUP_3_3_iomuxd_group_3_3_reserved_11_31_SHIFT (11U)
#define IOMUXD_IOMUXD_GROUP_3_3_iomuxd_group_3_3_reserved_11_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_3_iomuxd_group_3_3_reserved_11_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_3_iomuxd_group_3_3_reserved_11_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IOMUXD_Register_Masks */


/* IOMUXD - Peripheral instance base addresses */
/** Peripheral IOMUXD base address */
#define IOMUXD_BASE                              (0x33F80000u)
/** Peripheral IOMUXD base pointer */
#define IOMUXD                                   ((IOMUXD_Type *)IOMUXD_BASE)
/** Array initializer of IOMUXD peripheral base addresses */
#define IOMUXD_BASE_ADDRS                        { IOMUXD_BASE }
/** Array initializer of IOMUXD peripheral base pointers */
#define IOMUXD_BASE_PTRS                         { IOMUXD }

/*!
 * @}
 */ /* end of group IOMUXD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IRIS_MVPL Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IRIS_MVPL_Peripheral_Access_Layer IRIS_MVPL Peripheral Access Layer
 * @{
 */

/** IRIS_MVPL - Register Layout Typedef */
typedef struct {
  __IO uint32_t COMCTRL_IPIDENTIFIER;              /**< IP Identifier for this IMX DPU derivate., offset: 0x0 */
       uint8_t RESERVED_0[124];
  __I  uint32_t COMCTRL_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0x80 */
  __I  uint32_t COMCTRL_LOCKSTATUS;                /**< Protection status of this address block., offset: 0x84 */
  __IO uint32_t COMCTRL_USERINTERRUPTMASK0;        /**< Interrupt UserMask register 0, offset: 0x88 */
  __IO uint32_t COMCTRL_USERINTERRUPTMASK1;        /**< Interrupt UserMask register 1, offset: 0x8C */
  __IO uint32_t COMCTRL_USERINTERRUPTMASK2;        /**< Interrupt UserMask register 2, offset: 0x90 */
  __I  uint32_t COMCTRL_INTERRUPTENABLE0;          /**< Interrupt Enable register 0, offset: 0x94 */
  __I  uint32_t COMCTRL_INTERRUPTENABLE1;          /**< Interrupt Enable register 1, offset: 0x98 */
  __I  uint32_t COMCTRL_INTERRUPTENABLE2;          /**< Interrupt Enable register 2, offset: 0x9C */
  __O  uint32_t COMCTRL_INTERRUPTPRESET0;          /**< Interrupt Preset register 0, offset: 0xA0 */
  __O  uint32_t COMCTRL_INTERRUPTPRESET1;          /**< Interrupt Preset register 1, offset: 0xA4 */
  __O  uint32_t COMCTRL_INTERRUPTPRESET2;          /**< Interrupt Preset register 2, offset: 0xA8 */
  __O  uint32_t COMCTRL_INTERRUPTCLEAR0;           /**< Interrupt Clear register 0, offset: 0xAC */
  __O  uint32_t COMCTRL_INTERRUPTCLEAR1;           /**< Interrupt Clear register 1, offset: 0xB0 */
  __O  uint32_t COMCTRL_INTERRUPTCLEAR2;           /**< Interrupt Clear register 2, offset: 0xB4 */
  __I  uint32_t COMCTRL_INTERRUPTSTATUS0;          /**< Interrupt Status register 0, offset: 0xB8 */
  __I  uint32_t COMCTRL_INTERRUPTSTATUS1;          /**< Interrupt Status register 1, offset: 0xBC */
  __I  uint32_t COMCTRL_INTERRUPTSTATUS2;          /**< Interrupt Status register 2, offset: 0xC0 */
       uint8_t RESERVED_1[60];
  __I  uint32_t COMCTRL_USERINTERRUPTENABLE0;      /**< Interrupt Enable register 0 for user mode access, offset: 0x100 */
  __I  uint32_t COMCTRL_USERINTERRUPTENABLE1;      /**< Interrupt Enable register 1 for user mode access, offset: 0x104 */
  __I  uint32_t COMCTRL_USERINTERRUPTENABLE2;      /**< Interrupt Enable register 2 for user mode access, offset: 0x108 */
  __O  uint32_t COMCTRL_USERINTERRUPTPRESET0;      /**< Interrupt Preset register 0, offset: 0x10C */
  __O  uint32_t COMCTRL_USERINTERRUPTPRESET1;      /**< Interrupt Preset register 1, offset: 0x110 */
  __O  uint32_t COMCTRL_USERINTERRUPTPRESET2;      /**< Interrupt Preset register 2, offset: 0x114 */
  __O  uint32_t COMCTRL_USERINTERRUPTCLEAR0;       /**< Interrupt Clear register 0, offset: 0x118 */
  __O  uint32_t COMCTRL_USERINTERRUPTCLEAR1;       /**< Interrupt Clear register 1, offset: 0x11C */
  __O  uint32_t COMCTRL_USERINTERRUPTCLEAR2;       /**< Interrupt Clear register 2, offset: 0x120 */
  __I  uint32_t COMCTRL_USERINTERRUPTSTATUS0;      /**< Interrupt Status register 0, offset: 0x124 */
  __I  uint32_t COMCTRL_USERINTERRUPTSTATUS1;      /**< Interrupt Status register 1, offset: 0x128 */
  __I  uint32_t COMCTRL_USERINTERRUPTSTATUS2;      /**< Interrupt Status register 2, offset: 0x12C */
       uint8_t RESERVED_2[208];
  __IO uint32_t COMCTRL_GENERALPURPOSE;            /**< General purpose config memory, offset: 0x200 */
       uint8_t RESERVED_3[508];
  __I  uint32_t CMDSEQ_HIF;                        /**< Command input buffer, offset: 0x400 */
       uint8_t RESERVED_4[252];
  __I  uint32_t CMDSEQ_LOCKUNLOCKHIF;              /**< Register to change the protection status of this address block., offset: 0x500 */
  __I  uint32_t CMDSEQ_LOCKSTATUSHIF;              /**< Protection status of this address block., offset: 0x504 */
       uint8_t RESERVED_5[120];
  __I  uint32_t CMDSEQ_LOCKUNLOCK;                 /**< Register to change the protection status of this address block., offset: 0x580 */
  __I  uint32_t CMDSEQ_LOCKSTATUS;                 /**< Protection status of this address block., offset: 0x584 */
  __IO uint32_t CMDSEQ_BUFFERADDRESS;              /**< Command buffer address register, offset: 0x588 */
  __IO uint32_t CMDSEQ_BUFFERSIZE;                 /**< Command buffer size register, offset: 0x58C */
  __IO uint32_t CMDSEQ_WATERMARKCONTROL;           /**< Watermark Control register, offset: 0x590 */
  __O  uint32_t CMDSEQ_CONTROL;                    /**< Control register, offset: 0x594 */
  __I  uint32_t CMDSEQ_STATUS;                     /**< Status register, offset: 0x598 */
  __IO uint32_t CMDSEQ_PREFETCHWINDOWSTART;        /**< PrefetchWindowStart register, offset: 0x59C */
  __IO uint32_t CMDSEQ_PREFETCHWINDOWEND;          /**< PrefetchWindowEnd register, offset: 0x5A0 */
       uint8_t RESERVED_6[604];
  __I  uint32_t PIXENGCFG_SAFETYLOCKUNLOCK;        /**< Register to change the protection status of this address block., offset: 0x800 */
  __I  uint32_t PIXENGCFG_SAFETYLOCKSTATUS;        /**< Protection status of this address block., offset: 0x804 */
  __IO uint32_t PIXENGCFG_STORE9_SAFETYMASK_0;     /**< Safety mask 0 for store9, offset: 0x808 */
  __IO uint32_t PIXENGCFG_STORE9_SAFETYMASK_1;     /**< Safety mask 1 for store9, offset: 0x80C */
  __IO uint32_t PIXENGCFG_EXTDST0_SAFETYMASK_0;    /**< Safety mask 0 for extdst0, offset: 0x810 */
  __IO uint32_t PIXENGCFG_EXTDST0_SAFETYMASK_1;    /**< Safety mask 1 for extdst0, offset: 0x814 */
  __IO uint32_t PIXENGCFG_EXTDST4_SAFETYMASK_0;    /**< Safety mask 0 for extdst4, offset: 0x818 */
  __IO uint32_t PIXENGCFG_EXTDST4_SAFETYMASK_1;    /**< Safety mask 1 for extdst4, offset: 0x81C */
  __IO uint32_t PIXENGCFG_EXTDST1_SAFETYMASK_0;    /**< Safety mask 0 for extdst1, offset: 0x820 */
  __IO uint32_t PIXENGCFG_EXTDST1_SAFETYMASK_1;    /**< Safety mask 1 for extdst1, offset: 0x824 */
  __IO uint32_t PIXENGCFG_EXTDST5_SAFETYMASK_0;    /**< Safety mask 0 for extdst5, offset: 0x828 */
  __IO uint32_t PIXENGCFG_EXTDST5_SAFETYMASK_1;    /**< Safety mask 1 for extdst5, offset: 0x82C */
  __IO uint32_t PIXENGCFG_STORE4_SAFETYMASK_0;     /**< Safety mask 0 for store4, offset: 0x830 */
  __IO uint32_t PIXENGCFG_STORE4_SAFETYMASK_1;     /**< Safety mask 1 for store4, offset: 0x834 */
  __IO uint32_t PIXENGCFG_STORE5_SAFETYMASK_0;     /**< Safety mask 0 for store5, offset: 0x838 */
  __IO uint32_t PIXENGCFG_STORE5_SAFETYMASK_1;     /**< Safety mask 1 for store5, offset: 0x83C */
  __I  uint32_t PIXENGCFG_FETCHDECODE9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x840 */
  __I  uint32_t PIXENGCFG_FETCHDECODE9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x844 */
  __IO uint32_t PIXENGCFG_FETCHDECODE9_DYNAMIC;    /**< Dynamic pixel engine configuration for fetchdecode9, offset: 0x848 */
  __I  uint32_t PIXENGCFG_FETCHDECODE9_STATUS;     /**< Status information for pixel engine configuration of fetchdecode9, offset: 0x84C */
       uint8_t RESERVED_7[16];
  __I  uint32_t PIXENGCFG_FETCHPERSP9_LOCKUNLOCK;  /**< Register to change the protection status of this address block., offset: 0x860 */
  __I  uint32_t PIXENGCFG_FETCHPERSP9_LOCKSTATUS;  /**< Protection status of this address block., offset: 0x864 */
  __IO uint32_t PIXENGCFG_FETCHPERSP9_DYNAMIC;     /**< Dynamic pixel engine configuration for fetchpersp9, offset: 0x868 */
  __I  uint32_t PIXENGCFG_FETCHPERSP9_STATUS;      /**< Status information for pixel engine configuration of fetchpersp9, offset: 0x86C */
  __I  uint32_t PIXENGCFG_FETCHECO9_LOCKUNLOCK;    /**< Register to change the protection status of this address block., offset: 0x870 */
  __I  uint32_t PIXENGCFG_FETCHECO9_LOCKSTATUS;    /**< Protection status of this address block., offset: 0x874 */
  __I  uint32_t PIXENGCFG_FETCHECO9_STATUS;        /**< Status information for pixel engine configuration of fetcheco9, offset: 0x878 */
       uint8_t RESERVED_8[4];
  __I  uint32_t PIXENGCFG_ROP9_LOCKUNLOCK;         /**< Register to change the protection status of this address block., offset: 0x880 */
  __I  uint32_t PIXENGCFG_ROP9_LOCKSTATUS;         /**< Protection status of this address block., offset: 0x884 */
  __IO uint32_t PIXENGCFG_ROP9_DYNAMIC;            /**< Dynamic pixel engine configuration for rop9, offset: 0x888 */
  __I  uint32_t PIXENGCFG_ROP9_STATUS;             /**< Status information for pixel engine configuration of rop9, offset: 0x88C */
       uint8_t RESERVED_9[16];
  __I  uint32_t PIXENGCFG_CLUT9_LOCKUNLOCK;        /**< Register to change the protection status of this address block., offset: 0x8A0 */
  __I  uint32_t PIXENGCFG_CLUT9_LOCKSTATUS;        /**< Protection status of this address block., offset: 0x8A4 */
  __IO uint32_t PIXENGCFG_CLUT9_DYNAMIC;           /**< Dynamic pixel engine configuration for clut9, offset: 0x8A8 */
  __I  uint32_t PIXENGCFG_CLUT9_STATUS;            /**< Status information for pixel engine configuration of clut9, offset: 0x8AC */
       uint8_t RESERVED_10[16];
  __I  uint32_t PIXENGCFG_MATRIX9_LOCKUNLOCK;      /**< Register to change the protection status of this address block., offset: 0x8C0 */
  __I  uint32_t PIXENGCFG_MATRIX9_LOCKSTATUS;      /**< Protection status of this address block., offset: 0x8C4 */
  __IO uint32_t PIXENGCFG_MATRIX9_DYNAMIC;         /**< Dynamic pixel engine configuration for matrix9, offset: 0x8C8 */
  __I  uint32_t PIXENGCFG_MATRIX9_STATUS;          /**< Status information for pixel engine configuration of matrix9, offset: 0x8CC */
       uint8_t RESERVED_11[16];
  __I  uint32_t PIXENGCFG_HSCALER9_LOCKUNLOCK;     /**< Register to change the protection status of this address block., offset: 0x8E0 */
  __I  uint32_t PIXENGCFG_HSCALER9_LOCKSTATUS;     /**< Protection status of this address block., offset: 0x8E4 */
  __IO uint32_t PIXENGCFG_HSCALER9_DYNAMIC;        /**< Dynamic pixel engine configuration for hscaler9, offset: 0x8E8 */
  __I  uint32_t PIXENGCFG_HSCALER9_STATUS;         /**< Status information for pixel engine configuration of hscaler9, offset: 0x8EC */
       uint8_t RESERVED_12[16];
  __I  uint32_t PIXENGCFG_VSCALER9_LOCKUNLOCK;     /**< Register to change the protection status of this address block., offset: 0x900 */
  __I  uint32_t PIXENGCFG_VSCALER9_LOCKSTATUS;     /**< Protection status of this address block., offset: 0x904 */
  __IO uint32_t PIXENGCFG_VSCALER9_DYNAMIC;        /**< Dynamic pixel engine configuration for vscaler9, offset: 0x908 */
  __I  uint32_t PIXENGCFG_VSCALER9_STATUS;         /**< Status information for pixel engine configuration of vscaler9, offset: 0x90C */
       uint8_t RESERVED_13[16];
  __I  uint32_t PIXENGCFG_FILTER9_LOCKUNLOCK;      /**< Register to change the protection status of this address block., offset: 0x920 */
  __I  uint32_t PIXENGCFG_FILTER9_LOCKSTATUS;      /**< Protection status of this address block., offset: 0x924 */
  __IO uint32_t PIXENGCFG_FILTER9_DYNAMIC;         /**< Dynamic pixel engine configuration for filter9, offset: 0x928 */
  __I  uint32_t PIXENGCFG_FILTER9_STATUS;          /**< Status information for pixel engine configuration of filter9, offset: 0x92C */
       uint8_t RESERVED_14[16];
  __I  uint32_t PIXENGCFG_BLITBLEND9_LOCKUNLOCK;   /**< Register to change the protection status of this address block., offset: 0x940 */
  __I  uint32_t PIXENGCFG_BLITBLEND9_LOCKSTATUS;   /**< Protection status of this address block., offset: 0x944 */
  __IO uint32_t PIXENGCFG_BLITBLEND9_DYNAMIC;      /**< Dynamic pixel engine configuration for blitblend9, offset: 0x948 */
  __I  uint32_t PIXENGCFG_BLITBLEND9_STATUS;       /**< Status information for pixel engine configuration of blitblend9, offset: 0x94C */
       uint8_t RESERVED_15[16];
  __I  uint32_t PIXENGCFG_STORE9_LOCKUNLOCK;       /**< Register to change the protection status of this address block., offset: 0x960 */
  __I  uint32_t PIXENGCFG_STORE9_LOCKSTATUS;       /**< Protection status of this address block., offset: 0x964 */
  __IO uint32_t PIXENGCFG_STORE9_STATIC;           /**< Static pixel engine configuration for store9, offset: 0x968 */
  __IO uint32_t PIXENGCFG_STORE9_DYNAMIC;          /**< Dynamic pixel engine configuration for store9, offset: 0x96C */
  __I  uint32_t PIXENGCFG_STORE9_REQUEST;          /**< ShadowLoadRequest register for endpoint store9, offset: 0x970 */
  __O  uint32_t PIXENGCFG_STORE9_TRIGGER;          /**< Trigger bits for pixel engine configuration of store9, offset: 0x974 */
  __I  uint32_t PIXENGCFG_STORE9_STATUS;           /**< Status information for pixel engine configuration of store9, offset: 0x978 */
       uint8_t RESERVED_16[4];
  __I  uint32_t PIXENGCFG_CONSTFRAME0_LOCKUNLOCK;  /**< Register to change the protection status of this address block., offset: 0x980 */
  __I  uint32_t PIXENGCFG_CONSTFRAME0_LOCKSTATUS;  /**< Protection status of this address block., offset: 0x984 */
  __I  uint32_t PIXENGCFG_CONSTFRAME0_STATUS;      /**< Status information for pixel engine configuration of constframe0, offset: 0x988 */
       uint8_t RESERVED_17[20];
  __I  uint32_t PIXENGCFG_EXTDST0_LOCKUNLOCK;      /**< Register to change the protection status of this address block., offset: 0x9A0 */
  __I  uint32_t PIXENGCFG_EXTDST0_LOCKSTATUS;      /**< Protection status of this address block., offset: 0x9A4 */
  __IO uint32_t PIXENGCFG_EXTDST0_STATIC;          /**< Static pixel engine configuration for extdst0, offset: 0x9A8 */
  __IO uint32_t PIXENGCFG_EXTDST0_DYNAMIC;         /**< Dynamic pixel engine configuration for extdst0, offset: 0x9AC */
  __I  uint32_t PIXENGCFG_EXTDST0_REQUEST;         /**< ShadowLoadRequest register for endpoint extdst0, offset: 0x9B0 */
  __O  uint32_t PIXENGCFG_EXTDST0_TRIGGER;         /**< Trigger bits for pixel engine configuration of extdst0, offset: 0x9B4 */
  __I  uint32_t PIXENGCFG_EXTDST0_STATUS;          /**< Status information for pixel engine configuration of extdst0, offset: 0x9B8 */
       uint8_t RESERVED_18[4];
  __I  uint32_t PIXENGCFG_CONSTFRAME4_LOCKUNLOCK;  /**< Register to change the protection status of this address block., offset: 0x9C0 */
  __I  uint32_t PIXENGCFG_CONSTFRAME4_LOCKSTATUS;  /**< Protection status of this address block., offset: 0x9C4 */
  __I  uint32_t PIXENGCFG_CONSTFRAME4_STATUS;      /**< Status information for pixel engine configuration of constframe4, offset: 0x9C8 */
       uint8_t RESERVED_19[20];
  __I  uint32_t PIXENGCFG_EXTDST4_LOCKUNLOCK;      /**< Register to change the protection status of this address block., offset: 0x9E0 */
  __I  uint32_t PIXENGCFG_EXTDST4_LOCKSTATUS;      /**< Protection status of this address block., offset: 0x9E4 */
  __IO uint32_t PIXENGCFG_EXTDST4_STATIC;          /**< Static pixel engine configuration for extdst4, offset: 0x9E8 */
  __IO uint32_t PIXENGCFG_EXTDST4_DYNAMIC;         /**< Dynamic pixel engine configuration for extdst4, offset: 0x9EC */
  __I  uint32_t PIXENGCFG_EXTDST4_REQUEST;         /**< ShadowLoadRequest register for endpoint extdst4, offset: 0x9F0 */
  __O  uint32_t PIXENGCFG_EXTDST4_TRIGGER;         /**< Trigger bits for pixel engine configuration of extdst4, offset: 0x9F4 */
  __I  uint32_t PIXENGCFG_EXTDST4_STATUS;          /**< Status information for pixel engine configuration of extdst4, offset: 0x9F8 */
       uint8_t RESERVED_20[4];
  __I  uint32_t PIXENGCFG_CONSTFRAME1_LOCKUNLOCK;  /**< Register to change the protection status of this address block., offset: 0xA00 */
  __I  uint32_t PIXENGCFG_CONSTFRAME1_LOCKSTATUS;  /**< Protection status of this address block., offset: 0xA04 */
  __I  uint32_t PIXENGCFG_CONSTFRAME1_STATUS;      /**< Status information for pixel engine configuration of constframe1, offset: 0xA08 */
       uint8_t RESERVED_21[20];
  __I  uint32_t PIXENGCFG_EXTDST1_LOCKUNLOCK;      /**< Register to change the protection status of this address block., offset: 0xA20 */
  __I  uint32_t PIXENGCFG_EXTDST1_LOCKSTATUS;      /**< Protection status of this address block., offset: 0xA24 */
  __IO uint32_t PIXENGCFG_EXTDST1_STATIC;          /**< Static pixel engine configuration for extdst1, offset: 0xA28 */
  __IO uint32_t PIXENGCFG_EXTDST1_DYNAMIC;         /**< Dynamic pixel engine configuration for extdst1, offset: 0xA2C */
  __I  uint32_t PIXENGCFG_EXTDST1_REQUEST;         /**< ShadowLoadRequest register for endpoint extdst1, offset: 0xA30 */
  __O  uint32_t PIXENGCFG_EXTDST1_TRIGGER;         /**< Trigger bits for pixel engine configuration of extdst1, offset: 0xA34 */
  __I  uint32_t PIXENGCFG_EXTDST1_STATUS;          /**< Status information for pixel engine configuration of extdst1, offset: 0xA38 */
       uint8_t RESERVED_22[4];
  __I  uint32_t PIXENGCFG_CONSTFRAME5_LOCKUNLOCK;  /**< Register to change the protection status of this address block., offset: 0xA40 */
  __I  uint32_t PIXENGCFG_CONSTFRAME5_LOCKSTATUS;  /**< Protection status of this address block., offset: 0xA44 */
  __I  uint32_t PIXENGCFG_CONSTFRAME5_STATUS;      /**< Status information for pixel engine configuration of constframe5, offset: 0xA48 */
       uint8_t RESERVED_23[20];
  __I  uint32_t PIXENGCFG_EXTDST5_LOCKUNLOCK;      /**< Register to change the protection status of this address block., offset: 0xA60 */
  __I  uint32_t PIXENGCFG_EXTDST5_LOCKSTATUS;      /**< Protection status of this address block., offset: 0xA64 */
  __IO uint32_t PIXENGCFG_EXTDST5_STATIC;          /**< Static pixel engine configuration for extdst5, offset: 0xA68 */
  __IO uint32_t PIXENGCFG_EXTDST5_DYNAMIC;         /**< Dynamic pixel engine configuration for extdst5, offset: 0xA6C */
  __I  uint32_t PIXENGCFG_EXTDST5_REQUEST;         /**< ShadowLoadRequest register for endpoint extdst5, offset: 0xA70 */
  __O  uint32_t PIXENGCFG_EXTDST5_TRIGGER;         /**< Trigger bits for pixel engine configuration of extdst5, offset: 0xA74 */
  __I  uint32_t PIXENGCFG_EXTDST5_STATUS;          /**< Status information for pixel engine configuration of extdst5, offset: 0xA78 */
       uint8_t RESERVED_24[4];
  __I  uint32_t PIXENGCFG_EXTSRC4_LOCKUNLOCK;      /**< Register to change the protection status of this address block., offset: 0xA80 */
  __I  uint32_t PIXENGCFG_EXTSRC4_LOCKSTATUS;      /**< Protection status of this address block., offset: 0xA84 */
  __I  uint32_t PIXENGCFG_EXTSRC4_STATUS;          /**< Status information for pixel engine configuration of extsrc4, offset: 0xA88 */
       uint8_t RESERVED_25[20];
  __I  uint32_t PIXENGCFG_STORE4_LOCKUNLOCK;       /**< Register to change the protection status of this address block., offset: 0xAA0 */
  __I  uint32_t PIXENGCFG_STORE4_LOCKSTATUS;       /**< Protection status of this address block., offset: 0xAA4 */
  __IO uint32_t PIXENGCFG_STORE4_STATIC;           /**< Static pixel engine configuration for store4, offset: 0xAA8 */
  __IO uint32_t PIXENGCFG_STORE4_DYNAMIC;          /**< Dynamic pixel engine configuration for store4, offset: 0xAAC */
  __I  uint32_t PIXENGCFG_STORE4_REQUEST;          /**< ShadowLoadRequest register for endpoint store4, offset: 0xAB0 */
  __O  uint32_t PIXENGCFG_STORE4_TRIGGER;          /**< Trigger bits for pixel engine configuration of store4, offset: 0xAB4 */
  __I  uint32_t PIXENGCFG_STORE4_STATUS;           /**< Status information for pixel engine configuration of store4, offset: 0xAB8 */
       uint8_t RESERVED_26[4];
  __I  uint32_t PIXENGCFG_EXTSRC5_LOCKUNLOCK;      /**< Register to change the protection status of this address block., offset: 0xAC0 */
  __I  uint32_t PIXENGCFG_EXTSRC5_LOCKSTATUS;      /**< Protection status of this address block., offset: 0xAC4 */
  __I  uint32_t PIXENGCFG_EXTSRC5_STATUS;          /**< Status information for pixel engine configuration of extsrc5, offset: 0xAC8 */
       uint8_t RESERVED_27[20];
  __I  uint32_t PIXENGCFG_STORE5_LOCKUNLOCK;       /**< Register to change the protection status of this address block., offset: 0xAE0 */
  __I  uint32_t PIXENGCFG_STORE5_LOCKSTATUS;       /**< Protection status of this address block., offset: 0xAE4 */
  __IO uint32_t PIXENGCFG_STORE5_STATIC;           /**< Static pixel engine configuration for store5, offset: 0xAE8 */
  __IO uint32_t PIXENGCFG_STORE5_DYNAMIC;          /**< Dynamic pixel engine configuration for store5, offset: 0xAEC */
  __I  uint32_t PIXENGCFG_STORE5_REQUEST;          /**< ShadowLoadRequest register for endpoint store5, offset: 0xAF0 */
  __O  uint32_t PIXENGCFG_STORE5_TRIGGER;          /**< Trigger bits for pixel engine configuration of store5, offset: 0xAF4 */
  __I  uint32_t PIXENGCFG_STORE5_STATUS;           /**< Status information for pixel engine configuration of store5, offset: 0xAF8 */
       uint8_t RESERVED_28[4];
  __I  uint32_t PIXENGCFG_FETCHDECODE2_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB00 */
  __I  uint32_t PIXENGCFG_FETCHDECODE2_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB04 */
  __IO uint32_t PIXENGCFG_FETCHDECODE2_DYNAMIC;    /**< Dynamic pixel engine configuration for fetchdecode2, offset: 0xB08 */
  __I  uint32_t PIXENGCFG_FETCHDECODE2_STATUS;     /**< Status information for pixel engine configuration of fetchdecode2, offset: 0xB0C */
       uint8_t RESERVED_29[16];
  __I  uint32_t PIXENGCFG_FETCHDECODE3_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB20 */
  __I  uint32_t PIXENGCFG_FETCHDECODE3_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB24 */
  __IO uint32_t PIXENGCFG_FETCHDECODE3_DYNAMIC;    /**< Dynamic pixel engine configuration for fetchdecode3, offset: 0xB28 */
  __I  uint32_t PIXENGCFG_FETCHDECODE3_STATUS;     /**< Status information for pixel engine configuration of fetchdecode3, offset: 0xB2C */
       uint8_t RESERVED_30[16];
  __I  uint32_t PIXENGCFG_FETCHWARP2_LOCKUNLOCK;   /**< Register to change the protection status of this address block., offset: 0xB40 */
  __I  uint32_t PIXENGCFG_FETCHWARP2_LOCKSTATUS;   /**< Protection status of this address block., offset: 0xB44 */
  __IO uint32_t PIXENGCFG_FETCHWARP2_DYNAMIC;      /**< Dynamic pixel engine configuration for fetchwarp2, offset: 0xB48 */
  __I  uint32_t PIXENGCFG_FETCHWARP2_STATUS;       /**< Status information for pixel engine configuration of fetchwarp2, offset: 0xB4C */
  __I  uint32_t PIXENGCFG_FETCHECO2_LOCKUNLOCK;    /**< Register to change the protection status of this address block., offset: 0xB50 */
  __I  uint32_t PIXENGCFG_FETCHECO2_LOCKSTATUS;    /**< Protection status of this address block., offset: 0xB54 */
  __I  uint32_t PIXENGCFG_FETCHECO2_STATUS;        /**< Status information for pixel engine configuration of fetcheco2, offset: 0xB58 */
       uint8_t RESERVED_31[4];
  __I  uint32_t PIXENGCFG_FETCHDECODE0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB60 */
  __I  uint32_t PIXENGCFG_FETCHDECODE0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB64 */
  __IO uint32_t PIXENGCFG_FETCHDECODE0_DYNAMIC;    /**< Dynamic pixel engine configuration for fetchdecode0, offset: 0xB68 */
  __I  uint32_t PIXENGCFG_FETCHDECODE0_STATUS;     /**< Status information for pixel engine configuration of fetchdecode0, offset: 0xB6C */
  __I  uint32_t PIXENGCFG_FETCHECO0_LOCKUNLOCK;    /**< Register to change the protection status of this address block., offset: 0xB70 */
  __I  uint32_t PIXENGCFG_FETCHECO0_LOCKSTATUS;    /**< Protection status of this address block., offset: 0xB74 */
  __I  uint32_t PIXENGCFG_FETCHECO0_STATUS;        /**< Status information for pixel engine configuration of fetcheco0, offset: 0xB78 */
       uint8_t RESERVED_32[4];
  __I  uint32_t PIXENGCFG_FETCHDECODE1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB80 */
  __I  uint32_t PIXENGCFG_FETCHDECODE1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB84 */
  __IO uint32_t PIXENGCFG_FETCHDECODE1_DYNAMIC;    /**< Dynamic pixel engine configuration for fetchdecode1, offset: 0xB88 */
  __I  uint32_t PIXENGCFG_FETCHDECODE1_STATUS;     /**< Status information for pixel engine configuration of fetchdecode1, offset: 0xB8C */
  __I  uint32_t PIXENGCFG_FETCHECO1_LOCKUNLOCK;    /**< Register to change the protection status of this address block., offset: 0xB90 */
  __I  uint32_t PIXENGCFG_FETCHECO1_LOCKSTATUS;    /**< Protection status of this address block., offset: 0xB94 */
  __I  uint32_t PIXENGCFG_FETCHECO1_STATUS;        /**< Status information for pixel engine configuration of fetcheco1, offset: 0xB98 */
       uint8_t RESERVED_33[4];
  __I  uint32_t PIXENGCFG_FETCHLAYER0_LOCKUNLOCK;  /**< Register to change the protection status of this address block., offset: 0xBA0 */
  __I  uint32_t PIXENGCFG_FETCHLAYER0_LOCKSTATUS;  /**< Protection status of this address block., offset: 0xBA4 */
  __I  uint32_t PIXENGCFG_FETCHLAYER0_STATUS;      /**< Status information for pixel engine configuration of fetchlayer0, offset: 0xBA8 */
       uint8_t RESERVED_34[4];
  __I  uint32_t PIXENGCFG_FETCHLAYER1_LOCKUNLOCK;  /**< Register to change the protection status of this address block., offset: 0xBB0 */
  __I  uint32_t PIXENGCFG_FETCHLAYER1_LOCKSTATUS;  /**< Protection status of this address block., offset: 0xBB4 */
  __I  uint32_t PIXENGCFG_FETCHLAYER1_STATUS;      /**< Status information for pixel engine configuration of fetchlayer1, offset: 0xBB8 */
       uint8_t RESERVED_35[4];
  __I  uint32_t PIXENGCFG_GAMMACOR4_LOCKUNLOCK;    /**< Register to change the protection status of this address block., offset: 0xBC0 */
  __I  uint32_t PIXENGCFG_GAMMACOR4_LOCKSTATUS;    /**< Protection status of this address block., offset: 0xBC4 */
  __IO uint32_t PIXENGCFG_GAMMACOR4_DYNAMIC;       /**< Dynamic pixel engine configuration for gammacor4, offset: 0xBC8 */
  __I  uint32_t PIXENGCFG_GAMMACOR4_STATUS;        /**< Status information for pixel engine configuration of gammacor4, offset: 0xBCC */
       uint8_t RESERVED_36[16];
  __I  uint32_t PIXENGCFG_MATRIX4_LOCKUNLOCK;      /**< Register to change the protection status of this address block., offset: 0xBE0 */
  __I  uint32_t PIXENGCFG_MATRIX4_LOCKSTATUS;      /**< Protection status of this address block., offset: 0xBE4 */
  __IO uint32_t PIXENGCFG_MATRIX4_DYNAMIC;         /**< Dynamic pixel engine configuration for matrix4, offset: 0xBE8 */
  __I  uint32_t PIXENGCFG_MATRIX4_STATUS;          /**< Status information for pixel engine configuration of matrix4, offset: 0xBEC */
       uint8_t RESERVED_37[16];
  __I  uint32_t PIXENGCFG_HSCALER4_LOCKUNLOCK;     /**< Register to change the protection status of this address block., offset: 0xC00 */
  __I  uint32_t PIXENGCFG_HSCALER4_LOCKSTATUS;     /**< Protection status of this address block., offset: 0xC04 */
  __IO uint32_t PIXENGCFG_HSCALER4_DYNAMIC;        /**< Dynamic pixel engine configuration for hscaler4, offset: 0xC08 */
  __I  uint32_t PIXENGCFG_HSCALER4_STATUS;         /**< Status information for pixel engine configuration of hscaler4, offset: 0xC0C */
       uint8_t RESERVED_38[16];
  __I  uint32_t PIXENGCFG_VSCALER4_LOCKUNLOCK;     /**< Register to change the protection status of this address block., offset: 0xC20 */
  __I  uint32_t PIXENGCFG_VSCALER4_LOCKSTATUS;     /**< Protection status of this address block., offset: 0xC24 */
  __IO uint32_t PIXENGCFG_VSCALER4_DYNAMIC;        /**< Dynamic pixel engine configuration for vscaler4, offset: 0xC28 */
  __I  uint32_t PIXENGCFG_VSCALER4_STATUS;         /**< Status information for pixel engine configuration of vscaler4, offset: 0xC2C */
       uint8_t RESERVED_39[16];
  __I  uint32_t PIXENGCFG_HISTOGRAM4_LOCKUNLOCK;   /**< Register to change the protection status of this address block., offset: 0xC40 */
  __I  uint32_t PIXENGCFG_HISTOGRAM4_LOCKSTATUS;   /**< Protection status of this address block., offset: 0xC44 */
  __IO uint32_t PIXENGCFG_HISTOGRAM4_DYNAMIC;      /**< Dynamic pixel engine configuration for histogram4, offset: 0xC48 */
  __I  uint32_t PIXENGCFG_HISTOGRAM4_STATUS;       /**< Status information for pixel engine configuration of histogram4, offset: 0xC4C */
       uint8_t RESERVED_40[16];
  __I  uint32_t PIXENGCFG_GAMMACOR5_LOCKUNLOCK;    /**< Register to change the protection status of this address block., offset: 0xC60 */
  __I  uint32_t PIXENGCFG_GAMMACOR5_LOCKSTATUS;    /**< Protection status of this address block., offset: 0xC64 */
  __IO uint32_t PIXENGCFG_GAMMACOR5_DYNAMIC;       /**< Dynamic pixel engine configuration for gammacor5, offset: 0xC68 */
  __I  uint32_t PIXENGCFG_GAMMACOR5_STATUS;        /**< Status information for pixel engine configuration of gammacor5, offset: 0xC6C */
       uint8_t RESERVED_41[16];
  __I  uint32_t PIXENGCFG_MATRIX5_LOCKUNLOCK;      /**< Register to change the protection status of this address block., offset: 0xC80 */
  __I  uint32_t PIXENGCFG_MATRIX5_LOCKSTATUS;      /**< Protection status of this address block., offset: 0xC84 */
  __IO uint32_t PIXENGCFG_MATRIX5_DYNAMIC;         /**< Dynamic pixel engine configuration for matrix5, offset: 0xC88 */
  __I  uint32_t PIXENGCFG_MATRIX5_STATUS;          /**< Status information for pixel engine configuration of matrix5, offset: 0xC8C */
       uint8_t RESERVED_42[16];
  __I  uint32_t PIXENGCFG_HSCALER5_LOCKUNLOCK;     /**< Register to change the protection status of this address block., offset: 0xCA0 */
  __I  uint32_t PIXENGCFG_HSCALER5_LOCKSTATUS;     /**< Protection status of this address block., offset: 0xCA4 */
  __IO uint32_t PIXENGCFG_HSCALER5_DYNAMIC;        /**< Dynamic pixel engine configuration for hscaler5, offset: 0xCA8 */
  __I  uint32_t PIXENGCFG_HSCALER5_STATUS;         /**< Status information for pixel engine configuration of hscaler5, offset: 0xCAC */
       uint8_t RESERVED_43[16];
  __I  uint32_t PIXENGCFG_VSCALER5_LOCKUNLOCK;     /**< Register to change the protection status of this address block., offset: 0xCC0 */
  __I  uint32_t PIXENGCFG_VSCALER5_LOCKSTATUS;     /**< Protection status of this address block., offset: 0xCC4 */
  __IO uint32_t PIXENGCFG_VSCALER5_DYNAMIC;        /**< Dynamic pixel engine configuration for vscaler5, offset: 0xCC8 */
  __I  uint32_t PIXENGCFG_VSCALER5_STATUS;         /**< Status information for pixel engine configuration of vscaler5, offset: 0xCCC */
       uint8_t RESERVED_44[16];
  __I  uint32_t PIXENGCFG_HISTOGRAM5_LOCKUNLOCK;   /**< Register to change the protection status of this address block., offset: 0xCE0 */
  __I  uint32_t PIXENGCFG_HISTOGRAM5_LOCKSTATUS;   /**< Protection status of this address block., offset: 0xCE4 */
  __IO uint32_t PIXENGCFG_HISTOGRAM5_DYNAMIC;      /**< Dynamic pixel engine configuration for histogram5, offset: 0xCE8 */
  __I  uint32_t PIXENGCFG_HISTOGRAM5_STATUS;       /**< Status information for pixel engine configuration of histogram5, offset: 0xCEC */
       uint8_t RESERVED_45[16];
  __I  uint32_t PIXENGCFG_LAYERBLEND0_LOCKUNLOCK;  /**< Register to change the protection status of this address block., offset: 0xD00 */
  __I  uint32_t PIXENGCFG_LAYERBLEND0_LOCKSTATUS;  /**< Protection status of this address block., offset: 0xD04 */
  __IO uint32_t PIXENGCFG_LAYERBLEND0_DYNAMIC;     /**< Dynamic pixel engine configuration for layerblend0, offset: 0xD08 */
  __I  uint32_t PIXENGCFG_LAYERBLEND0_STATUS;      /**< Status information for pixel engine configuration of layerblend0, offset: 0xD0C */
       uint8_t RESERVED_46[16];
  __I  uint32_t PIXENGCFG_LAYERBLEND1_LOCKUNLOCK;  /**< Register to change the protection status of this address block., offset: 0xD20 */
  __I  uint32_t PIXENGCFG_LAYERBLEND1_LOCKSTATUS;  /**< Protection status of this address block., offset: 0xD24 */
  __IO uint32_t PIXENGCFG_LAYERBLEND1_DYNAMIC;     /**< Dynamic pixel engine configuration for layerblend1, offset: 0xD28 */
  __I  uint32_t PIXENGCFG_LAYERBLEND1_STATUS;      /**< Status information for pixel engine configuration of layerblend1, offset: 0xD2C */
       uint8_t RESERVED_47[16];
  __I  uint32_t PIXENGCFG_LAYERBLEND2_LOCKUNLOCK;  /**< Register to change the protection status of this address block., offset: 0xD40 */
  __I  uint32_t PIXENGCFG_LAYERBLEND2_LOCKSTATUS;  /**< Protection status of this address block., offset: 0xD44 */
  __IO uint32_t PIXENGCFG_LAYERBLEND2_DYNAMIC;     /**< Dynamic pixel engine configuration for layerblend2, offset: 0xD48 */
  __I  uint32_t PIXENGCFG_LAYERBLEND2_STATUS;      /**< Status information for pixel engine configuration of layerblend2, offset: 0xD4C */
       uint8_t RESERVED_48[16];
  __I  uint32_t PIXENGCFG_LAYERBLEND3_LOCKUNLOCK;  /**< Register to change the protection status of this address block., offset: 0xD60 */
  __I  uint32_t PIXENGCFG_LAYERBLEND3_LOCKSTATUS;  /**< Protection status of this address block., offset: 0xD64 */
  __IO uint32_t PIXENGCFG_LAYERBLEND3_DYNAMIC;     /**< Dynamic pixel engine configuration for layerblend3, offset: 0xD68 */
  __I  uint32_t PIXENGCFG_LAYERBLEND3_STATUS;      /**< Status information for pixel engine configuration of layerblend3, offset: 0xD6C */
       uint8_t RESERVED_49[16];
  __I  uint32_t PIXENGCFG_LAYERBLEND4_LOCKUNLOCK;  /**< Register to change the protection status of this address block., offset: 0xD80 */
  __I  uint32_t PIXENGCFG_LAYERBLEND4_LOCKSTATUS;  /**< Protection status of this address block., offset: 0xD84 */
  __IO uint32_t PIXENGCFG_LAYERBLEND4_DYNAMIC;     /**< Dynamic pixel engine configuration for layerblend4, offset: 0xD88 */
  __I  uint32_t PIXENGCFG_LAYERBLEND4_STATUS;      /**< Status information for pixel engine configuration of layerblend4, offset: 0xD8C */
       uint8_t RESERVED_50[16];
  __I  uint32_t PIXENGCFG_LAYERBLEND5_LOCKUNLOCK;  /**< Register to change the protection status of this address block., offset: 0xDA0 */
  __I  uint32_t PIXENGCFG_LAYERBLEND5_LOCKSTATUS;  /**< Protection status of this address block., offset: 0xDA4 */
  __IO uint32_t PIXENGCFG_LAYERBLEND5_DYNAMIC;     /**< Dynamic pixel engine configuration for layerblend5, offset: 0xDA8 */
  __I  uint32_t PIXENGCFG_LAYERBLEND5_STATUS;      /**< Status information for pixel engine configuration of layerblend5, offset: 0xDAC */
       uint8_t RESERVED_51[16];
  __I  uint32_t PIXENGCFG_LAYERBLEND6_LOCKUNLOCK;  /**< Register to change the protection status of this address block., offset: 0xDC0 */
  __I  uint32_t PIXENGCFG_LAYERBLEND6_LOCKSTATUS;  /**< Protection status of this address block., offset: 0xDC4 */
  __IO uint32_t PIXENGCFG_LAYERBLEND6_DYNAMIC;     /**< Dynamic pixel engine configuration for layerblend6, offset: 0xDC8 */
  __I  uint32_t PIXENGCFG_LAYERBLEND6_STATUS;      /**< Status information for pixel engine configuration of layerblend6, offset: 0xDCC */
  __I  uint32_t PIXENGCFG_EXTSRC0_LOCKUNLOCK;      /**< Register to change the protection status of this address block., offset: 0xDD0 */
  __I  uint32_t PIXENGCFG_EXTSRC0_LOCKSTATUS;      /**< Protection status of this address block., offset: 0xDD4 */
  __I  uint32_t PIXENGCFG_EXTSRC0_STATUS;          /**< Status information for pixel engine configuration of extsrc0, offset: 0xDD8 */
       uint8_t RESERVED_52[4];
  __I  uint32_t PIXENGCFG_EXTSRC1_LOCKUNLOCK;      /**< Register to change the protection status of this address block., offset: 0xDE0 */
  __I  uint32_t PIXENGCFG_EXTSRC1_LOCKSTATUS;      /**< Protection status of this address block., offset: 0xDE4 */
  __I  uint32_t PIXENGCFG_EXTSRC1_STATUS;          /**< Status information for pixel engine configuration of extsrc1, offset: 0xDE8 */
       uint8_t RESERVED_53[532];
  __I  uint32_t FETCHDECODE9_LOCKUNLOCK;           /**< Register to change the protection status of this address block., offset: 0x1000 */
  __I  uint32_t FETCHDECODE9_LOCKSTATUS;           /**< Protection status of this address block., offset: 0x1004 */
  __IO uint32_t FETCHDECODE9_STATICCONTROL;        /**< Common static control options., offset: 0x1008 */
  __IO uint32_t FETCHDECODE9_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x100C */
  __IO uint32_t FETCHDECODE9_RINGBUFSTARTADDR0;    /**< Ring buffer setup for layer 0., offset: 0x1010 */
  __IO uint32_t FETCHDECODE9_RINGBUFWRAPADDR0;     /**< Ring buffer setup for layer 0., offset: 0x1014 */
  __IO uint32_t FETCHDECODE9_FRAMEPROPERTIES0;     /**< Frame property setup for layer 0., offset: 0x1018 */
  __IO uint32_t FETCHDECODE9_BASEADDRESS0;         /**< Source buffer base address of layer 0., offset: 0x101C */
  __IO uint32_t FETCHDECODE9_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x1020 */
  __IO uint32_t FETCHDECODE9_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x1024 */
  __IO uint32_t FETCHDECODE9_COLORCOMPONENTBITS0;  /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x1028 */
  __IO uint32_t FETCHDECODE9_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x102C */
  __IO uint32_t FETCHDECODE9_LAYEROFFSET0;         /**< Position of layer 0 within the destination frame., offset: 0x1030 */
  __IO uint32_t FETCHDECODE9_CLIPWINDOWOFFSET0;    /**< Clip window position for layer 0., offset: 0x1034 */
  __IO uint32_t FETCHDECODE9_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x1038 */
  __IO uint32_t FETCHDECODE9_CONSTANTCOLOR0;       /**< Constant color for layer 0., offset: 0x103C */
  __IO uint32_t FETCHDECODE9_LAYERPROPERTY0;       /**< Common properties of layer 0., offset: 0x1040 */
  __IO uint32_t FETCHDECODE9_FRAMEDIMENSIONS;      /**< Output frame dimension., offset: 0x1044 */
  __IO uint32_t FETCHDECODE9_FRAMERESAMPLING;      /**< Resampling options for output frame., offset: 0x1048 */
  __IO uint32_t FETCHDECODE9_DECODECONTROL;        /**< Control options for RLAD decompression., offset: 0x104C */
  __IO uint32_t FETCHDECODE9_SOURCEBUFFERLENGTH;   /**< Source buffer length for compressed data., offset: 0x1050 */
  __IO uint32_t FETCHDECODE9_CONTROL;              /**< Shared common control settings for all layers., offset: 0x1054 */
  __O  uint32_t FETCHDECODE9_CONTROLTRIGGER;       /**< Shadow load trigger., offset: 0x1058 */
  __O  uint32_t FETCHDECODE9_START;                /**< Frame start trigger., offset: 0x105C */
  __I  uint32_t FETCHDECODE9_FETCHTYPE;            /**< Fetch unit type., offset: 0x1060 */
  __IO uint32_t FETCHDECODE9_DECODERSTATUS;        /**< Status information of the RLAD decoder., offset: 0x1064 */
  __I  uint32_t FETCHDECODE9_READADDRESS0;         /**< Ring buffer synchronization for layer 0., offset: 0x1068 */
  __I  uint32_t FETCHDECODE9_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x106C */
  __IO uint32_t FETCHDECODE9_STATUS;               /**< Status informations., offset: 0x1070 */
  __I  uint32_t FETCHDECODE9_HIDDENSTATUS;         /**< Hidden status informations., offset: 0x1074 */
       uint8_t RESERVED_54[904];
  __IO uint32_t FETCHDECODE9_COLORPALETTE;         /**< Color palette look up table., offset: 0x1400 */
       uint8_t RESERVED_55[1020];
  __I  uint32_t FETCHPERSP9_LOCKUNLOCK;            /**< Register to change the protection status of this address block., offset: 0x1800 */
  __I  uint32_t FETCHPERSP9_LOCKSTATUS;            /**< Protection status of this address block., offset: 0x1804 */
  __IO uint32_t FETCHPERSP9_STATICCONTROL;         /**< Common static control options., offset: 0x1808 */
  __IO uint32_t FETCHPERSP9_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x180C */
  __IO uint32_t FETCHPERSP9_BASEADDRESS0;          /**< Source buffer base address of layer 0., offset: 0x1810 */
  __IO uint32_t FETCHPERSP9_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x1814 */
  __IO uint32_t FETCHPERSP9_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x1818 */
  __IO uint32_t FETCHPERSP9_COLORCOMPONENTBITS0;   /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x181C */
  __IO uint32_t FETCHPERSP9_COLORCOMPONENTSHIFT0;  /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x1820 */
  __IO uint32_t FETCHPERSP9_LAYEROFFSET0;          /**< Position of layer 0 within the destination frame., offset: 0x1824 */
  __IO uint32_t FETCHPERSP9_CLIPWINDOWOFFSET0;     /**< Clip window position for layer 0., offset: 0x1828 */
  __IO uint32_t FETCHPERSP9_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x182C */
  __IO uint32_t FETCHPERSP9_CONSTANTCOLOR0;        /**< Constant color for layer 0., offset: 0x1830 */
  __IO uint32_t FETCHPERSP9_LAYERPROPERTY0;        /**< Common properties of layer 0., offset: 0x1834 */
  __IO uint32_t FETCHPERSP9_FRAMEDIMENSIONS;       /**< Output frame dimension., offset: 0x1838 */
  __IO uint32_t FETCHPERSP9_FRAMERESAMPLING;       /**< Resampling options for output frame., offset: 0x183C */
  __IO uint32_t FETCHPERSP9_WARPCONTROL;           /**< Warping control options., offset: 0x1840 */
  __IO uint32_t FETCHPERSP9_PERSPSTARTX;           /**< Start value X for affine/perspective warping., offset: 0x1844 */
  __IO uint32_t FETCHPERSP9_PERSPSTARTY;           /**< Start value Y for affine/perspective warping., offset: 0x1848 */
  __IO uint32_t FETCHPERSP9_PERSPSTARTW;           /**< Start value W for perspective warping., offset: 0x184C */
  __IO uint32_t FETCHPERSP9_PERSPDELTAXX;          /**< DeltaXX increment for affine/perspective warping., offset: 0x1850 */
  __IO uint32_t FETCHPERSP9_PERSPDELTAXY;          /**< DeltaXY increment for affine/perspective warping., offset: 0x1854 */
  __IO uint32_t FETCHPERSP9_PERSPDELTAXW;          /**< DeltaWX increment for perspective warping., offset: 0x1858 */
  __IO uint32_t FETCHPERSP9_PERSPDELTAYX;          /**< DeltaXX increment for affine/perspective warping., offset: 0x185C */
  __IO uint32_t FETCHPERSP9_PERSPDELTAYY;          /**< DeltaYY increment for affine/perspective warping., offset: 0x1860 */
  __IO uint32_t FETCHPERSP9_PERSPDELTAYW;          /**< DeltaWY increment for perspective warping., offset: 0x1864 */
  __IO uint32_t FETCHPERSP9_ARBSTARTX;             /**< Start value X for arbitrary warping., offset: 0x1868 */
  __IO uint32_t FETCHPERSP9_ARBSTARTY;             /**< Start value Y for arbitrary warping., offset: 0x186C */
  __IO uint32_t FETCHPERSP9_ARBDELTA;              /**< Start values for delta incrementation of arbitrary warping., offset: 0x1870 */
  __IO uint32_t FETCHPERSP9_FIRPOSITIONS;          /**< FIR sequence control register., offset: 0x1874 */
  __IO uint32_t FETCHPERSP9_FIRCOEFFICIENTS;       /**< FIR coefficients register., offset: 0x1878 */
  __IO uint32_t FETCHPERSP9_CONTROL;               /**< Shared common control settings for all layers., offset: 0x187C */
  __O  uint32_t FETCHPERSP9_CONTROLTRIGGER;        /**< Shadow load trigger., offset: 0x1880 */
  __O  uint32_t FETCHPERSP9_START;                 /**< Frame start trigger., offset: 0x1884 */
  __I  uint32_t FETCHPERSP9_FETCHTYPE;             /**< Fetch unit type., offset: 0x1888 */
  __I  uint32_t FETCHPERSP9_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x188C */
  __I  uint32_t FETCHPERSP9_HIDDENSTATUS;          /**< Hidden status informations., offset: 0x1890 */
       uint8_t RESERVED_56[876];
  __I  uint32_t FETCHECO9_LOCKUNLOCK;              /**< Register to change the protection status of this address block., offset: 0x1C00 */
  __I  uint32_t FETCHECO9_LOCKSTATUS;              /**< Protection status of this address block., offset: 0x1C04 */
  __IO uint32_t FETCHECO9_STATICCONTROL;           /**< Common static control options., offset: 0x1C08 */
  __IO uint32_t FETCHECO9_BURSTBUFFERMANAGEMENT;   /**< AXI interface buffer management register, offset: 0x1C0C */
  __IO uint32_t FETCHECO9_BASEADDRESS0;            /**< Source buffer base address of layer 0., offset: 0x1C10 */
  __IO uint32_t FETCHECO9_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x1C14 */
  __IO uint32_t FETCHECO9_SOURCEBUFFERDIMENSION0;  /**< Source buffer dimension of layer 0., offset: 0x1C18 */
  __IO uint32_t FETCHECO9_COLORCOMPONENTBITS0;     /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x1C1C */
  __IO uint32_t FETCHECO9_COLORCOMPONENTSHIFT0;    /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x1C20 */
  __IO uint32_t FETCHECO9_LAYEROFFSET0;            /**< Position of layer 0 within the destination frame., offset: 0x1C24 */
  __IO uint32_t FETCHECO9_CLIPWINDOWOFFSET0;       /**< Clip window position for layer 0., offset: 0x1C28 */
  __IO uint32_t FETCHECO9_CLIPWINDOWDIMENSIONS0;   /**< Clip window size for layer 0., offset: 0x1C2C */
  __IO uint32_t FETCHECO9_CONSTANTCOLOR0;          /**< Constant color for layer 0., offset: 0x1C30 */
  __IO uint32_t FETCHECO9_LAYERPROPERTY0;          /**< Common properties of layer 0., offset: 0x1C34 */
  __IO uint32_t FETCHECO9_FRAMEDIMENSIONS;         /**< Output frame dimension., offset: 0x1C38 */
  __IO uint32_t FETCHECO9_FRAMERESAMPLING;         /**< Resampling options for output frame., offset: 0x1C3C */
  __IO uint32_t FETCHECO9_CONTROL;                 /**< Shared common control settings for all layers., offset: 0x1C40 */
  __O  uint32_t FETCHECO9_CONTROLTRIGGER;          /**< Shadow load trigger., offset: 0x1C44 */
  __O  uint32_t FETCHECO9_START;                   /**< Frame start trigger., offset: 0x1C48 */
  __I  uint32_t FETCHECO9_FETCHTYPE;               /**< Fetch unit type., offset: 0x1C4C */
  __I  uint32_t FETCHECO9_BURSTBUFFERPROPERTIES;   /**< Burst buffer properties., offset: 0x1C50 */
  __I  uint32_t FETCHECO9_HIDDENSTATUS;            /**< Hidden status informations., offset: 0x1C54 */
       uint8_t RESERVED_57[936];
  __I  uint32_t ROP9_LOCKUNLOCK;                   /**< Register to change the protection status of this address block., offset: 0x2000 */
  __I  uint32_t ROP9_LOCKSTATUS;                   /**< Protection status of this address block., offset: 0x2004 */
  __IO uint32_t ROP9_STATICCONTROL;                /**< Raster Operation static control register, offset: 0x2008 */
  __IO uint32_t ROP9_CONTROL;                      /**< Raster Operation control register, offset: 0x200C */
  __IO uint32_t ROP9_RASTEROPERATIONINDICES;       /**< ROP operation indices, offset: 0x2010 */
  __I  uint32_t ROP9_PRIMCONTROLWORD;              /**< Value of last received primary control word, offset: 0x2014 */
  __I  uint32_t ROP9_SECCONTROLWORD;               /**< Value of last received secondary control word, offset: 0x2018 */
  __I  uint32_t ROP9_TERTCONTROLWORD;              /**< Value of last received tertiary control word, offset: 0x201C */
       uint8_t RESERVED_58[992];
  __I  uint32_t CLUT9_LOCKUNLOCK;                  /**< Register to change the protection status of this address block., offset: 0x2400 */
  __I  uint32_t CLUT9_LOCKSTATUS;                  /**< Protection status of this address block., offset: 0x2404 */
  __IO uint32_t CLUT9_STATICCONTROL;               /**< CLUT static control register, offset: 0x2408 */
  __IO uint32_t CLUT9_UNSHADOWEDCONTROL;           /**< CLUT unshadowed control register, offset: 0x240C */
  __IO uint32_t CLUT9_CONTROL;                     /**< CLUT control register, offset: 0x2410 */
  __IO uint32_t CLUT9_STATUS;                      /**< CLUT status register, offset: 0x2414 */
  __I  uint32_t CLUT9_LASTCONTROLWORD;             /**< Value of last received control word, for debugging, offset: 0x2418 */
       uint8_t RESERVED_59[996];
  __IO uint32_t CLUT9_LUT;                         /**< Look Up Table, offset: 0x2800 */
       uint8_t RESERVED_60[1020];
  __I  uint32_t MATRIX9_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0x2C00 */
  __I  uint32_t MATRIX9_LOCKSTATUS;                /**< Protection status of this address block., offset: 0x2C04 */
  __IO uint32_t MATRIX9_STATICCONTROL;             /**< Color Matrix static control register, offset: 0x2C08 */
  __IO uint32_t MATRIX9_CONTROL;                   /**< Color Matrix control register, offset: 0x2C0C */
  __IO uint32_t MATRIX9_RED0;                      /**< Matrix values for calculation of the red output value., offset: 0x2C10 */
  __IO uint32_t MATRIX9_RED1;                      /**< Matrix values for calculation of the red output value., offset: 0x2C14 */
  __IO uint32_t MATRIX9_GREEN0;                    /**< Matrix values for calculation of the green output value., offset: 0x2C18 */
  __IO uint32_t MATRIX9_GREEN1;                    /**< Matrix values for calculation of the green output value., offset: 0x2C1C */
  __IO uint32_t MATRIX9_BLUE0;                     /**< Matrix values for calculation of the blue output value., offset: 0x2C20 */
  __IO uint32_t MATRIX9_BLUE1;                     /**< Matrix values for calculation of the blue output value., offset: 0x2C24 */
  __IO uint32_t MATRIX9_ALPHA0;                    /**< Matrix values for calculation of the alpha output value., offset: 0x2C28 */
  __IO uint32_t MATRIX9_ALPHA1;                    /**< Matrix values for calculation of the alpha output value., offset: 0x2C2C */
  __IO uint32_t MATRIX9_OFFSETVECTOR0;             /**< Offset vectors for red and green output., offset: 0x2C30 */
  __IO uint32_t MATRIX9_OFFSETVECTOR1;             /**< Offset vectors for blue and alpha output., offset: 0x2C34 */
  __I  uint32_t MATRIX9_LASTCONTROLWORD;           /**< Value of last received control word, for debugging., offset: 0x2C38 */
       uint8_t RESERVED_61[964];
  __I  uint32_t HSCALER9_LOCKUNLOCK;               /**< Register to change the protection status of this address block., offset: 0x3000 */
  __I  uint32_t HSCALER9_LOCKSTATUS;               /**< Protection status of this address block., offset: 0x3004 */
  __IO uint32_t HSCALER9_STATICCONTROL;            /**< Static control settings that must typically be setup once only., offset: 0x3008 */
  __IO uint32_t HSCALER9_SETUP1;                   /**< Phase interpolator setup., offset: 0x300C */
  __IO uint32_t HSCALER9_SETUP2;                   /**< Phase interpolator setup., offset: 0x3010 */
  __IO uint32_t HSCALER9_CONTROL;                  /**< Scaler operation control., offset: 0x3014 */
       uint8_t RESERVED_62[1000];
  __I  uint32_t VSCALER9_LOCKUNLOCK;               /**< Register to change the protection status of this address block., offset: 0x3400 */
  __I  uint32_t VSCALER9_LOCKSTATUS;               /**< Protection status of this address block., offset: 0x3404 */
  __IO uint32_t VSCALER9_STATICCONTROL;            /**< Static control settings that must typically be setup once only., offset: 0x3408 */
  __IO uint32_t VSCALER9_SETUP1;                   /**< Phase interpolator setup., offset: 0x340C */
  __IO uint32_t VSCALER9_SETUP2;                   /**< Phase interpolator setup, selected if input and output field polarity is 0., offset: 0x3410 */
  __IO uint32_t VSCALER9_SETUP3;                   /**< Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0., offset: 0x3414 */
  __IO uint32_t VSCALER9_SETUP4;                   /**< Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1., offset: 0x3418 */
  __IO uint32_t VSCALER9_SETUP5;                   /**< Phase interpolator setup, selected if input and output field polarity is 1., offset: 0x341C */
  __IO uint32_t VSCALER9_CONTROL;                  /**< Scaler operation control., offset: 0x3420 */
       uint8_t RESERVED_63[988];
  __I  uint32_t FILTER9_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0x3800 */
  __I  uint32_t FILTER9_LOCKSTATUS;                /**< Protection status of this address block., offset: 0x3804 */
  __IO uint32_t FILTER9_STATICCONTROL;             /**< Static control settings that must typically be setup once only., offset: 0x3808 */
  __IO uint32_t FILTER9_CONTROL;                   /**< Filter operation main control., offset: 0x380C */
  __IO uint32_t FILTER9_FIR_CONTROL;               /**< FIR filter operation control., offset: 0x3810 */
  __IO uint32_t FILTER9_COEFFICIENTS0;             /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3814 */
  __IO uint32_t FILTER9_COEFFICIENTS1;             /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3818 */
  __IO uint32_t FILTER9_COEFFICIENTS2;             /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x381C */
  __IO uint32_t FILTER9_COEFFICIENTS3;             /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3820 */
  __IO uint32_t FILTER9_COEFFICIENTS4;             /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3824 */
  __IO uint32_t FILTER9_COEFFICIENTS5;             /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3828 */
  __IO uint32_t FILTER9_COEFFICIENTS6;             /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x382C */
       uint8_t RESERVED_64[976];
  __I  uint32_t BLITBLEND9_LOCKUNLOCK;             /**< Register to change the protection status of this address block., offset: 0x3C00 */
  __I  uint32_t BLITBLEND9_LOCKSTATUS;             /**< Protection status of this address block., offset: 0x3C04 */
  __IO uint32_t BLITBLEND9_STATICCONTROL;          /**< BlitBlend static control register, offset: 0x3C08 */
  __IO uint32_t BLITBLEND9_CONTROL;                /**< BlitBlend control register, offset: 0x3C0C */
  __IO uint32_t BLITBLEND9_NEUTRALBORDER;          /**< Neutral border setup register, offset: 0x3C10 */
  __IO uint32_t BLITBLEND9_CONSTANTCOLOR;          /**< Constant color register, offset: 0x3C14 */
  __IO uint32_t BLITBLEND9_COLORREDBLENDFUNCTION;  /**< Open GL RGB blending factors, offset: 0x3C18 */
  __IO uint32_t BLITBLEND9_COLORGREENBLENDFUNCTION; /**< Open GL RGB blending factors, offset: 0x3C1C */
  __IO uint32_t BLITBLEND9_COLORBLUEBLENDFUNCTION; /**< Open GL RGB blending factors, offset: 0x3C20 */
  __IO uint32_t BLITBLEND9_ALPHABLENDFUNCTION;     /**< Open GL alpha blending factors, offset: 0x3C24 */
  __IO uint32_t BLITBLEND9_BLENDMODE1;             /**< Open GL and Open VG blending modes for colors red and green, offset: 0x3C28 */
  __IO uint32_t BLITBLEND9_BLENDMODE2;             /**< Open GL and Open VG blending modes for color blue and alpha, offset: 0x3C2C */
  __IO uint32_t BLITBLEND9_DIRECTSETUP;            /**< Direct Control of the BlitBlend Datapath multiplexers, do not change, offset: 0x3C30 */
  __I  uint32_t BLITBLEND9_PRIMCONTROLWORD;        /**< Value of last received primary control word, offset: 0x3C34 */
  __I  uint32_t BLITBLEND9_SECCONTROLWORD;         /**< Value of last received secondary control word, offset: 0x3C38 */
       uint8_t RESERVED_65[964];
  __I  uint32_t STORE9_LOCKUNLOCK;                 /**< Register to change the protection status of this address block., offset: 0x4000 */
  __I  uint32_t STORE9_LOCKSTATUS;                 /**< Protection status of this address block., offset: 0x4004 */
  __IO uint32_t STORE9_STATICCONTROL;              /**< Store unit static control register., offset: 0x4008 */
  __IO uint32_t STORE9_BURSTBUFFERMANAGEMENT;      /**< Burst Buffer setup register., offset: 0x400C */
  __IO uint32_t STORE9_RINGBUFSTARTADDR;           /**< Ring buffer setup for destination., offset: 0x4010 */
  __IO uint32_t STORE9_RINGBUFWRAPADDR;            /**< Ring buffer setup for destination., offset: 0x4014 */
  __IO uint32_t STORE9_BASEADDRESS;                /**< Destination buffer base address., offset: 0x4018 */
  __IO uint32_t STORE9_DESTINATIONBUFFERATTRIBUTES; /**< Destination buffer attributes., offset: 0x401C */
  __IO uint32_t STORE9_DESTINATIONBUFFERDIMENSION; /**< Destination buffer dimension., offset: 0x4020 */
  __IO uint32_t STORE9_FRAMEOFFSET;                /**< Offset between destination frame and buffer., offset: 0x4024 */
  __IO uint32_t STORE9_COLORCOMPONENTBITS;         /**< Color component size of destination buffer, offset: 0x4028 */
  __IO uint32_t STORE9_COLORCOMPONENTSHIFT;        /**< Color component offset of destination buffer., offset: 0x402C */
  __IO uint32_t STORE9_CONTROL;                    /**< Store unit dynamic control register, offset: 0x4030 */
  __IO uint32_t STORE9_ENCODECONTROL;              /**< Control options for RLAD compression., offset: 0x4034 */
  __IO uint32_t STORE9_DESTINATIONBUFFERLENGTH;    /**< Destination buffer length for compressed data., offset: 0x4038 */
  __O  uint32_t STORE9_START;                      /**< Store unit start register, offset: 0x403C */
  __IO uint32_t STORE9_ENCODERSTATUS;              /**< Status information of the RLAD encoder., offset: 0x4040 */
  __I  uint32_t STORE9_WRITEADDRESS;               /**< Ring buffer synchronization., offset: 0x4044 */
  __I  uint32_t STORE9_FRAMEPROPERTIES;            /**< Ring buffer synchronization., offset: 0x4048 */
  __I  uint32_t STORE9_BURSTBUFFERPROPERTIES;      /**< Burst Buffer Property register, offset: 0x404C */
  __I  uint32_t STORE9_LASTCONTROLWORD;            /**< Shows the last control word received, offset: 0x4050 */
  __I  uint32_t STORE9_PERFCOUNTER;                /**< Performance counter result, offset: 0x4054 */
  __IO uint32_t STORE9_STATUS;                     /**< Shows status information, offset: 0x4058 */
       uint8_t RESERVED_66[932];
  __I  uint32_t CONSTFRAME0_LOCKUNLOCK;            /**< Register to change the protection status of this address block., offset: 0x4400 */
  __I  uint32_t CONSTFRAME0_LOCKSTATUS;            /**< Protection status of this address block., offset: 0x4404 */
  __IO uint32_t CONSTFRAME0_STATICCONTROL;         /**< ConstFrame unit static control register, offset: 0x4408 */
  __IO uint32_t CONSTFRAME0_FRAMEDIMENSIONS;       /**< Output frame dimensions., offset: 0x440C */
  __IO uint32_t CONSTFRAME0_CONSTANTCOLOR;         /**< Color of output frame., offset: 0x4410 */
  __O  uint32_t CONSTFRAME0_CONTROLTRIGGER;        /**< ConstFrame unit trigger register, offset: 0x4414 */
  __O  uint32_t CONSTFRAME0_START;                 /**< ConstFrame unit start register, offset: 0x4418 */
  __I  uint32_t CONSTFRAME0_STATUS;                /**< Shows status information, offset: 0x441C */
       uint8_t RESERVED_67[992];
  __I  uint32_t EXTDST0_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0x4800 */
  __I  uint32_t EXTDST0_LOCKSTATUS;                /**< Protection status of this address block., offset: 0x4804 */
  __IO uint32_t EXTDST0_STATICCONTROL;             /**< External Destination static control register, offset: 0x4808 */
  __IO uint32_t EXTDST0_CONTROL;                   /**< External Destination shadowed control register, offset: 0x480C */
  __O  uint32_t EXTDST0_SOFTWAREKICK;              /**< External Destination software kick, offset: 0x4810 */
  __IO uint32_t EXTDST0_STATUS;                    /**< External Destination Unit current status, offset: 0x4814 */
  __I  uint32_t EXTDST0_CONTROLWORD;               /**< Value of last received control word, offset: 0x4818 */
  __I  uint32_t EXTDST0_CURPIXELCNT;               /**< pixel count of currently running frame, offset: 0x481C */
  __I  uint32_t EXTDST0_LASTPIXELCNT;              /**< pixel count between last two control words, offset: 0x4820 */
  __I  uint32_t EXTDST0_PERFCOUNTER;               /**< Performance counter result, offset: 0x4824 */
       uint8_t RESERVED_68[984];
  __I  uint32_t CONSTFRAME4_LOCKUNLOCK;            /**< Register to change the protection status of this address block., offset: 0x4C00 */
  __I  uint32_t CONSTFRAME4_LOCKSTATUS;            /**< Protection status of this address block., offset: 0x4C04 */
  __IO uint32_t CONSTFRAME4_STATICCONTROL;         /**< ConstFrame unit static control register, offset: 0x4C08 */
  __IO uint32_t CONSTFRAME4_FRAMEDIMENSIONS;       /**< Output frame dimensions., offset: 0x4C0C */
  __IO uint32_t CONSTFRAME4_CONSTANTCOLOR;         /**< Color of output frame., offset: 0x4C10 */
  __O  uint32_t CONSTFRAME4_CONTROLTRIGGER;        /**< ConstFrame unit trigger register, offset: 0x4C14 */
  __O  uint32_t CONSTFRAME4_START;                 /**< ConstFrame unit start register, offset: 0x4C18 */
  __I  uint32_t CONSTFRAME4_STATUS;                /**< Shows status information, offset: 0x4C1C */
       uint8_t RESERVED_69[992];
  __I  uint32_t EXTDST4_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0x5000 */
  __I  uint32_t EXTDST4_LOCKSTATUS;                /**< Protection status of this address block., offset: 0x5004 */
  __IO uint32_t EXTDST4_STATICCONTROL;             /**< External Destination static control register, offset: 0x5008 */
  __IO uint32_t EXTDST4_CONTROL;                   /**< External Destination shadowed control register, offset: 0x500C */
  __O  uint32_t EXTDST4_SOFTWAREKICK;              /**< External Destination software kick, offset: 0x5010 */
  __IO uint32_t EXTDST4_STATUS;                    /**< External Destination Unit current status, offset: 0x5014 */
  __I  uint32_t EXTDST4_CONTROLWORD;               /**< Value of last received control word, offset: 0x5018 */
  __I  uint32_t EXTDST4_CURPIXELCNT;               /**< pixel count of currently running frame, offset: 0x501C */
  __I  uint32_t EXTDST4_LASTPIXELCNT;              /**< pixel count between last two control words, offset: 0x5020 */
  __I  uint32_t EXTDST4_PERFCOUNTER;               /**< Performance counter result, offset: 0x5024 */
       uint8_t RESERVED_70[984];
  __I  uint32_t CONSTFRAME1_LOCKUNLOCK;            /**< Register to change the protection status of this address block., offset: 0x5400 */
  __I  uint32_t CONSTFRAME1_LOCKSTATUS;            /**< Protection status of this address block., offset: 0x5404 */
  __IO uint32_t CONSTFRAME1_STATICCONTROL;         /**< ConstFrame unit static control register, offset: 0x5408 */
  __IO uint32_t CONSTFRAME1_FRAMEDIMENSIONS;       /**< Output frame dimensions., offset: 0x540C */
  __IO uint32_t CONSTFRAME1_CONSTANTCOLOR;         /**< Color of output frame., offset: 0x5410 */
  __O  uint32_t CONSTFRAME1_CONTROLTRIGGER;        /**< ConstFrame unit trigger register, offset: 0x5414 */
  __O  uint32_t CONSTFRAME1_START;                 /**< ConstFrame unit start register, offset: 0x5418 */
  __I  uint32_t CONSTFRAME1_STATUS;                /**< Shows status information, offset: 0x541C */
       uint8_t RESERVED_71[992];
  __I  uint32_t EXTDST1_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0x5800 */
  __I  uint32_t EXTDST1_LOCKSTATUS;                /**< Protection status of this address block., offset: 0x5804 */
  __IO uint32_t EXTDST1_STATICCONTROL;             /**< External Destination static control register, offset: 0x5808 */
  __IO uint32_t EXTDST1_CONTROL;                   /**< External Destination shadowed control register, offset: 0x580C */
  __O  uint32_t EXTDST1_SOFTWAREKICK;              /**< External Destination software kick, offset: 0x5810 */
  __IO uint32_t EXTDST1_STATUS;                    /**< External Destination Unit current status, offset: 0x5814 */
  __I  uint32_t EXTDST1_CONTROLWORD;               /**< Value of last received control word, offset: 0x5818 */
  __I  uint32_t EXTDST1_CURPIXELCNT;               /**< pixel count of currently running frame, offset: 0x581C */
  __I  uint32_t EXTDST1_LASTPIXELCNT;              /**< pixel count between last two control words, offset: 0x5820 */
  __I  uint32_t EXTDST1_PERFCOUNTER;               /**< Performance counter result, offset: 0x5824 */
       uint8_t RESERVED_72[984];
  __I  uint32_t CONSTFRAME5_LOCKUNLOCK;            /**< Register to change the protection status of this address block., offset: 0x5C00 */
  __I  uint32_t CONSTFRAME5_LOCKSTATUS;            /**< Protection status of this address block., offset: 0x5C04 */
  __IO uint32_t CONSTFRAME5_STATICCONTROL;         /**< ConstFrame unit static control register, offset: 0x5C08 */
  __IO uint32_t CONSTFRAME5_FRAMEDIMENSIONS;       /**< Output frame dimensions., offset: 0x5C0C */
  __IO uint32_t CONSTFRAME5_CONSTANTCOLOR;         /**< Color of output frame., offset: 0x5C10 */
  __O  uint32_t CONSTFRAME5_CONTROLTRIGGER;        /**< ConstFrame unit trigger register, offset: 0x5C14 */
  __O  uint32_t CONSTFRAME5_START;                 /**< ConstFrame unit start register, offset: 0x5C18 */
  __I  uint32_t CONSTFRAME5_STATUS;                /**< Shows status information, offset: 0x5C1C */
       uint8_t RESERVED_73[992];
  __I  uint32_t EXTDST5_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0x6000 */
  __I  uint32_t EXTDST5_LOCKSTATUS;                /**< Protection status of this address block., offset: 0x6004 */
  __IO uint32_t EXTDST5_STATICCONTROL;             /**< External Destination static control register, offset: 0x6008 */
  __IO uint32_t EXTDST5_CONTROL;                   /**< External Destination shadowed control register, offset: 0x600C */
  __O  uint32_t EXTDST5_SOFTWAREKICK;              /**< External Destination software kick, offset: 0x6010 */
  __IO uint32_t EXTDST5_STATUS;                    /**< External Destination Unit current status, offset: 0x6014 */
  __I  uint32_t EXTDST5_CONTROLWORD;               /**< Value of last received control word, offset: 0x6018 */
  __I  uint32_t EXTDST5_CURPIXELCNT;               /**< pixel count of currently running frame, offset: 0x601C */
  __I  uint32_t EXTDST5_LASTPIXELCNT;              /**< pixel count between last two control words, offset: 0x6020 */
  __I  uint32_t EXTDST5_PERFCOUNTER;               /**< Performance counter result, offset: 0x6024 */
       uint8_t RESERVED_74[984];
  __I  uint32_t EXTSRC4_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0x6400 */
  __I  uint32_t EXTSRC4_LOCKSTATUS;                /**< Protection status of this address block., offset: 0x6404 */
  __IO uint32_t EXTSRC4_STATICCONTROL;             /**< ExtSrc static control register, offset: 0x6408 */
  __IO uint32_t EXTSRC4_CLIPWINDOWOFFSET;          /**< Clip window offset, to generate a clipping of the frame. It has to be within the input frame., offset: 0x640C */
  __IO uint32_t EXTSRC4_CLIPWINDOWDIMENSION;       /**< Define the clip window dimension. If the clip window feature is enabled this dimension is used for the new frame dimension. Note that the clip window has to be smaller or equal to the original frame dimensions. The new frame has to be within the active area of the original frame., offset: 0x6410 */
  __IO uint32_t EXTSRC4_COLORCOMPONENTBITS;        /**< Color component size of raw input data. Please note that the width must be equal or lower than the output width., offset: 0x6414 */
  __IO uint32_t EXTSRC4_COLORCOMPONENTSHIFT;       /**< Color component offset of raw input data., offset: 0x6418 */
  __IO uint32_t EXTSRC4_CONSTANTCOLOR;             /**< Constant color register, offset: 0x641C */
  __IO uint32_t EXTSRC4_CONTROL;                   /**< Common control settings., offset: 0x6420 */
  __O  uint32_t EXTSRC4_CONTROLTRIGGER;            /**< ExtSrc unit trigger token generation, offset: 0x6424 */
  __O  uint32_t EXTSRC4_START;                     /**< ExtSrc unit start register, offset: 0x6428 */
  __I  uint32_t EXTSRC4_LASTCOMMANDWORD;           /**< Subset of last input command word with the following mapping: val[31:0]={data[37:22], data[19:12], data[9:2]}, offset: 0x642C */
  __I  uint32_t EXTSRC4_STATUS;                    /**< Shows status information, offset: 0x6430 */
       uint8_t RESERVED_75[972];
  __I  uint32_t STORE4_LOCKUNLOCK;                 /**< Register to change the protection status of this address block., offset: 0x6800 */
  __I  uint32_t STORE4_LOCKSTATUS;                 /**< Protection status of this address block., offset: 0x6804 */
  __IO uint32_t STORE4_STATICCONTROL;              /**< Store unit static control register., offset: 0x6808 */
  __IO uint32_t STORE4_BURSTBUFFERMANAGEMENT;      /**< Burst Buffer setup register., offset: 0x680C */
  __IO uint32_t STORE4_RINGBUFSTARTADDR;           /**< Ring buffer setup for destination., offset: 0x6810 */
  __IO uint32_t STORE4_RINGBUFWRAPADDR;            /**< Ring buffer setup for destination., offset: 0x6814 */
  __IO uint32_t STORE4_BASEADDRESS;                /**< Destination buffer base address., offset: 0x6818 */
  __IO uint32_t STORE4_DESTINATIONBUFFERATTRIBUTES; /**< Destination buffer attributes., offset: 0x681C */
  __IO uint32_t STORE4_DESTINATIONBUFFERDIMENSION; /**< Destination buffer dimension., offset: 0x6820 */
  __IO uint32_t STORE4_FRAMEOFFSET;                /**< Offset between destination frame and buffer., offset: 0x6824 */
  __IO uint32_t STORE4_COLORCOMPONENTBITS;         /**< Color component size of destination buffer, offset: 0x6828 */
  __IO uint32_t STORE4_COLORCOMPONENTSHIFT;        /**< Color component offset of destination buffer., offset: 0x682C */
  __IO uint32_t STORE4_CONTROL;                    /**< Store unit dynamic control register, offset: 0x6830 */
  __IO uint32_t STORE4_ENCODECONTROL;              /**< Control options for RLAD compression., offset: 0x6834 */
  __IO uint32_t STORE4_DESTINATIONBUFFERLENGTH;    /**< Destination buffer length for compressed data., offset: 0x6838 */
  __O  uint32_t STORE4_START;                      /**< Store unit start register, offset: 0x683C */
  __IO uint32_t STORE4_ENCODERSTATUS;              /**< Status information of the RLAD encoder., offset: 0x6840 */
  __I  uint32_t STORE4_WRITEADDRESS;               /**< Ring buffer synchronization., offset: 0x6844 */
  __I  uint32_t STORE4_FRAMEPROPERTIES;            /**< Ring buffer synchronization., offset: 0x6848 */
  __I  uint32_t STORE4_BURSTBUFFERPROPERTIES;      /**< Burst Buffer Property register, offset: 0x684C */
  __I  uint32_t STORE4_LASTCONTROLWORD;            /**< Shows the last control word received, offset: 0x6850 */
  __I  uint32_t STORE4_PERFCOUNTER;                /**< Performance counter result, offset: 0x6854 */
  __IO uint32_t STORE4_STATUS;                     /**< Shows status information, offset: 0x6858 */
       uint8_t RESERVED_76[932];
  __I  uint32_t EXTSRC5_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0x6C00 */
  __I  uint32_t EXTSRC5_LOCKSTATUS;                /**< Protection status of this address block., offset: 0x6C04 */
  __IO uint32_t EXTSRC5_STATICCONTROL;             /**< ExtSrc static control register, offset: 0x6C08 */
  __IO uint32_t EXTSRC5_CLIPWINDOWOFFSET;          /**< Clip window offset, to generate a clipping of the frame. It has to be within the input frame., offset: 0x6C0C */
  __IO uint32_t EXTSRC5_CLIPWINDOWDIMENSION;       /**< Define the clip window dimension. If the clip window feature is enabled this dimension is used for the new frame dimension. Note that the clip window has to be smaller or equal to the original frame dimensions. The new frame has to be within the active area of the original frame., offset: 0x6C10 */
  __IO uint32_t EXTSRC5_COLORCOMPONENTBITS;        /**< Color component size of raw input data. Please note that the width must be equal or lower than the output width., offset: 0x6C14 */
  __IO uint32_t EXTSRC5_COLORCOMPONENTSHIFT;       /**< Color component offset of raw input data., offset: 0x6C18 */
  __IO uint32_t EXTSRC5_CONSTANTCOLOR;             /**< Constant color register, offset: 0x6C1C */
  __IO uint32_t EXTSRC5_CONTROL;                   /**< Common control settings., offset: 0x6C20 */
  __O  uint32_t EXTSRC5_CONTROLTRIGGER;            /**< ExtSrc unit trigger token generation, offset: 0x6C24 */
  __O  uint32_t EXTSRC5_START;                     /**< ExtSrc unit start register, offset: 0x6C28 */
  __I  uint32_t EXTSRC5_LASTCOMMANDWORD;           /**< Subset of last input command word with the following mapping: val[31:0]={data[37:22], data[19:12], data[9:2]}, offset: 0x6C2C */
  __I  uint32_t EXTSRC5_STATUS;                    /**< Shows status information, offset: 0x6C30 */
       uint8_t RESERVED_77[972];
  __I  uint32_t STORE5_LOCKUNLOCK;                 /**< Register to change the protection status of this address block., offset: 0x7000 */
  __I  uint32_t STORE5_LOCKSTATUS;                 /**< Protection status of this address block., offset: 0x7004 */
  __IO uint32_t STORE5_STATICCONTROL;              /**< Store unit static control register., offset: 0x7008 */
  __IO uint32_t STORE5_BURSTBUFFERMANAGEMENT;      /**< Burst Buffer setup register., offset: 0x700C */
  __IO uint32_t STORE5_RINGBUFSTARTADDR;           /**< Ring buffer setup for destination., offset: 0x7010 */
  __IO uint32_t STORE5_RINGBUFWRAPADDR;            /**< Ring buffer setup for destination., offset: 0x7014 */
  __IO uint32_t STORE5_BASEADDRESS;                /**< Destination buffer base address., offset: 0x7018 */
  __IO uint32_t STORE5_DESTINATIONBUFFERATTRIBUTES; /**< Destination buffer attributes., offset: 0x701C */
  __IO uint32_t STORE5_DESTINATIONBUFFERDIMENSION; /**< Destination buffer dimension., offset: 0x7020 */
  __IO uint32_t STORE5_FRAMEOFFSET;                /**< Offset between destination frame and buffer., offset: 0x7024 */
  __IO uint32_t STORE5_COLORCOMPONENTBITS;         /**< Color component size of destination buffer, offset: 0x7028 */
  __IO uint32_t STORE5_COLORCOMPONENTSHIFT;        /**< Color component offset of destination buffer., offset: 0x702C */
  __IO uint32_t STORE5_CONTROL;                    /**< Store unit dynamic control register, offset: 0x7030 */
  __IO uint32_t STORE5_ENCODECONTROL;              /**< Control options for RLAD compression., offset: 0x7034 */
  __IO uint32_t STORE5_DESTINATIONBUFFERLENGTH;    /**< Destination buffer length for compressed data., offset: 0x7038 */
  __O  uint32_t STORE5_START;                      /**< Store unit start register, offset: 0x703C */
  __IO uint32_t STORE5_ENCODERSTATUS;              /**< Status information of the RLAD encoder., offset: 0x7040 */
  __I  uint32_t STORE5_WRITEADDRESS;               /**< Ring buffer synchronization., offset: 0x7044 */
  __I  uint32_t STORE5_FRAMEPROPERTIES;            /**< Ring buffer synchronization., offset: 0x7048 */
  __I  uint32_t STORE5_BURSTBUFFERPROPERTIES;      /**< Burst Buffer Property register, offset: 0x704C */
  __I  uint32_t STORE5_LASTCONTROLWORD;            /**< Shows the last control word received, offset: 0x7050 */
  __I  uint32_t STORE5_PERFCOUNTER;                /**< Performance counter result, offset: 0x7054 */
  __IO uint32_t STORE5_STATUS;                     /**< Shows status information, offset: 0x7058 */
       uint8_t RESERVED_78[932];
  __I  uint32_t FETCHDECODE2_LOCKUNLOCK;           /**< Register to change the protection status of this address block., offset: 0x7400 */
  __I  uint32_t FETCHDECODE2_LOCKSTATUS;           /**< Protection status of this address block., offset: 0x7404 */
  __IO uint32_t FETCHDECODE2_STATICCONTROL;        /**< Common static control options., offset: 0x7408 */
  __IO uint32_t FETCHDECODE2_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x740C */
  __IO uint32_t FETCHDECODE2_RINGBUFSTARTADDR0;    /**< Ring buffer setup for layer 0., offset: 0x7410 */
  __IO uint32_t FETCHDECODE2_RINGBUFWRAPADDR0;     /**< Ring buffer setup for layer 0., offset: 0x7414 */
  __IO uint32_t FETCHDECODE2_FRAMEPROPERTIES0;     /**< Frame property setup for layer 0., offset: 0x7418 */
  __IO uint32_t FETCHDECODE2_BASEADDRESS0;         /**< Source buffer base address of layer 0., offset: 0x741C */
  __IO uint32_t FETCHDECODE2_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x7420 */
  __IO uint32_t FETCHDECODE2_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x7424 */
  __IO uint32_t FETCHDECODE2_COLORCOMPONENTBITS0;  /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x7428 */
  __IO uint32_t FETCHDECODE2_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x742C */
  __IO uint32_t FETCHDECODE2_LAYEROFFSET0;         /**< Position of layer 0 within the destination frame., offset: 0x7430 */
  __IO uint32_t FETCHDECODE2_CLIPWINDOWOFFSET0;    /**< Clip window position for layer 0., offset: 0x7434 */
  __IO uint32_t FETCHDECODE2_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x7438 */
  __IO uint32_t FETCHDECODE2_CONSTANTCOLOR0;       /**< Constant color for layer 0., offset: 0x743C */
  __IO uint32_t FETCHDECODE2_LAYERPROPERTY0;       /**< Common properties of layer 0., offset: 0x7440 */
  __IO uint32_t FETCHDECODE2_FRAMEDIMENSIONS;      /**< Output frame dimension., offset: 0x7444 */
  __IO uint32_t FETCHDECODE2_FRAMERESAMPLING;      /**< Resampling options for output frame., offset: 0x7448 */
  __IO uint32_t FETCHDECODE2_DECODECONTROL;        /**< Control options for RLAD decompression., offset: 0x744C */
  __IO uint32_t FETCHDECODE2_SOURCEBUFFERLENGTH;   /**< Source buffer length for compressed data., offset: 0x7450 */
  __IO uint32_t FETCHDECODE2_CONTROL;              /**< Shared common control settings for all layers., offset: 0x7454 */
  __O  uint32_t FETCHDECODE2_CONTROLTRIGGER;       /**< Shadow load trigger., offset: 0x7458 */
  __O  uint32_t FETCHDECODE2_START;                /**< Frame start trigger., offset: 0x745C */
  __I  uint32_t FETCHDECODE2_FETCHTYPE;            /**< Fetch unit type., offset: 0x7460 */
  __IO uint32_t FETCHDECODE2_DECODERSTATUS;        /**< Status information of the RLAD decoder., offset: 0x7464 */
  __I  uint32_t FETCHDECODE2_READADDRESS0;         /**< Ring buffer synchronization for layer 0., offset: 0x7468 */
  __I  uint32_t FETCHDECODE2_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x746C */
  __IO uint32_t FETCHDECODE2_STATUS;               /**< Status informations., offset: 0x7470 */
  __I  uint32_t FETCHDECODE2_HIDDENSTATUS;         /**< Hidden status informations., offset: 0x7474 */
       uint8_t RESERVED_79[904];
  __IO uint32_t FETCHDECODE2_COLORPALETTE;         /**< Color palette look up table., offset: 0x7800 */
       uint8_t RESERVED_80[1020];
  __I  uint32_t FETCHDECODE3_LOCKUNLOCK;           /**< Register to change the protection status of this address block., offset: 0x7C00 */
  __I  uint32_t FETCHDECODE3_LOCKSTATUS;           /**< Protection status of this address block., offset: 0x7C04 */
  __IO uint32_t FETCHDECODE3_STATICCONTROL;        /**< Common static control options., offset: 0x7C08 */
  __IO uint32_t FETCHDECODE3_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x7C0C */
  __IO uint32_t FETCHDECODE3_RINGBUFSTARTADDR0;    /**< Ring buffer setup for layer 0., offset: 0x7C10 */
  __IO uint32_t FETCHDECODE3_RINGBUFWRAPADDR0;     /**< Ring buffer setup for layer 0., offset: 0x7C14 */
  __IO uint32_t FETCHDECODE3_FRAMEPROPERTIES0;     /**< Frame property setup for layer 0., offset: 0x7C18 */
  __IO uint32_t FETCHDECODE3_BASEADDRESS0;         /**< Source buffer base address of layer 0., offset: 0x7C1C */
  __IO uint32_t FETCHDECODE3_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x7C20 */
  __IO uint32_t FETCHDECODE3_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x7C24 */
  __IO uint32_t FETCHDECODE3_COLORCOMPONENTBITS0;  /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x7C28 */
  __IO uint32_t FETCHDECODE3_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x7C2C */
  __IO uint32_t FETCHDECODE3_LAYEROFFSET0;         /**< Position of layer 0 within the destination frame., offset: 0x7C30 */
  __IO uint32_t FETCHDECODE3_CLIPWINDOWOFFSET0;    /**< Clip window position for layer 0., offset: 0x7C34 */
  __IO uint32_t FETCHDECODE3_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x7C38 */
  __IO uint32_t FETCHDECODE3_CONSTANTCOLOR0;       /**< Constant color for layer 0., offset: 0x7C3C */
  __IO uint32_t FETCHDECODE3_LAYERPROPERTY0;       /**< Common properties of layer 0., offset: 0x7C40 */
  __IO uint32_t FETCHDECODE3_FRAMEDIMENSIONS;      /**< Output frame dimension., offset: 0x7C44 */
  __IO uint32_t FETCHDECODE3_FRAMERESAMPLING;      /**< Resampling options for output frame., offset: 0x7C48 */
  __IO uint32_t FETCHDECODE3_DECODECONTROL;        /**< Control options for RLAD decompression., offset: 0x7C4C */
  __IO uint32_t FETCHDECODE3_SOURCEBUFFERLENGTH;   /**< Source buffer length for compressed data., offset: 0x7C50 */
  __IO uint32_t FETCHDECODE3_CONTROL;              /**< Shared common control settings for all layers., offset: 0x7C54 */
  __O  uint32_t FETCHDECODE3_CONTROLTRIGGER;       /**< Shadow load trigger., offset: 0x7C58 */
  __O  uint32_t FETCHDECODE3_START;                /**< Frame start trigger., offset: 0x7C5C */
  __I  uint32_t FETCHDECODE3_FETCHTYPE;            /**< Fetch unit type., offset: 0x7C60 */
  __IO uint32_t FETCHDECODE3_DECODERSTATUS;        /**< Status information of the RLAD decoder., offset: 0x7C64 */
  __I  uint32_t FETCHDECODE3_READADDRESS0;         /**< Ring buffer synchronization for layer 0., offset: 0x7C68 */
  __I  uint32_t FETCHDECODE3_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x7C6C */
  __IO uint32_t FETCHDECODE3_STATUS;               /**< Status informations., offset: 0x7C70 */
  __I  uint32_t FETCHDECODE3_HIDDENSTATUS;         /**< Hidden status informations., offset: 0x7C74 */
       uint8_t RESERVED_81[904];
  __IO uint32_t FETCHDECODE3_COLORPALETTE;         /**< Color palette look up table., offset: 0x8000 */
       uint8_t RESERVED_82[1020];
  __I  uint32_t FETCHWARP2_LOCKUNLOCK;             /**< Register to change the protection status of this address block., offset: 0x8400 */
  __I  uint32_t FETCHWARP2_LOCKSTATUS;             /**< Protection status of this address block., offset: 0x8404 */
  __IO uint32_t FETCHWARP2_STATICCONTROL;          /**< Common static control options., offset: 0x8408 */
  __IO uint32_t FETCHWARP2_BURSTBUFFERMANAGEMENT;  /**< AXI interface buffer management register, offset: 0x840C */
  __IO uint32_t FETCHWARP2_BASEADDRESS0;           /**< Source buffer base address of layer 0., offset: 0x8410 */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x8414 */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x8418 */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS0;    /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x841C */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT0;   /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x8420 */
  __IO uint32_t FETCHWARP2_LAYEROFFSET0;           /**< Position of layer 0 within the destination frame., offset: 0x8424 */
  __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET0;      /**< Clip window position for layer 0., offset: 0x8428 */
  __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS0;  /**< Clip window size for layer 0., offset: 0x842C */
  __IO uint32_t FETCHWARP2_CONSTANTCOLOR0;         /**< Constant color for layer 0., offset: 0x8430 */
  __IO uint32_t FETCHWARP2_LAYERPROPERTY0;         /**< Common properties of layer 0., offset: 0x8434 */
  __IO uint32_t FETCHWARP2_BASEADDRESS1;           /**< Source buffer base address of layer 1., offset: 0x8438 */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES1; /**< Source buffer attributes for layer 1., offset: 0x843C */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION1; /**< Source buffer dimensions of layer 1,, offset: 0x8440 */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS1;    /**< Size of color components for RGB, YUV and index formats (layer 1)., offset: 0x8444 */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT1;   /**< Bit position of color components for RGB, YUV and index formats (layer 1)., offset: 0x8448 */
  __IO uint32_t FETCHWARP2_LAYEROFFSET1;           /**< Position of layer 1 within the destination frame., offset: 0x844C */
  __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET1;      /**< Clip window position for layer 1., offset: 0x8450 */
  __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS1;  /**< Clip window size for layer 1., offset: 0x8454 */
  __IO uint32_t FETCHWARP2_CONSTANTCOLOR1;         /**< Constant color for layer 1., offset: 0x8458 */
  __IO uint32_t FETCHWARP2_LAYERPROPERTY1;         /**< Common properties of layer 1., offset: 0x845C */
  __IO uint32_t FETCHWARP2_BASEADDRESS2;           /**< Source buffer base address of layer 2., offset: 0x8460 */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES2; /**< Source buffer attributes for layer 2., offset: 0x8464 */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION2; /**< Source buffer dimension of layer 2., offset: 0x8468 */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS2;    /**< Size of color components for RGB, YUV and index formats (layer 2)., offset: 0x846C */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT2;   /**< Bit position of color components for RGB, YUV and index formats (layer 2)., offset: 0x8470 */
  __IO uint32_t FETCHWARP2_LAYEROFFSET2;           /**< Position of layer 2 within the destination frame., offset: 0x8474 */
  __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET2;      /**< Clip window position for layer 2., offset: 0x8478 */
  __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS2;  /**< Clip window size for layer 2., offset: 0x847C */
  __IO uint32_t FETCHWARP2_CONSTANTCOLOR2;         /**< Constant color for layer 2., offset: 0x8480 */
  __IO uint32_t FETCHWARP2_LAYERPROPERTY2;         /**< Common properties of layer 2., offset: 0x8484 */
  __IO uint32_t FETCHWARP2_BASEADDRESS3;           /**< Source buffer base address of layer 3., offset: 0x8488 */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES3; /**< Source buffer attributes for layer 3., offset: 0x848C */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION3; /**< Source buffer dimension of layer 3., offset: 0x8490 */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS3;    /**< Size of color components for RGB, YUV and index formats (layer 3)., offset: 0x8494 */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT3;   /**< Bit position of color components for RGB, YUV and index formats (layer 3)., offset: 0x8498 */
  __IO uint32_t FETCHWARP2_LAYEROFFSET3;           /**< Position of layer 3 within the destination frame., offset: 0x849C */
  __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET3;      /**< Clip window position for layer 3., offset: 0x84A0 */
  __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS3;  /**< Clip window size for layer 3., offset: 0x84A4 */
  __IO uint32_t FETCHWARP2_CONSTANTCOLOR3;         /**< Constant color for layer 3., offset: 0x84A8 */
  __IO uint32_t FETCHWARP2_LAYERPROPERTY3;         /**< Common properties of layer 3., offset: 0x84AC */
  __IO uint32_t FETCHWARP2_BASEADDRESS4;           /**< Source buffer base address of layer 4., offset: 0x84B0 */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES4; /**< Source buffer attributes for layer 4., offset: 0x84B4 */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION4; /**< Source buffer dimension of layer 4., offset: 0x84B8 */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS4;    /**< Size of color components for RGB, YUV and index formats (layer 4)., offset: 0x84BC */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT4;   /**< Bit position of color components for RGB, YUV and index formats (layer 4)., offset: 0x84C0 */
  __IO uint32_t FETCHWARP2_LAYEROFFSET4;           /**< Position of layer 4 within the destination frame., offset: 0x84C4 */
  __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET4;      /**< Clip window position for layer 4., offset: 0x84C8 */
  __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS4;  /**< Clip window size for layer 4., offset: 0x84CC */
  __IO uint32_t FETCHWARP2_CONSTANTCOLOR4;         /**< Constant color for layer 4., offset: 0x84D0 */
  __IO uint32_t FETCHWARP2_LAYERPROPERTY4;         /**< Common properties of layer 4., offset: 0x84D4 */
  __IO uint32_t FETCHWARP2_BASEADDRESS5;           /**< Source buffer base address of layer 5., offset: 0x84D8 */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES5; /**< Source buffer attributes for layer 5., offset: 0x84DC */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION5; /**< Source buffer dimension of layer 5., offset: 0x84E0 */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS5;    /**< Size of color components for RGB, YUV and index formats (layer 5)., offset: 0x84E4 */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT5;   /**< Bit position of color components for RGB, YUV and index formats (layer 5)., offset: 0x84E8 */
  __IO uint32_t FETCHWARP2_LAYEROFFSET5;           /**< Position of layer 5 within the destination frame., offset: 0x84EC */
  __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET5;      /**< Clip window position for layer 5., offset: 0x84F0 */
  __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS5;  /**< Clip window size for layer 5., offset: 0x84F4 */
  __IO uint32_t FETCHWARP2_CONSTANTCOLOR5;         /**< Constant color for layer 5., offset: 0x84F8 */
  __IO uint32_t FETCHWARP2_LAYERPROPERTY5;         /**< Common properties of layer 5., offset: 0x84FC */
  __IO uint32_t FETCHWARP2_BASEADDRESS6;           /**< Source buffer base address of layer 6., offset: 0x8500 */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES6; /**< Source buffer attributes for layer 6., offset: 0x8504 */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION6; /**< Source buffer dimension of layer 6., offset: 0x8508 */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS6;    /**< Size of color components for RGB, YUV and index formats (layer 6)., offset: 0x850C */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT6;   /**< Bit position of color components for RGB, YUV and index formats (layer 6)., offset: 0x8510 */
  __IO uint32_t FETCHWARP2_LAYEROFFSET6;           /**< Position of layer 1 within the destination frame., offset: 0x8514 */
  __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET6;      /**< Clip window position for layer 6., offset: 0x8518 */
  __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS6;  /**< Clip window size for layer 6., offset: 0x851C */
  __IO uint32_t FETCHWARP2_CONSTANTCOLOR6;         /**< Constant color for layer 6., offset: 0x8520 */
  __IO uint32_t FETCHWARP2_LAYERPROPERTY6;         /**< Common properties of layer 6., offset: 0x8524 */
  __IO uint32_t FETCHWARP2_BASEADDRESS7;           /**< Source buffer base address of layer 7., offset: 0x8528 */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES7; /**< Source buffer stride for layer 7., offset: 0x852C */
  __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION7; /**< Source buffer dimension of layer 7., offset: 0x8530 */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS7;    /**< Size of color components for RGB, YUV and index formats (layer 7)., offset: 0x8534 */
  __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT7;   /**< Bit position of color components for RGB, YUV and index formats (layer 7)., offset: 0x8538 */
  __IO uint32_t FETCHWARP2_LAYEROFFSET7;           /**< Position of layer 7 within the destination frame., offset: 0x853C */
  __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET7;      /**< Clip window position for layer 7., offset: 0x8540 */
  __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS7;  /**< Clip window size for layer 7., offset: 0x8544 */
  __IO uint32_t FETCHWARP2_CONSTANTCOLOR7;         /**< Constant color for layer 7., offset: 0x8548 */
  __IO uint32_t FETCHWARP2_LAYERPROPERTY7;         /**< Common properties of layer 7., offset: 0x854C */
  __IO uint32_t FETCHWARP2_FRAMEDIMENSIONS;        /**< Output frame dimension., offset: 0x8550 */
  __IO uint32_t FETCHWARP2_FRAMERESAMPLING;        /**< Resampling options for output frame., offset: 0x8554 */
  __IO uint32_t FETCHWARP2_WARPCONTROL;            /**< Warping control options., offset: 0x8558 */
  __IO uint32_t FETCHWARP2_ARBSTARTX;              /**< Start value X for arbitrary warping., offset: 0x855C */
  __IO uint32_t FETCHWARP2_ARBSTARTY;              /**< Start value Y for arbitrary warping., offset: 0x8560 */
  __IO uint32_t FETCHWARP2_ARBDELTA;               /**< Start values for delta incrementation of arbitrary warping., offset: 0x8564 */
  __IO uint32_t FETCHWARP2_FIRPOSITIONS;           /**< FIR sequence control register., offset: 0x8568 */
  __IO uint32_t FETCHWARP2_FIRCOEFFICIENTS;        /**< FIR coefficients register., offset: 0x856C */
  __IO uint32_t FETCHWARP2_CONTROL;                /**< Shared common control settings for all layers., offset: 0x8570 */
  __I  uint32_t FETCHWARP2_TRIGGERENABLE;          /**< Shadow load enable flags for all layers., offset: 0x8574 */
  __O  uint32_t FETCHWARP2_CONTROLTRIGGER;         /**< Shadow load trigger., offset: 0x8578 */
  __O  uint32_t FETCHWARP2_START;                  /**< Frame start trigger., offset: 0x857C */
  __I  uint32_t FETCHWARP2_FETCHTYPE;              /**< Fetch unit type., offset: 0x8580 */
  __I  uint32_t FETCHWARP2_BURSTBUFFERPROPERTIES;  /**< Burst buffer properties., offset: 0x8584 */
  __IO uint32_t FETCHWARP2_STATUS;                 /**< Status informations., offset: 0x8588 */
  __I  uint32_t FETCHWARP2_HIDDENSTATUS;           /**< Hidden status informations., offset: 0x858C */
       uint8_t RESERVED_83[624];
  __I  uint32_t FETCHECO2_LOCKUNLOCK;              /**< Register to change the protection status of this address block., offset: 0x8800 */
  __I  uint32_t FETCHECO2_LOCKSTATUS;              /**< Protection status of this address block., offset: 0x8804 */
  __IO uint32_t FETCHECO2_STATICCONTROL;           /**< Common static control options., offset: 0x8808 */
  __IO uint32_t FETCHECO2_BURSTBUFFERMANAGEMENT;   /**< AXI interface buffer management register, offset: 0x880C */
  __IO uint32_t FETCHECO2_BASEADDRESS0;            /**< Source buffer base address of layer 0., offset: 0x8810 */
  __IO uint32_t FETCHECO2_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x8814 */
  __IO uint32_t FETCHECO2_SOURCEBUFFERDIMENSION0;  /**< Source buffer dimension of layer 0., offset: 0x8818 */
  __IO uint32_t FETCHECO2_COLORCOMPONENTBITS0;     /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x881C */
  __IO uint32_t FETCHECO2_COLORCOMPONENTSHIFT0;    /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x8820 */
  __IO uint32_t FETCHECO2_LAYEROFFSET0;            /**< Position of layer 0 within the destination frame., offset: 0x8824 */
  __IO uint32_t FETCHECO2_CLIPWINDOWOFFSET0;       /**< Clip window position for layer 0., offset: 0x8828 */
  __IO uint32_t FETCHECO2_CLIPWINDOWDIMENSIONS0;   /**< Clip window size for layer 0., offset: 0x882C */
  __IO uint32_t FETCHECO2_CONSTANTCOLOR0;          /**< Constant color for layer 0., offset: 0x8830 */
  __IO uint32_t FETCHECO2_LAYERPROPERTY0;          /**< Common properties of layer 0., offset: 0x8834 */
  __IO uint32_t FETCHECO2_FRAMEDIMENSIONS;         /**< Output frame dimension., offset: 0x8838 */
  __IO uint32_t FETCHECO2_FRAMERESAMPLING;         /**< Resampling options for output frame., offset: 0x883C */
  __IO uint32_t FETCHECO2_CONTROL;                 /**< Shared common control settings for all layers., offset: 0x8840 */
  __O  uint32_t FETCHECO2_CONTROLTRIGGER;          /**< Shadow load trigger., offset: 0x8844 */
  __O  uint32_t FETCHECO2_START;                   /**< Frame start trigger., offset: 0x8848 */
  __I  uint32_t FETCHECO2_FETCHTYPE;               /**< Fetch unit type., offset: 0x884C */
  __I  uint32_t FETCHECO2_BURSTBUFFERPROPERTIES;   /**< Burst buffer properties., offset: 0x8850 */
  __I  uint32_t FETCHECO2_HIDDENSTATUS;            /**< Hidden status informations., offset: 0x8854 */
       uint8_t RESERVED_84[936];
  __I  uint32_t FETCHDECODE0_LOCKUNLOCK;           /**< Register to change the protection status of this address block., offset: 0x8C00 */
  __I  uint32_t FETCHDECODE0_LOCKSTATUS;           /**< Protection status of this address block., offset: 0x8C04 */
  __IO uint32_t FETCHDECODE0_STATICCONTROL;        /**< Common static control options., offset: 0x8C08 */
  __IO uint32_t FETCHDECODE0_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x8C0C */
  __IO uint32_t FETCHDECODE0_RINGBUFSTARTADDR0;    /**< Ring buffer setup for layer 0., offset: 0x8C10 */
  __IO uint32_t FETCHDECODE0_RINGBUFWRAPADDR0;     /**< Ring buffer setup for layer 0., offset: 0x8C14 */
  __IO uint32_t FETCHDECODE0_FRAMEPROPERTIES0;     /**< Frame property setup for layer 0., offset: 0x8C18 */
  __IO uint32_t FETCHDECODE0_BASEADDRESS0;         /**< Source buffer base address of layer 0., offset: 0x8C1C */
  __IO uint32_t FETCHDECODE0_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x8C20 */
  __IO uint32_t FETCHDECODE0_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x8C24 */
  __IO uint32_t FETCHDECODE0_COLORCOMPONENTBITS0;  /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x8C28 */
  __IO uint32_t FETCHDECODE0_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x8C2C */
  __IO uint32_t FETCHDECODE0_LAYEROFFSET0;         /**< Position of layer 0 within the destination frame., offset: 0x8C30 */
  __IO uint32_t FETCHDECODE0_CLIPWINDOWOFFSET0;    /**< Clip window position for layer 0., offset: 0x8C34 */
  __IO uint32_t FETCHDECODE0_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x8C38 */
  __IO uint32_t FETCHDECODE0_CONSTANTCOLOR0;       /**< Constant color for layer 0., offset: 0x8C3C */
  __IO uint32_t FETCHDECODE0_LAYERPROPERTY0;       /**< Common properties of layer 0., offset: 0x8C40 */
  __IO uint32_t FETCHDECODE0_FRAMEDIMENSIONS;      /**< Output frame dimension., offset: 0x8C44 */
  __IO uint32_t FETCHDECODE0_FRAMERESAMPLING;      /**< Resampling options for output frame., offset: 0x8C48 */
  __IO uint32_t FETCHDECODE0_DECODECONTROL;        /**< Control options for RLAD decompression., offset: 0x8C4C */
  __IO uint32_t FETCHDECODE0_SOURCEBUFFERLENGTH;   /**< Source buffer length for compressed data., offset: 0x8C50 */
  __IO uint32_t FETCHDECODE0_CONTROL;              /**< Shared common control settings for all layers., offset: 0x8C54 */
  __O  uint32_t FETCHDECODE0_CONTROLTRIGGER;       /**< Shadow load trigger., offset: 0x8C58 */
  __O  uint32_t FETCHDECODE0_START;                /**< Frame start trigger., offset: 0x8C5C */
  __I  uint32_t FETCHDECODE0_FETCHTYPE;            /**< Fetch unit type., offset: 0x8C60 */
  __IO uint32_t FETCHDECODE0_DECODERSTATUS;        /**< Status information of the RLAD decoder., offset: 0x8C64 */
  __I  uint32_t FETCHDECODE0_READADDRESS0;         /**< Ring buffer synchronization for layer 0., offset: 0x8C68 */
  __I  uint32_t FETCHDECODE0_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x8C6C */
  __IO uint32_t FETCHDECODE0_STATUS;               /**< Status informations., offset: 0x8C70 */
  __I  uint32_t FETCHDECODE0_HIDDENSTATUS;         /**< Hidden status informations., offset: 0x8C74 */
       uint8_t RESERVED_85[904];
  __IO uint32_t FETCHDECODE0_COLORPALETTE;         /**< Color palette look up table., offset: 0x9000 */
       uint8_t RESERVED_86[1020];
  __I  uint32_t FETCHECO0_LOCKUNLOCK;              /**< Register to change the protection status of this address block., offset: 0x9400 */
  __I  uint32_t FETCHECO0_LOCKSTATUS;              /**< Protection status of this address block., offset: 0x9404 */
  __IO uint32_t FETCHECO0_STATICCONTROL;           /**< Common static control options., offset: 0x9408 */
  __IO uint32_t FETCHECO0_BURSTBUFFERMANAGEMENT;   /**< AXI interface buffer management register, offset: 0x940C */
  __IO uint32_t FETCHECO0_BASEADDRESS0;            /**< Source buffer base address of layer 0., offset: 0x9410 */
  __IO uint32_t FETCHECO0_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x9414 */
  __IO uint32_t FETCHECO0_SOURCEBUFFERDIMENSION0;  /**< Source buffer dimension of layer 0., offset: 0x9418 */
  __IO uint32_t FETCHECO0_COLORCOMPONENTBITS0;     /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x941C */
  __IO uint32_t FETCHECO0_COLORCOMPONENTSHIFT0;    /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x9420 */
  __IO uint32_t FETCHECO0_LAYEROFFSET0;            /**< Position of layer 0 within the destination frame., offset: 0x9424 */
  __IO uint32_t FETCHECO0_CLIPWINDOWOFFSET0;       /**< Clip window position for layer 0., offset: 0x9428 */
  __IO uint32_t FETCHECO0_CLIPWINDOWDIMENSIONS0;   /**< Clip window size for layer 0., offset: 0x942C */
  __IO uint32_t FETCHECO0_CONSTANTCOLOR0;          /**< Constant color for layer 0., offset: 0x9430 */
  __IO uint32_t FETCHECO0_LAYERPROPERTY0;          /**< Common properties of layer 0., offset: 0x9434 */
  __IO uint32_t FETCHECO0_FRAMEDIMENSIONS;         /**< Output frame dimension., offset: 0x9438 */
  __IO uint32_t FETCHECO0_FRAMERESAMPLING;         /**< Resampling options for output frame., offset: 0x943C */
  __IO uint32_t FETCHECO0_CONTROL;                 /**< Shared common control settings for all layers., offset: 0x9440 */
  __O  uint32_t FETCHECO0_CONTROLTRIGGER;          /**< Shadow load trigger., offset: 0x9444 */
  __O  uint32_t FETCHECO0_START;                   /**< Frame start trigger., offset: 0x9448 */
  __I  uint32_t FETCHECO0_FETCHTYPE;               /**< Fetch unit type., offset: 0x944C */
  __I  uint32_t FETCHECO0_BURSTBUFFERPROPERTIES;   /**< Burst buffer properties., offset: 0x9450 */
  __I  uint32_t FETCHECO0_HIDDENSTATUS;            /**< Hidden status informations., offset: 0x9454 */
       uint8_t RESERVED_87[936];
  __I  uint32_t FETCHDECODE1_LOCKUNLOCK;           /**< Register to change the protection status of this address block., offset: 0x9800 */
  __I  uint32_t FETCHDECODE1_LOCKSTATUS;           /**< Protection status of this address block., offset: 0x9804 */
  __IO uint32_t FETCHDECODE1_STATICCONTROL;        /**< Common static control options., offset: 0x9808 */
  __IO uint32_t FETCHDECODE1_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x980C */
  __IO uint32_t FETCHDECODE1_RINGBUFSTARTADDR0;    /**< Ring buffer setup for layer 0., offset: 0x9810 */
  __IO uint32_t FETCHDECODE1_RINGBUFWRAPADDR0;     /**< Ring buffer setup for layer 0., offset: 0x9814 */
  __IO uint32_t FETCHDECODE1_FRAMEPROPERTIES0;     /**< Frame property setup for layer 0., offset: 0x9818 */
  __IO uint32_t FETCHDECODE1_BASEADDRESS0;         /**< Source buffer base address of layer 0., offset: 0x981C */
  __IO uint32_t FETCHDECODE1_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x9820 */
  __IO uint32_t FETCHDECODE1_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x9824 */
  __IO uint32_t FETCHDECODE1_COLORCOMPONENTBITS0;  /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x9828 */
  __IO uint32_t FETCHDECODE1_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x982C */
  __IO uint32_t FETCHDECODE1_LAYEROFFSET0;         /**< Position of layer 0 within the destination frame., offset: 0x9830 */
  __IO uint32_t FETCHDECODE1_CLIPWINDOWOFFSET0;    /**< Clip window position for layer 0., offset: 0x9834 */
  __IO uint32_t FETCHDECODE1_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x9838 */
  __IO uint32_t FETCHDECODE1_CONSTANTCOLOR0;       /**< Constant color for layer 0., offset: 0x983C */
  __IO uint32_t FETCHDECODE1_LAYERPROPERTY0;       /**< Common properties of layer 0., offset: 0x9840 */
  __IO uint32_t FETCHDECODE1_FRAMEDIMENSIONS;      /**< Output frame dimension., offset: 0x9844 */
  __IO uint32_t FETCHDECODE1_FRAMERESAMPLING;      /**< Resampling options for output frame., offset: 0x9848 */
  __IO uint32_t FETCHDECODE1_DECODECONTROL;        /**< Control options for RLAD decompression., offset: 0x984C */
  __IO uint32_t FETCHDECODE1_SOURCEBUFFERLENGTH;   /**< Source buffer length for compressed data., offset: 0x9850 */
  __IO uint32_t FETCHDECODE1_CONTROL;              /**< Shared common control settings for all layers., offset: 0x9854 */
  __O  uint32_t FETCHDECODE1_CONTROLTRIGGER;       /**< Shadow load trigger., offset: 0x9858 */
  __O  uint32_t FETCHDECODE1_START;                /**< Frame start trigger., offset: 0x985C */
  __I  uint32_t FETCHDECODE1_FETCHTYPE;            /**< Fetch unit type., offset: 0x9860 */
  __IO uint32_t FETCHDECODE1_DECODERSTATUS;        /**< Status information of the RLAD decoder., offset: 0x9864 */
  __I  uint32_t FETCHDECODE1_READADDRESS0;         /**< Ring buffer synchronization for layer 0., offset: 0x9868 */
  __I  uint32_t FETCHDECODE1_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x986C */
  __IO uint32_t FETCHDECODE1_STATUS;               /**< Status informations., offset: 0x9870 */
  __I  uint32_t FETCHDECODE1_HIDDENSTATUS;         /**< Hidden status informations., offset: 0x9874 */
       uint8_t RESERVED_88[904];
  __IO uint32_t FETCHDECODE1_COLORPALETTE;         /**< Color palette look up table., offset: 0x9C00 */
       uint8_t RESERVED_89[1020];
  __I  uint32_t FETCHECO1_LOCKUNLOCK;              /**< Register to change the protection status of this address block., offset: 0xA000 */
  __I  uint32_t FETCHECO1_LOCKSTATUS;              /**< Protection status of this address block., offset: 0xA004 */
  __IO uint32_t FETCHECO1_STATICCONTROL;           /**< Common static control options., offset: 0xA008 */
  __IO uint32_t FETCHECO1_BURSTBUFFERMANAGEMENT;   /**< AXI interface buffer management register, offset: 0xA00C */
  __IO uint32_t FETCHECO1_BASEADDRESS0;            /**< Source buffer base address of layer 0., offset: 0xA010 */
  __IO uint32_t FETCHECO1_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0xA014 */
  __IO uint32_t FETCHECO1_SOURCEBUFFERDIMENSION0;  /**< Source buffer dimension of layer 0., offset: 0xA018 */
  __IO uint32_t FETCHECO1_COLORCOMPONENTBITS0;     /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0xA01C */
  __IO uint32_t FETCHECO1_COLORCOMPONENTSHIFT0;    /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0xA020 */
  __IO uint32_t FETCHECO1_LAYEROFFSET0;            /**< Position of layer 0 within the destination frame., offset: 0xA024 */
  __IO uint32_t FETCHECO1_CLIPWINDOWOFFSET0;       /**< Clip window position for layer 0., offset: 0xA028 */
  __IO uint32_t FETCHECO1_CLIPWINDOWDIMENSIONS0;   /**< Clip window size for layer 0., offset: 0xA02C */
  __IO uint32_t FETCHECO1_CONSTANTCOLOR0;          /**< Constant color for layer 0., offset: 0xA030 */
  __IO uint32_t FETCHECO1_LAYERPROPERTY0;          /**< Common properties of layer 0., offset: 0xA034 */
  __IO uint32_t FETCHECO1_FRAMEDIMENSIONS;         /**< Output frame dimension., offset: 0xA038 */
  __IO uint32_t FETCHECO1_FRAMERESAMPLING;         /**< Resampling options for output frame., offset: 0xA03C */
  __IO uint32_t FETCHECO1_CONTROL;                 /**< Shared common control settings for all layers., offset: 0xA040 */
  __O  uint32_t FETCHECO1_CONTROLTRIGGER;          /**< Shadow load trigger., offset: 0xA044 */
  __O  uint32_t FETCHECO1_START;                   /**< Frame start trigger., offset: 0xA048 */
  __I  uint32_t FETCHECO1_FETCHTYPE;               /**< Fetch unit type., offset: 0xA04C */
  __I  uint32_t FETCHECO1_BURSTBUFFERPROPERTIES;   /**< Burst buffer properties., offset: 0xA050 */
  __I  uint32_t FETCHECO1_HIDDENSTATUS;            /**< Hidden status informations., offset: 0xA054 */
       uint8_t RESERVED_90[936];
  __I  uint32_t FETCHLAYER0_LOCKUNLOCK;            /**< Register to change the protection status of this address block., offset: 0xA400 */
  __I  uint32_t FETCHLAYER0_LOCKSTATUS;            /**< Protection status of this address block., offset: 0xA404 */
  __IO uint32_t FETCHLAYER0_STATICCONTROL;         /**< Common static control options., offset: 0xA408 */
  __IO uint32_t FETCHLAYER0_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0xA40C */
  __IO uint32_t FETCHLAYER0_BASEADDRESS0;          /**< Source buffer base address of layer 0., offset: 0xA410 */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0xA414 */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0xA418 */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS0;   /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0xA41C */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT0;  /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0xA420 */
  __IO uint32_t FETCHLAYER0_LAYEROFFSET0;          /**< Position of layer 0 within the destination frame., offset: 0xA424 */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET0;     /**< Clip window position for layer 0., offset: 0xA428 */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0xA42C */
  __IO uint32_t FETCHLAYER0_CONSTANTCOLOR0;        /**< Constant color for layer 0., offset: 0xA430 */
  __IO uint32_t FETCHLAYER0_LAYERPROPERTY0;        /**< Common properties of layer 0., offset: 0xA434 */
  __IO uint32_t FETCHLAYER0_BASEADDRESS1;          /**< Source buffer base address of layer 1., offset: 0xA438 */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES1; /**< Source buffer attributes for layer 1., offset: 0xA43C */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION1; /**< Source buffer dimensions of layer 1,, offset: 0xA440 */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS1;   /**< Size of color components for RGB, YUV and index formats (layer 1)., offset: 0xA444 */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT1;  /**< Bit position of color components for RGB, YUV and index formats (layer 1)., offset: 0xA448 */
  __IO uint32_t FETCHLAYER0_LAYEROFFSET1;          /**< Position of layer 1 within the destination frame., offset: 0xA44C */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET1;     /**< Clip window position for layer 1., offset: 0xA450 */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS1; /**< Clip window size for layer 1., offset: 0xA454 */
  __IO uint32_t FETCHLAYER0_CONSTANTCOLOR1;        /**< Constant color for layer 1., offset: 0xA458 */
  __IO uint32_t FETCHLAYER0_LAYERPROPERTY1;        /**< Common properties of layer 1., offset: 0xA45C */
  __IO uint32_t FETCHLAYER0_BASEADDRESS2;          /**< Source buffer base address of layer 2., offset: 0xA460 */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES2; /**< Source buffer attributes for layer 2., offset: 0xA464 */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION2; /**< Source buffer dimension of layer 2., offset: 0xA468 */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS2;   /**< Size of color components for RGB, YUV and index formats (layer 2)., offset: 0xA46C */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT2;  /**< Bit position of color components for RGB, YUV and index formats (layer 2)., offset: 0xA470 */
  __IO uint32_t FETCHLAYER0_LAYEROFFSET2;          /**< Position of layer 2 within the destination frame., offset: 0xA474 */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET2;     /**< Clip window position for layer 2., offset: 0xA478 */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS2; /**< Clip window size for layer 2., offset: 0xA47C */
  __IO uint32_t FETCHLAYER0_CONSTANTCOLOR2;        /**< Constant color for layer 2., offset: 0xA480 */
  __IO uint32_t FETCHLAYER0_LAYERPROPERTY2;        /**< Common properties of layer 2., offset: 0xA484 */
  __IO uint32_t FETCHLAYER0_BASEADDRESS3;          /**< Source buffer base address of layer 3., offset: 0xA488 */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES3; /**< Source buffer attributes for layer 3., offset: 0xA48C */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION3; /**< Source buffer dimension of layer 3., offset: 0xA490 */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS3;   /**< Size of color components for RGB, YUV and index formats (layer 3)., offset: 0xA494 */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT3;  /**< Bit position of color components for RGB, YUV and index formats (layer 3)., offset: 0xA498 */
  __IO uint32_t FETCHLAYER0_LAYEROFFSET3;          /**< Position of layer 3 within the destination frame., offset: 0xA49C */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET3;     /**< Clip window position for layer 3., offset: 0xA4A0 */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS3; /**< Clip window size for layer 3., offset: 0xA4A4 */
  __IO uint32_t FETCHLAYER0_CONSTANTCOLOR3;        /**< Constant color for layer 3., offset: 0xA4A8 */
  __IO uint32_t FETCHLAYER0_LAYERPROPERTY3;        /**< Common properties of layer 3., offset: 0xA4AC */
  __IO uint32_t FETCHLAYER0_BASEADDRESS4;          /**< Source buffer base address of layer 4., offset: 0xA4B0 */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES4; /**< Source buffer attributes for layer 4., offset: 0xA4B4 */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION4; /**< Source buffer dimension of layer 4., offset: 0xA4B8 */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS4;   /**< Size of color components for RGB, YUV and index formats (layer 4)., offset: 0xA4BC */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT4;  /**< Bit position of color components for RGB, YUV and index formats (layer 4)., offset: 0xA4C0 */
  __IO uint32_t FETCHLAYER0_LAYEROFFSET4;          /**< Position of layer 4 within the destination frame., offset: 0xA4C4 */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET4;     /**< Clip window position for layer 4., offset: 0xA4C8 */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS4; /**< Clip window size for layer 4., offset: 0xA4CC */
  __IO uint32_t FETCHLAYER0_CONSTANTCOLOR4;        /**< Constant color for layer 4., offset: 0xA4D0 */
  __IO uint32_t FETCHLAYER0_LAYERPROPERTY4;        /**< Common properties of layer 4., offset: 0xA4D4 */
  __IO uint32_t FETCHLAYER0_BASEADDRESS5;          /**< Source buffer base address of layer 5., offset: 0xA4D8 */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES5; /**< Source buffer attributes for layer 5., offset: 0xA4DC */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION5; /**< Source buffer dimension of layer 5., offset: 0xA4E0 */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS5;   /**< Size of color components for RGB, YUV and index formats (layer 5)., offset: 0xA4E4 */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT5;  /**< Bit position of color components for RGB, YUV and index formats (layer 5)., offset: 0xA4E8 */
  __IO uint32_t FETCHLAYER0_LAYEROFFSET5;          /**< Position of layer 5 within the destination frame., offset: 0xA4EC */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET5;     /**< Clip window position for layer 5., offset: 0xA4F0 */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS5; /**< Clip window size for layer 5., offset: 0xA4F4 */
  __IO uint32_t FETCHLAYER0_CONSTANTCOLOR5;        /**< Constant color for layer 5., offset: 0xA4F8 */
  __IO uint32_t FETCHLAYER0_LAYERPROPERTY5;        /**< Common properties of layer 5., offset: 0xA4FC */
  __IO uint32_t FETCHLAYER0_BASEADDRESS6;          /**< Source buffer base address of layer 6., offset: 0xA500 */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES6; /**< Source buffer attributes for layer 6., offset: 0xA504 */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION6; /**< Source buffer dimension of layer 6., offset: 0xA508 */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS6;   /**< Size of color components for RGB, YUV and index formats (layer 6)., offset: 0xA50C */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT6;  /**< Bit position of color components for RGB, YUV and index formats (layer 6)., offset: 0xA510 */
  __IO uint32_t FETCHLAYER0_LAYEROFFSET6;          /**< Position of layer 1 within the destination frame., offset: 0xA514 */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET6;     /**< Clip window position for layer 6., offset: 0xA518 */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS6; /**< Clip window size for layer 6., offset: 0xA51C */
  __IO uint32_t FETCHLAYER0_CONSTANTCOLOR6;        /**< Constant color for layer 6., offset: 0xA520 */
  __IO uint32_t FETCHLAYER0_LAYERPROPERTY6;        /**< Common properties of layer 6., offset: 0xA524 */
  __IO uint32_t FETCHLAYER0_BASEADDRESS7;          /**< Source buffer base address of layer 7., offset: 0xA528 */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES7; /**< Source buffer stride for layer 7., offset: 0xA52C */
  __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION7; /**< Source buffer dimension of layer 7., offset: 0xA530 */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS7;   /**< Size of color components for RGB, YUV and index formats (layer 7)., offset: 0xA534 */
  __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT7;  /**< Bit position of color components for RGB, YUV and index formats (layer 7)., offset: 0xA538 */
  __IO uint32_t FETCHLAYER0_LAYEROFFSET7;          /**< Position of layer 7 within the destination frame., offset: 0xA53C */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET7;     /**< Clip window position for layer 7., offset: 0xA540 */
  __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS7; /**< Clip window size for layer 7., offset: 0xA544 */
  __IO uint32_t FETCHLAYER0_CONSTANTCOLOR7;        /**< Constant color for layer 7., offset: 0xA548 */
  __IO uint32_t FETCHLAYER0_LAYERPROPERTY7;        /**< Common properties of layer 7., offset: 0xA54C */
  __IO uint32_t FETCHLAYER0_FRAMEDIMENSIONS;       /**< Output frame dimension., offset: 0xA550 */
  __IO uint32_t FETCHLAYER0_FRAMERESAMPLING;       /**< Resampling options for output frame., offset: 0xA554 */
  __IO uint32_t FETCHLAYER0_CONTROL;               /**< Shared common control settings for all layers., offset: 0xA558 */
  __I  uint32_t FETCHLAYER0_TRIGGERENABLE;         /**< Shadow load enable flags for all layers., offset: 0xA55C */
  __O  uint32_t FETCHLAYER0_CONTROLTRIGGER;        /**< Shadow load trigger., offset: 0xA560 */
  __O  uint32_t FETCHLAYER0_START;                 /**< Frame start trigger., offset: 0xA564 */
  __I  uint32_t FETCHLAYER0_FETCHTYPE;             /**< Fetch unit type., offset: 0xA568 */
  __I  uint32_t FETCHLAYER0_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0xA56C */
  __IO uint32_t FETCHLAYER0_STATUS;                /**< Status informations., offset: 0xA570 */
  __I  uint32_t FETCHLAYER0_HIDDENSTATUS;          /**< Hidden status informations., offset: 0xA574 */
       uint8_t RESERVED_91[648];
  __IO uint32_t FETCHLAYER0_COLORPALETTE;          /**< Color palette look up table., offset: 0xA800 */
       uint8_t RESERVED_92[1020];
  __I  uint32_t FETCHLAYER1_LOCKUNLOCK;            /**< Register to change the protection status of this address block., offset: 0xAC00 */
  __I  uint32_t FETCHLAYER1_LOCKSTATUS;            /**< Protection status of this address block., offset: 0xAC04 */
  __IO uint32_t FETCHLAYER1_STATICCONTROL;         /**< Common static control options., offset: 0xAC08 */
  __IO uint32_t FETCHLAYER1_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0xAC0C */
  __IO uint32_t FETCHLAYER1_BASEADDRESS0;          /**< Source buffer base address of layer 0., offset: 0xAC10 */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0xAC14 */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0xAC18 */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTBITS0;   /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0xAC1C */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTSHIFT0;  /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0xAC20 */
  __IO uint32_t FETCHLAYER1_LAYEROFFSET0;          /**< Position of layer 0 within the destination frame., offset: 0xAC24 */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWOFFSET0;     /**< Clip window position for layer 0., offset: 0xAC28 */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0xAC2C */
  __IO uint32_t FETCHLAYER1_CONSTANTCOLOR0;        /**< Constant color for layer 0., offset: 0xAC30 */
  __IO uint32_t FETCHLAYER1_LAYERPROPERTY0;        /**< Common properties of layer 0., offset: 0xAC34 */
  __IO uint32_t FETCHLAYER1_BASEADDRESS1;          /**< Source buffer base address of layer 1., offset: 0xAC38 */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERATTRIBUTES1; /**< Source buffer attributes for layer 1., offset: 0xAC3C */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERDIMENSION1; /**< Source buffer dimensions of layer 1,, offset: 0xAC40 */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTBITS1;   /**< Size of color components for RGB, YUV and index formats (layer 1)., offset: 0xAC44 */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTSHIFT1;  /**< Bit position of color components for RGB, YUV and index formats (layer 1)., offset: 0xAC48 */
  __IO uint32_t FETCHLAYER1_LAYEROFFSET1;          /**< Position of layer 1 within the destination frame., offset: 0xAC4C */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWOFFSET1;     /**< Clip window position for layer 1., offset: 0xAC50 */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWDIMENSIONS1; /**< Clip window size for layer 1., offset: 0xAC54 */
  __IO uint32_t FETCHLAYER1_CONSTANTCOLOR1;        /**< Constant color for layer 1., offset: 0xAC58 */
  __IO uint32_t FETCHLAYER1_LAYERPROPERTY1;        /**< Common properties of layer 1., offset: 0xAC5C */
  __IO uint32_t FETCHLAYER1_BASEADDRESS2;          /**< Source buffer base address of layer 2., offset: 0xAC60 */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERATTRIBUTES2; /**< Source buffer attributes for layer 2., offset: 0xAC64 */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERDIMENSION2; /**< Source buffer dimension of layer 2., offset: 0xAC68 */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTBITS2;   /**< Size of color components for RGB, YUV and index formats (layer 2)., offset: 0xAC6C */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTSHIFT2;  /**< Bit position of color components for RGB, YUV and index formats (layer 2)., offset: 0xAC70 */
  __IO uint32_t FETCHLAYER1_LAYEROFFSET2;          /**< Position of layer 2 within the destination frame., offset: 0xAC74 */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWOFFSET2;     /**< Clip window position for layer 2., offset: 0xAC78 */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWDIMENSIONS2; /**< Clip window size for layer 2., offset: 0xAC7C */
  __IO uint32_t FETCHLAYER1_CONSTANTCOLOR2;        /**< Constant color for layer 2., offset: 0xAC80 */
  __IO uint32_t FETCHLAYER1_LAYERPROPERTY2;        /**< Common properties of layer 2., offset: 0xAC84 */
  __IO uint32_t FETCHLAYER1_BASEADDRESS3;          /**< Source buffer base address of layer 3., offset: 0xAC88 */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERATTRIBUTES3; /**< Source buffer attributes for layer 3., offset: 0xAC8C */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERDIMENSION3; /**< Source buffer dimension of layer 3., offset: 0xAC90 */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTBITS3;   /**< Size of color components for RGB, YUV and index formats (layer 3)., offset: 0xAC94 */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTSHIFT3;  /**< Bit position of color components for RGB, YUV and index formats (layer 3)., offset: 0xAC98 */
  __IO uint32_t FETCHLAYER1_LAYEROFFSET3;          /**< Position of layer 3 within the destination frame., offset: 0xAC9C */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWOFFSET3;     /**< Clip window position for layer 3., offset: 0xACA0 */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWDIMENSIONS3; /**< Clip window size for layer 3., offset: 0xACA4 */
  __IO uint32_t FETCHLAYER1_CONSTANTCOLOR3;        /**< Constant color for layer 3., offset: 0xACA8 */
  __IO uint32_t FETCHLAYER1_LAYERPROPERTY3;        /**< Common properties of layer 3., offset: 0xACAC */
  __IO uint32_t FETCHLAYER1_BASEADDRESS4;          /**< Source buffer base address of layer 4., offset: 0xACB0 */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERATTRIBUTES4; /**< Source buffer attributes for layer 4., offset: 0xACB4 */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERDIMENSION4; /**< Source buffer dimension of layer 4., offset: 0xACB8 */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTBITS4;   /**< Size of color components for RGB, YUV and index formats (layer 4)., offset: 0xACBC */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTSHIFT4;  /**< Bit position of color components for RGB, YUV and index formats (layer 4)., offset: 0xACC0 */
  __IO uint32_t FETCHLAYER1_LAYEROFFSET4;          /**< Position of layer 4 within the destination frame., offset: 0xACC4 */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWOFFSET4;     /**< Clip window position for layer 4., offset: 0xACC8 */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWDIMENSIONS4; /**< Clip window size for layer 4., offset: 0xACCC */
  __IO uint32_t FETCHLAYER1_CONSTANTCOLOR4;        /**< Constant color for layer 4., offset: 0xACD0 */
  __IO uint32_t FETCHLAYER1_LAYERPROPERTY4;        /**< Common properties of layer 4., offset: 0xACD4 */
  __IO uint32_t FETCHLAYER1_BASEADDRESS5;          /**< Source buffer base address of layer 5., offset: 0xACD8 */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERATTRIBUTES5; /**< Source buffer attributes for layer 5., offset: 0xACDC */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERDIMENSION5; /**< Source buffer dimension of layer 5., offset: 0xACE0 */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTBITS5;   /**< Size of color components for RGB, YUV and index formats (layer 5)., offset: 0xACE4 */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTSHIFT5;  /**< Bit position of color components for RGB, YUV and index formats (layer 5)., offset: 0xACE8 */
  __IO uint32_t FETCHLAYER1_LAYEROFFSET5;          /**< Position of layer 5 within the destination frame., offset: 0xACEC */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWOFFSET5;     /**< Clip window position for layer 5., offset: 0xACF0 */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWDIMENSIONS5; /**< Clip window size for layer 5., offset: 0xACF4 */
  __IO uint32_t FETCHLAYER1_CONSTANTCOLOR5;        /**< Constant color for layer 5., offset: 0xACF8 */
  __IO uint32_t FETCHLAYER1_LAYERPROPERTY5;        /**< Common properties of layer 5., offset: 0xACFC */
  __IO uint32_t FETCHLAYER1_BASEADDRESS6;          /**< Source buffer base address of layer 6., offset: 0xAD00 */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERATTRIBUTES6; /**< Source buffer attributes for layer 6., offset: 0xAD04 */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERDIMENSION6; /**< Source buffer dimension of layer 6., offset: 0xAD08 */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTBITS6;   /**< Size of color components for RGB, YUV and index formats (layer 6)., offset: 0xAD0C */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTSHIFT6;  /**< Bit position of color components for RGB, YUV and index formats (layer 6)., offset: 0xAD10 */
  __IO uint32_t FETCHLAYER1_LAYEROFFSET6;          /**< Position of layer 1 within the destination frame., offset: 0xAD14 */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWOFFSET6;     /**< Clip window position for layer 6., offset: 0xAD18 */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWDIMENSIONS6; /**< Clip window size for layer 6., offset: 0xAD1C */
  __IO uint32_t FETCHLAYER1_CONSTANTCOLOR6;        /**< Constant color for layer 6., offset: 0xAD20 */
  __IO uint32_t FETCHLAYER1_LAYERPROPERTY6;        /**< Common properties of layer 6., offset: 0xAD24 */
  __IO uint32_t FETCHLAYER1_BASEADDRESS7;          /**< Source buffer base address of layer 7., offset: 0xAD28 */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERATTRIBUTES7; /**< Source buffer stride for layer 7., offset: 0xAD2C */
  __IO uint32_t FETCHLAYER1_SOURCEBUFFERDIMENSION7; /**< Source buffer dimension of layer 7., offset: 0xAD30 */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTBITS7;   /**< Size of color components for RGB, YUV and index formats (layer 7)., offset: 0xAD34 */
  __IO uint32_t FETCHLAYER1_COLORCOMPONENTSHIFT7;  /**< Bit position of color components for RGB, YUV and index formats (layer 7)., offset: 0xAD38 */
  __IO uint32_t FETCHLAYER1_LAYEROFFSET7;          /**< Position of layer 7 within the destination frame., offset: 0xAD3C */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWOFFSET7;     /**< Clip window position for layer 7., offset: 0xAD40 */
  __IO uint32_t FETCHLAYER1_CLIPWINDOWDIMENSIONS7; /**< Clip window size for layer 7., offset: 0xAD44 */
  __IO uint32_t FETCHLAYER1_CONSTANTCOLOR7;        /**< Constant color for layer 7., offset: 0xAD48 */
  __IO uint32_t FETCHLAYER1_LAYERPROPERTY7;        /**< Common properties of layer 7., offset: 0xAD4C */
  __IO uint32_t FETCHLAYER1_FRAMEDIMENSIONS;       /**< Output frame dimension., offset: 0xAD50 */
  __IO uint32_t FETCHLAYER1_FRAMERESAMPLING;       /**< Resampling options for output frame., offset: 0xAD54 */
  __IO uint32_t FETCHLAYER1_CONTROL;               /**< Shared common control settings for all layers., offset: 0xAD58 */
  __I  uint32_t FETCHLAYER1_TRIGGERENABLE;         /**< Shadow load enable flags for all layers., offset: 0xAD5C */
  __O  uint32_t FETCHLAYER1_CONTROLTRIGGER;        /**< Shadow load trigger., offset: 0xAD60 */
  __O  uint32_t FETCHLAYER1_START;                 /**< Frame start trigger., offset: 0xAD64 */
  __I  uint32_t FETCHLAYER1_FETCHTYPE;             /**< Fetch unit type., offset: 0xAD68 */
  __I  uint32_t FETCHLAYER1_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0xAD6C */
  __IO uint32_t FETCHLAYER1_STATUS;                /**< Status informations., offset: 0xAD70 */
  __I  uint32_t FETCHLAYER1_HIDDENSTATUS;          /**< Hidden status informations., offset: 0xAD74 */
       uint8_t RESERVED_93[648];
  __IO uint32_t FETCHLAYER1_COLORPALETTE;          /**< Color palette look up table., offset: 0xB000 */
       uint8_t RESERVED_94[1020];
  __I  uint32_t GAMMACOR4_LOCKUNLOCK;              /**< Register to change the protection status of this address block., offset: 0xB400 */
  __I  uint32_t GAMMACOR4_LOCKSTATUS;              /**< Protection status of this address block., offset: 0xB404 */
  __IO uint32_t GAMMACOR4_STATICCONTROL;           /**< Static control settings., offset: 0xB408 */
  __I  uint32_t GAMMACOR4_LUTSTART;                /**< Start values for look-up table programming., offset: 0xB40C */
  __I  uint32_t GAMMACOR4_LUTDELTAS;               /**< Delta values for look-up table programming., offset: 0xB410 */
  __IO uint32_t GAMMACOR4_CONTROL;                 /**< Dynamic control settings., offset: 0xB414 */
  __IO uint32_t GAMMACOR4_STATUS;                  /**< Internal status bits., offset: 0xB418 */
  __I  uint32_t GAMMACOR4_LASTCONTROLWORD;         /**< Value of last received control word., offset: 0xB41C */
       uint8_t RESERVED_95[992];
  __I  uint32_t MATRIX4_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0xB800 */
  __I  uint32_t MATRIX4_LOCKSTATUS;                /**< Protection status of this address block., offset: 0xB804 */
  __IO uint32_t MATRIX4_STATICCONTROL;             /**< Color Matrix static control register, offset: 0xB808 */
  __IO uint32_t MATRIX4_CONTROL;                   /**< Color Matrix control register, offset: 0xB80C */
  __IO uint32_t MATRIX4_RED0;                      /**< Matrix values for calculation of the red output value., offset: 0xB810 */
  __IO uint32_t MATRIX4_RED1;                      /**< Matrix values for calculation of the red output value., offset: 0xB814 */
  __IO uint32_t MATRIX4_GREEN0;                    /**< Matrix values for calculation of the green output value., offset: 0xB818 */
  __IO uint32_t MATRIX4_GREEN1;                    /**< Matrix values for calculation of the green output value., offset: 0xB81C */
  __IO uint32_t MATRIX4_BLUE0;                     /**< Matrix values for calculation of the blue output value., offset: 0xB820 */
  __IO uint32_t MATRIX4_BLUE1;                     /**< Matrix values for calculation of the blue output value., offset: 0xB824 */
  __IO uint32_t MATRIX4_ALPHA0;                    /**< Matrix values for calculation of the alpha output value., offset: 0xB828 */
  __IO uint32_t MATRIX4_ALPHA1;                    /**< Matrix values for calculation of the alpha output value., offset: 0xB82C */
  __IO uint32_t MATRIX4_OFFSETVECTOR0;             /**< Offset vectors for red and green output., offset: 0xB830 */
  __IO uint32_t MATRIX4_OFFSETVECTOR1;             /**< Offset vectors for blue and alpha output., offset: 0xB834 */
  __I  uint32_t MATRIX4_LASTCONTROLWORD;           /**< Value of last received control word, for debugging., offset: 0xB838 */
       uint8_t RESERVED_96[964];
  __I  uint32_t HSCALER4_LOCKUNLOCK;               /**< Register to change the protection status of this address block., offset: 0xBC00 */
  __I  uint32_t HSCALER4_LOCKSTATUS;               /**< Protection status of this address block., offset: 0xBC04 */
  __IO uint32_t HSCALER4_STATICCONTROL;            /**< Static control settings that must typically be setup once only., offset: 0xBC08 */
  __IO uint32_t HSCALER4_SETUP1;                   /**< Phase interpolator setup., offset: 0xBC0C */
  __IO uint32_t HSCALER4_SETUP2;                   /**< Phase interpolator setup., offset: 0xBC10 */
  __IO uint32_t HSCALER4_CONTROL;                  /**< Scaler operation control., offset: 0xBC14 */
       uint8_t RESERVED_97[1000];
  __I  uint32_t VSCALER4_LOCKUNLOCK;               /**< Register to change the protection status of this address block., offset: 0xC000 */
  __I  uint32_t VSCALER4_LOCKSTATUS;               /**< Protection status of this address block., offset: 0xC004 */
  __IO uint32_t VSCALER4_STATICCONTROL;            /**< Static control settings that must typically be setup once only., offset: 0xC008 */
  __IO uint32_t VSCALER4_SETUP1;                   /**< Phase interpolator setup., offset: 0xC00C */
  __IO uint32_t VSCALER4_SETUP2;                   /**< Phase interpolator setup, selected if input and output field polarity is 0., offset: 0xC010 */
  __IO uint32_t VSCALER4_SETUP3;                   /**< Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0., offset: 0xC014 */
  __IO uint32_t VSCALER4_SETUP4;                   /**< Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1., offset: 0xC018 */
  __IO uint32_t VSCALER4_SETUP5;                   /**< Phase interpolator setup, selected if input and output field polarity is 1., offset: 0xC01C */
  __IO uint32_t VSCALER4_CONTROL;                  /**< Scaler operation control., offset: 0xC020 */
       uint8_t RESERVED_98[988];
  __IO uint32_t HISTOGRAM4_CONTROL;                /**< Controls some settings concerning input components and alpha mask., offset: 0xC400 */
  __IO uint32_t HISTOGRAM4_BINPROPERTIES;          /**< Configures the histogram bins., offset: 0xC404 */
  __IO uint32_t HISTOGRAM4_BINCNTTHRESH;           /**< Bin counter threshold value., offset: 0xC408 */
  __IO uint32_t HISTOGRAM4_CLIPWINUPPERLEFT;       /**< Coordinates of upper left corner of clip window., offset: 0xC40C */
  __IO uint32_t HISTOGRAM4_CLIPWINSIZE;            /**< Dimensions of clip window., offset: 0xC410 */
  __I  uint32_t HISTOGRAM4_RSLTRDY;                /**< Measurement result status., offset: 0xC414 */
  __I  uint32_t HISTOGRAM4_RSLTFRMINF;             /**< Additional information on the measurement results., offset: 0xC418 */
  __I  uint32_t HISTOGRAM4_RSLTCOMP0BINIDX;        /**< Results of frame measurement for component 0., offset: 0xC41C */
  __I  uint32_t HISTOGRAM4_RSLTCOMP1BINIDX;        /**< Results of frame measurement for component 1., offset: 0xC420 */
  __I  uint32_t HISTOGRAM4_RSLTCOMP2BINIDX;        /**< Results of frame measurement for component 2., offset: 0xC424 */
  __I  uint32_t HISTOGRAM4_RSLTCOMP0SUM;           /**< Sum of all component 0 values., offset: 0xC428 */
  __I  uint32_t HISTOGRAM4_RSLTCOMP1SUM;           /**< Sum of all component 1 values., offset: 0xC42C */
  __I  uint32_t HISTOGRAM4_RSLTCOMP2SUM;           /**< Sum of all component 2 values., offset: 0xC430 */
  __I  uint32_t HISTOGRAM4_RSLTCOMP0BINCNT;        /**< Bin counters of component 0 histogram., offset: 0xC434 */
  __I  uint32_t HISTOGRAM4_RSLTCOMP1BINCNT;        /**< Bin counters of component 1 histogram., offset: 0xC438 */
  __I  uint32_t HISTOGRAM4_RSLTCOMP2BINCNT;        /**< Bin counters of component 2 histogram., offset: 0xC43C */
  __O  uint32_t HISTOGRAM4_FRMSTRTTRIG;            /**< Triggers for loading shadow registers and starting measurement with next input frame., offset: 0xC440 */
       uint8_t RESERVED_99[956];
  __I  uint32_t GAMMACOR5_LOCKUNLOCK;              /**< Register to change the protection status of this address block., offset: 0xC800 */
  __I  uint32_t GAMMACOR5_LOCKSTATUS;              /**< Protection status of this address block., offset: 0xC804 */
  __IO uint32_t GAMMACOR5_STATICCONTROL;           /**< Static control settings., offset: 0xC808 */
  __I  uint32_t GAMMACOR5_LUTSTART;                /**< Start values for look-up table programming., offset: 0xC80C */
  __I  uint32_t GAMMACOR5_LUTDELTAS;               /**< Delta values for look-up table programming., offset: 0xC810 */
  __IO uint32_t GAMMACOR5_CONTROL;                 /**< Dynamic control settings., offset: 0xC814 */
  __IO uint32_t GAMMACOR5_STATUS;                  /**< Internal status bits., offset: 0xC818 */
  __I  uint32_t GAMMACOR5_LASTCONTROLWORD;         /**< Value of last received control word., offset: 0xC81C */
       uint8_t RESERVED_100[992];
  __I  uint32_t MATRIX5_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0xCC00 */
  __I  uint32_t MATRIX5_LOCKSTATUS;                /**< Protection status of this address block., offset: 0xCC04 */
  __IO uint32_t MATRIX5_STATICCONTROL;             /**< Color Matrix static control register, offset: 0xCC08 */
  __IO uint32_t MATRIX5_CONTROL;                   /**< Color Matrix control register, offset: 0xCC0C */
  __IO uint32_t MATRIX5_RED0;                      /**< Matrix values for calculation of the red output value., offset: 0xCC10 */
  __IO uint32_t MATRIX5_RED1;                      /**< Matrix values for calculation of the red output value., offset: 0xCC14 */
  __IO uint32_t MATRIX5_GREEN0;                    /**< Matrix values for calculation of the green output value., offset: 0xCC18 */
  __IO uint32_t MATRIX5_GREEN1;                    /**< Matrix values for calculation of the green output value., offset: 0xCC1C */
  __IO uint32_t MATRIX5_BLUE0;                     /**< Matrix values for calculation of the blue output value., offset: 0xCC20 */
  __IO uint32_t MATRIX5_BLUE1;                     /**< Matrix values for calculation of the blue output value., offset: 0xCC24 */
  __IO uint32_t MATRIX5_ALPHA0;                    /**< Matrix values for calculation of the alpha output value., offset: 0xCC28 */
  __IO uint32_t MATRIX5_ALPHA1;                    /**< Matrix values for calculation of the alpha output value., offset: 0xCC2C */
  __IO uint32_t MATRIX5_OFFSETVECTOR0;             /**< Offset vectors for red and green output., offset: 0xCC30 */
  __IO uint32_t MATRIX5_OFFSETVECTOR1;             /**< Offset vectors for blue and alpha output., offset: 0xCC34 */
  __I  uint32_t MATRIX5_LASTCONTROLWORD;           /**< Value of last received control word, for debugging., offset: 0xCC38 */
       uint8_t RESERVED_101[964];
  __I  uint32_t HSCALER5_LOCKUNLOCK;               /**< Register to change the protection status of this address block., offset: 0xD000 */
  __I  uint32_t HSCALER5_LOCKSTATUS;               /**< Protection status of this address block., offset: 0xD004 */
  __IO uint32_t HSCALER5_STATICCONTROL;            /**< Static control settings that must typically be setup once only., offset: 0xD008 */
  __IO uint32_t HSCALER5_SETUP1;                   /**< Phase interpolator setup., offset: 0xD00C */
  __IO uint32_t HSCALER5_SETUP2;                   /**< Phase interpolator setup., offset: 0xD010 */
  __IO uint32_t HSCALER5_CONTROL;                  /**< Scaler operation control., offset: 0xD014 */
       uint8_t RESERVED_102[1000];
  __I  uint32_t VSCALER5_LOCKUNLOCK;               /**< Register to change the protection status of this address block., offset: 0xD400 */
  __I  uint32_t VSCALER5_LOCKSTATUS;               /**< Protection status of this address block., offset: 0xD404 */
  __IO uint32_t VSCALER5_STATICCONTROL;            /**< Static control settings that must typically be setup once only., offset: 0xD408 */
  __IO uint32_t VSCALER5_SETUP1;                   /**< Phase interpolator setup., offset: 0xD40C */
  __IO uint32_t VSCALER5_SETUP2;                   /**< Phase interpolator setup, selected if input and output field polarity is 0., offset: 0xD410 */
  __IO uint32_t VSCALER5_SETUP3;                   /**< Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0., offset: 0xD414 */
  __IO uint32_t VSCALER5_SETUP4;                   /**< Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1., offset: 0xD418 */
  __IO uint32_t VSCALER5_SETUP5;                   /**< Phase interpolator setup, selected if input and output field polarity is 1., offset: 0xD41C */
  __IO uint32_t VSCALER5_CONTROL;                  /**< Scaler operation control., offset: 0xD420 */
       uint8_t RESERVED_103[988];
  __IO uint32_t HISTOGRAM5_CONTROL;                /**< Controls some settings concerning input components and alpha mask., offset: 0xD800 */
  __IO uint32_t HISTOGRAM5_BINPROPERTIES;          /**< Configures the histogram bins., offset: 0xD804 */
  __IO uint32_t HISTOGRAM5_BINCNTTHRESH;           /**< Bin counter threshold value., offset: 0xD808 */
  __IO uint32_t HISTOGRAM5_CLIPWINUPPERLEFT;       /**< Coordinates of upper left corner of clip window., offset: 0xD80C */
  __IO uint32_t HISTOGRAM5_CLIPWINSIZE;            /**< Dimensions of clip window., offset: 0xD810 */
  __I  uint32_t HISTOGRAM5_RSLTRDY;                /**< Measurement result status., offset: 0xD814 */
  __I  uint32_t HISTOGRAM5_RSLTFRMINF;             /**< Additional information on the measurement results., offset: 0xD818 */
  __I  uint32_t HISTOGRAM5_RSLTCOMP0BINIDX;        /**< Results of frame measurement for component 0., offset: 0xD81C */
  __I  uint32_t HISTOGRAM5_RSLTCOMP1BINIDX;        /**< Results of frame measurement for component 1., offset: 0xD820 */
  __I  uint32_t HISTOGRAM5_RSLTCOMP2BINIDX;        /**< Results of frame measurement for component 2., offset: 0xD824 */
  __I  uint32_t HISTOGRAM5_RSLTCOMP0SUM;           /**< Sum of all component 0 values., offset: 0xD828 */
  __I  uint32_t HISTOGRAM5_RSLTCOMP1SUM;           /**< Sum of all component 1 values., offset: 0xD82C */
  __I  uint32_t HISTOGRAM5_RSLTCOMP2SUM;           /**< Sum of all component 2 values., offset: 0xD830 */
  __I  uint32_t HISTOGRAM5_RSLTCOMP0BINCNT;        /**< Bin counters of component 0 histogram., offset: 0xD834 */
  __I  uint32_t HISTOGRAM5_RSLTCOMP1BINCNT;        /**< Bin counters of component 1 histogram., offset: 0xD838 */
  __I  uint32_t HISTOGRAM5_RSLTCOMP2BINCNT;        /**< Bin counters of component 2 histogram., offset: 0xD83C */
  __O  uint32_t HISTOGRAM5_FRMSTRTTRIG;            /**< Triggers for loading shadow registers and starting measurement with next input frame., offset: 0xD840 */
       uint8_t RESERVED_104[956];
  __I  uint32_t LAYERBLEND0_LOCKUNLOCK;            /**< Register to change the protection status of this address block., offset: 0xDC00 */
  __I  uint32_t LAYERBLEND0_LOCKSTATUS;            /**< Protection status of this address block., offset: 0xDC04 */
  __IO uint32_t LAYERBLEND0_STATICCONTROL;         /**< Static control settings., offset: 0xDC08 */
  __IO uint32_t LAYERBLEND0_CONTROL;               /**< Common control settings., offset: 0xDC0C */
  __IO uint32_t LAYERBLEND0_BLENDCONTROL;          /**< Options for blend operations, offset: 0xDC10 */
  __IO uint32_t LAYERBLEND0_POSITION;              /**< Position of secondary (overlay) input frame, offset: 0xDC14 */
  __I  uint32_t LAYERBLEND0_PRIMCONTROLWORD;       /**< Value of last received primary (background) control word, for debugging, offset: 0xDC18 */
  __I  uint32_t LAYERBLEND0_SECCONTROLWORD;        /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xDC1C */
       uint8_t RESERVED_105[992];
  __I  uint32_t LAYERBLEND1_LOCKUNLOCK;            /**< Register to change the protection status of this address block., offset: 0xE000 */
  __I  uint32_t LAYERBLEND1_LOCKSTATUS;            /**< Protection status of this address block., offset: 0xE004 */
  __IO uint32_t LAYERBLEND1_STATICCONTROL;         /**< Static control settings., offset: 0xE008 */
  __IO uint32_t LAYERBLEND1_CONTROL;               /**< Common control settings., offset: 0xE00C */
  __IO uint32_t LAYERBLEND1_BLENDCONTROL;          /**< Options for blend operations, offset: 0xE010 */
  __IO uint32_t LAYERBLEND1_POSITION;              /**< Position of secondary (overlay) input frame, offset: 0xE014 */
  __I  uint32_t LAYERBLEND1_PRIMCONTROLWORD;       /**< Value of last received primary (background) control word, for debugging, offset: 0xE018 */
  __I  uint32_t LAYERBLEND1_SECCONTROLWORD;        /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xE01C */
       uint8_t RESERVED_106[992];
  __I  uint32_t LAYERBLEND2_LOCKUNLOCK;            /**< Register to change the protection status of this address block., offset: 0xE400 */
  __I  uint32_t LAYERBLEND2_LOCKSTATUS;            /**< Protection status of this address block., offset: 0xE404 */
  __IO uint32_t LAYERBLEND2_STATICCONTROL;         /**< Static control settings., offset: 0xE408 */
  __IO uint32_t LAYERBLEND2_CONTROL;               /**< Common control settings., offset: 0xE40C */
  __IO uint32_t LAYERBLEND2_BLENDCONTROL;          /**< Options for blend operations, offset: 0xE410 */
  __IO uint32_t LAYERBLEND2_POSITION;              /**< Position of secondary (overlay) input frame, offset: 0xE414 */
  __I  uint32_t LAYERBLEND2_PRIMCONTROLWORD;       /**< Value of last received primary (background) control word, for debugging, offset: 0xE418 */
  __I  uint32_t LAYERBLEND2_SECCONTROLWORD;        /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xE41C */
       uint8_t RESERVED_107[992];
  __I  uint32_t LAYERBLEND3_LOCKUNLOCK;            /**< Register to change the protection status of this address block., offset: 0xE800 */
  __I  uint32_t LAYERBLEND3_LOCKSTATUS;            /**< Protection status of this address block., offset: 0xE804 */
  __IO uint32_t LAYERBLEND3_STATICCONTROL;         /**< Static control settings., offset: 0xE808 */
  __IO uint32_t LAYERBLEND3_CONTROL;               /**< Common control settings., offset: 0xE80C */
  __IO uint32_t LAYERBLEND3_BLENDCONTROL;          /**< Options for blend operations, offset: 0xE810 */
  __IO uint32_t LAYERBLEND3_POSITION;              /**< Position of secondary (overlay) input frame, offset: 0xE814 */
  __I  uint32_t LAYERBLEND3_PRIMCONTROLWORD;       /**< Value of last received primary (background) control word, for debugging, offset: 0xE818 */
  __I  uint32_t LAYERBLEND3_SECCONTROLWORD;        /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xE81C */
       uint8_t RESERVED_108[992];
  __I  uint32_t LAYERBLEND4_LOCKUNLOCK;            /**< Register to change the protection status of this address block., offset: 0xEC00 */
  __I  uint32_t LAYERBLEND4_LOCKSTATUS;            /**< Protection status of this address block., offset: 0xEC04 */
  __IO uint32_t LAYERBLEND4_STATICCONTROL;         /**< Static control settings., offset: 0xEC08 */
  __IO uint32_t LAYERBLEND4_CONTROL;               /**< Common control settings., offset: 0xEC0C */
  __IO uint32_t LAYERBLEND4_BLENDCONTROL;          /**< Options for blend operations, offset: 0xEC10 */
  __IO uint32_t LAYERBLEND4_POSITION;              /**< Position of secondary (overlay) input frame, offset: 0xEC14 */
  __I  uint32_t LAYERBLEND4_PRIMCONTROLWORD;       /**< Value of last received primary (background) control word, for debugging, offset: 0xEC18 */
  __I  uint32_t LAYERBLEND4_SECCONTROLWORD;        /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xEC1C */
       uint8_t RESERVED_109[992];
  __I  uint32_t LAYERBLEND5_LOCKUNLOCK;            /**< Register to change the protection status of this address block., offset: 0xF000 */
  __I  uint32_t LAYERBLEND5_LOCKSTATUS;            /**< Protection status of this address block., offset: 0xF004 */
  __IO uint32_t LAYERBLEND5_STATICCONTROL;         /**< Static control settings., offset: 0xF008 */
  __IO uint32_t LAYERBLEND5_CONTROL;               /**< Common control settings., offset: 0xF00C */
  __IO uint32_t LAYERBLEND5_BLENDCONTROL;          /**< Options for blend operations, offset: 0xF010 */
  __IO uint32_t LAYERBLEND5_POSITION;              /**< Position of secondary (overlay) input frame, offset: 0xF014 */
  __I  uint32_t LAYERBLEND5_PRIMCONTROLWORD;       /**< Value of last received primary (background) control word, for debugging, offset: 0xF018 */
  __I  uint32_t LAYERBLEND5_SECCONTROLWORD;        /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xF01C */
       uint8_t RESERVED_110[992];
  __I  uint32_t LAYERBLEND6_LOCKUNLOCK;            /**< Register to change the protection status of this address block., offset: 0xF400 */
  __I  uint32_t LAYERBLEND6_LOCKSTATUS;            /**< Protection status of this address block., offset: 0xF404 */
  __IO uint32_t LAYERBLEND6_STATICCONTROL;         /**< Static control settings., offset: 0xF408 */
  __IO uint32_t LAYERBLEND6_CONTROL;               /**< Common control settings., offset: 0xF40C */
  __IO uint32_t LAYERBLEND6_BLENDCONTROL;          /**< Options for blend operations, offset: 0xF410 */
  __IO uint32_t LAYERBLEND6_POSITION;              /**< Position of secondary (overlay) input frame, offset: 0xF414 */
  __I  uint32_t LAYERBLEND6_PRIMCONTROLWORD;       /**< Value of last received primary (background) control word, for debugging, offset: 0xF418 */
  __I  uint32_t LAYERBLEND6_SECCONTROLWORD;        /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xF41C */
       uint8_t RESERVED_111[992];
  __I  uint32_t EXTSRC0_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0xF800 */
  __I  uint32_t EXTSRC0_LOCKSTATUS;                /**< Protection status of this address block., offset: 0xF804 */
  __IO uint32_t EXTSRC0_STATICCONTROL;             /**< ExtSrc static control register, offset: 0xF808 */
  __IO uint32_t EXTSRC0_CLIPWINDOWOFFSET;          /**< Clip window offset, to generate a clipping of the frame. It has to be within the input frame., offset: 0xF80C */
  __IO uint32_t EXTSRC0_CLIPWINDOWDIMENSION;       /**< Define the clip window dimension. If the clip window feature is enabled this dimension is used for the new frame dimension. Note that the clip window has to be smaller or equal to the original frame dimensions. The new frame has to be within the active area of the original frame., offset: 0xF810 */
  __IO uint32_t EXTSRC0_COLORCOMPONENTBITS;        /**< Color component size of raw input data. Please note that the width must be equal or lower than the output width., offset: 0xF814 */
  __IO uint32_t EXTSRC0_COLORCOMPONENTSHIFT;       /**< Color component offset of raw input data., offset: 0xF818 */
  __IO uint32_t EXTSRC0_CONSTANTCOLOR;             /**< Constant color register, offset: 0xF81C */
  __IO uint32_t EXTSRC0_CONTROL;                   /**< Common control settings., offset: 0xF820 */
  __O  uint32_t EXTSRC0_CONTROLTRIGGER;            /**< ExtSrc unit trigger token generation, offset: 0xF824 */
  __O  uint32_t EXTSRC0_START;                     /**< ExtSrc unit start register, offset: 0xF828 */
  __I  uint32_t EXTSRC0_LASTCOMMANDWORD;           /**< Subset of last input command word with the following mapping: val[31:0]={data[37:22], data[19:12], data[9:2]}, offset: 0xF82C */
  __I  uint32_t EXTSRC0_STATUS;                    /**< Shows status information, offset: 0xF830 */
       uint8_t RESERVED_112[972];
  __I  uint32_t EXTSRC1_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0xFC00 */
  __I  uint32_t EXTSRC1_LOCKSTATUS;                /**< Protection status of this address block., offset: 0xFC04 */
  __IO uint32_t EXTSRC1_STATICCONTROL;             /**< ExtSrc static control register, offset: 0xFC08 */
  __IO uint32_t EXTSRC1_CLIPWINDOWOFFSET;          /**< Clip window offset, to generate a clipping of the frame. It has to be within the input frame., offset: 0xFC0C */
  __IO uint32_t EXTSRC1_CLIPWINDOWDIMENSION;       /**< Define the clip window dimension. If the clip window feature is enabled this dimension is used for the new frame dimension. Note that the clip window has to be smaller or equal to the original frame dimensions. The new frame has to be within the active area of the original frame., offset: 0xFC10 */
  __IO uint32_t EXTSRC1_COLORCOMPONENTBITS;        /**< Color component size of raw input data. Please note that the width must be equal or lower than the output width., offset: 0xFC14 */
  __IO uint32_t EXTSRC1_COLORCOMPONENTSHIFT;       /**< Color component offset of raw input data., offset: 0xFC18 */
  __IO uint32_t EXTSRC1_CONSTANTCOLOR;             /**< Constant color register, offset: 0xFC1C */
  __IO uint32_t EXTSRC1_CONTROL;                   /**< Common control settings., offset: 0xFC20 */
  __O  uint32_t EXTSRC1_CONTROLTRIGGER;            /**< ExtSrc unit trigger token generation, offset: 0xFC24 */
  __O  uint32_t EXTSRC1_START;                     /**< ExtSrc unit start register, offset: 0xFC28 */
  __I  uint32_t EXTSRC1_LASTCOMMANDWORD;           /**< Subset of last input command word with the following mapping: val[31:0]={data[37:22], data[19:12], data[9:2]}, offset: 0xFC2C */
  __I  uint32_t EXTSRC1_STATUS;                    /**< Shows status information, offset: 0xFC30 */
       uint8_t RESERVED_113[972];
  __I  uint32_t DISENGCFG_LOCKUNLOCK0;             /**< Register to change the protection status of this address block., offset: 0x10000 */
  __I  uint32_t DISENGCFG_LOCKSTATUS0;             /**< Protection status of this address block., offset: 0x10004 */
  __IO uint32_t DISENGCFG_CLOCKCTRL0;              /**< Controls generation of display clock signals for display stream 0., offset: 0x10008 */
  __IO uint32_t DISENGCFG_POLARITYCTRL0;           /**< Polarity control for TCon#0 input and corresponding top-level output (TCon by-pass port)., offset: 0x1000C */
  __IO uint32_t DISENGCFG_SRCSELECT0;              /**< Tap selection for Signature and Frame Dump (display stream 0)., offset: 0x10010 */
       uint8_t RESERVED_114[12];
  __I  uint32_t DISENGCFG_LOCKUNLOCK1;             /**< Register to change the protection status of this address block., offset: 0x10020 */
  __I  uint32_t DISENGCFG_LOCKSTATUS1;             /**< Protection status of this address block., offset: 0x10024 */
  __IO uint32_t DISENGCFG_CLOCKCTRL1;              /**< Controls generation of display clock signals for display stream 1., offset: 0x10028 */
  __IO uint32_t DISENGCFG_POLARITYCTRL1;           /**< Polarity control for TCon#1 input and corresponding top-level output (TCon by-pass port)., offset: 0x1002C */
  __IO uint32_t DISENGCFG_SRCSELECT1;              /**< Tap selection for Signature and Frame Dump (display stream 1)., offset: 0x10030 */
       uint8_t RESERVED_115[972];
  __IO uint32_t FRAMEDUMP0_CONTROL;                /**< Control settings., offset: 0x10400 */
  __IO uint32_t FRAMEDUMP0_FRAMESIZE;              /**< Dump window size., offset: 0x10404 */
  __IO uint32_t FRAMEDUMP0_INPUTSETUP;             /**< Dump window position., offset: 0x10408 */
  __IO uint32_t FRAMEDUMP0_ENABLE;                 /**< Enable register., offset: 0x1040C */
  __I  uint32_t FRAMEDUMP0_TRIGGER;                /**< Trigger bits., offset: 0x10410 */
  __I  uint32_t FRAMEDUMP0_STATUS;                 /**< Status register., offset: 0x10414 */
       uint8_t RESERVED_116[1000];
  __IO uint32_t FRAMEDUMP1_CONTROL;                /**< Control settings., offset: 0x10800 */
  __IO uint32_t FRAMEDUMP1_FRAMESIZE;              /**< Dump window size., offset: 0x10804 */
  __IO uint32_t FRAMEDUMP1_INPUTSETUP;             /**< Dump window position., offset: 0x10808 */
  __IO uint32_t FRAMEDUMP1_ENABLE;                 /**< Enable register., offset: 0x1080C */
  __I  uint32_t FRAMEDUMP1_TRIGGER;                /**< Trigger bits., offset: 0x10810 */
  __I  uint32_t FRAMEDUMP1_STATUS;                 /**< Status register., offset: 0x10814 */
       uint8_t RESERVED_117[1000];
  __I  uint32_t FRAMEGEN0_LOCKUNLOCK;              /**< Register to change the protection status of this address block., offset: 0x10C00 */
  __I  uint32_t FRAMEGEN0_LOCKSTATUS;              /**< Protection status of this address block., offset: 0x10C04 */
  __IO uint32_t FRAMEGEN0_FGSTCTRL;                /**< FrameGen Static Control Register, offset: 0x10C08 */
  __IO uint32_t FRAMEGEN0_HTCFG1;                  /**< FrameGen Horizontal Timing Config Register 1, offset: 0x10C0C */
  __IO uint32_t FRAMEGEN0_HTCFG2;                  /**< FrameGen Horizontal Timing Config Register 2, offset: 0x10C10 */
  __IO uint32_t FRAMEGEN0_VTCFG1;                  /**< FrameGen Vertical Timing Config Register 1, offset: 0x10C14 */
  __IO uint32_t FRAMEGEN0_VTCFG2;                  /**< FrameGen Vertical Timing Config Register 2, offset: 0x10C18 */
  __I  uint32_t FRAMEGEN0_INT0CONFIG;              /**< Coordinates of the trigger point for generation of the Int0 interrupt signal, offset: 0x10C1C */
  __I  uint32_t FRAMEGEN0_INT1CONFIG;              /**< Coordinates of the trigger point for generation of the Int1 interrupt signal, offset: 0x10C20 */
  __I  uint32_t FRAMEGEN0_INT2CONFIG;              /**< Coordinates of the trigger point for generation of the Int2 interrupt signal, offset: 0x10C24 */
  __I  uint32_t FRAMEGEN0_INT3CONFIG;              /**< Coordinates of the trigger point for generation of the Int3 interrupt signal, offset: 0x10C28 */
  __IO uint32_t FRAMEGEN0_PKICKCONFIG;             /**< Coordinates of the trigger point for generation of the primary kick signal, offset: 0x10C2C */
  __IO uint32_t FRAMEGEN0_SKICKCONFIG;             /**< Coordinates of the trigger point for generation of the secondary kick signal, offset: 0x10C30 */
  __IO uint32_t FRAMEGEN0_SECSTATCONFIG;           /**< Configuration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register., offset: 0x10C34 */
  __IO uint32_t FRAMEGEN0_FGSRCR1;                 /**< FrameGen Skew Regulation Control Register 1., offset: 0x10C38 */
  __IO uint32_t FRAMEGEN0_FGSRCR2;                 /**< FrameGen Skew Regulation Control Register 2, offset: 0x10C3C */
  __IO uint32_t FRAMEGEN0_FGSRCR3;                 /**< FrameGen Skew Regulation Control Register 3, offset: 0x10C40 */
  __IO uint32_t FRAMEGEN0_FGSRCR4;                 /**< FrameGen Skew Regulation Control Register 4, offset: 0x10C44 */
  __IO uint32_t FRAMEGEN0_FGSRCR5;                 /**< FrameGen Skew Regulation Control Register 5, offset: 0x10C48 */
  __IO uint32_t FRAMEGEN0_FGSRCR6;                 /**< FrameGen Skew Regulation Control Register 6, offset: 0x10C4C */
  __IO uint32_t FRAMEGEN0_FGKSDR;                  /**< FrameGen Kick System Debug Register, offset: 0x10C50 */
  __IO uint32_t FRAMEGEN0_PACFG;                   /**< FrameGen Primary Area Config Register 1 (shadowed), offset: 0x10C54 */
  __IO uint32_t FRAMEGEN0_SACFG;                   /**< FrameGen Secondary Area Config Register 1 (shadowed), offset: 0x10C58 */
  __IO uint32_t FRAMEGEN0_FGINCTRL;                /**< FrameGen Input Control Register (shadowed), offset: 0x10C5C */
  __IO uint32_t FRAMEGEN0_FGINCTRLPANIC;           /**< FrameGen Input Control Panic Register (shadowed), offset: 0x10C60 */
  __IO uint32_t FRAMEGEN0_FGCCR;                   /**< FrameGen Constant Color Register (shadowed), offset: 0x10C64 */
  __IO uint32_t FRAMEGEN0_FGENABLE;                /**< FrameGen Enable Register, offset: 0x10C68 */
  __O  uint32_t FRAMEGEN0_FGSLR;                   /**< FrameGen Shadow Load Register, offset: 0x10C6C */
  __I  uint32_t FRAMEGEN0_FGENSTS;                 /**< FrameGen Enable Status Register, offset: 0x10C70 */
  __I  uint32_t FRAMEGEN0_FGTIMESTAMP;             /**< Time stamp status., offset: 0x10C74 */
  __I  uint32_t FRAMEGEN0_FGCHSTAT;                /**< FrameGen Channel Status Register, offset: 0x10C78 */
  __O  uint32_t FRAMEGEN0_FGCHSTATCLR;             /**< FrameGen Channel Status Clear Register, offset: 0x10C7C */
  __I  uint32_t FRAMEGEN0_FGSKEWMON;               /**< FrameGen Skew Monitor Register for Secondary Channel Skew Control, offset: 0x10C80 */
  __I  uint32_t FRAMEGEN0_FGSFIFOMIN;              /**< FrameGen Secondary FIFO Min Fill Register, offset: 0x10C84 */
  __I  uint32_t FRAMEGEN0_FGSFIFOMAX;              /**< FrameGen Secondary FIFO Max Fill Register, offset: 0x10C88 */
  __O  uint32_t FRAMEGEN0_FGSFIFOFILLCLR;          /**< FrameGen Secondary FIFO Fill Clear Register, offset: 0x10C8C */
  __I  uint32_t FRAMEGEN0_FGSREPD;                 /**< FrameGen Skew Regulation ExtraPolation Debug Register, offset: 0x10C90 */
  __I  uint32_t FRAMEGEN0_FGSRFTD;                 /**< FrameGen Skew Regulation Frame Total Debug Register, offset: 0x10C94 */
       uint8_t RESERVED_118[872];
  __I  uint32_t MATRIX0_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0x11000 */
  __I  uint32_t MATRIX0_LOCKSTATUS;                /**< Protection status of this address block., offset: 0x11004 */
  __IO uint32_t MATRIX0_STATICCONTROL;             /**< Color Matrix static control register, offset: 0x11008 */
  __IO uint32_t MATRIX0_CONTROL;                   /**< Color Matrix control register, offset: 0x1100C */
  __IO uint32_t MATRIX0_RED0;                      /**< Matrix values for calculation of the red output value., offset: 0x11010 */
  __IO uint32_t MATRIX0_RED1;                      /**< Matrix values for calculation of the red output value., offset: 0x11014 */
  __IO uint32_t MATRIX0_GREEN0;                    /**< Matrix values for calculation of the green output value., offset: 0x11018 */
  __IO uint32_t MATRIX0_GREEN1;                    /**< Matrix values for calculation of the green output value., offset: 0x1101C */
  __IO uint32_t MATRIX0_BLUE0;                     /**< Matrix values for calculation of the blue output value., offset: 0x11020 */
  __IO uint32_t MATRIX0_BLUE1;                     /**< Matrix values for calculation of the blue output value., offset: 0x11024 */
  __IO uint32_t MATRIX0_ALPHA0;                    /**< Matrix values for calculation of the alpha output value., offset: 0x11028 */
  __IO uint32_t MATRIX0_ALPHA1;                    /**< Matrix values for calculation of the alpha output value., offset: 0x1102C */
  __IO uint32_t MATRIX0_OFFSETVECTOR0;             /**< Offset vectors for red and green output., offset: 0x11030 */
  __IO uint32_t MATRIX0_OFFSETVECTOR1;             /**< Offset vectors for blue and alpha output., offset: 0x11034 */
  __I  uint32_t MATRIX0_LASTCONTROLWORD;           /**< Value of last received control word, for debugging., offset: 0x11038 */
       uint8_t RESERVED_119[964];
  __I  uint32_t GAMMACOR0_LOCKUNLOCK;              /**< Register to change the protection status of this address block., offset: 0x11400 */
  __I  uint32_t GAMMACOR0_LOCKSTATUS;              /**< Protection status of this address block., offset: 0x11404 */
  __IO uint32_t GAMMACOR0_STATICCONTROL;           /**< Static control settings., offset: 0x11408 */
  __I  uint32_t GAMMACOR0_LUTSTART;                /**< Start values for look-up table programming., offset: 0x1140C */
  __I  uint32_t GAMMACOR0_LUTDELTAS;               /**< Delta values for look-up table programming., offset: 0x11410 */
  __IO uint32_t GAMMACOR0_CONTROL;                 /**< Dynamic control settings., offset: 0x11414 */
  __IO uint32_t GAMMACOR0_STATUS;                  /**< Internal status bits., offset: 0x11418 */
  __I  uint32_t GAMMACOR0_LASTCONTROLWORD;         /**< Value of last received control word., offset: 0x1141C */
       uint8_t RESERVED_120[992];
  __I  uint32_t DITHER0_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0x11800 */
  __I  uint32_t DITHER0_LOCKSTATUS;                /**< Protection status of this address block., offset: 0x11804 */
  __IO uint32_t DITHER0_CONTROL;                   /**< Dither Unit common control., offset: 0x11808 */
  __IO uint32_t DITHER0_DITHERCONTROL;             /**< Dither Unit processing control., offset: 0x1180C */
  __I  uint32_t DITHER0_RELEASE;                   /**< Dither Unit release., offset: 0x11810 */
       uint8_t RESERVED_121[1004];
  __I  uint32_t TCON0_SSQCNTS;                     /**< The 64 Sequencer Position Definitions registers define the X/Y scan positions of the sequencers, hold their output value and assign the sequencer to an odd/even field, offset: 0x11C00 */
       uint8_t RESERVED_122[1020];
  __I  uint32_t TCON0_LOCKUNLOCK;                  /**< Register to change the protection status of this address block., offset: 0x12000 */
  __I  uint32_t TCON0_LOCKSTATUS;                  /**< Protection status of this address block., offset: 0x12004 */
  __IO uint32_t TCON0_SSQCYCLE;                    /**< This bitfield sets the sequencer cycle length. The value set here -1 is the number of sequencer cycles, offset: 0x12008 */
  __IO uint32_t TCON0_SWRESET;                     /**< TCON Software Reset - Reset all tcon registers except configuration registers. Detailed description in specification document, offset: 0x1200C */
  __IO uint32_t TCON0_TCON_CTRL;                   /**< TCON Control register, offset: 0x12010 */
  __IO uint32_t TCON0_RSDSINVCTRL;                 /**< Controls inversion of output polarity when connected IO cells operate in RSDS mode, offset: 0x12014 */
  __IO uint32_t TCON0_MAPBIT3_0;                   /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3, offset: 0x12018 */
  __IO uint32_t TCON0_MAPBIT7_4;                   /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7, offset: 0x1201C */
  __IO uint32_t TCON0_MAPBIT11_8;                  /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11, offset: 0x12020 */
  __IO uint32_t TCON0_MAPBIT15_12;                 /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15, offset: 0x12024 */
  __IO uint32_t TCON0_MAPBIT19_16;                 /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19, offset: 0x12028 */
  __IO uint32_t TCON0_MAPBIT23_20;                 /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23, offset: 0x1202C */
  __IO uint32_t TCON0_MAPBIT27_24;                 /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27, offset: 0x12030 */
  __IO uint32_t TCON0_MAPBIT31_28;                 /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31, offset: 0x12034 */
  __IO uint32_t TCON0_MAPBIT34_32;                 /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34, offset: 0x12038 */
  __IO uint32_t TCON0_MAPBIT3_0_DUAL;              /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3 2nd channel, offset: 0x1203C */
  __IO uint32_t TCON0_MAPBIT7_4_DUAL;              /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7 2nd channel, offset: 0x12040 */
  __IO uint32_t TCON0_MAPBIT11_8_DUAL;             /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11 2nd channel, offset: 0x12044 */
  __IO uint32_t TCON0_MAPBIT15_12_DUAL;            /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15 2nd channel, offset: 0x12048 */
  __IO uint32_t TCON0_MAPBIT19_16_DUAL;            /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19 2nd channel, offset: 0x1204C */
  __IO uint32_t TCON0_MAPBIT23_20_DUAL;            /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23 2nd channel, offset: 0x12050 */
  __IO uint32_t TCON0_MAPBIT27_24_DUAL;            /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27 2nd channel, offset: 0x12054 */
  __IO uint32_t TCON0_MAPBIT31_28_DUAL;            /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31 2nd channel, offset: 0x12058 */
  __IO uint32_t TCON0_MAPBIT34_32_DUAL;            /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34 2nd channel, offset: 0x1205C */
  __IO uint32_t TCON0_SPG0POSON;                   /**< Sync pulse generator 0, 'Switch on' position, offset: 0x12060 */
  __IO uint32_t TCON0_SPG0MASKON;                  /**< The Sequencer Pulse Generator 0 Mask Enable register is used to mask the enable of SPG 0, offset: 0x12064 */
  __IO uint32_t TCON0_SPG0POSOFF;                  /**< Sync pulse generator 0, 'Switch off' position, offset: 0x12068 */
  __IO uint32_t TCON0_SPG0MASKOFF;                 /**< The Sequencer Pulse Generator 0 Mask Enable register is used to mask the disable of SPG 0, offset: 0x1206C */
  __IO uint32_t TCON0_SPG1POSON;                   /**< Sync pulse generator 1, 'Switch on' position, offset: 0x12070 */
  __IO uint32_t TCON0_SPG1MASKON;                  /**< The Sequencer Pulse Generator 1 Mask Enable register is used to mask the enable of SPG 1, offset: 0x12074 */
  __IO uint32_t TCON0_SPG1POSOFF;                  /**< Sync pulse generator 1, 'Switch off' position, offset: 0x12078 */
  __IO uint32_t TCON0_SPG1MASKOFF;                 /**< The Sequencer Pulse Generator 1 Mask Enable register is used to mask the disable of SPG 1, offset: 0x1207C */
  __IO uint32_t TCON0_SPG2POSON;                   /**< Sync pulse generator 2, 'Switch on' position, offset: 0x12080 */
  __IO uint32_t TCON0_SPG2MASKON;                  /**< The Sequencer Pulse Generator 2 Mask Enable register is used to mask the enable of SPG 2, offset: 0x12084 */
  __IO uint32_t TCON0_SPG2POSOFF;                  /**< Sync pulse generator 2, 'Switch off' position, offset: 0x12088 */
  __IO uint32_t TCON0_SPG2MASKOFF;                 /**< The Sequencer Pulse Generator 2 Mask Enable register is used to mask the disable of SPG 2, offset: 0x1208C */
  __IO uint32_t TCON0_SPG3POSON;                   /**< Sync pulse generator 3, 'Switch on' position, offset: 0x12090 */
  __IO uint32_t TCON0_SPG3MASKON;                  /**< The Sequencer Pulse Generator 3 Mask Enable register is used to mask the enable of SPG 3, offset: 0x12094 */
  __IO uint32_t TCON0_SPG3POSOFF;                  /**< Sync pulse generator 3, 'Switch off' position, offset: 0x12098 */
  __IO uint32_t TCON0_SPG3MASKOFF;                 /**< The Sequencer Pulse Generator 3 Mask Enable register is used to mask the disable of SPG 3, offset: 0x1209C */
  __IO uint32_t TCON0_SPG4POSON;                   /**< Sync pulse generator 4, 'Switch on' position, offset: 0x120A0 */
  __IO uint32_t TCON0_SPG4MASKON;                  /**< The Sequencer Pulse Generator 4 Mask Enable register is used to mask the enable of SPG 4, offset: 0x120A4 */
  __IO uint32_t TCON0_SPG4POSOFF;                  /**< Sync pulse generator 4, 'Switch off' position, offset: 0x120A8 */
  __IO uint32_t TCON0_SPG4MASKOFF;                 /**< The Sequencer Pulse Generator 4 Mask Enable register is used to mask the disable of SPG 4, offset: 0x120AC */
  __IO uint32_t TCON0_SPG5POSON;                   /**< Sync pulse generator 5, 'Switch on' position, offset: 0x120B0 */
  __IO uint32_t TCON0_SPG5MASKON;                  /**< The Sequencer Pulse Generator 5 Mask Enable register is used to mask the enable of SPG 5, offset: 0x120B4 */
  __IO uint32_t TCON0_SPG5POSOFF;                  /**< Sync pulse generator 5, 'Switch off' position, offset: 0x120B8 */
  __IO uint32_t TCON0_SPG5MASKOFF;                 /**< The Sequencer Pulse Generator 5 Mask Enable register is used to mask the disable of SPG 5, offset: 0x120BC */
  __IO uint32_t TCON0_SPG6POSON;                   /**< Sync pulse generator 6, 'Switch on' position, offset: 0x120C0 */
  __IO uint32_t TCON0_SPG6MASKON;                  /**< The Sequencer Pulse Generator 6 Mask Enable register is used to mask the enable of SPG 6, offset: 0x120C4 */
  __IO uint32_t TCON0_SPG6POSOFF;                  /**< Sync pulse generator 6, 'Switch off' position, offset: 0x120C8 */
  __IO uint32_t TCON0_SPG6MASKOFF;                 /**< The Sequencer Pulse Generator 6 Mask Enable register is used to mask the disable of SPG 6, offset: 0x120CC */
  __IO uint32_t TCON0_SPG7POSON;                   /**< Sync pulse generator 7, 'Switch on' position, offset: 0x120D0 */
  __IO uint32_t TCON0_SPG7MASKON;                  /**< The Sequencer Pulse Generator 7 Mask Enable register is used to mask the enable of SPG 7, offset: 0x120D4 */
  __IO uint32_t TCON0_SPG7POSOFF;                  /**< Sync pulse generator 7, 'Switch off' position, offset: 0x120D8 */
  __IO uint32_t TCON0_SPG7MASKOFF;                 /**< The Sequencer Pulse Generator 7 Mask Enable register is used to mask the disable of SPG 7, offset: 0x120DC */
  __IO uint32_t TCON0_SPG8POSON;                   /**< Sync pulse generator 8, 'Switch on' position, offset: 0x120E0 */
  __IO uint32_t TCON0_SPG8MASKON;                  /**< The Sequencer Pulse Generator 8 Mask Enable register is used to mask the enable of SPG 8, offset: 0x120E4 */
  __IO uint32_t TCON0_SPG8POSOFF;                  /**< Sync pulse generator 8, 'Switch off' position, offset: 0x120E8 */
  __IO uint32_t TCON0_SPG8MASKOFF;                 /**< The Sequencer Pulse Generator 8 Mask Enable register is used to mask the disable of SPG 8, offset: 0x120EC */
  __IO uint32_t TCON0_SPG9POSON;                   /**< Sync pulse generator 9, 'Switch on' position, offset: 0x120F0 */
  __IO uint32_t TCON0_SPG9MASKON;                  /**< The Sequencer Pulse Generator 9 Mask Enable register is used to mask the enable of SPG 9, offset: 0x120F4 */
  __IO uint32_t TCON0_SPG9POSOFF;                  /**< Sync pulse generator 9, 'Switch off' position, offset: 0x120F8 */
  __IO uint32_t TCON0_SPG9MASKOFF;                 /**< The Sequencer Pulse Generator 9 Mask Enable register is used to mask the disable of SPG 9, offset: 0x120FC */
  __IO uint32_t TCON0_SPG10POSON;                  /**< Sync pulse generator 10, 'Switch on' position, offset: 0x12100 */
  __IO uint32_t TCON0_SPG10MASKON;                 /**< The Sequencer Pulse Generator 10 Mask Enable register is used to mask the enable of SPG 10, offset: 0x12104 */
  __IO uint32_t TCON0_SPG10POSOFF;                 /**< Sync pulse generator 10, 'Switch off' position, offset: 0x12108 */
  __IO uint32_t TCON0_SPG10MASKOFF;                /**< The Sequencer Pulse Generator 10 Mask Enable register is used to mask the disable of SPG 10, offset: 0x1210C */
  __IO uint32_t TCON0_SPG11POSON;                  /**< Sync pulse generator 11, 'Switch on' position, offset: 0x12110 */
  __IO uint32_t TCON0_SPG11MASKON;                 /**< The Sequencer Pulse Generator 11 Mask Enable register is used to mask the enable of SPG 11, offset: 0x12114 */
  __IO uint32_t TCON0_SPG11POSOFF;                 /**< Sync pulse generator 11, 'Switch off' position, offset: 0x12118 */
  __IO uint32_t TCON0_SPG11MASKOFF;                /**< The Sequencer Pulse Generator 11 Mask Enable register is used to mask the disable of SPG 11, offset: 0x1211C */
  __IO uint32_t TCON0_SMX0SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x12120 */
  __IO uint32_t TCON0_SMX0FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x12124 */
  __IO uint32_t TCON0_SMX1SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x12128 */
  __IO uint32_t TCON0_SMX1FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x1212C */
  __IO uint32_t TCON0_SMX2SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x12130 */
  __IO uint32_t TCON0_SMX2FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s**3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x12134 */
  __IO uint32_t TCON0_SMX3SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x12138 */
  __IO uint32_t TCON0_SMX3FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x1213C */
  __IO uint32_t TCON0_SMX4SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x12140 */
  __IO uint32_t TCON0_SMX4FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x12144 */
  __IO uint32_t TCON0_SMX5SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x12148 */
  __IO uint32_t TCON0_SMX5FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x1214C */
  __IO uint32_t TCON0_SMX6SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x12150 */
  __IO uint32_t TCON0_SMX6FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x12154 */
  __IO uint32_t TCON0_SMX7SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x12158 */
  __IO uint32_t TCON0_SMX7FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x1215C */
  __IO uint32_t TCON0_SMX8SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x12160 */
  __IO uint32_t TCON0_SMX8FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x12164 */
  __IO uint32_t TCON0_SMX9SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x12168 */
  __IO uint32_t TCON0_SMX9FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x1216C */
  __IO uint32_t TCON0_SMX10SIGS;                   /**< Selection of input signals of sync mixer, offset: 0x12170 */
  __IO uint32_t TCON0_SMX10FCTTABLE;               /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x12174 */
  __IO uint32_t TCON0_SMX11SIGS;                   /**< Selection of input signals of sync mixer, offset: 0x12178 */
  __IO uint32_t TCON0_SMX11FCTTABLE;               /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x1217C */
  __O  uint32_t TCON0_RESET_OVER_UNFERFLOW;        /**< reset status overflow and underflow of both dual channel fifos, offset: 0x12180 */
  __I  uint32_t TCON0_DUAL_DEBUG;                  /**< Status of fifo during dual channel operation. They are only available in Split Mode, offset: 0x12184 */
       uint8_t RESERVED_123[632];
  __I  uint32_t SIG0_LOCKUNLOCK;                   /**< Register to change the protection status of this address block., offset: 0x12400 */
  __I  uint32_t SIG0_LOCKSTATUS;                   /**< Protection status of this address block., offset: 0x12404 */
  __IO uint32_t SIG0_STATICCONTROL;                /**< Global configuration shared by all evaluation windows., offset: 0x12408 */
  __IO uint32_t SIG0_PANICCOLOR;                   /**< Overlay color for evaluation windows in panic mode., offset: 0x1240C */
  __IO uint32_t SIG0_EVALCONTROL0;                 /**< Control settings for evaluation window 0., offset: 0x12410 */
  __IO uint32_t SIG0_EVALUPPERLEFT0;               /**< Upper left corner of evaluation window 0., offset: 0x12414 */
  __IO uint32_t SIG0_EVALLOWERRIGHT0;              /**< Lower right corner of evaluation window 0., offset: 0x12418 */
  __IO uint32_t SIG0_SIGCRCREDREF0;                /**< Reference signature of red channel for evaluation window 0., offset: 0x1241C */
  __IO uint32_t SIG0_SIGCRCGREENREF0;              /**< Reference signature of green channel for evaluation window 0., offset: 0x12420 */
  __IO uint32_t SIG0_SIGCRCBLUEREF0;               /**< Reference signature of blue channel for evaluation window 0., offset: 0x12424 */
  __I  uint32_t SIG0_SIGCRCRED0;                   /**< Measured signature of red channel for evaluation window 0., offset: 0x12428 */
  __I  uint32_t SIG0_SIGCRCGREEN0;                 /**< Measured signature of green channel for evaluation window 0., offset: 0x1242C */
  __I  uint32_t SIG0_SIGCRCBLUE0;                  /**< Measured signature of blue channel for evaluation window 0., offset: 0x12430 */
  __IO uint32_t SIG0_EVALCONTROL1;                 /**< Control settings for evaluation window 1., offset: 0x12434 */
  __IO uint32_t SIG0_EVALUPPERLEFT1;               /**< Upper left corner of evaluation window 1., offset: 0x12438 */
  __IO uint32_t SIG0_EVALLOWERRIGHT1;              /**< Lower right corner of evaluation window 1., offset: 0x1243C */
  __IO uint32_t SIG0_SIGCRCREDREF1;                /**< Reference signature of red channel for evaluation window 1., offset: 0x12440 */
  __IO uint32_t SIG0_SIGCRCGREENREF1;              /**< Reference signature of green channel for evaluation window 1., offset: 0x12444 */
  __IO uint32_t SIG0_SIGCRCBLUEREF1;               /**< Reference signature of blue channel for evaluation window 1., offset: 0x12448 */
  __I  uint32_t SIG0_SIGCRCRED1;                   /**< Measured signature of red channel for evaluation window 1., offset: 0x1244C */
  __I  uint32_t SIG0_SIGCRCGREEN1;                 /**< Measured signature of green channel for evaluation window 1., offset: 0x12450 */
  __I  uint32_t SIG0_SIGCRCBLUE1;                  /**< Measured signature of blue channel for evaluation window 1., offset: 0x12454 */
  __IO uint32_t SIG0_EVALCONTROL2;                 /**< Control settings for evaluation window 2., offset: 0x12458 */
  __IO uint32_t SIG0_EVALUPPERLEFT2;               /**< Upper left corner of evaluation window 2., offset: 0x1245C */
  __IO uint32_t SIG0_EVALLOWERRIGHT2;              /**< Lower right corner of evaluation window 2., offset: 0x12460 */
  __IO uint32_t SIG0_SIGCRCREDREF2;                /**< Reference signature of red channel for evaluation window 2., offset: 0x12464 */
  __IO uint32_t SIG0_SIGCRCGREENREF2;              /**< Reference signature of green channel for evaluation window 2., offset: 0x12468 */
  __IO uint32_t SIG0_SIGCRCBLUEREF2;               /**< Reference signature of blue channel for evaluation window 2., offset: 0x1246C */
  __I  uint32_t SIG0_SIGCRCRED2;                   /**< Measured signature of red channel for evaluation window 2., offset: 0x12470 */
  __I  uint32_t SIG0_SIGCRCGREEN2;                 /**< Measured signature of green channel for evaluation window 2., offset: 0x12474 */
  __I  uint32_t SIG0_SIGCRCBLUE2;                  /**< Measured signature of blue channel for evaluation window 2., offset: 0x12478 */
  __IO uint32_t SIG0_EVALCONTROL3;                 /**< Control settings for evaluation window 3., offset: 0x1247C */
  __IO uint32_t SIG0_EVALUPPERLEFT3;               /**< Upper left corner of evaluation window 3., offset: 0x12480 */
  __IO uint32_t SIG0_EVALLOWERRIGHT3;              /**< Lower right corner of evaluation window 3., offset: 0x12484 */
  __IO uint32_t SIG0_SIGCRCREDREF3;                /**< Reference signature of red channel for evaluation window 3., offset: 0x12488 */
  __IO uint32_t SIG0_SIGCRCGREENREF3;              /**< Reference signature of green channel for evaluation window 3., offset: 0x1248C */
  __IO uint32_t SIG0_SIGCRCBLUEREF3;               /**< Reference signature of blue channel for evaluation window 3., offset: 0x12490 */
  __I  uint32_t SIG0_SIGCRCRED3;                   /**< Measured signature of red channel for evaluation window 3., offset: 0x12494 */
  __I  uint32_t SIG0_SIGCRCGREEN3;                 /**< Measured signature of green channel for evaluation window 3., offset: 0x12498 */
  __I  uint32_t SIG0_SIGCRCBLUE3;                  /**< Measured signature of blue channel for evaluation window 3., offset: 0x1249C */
  __IO uint32_t SIG0_EVALCONTROL4;                 /**< Control settings for evaluation window 4., offset: 0x124A0 */
  __IO uint32_t SIG0_EVALUPPERLEFT4;               /**< Upper left corner of evaluation window 4., offset: 0x124A4 */
  __IO uint32_t SIG0_EVALLOWERRIGHT4;              /**< Lower right corner of evaluation window 4., offset: 0x124A8 */
  __IO uint32_t SIG0_SIGCRCREDREF4;                /**< Reference signature of red channel for evaluation window 4., offset: 0x124AC */
  __IO uint32_t SIG0_SIGCRCGREENREF4;              /**< Reference signature of green channel for evaluation window 4., offset: 0x124B0 */
  __IO uint32_t SIG0_SIGCRCBLUEREF4;               /**< Reference signature of blue channel for evaluation window 4., offset: 0x124B4 */
  __I  uint32_t SIG0_SIGCRCRED4;                   /**< Measured signature of red channel for evaluation window 4., offset: 0x124B8 */
  __I  uint32_t SIG0_SIGCRCGREEN4;                 /**< Measured signature of green channel for evaluation window 4., offset: 0x124BC */
  __I  uint32_t SIG0_SIGCRCBLUE4;                  /**< Measured signature of blue channel for evaluation window 4., offset: 0x124C0 */
  __IO uint32_t SIG0_EVALCONTROL5;                 /**< Control settings for evaluation window 5., offset: 0x124C4 */
  __IO uint32_t SIG0_EVALUPPERLEFT5;               /**< Upper left corner of evaluation window 5., offset: 0x124C8 */
  __IO uint32_t SIG0_EVALLOWERRIGHT5;              /**< Lower right corner of evaluation window 5., offset: 0x124CC */
  __IO uint32_t SIG0_SIGCRCREDREF5;                /**< Reference signature of red channel for evaluation window 5., offset: 0x124D0 */
  __IO uint32_t SIG0_SIGCRCGREENREF5;              /**< Reference signature of green channel for evaluation window 5., offset: 0x124D4 */
  __IO uint32_t SIG0_SIGCRCBLUEREF5;               /**< Reference signature of blue channel for evaluation window 5., offset: 0x124D8 */
  __I  uint32_t SIG0_SIGCRCRED5;                   /**< Measured signature of red channel for evaluation window 5., offset: 0x124DC */
  __I  uint32_t SIG0_SIGCRCGREEN5;                 /**< Measured signature of green channel for evaluation window 5., offset: 0x124E0 */
  __I  uint32_t SIG0_SIGCRCBLUE5;                  /**< Measured signature of blue channel for evaluation window 5., offset: 0x124E4 */
  __IO uint32_t SIG0_EVALCONTROL6;                 /**< Control settings for evaluation window 6., offset: 0x124E8 */
  __IO uint32_t SIG0_EVALUPPERLEFT6;               /**< Upper left corner of evaluation window 6., offset: 0x124EC */
  __IO uint32_t SIG0_EVALLOWERRIGHT6;              /**< Lower right corner of evaluation window 6., offset: 0x124F0 */
  __IO uint32_t SIG0_SIGCRCREDREF6;                /**< Reference signature of red channel for evaluation window 6., offset: 0x124F4 */
  __IO uint32_t SIG0_SIGCRCGREENREF6;              /**< Reference signature of green channel for evaluation window 6., offset: 0x124F8 */
  __IO uint32_t SIG0_SIGCRCBLUEREF6;               /**< Reference signature of blue channel for evaluation window 6., offset: 0x124FC */
  __I  uint32_t SIG0_SIGCRCRED6;                   /**< Measured signature of red channel for evaluation window 6., offset: 0x12500 */
  __I  uint32_t SIG0_SIGCRCGREEN6;                 /**< Measured signature of green channel for evaluation window 6., offset: 0x12504 */
  __I  uint32_t SIG0_SIGCRCBLUE6;                  /**< Measured signature of blue channel for evaluation window 6., offset: 0x12508 */
  __IO uint32_t SIG0_EVALCONTROL7;                 /**< Control settings for evaluation window 7., offset: 0x1250C */
  __IO uint32_t SIG0_EVALUPPERLEFT7;               /**< Upper left corner of evaluation window 7., offset: 0x12510 */
  __IO uint32_t SIG0_EVALLOWERRIGHT7;              /**< Lower right corner of evaluation window 7., offset: 0x12514 */
  __IO uint32_t SIG0_SIGCRCREDREF7;                /**< Reference signature of red channel for evaluation window 7., offset: 0x12518 */
  __IO uint32_t SIG0_SIGCRCGREENREF7;              /**< Reference signature of green channel for evaluation window 7., offset: 0x1251C */
  __IO uint32_t SIG0_SIGCRCBLUEREF7;               /**< Reference signature of blue channel for evaluation window 7., offset: 0x12520 */
  __I  uint32_t SIG0_SIGCRCRED7;                   /**< Measured signature of red channel for evaluation window 7., offset: 0x12524 */
  __I  uint32_t SIG0_SIGCRCGREEN7;                 /**< Measured signature of green channel for evaluation window 7., offset: 0x12528 */
  __I  uint32_t SIG0_SIGCRCBLUE7;                  /**< Measured signature of blue channel for evaluation window 7., offset: 0x1252C */
  __I  uint32_t SIG0_SHADOWLOAD;                   /**< Shadow load control register., offset: 0x12530 */
  __IO uint32_t SIG0_CONTINUOUSMODE;               /**< Signature operation mode control., offset: 0x12534 */
  __O  uint32_t SIG0_SOFTWAREKICK;                 /**< Signature measurement trigger., offset: 0x12538 */
  __I  uint32_t SIG0_STATUS;                       /**< Module status., offset: 0x1253C */
       uint8_t RESERVED_124[704];
  __I  uint32_t FRAMEGEN1_LOCKUNLOCK;              /**< Register to change the protection status of this address block., offset: 0x12800 */
  __I  uint32_t FRAMEGEN1_LOCKSTATUS;              /**< Protection status of this address block., offset: 0x12804 */
  __IO uint32_t FRAMEGEN1_FGSTCTRL;                /**< FrameGen Static Control Register, offset: 0x12808 */
  __IO uint32_t FRAMEGEN1_HTCFG1;                  /**< FrameGen Horizontal Timing Config Register 1, offset: 0x1280C */
  __IO uint32_t FRAMEGEN1_HTCFG2;                  /**< FrameGen Horizontal Timing Config Register 2, offset: 0x12810 */
  __IO uint32_t FRAMEGEN1_VTCFG1;                  /**< FrameGen Vertical Timing Config Register 1, offset: 0x12814 */
  __IO uint32_t FRAMEGEN1_VTCFG2;                  /**< FrameGen Vertical Timing Config Register 2, offset: 0x12818 */
  __I  uint32_t FRAMEGEN1_INT0CONFIG;              /**< Coordinates of the trigger point for generation of the Int0 interrupt signal, offset: 0x1281C */
  __I  uint32_t FRAMEGEN1_INT1CONFIG;              /**< Coordinates of the trigger point for generation of the Int1 interrupt signal, offset: 0x12820 */
  __I  uint32_t FRAMEGEN1_INT2CONFIG;              /**< Coordinates of the trigger point for generation of the Int2 interrupt signal, offset: 0x12824 */
  __I  uint32_t FRAMEGEN1_INT3CONFIG;              /**< Coordinates of the trigger point for generation of the Int3 interrupt signal, offset: 0x12828 */
  __IO uint32_t FRAMEGEN1_PKICKCONFIG;             /**< Coordinates of the trigger point for generation of the primary kick signal, offset: 0x1282C */
  __IO uint32_t FRAMEGEN1_SKICKCONFIG;             /**< Coordinates of the trigger point for generation of the secondary kick signal, offset: 0x12830 */
  __IO uint32_t FRAMEGEN1_SECSTATCONFIG;           /**< Configuration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register., offset: 0x12834 */
  __IO uint32_t FRAMEGEN1_FGSRCR1;                 /**< FrameGen Skew Regulation Control Register 1., offset: 0x12838 */
  __IO uint32_t FRAMEGEN1_FGSRCR2;                 /**< FrameGen Skew Regulation Control Register 2, offset: 0x1283C */
  __IO uint32_t FRAMEGEN1_FGSRCR3;                 /**< FrameGen Skew Regulation Control Register 3, offset: 0x12840 */
  __IO uint32_t FRAMEGEN1_FGSRCR4;                 /**< FrameGen Skew Regulation Control Register 4, offset: 0x12844 */
  __IO uint32_t FRAMEGEN1_FGSRCR5;                 /**< FrameGen Skew Regulation Control Register 5, offset: 0x12848 */
  __IO uint32_t FRAMEGEN1_FGSRCR6;                 /**< FrameGen Skew Regulation Control Register 6, offset: 0x1284C */
  __IO uint32_t FRAMEGEN1_FGKSDR;                  /**< FrameGen Kick System Debug Register, offset: 0x12850 */
  __IO uint32_t FRAMEGEN1_PACFG;                   /**< FrameGen Primary Area Config Register 1 (shadowed), offset: 0x12854 */
  __IO uint32_t FRAMEGEN1_SACFG;                   /**< FrameGen Secondary Area Config Register 1 (shadowed), offset: 0x12858 */
  __IO uint32_t FRAMEGEN1_FGINCTRL;                /**< FrameGen Input Control Register (shadowed), offset: 0x1285C */
  __IO uint32_t FRAMEGEN1_FGINCTRLPANIC;           /**< FrameGen Input Control Panic Register (shadowed), offset: 0x12860 */
  __IO uint32_t FRAMEGEN1_FGCCR;                   /**< FrameGen Constant Color Register (shadowed), offset: 0x12864 */
  __IO uint32_t FRAMEGEN1_FGENABLE;                /**< FrameGen Enable Register, offset: 0x12868 */
  __O  uint32_t FRAMEGEN1_FGSLR;                   /**< FrameGen Shadow Load Register, offset: 0x1286C */
  __I  uint32_t FRAMEGEN1_FGENSTS;                 /**< FrameGen Enable Status Register, offset: 0x12870 */
  __I  uint32_t FRAMEGEN1_FGTIMESTAMP;             /**< Time stamp status., offset: 0x12874 */
  __I  uint32_t FRAMEGEN1_FGCHSTAT;                /**< FrameGen Channel Status Register, offset: 0x12878 */
  __O  uint32_t FRAMEGEN1_FGCHSTATCLR;             /**< FrameGen Channel Status Clear Register, offset: 0x1287C */
  __I  uint32_t FRAMEGEN1_FGSKEWMON;               /**< FrameGen Skew Monitor Register for Secondary Channel Skew Control, offset: 0x12880 */
  __I  uint32_t FRAMEGEN1_FGSFIFOMIN;              /**< FrameGen Secondary FIFO Min Fill Register, offset: 0x12884 */
  __I  uint32_t FRAMEGEN1_FGSFIFOMAX;              /**< FrameGen Secondary FIFO Max Fill Register, offset: 0x12888 */
  __O  uint32_t FRAMEGEN1_FGSFIFOFILLCLR;          /**< FrameGen Secondary FIFO Fill Clear Register, offset: 0x1288C */
  __I  uint32_t FRAMEGEN1_FGSREPD;                 /**< FrameGen Skew Regulation ExtraPolation Debug Register, offset: 0x12890 */
  __I  uint32_t FRAMEGEN1_FGSRFTD;                 /**< FrameGen Skew Regulation Frame Total Debug Register, offset: 0x12894 */
       uint8_t RESERVED_125[872];
  __I  uint32_t MATRIX1_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0x12C00 */
  __I  uint32_t MATRIX1_LOCKSTATUS;                /**< Protection status of this address block., offset: 0x12C04 */
  __IO uint32_t MATRIX1_STATICCONTROL;             /**< Color Matrix static control register, offset: 0x12C08 */
  __IO uint32_t MATRIX1_CONTROL;                   /**< Color Matrix control register, offset: 0x12C0C */
  __IO uint32_t MATRIX1_RED0;                      /**< Matrix values for calculation of the red output value., offset: 0x12C10 */
  __IO uint32_t MATRIX1_RED1;                      /**< Matrix values for calculation of the red output value., offset: 0x12C14 */
  __IO uint32_t MATRIX1_GREEN0;                    /**< Matrix values for calculation of the green output value., offset: 0x12C18 */
  __IO uint32_t MATRIX1_GREEN1;                    /**< Matrix values for calculation of the green output value., offset: 0x12C1C */
  __IO uint32_t MATRIX1_BLUE0;                     /**< Matrix values for calculation of the blue output value., offset: 0x12C20 */
  __IO uint32_t MATRIX1_BLUE1;                     /**< Matrix values for calculation of the blue output value., offset: 0x12C24 */
  __IO uint32_t MATRIX1_ALPHA0;                    /**< Matrix values for calculation of the alpha output value., offset: 0x12C28 */
  __IO uint32_t MATRIX1_ALPHA1;                    /**< Matrix values for calculation of the alpha output value., offset: 0x12C2C */
  __IO uint32_t MATRIX1_OFFSETVECTOR0;             /**< Offset vectors for red and green output., offset: 0x12C30 */
  __IO uint32_t MATRIX1_OFFSETVECTOR1;             /**< Offset vectors for blue and alpha output., offset: 0x12C34 */
  __I  uint32_t MATRIX1_LASTCONTROLWORD;           /**< Value of last received control word, for debugging., offset: 0x12C38 */
       uint8_t RESERVED_126[964];
  __I  uint32_t GAMMACOR1_LOCKUNLOCK;              /**< Register to change the protection status of this address block., offset: 0x13000 */
  __I  uint32_t GAMMACOR1_LOCKSTATUS;              /**< Protection status of this address block., offset: 0x13004 */
  __IO uint32_t GAMMACOR1_STATICCONTROL;           /**< Static control settings., offset: 0x13008 */
  __I  uint32_t GAMMACOR1_LUTSTART;                /**< Start values for look-up table programming., offset: 0x1300C */
  __I  uint32_t GAMMACOR1_LUTDELTAS;               /**< Delta values for look-up table programming., offset: 0x13010 */
  __IO uint32_t GAMMACOR1_CONTROL;                 /**< Dynamic control settings., offset: 0x13014 */
  __IO uint32_t GAMMACOR1_STATUS;                  /**< Internal status bits., offset: 0x13018 */
  __I  uint32_t GAMMACOR1_LASTCONTROLWORD;         /**< Value of last received control word., offset: 0x1301C */
       uint8_t RESERVED_127[992];
  __I  uint32_t DITHER1_LOCKUNLOCK;                /**< Register to change the protection status of this address block., offset: 0x13400 */
  __I  uint32_t DITHER1_LOCKSTATUS;                /**< Protection status of this address block., offset: 0x13404 */
  __IO uint32_t DITHER1_CONTROL;                   /**< Dither Unit common control., offset: 0x13408 */
  __IO uint32_t DITHER1_DITHERCONTROL;             /**< Dither Unit processing control., offset: 0x1340C */
  __I  uint32_t DITHER1_RELEASE;                   /**< Dither Unit release., offset: 0x13410 */
       uint8_t RESERVED_128[1004];
  __I  uint32_t TCON1_SSQCNTS;                     /**< The 64 Sequencer Position Definitions registers define the X/Y scan positions of the sequencers, hold their output value and assign the sequencer to an odd/even field, offset: 0x13800 */
       uint8_t RESERVED_129[1020];
  __I  uint32_t TCON1_LOCKUNLOCK;                  /**< Register to change the protection status of this address block., offset: 0x13C00 */
  __I  uint32_t TCON1_LOCKSTATUS;                  /**< Protection status of this address block., offset: 0x13C04 */
  __IO uint32_t TCON1_SSQCYCLE;                    /**< This bitfield sets the sequencer cycle length. The value set here -1 is the number of sequencer cycles, offset: 0x13C08 */
  __IO uint32_t TCON1_SWRESET;                     /**< TCON Software Reset - Reset all tcon registers except configuration registers. Detailed description in specification document, offset: 0x13C0C */
  __IO uint32_t TCON1_TCON_CTRL;                   /**< TCON Control register, offset: 0x13C10 */
  __IO uint32_t TCON1_RSDSINVCTRL;                 /**< Controls inversion of output polarity when connected IO cells operate in RSDS mode, offset: 0x13C14 */
  __IO uint32_t TCON1_MAPBIT3_0;                   /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3, offset: 0x13C18 */
  __IO uint32_t TCON1_MAPBIT7_4;                   /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7, offset: 0x13C1C */
  __IO uint32_t TCON1_MAPBIT11_8;                  /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11, offset: 0x13C20 */
  __IO uint32_t TCON1_MAPBIT15_12;                 /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15, offset: 0x13C24 */
  __IO uint32_t TCON1_MAPBIT19_16;                 /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19, offset: 0x13C28 */
  __IO uint32_t TCON1_MAPBIT23_20;                 /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23, offset: 0x13C2C */
  __IO uint32_t TCON1_MAPBIT27_24;                 /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27, offset: 0x13C30 */
  __IO uint32_t TCON1_MAPBIT31_28;                 /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31, offset: 0x13C34 */
  __IO uint32_t TCON1_MAPBIT34_32;                 /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34, offset: 0x13C38 */
  __IO uint32_t TCON1_MAPBIT3_0_DUAL;              /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3 2nd channel, offset: 0x13C3C */
  __IO uint32_t TCON1_MAPBIT7_4_DUAL;              /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7 2nd channel, offset: 0x13C40 */
  __IO uint32_t TCON1_MAPBIT11_8_DUAL;             /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11 2nd channel, offset: 0x13C44 */
  __IO uint32_t TCON1_MAPBIT15_12_DUAL;            /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15 2nd channel, offset: 0x13C48 */
  __IO uint32_t TCON1_MAPBIT19_16_DUAL;            /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19 2nd channel, offset: 0x13C4C */
  __IO uint32_t TCON1_MAPBIT23_20_DUAL;            /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23 2nd channel, offset: 0x13C50 */
  __IO uint32_t TCON1_MAPBIT27_24_DUAL;            /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27 2nd channel, offset: 0x13C54 */
  __IO uint32_t TCON1_MAPBIT31_28_DUAL;            /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31 2nd channel, offset: 0x13C58 */
  __IO uint32_t TCON1_MAPBIT34_32_DUAL;            /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34 2nd channel, offset: 0x13C5C */
  __IO uint32_t TCON1_SPG0POSON;                   /**< Sync pulse generator 0, 'Switch on' position, offset: 0x13C60 */
  __IO uint32_t TCON1_SPG0MASKON;                  /**< The Sequencer Pulse Generator 0 Mask Enable register is used to mask the enable of SPG 0, offset: 0x13C64 */
  __IO uint32_t TCON1_SPG0POSOFF;                  /**< Sync pulse generator 0, 'Switch off' position, offset: 0x13C68 */
  __IO uint32_t TCON1_SPG0MASKOFF;                 /**< The Sequencer Pulse Generator 0 Mask Enable register is used to mask the disable of SPG 0, offset: 0x13C6C */
  __IO uint32_t TCON1_SPG1POSON;                   /**< Sync pulse generator 1, 'Switch on' position, offset: 0x13C70 */
  __IO uint32_t TCON1_SPG1MASKON;                  /**< The Sequencer Pulse Generator 1 Mask Enable register is used to mask the enable of SPG 1, offset: 0x13C74 */
  __IO uint32_t TCON1_SPG1POSOFF;                  /**< Sync pulse generator 1, 'Switch off' position, offset: 0x13C78 */
  __IO uint32_t TCON1_SPG1MASKOFF;                 /**< The Sequencer Pulse Generator 1 Mask Enable register is used to mask the disable of SPG 1, offset: 0x13C7C */
  __IO uint32_t TCON1_SPG2POSON;                   /**< Sync pulse generator 2, 'Switch on' position, offset: 0x13C80 */
  __IO uint32_t TCON1_SPG2MASKON;                  /**< The Sequencer Pulse Generator 2 Mask Enable register is used to mask the enable of SPG 2, offset: 0x13C84 */
  __IO uint32_t TCON1_SPG2POSOFF;                  /**< Sync pulse generator 2, 'Switch off' position, offset: 0x13C88 */
  __IO uint32_t TCON1_SPG2MASKOFF;                 /**< The Sequencer Pulse Generator 2 Mask Enable register is used to mask the disable of SPG 2, offset: 0x13C8C */
  __IO uint32_t TCON1_SPG3POSON;                   /**< Sync pulse generator 3, 'Switch on' position, offset: 0x13C90 */
  __IO uint32_t TCON1_SPG3MASKON;                  /**< The Sequencer Pulse Generator 3 Mask Enable register is used to mask the enable of SPG 3, offset: 0x13C94 */
  __IO uint32_t TCON1_SPG3POSOFF;                  /**< Sync pulse generator 3, 'Switch off' position, offset: 0x13C98 */
  __IO uint32_t TCON1_SPG3MASKOFF;                 /**< The Sequencer Pulse Generator 3 Mask Enable register is used to mask the disable of SPG 3, offset: 0x13C9C */
  __IO uint32_t TCON1_SPG4POSON;                   /**< Sync pulse generator 4, 'Switch on' position, offset: 0x13CA0 */
  __IO uint32_t TCON1_SPG4MASKON;                  /**< The Sequencer Pulse Generator 4 Mask Enable register is used to mask the enable of SPG 4, offset: 0x13CA4 */
  __IO uint32_t TCON1_SPG4POSOFF;                  /**< Sync pulse generator 4, 'Switch off' position, offset: 0x13CA8 */
  __IO uint32_t TCON1_SPG4MASKOFF;                 /**< The Sequencer Pulse Generator 4 Mask Enable register is used to mask the disable of SPG 4, offset: 0x13CAC */
  __IO uint32_t TCON1_SPG5POSON;                   /**< Sync pulse generator 5, 'Switch on' position, offset: 0x13CB0 */
  __IO uint32_t TCON1_SPG5MASKON;                  /**< The Sequencer Pulse Generator 5 Mask Enable register is used to mask the enable of SPG 5, offset: 0x13CB4 */
  __IO uint32_t TCON1_SPG5POSOFF;                  /**< Sync pulse generator 5, 'Switch off' position, offset: 0x13CB8 */
  __IO uint32_t TCON1_SPG5MASKOFF;                 /**< The Sequencer Pulse Generator 5 Mask Enable register is used to mask the disable of SPG 5, offset: 0x13CBC */
  __IO uint32_t TCON1_SPG6POSON;                   /**< Sync pulse generator 6, 'Switch on' position, offset: 0x13CC0 */
  __IO uint32_t TCON1_SPG6MASKON;                  /**< The Sequencer Pulse Generator 6 Mask Enable register is used to mask the enable of SPG 6, offset: 0x13CC4 */
  __IO uint32_t TCON1_SPG6POSOFF;                  /**< Sync pulse generator 6, 'Switch off' position, offset: 0x13CC8 */
  __IO uint32_t TCON1_SPG6MASKOFF;                 /**< The Sequencer Pulse Generator 6 Mask Enable register is used to mask the disable of SPG 6, offset: 0x13CCC */
  __IO uint32_t TCON1_SPG7POSON;                   /**< Sync pulse generator 7, 'Switch on' position, offset: 0x13CD0 */
  __IO uint32_t TCON1_SPG7MASKON;                  /**< The Sequencer Pulse Generator 7 Mask Enable register is used to mask the enable of SPG 7, offset: 0x13CD4 */
  __IO uint32_t TCON1_SPG7POSOFF;                  /**< Sync pulse generator 7, 'Switch off' position, offset: 0x13CD8 */
  __IO uint32_t TCON1_SPG7MASKOFF;                 /**< The Sequencer Pulse Generator 7 Mask Enable register is used to mask the disable of SPG 7, offset: 0x13CDC */
  __IO uint32_t TCON1_SPG8POSON;                   /**< Sync pulse generator 8, 'Switch on' position, offset: 0x13CE0 */
  __IO uint32_t TCON1_SPG8MASKON;                  /**< The Sequencer Pulse Generator 8 Mask Enable register is used to mask the enable of SPG 8, offset: 0x13CE4 */
  __IO uint32_t TCON1_SPG8POSOFF;                  /**< Sync pulse generator 8, 'Switch off' position, offset: 0x13CE8 */
  __IO uint32_t TCON1_SPG8MASKOFF;                 /**< The Sequencer Pulse Generator 8 Mask Enable register is used to mask the disable of SPG 8, offset: 0x13CEC */
  __IO uint32_t TCON1_SPG9POSON;                   /**< Sync pulse generator 9, 'Switch on' position, offset: 0x13CF0 */
  __IO uint32_t TCON1_SPG9MASKON;                  /**< The Sequencer Pulse Generator 9 Mask Enable register is used to mask the enable of SPG 9, offset: 0x13CF4 */
  __IO uint32_t TCON1_SPG9POSOFF;                  /**< Sync pulse generator 9, 'Switch off' position, offset: 0x13CF8 */
  __IO uint32_t TCON1_SPG9MASKOFF;                 /**< The Sequencer Pulse Generator 9 Mask Enable register is used to mask the disable of SPG 9, offset: 0x13CFC */
  __IO uint32_t TCON1_SPG10POSON;                  /**< Sync pulse generator 10, 'Switch on' position, offset: 0x13D00 */
  __IO uint32_t TCON1_SPG10MASKON;                 /**< The Sequencer Pulse Generator 10 Mask Enable register is used to mask the enable of SPG 10, offset: 0x13D04 */
  __IO uint32_t TCON1_SPG10POSOFF;                 /**< Sync pulse generator 10, 'Switch off' position, offset: 0x13D08 */
  __IO uint32_t TCON1_SPG10MASKOFF;                /**< The Sequencer Pulse Generator 10 Mask Enable register is used to mask the disable of SPG 10, offset: 0x13D0C */
  __IO uint32_t TCON1_SPG11POSON;                  /**< Sync pulse generator 11, 'Switch on' position, offset: 0x13D10 */
  __IO uint32_t TCON1_SPG11MASKON;                 /**< The Sequencer Pulse Generator 11 Mask Enable register is used to mask the enable of SPG 11, offset: 0x13D14 */
  __IO uint32_t TCON1_SPG11POSOFF;                 /**< Sync pulse generator 11, 'Switch off' position, offset: 0x13D18 */
  __IO uint32_t TCON1_SPG11MASKOFF;                /**< The Sequencer Pulse Generator 11 Mask Enable register is used to mask the disable of SPG 11, offset: 0x13D1C */
  __IO uint32_t TCON1_SMX0SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x13D20 */
  __IO uint32_t TCON1_SMX0FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x13D24 */
  __IO uint32_t TCON1_SMX1SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x13D28 */
  __IO uint32_t TCON1_SMX1FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x13D2C */
  __IO uint32_t TCON1_SMX2SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x13D30 */
  __IO uint32_t TCON1_SMX2FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s**3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x13D34 */
  __IO uint32_t TCON1_SMX3SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x13D38 */
  __IO uint32_t TCON1_SMX3FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x13D3C */
  __IO uint32_t TCON1_SMX4SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x13D40 */
  __IO uint32_t TCON1_SMX4FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x13D44 */
  __IO uint32_t TCON1_SMX5SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x13D48 */
  __IO uint32_t TCON1_SMX5FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x13D4C */
  __IO uint32_t TCON1_SMX6SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x13D50 */
  __IO uint32_t TCON1_SMX6FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x13D54 */
  __IO uint32_t TCON1_SMX7SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x13D58 */
  __IO uint32_t TCON1_SMX7FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x13D5C */
  __IO uint32_t TCON1_SMX8SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x13D60 */
  __IO uint32_t TCON1_SMX8FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x13D64 */
  __IO uint32_t TCON1_SMX9SIGS;                    /**< Selection of input signals of sync mixer, offset: 0x13D68 */
  __IO uint32_t TCON1_SMX9FCTTABLE;                /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x13D6C */
  __IO uint32_t TCON1_SMX10SIGS;                   /**< Selection of input signals of sync mixer, offset: 0x13D70 */
  __IO uint32_t TCON1_SMX10FCTTABLE;               /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x13D74 */
  __IO uint32_t TCON1_SMX11SIGS;                   /**< Selection of input signals of sync mixer, offset: 0x13D78 */
  __IO uint32_t TCON1_SMX11FCTTABLE;               /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0x13D7C */
  __O  uint32_t TCON1_RESET_OVER_UNFERFLOW;        /**< reset status overflow and underflow of both dual channel fifos, offset: 0x13D80 */
  __I  uint32_t TCON1_DUAL_DEBUG;                  /**< Status of fifo during dual channel operation. They are only available in Split Mode, offset: 0x13D84 */
       uint8_t RESERVED_130[632];
  __I  uint32_t SIG1_LOCKUNLOCK;                   /**< Register to change the protection status of this address block., offset: 0x14000 */
  __I  uint32_t SIG1_LOCKSTATUS;                   /**< Protection status of this address block., offset: 0x14004 */
  __IO uint32_t SIG1_STATICCONTROL;                /**< Global configuration shared by all evaluation windows., offset: 0x14008 */
  __IO uint32_t SIG1_PANICCOLOR;                   /**< Overlay color for evaluation windows in panic mode., offset: 0x1400C */
  __IO uint32_t SIG1_EVALCONTROL0;                 /**< Control settings for evaluation window 0., offset: 0x14010 */
  __IO uint32_t SIG1_EVALUPPERLEFT0;               /**< Upper left corner of evaluation window 0., offset: 0x14014 */
  __IO uint32_t SIG1_EVALLOWERRIGHT0;              /**< Lower right corner of evaluation window 0., offset: 0x14018 */
  __IO uint32_t SIG1_SIGCRCREDREF0;                /**< Reference signature of red channel for evaluation window 0., offset: 0x1401C */
  __IO uint32_t SIG1_SIGCRCGREENREF0;              /**< Reference signature of green channel for evaluation window 0., offset: 0x14020 */
  __IO uint32_t SIG1_SIGCRCBLUEREF0;               /**< Reference signature of blue channel for evaluation window 0., offset: 0x14024 */
  __I  uint32_t SIG1_SIGCRCRED0;                   /**< Measured signature of red channel for evaluation window 0., offset: 0x14028 */
  __I  uint32_t SIG1_SIGCRCGREEN0;                 /**< Measured signature of green channel for evaluation window 0., offset: 0x1402C */
  __I  uint32_t SIG1_SIGCRCBLUE0;                  /**< Measured signature of blue channel for evaluation window 0., offset: 0x14030 */
  __IO uint32_t SIG1_EVALCONTROL1;                 /**< Control settings for evaluation window 1., offset: 0x14034 */
  __IO uint32_t SIG1_EVALUPPERLEFT1;               /**< Upper left corner of evaluation window 1., offset: 0x14038 */
  __IO uint32_t SIG1_EVALLOWERRIGHT1;              /**< Lower right corner of evaluation window 1., offset: 0x1403C */
  __IO uint32_t SIG1_SIGCRCREDREF1;                /**< Reference signature of red channel for evaluation window 1., offset: 0x14040 */
  __IO uint32_t SIG1_SIGCRCGREENREF1;              /**< Reference signature of green channel for evaluation window 1., offset: 0x14044 */
  __IO uint32_t SIG1_SIGCRCBLUEREF1;               /**< Reference signature of blue channel for evaluation window 1., offset: 0x14048 */
  __I  uint32_t SIG1_SIGCRCRED1;                   /**< Measured signature of red channel for evaluation window 1., offset: 0x1404C */
  __I  uint32_t SIG1_SIGCRCGREEN1;                 /**< Measured signature of green channel for evaluation window 1., offset: 0x14050 */
  __I  uint32_t SIG1_SIGCRCBLUE1;                  /**< Measured signature of blue channel for evaluation window 1., offset: 0x14054 */
  __IO uint32_t SIG1_EVALCONTROL2;                 /**< Control settings for evaluation window 2., offset: 0x14058 */
  __IO uint32_t SIG1_EVALUPPERLEFT2;               /**< Upper left corner of evaluation window 2., offset: 0x1405C */
  __IO uint32_t SIG1_EVALLOWERRIGHT2;              /**< Lower right corner of evaluation window 2., offset: 0x14060 */
  __IO uint32_t SIG1_SIGCRCREDREF2;                /**< Reference signature of red channel for evaluation window 2., offset: 0x14064 */
  __IO uint32_t SIG1_SIGCRCGREENREF2;              /**< Reference signature of green channel for evaluation window 2., offset: 0x14068 */
  __IO uint32_t SIG1_SIGCRCBLUEREF2;               /**< Reference signature of blue channel for evaluation window 2., offset: 0x1406C */
  __I  uint32_t SIG1_SIGCRCRED2;                   /**< Measured signature of red channel for evaluation window 2., offset: 0x14070 */
  __I  uint32_t SIG1_SIGCRCGREEN2;                 /**< Measured signature of green channel for evaluation window 2., offset: 0x14074 */
  __I  uint32_t SIG1_SIGCRCBLUE2;                  /**< Measured signature of blue channel for evaluation window 2., offset: 0x14078 */
  __IO uint32_t SIG1_EVALCONTROL3;                 /**< Control settings for evaluation window 3., offset: 0x1407C */
  __IO uint32_t SIG1_EVALUPPERLEFT3;               /**< Upper left corner of evaluation window 3., offset: 0x14080 */
  __IO uint32_t SIG1_EVALLOWERRIGHT3;              /**< Lower right corner of evaluation window 3., offset: 0x14084 */
  __IO uint32_t SIG1_SIGCRCREDREF3;                /**< Reference signature of red channel for evaluation window 3., offset: 0x14088 */
  __IO uint32_t SIG1_SIGCRCGREENREF3;              /**< Reference signature of green channel for evaluation window 3., offset: 0x1408C */
  __IO uint32_t SIG1_SIGCRCBLUEREF3;               /**< Reference signature of blue channel for evaluation window 3., offset: 0x14090 */
  __I  uint32_t SIG1_SIGCRCRED3;                   /**< Measured signature of red channel for evaluation window 3., offset: 0x14094 */
  __I  uint32_t SIG1_SIGCRCGREEN3;                 /**< Measured signature of green channel for evaluation window 3., offset: 0x14098 */
  __I  uint32_t SIG1_SIGCRCBLUE3;                  /**< Measured signature of blue channel for evaluation window 3., offset: 0x1409C */
  __IO uint32_t SIG1_EVALCONTROL4;                 /**< Control settings for evaluation window 4., offset: 0x140A0 */
  __IO uint32_t SIG1_EVALUPPERLEFT4;               /**< Upper left corner of evaluation window 4., offset: 0x140A4 */
  __IO uint32_t SIG1_EVALLOWERRIGHT4;              /**< Lower right corner of evaluation window 4., offset: 0x140A8 */
  __IO uint32_t SIG1_SIGCRCREDREF4;                /**< Reference signature of red channel for evaluation window 4., offset: 0x140AC */
  __IO uint32_t SIG1_SIGCRCGREENREF4;              /**< Reference signature of green channel for evaluation window 4., offset: 0x140B0 */
  __IO uint32_t SIG1_SIGCRCBLUEREF4;               /**< Reference signature of blue channel for evaluation window 4., offset: 0x140B4 */
  __I  uint32_t SIG1_SIGCRCRED4;                   /**< Measured signature of red channel for evaluation window 4., offset: 0x140B8 */
  __I  uint32_t SIG1_SIGCRCGREEN4;                 /**< Measured signature of green channel for evaluation window 4., offset: 0x140BC */
  __I  uint32_t SIG1_SIGCRCBLUE4;                  /**< Measured signature of blue channel for evaluation window 4., offset: 0x140C0 */
  __IO uint32_t SIG1_EVALCONTROL5;                 /**< Control settings for evaluation window 5., offset: 0x140C4 */
  __IO uint32_t SIG1_EVALUPPERLEFT5;               /**< Upper left corner of evaluation window 5., offset: 0x140C8 */
  __IO uint32_t SIG1_EVALLOWERRIGHT5;              /**< Lower right corner of evaluation window 5., offset: 0x140CC */
  __IO uint32_t SIG1_SIGCRCREDREF5;                /**< Reference signature of red channel for evaluation window 5., offset: 0x140D0 */
  __IO uint32_t SIG1_SIGCRCGREENREF5;              /**< Reference signature of green channel for evaluation window 5., offset: 0x140D4 */
  __IO uint32_t SIG1_SIGCRCBLUEREF5;               /**< Reference signature of blue channel for evaluation window 5., offset: 0x140D8 */
  __I  uint32_t SIG1_SIGCRCRED5;                   /**< Measured signature of red channel for evaluation window 5., offset: 0x140DC */
  __I  uint32_t SIG1_SIGCRCGREEN5;                 /**< Measured signature of green channel for evaluation window 5., offset: 0x140E0 */
  __I  uint32_t SIG1_SIGCRCBLUE5;                  /**< Measured signature of blue channel for evaluation window 5., offset: 0x140E4 */
  __IO uint32_t SIG1_EVALCONTROL6;                 /**< Control settings for evaluation window 6., offset: 0x140E8 */
  __IO uint32_t SIG1_EVALUPPERLEFT6;               /**< Upper left corner of evaluation window 6., offset: 0x140EC */
  __IO uint32_t SIG1_EVALLOWERRIGHT6;              /**< Lower right corner of evaluation window 6., offset: 0x140F0 */
  __IO uint32_t SIG1_SIGCRCREDREF6;                /**< Reference signature of red channel for evaluation window 6., offset: 0x140F4 */
  __IO uint32_t SIG1_SIGCRCGREENREF6;              /**< Reference signature of green channel for evaluation window 6., offset: 0x140F8 */
  __IO uint32_t SIG1_SIGCRCBLUEREF6;               /**< Reference signature of blue channel for evaluation window 6., offset: 0x140FC */
  __I  uint32_t SIG1_SIGCRCRED6;                   /**< Measured signature of red channel for evaluation window 6., offset: 0x14100 */
  __I  uint32_t SIG1_SIGCRCGREEN6;                 /**< Measured signature of green channel for evaluation window 6., offset: 0x14104 */
  __I  uint32_t SIG1_SIGCRCBLUE6;                  /**< Measured signature of blue channel for evaluation window 6., offset: 0x14108 */
  __IO uint32_t SIG1_EVALCONTROL7;                 /**< Control settings for evaluation window 7., offset: 0x1410C */
  __IO uint32_t SIG1_EVALUPPERLEFT7;               /**< Upper left corner of evaluation window 7., offset: 0x14110 */
  __IO uint32_t SIG1_EVALLOWERRIGHT7;              /**< Lower right corner of evaluation window 7., offset: 0x14114 */
  __IO uint32_t SIG1_SIGCRCREDREF7;                /**< Reference signature of red channel for evaluation window 7., offset: 0x14118 */
  __IO uint32_t SIG1_SIGCRCGREENREF7;              /**< Reference signature of green channel for evaluation window 7., offset: 0x1411C */
  __IO uint32_t SIG1_SIGCRCBLUEREF7;               /**< Reference signature of blue channel for evaluation window 7., offset: 0x14120 */
  __I  uint32_t SIG1_SIGCRCRED7;                   /**< Measured signature of red channel for evaluation window 7., offset: 0x14124 */
  __I  uint32_t SIG1_SIGCRCGREEN7;                 /**< Measured signature of green channel for evaluation window 7., offset: 0x14128 */
  __I  uint32_t SIG1_SIGCRCBLUE7;                  /**< Measured signature of blue channel for evaluation window 7., offset: 0x1412C */
  __I  uint32_t SIG1_SHADOWLOAD;                   /**< Shadow load control register., offset: 0x14130 */
  __IO uint32_t SIG1_CONTINUOUSMODE;               /**< Signature operation mode control., offset: 0x14134 */
  __O  uint32_t SIG1_SOFTWAREKICK;                 /**< Signature measurement trigger., offset: 0x14138 */
  __I  uint32_t SIG1_STATUS;                       /**< Module status., offset: 0x1413C */
       uint8_t RESERVED_131[704];
  __IO uint32_t CAPENGCFG_CAPTUREINPUT0;           /**< Capture status fields., offset: 0x14400 */
  __IO uint32_t CAPENGCFG_CAPTUREINPUT1;           /**< Capture status fields., offset: 0x14404 */
       uint8_t RESERVED_132[1016];
  __I  uint32_t FRAMECAP4_LOCKUNLOCK;              /**< Register to change the protection status of this address block., offset: 0x14800 */
  __I  uint32_t FRAMECAP4_LOCKSTATUS;              /**< Protection status of this address block., offset: 0x14804 */
  __IO uint32_t FRAMECAP4_CTR;                     /**< FrameCap Control Register, offset: 0x14808 */
  __IO uint32_t FRAMECAP4_SPR;                     /**< FrameCap Sync Polarity Register, offset: 0x1480C */
  __IO uint32_t FRAMECAP4_FDR;                     /**< Frame dimension (progressive frame and field 0)., offset: 0x14810 */
  __IO uint32_t FRAMECAP4_FDR1;                    /**< Frame dimension (field 1)., offset: 0x14814 */
  __IO uint32_t FRAMECAP4_KCR;                     /**< FrameCap Kick Config Register, offset: 0x14818 */
  __IO uint32_t FRAMECAP4_SCR;                     /**< FrameCap Sync Config Register, offset: 0x1481C */
  __I  uint32_t FRAMECAP4_STS;                     /**< FrameCap Status Register. Shows current status of the FrameCap module., offset: 0x14820 */
  __O  uint32_t FRAMECAP4_STSCLR;                  /**< FrameCap Status Clear Register. Clears the locked status bits in Sts register., offset: 0x14824 */
  __I  uint32_t FRAMECAP4_FRCNT;                   /**< FrameCap Frame Rate Count Register., offset: 0x14828 */
  __I  uint32_t FRAMECAP4_FRLINECOUNT;             /**< FrameCap Line Counter register., offset: 0x1482C */
       uint8_t RESERVED_133[976];
  __I  uint32_t FRAMECAP5_LOCKUNLOCK;              /**< Register to change the protection status of this address block., offset: 0x14C00 */
  __I  uint32_t FRAMECAP5_LOCKSTATUS;              /**< Protection status of this address block., offset: 0x14C04 */
  __IO uint32_t FRAMECAP5_CTR;                     /**< FrameCap Control Register, offset: 0x14C08 */
  __IO uint32_t FRAMECAP5_SPR;                     /**< FrameCap Sync Polarity Register, offset: 0x14C0C */
  __IO uint32_t FRAMECAP5_FDR;                     /**< Frame dimension (progressive frame and field 0)., offset: 0x14C10 */
  __IO uint32_t FRAMECAP5_FDR1;                    /**< Frame dimension (field 1)., offset: 0x14C14 */
  __IO uint32_t FRAMECAP5_KCR;                     /**< FrameCap Kick Config Register, offset: 0x14C18 */
  __IO uint32_t FRAMECAP5_SCR;                     /**< FrameCap Sync Config Register, offset: 0x14C1C */
  __I  uint32_t FRAMECAP5_STS;                     /**< FrameCap Status Register. Shows current status of the FrameCap module., offset: 0x14C20 */
  __O  uint32_t FRAMECAP5_STSCLR;                  /**< FrameCap Status Clear Register. Clears the locked status bits in Sts register., offset: 0x14C24 */
  __I  uint32_t FRAMECAP5_FRCNT;                   /**< FrameCap Frame Rate Count Register., offset: 0x14C28 */
  __I  uint32_t FRAMECAP5_FRLINECOUNT;             /**< FrameCap Line Counter register., offset: 0x14C2C */
       uint8_t RESERVED_134[976];
  __IO uint32_t ANALYSER4_MON_RGB_CTRL;            /**< Configuration of the RGB sync signals and timing., offset: 0x15000 */
  __IO uint32_t ANALYSER4_MON_THRESH_TIM;          /**< Configures threshold for stability and jitter check., offset: 0x15004 */
  __IO uint32_t ANALYSER4_MON_THRESH_POL;          /**< Configures the threshold for polarity detection., offset: 0x15008 */
  __IO uint32_t ANALYSER4_MON_THRESH_MODE;         /**< Configures the threshold for mode detection., offset: 0x1500C */
  __IO uint32_t ANALYSER4_MON_MODE_STATUS;         /**< Shows the detected mode of the RGB sync signals., offset: 0x15010 */
  __IO uint32_t ANALYSER4_MON_POL_STATUS;          /**< Shows the detected polarity of the RGB sync signals., offset: 0x15014 */
  __I  uint32_t ANALYSER4_MON_STATUS;              /**< Shows the stability/jitter of horizontal/vertical total and active parameters., offset: 0x15018 */
  __I  uint32_t ANALYSER4_MON_VAL_HTOTAL;          /**< Detected timing parameter horizontal total pixel., offset: 0x1501C */
  __I  uint32_t ANALYSER4_MON_VAL_HACTIVE;         /**< Detected timing parameter horizontal active pixels., offset: 0x15020 */
  __I  uint32_t ANALYSER4_MON_VAL_HBACK;           /**< Detected timing parameter horizontal back porch., offset: 0x15024 */
  __I  uint32_t ANALYSER4_TIM_VAL_HFRONT;          /**< Detected timing parameter horizontal front porch., offset: 0x15028 */
  __I  uint32_t ANALYSER4_MON_VAL_VTOTAL;          /**< Detected timing parameter vertical total lines., offset: 0x1502C */
  __I  uint32_t ANALYSER4_MON_VAL_VACTIVE;         /**< Detected timing parameter vertical active lines., offset: 0x15030 */
  __I  uint32_t ANALYSER4_MON_VAL_VBACK;           /**< Detected timing parameter vertical back porch., offset: 0x15034 */
  __I  uint32_t ANALYSER4_MON_VAL_VFRONT;          /**< Detected timing parameter vertical front porch., offset: 0x15038 */
  __I  uint32_t ANALYSER4_MON_VAL_TOTAL_CLK;       /**< Detected timing parameter total clocks., offset: 0x1503C */
  __IO uint32_t ANALYSER4_MON_PIXEL_CTRL;          /**< Configure RGB pixel observation., offset: 0x15040 */
  __I  uint32_t ANALYSER4_MON_PIXEL_STAT;          /**< Status RGB pixel observation., offset: 0x15044 */
  __IO uint32_t ANALYSER4_MON_WATCHDOG_TOUT;       /**< Configure sync-activity timeout (watchdog)., offset: 0x15048 */
  __IO uint32_t ANALYSER4_MON_WATCHDOG_STAT;       /**< Detected timing parameter total clocks., offset: 0x1504C */
       uint8_t RESERVED_135[944];
  __IO uint32_t ANALYSER5_MON_RGB_CTRL;            /**< Configuration of the RGB sync signals and timing., offset: 0x15400 */
  __IO uint32_t ANALYSER5_MON_THRESH_TIM;          /**< Configures threshold for stability and jitter check., offset: 0x15404 */
  __IO uint32_t ANALYSER5_MON_THRESH_POL;          /**< Configures the threshold for polarity detection., offset: 0x15408 */
  __IO uint32_t ANALYSER5_MON_THRESH_MODE;         /**< Configures the threshold for mode detection., offset: 0x1540C */
  __IO uint32_t ANALYSER5_MON_MODE_STATUS;         /**< Shows the detected mode of the RGB sync signals., offset: 0x15410 */
  __IO uint32_t ANALYSER5_MON_POL_STATUS;          /**< Shows the detected polarity of the RGB sync signals., offset: 0x15414 */
  __I  uint32_t ANALYSER5_MON_STATUS;              /**< Shows the stability/jitter of horizontal/vertical total and active parameters., offset: 0x15418 */
  __I  uint32_t ANALYSER5_MON_VAL_HTOTAL;          /**< Detected timing parameter horizontal total pixel., offset: 0x1541C */
  __I  uint32_t ANALYSER5_MON_VAL_HACTIVE;         /**< Detected timing parameter horizontal active pixels., offset: 0x15420 */
  __I  uint32_t ANALYSER5_MON_VAL_HBACK;           /**< Detected timing parameter horizontal back porch., offset: 0x15424 */
  __I  uint32_t ANALYSER5_TIM_VAL_HFRONT;          /**< Detected timing parameter horizontal front porch., offset: 0x15428 */
  __I  uint32_t ANALYSER5_MON_VAL_VTOTAL;          /**< Detected timing parameter vertical total lines., offset: 0x1542C */
  __I  uint32_t ANALYSER5_MON_VAL_VACTIVE;         /**< Detected timing parameter vertical active lines., offset: 0x15430 */
  __I  uint32_t ANALYSER5_MON_VAL_VBACK;           /**< Detected timing parameter vertical back porch., offset: 0x15434 */
  __I  uint32_t ANALYSER5_MON_VAL_VFRONT;          /**< Detected timing parameter vertical front porch., offset: 0x15438 */
  __I  uint32_t ANALYSER5_MON_VAL_TOTAL_CLK;       /**< Detected timing parameter total clocks., offset: 0x1543C */
  __IO uint32_t ANALYSER5_MON_PIXEL_CTRL;          /**< Configure RGB pixel observation., offset: 0x15440 */
  __I  uint32_t ANALYSER5_MON_PIXEL_STAT;          /**< Status RGB pixel observation., offset: 0x15444 */
  __IO uint32_t ANALYSER5_MON_WATCHDOG_TOUT;       /**< Configure sync-activity timeout (watchdog)., offset: 0x15448 */
  __IO uint32_t ANALYSER5_MON_WATCHDOG_STAT;       /**< Detected timing parameter total clocks., offset: 0x1544C */
       uint8_t RESERVED_136[944];
  __IO uint32_t DPUXPC_CONTROL;                    /**< , offset: 0x15800 */
  __IO uint32_t DPUXPC_TIMER;                      /**< , offset: 0x15804 */
  __IO uint32_t DPUXPC_MEASUREMENTTIMECONTROL;     /**< , offset: 0x15808 */
  __I  uint32_t DPUXPC_SW_TAG;                     /**< , offset: 0x1580C */
  __I  uint32_t DPUXPC_MEASUREMENTTIME;            /**< , offset: 0x15810 */
  __I  uint32_t DPUXPC_GLOBAL_COUNTER;             /**< , offset: 0x15814 */
  __IO uint32_t DPUXPC_MU00_SWITCH;                /**< , offset: 0x15818 */
  __I  uint32_t DPUXPC_MU00_DATA_COUNTER;          /**< , offset: 0x1581C */
  __I  uint32_t DPUXPC_MU00_BUSY_COUNTER;          /**< , offset: 0x15820 */
  __I  uint32_t DPUXPC_MU00_TRANSFER_COUNTER;      /**< , offset: 0x15824 */
  __I  uint32_t DPUXPC_MU00_ADDRBUSY_COUNTER;      /**< , offset: 0x15828 */
  __I  uint32_t DPUXPC_MU00_LATENCY_COUNTER;       /**< , offset: 0x1582C */
  __IO uint32_t DPUXPC_MU01_SWITCH;                /**< , offset: 0x15830 */
  __I  uint32_t DPUXPC_MU01_DATA_COUNTER;          /**< , offset: 0x15834 */
  __I  uint32_t DPUXPC_MU01_BUSY_COUNTER;          /**< , offset: 0x15838 */
  __I  uint32_t DPUXPC_MU01_TRANSFER_COUNTER;      /**< , offset: 0x1583C */
  __I  uint32_t DPUXPC_MU01_ADDRBUSY_COUNTER;      /**< , offset: 0x15840 */
  __I  uint32_t DPUXPC_MU01_LATENCY_COUNTER;       /**< , offset: 0x15844 */
  __IO uint32_t DPUXPC_MU02_SWITCH;                /**< , offset: 0x15848 */
  __I  uint32_t DPUXPC_MU02_DATA_COUNTER;          /**< , offset: 0x1584C */
  __I  uint32_t DPUXPC_MU02_BUSY_COUNTER;          /**< , offset: 0x15850 */
  __I  uint32_t DPUXPC_MU02_TRANSFER_COUNTER;      /**< , offset: 0x15854 */
  __I  uint32_t DPUXPC_MU02_ADDRBUSY_COUNTER;      /**< , offset: 0x15858 */
  __I  uint32_t DPUXPC_MU02_LATENCY_COUNTER;       /**< , offset: 0x1585C */
  __IO uint32_t DPUXPC_MU03_SWITCH;                /**< , offset: 0x15860 */
  __I  uint32_t DPUXPC_MU03_DATA_COUNTER;          /**< , offset: 0x15864 */
  __I  uint32_t DPUXPC_MU03_BUSY_COUNTER;          /**< , offset: 0x15868 */
  __I  uint32_t DPUXPC_MU03_TRANSFER_COUNTER;      /**< , offset: 0x1586C */
  __I  uint32_t DPUXPC_MU03_ADDRBUSY_COUNTER;      /**< , offset: 0x15870 */
  __I  uint32_t DPUXPC_MU03_LATENCY_COUNTER;       /**< , offset: 0x15874 */
  __IO uint32_t DPUXPC_MU04_SWITCH;                /**< , offset: 0x15878 */
  __I  uint32_t DPUXPC_MU04_DATA_COUNTER;          /**< , offset: 0x1587C */
  __I  uint32_t DPUXPC_MU04_BUSY_COUNTER;          /**< , offset: 0x15880 */
  __I  uint32_t DPUXPC_MU04_TRANSFER_COUNTER;      /**< , offset: 0x15884 */
  __I  uint32_t DPUXPC_MU04_ADDRBUSY_COUNTER;      /**< , offset: 0x15888 */
  __I  uint32_t DPUXPC_MU04_LATENCY_COUNTER;       /**< , offset: 0x1588C */
} IRIS_MVPL_Type;

/* ----------------------------------------------------------------------------
   -- IRIS_MVPL Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IRIS_MVPL_Register_Masks IRIS_MVPL Register Masks
 * @{
 */

/*! @name COMCTRL_IPIDENTIFIER - IP Identifier for this IMX DPU derivate. */
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_DesignDeliveryID_MASK (0xF0U)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_DesignDeliveryID_SHIFT (4U)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_DesignDeliveryID(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_IPIDENTIFIER_DesignDeliveryID_SHIFT)) & IRIS_MVPL_COMCTRL_IPIDENTIFIER_DesignDeliveryID_MASK)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_DesignMaturityLevel_MASK (0xF00U)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_DesignMaturityLevel_SHIFT (8U)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_DesignMaturityLevel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_IPIDENTIFIER_DesignMaturityLevel_SHIFT)) & IRIS_MVPL_COMCTRL_IPIDENTIFIER_DesignMaturityLevel_MASK)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPEvolution_MASK (0xF000U)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPEvolution_SHIFT (12U)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPEvolution(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPEvolution_SHIFT)) & IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPEvolution_MASK)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPFeatureSet_MASK (0xF0000U)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPFeatureSet_SHIFT (16U)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPFeatureSet(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPFeatureSet_SHIFT)) & IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPFeatureSet_MASK)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPApplication_MASK (0xF00000U)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPApplication_SHIFT (20U)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPApplication(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPApplication_SHIFT)) & IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPApplication_MASK)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPConfiguration_MASK (0xF000000U)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPConfiguration_SHIFT (24U)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPConfiguration(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPConfiguration_SHIFT)) & IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPConfiguration_MASK)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPFamily_MASK (0xF0000000U)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPFamily_SHIFT (28U)
#define IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPFamily(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPFamily_SHIFT)) & IRIS_MVPL_COMCTRL_IPIDENTIFIER_IPFamily_MASK)

/*! @name COMCTRL_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock_MASK)

/*! @name COMCTRL_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus_MASK)

/*! @name COMCTRL_USERINTERRUPTMASK0 - Interrupt UserMask register 0 */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0_MASK)

/*! @name COMCTRL_USERINTERRUPTMASK1 - Interrupt UserMask register 1 */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1_MASK)

/*! @name COMCTRL_USERINTERRUPTMASK2 - Interrupt UserMask register 2 */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK2_UserInterruptMask2_MASK (0x7U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK2_UserInterruptMask2_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK2_UserInterruptMask2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTMASK2_UserInterruptMask2_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTMASK2_UserInterruptMask2_MASK)

/*! @name COMCTRL_INTERRUPTENABLE0 - Interrupt Enable register 0 */
#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK)

/*! @name COMCTRL_INTERRUPTENABLE1 - Interrupt Enable register 1 */
#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1_MASK)

/*! @name COMCTRL_INTERRUPTENABLE2 - Interrupt Enable register 2 */
#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE2_InterruptEnable2_MASK (0x7U)
#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE2_InterruptEnable2_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE2_InterruptEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTENABLE2_InterruptEnable2_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE2_InterruptEnable2_MASK)

/*! @name COMCTRL_INTERRUPTPRESET0 - Interrupt Preset register 0 */
#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0_MASK)

/*! @name COMCTRL_INTERRUPTPRESET1 - Interrupt Preset register 1 */
#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1_MASK)

/*! @name COMCTRL_INTERRUPTPRESET2 - Interrupt Preset register 2 */
#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET2_InterruptPreset2_MASK (0x7U)
#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET2_InterruptPreset2_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET2_InterruptPreset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTPRESET2_InterruptPreset2_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTPRESET2_InterruptPreset2_MASK)

/*! @name COMCTRL_INTERRUPTCLEAR0 - Interrupt Clear register 0 */
#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0_MASK)

/*! @name COMCTRL_INTERRUPTCLEAR1 - Interrupt Clear register 1 */
#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1_MASK)

/*! @name COMCTRL_INTERRUPTCLEAR2 - Interrupt Clear register 2 */
#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR2_InterruptClear2_MASK (0x7U)
#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR2_InterruptClear2_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR2_InterruptClear2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTCLEAR2_InterruptClear2_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTCLEAR2_InterruptClear2_MASK)

/*! @name COMCTRL_INTERRUPTSTATUS0 - Interrupt Status register 0 */
#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0_MASK)

/*! @name COMCTRL_INTERRUPTSTATUS1 - Interrupt Status register 1 */
#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1_MASK)

/*! @name COMCTRL_INTERRUPTSTATUS2 - Interrupt Status register 2 */
#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS2_InterruptStatus2_MASK (0x7U)
#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS2_InterruptStatus2_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS2_InterruptStatus2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTSTATUS2_InterruptStatus2_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTSTATUS2_InterruptStatus2_MASK)

/*! @name COMCTRL_USERINTERRUPTENABLE0 - Interrupt Enable register 0 for user mode access */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE0_UserInterruptEnable0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE0_UserInterruptEnable0_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE0_UserInterruptEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE0_UserInterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE0_UserInterruptEnable0_MASK)

/*! @name COMCTRL_USERINTERRUPTENABLE1 - Interrupt Enable register 1 for user mode access */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE1_UserInterruptEnable1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE1_UserInterruptEnable1_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE1_UserInterruptEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE1_UserInterruptEnable1_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE1_UserInterruptEnable1_MASK)

/*! @name COMCTRL_USERINTERRUPTENABLE2 - Interrupt Enable register 2 for user mode access */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE2_UserInterruptEnable2_MASK (0x7U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE2_UserInterruptEnable2_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE2_UserInterruptEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE2_UserInterruptEnable2_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTENABLE2_UserInterruptEnable2_MASK)

/*! @name COMCTRL_USERINTERRUPTPRESET0 - Interrupt Preset register 0 */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET0_UserInterruptPreset0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET0_UserInterruptPreset0_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET0_UserInterruptPreset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET0_UserInterruptPreset0_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET0_UserInterruptPreset0_MASK)

/*! @name COMCTRL_USERINTERRUPTPRESET1 - Interrupt Preset register 1 */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET1_UserInterruptPreset1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET1_UserInterruptPreset1_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET1_UserInterruptPreset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET1_UserInterruptPreset1_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET1_UserInterruptPreset1_MASK)

/*! @name COMCTRL_USERINTERRUPTPRESET2 - Interrupt Preset register 2 */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET2_UserInterruptPreset2_MASK (0x7U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET2_UserInterruptPreset2_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET2_UserInterruptPreset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET2_UserInterruptPreset2_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTPRESET2_UserInterruptPreset2_MASK)

/*! @name COMCTRL_USERINTERRUPTCLEAR0 - Interrupt Clear register 0 */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR0_UserInterruptClear0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR0_UserInterruptClear0_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR0_UserInterruptClear0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR0_UserInterruptClear0_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR0_UserInterruptClear0_MASK)

/*! @name COMCTRL_USERINTERRUPTCLEAR1 - Interrupt Clear register 1 */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR1_UserInterruptClear1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR1_UserInterruptClear1_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR1_UserInterruptClear1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR1_UserInterruptClear1_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR1_UserInterruptClear1_MASK)

/*! @name COMCTRL_USERINTERRUPTCLEAR2 - Interrupt Clear register 2 */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR2_UserInterruptClear2_MASK (0x7U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR2_UserInterruptClear2_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR2_UserInterruptClear2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR2_UserInterruptClear2_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTCLEAR2_UserInterruptClear2_MASK)

/*! @name COMCTRL_USERINTERRUPTSTATUS0 - Interrupt Status register 0 */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS0_UserInterruptStatus0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS0_UserInterruptStatus0_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS0_UserInterruptStatus0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS0_UserInterruptStatus0_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS0_UserInterruptStatus0_MASK)

/*! @name COMCTRL_USERINTERRUPTSTATUS1 - Interrupt Status register 1 */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS1_UserInterruptStatus1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS1_UserInterruptStatus1_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS1_UserInterruptStatus1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS1_UserInterruptStatus1_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS1_UserInterruptStatus1_MASK)

/*! @name COMCTRL_USERINTERRUPTSTATUS2 - Interrupt Status register 2 */
#define IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS2_UserInterruptStatus2_MASK (0x7U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS2_UserInterruptStatus2_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS2_UserInterruptStatus2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS2_UserInterruptStatus2_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTSTATUS2_UserInterruptStatus2_MASK)

/*! @name COMCTRL_GENERALPURPOSE - General purpose config memory */
#define IRIS_MVPL_COMCTRL_GENERALPURPOSE_GeneralPurpose_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_COMCTRL_GENERALPURPOSE_GeneralPurpose_SHIFT (0U)
#define IRIS_MVPL_COMCTRL_GENERALPURPOSE_GeneralPurpose(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_GENERALPURPOSE_GeneralPurpose_SHIFT)) & IRIS_MVPL_COMCTRL_GENERALPURPOSE_GeneralPurpose_MASK)

/*! @name CMDSEQ_HIF - Command input buffer */
#define IRIS_MVPL_CMDSEQ_HIF_CommandFIFO_MASK    (0xFFFFFFFFU)
#define IRIS_MVPL_CMDSEQ_HIF_CommandFIFO_SHIFT   (0U)
#define IRIS_MVPL_CMDSEQ_HIF_CommandFIFO(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_HIF_CommandFIFO_SHIFT)) & IRIS_MVPL_CMDSEQ_HIF_CommandFIFO_MASK)

/*! @name CMDSEQ_LOCKUNLOCKHIF - Register to change the protection status of this address block. */
#define IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF_SHIFT (0U)
#define IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF_MASK)

/*! @name CMDSEQ_LOCKSTATUSHIF - Protection status of this address block. */
#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF_MASK (0x1U)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF_SHIFT (0U)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF_MASK)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF_MASK (0x10U)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF_SHIFT (4U)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF_MASK)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF_MASK (0x100U)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF_SHIFT (8U)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF_MASK)

/*! @name CMDSEQ_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock_MASK)

/*! @name CMDSEQ_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus_MASK)

/*! @name CMDSEQ_BUFFERADDRESS - Command buffer address register */
#define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local_MASK (0x1U)
#define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local_SHIFT (0U)
#define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local_SHIFT)) & IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local_MASK)
#define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr_MASK (0xFFFFFFE0U)
#define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr_SHIFT (5U)
#define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr_SHIFT)) & IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr_MASK)

/*! @name CMDSEQ_BUFFERSIZE - Command buffer size register */
#define IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size_MASK    (0xFFF8U)
#define IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size_SHIFT   (3U)
#define IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size_SHIFT)) & IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size_MASK)

/*! @name CMDSEQ_WATERMARKCONTROL - Watermark Control register */
#define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM_MASK (0xFFFFU)
#define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM_SHIFT (0U)
#define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM_SHIFT)) & IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM_MASK)
#define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM_MASK (0xFFFF0000U)
#define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM_SHIFT (16U)
#define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM_SHIFT)) & IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM_MASK)

/*! @name CMDSEQ_CONTROL - Control register */
#define IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw_MASK    (0x1U)
#define IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw_SHIFT   (0U)
#define IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw_SHIFT)) & IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw_MASK)
#define IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf_MASK    (0x4U)
#define IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf_SHIFT   (2U)
#define IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf_SHIFT)) & IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf_MASK)
#define IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf_MASK  (0x8U)
#define IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf_SHIFT (3U)
#define IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf_SHIFT)) & IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf_MASK)
#define IRIS_MVPL_CMDSEQ_CONTROL_Clear_MASK      (0x80000000U)
#define IRIS_MVPL_CMDSEQ_CONTROL_Clear_SHIFT     (31U)
#define IRIS_MVPL_CMDSEQ_CONTROL_Clear(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_CONTROL_Clear_SHIFT)) & IRIS_MVPL_CMDSEQ_CONTROL_Clear_MASK)

/*! @name CMDSEQ_STATUS - Status register */
#define IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace_MASK   (0x1FFFFU)
#define IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace_SHIFT  (0U)
#define IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace_MASK)
#define IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty_MASK   (0x1000000U)
#define IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty_SHIFT  (24U)
#define IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty_MASK)
#define IRIS_MVPL_CMDSEQ_STATUS_FIFOFull_MASK    (0x2000000U)
#define IRIS_MVPL_CMDSEQ_STATUS_FIFOFull_SHIFT   (25U)
#define IRIS_MVPL_CMDSEQ_STATUS_FIFOFull(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_FIFOFull_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_FIFOFull_MASK)
#define IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState_MASK (0x4000000U)
#define IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState_SHIFT (26U)
#define IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState_MASK)
#define IRIS_MVPL_CMDSEQ_STATUS_Watchdog_MASK    (0x8000000U)
#define IRIS_MVPL_CMDSEQ_STATUS_Watchdog_SHIFT   (27U)
#define IRIS_MVPL_CMDSEQ_STATUS_Watchdog(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_Watchdog_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_Watchdog_MASK)
#define IRIS_MVPL_CMDSEQ_STATUS_ReadBusy_MASK    (0x10000000U)
#define IRIS_MVPL_CMDSEQ_STATUS_ReadBusy_SHIFT   (28U)
#define IRIS_MVPL_CMDSEQ_STATUS_ReadBusy(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_ReadBusy_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_ReadBusy_MASK)
#define IRIS_MVPL_CMDSEQ_STATUS_WriteBusy_MASK   (0x20000000U)
#define IRIS_MVPL_CMDSEQ_STATUS_WriteBusy_SHIFT  (29U)
#define IRIS_MVPL_CMDSEQ_STATUS_WriteBusy(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_WriteBusy_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_WriteBusy_MASK)
#define IRIS_MVPL_CMDSEQ_STATUS_Idle_MASK        (0x40000000U)
#define IRIS_MVPL_CMDSEQ_STATUS_Idle_SHIFT       (30U)
#define IRIS_MVPL_CMDSEQ_STATUS_Idle(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_Idle_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_Idle_MASK)
#define IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt_MASK   (0x80000000U)
#define IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt_SHIFT  (31U)
#define IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt_MASK)

/*! @name CMDSEQ_PREFETCHWINDOWSTART - PrefetchWindowStart register */
#define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart_MASK (0xFFFFFFFCU)
#define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart_SHIFT (2U)
#define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart_SHIFT)) & IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart_MASK)

/*! @name CMDSEQ_PREFETCHWINDOWEND - PrefetchWindowEnd register */
#define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd_MASK (0xFFFFFFFCU)
#define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd_SHIFT (2U)
#define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd_SHIFT)) & IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd_MASK)

/*! @name PIXENGCFG_SAFETYLOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_SAFETYLOCKUNLOCK_SafetyLockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_SAFETYLOCKUNLOCK_SafetyLockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_SAFETYLOCKUNLOCK_SafetyLockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_SAFETYLOCKUNLOCK_SafetyLockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_SAFETYLOCKUNLOCK_SafetyLockUnlock_MASK)

/*! @name PIXENGCFG_SAFETYLOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyLockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyLockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyLockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyLockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyLockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyPrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyPrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyPrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyPrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyPrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyFreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyFreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyFreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyFreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_SAFETYLOCKSTATUS_SafetyFreezeStatus_MASK)

/*! @name PIXENGCFG_STORE9_SAFETYMASK_0 - Safety mask 0 for store9 */
#define IRIS_MVPL_PIXENGCFG_STORE9_SAFETYMASK_0_store9_SafetyMask_0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_STORE9_SAFETYMASK_0_store9_SafetyMask_0_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE9_SAFETYMASK_0_store9_SafetyMask_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_SAFETYMASK_0_store9_SafetyMask_0_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_SAFETYMASK_0_store9_SafetyMask_0_MASK)

/*! @name PIXENGCFG_STORE9_SAFETYMASK_1 - Safety mask 1 for store9 */
#define IRIS_MVPL_PIXENGCFG_STORE9_SAFETYMASK_1_store9_SafetyMask_1_MASK (0x7FFU)
#define IRIS_MVPL_PIXENGCFG_STORE9_SAFETYMASK_1_store9_SafetyMask_1_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE9_SAFETYMASK_1_store9_SafetyMask_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_SAFETYMASK_1_store9_SafetyMask_1_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_SAFETYMASK_1_store9_SafetyMask_1_MASK)

/*! @name PIXENGCFG_EXTDST0_SAFETYMASK_0 - Safety mask 0 for extdst0 */
#define IRIS_MVPL_PIXENGCFG_EXTDST0_SAFETYMASK_0_extdst0_SafetyMask_0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_SAFETYMASK_0_extdst0_SafetyMask_0_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_SAFETYMASK_0_extdst0_SafetyMask_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_SAFETYMASK_0_extdst0_SafetyMask_0_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_SAFETYMASK_0_extdst0_SafetyMask_0_MASK)

/*! @name PIXENGCFG_EXTDST0_SAFETYMASK_1 - Safety mask 1 for extdst0 */
#define IRIS_MVPL_PIXENGCFG_EXTDST0_SAFETYMASK_1_extdst0_SafetyMask_1_MASK (0x7FFU)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_SAFETYMASK_1_extdst0_SafetyMask_1_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_SAFETYMASK_1_extdst0_SafetyMask_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_SAFETYMASK_1_extdst0_SafetyMask_1_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_SAFETYMASK_1_extdst0_SafetyMask_1_MASK)

/*! @name PIXENGCFG_EXTDST4_SAFETYMASK_0 - Safety mask 0 for extdst4 */
#define IRIS_MVPL_PIXENGCFG_EXTDST4_SAFETYMASK_0_extdst4_SafetyMask_0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_SAFETYMASK_0_extdst4_SafetyMask_0_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_SAFETYMASK_0_extdst4_SafetyMask_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_SAFETYMASK_0_extdst4_SafetyMask_0_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_SAFETYMASK_0_extdst4_SafetyMask_0_MASK)

/*! @name PIXENGCFG_EXTDST4_SAFETYMASK_1 - Safety mask 1 for extdst4 */
#define IRIS_MVPL_PIXENGCFG_EXTDST4_SAFETYMASK_1_extdst4_SafetyMask_1_MASK (0x7FFU)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_SAFETYMASK_1_extdst4_SafetyMask_1_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_SAFETYMASK_1_extdst4_SafetyMask_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_SAFETYMASK_1_extdst4_SafetyMask_1_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_SAFETYMASK_1_extdst4_SafetyMask_1_MASK)

/*! @name PIXENGCFG_EXTDST1_SAFETYMASK_0 - Safety mask 0 for extdst1 */
#define IRIS_MVPL_PIXENGCFG_EXTDST1_SAFETYMASK_0_extdst1_SafetyMask_0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_SAFETYMASK_0_extdst1_SafetyMask_0_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_SAFETYMASK_0_extdst1_SafetyMask_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_SAFETYMASK_0_extdst1_SafetyMask_0_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_SAFETYMASK_0_extdst1_SafetyMask_0_MASK)

/*! @name PIXENGCFG_EXTDST1_SAFETYMASK_1 - Safety mask 1 for extdst1 */
#define IRIS_MVPL_PIXENGCFG_EXTDST1_SAFETYMASK_1_extdst1_SafetyMask_1_MASK (0x7FFU)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_SAFETYMASK_1_extdst1_SafetyMask_1_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_SAFETYMASK_1_extdst1_SafetyMask_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_SAFETYMASK_1_extdst1_SafetyMask_1_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_SAFETYMASK_1_extdst1_SafetyMask_1_MASK)

/*! @name PIXENGCFG_EXTDST5_SAFETYMASK_0 - Safety mask 0 for extdst5 */
#define IRIS_MVPL_PIXENGCFG_EXTDST5_SAFETYMASK_0_extdst5_SafetyMask_0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_SAFETYMASK_0_extdst5_SafetyMask_0_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_SAFETYMASK_0_extdst5_SafetyMask_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_SAFETYMASK_0_extdst5_SafetyMask_0_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_SAFETYMASK_0_extdst5_SafetyMask_0_MASK)

/*! @name PIXENGCFG_EXTDST5_SAFETYMASK_1 - Safety mask 1 for extdst5 */
#define IRIS_MVPL_PIXENGCFG_EXTDST5_SAFETYMASK_1_extdst5_SafetyMask_1_MASK (0x7FFU)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_SAFETYMASK_1_extdst5_SafetyMask_1_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_SAFETYMASK_1_extdst5_SafetyMask_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_SAFETYMASK_1_extdst5_SafetyMask_1_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_SAFETYMASK_1_extdst5_SafetyMask_1_MASK)

/*! @name PIXENGCFG_STORE4_SAFETYMASK_0 - Safety mask 0 for store4 */
#define IRIS_MVPL_PIXENGCFG_STORE4_SAFETYMASK_0_store4_SafetyMask_0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_STORE4_SAFETYMASK_0_store4_SafetyMask_0_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE4_SAFETYMASK_0_store4_SafetyMask_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_SAFETYMASK_0_store4_SafetyMask_0_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_SAFETYMASK_0_store4_SafetyMask_0_MASK)

/*! @name PIXENGCFG_STORE4_SAFETYMASK_1 - Safety mask 1 for store4 */
#define IRIS_MVPL_PIXENGCFG_STORE4_SAFETYMASK_1_store4_SafetyMask_1_MASK (0x7FFU)
#define IRIS_MVPL_PIXENGCFG_STORE4_SAFETYMASK_1_store4_SafetyMask_1_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE4_SAFETYMASK_1_store4_SafetyMask_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_SAFETYMASK_1_store4_SafetyMask_1_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_SAFETYMASK_1_store4_SafetyMask_1_MASK)

/*! @name PIXENGCFG_STORE5_SAFETYMASK_0 - Safety mask 0 for store5 */
#define IRIS_MVPL_PIXENGCFG_STORE5_SAFETYMASK_0_store5_SafetyMask_0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_STORE5_SAFETYMASK_0_store5_SafetyMask_0_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE5_SAFETYMASK_0_store5_SafetyMask_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_SAFETYMASK_0_store5_SafetyMask_0_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_SAFETYMASK_0_store5_SafetyMask_0_MASK)

/*! @name PIXENGCFG_STORE5_SAFETYMASK_1 - Safety mask 1 for store5 */
#define IRIS_MVPL_PIXENGCFG_STORE5_SAFETYMASK_1_store5_SafetyMask_1_MASK (0x7FFU)
#define IRIS_MVPL_PIXENGCFG_STORE5_SAFETYMASK_1_store5_SafetyMask_1_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE5_SAFETYMASK_1_store5_SafetyMask_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_SAFETYMASK_1_store5_SafetyMask_1_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_SAFETYMASK_1_store5_SafetyMask_1_MASK)

/*! @name PIXENGCFG_FETCHDECODE9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_fetchdecode9_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_fetchdecode9_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_fetchdecode9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_fetchdecode9_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_fetchdecode9_LockUnlock_MASK)

/*! @name PIXENGCFG_FETCHDECODE9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_fetchdecode9_FreezeStatus_MASK)

/*! @name PIXENGCFG_FETCHDECODE9_DYNAMIC - Dynamic pixel engine configuration for fetchdecode9 */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_DYNAMIC_fetchdecode9_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_DYNAMIC_fetchdecode9_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_DYNAMIC_fetchdecode9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE9_DYNAMIC_fetchdecode9_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE9_DYNAMIC_fetchdecode9_src_sel_MASK)

/*! @name PIXENGCFG_FETCHDECODE9_STATUS - Status information for pixel engine configuration of fetchdecode9 */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_STATUS_fetchdecode9_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_STATUS_fetchdecode9_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE9_STATUS_fetchdecode9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE9_STATUS_fetchdecode9_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE9_STATUS_fetchdecode9_sel_MASK)

/*! @name PIXENGCFG_FETCHPERSP9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKUNLOCK_fetchpersp9_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKUNLOCK_fetchpersp9_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKUNLOCK_fetchpersp9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKUNLOCK_fetchpersp9_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKUNLOCK_fetchpersp9_LockUnlock_MASK)

/*! @name PIXENGCFG_FETCHPERSP9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHPERSP9_LOCKSTATUS_fetchpersp9_FreezeStatus_MASK)

/*! @name PIXENGCFG_FETCHPERSP9_DYNAMIC - Dynamic pixel engine configuration for fetchpersp9 */
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_DYNAMIC_fetchpersp9_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_DYNAMIC_fetchpersp9_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_DYNAMIC_fetchpersp9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHPERSP9_DYNAMIC_fetchpersp9_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHPERSP9_DYNAMIC_fetchpersp9_src_sel_MASK)

/*! @name PIXENGCFG_FETCHPERSP9_STATUS - Status information for pixel engine configuration of fetchpersp9 */
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_STATUS_fetchpersp9_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_STATUS_fetchpersp9_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_FETCHPERSP9_STATUS_fetchpersp9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHPERSP9_STATUS_fetchpersp9_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHPERSP9_STATUS_fetchpersp9_sel_MASK)

/*! @name PIXENGCFG_FETCHECO9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKUNLOCK_fetcheco9_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKUNLOCK_fetcheco9_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKUNLOCK_fetcheco9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKUNLOCK_fetcheco9_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKUNLOCK_fetcheco9_LockUnlock_MASK)

/*! @name PIXENGCFG_FETCHECO9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO9_LOCKSTATUS_fetcheco9_FreezeStatus_MASK)

/*! @name PIXENGCFG_FETCHECO9_STATUS - Status information for pixel engine configuration of fetcheco9 */
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_STATUS_fetcheco9_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_STATUS_fetcheco9_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO9_STATUS_fetcheco9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO9_STATUS_fetcheco9_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO9_STATUS_fetcheco9_sel_MASK)

/*! @name PIXENGCFG_ROP9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_ROP9_LOCKUNLOCK_rop9_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_ROP9_LOCKUNLOCK_rop9_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_ROP9_LOCKUNLOCK_rop9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_ROP9_LOCKUNLOCK_rop9_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_ROP9_LOCKUNLOCK_rop9_LockUnlock_MASK)

/*! @name PIXENGCFG_ROP9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_ROP9_LOCKSTATUS_rop9_FreezeStatus_MASK)

/*! @name PIXENGCFG_ROP9_DYNAMIC - Dynamic pixel engine configuration for rop9 */
#define IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_prim_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_prim_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_prim_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_prim_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_sec_sel_MASK (0x3F00U)
#define IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_sec_sel_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_sec_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_sec_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_tert_sel_MASK (0x3F0000U)
#define IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_tert_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_tert_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_tert_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_tert_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_ROP9_DYNAMIC_rop9_clken_MASK)

/*! @name PIXENGCFG_ROP9_STATUS - Status information for pixel engine configuration of rop9 */
#define IRIS_MVPL_PIXENGCFG_ROP9_STATUS_rop9_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_ROP9_STATUS_rop9_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_ROP9_STATUS_rop9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_ROP9_STATUS_rop9_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_ROP9_STATUS_rop9_sel_MASK)

/*! @name PIXENGCFG_CLUT9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_CLUT9_LOCKUNLOCK_clut9_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_CLUT9_LOCKUNLOCK_clut9_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_CLUT9_LOCKUNLOCK_clut9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CLUT9_LOCKUNLOCK_clut9_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_CLUT9_LOCKUNLOCK_clut9_LockUnlock_MASK)

/*! @name PIXENGCFG_CLUT9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CLUT9_LOCKSTATUS_clut9_FreezeStatus_MASK)

/*! @name PIXENGCFG_CLUT9_DYNAMIC - Dynamic pixel engine configuration for clut9 */
#define IRIS_MVPL_PIXENGCFG_CLUT9_DYNAMIC_clut9_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_CLUT9_DYNAMIC_clut9_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_CLUT9_DYNAMIC_clut9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CLUT9_DYNAMIC_clut9_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_CLUT9_DYNAMIC_clut9_src_sel_MASK)

/*! @name PIXENGCFG_CLUT9_STATUS - Status information for pixel engine configuration of clut9 */
#define IRIS_MVPL_PIXENGCFG_CLUT9_STATUS_clut9_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_CLUT9_STATUS_clut9_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_CLUT9_STATUS_clut9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CLUT9_STATUS_clut9_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_CLUT9_STATUS_clut9_sel_MASK)

/*! @name PIXENGCFG_MATRIX9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKUNLOCK_matrix9_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKUNLOCK_matrix9_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKUNLOCK_matrix9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKUNLOCK_matrix9_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKUNLOCK_matrix9_LockUnlock_MASK)

/*! @name PIXENGCFG_MATRIX9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX9_LOCKSTATUS_matrix9_FreezeStatus_MASK)

/*! @name PIXENGCFG_MATRIX9_DYNAMIC - Dynamic pixel engine configuration for matrix9 */
#define IRIS_MVPL_PIXENGCFG_MATRIX9_DYNAMIC_matrix9_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_DYNAMIC_matrix9_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_DYNAMIC_matrix9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX9_DYNAMIC_matrix9_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX9_DYNAMIC_matrix9_src_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_DYNAMIC_matrix9_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_DYNAMIC_matrix9_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_DYNAMIC_matrix9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX9_DYNAMIC_matrix9_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX9_DYNAMIC_matrix9_clken_MASK)

/*! @name PIXENGCFG_MATRIX9_STATUS - Status information for pixel engine configuration of matrix9 */
#define IRIS_MVPL_PIXENGCFG_MATRIX9_STATUS_matrix9_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_STATUS_matrix9_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_MATRIX9_STATUS_matrix9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX9_STATUS_matrix9_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX9_STATUS_matrix9_sel_MASK)

/*! @name PIXENGCFG_HSCALER9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKUNLOCK_hscaler9_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKUNLOCK_hscaler9_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKUNLOCK_hscaler9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKUNLOCK_hscaler9_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKUNLOCK_hscaler9_LockUnlock_MASK)

/*! @name PIXENGCFG_HSCALER9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER9_LOCKSTATUS_hscaler9_FreezeStatus_MASK)

/*! @name PIXENGCFG_HSCALER9_DYNAMIC - Dynamic pixel engine configuration for hscaler9 */
#define IRIS_MVPL_PIXENGCFG_HSCALER9_DYNAMIC_hscaler9_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_DYNAMIC_hscaler9_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_DYNAMIC_hscaler9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER9_DYNAMIC_hscaler9_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER9_DYNAMIC_hscaler9_src_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_DYNAMIC_hscaler9_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_DYNAMIC_hscaler9_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_DYNAMIC_hscaler9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER9_DYNAMIC_hscaler9_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER9_DYNAMIC_hscaler9_clken_MASK)

/*! @name PIXENGCFG_HSCALER9_STATUS - Status information for pixel engine configuration of hscaler9 */
#define IRIS_MVPL_PIXENGCFG_HSCALER9_STATUS_hscaler9_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_STATUS_hscaler9_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_HSCALER9_STATUS_hscaler9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER9_STATUS_hscaler9_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER9_STATUS_hscaler9_sel_MASK)

/*! @name PIXENGCFG_VSCALER9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKUNLOCK_vscaler9_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKUNLOCK_vscaler9_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKUNLOCK_vscaler9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKUNLOCK_vscaler9_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKUNLOCK_vscaler9_LockUnlock_MASK)

/*! @name PIXENGCFG_VSCALER9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER9_LOCKSTATUS_vscaler9_FreezeStatus_MASK)

/*! @name PIXENGCFG_VSCALER9_DYNAMIC - Dynamic pixel engine configuration for vscaler9 */
#define IRIS_MVPL_PIXENGCFG_VSCALER9_DYNAMIC_vscaler9_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_DYNAMIC_vscaler9_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_DYNAMIC_vscaler9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER9_DYNAMIC_vscaler9_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER9_DYNAMIC_vscaler9_src_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_DYNAMIC_vscaler9_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_DYNAMIC_vscaler9_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_DYNAMIC_vscaler9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER9_DYNAMIC_vscaler9_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER9_DYNAMIC_vscaler9_clken_MASK)

/*! @name PIXENGCFG_VSCALER9_STATUS - Status information for pixel engine configuration of vscaler9 */
#define IRIS_MVPL_PIXENGCFG_VSCALER9_STATUS_vscaler9_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_STATUS_vscaler9_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_VSCALER9_STATUS_vscaler9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER9_STATUS_vscaler9_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER9_STATUS_vscaler9_sel_MASK)

/*! @name PIXENGCFG_FILTER9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FILTER9_LOCKUNLOCK_filter9_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_FILTER9_LOCKUNLOCK_filter9_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FILTER9_LOCKUNLOCK_filter9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FILTER9_LOCKUNLOCK_filter9_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_FILTER9_LOCKUNLOCK_filter9_LockUnlock_MASK)

/*! @name PIXENGCFG_FILTER9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FILTER9_LOCKSTATUS_filter9_FreezeStatus_MASK)

/*! @name PIXENGCFG_FILTER9_DYNAMIC - Dynamic pixel engine configuration for filter9 */
#define IRIS_MVPL_PIXENGCFG_FILTER9_DYNAMIC_filter9_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_FILTER9_DYNAMIC_filter9_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FILTER9_DYNAMIC_filter9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FILTER9_DYNAMIC_filter9_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FILTER9_DYNAMIC_filter9_src_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_FILTER9_DYNAMIC_filter9_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_FILTER9_DYNAMIC_filter9_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_FILTER9_DYNAMIC_filter9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FILTER9_DYNAMIC_filter9_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_FILTER9_DYNAMIC_filter9_clken_MASK)

/*! @name PIXENGCFG_FILTER9_STATUS - Status information for pixel engine configuration of filter9 */
#define IRIS_MVPL_PIXENGCFG_FILTER9_STATUS_filter9_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_FILTER9_STATUS_filter9_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_FILTER9_STATUS_filter9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FILTER9_STATUS_filter9_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FILTER9_STATUS_filter9_sel_MASK)

/*! @name PIXENGCFG_BLITBLEND9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_blitblend9_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_blitblend9_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_blitblend9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_blitblend9_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_blitblend9_LockUnlock_MASK)

/*! @name PIXENGCFG_BLITBLEND9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_BLITBLEND9_LOCKSTATUS_blitblend9_FreezeStatus_MASK)

/*! @name PIXENGCFG_BLITBLEND9_DYNAMIC - Dynamic pixel engine configuration for blitblend9 */
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_prim_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_prim_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_prim_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_prim_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_sec_sel_MASK (0x3F00U)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_sec_sel_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_sec_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_sec_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_BLITBLEND9_DYNAMIC_blitblend9_clken_MASK)

/*! @name PIXENGCFG_BLITBLEND9_STATUS - Status information for pixel engine configuration of blitblend9 */
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_STATUS_blitblend9_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_STATUS_blitblend9_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_BLITBLEND9_STATUS_blitblend9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_BLITBLEND9_STATUS_blitblend9_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_BLITBLEND9_STATUS_blitblend9_sel_MASK)

/*! @name PIXENGCFG_STORE9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_STORE9_LOCKUNLOCK_store9_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_STORE9_LOCKUNLOCK_store9_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE9_LOCKUNLOCK_store9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_LOCKUNLOCK_store9_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_LOCKUNLOCK_store9_LockUnlock_MASK)

/*! @name PIXENGCFG_STORE9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_LOCKSTATUS_store9_FreezeStatus_MASK)

/*! @name PIXENGCFG_STORE9_STATIC - Static pixel engine configuration for store9 */
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_ShdEn_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_ShdEn_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_ShdEn_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_ShdEn_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_powerdown_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_powerdown_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_powerdown_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_powerdown_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_Sync_Mode_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_Sync_Mode_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_Sync_Mode_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_Sync_Mode_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_SW_Reset_MASK (0x800U)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_SW_Reset_SHIFT (11U)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_SW_Reset_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_SW_Reset_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_div_MASK (0xFF0000U)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_div_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_div_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_STATIC_store9_div_MASK)

/*! @name PIXENGCFG_STORE9_DYNAMIC - Dynamic pixel engine configuration for store9 */
#define IRIS_MVPL_PIXENGCFG_STORE9_DYNAMIC_store9_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_STORE9_DYNAMIC_store9_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE9_DYNAMIC_store9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_DYNAMIC_store9_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_DYNAMIC_store9_src_sel_MASK)

/*! @name PIXENGCFG_STORE9_REQUEST - ShadowLoadRequest register for endpoint store9 */
#define IRIS_MVPL_PIXENGCFG_STORE9_REQUEST_store9_sel_ShdLdReq_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_STORE9_REQUEST_store9_sel_ShdLdReq_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE9_REQUEST_store9_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_REQUEST_store9_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_REQUEST_store9_sel_ShdLdReq_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE9_REQUEST_store9_ShdLdReq_MASK (0x3FFFFEU)
#define IRIS_MVPL_PIXENGCFG_STORE9_REQUEST_store9_ShdLdReq_SHIFT (1U)
#define IRIS_MVPL_PIXENGCFG_STORE9_REQUEST_store9_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_REQUEST_store9_ShdLdReq_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_REQUEST_store9_ShdLdReq_MASK)

/*! @name PIXENGCFG_STORE9_TRIGGER - Trigger bits for pixel engine configuration of store9 */
#define IRIS_MVPL_PIXENGCFG_STORE9_TRIGGER_store9_Sync_Trigger_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_STORE9_TRIGGER_store9_Sync_Trigger_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE9_TRIGGER_store9_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_TRIGGER_store9_Sync_Trigger_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_TRIGGER_store9_Sync_Trigger_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE9_TRIGGER_store9_trigger_sequence_complete_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_STORE9_TRIGGER_store9_trigger_sequence_complete_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_STORE9_TRIGGER_store9_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_TRIGGER_store9_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_TRIGGER_store9_trigger_sequence_complete_MASK)

/*! @name PIXENGCFG_STORE9_STATUS - Status information for pixel engine configuration of store9 */
#define IRIS_MVPL_PIXENGCFG_STORE9_STATUS_store9_pipeline_status_MASK (0x3U)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATUS_store9_pipeline_status_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATUS_store9_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_STATUS_store9_pipeline_status_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_STATUS_store9_pipeline_status_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATUS_store9_sync_busy_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATUS_store9_sync_busy_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_STORE9_STATUS_store9_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE9_STATUS_store9_sync_busy_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE9_STATUS_store9_sync_busy_MASK)

/*! @name PIXENGCFG_CONSTFRAME0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_constframe0_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_constframe0_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_constframe0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_constframe0_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_constframe0_LockUnlock_MASK)

/*! @name PIXENGCFG_CONSTFRAME0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_constframe0_FreezeStatus_MASK)

/*! @name PIXENGCFG_CONSTFRAME0_STATUS - Status information for pixel engine configuration of constframe0 */
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_STATUS_constframe0_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_STATUS_constframe0_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME0_STATUS_constframe0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME0_STATUS_constframe0_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME0_STATUS_constframe0_sel_MASK)

/*! @name PIXENGCFG_EXTDST0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKUNLOCK_extdst0_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKUNLOCK_extdst0_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKUNLOCK_extdst0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKUNLOCK_extdst0_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKUNLOCK_extdst0_LockUnlock_MASK)

/*! @name PIXENGCFG_EXTDST0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_LOCKSTATUS_extdst0_FreezeStatus_MASK)

/*! @name PIXENGCFG_EXTDST0_STATIC - Static pixel engine configuration for extdst0 */
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_ShdEn_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_ShdEn_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_ShdEn_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_ShdEn_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_powerdown_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_powerdown_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_powerdown_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_powerdown_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_Sync_Mode_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_Sync_Mode_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_Sync_Mode_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_Sync_Mode_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_SW_Reset_MASK (0x800U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_SW_Reset_SHIFT (11U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_SW_Reset_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_SW_Reset_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_div_MASK (0xFF0000U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_div_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_div_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_STATIC_extdst0_div_MASK)

/*! @name PIXENGCFG_EXTDST0_DYNAMIC - Dynamic pixel engine configuration for extdst0 */
#define IRIS_MVPL_PIXENGCFG_EXTDST0_DYNAMIC_extdst0_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_DYNAMIC_extdst0_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_DYNAMIC_extdst0_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_DYNAMIC_extdst0_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_DYNAMIC_extdst0_src_sel_MASK)

/*! @name PIXENGCFG_EXTDST0_REQUEST - ShadowLoadRequest register for endpoint extdst0 */
#define IRIS_MVPL_PIXENGCFG_EXTDST0_REQUEST_extdst0_sel_ShdLdReq_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_REQUEST_extdst0_sel_ShdLdReq_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_REQUEST_extdst0_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_REQUEST_extdst0_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_REQUEST_extdst0_sel_ShdLdReq_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_REQUEST_extdst0_ShdLdReq_MASK (0x3FFFFEU)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_REQUEST_extdst0_ShdLdReq_SHIFT (1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_REQUEST_extdst0_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_REQUEST_extdst0_ShdLdReq_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_REQUEST_extdst0_ShdLdReq_MASK)

/*! @name PIXENGCFG_EXTDST0_TRIGGER - Trigger bits for pixel engine configuration of extdst0 */
#define IRIS_MVPL_PIXENGCFG_EXTDST0_TRIGGER_extdst0_Sync_Trigger_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_TRIGGER_extdst0_Sync_Trigger_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_TRIGGER_extdst0_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_TRIGGER_extdst0_Sync_Trigger_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_TRIGGER_extdst0_Sync_Trigger_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_TRIGGER_extdst0_trigger_sequence_complete_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_TRIGGER_extdst0_trigger_sequence_complete_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_TRIGGER_extdst0_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_TRIGGER_extdst0_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_TRIGGER_extdst0_trigger_sequence_complete_MASK)

/*! @name PIXENGCFG_EXTDST0_STATUS - Status information for pixel engine configuration of extdst0 */
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATUS_extdst0_pipeline_status_MASK (0x3U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATUS_extdst0_pipeline_status_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATUS_extdst0_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_STATUS_extdst0_pipeline_status_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_STATUS_extdst0_pipeline_status_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATUS_extdst0_sync_busy_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATUS_extdst0_sync_busy_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTDST0_STATUS_extdst0_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST0_STATUS_extdst0_sync_busy_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST0_STATUS_extdst0_sync_busy_MASK)

/*! @name PIXENGCFG_CONSTFRAME4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_constframe4_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_constframe4_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_constframe4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_constframe4_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_constframe4_LockUnlock_MASK)

/*! @name PIXENGCFG_CONSTFRAME4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_constframe4_FreezeStatus_MASK)

/*! @name PIXENGCFG_CONSTFRAME4_STATUS - Status information for pixel engine configuration of constframe4 */
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_STATUS_constframe4_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_STATUS_constframe4_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME4_STATUS_constframe4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME4_STATUS_constframe4_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME4_STATUS_constframe4_sel_MASK)

/*! @name PIXENGCFG_EXTDST4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKUNLOCK_extdst4_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKUNLOCK_extdst4_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKUNLOCK_extdst4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKUNLOCK_extdst4_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKUNLOCK_extdst4_LockUnlock_MASK)

/*! @name PIXENGCFG_EXTDST4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_LOCKSTATUS_extdst4_FreezeStatus_MASK)

/*! @name PIXENGCFG_EXTDST4_STATIC - Static pixel engine configuration for extdst4 */
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_ShdEn_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_ShdEn_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_ShdEn_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_ShdEn_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_powerdown_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_powerdown_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_powerdown_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_powerdown_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_Sync_Mode_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_Sync_Mode_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_Sync_Mode_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_Sync_Mode_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_SW_Reset_MASK (0x800U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_SW_Reset_SHIFT (11U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_SW_Reset_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_SW_Reset_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_div_MASK (0xFF0000U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_div_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_div_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_STATIC_extdst4_div_MASK)

/*! @name PIXENGCFG_EXTDST4_DYNAMIC - Dynamic pixel engine configuration for extdst4 */
#define IRIS_MVPL_PIXENGCFG_EXTDST4_DYNAMIC_extdst4_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_DYNAMIC_extdst4_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_DYNAMIC_extdst4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_DYNAMIC_extdst4_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_DYNAMIC_extdst4_src_sel_MASK)

/*! @name PIXENGCFG_EXTDST4_REQUEST - ShadowLoadRequest register for endpoint extdst4 */
#define IRIS_MVPL_PIXENGCFG_EXTDST4_REQUEST_extdst4_sel_ShdLdReq_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_REQUEST_extdst4_sel_ShdLdReq_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_REQUEST_extdst4_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_REQUEST_extdst4_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_REQUEST_extdst4_sel_ShdLdReq_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_REQUEST_extdst4_ShdLdReq_MASK (0x3FFFFEU)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_REQUEST_extdst4_ShdLdReq_SHIFT (1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_REQUEST_extdst4_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_REQUEST_extdst4_ShdLdReq_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_REQUEST_extdst4_ShdLdReq_MASK)

/*! @name PIXENGCFG_EXTDST4_TRIGGER - Trigger bits for pixel engine configuration of extdst4 */
#define IRIS_MVPL_PIXENGCFG_EXTDST4_TRIGGER_extdst4_Sync_Trigger_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_TRIGGER_extdst4_Sync_Trigger_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_TRIGGER_extdst4_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_TRIGGER_extdst4_Sync_Trigger_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_TRIGGER_extdst4_Sync_Trigger_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_TRIGGER_extdst4_trigger_sequence_complete_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_TRIGGER_extdst4_trigger_sequence_complete_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_TRIGGER_extdst4_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_TRIGGER_extdst4_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_TRIGGER_extdst4_trigger_sequence_complete_MASK)

/*! @name PIXENGCFG_EXTDST4_STATUS - Status information for pixel engine configuration of extdst4 */
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATUS_extdst4_pipeline_status_MASK (0x3U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATUS_extdst4_pipeline_status_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATUS_extdst4_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_STATUS_extdst4_pipeline_status_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_STATUS_extdst4_pipeline_status_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATUS_extdst4_sync_busy_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATUS_extdst4_sync_busy_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTDST4_STATUS_extdst4_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST4_STATUS_extdst4_sync_busy_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST4_STATUS_extdst4_sync_busy_MASK)

/*! @name PIXENGCFG_CONSTFRAME1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_constframe1_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_constframe1_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_constframe1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_constframe1_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_constframe1_LockUnlock_MASK)

/*! @name PIXENGCFG_CONSTFRAME1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_constframe1_FreezeStatus_MASK)

/*! @name PIXENGCFG_CONSTFRAME1_STATUS - Status information for pixel engine configuration of constframe1 */
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_STATUS_constframe1_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_STATUS_constframe1_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME1_STATUS_constframe1_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME1_STATUS_constframe1_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME1_STATUS_constframe1_sel_MASK)

/*! @name PIXENGCFG_EXTDST1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKUNLOCK_extdst1_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKUNLOCK_extdst1_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKUNLOCK_extdst1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKUNLOCK_extdst1_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKUNLOCK_extdst1_LockUnlock_MASK)

/*! @name PIXENGCFG_EXTDST1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_LOCKSTATUS_extdst1_FreezeStatus_MASK)

/*! @name PIXENGCFG_EXTDST1_STATIC - Static pixel engine configuration for extdst1 */
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_ShdEn_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_ShdEn_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_ShdEn_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_ShdEn_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_powerdown_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_powerdown_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_powerdown_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_powerdown_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_Sync_Mode_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_Sync_Mode_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_Sync_Mode_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_Sync_Mode_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_SW_Reset_MASK (0x800U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_SW_Reset_SHIFT (11U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_SW_Reset_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_SW_Reset_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_div_MASK (0xFF0000U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_div_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_div_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_STATIC_extdst1_div_MASK)

/*! @name PIXENGCFG_EXTDST1_DYNAMIC - Dynamic pixel engine configuration for extdst1 */
#define IRIS_MVPL_PIXENGCFG_EXTDST1_DYNAMIC_extdst1_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_DYNAMIC_extdst1_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_DYNAMIC_extdst1_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_DYNAMIC_extdst1_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_DYNAMIC_extdst1_src_sel_MASK)

/*! @name PIXENGCFG_EXTDST1_REQUEST - ShadowLoadRequest register for endpoint extdst1 */
#define IRIS_MVPL_PIXENGCFG_EXTDST1_REQUEST_extdst1_sel_ShdLdReq_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_REQUEST_extdst1_sel_ShdLdReq_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_REQUEST_extdst1_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_REQUEST_extdst1_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_REQUEST_extdst1_sel_ShdLdReq_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_REQUEST_extdst1_ShdLdReq_MASK (0x3FFFFEU)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_REQUEST_extdst1_ShdLdReq_SHIFT (1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_REQUEST_extdst1_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_REQUEST_extdst1_ShdLdReq_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_REQUEST_extdst1_ShdLdReq_MASK)

/*! @name PIXENGCFG_EXTDST1_TRIGGER - Trigger bits for pixel engine configuration of extdst1 */
#define IRIS_MVPL_PIXENGCFG_EXTDST1_TRIGGER_extdst1_Sync_Trigger_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_TRIGGER_extdst1_Sync_Trigger_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_TRIGGER_extdst1_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_TRIGGER_extdst1_Sync_Trigger_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_TRIGGER_extdst1_Sync_Trigger_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete_MASK)

/*! @name PIXENGCFG_EXTDST1_STATUS - Status information for pixel engine configuration of extdst1 */
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATUS_extdst1_pipeline_status_MASK (0x3U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATUS_extdst1_pipeline_status_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATUS_extdst1_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_STATUS_extdst1_pipeline_status_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_STATUS_extdst1_pipeline_status_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATUS_extdst1_sync_busy_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATUS_extdst1_sync_busy_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTDST1_STATUS_extdst1_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST1_STATUS_extdst1_sync_busy_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST1_STATUS_extdst1_sync_busy_MASK)

/*! @name PIXENGCFG_CONSTFRAME5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_constframe5_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_constframe5_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_constframe5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_constframe5_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_constframe5_LockUnlock_MASK)

/*! @name PIXENGCFG_CONSTFRAME5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_constframe5_FreezeStatus_MASK)

/*! @name PIXENGCFG_CONSTFRAME5_STATUS - Status information for pixel engine configuration of constframe5 */
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_STATUS_constframe5_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_STATUS_constframe5_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_CONSTFRAME5_STATUS_constframe5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_CONSTFRAME5_STATUS_constframe5_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_CONSTFRAME5_STATUS_constframe5_sel_MASK)

/*! @name PIXENGCFG_EXTDST5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKUNLOCK_extdst5_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKUNLOCK_extdst5_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKUNLOCK_extdst5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKUNLOCK_extdst5_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKUNLOCK_extdst5_LockUnlock_MASK)

/*! @name PIXENGCFG_EXTDST5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_LOCKSTATUS_extdst5_FreezeStatus_MASK)

/*! @name PIXENGCFG_EXTDST5_STATIC - Static pixel engine configuration for extdst5 */
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_ShdEn_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_ShdEn_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_ShdEn_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_ShdEn_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_powerdown_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_powerdown_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_powerdown_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_powerdown_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_Sync_Mode_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_Sync_Mode_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_Sync_Mode_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_Sync_Mode_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_SW_Reset_MASK (0x800U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_SW_Reset_SHIFT (11U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_SW_Reset_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_SW_Reset_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_div_MASK (0xFF0000U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_div_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_div_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_STATIC_extdst5_div_MASK)

/*! @name PIXENGCFG_EXTDST5_DYNAMIC - Dynamic pixel engine configuration for extdst5 */
#define IRIS_MVPL_PIXENGCFG_EXTDST5_DYNAMIC_extdst5_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_DYNAMIC_extdst5_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_DYNAMIC_extdst5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_DYNAMIC_extdst5_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_DYNAMIC_extdst5_src_sel_MASK)

/*! @name PIXENGCFG_EXTDST5_REQUEST - ShadowLoadRequest register for endpoint extdst5 */
#define IRIS_MVPL_PIXENGCFG_EXTDST5_REQUEST_extdst5_sel_ShdLdReq_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_REQUEST_extdst5_sel_ShdLdReq_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_REQUEST_extdst5_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_REQUEST_extdst5_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_REQUEST_extdst5_sel_ShdLdReq_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_REQUEST_extdst5_ShdLdReq_MASK (0x3FFFFEU)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_REQUEST_extdst5_ShdLdReq_SHIFT (1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_REQUEST_extdst5_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_REQUEST_extdst5_ShdLdReq_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_REQUEST_extdst5_ShdLdReq_MASK)

/*! @name PIXENGCFG_EXTDST5_TRIGGER - Trigger bits for pixel engine configuration of extdst5 */
#define IRIS_MVPL_PIXENGCFG_EXTDST5_TRIGGER_extdst5_Sync_Trigger_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_TRIGGER_extdst5_Sync_Trigger_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_TRIGGER_extdst5_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_TRIGGER_extdst5_Sync_Trigger_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_TRIGGER_extdst5_Sync_Trigger_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete_MASK)

/*! @name PIXENGCFG_EXTDST5_STATUS - Status information for pixel engine configuration of extdst5 */
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATUS_extdst5_pipeline_status_MASK (0x3U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATUS_extdst5_pipeline_status_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATUS_extdst5_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_STATUS_extdst5_pipeline_status_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_STATUS_extdst5_pipeline_status_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATUS_extdst5_sync_busy_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATUS_extdst5_sync_busy_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTDST5_STATUS_extdst5_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTDST5_STATUS_extdst5_sync_busy_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTDST5_STATUS_extdst5_sync_busy_MASK)

/*! @name PIXENGCFG_EXTSRC4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKUNLOCK_extsrc4_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKUNLOCK_extsrc4_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKUNLOCK_extsrc4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKUNLOCK_extsrc4_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKUNLOCK_extsrc4_LockUnlock_MASK)

/*! @name PIXENGCFG_EXTSRC4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC4_LOCKSTATUS_extsrc4_FreezeStatus_MASK)

/*! @name PIXENGCFG_EXTSRC4_STATUS - Status information for pixel engine configuration of extsrc4 */
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_STATUS_extsrc4_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_STATUS_extsrc4_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC4_STATUS_extsrc4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC4_STATUS_extsrc4_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC4_STATUS_extsrc4_sel_MASK)

/*! @name PIXENGCFG_STORE4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_STORE4_LOCKUNLOCK_store4_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_STORE4_LOCKUNLOCK_store4_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE4_LOCKUNLOCK_store4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_LOCKUNLOCK_store4_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_LOCKUNLOCK_store4_LockUnlock_MASK)

/*! @name PIXENGCFG_STORE4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_LOCKSTATUS_store4_FreezeStatus_MASK)

/*! @name PIXENGCFG_STORE4_STATIC - Static pixel engine configuration for store4 */
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_ShdEn_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_ShdEn_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_ShdEn_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_ShdEn_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_powerdown_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_powerdown_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_powerdown_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_powerdown_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_Sync_Mode_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_Sync_Mode_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_Sync_Mode_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_Sync_Mode_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_SW_Reset_MASK (0x800U)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_SW_Reset_SHIFT (11U)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_SW_Reset_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_SW_Reset_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_div_MASK (0xFF0000U)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_div_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_div_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_STATIC_store4_div_MASK)

/*! @name PIXENGCFG_STORE4_DYNAMIC - Dynamic pixel engine configuration for store4 */
#define IRIS_MVPL_PIXENGCFG_STORE4_DYNAMIC_store4_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_STORE4_DYNAMIC_store4_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE4_DYNAMIC_store4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_DYNAMIC_store4_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_DYNAMIC_store4_src_sel_MASK)

/*! @name PIXENGCFG_STORE4_REQUEST - ShadowLoadRequest register for endpoint store4 */
#define IRIS_MVPL_PIXENGCFG_STORE4_REQUEST_store4_sel_ShdLdReq_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_STORE4_REQUEST_store4_sel_ShdLdReq_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE4_REQUEST_store4_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_REQUEST_store4_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_REQUEST_store4_sel_ShdLdReq_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE4_REQUEST_store4_ShdLdReq_MASK (0x3FFFFEU)
#define IRIS_MVPL_PIXENGCFG_STORE4_REQUEST_store4_ShdLdReq_SHIFT (1U)
#define IRIS_MVPL_PIXENGCFG_STORE4_REQUEST_store4_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_REQUEST_store4_ShdLdReq_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_REQUEST_store4_ShdLdReq_MASK)

/*! @name PIXENGCFG_STORE4_TRIGGER - Trigger bits for pixel engine configuration of store4 */
#define IRIS_MVPL_PIXENGCFG_STORE4_TRIGGER_store4_Sync_Trigger_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_STORE4_TRIGGER_store4_Sync_Trigger_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE4_TRIGGER_store4_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_TRIGGER_store4_Sync_Trigger_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_TRIGGER_store4_Sync_Trigger_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE4_TRIGGER_store4_trigger_sequence_complete_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_STORE4_TRIGGER_store4_trigger_sequence_complete_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_STORE4_TRIGGER_store4_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_TRIGGER_store4_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_TRIGGER_store4_trigger_sequence_complete_MASK)

/*! @name PIXENGCFG_STORE4_STATUS - Status information for pixel engine configuration of store4 */
#define IRIS_MVPL_PIXENGCFG_STORE4_STATUS_store4_pipeline_status_MASK (0x3U)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATUS_store4_pipeline_status_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATUS_store4_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_STATUS_store4_pipeline_status_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_STATUS_store4_pipeline_status_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATUS_store4_sync_busy_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATUS_store4_sync_busy_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_STORE4_STATUS_store4_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE4_STATUS_store4_sync_busy_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE4_STATUS_store4_sync_busy_MASK)

/*! @name PIXENGCFG_EXTSRC5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKUNLOCK_extsrc5_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKUNLOCK_extsrc5_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKUNLOCK_extsrc5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKUNLOCK_extsrc5_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKUNLOCK_extsrc5_LockUnlock_MASK)

/*! @name PIXENGCFG_EXTSRC5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC5_LOCKSTATUS_extsrc5_FreezeStatus_MASK)

/*! @name PIXENGCFG_EXTSRC5_STATUS - Status information for pixel engine configuration of extsrc5 */
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_STATUS_extsrc5_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_STATUS_extsrc5_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC5_STATUS_extsrc5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC5_STATUS_extsrc5_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC5_STATUS_extsrc5_sel_MASK)

/*! @name PIXENGCFG_STORE5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_STORE5_LOCKUNLOCK_store5_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_STORE5_LOCKUNLOCK_store5_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE5_LOCKUNLOCK_store5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_LOCKUNLOCK_store5_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_LOCKUNLOCK_store5_LockUnlock_MASK)

/*! @name PIXENGCFG_STORE5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_LOCKSTATUS_store5_FreezeStatus_MASK)

/*! @name PIXENGCFG_STORE5_STATIC - Static pixel engine configuration for store5 */
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_ShdEn_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_ShdEn_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_ShdEn_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_ShdEn_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_powerdown_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_powerdown_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_powerdown_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_powerdown_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_Sync_Mode_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_Sync_Mode_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_Sync_Mode_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_Sync_Mode_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_SW_Reset_MASK (0x800U)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_SW_Reset_SHIFT (11U)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_SW_Reset_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_SW_Reset_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_div_MASK (0xFF0000U)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_div_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_div_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_STATIC_store5_div_MASK)

/*! @name PIXENGCFG_STORE5_DYNAMIC - Dynamic pixel engine configuration for store5 */
#define IRIS_MVPL_PIXENGCFG_STORE5_DYNAMIC_store5_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_STORE5_DYNAMIC_store5_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE5_DYNAMIC_store5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_DYNAMIC_store5_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_DYNAMIC_store5_src_sel_MASK)

/*! @name PIXENGCFG_STORE5_REQUEST - ShadowLoadRequest register for endpoint store5 */
#define IRIS_MVPL_PIXENGCFG_STORE5_REQUEST_store5_sel_ShdLdReq_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_STORE5_REQUEST_store5_sel_ShdLdReq_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE5_REQUEST_store5_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_REQUEST_store5_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_REQUEST_store5_sel_ShdLdReq_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE5_REQUEST_store5_ShdLdReq_MASK (0x3FFFFEU)
#define IRIS_MVPL_PIXENGCFG_STORE5_REQUEST_store5_ShdLdReq_SHIFT (1U)
#define IRIS_MVPL_PIXENGCFG_STORE5_REQUEST_store5_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_REQUEST_store5_ShdLdReq_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_REQUEST_store5_ShdLdReq_MASK)

/*! @name PIXENGCFG_STORE5_TRIGGER - Trigger bits for pixel engine configuration of store5 */
#define IRIS_MVPL_PIXENGCFG_STORE5_TRIGGER_store5_Sync_Trigger_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_STORE5_TRIGGER_store5_Sync_Trigger_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE5_TRIGGER_store5_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_TRIGGER_store5_Sync_Trigger_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_TRIGGER_store5_Sync_Trigger_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE5_TRIGGER_store5_trigger_sequence_complete_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_STORE5_TRIGGER_store5_trigger_sequence_complete_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_STORE5_TRIGGER_store5_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_TRIGGER_store5_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_TRIGGER_store5_trigger_sequence_complete_MASK)

/*! @name PIXENGCFG_STORE5_STATUS - Status information for pixel engine configuration of store5 */
#define IRIS_MVPL_PIXENGCFG_STORE5_STATUS_store5_pipeline_status_MASK (0x3U)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATUS_store5_pipeline_status_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATUS_store5_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_STATUS_store5_pipeline_status_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_STATUS_store5_pipeline_status_MASK)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATUS_store5_sync_busy_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATUS_store5_sync_busy_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_STORE5_STATUS_store5_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_STORE5_STATUS_store5_sync_busy_SHIFT)) & IRIS_MVPL_PIXENGCFG_STORE5_STATUS_store5_sync_busy_MASK)

/*! @name PIXENGCFG_FETCHDECODE2_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKUNLOCK_fetchdecode2_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKUNLOCK_fetchdecode2_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKUNLOCK_fetchdecode2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKUNLOCK_fetchdecode2_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKUNLOCK_fetchdecode2_LockUnlock_MASK)

/*! @name PIXENGCFG_FETCHDECODE2_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE2_LOCKSTATUS_fetchdecode2_FreezeStatus_MASK)

/*! @name PIXENGCFG_FETCHDECODE2_DYNAMIC - Dynamic pixel engine configuration for fetchdecode2 */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_DYNAMIC_fetchdecode2_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_DYNAMIC_fetchdecode2_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_DYNAMIC_fetchdecode2_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE2_DYNAMIC_fetchdecode2_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE2_DYNAMIC_fetchdecode2_src_sel_MASK)

/*! @name PIXENGCFG_FETCHDECODE2_STATUS - Status information for pixel engine configuration of fetchdecode2 */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_STATUS_fetchdecode2_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_STATUS_fetchdecode2_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE2_STATUS_fetchdecode2_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE2_STATUS_fetchdecode2_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE2_STATUS_fetchdecode2_sel_MASK)

/*! @name PIXENGCFG_FETCHDECODE3_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKUNLOCK_fetchdecode3_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKUNLOCK_fetchdecode3_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKUNLOCK_fetchdecode3_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKUNLOCK_fetchdecode3_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKUNLOCK_fetchdecode3_LockUnlock_MASK)

/*! @name PIXENGCFG_FETCHDECODE3_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE3_LOCKSTATUS_fetchdecode3_FreezeStatus_MASK)

/*! @name PIXENGCFG_FETCHDECODE3_DYNAMIC - Dynamic pixel engine configuration for fetchdecode3 */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_DYNAMIC_fetchdecode3_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_DYNAMIC_fetchdecode3_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_DYNAMIC_fetchdecode3_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE3_DYNAMIC_fetchdecode3_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE3_DYNAMIC_fetchdecode3_src_sel_MASK)

/*! @name PIXENGCFG_FETCHDECODE3_STATUS - Status information for pixel engine configuration of fetchdecode3 */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_STATUS_fetchdecode3_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_STATUS_fetchdecode3_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE3_STATUS_fetchdecode3_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE3_STATUS_fetchdecode3_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE3_STATUS_fetchdecode3_sel_MASK)

/*! @name PIXENGCFG_FETCHWARP2_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_fetchwarp2_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_fetchwarp2_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_fetchwarp2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_fetchwarp2_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_fetchwarp2_LockUnlock_MASK)

/*! @name PIXENGCFG_FETCHWARP2_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHWARP2_LOCKSTATUS_fetchwarp2_FreezeStatus_MASK)

/*! @name PIXENGCFG_FETCHWARP2_DYNAMIC - Dynamic pixel engine configuration for fetchwarp2 */
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_DYNAMIC_fetchwarp2_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_DYNAMIC_fetchwarp2_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_DYNAMIC_fetchwarp2_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHWARP2_DYNAMIC_fetchwarp2_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHWARP2_DYNAMIC_fetchwarp2_src_sel_MASK)

/*! @name PIXENGCFG_FETCHWARP2_STATUS - Status information for pixel engine configuration of fetchwarp2 */
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_STATUS_fetchwarp2_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_STATUS_fetchwarp2_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_FETCHWARP2_STATUS_fetchwarp2_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHWARP2_STATUS_fetchwarp2_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHWARP2_STATUS_fetchwarp2_sel_MASK)

/*! @name PIXENGCFG_FETCHECO2_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKUNLOCK_fetcheco2_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKUNLOCK_fetcheco2_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKUNLOCK_fetcheco2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKUNLOCK_fetcheco2_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKUNLOCK_fetcheco2_LockUnlock_MASK)

/*! @name PIXENGCFG_FETCHECO2_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO2_LOCKSTATUS_fetcheco2_FreezeStatus_MASK)

/*! @name PIXENGCFG_FETCHECO2_STATUS - Status information for pixel engine configuration of fetcheco2 */
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_STATUS_fetcheco2_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_STATUS_fetcheco2_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO2_STATUS_fetcheco2_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO2_STATUS_fetcheco2_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO2_STATUS_fetcheco2_sel_MASK)

/*! @name PIXENGCFG_FETCHDECODE0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock_MASK)

/*! @name PIXENGCFG_FETCHDECODE0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus_MASK)

/*! @name PIXENGCFG_FETCHDECODE0_DYNAMIC - Dynamic pixel engine configuration for fetchdecode0 */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel_MASK)

/*! @name PIXENGCFG_FETCHDECODE0_STATUS - Status information for pixel engine configuration of fetchdecode0 */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_STATUS_fetchdecode0_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_STATUS_fetchdecode0_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE0_STATUS_fetchdecode0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE0_STATUS_fetchdecode0_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE0_STATUS_fetchdecode0_sel_MASK)

/*! @name PIXENGCFG_FETCHECO0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKUNLOCK_fetcheco0_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKUNLOCK_fetcheco0_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKUNLOCK_fetcheco0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKUNLOCK_fetcheco0_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKUNLOCK_fetcheco0_LockUnlock_MASK)

/*! @name PIXENGCFG_FETCHECO0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO0_LOCKSTATUS_fetcheco0_FreezeStatus_MASK)

/*! @name PIXENGCFG_FETCHECO0_STATUS - Status information for pixel engine configuration of fetcheco0 */
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_STATUS_fetcheco0_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_STATUS_fetcheco0_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO0_STATUS_fetcheco0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO0_STATUS_fetcheco0_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO0_STATUS_fetcheco0_sel_MASK)

/*! @name PIXENGCFG_FETCHDECODE1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_fetchdecode1_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_fetchdecode1_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_fetchdecode1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_fetchdecode1_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_fetchdecode1_LockUnlock_MASK)

/*! @name PIXENGCFG_FETCHDECODE1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_fetchdecode1_FreezeStatus_MASK)

/*! @name PIXENGCFG_FETCHDECODE1_DYNAMIC - Dynamic pixel engine configuration for fetchdecode1 */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel_MASK)

/*! @name PIXENGCFG_FETCHDECODE1_STATUS - Status information for pixel engine configuration of fetchdecode1 */
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_STATUS_fetchdecode1_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_STATUS_fetchdecode1_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_FETCHDECODE1_STATUS_fetchdecode1_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHDECODE1_STATUS_fetchdecode1_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHDECODE1_STATUS_fetchdecode1_sel_MASK)

/*! @name PIXENGCFG_FETCHECO1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKUNLOCK_fetcheco1_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKUNLOCK_fetcheco1_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKUNLOCK_fetcheco1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKUNLOCK_fetcheco1_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKUNLOCK_fetcheco1_LockUnlock_MASK)

/*! @name PIXENGCFG_FETCHECO1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO1_LOCKSTATUS_fetcheco1_FreezeStatus_MASK)

/*! @name PIXENGCFG_FETCHECO1_STATUS - Status information for pixel engine configuration of fetcheco1 */
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_STATUS_fetcheco1_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_STATUS_fetcheco1_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_FETCHECO1_STATUS_fetcheco1_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHECO1_STATUS_fetcheco1_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHECO1_STATUS_fetcheco1_sel_MASK)

/*! @name PIXENGCFG_FETCHLAYER0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_fetchlayer0_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_fetchlayer0_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_fetchlayer0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_fetchlayer0_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_fetchlayer0_LockUnlock_MASK)

/*! @name PIXENGCFG_FETCHLAYER0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_fetchlayer0_FreezeStatus_MASK)

/*! @name PIXENGCFG_FETCHLAYER0_STATUS - Status information for pixel engine configuration of fetchlayer0 */
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_STATUS_fetchlayer0_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_STATUS_fetchlayer0_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER0_STATUS_fetchlayer0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHLAYER0_STATUS_fetchlayer0_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHLAYER0_STATUS_fetchlayer0_sel_MASK)

/*! @name PIXENGCFG_FETCHLAYER1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKUNLOCK_fetchlayer1_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKUNLOCK_fetchlayer1_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKUNLOCK_fetchlayer1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKUNLOCK_fetchlayer1_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKUNLOCK_fetchlayer1_LockUnlock_MASK)

/*! @name PIXENGCFG_FETCHLAYER1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHLAYER1_LOCKSTATUS_fetchlayer1_FreezeStatus_MASK)

/*! @name PIXENGCFG_FETCHLAYER1_STATUS - Status information for pixel engine configuration of fetchlayer1 */
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_STATUS_fetchlayer1_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_STATUS_fetchlayer1_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_FETCHLAYER1_STATUS_fetchlayer1_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_FETCHLAYER1_STATUS_fetchlayer1_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_FETCHLAYER1_STATUS_fetchlayer1_sel_MASK)

/*! @name PIXENGCFG_GAMMACOR4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKUNLOCK_gammacor4_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKUNLOCK_gammacor4_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKUNLOCK_gammacor4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKUNLOCK_gammacor4_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKUNLOCK_gammacor4_LockUnlock_MASK)

/*! @name PIXENGCFG_GAMMACOR4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_GAMMACOR4_LOCKSTATUS_gammacor4_FreezeStatus_MASK)

/*! @name PIXENGCFG_GAMMACOR4_DYNAMIC - Dynamic pixel engine configuration for gammacor4 */
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_DYNAMIC_gammacor4_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_DYNAMIC_gammacor4_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_DYNAMIC_gammacor4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_GAMMACOR4_DYNAMIC_gammacor4_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_GAMMACOR4_DYNAMIC_gammacor4_src_sel_MASK)

/*! @name PIXENGCFG_GAMMACOR4_STATUS - Status information for pixel engine configuration of gammacor4 */
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_STATUS_gammacor4_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_STATUS_gammacor4_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR4_STATUS_gammacor4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_GAMMACOR4_STATUS_gammacor4_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_GAMMACOR4_STATUS_gammacor4_sel_MASK)

/*! @name PIXENGCFG_MATRIX4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKUNLOCK_matrix4_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKUNLOCK_matrix4_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKUNLOCK_matrix4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKUNLOCK_matrix4_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKUNLOCK_matrix4_LockUnlock_MASK)

/*! @name PIXENGCFG_MATRIX4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX4_LOCKSTATUS_matrix4_FreezeStatus_MASK)

/*! @name PIXENGCFG_MATRIX4_DYNAMIC - Dynamic pixel engine configuration for matrix4 */
#define IRIS_MVPL_PIXENGCFG_MATRIX4_DYNAMIC_matrix4_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_DYNAMIC_matrix4_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_DYNAMIC_matrix4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX4_DYNAMIC_matrix4_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX4_DYNAMIC_matrix4_src_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_DYNAMIC_matrix4_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_DYNAMIC_matrix4_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_DYNAMIC_matrix4_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX4_DYNAMIC_matrix4_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX4_DYNAMIC_matrix4_clken_MASK)

/*! @name PIXENGCFG_MATRIX4_STATUS - Status information for pixel engine configuration of matrix4 */
#define IRIS_MVPL_PIXENGCFG_MATRIX4_STATUS_matrix4_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_STATUS_matrix4_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_MATRIX4_STATUS_matrix4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX4_STATUS_matrix4_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX4_STATUS_matrix4_sel_MASK)

/*! @name PIXENGCFG_HSCALER4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKUNLOCK_hscaler4_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKUNLOCK_hscaler4_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKUNLOCK_hscaler4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKUNLOCK_hscaler4_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKUNLOCK_hscaler4_LockUnlock_MASK)

/*! @name PIXENGCFG_HSCALER4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER4_LOCKSTATUS_hscaler4_FreezeStatus_MASK)

/*! @name PIXENGCFG_HSCALER4_DYNAMIC - Dynamic pixel engine configuration for hscaler4 */
#define IRIS_MVPL_PIXENGCFG_HSCALER4_DYNAMIC_hscaler4_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_DYNAMIC_hscaler4_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_DYNAMIC_hscaler4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER4_DYNAMIC_hscaler4_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER4_DYNAMIC_hscaler4_src_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_DYNAMIC_hscaler4_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_DYNAMIC_hscaler4_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_DYNAMIC_hscaler4_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER4_DYNAMIC_hscaler4_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER4_DYNAMIC_hscaler4_clken_MASK)

/*! @name PIXENGCFG_HSCALER4_STATUS - Status information for pixel engine configuration of hscaler4 */
#define IRIS_MVPL_PIXENGCFG_HSCALER4_STATUS_hscaler4_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_STATUS_hscaler4_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_HSCALER4_STATUS_hscaler4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER4_STATUS_hscaler4_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER4_STATUS_hscaler4_sel_MASK)

/*! @name PIXENGCFG_VSCALER4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKUNLOCK_vscaler4_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKUNLOCK_vscaler4_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKUNLOCK_vscaler4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKUNLOCK_vscaler4_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKUNLOCK_vscaler4_LockUnlock_MASK)

/*! @name PIXENGCFG_VSCALER4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER4_LOCKSTATUS_vscaler4_FreezeStatus_MASK)

/*! @name PIXENGCFG_VSCALER4_DYNAMIC - Dynamic pixel engine configuration for vscaler4 */
#define IRIS_MVPL_PIXENGCFG_VSCALER4_DYNAMIC_vscaler4_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_DYNAMIC_vscaler4_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_DYNAMIC_vscaler4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER4_DYNAMIC_vscaler4_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER4_DYNAMIC_vscaler4_src_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_DYNAMIC_vscaler4_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_DYNAMIC_vscaler4_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_DYNAMIC_vscaler4_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER4_DYNAMIC_vscaler4_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER4_DYNAMIC_vscaler4_clken_MASK)

/*! @name PIXENGCFG_VSCALER4_STATUS - Status information for pixel engine configuration of vscaler4 */
#define IRIS_MVPL_PIXENGCFG_VSCALER4_STATUS_vscaler4_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_STATUS_vscaler4_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_VSCALER4_STATUS_vscaler4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER4_STATUS_vscaler4_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER4_STATUS_vscaler4_sel_MASK)

/*! @name PIXENGCFG_HISTOGRAM4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKUNLOCK_histogram4_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKUNLOCK_histogram4_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKUNLOCK_histogram4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKUNLOCK_histogram4_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKUNLOCK_histogram4_LockUnlock_MASK)

/*! @name PIXENGCFG_HISTOGRAM4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HISTOGRAM4_LOCKSTATUS_histogram4_FreezeStatus_MASK)

/*! @name PIXENGCFG_HISTOGRAM4_DYNAMIC - Dynamic pixel engine configuration for histogram4 */
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_DYNAMIC_histogram4_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_DYNAMIC_histogram4_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_DYNAMIC_histogram4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HISTOGRAM4_DYNAMIC_histogram4_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_HISTOGRAM4_DYNAMIC_histogram4_src_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_DYNAMIC_histogram4_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_DYNAMIC_histogram4_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_DYNAMIC_histogram4_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HISTOGRAM4_DYNAMIC_histogram4_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_HISTOGRAM4_DYNAMIC_histogram4_clken_MASK)

/*! @name PIXENGCFG_HISTOGRAM4_STATUS - Status information for pixel engine configuration of histogram4 */
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_STATUS_histogram4_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_STATUS_histogram4_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM4_STATUS_histogram4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HISTOGRAM4_STATUS_histogram4_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_HISTOGRAM4_STATUS_histogram4_sel_MASK)

/*! @name PIXENGCFG_GAMMACOR5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKUNLOCK_gammacor5_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKUNLOCK_gammacor5_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKUNLOCK_gammacor5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKUNLOCK_gammacor5_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKUNLOCK_gammacor5_LockUnlock_MASK)

/*! @name PIXENGCFG_GAMMACOR5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_GAMMACOR5_LOCKSTATUS_gammacor5_FreezeStatus_MASK)

/*! @name PIXENGCFG_GAMMACOR5_DYNAMIC - Dynamic pixel engine configuration for gammacor5 */
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_DYNAMIC_gammacor5_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_DYNAMIC_gammacor5_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_DYNAMIC_gammacor5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_GAMMACOR5_DYNAMIC_gammacor5_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_GAMMACOR5_DYNAMIC_gammacor5_src_sel_MASK)

/*! @name PIXENGCFG_GAMMACOR5_STATUS - Status information for pixel engine configuration of gammacor5 */
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_STATUS_gammacor5_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_STATUS_gammacor5_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_GAMMACOR5_STATUS_gammacor5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_GAMMACOR5_STATUS_gammacor5_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_GAMMACOR5_STATUS_gammacor5_sel_MASK)

/*! @name PIXENGCFG_MATRIX5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKUNLOCK_matrix5_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKUNLOCK_matrix5_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKUNLOCK_matrix5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKUNLOCK_matrix5_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKUNLOCK_matrix5_LockUnlock_MASK)

/*! @name PIXENGCFG_MATRIX5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX5_LOCKSTATUS_matrix5_FreezeStatus_MASK)

/*! @name PIXENGCFG_MATRIX5_DYNAMIC - Dynamic pixel engine configuration for matrix5 */
#define IRIS_MVPL_PIXENGCFG_MATRIX5_DYNAMIC_matrix5_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_DYNAMIC_matrix5_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_DYNAMIC_matrix5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX5_DYNAMIC_matrix5_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX5_DYNAMIC_matrix5_src_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_DYNAMIC_matrix5_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_DYNAMIC_matrix5_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_DYNAMIC_matrix5_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX5_DYNAMIC_matrix5_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX5_DYNAMIC_matrix5_clken_MASK)

/*! @name PIXENGCFG_MATRIX5_STATUS - Status information for pixel engine configuration of matrix5 */
#define IRIS_MVPL_PIXENGCFG_MATRIX5_STATUS_matrix5_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_STATUS_matrix5_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_MATRIX5_STATUS_matrix5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_MATRIX5_STATUS_matrix5_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_MATRIX5_STATUS_matrix5_sel_MASK)

/*! @name PIXENGCFG_HSCALER5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKUNLOCK_hscaler5_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKUNLOCK_hscaler5_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKUNLOCK_hscaler5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKUNLOCK_hscaler5_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKUNLOCK_hscaler5_LockUnlock_MASK)

/*! @name PIXENGCFG_HSCALER5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER5_LOCKSTATUS_hscaler5_FreezeStatus_MASK)

/*! @name PIXENGCFG_HSCALER5_DYNAMIC - Dynamic pixel engine configuration for hscaler5 */
#define IRIS_MVPL_PIXENGCFG_HSCALER5_DYNAMIC_hscaler5_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_DYNAMIC_hscaler5_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_DYNAMIC_hscaler5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER5_DYNAMIC_hscaler5_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER5_DYNAMIC_hscaler5_src_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_DYNAMIC_hscaler5_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_DYNAMIC_hscaler5_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_DYNAMIC_hscaler5_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER5_DYNAMIC_hscaler5_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER5_DYNAMIC_hscaler5_clken_MASK)

/*! @name PIXENGCFG_HSCALER5_STATUS - Status information for pixel engine configuration of hscaler5 */
#define IRIS_MVPL_PIXENGCFG_HSCALER5_STATUS_hscaler5_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_STATUS_hscaler5_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_HSCALER5_STATUS_hscaler5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HSCALER5_STATUS_hscaler5_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_HSCALER5_STATUS_hscaler5_sel_MASK)

/*! @name PIXENGCFG_VSCALER5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKUNLOCK_vscaler5_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKUNLOCK_vscaler5_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKUNLOCK_vscaler5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKUNLOCK_vscaler5_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKUNLOCK_vscaler5_LockUnlock_MASK)

/*! @name PIXENGCFG_VSCALER5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER5_LOCKSTATUS_vscaler5_FreezeStatus_MASK)

/*! @name PIXENGCFG_VSCALER5_DYNAMIC - Dynamic pixel engine configuration for vscaler5 */
#define IRIS_MVPL_PIXENGCFG_VSCALER5_DYNAMIC_vscaler5_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_DYNAMIC_vscaler5_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_DYNAMIC_vscaler5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER5_DYNAMIC_vscaler5_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER5_DYNAMIC_vscaler5_src_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_DYNAMIC_vscaler5_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_DYNAMIC_vscaler5_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_DYNAMIC_vscaler5_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER5_DYNAMIC_vscaler5_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER5_DYNAMIC_vscaler5_clken_MASK)

/*! @name PIXENGCFG_VSCALER5_STATUS - Status information for pixel engine configuration of vscaler5 */
#define IRIS_MVPL_PIXENGCFG_VSCALER5_STATUS_vscaler5_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_STATUS_vscaler5_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_VSCALER5_STATUS_vscaler5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_VSCALER5_STATUS_vscaler5_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_VSCALER5_STATUS_vscaler5_sel_MASK)

/*! @name PIXENGCFG_HISTOGRAM5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKUNLOCK_histogram5_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKUNLOCK_histogram5_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKUNLOCK_histogram5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKUNLOCK_histogram5_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKUNLOCK_histogram5_LockUnlock_MASK)

/*! @name PIXENGCFG_HISTOGRAM5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_HISTOGRAM5_LOCKSTATUS_histogram5_FreezeStatus_MASK)

/*! @name PIXENGCFG_HISTOGRAM5_DYNAMIC - Dynamic pixel engine configuration for histogram5 */
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_DYNAMIC_histogram5_src_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_DYNAMIC_histogram5_src_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_DYNAMIC_histogram5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HISTOGRAM5_DYNAMIC_histogram5_src_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_HISTOGRAM5_DYNAMIC_histogram5_src_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_DYNAMIC_histogram5_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_DYNAMIC_histogram5_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_DYNAMIC_histogram5_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HISTOGRAM5_DYNAMIC_histogram5_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_HISTOGRAM5_DYNAMIC_histogram5_clken_MASK)

/*! @name PIXENGCFG_HISTOGRAM5_STATUS - Status information for pixel engine configuration of histogram5 */
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_STATUS_histogram5_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_STATUS_histogram5_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_HISTOGRAM5_STATUS_histogram5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_HISTOGRAM5_STATUS_histogram5_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_HISTOGRAM5_STATUS_histogram5_sel_MASK)

/*! @name PIXENGCFG_LAYERBLEND0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_layerblend0_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_layerblend0_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_layerblend0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_layerblend0_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_layerblend0_LockUnlock_MASK)

/*! @name PIXENGCFG_LAYERBLEND0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_layerblend0_FreezeStatus_MASK)

/*! @name PIXENGCFG_LAYERBLEND0_DYNAMIC - Dynamic pixel engine configuration for layerblend0 */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel_MASK (0x3F00U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND0_DYNAMIC_layerblend0_clken_MASK)

/*! @name PIXENGCFG_LAYERBLEND0_STATUS - Status information for pixel engine configuration of layerblend0 */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_STATUS_layerblend0_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_STATUS_layerblend0_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND0_STATUS_layerblend0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND0_STATUS_layerblend0_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND0_STATUS_layerblend0_sel_MASK)

/*! @name PIXENGCFG_LAYERBLEND1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_layerblend1_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_layerblend1_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_layerblend1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_layerblend1_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_layerblend1_LockUnlock_MASK)

/*! @name PIXENGCFG_LAYERBLEND1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_layerblend1_FreezeStatus_MASK)

/*! @name PIXENGCFG_LAYERBLEND1_DYNAMIC - Dynamic pixel engine configuration for layerblend1 */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel_MASK (0x3F00U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND1_DYNAMIC_layerblend1_clken_MASK)

/*! @name PIXENGCFG_LAYERBLEND1_STATUS - Status information for pixel engine configuration of layerblend1 */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_STATUS_layerblend1_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_STATUS_layerblend1_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND1_STATUS_layerblend1_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND1_STATUS_layerblend1_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND1_STATUS_layerblend1_sel_MASK)

/*! @name PIXENGCFG_LAYERBLEND2_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_layerblend2_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_layerblend2_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_layerblend2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_layerblend2_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_layerblend2_LockUnlock_MASK)

/*! @name PIXENGCFG_LAYERBLEND2_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_layerblend2_FreezeStatus_MASK)

/*! @name PIXENGCFG_LAYERBLEND2_DYNAMIC - Dynamic pixel engine configuration for layerblend2 */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel_MASK (0x3F00U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND2_DYNAMIC_layerblend2_clken_MASK)

/*! @name PIXENGCFG_LAYERBLEND2_STATUS - Status information for pixel engine configuration of layerblend2 */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_STATUS_layerblend2_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_STATUS_layerblend2_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND2_STATUS_layerblend2_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND2_STATUS_layerblend2_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND2_STATUS_layerblend2_sel_MASK)

/*! @name PIXENGCFG_LAYERBLEND3_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_layerblend3_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_layerblend3_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_layerblend3_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_layerblend3_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_layerblend3_LockUnlock_MASK)

/*! @name PIXENGCFG_LAYERBLEND3_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_layerblend3_FreezeStatus_MASK)

/*! @name PIXENGCFG_LAYERBLEND3_DYNAMIC - Dynamic pixel engine configuration for layerblend3 */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel_MASK (0x3F00U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND3_DYNAMIC_layerblend3_clken_MASK)

/*! @name PIXENGCFG_LAYERBLEND3_STATUS - Status information for pixel engine configuration of layerblend3 */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_STATUS_layerblend3_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_STATUS_layerblend3_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND3_STATUS_layerblend3_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND3_STATUS_layerblend3_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND3_STATUS_layerblend3_sel_MASK)

/*! @name PIXENGCFG_LAYERBLEND4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKUNLOCK_layerblend4_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKUNLOCK_layerblend4_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKUNLOCK_layerblend4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKUNLOCK_layerblend4_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKUNLOCK_layerblend4_LockUnlock_MASK)

/*! @name PIXENGCFG_LAYERBLEND4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND4_LOCKSTATUS_layerblend4_FreezeStatus_MASK)

/*! @name PIXENGCFG_LAYERBLEND4_DYNAMIC - Dynamic pixel engine configuration for layerblend4 */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_prim_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_prim_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_prim_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_prim_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_sec_sel_MASK (0x3F00U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_sec_sel_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_sec_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_sec_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND4_DYNAMIC_layerblend4_clken_MASK)

/*! @name PIXENGCFG_LAYERBLEND4_STATUS - Status information for pixel engine configuration of layerblend4 */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_STATUS_layerblend4_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_STATUS_layerblend4_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND4_STATUS_layerblend4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND4_STATUS_layerblend4_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND4_STATUS_layerblend4_sel_MASK)

/*! @name PIXENGCFG_LAYERBLEND5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKUNLOCK_layerblend5_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKUNLOCK_layerblend5_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKUNLOCK_layerblend5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKUNLOCK_layerblend5_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKUNLOCK_layerblend5_LockUnlock_MASK)

/*! @name PIXENGCFG_LAYERBLEND5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND5_LOCKSTATUS_layerblend5_FreezeStatus_MASK)

/*! @name PIXENGCFG_LAYERBLEND5_DYNAMIC - Dynamic pixel engine configuration for layerblend5 */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_prim_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_prim_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_prim_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_prim_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_sec_sel_MASK (0x3F00U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_sec_sel_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_sec_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_sec_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND5_DYNAMIC_layerblend5_clken_MASK)

/*! @name PIXENGCFG_LAYERBLEND5_STATUS - Status information for pixel engine configuration of layerblend5 */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_STATUS_layerblend5_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_STATUS_layerblend5_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND5_STATUS_layerblend5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND5_STATUS_layerblend5_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND5_STATUS_layerblend5_sel_MASK)

/*! @name PIXENGCFG_LAYERBLEND6_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKUNLOCK_layerblend6_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKUNLOCK_layerblend6_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKUNLOCK_layerblend6_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKUNLOCK_layerblend6_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKUNLOCK_layerblend6_LockUnlock_MASK)

/*! @name PIXENGCFG_LAYERBLEND6_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND6_LOCKSTATUS_layerblend6_FreezeStatus_MASK)

/*! @name PIXENGCFG_LAYERBLEND6_DYNAMIC - Dynamic pixel engine configuration for layerblend6 */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_prim_sel_MASK (0x3FU)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_prim_sel_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_prim_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_prim_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_sec_sel_MASK (0x3F00U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_sec_sel_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_sec_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_sec_sel_MASK)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_clken_MASK (0x3000000U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_clken_SHIFT (24U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_clken_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND6_DYNAMIC_layerblend6_clken_MASK)

/*! @name PIXENGCFG_LAYERBLEND6_STATUS - Status information for pixel engine configuration of layerblend6 */
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_STATUS_layerblend6_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_STATUS_layerblend6_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_LAYERBLEND6_STATUS_layerblend6_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_LAYERBLEND6_STATUS_layerblend6_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_LAYERBLEND6_STATUS_layerblend6_sel_MASK)

/*! @name PIXENGCFG_EXTSRC0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKUNLOCK_extsrc0_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKUNLOCK_extsrc0_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKUNLOCK_extsrc0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKUNLOCK_extsrc0_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKUNLOCK_extsrc0_LockUnlock_MASK)

/*! @name PIXENGCFG_EXTSRC0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC0_LOCKSTATUS_extsrc0_FreezeStatus_MASK)

/*! @name PIXENGCFG_EXTSRC0_STATUS - Status information for pixel engine configuration of extsrc0 */
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_STATUS_extsrc0_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_STATUS_extsrc0_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC0_STATUS_extsrc0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC0_STATUS_extsrc0_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC0_STATUS_extsrc0_sel_MASK)

/*! @name PIXENGCFG_EXTSRC1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKUNLOCK_extsrc1_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKUNLOCK_extsrc1_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKUNLOCK_extsrc1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKUNLOCK_extsrc1_LockUnlock_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKUNLOCK_extsrc1_LockUnlock_MASK)

/*! @name PIXENGCFG_EXTSRC1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_LockStatus_MASK (0x1U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_LockStatus_SHIFT (0U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_LockStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_LockStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_PrivilegeStatus_MASK)
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_FreezeStatus_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC1_LOCKSTATUS_extsrc1_FreezeStatus_MASK)

/*! @name PIXENGCFG_EXTSRC1_STATUS - Status information for pixel engine configuration of extsrc1 */
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_STATUS_extsrc1_sel_MASK (0x70000U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_STATUS_extsrc1_sel_SHIFT (16U)
#define IRIS_MVPL_PIXENGCFG_EXTSRC1_STATUS_extsrc1_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_PIXENGCFG_EXTSRC1_STATUS_extsrc1_sel_SHIFT)) & IRIS_MVPL_PIXENGCFG_EXTSRC1_STATUS_extsrc1_sel_MASK)

/*! @name FETCHDECODE9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FETCHDECODE9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FETCHDECODE9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FETCHDECODE9_STATICCONTROL - Common static control options. */
#define IRIS_MVPL_FETCHDECODE9_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE9_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHDECODE9_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_FETCHDECODE9_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHDECODE9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE9_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHDECODE9_STATICCONTROL_BaseAddressAutoUpdate_MASK)

/*! @name FETCHDECODE9_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LineMode_MASK)

/*! @name FETCHDECODE9_RINGBUFSTARTADDR0 - Ring buffer setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE9_RINGBUFSTARTADDR0_RingBufStartAddr0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE9_RINGBUFSTARTADDR0_RingBufStartAddr0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_RINGBUFSTARTADDR0_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_RINGBUFSTARTADDR0_RingBufStartAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_RINGBUFSTARTADDR0_RingBufStartAddr0_MASK)

/*! @name FETCHDECODE9_RINGBUFWRAPADDR0 - Ring buffer setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE9_RINGBUFWRAPADDR0_RingBufWrapAddr0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE9_RINGBUFWRAPADDR0_RingBufWrapAddr0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_RINGBUFWRAPADDR0_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_RINGBUFWRAPADDR0_RingBufWrapAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_RINGBUFWRAPADDR0_RingBufWrapAddr0_MASK)

/*! @name FETCHDECODE9_FRAMEPROPERTIES0 - Frame property setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE9_FRAMEPROPERTIES0_FieldId0_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE9_FRAMEPROPERTIES0_FieldId0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_FRAMEPROPERTIES0_FieldId0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_FRAMEPROPERTIES0_FieldId0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_FRAMEPROPERTIES0_FieldId0_MASK)

/*! @name FETCHDECODE9_BASEADDRESS0 - Source buffer base address of layer 0. */
#define IRIS_MVPL_FETCHDECODE9_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE9_BASEADDRESS0_BaseAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_BASEADDRESS0_BaseAddress0_MASK)

/*! @name FETCHDECODE9_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)

/*! @name FETCHDECODE9_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LineCount0_MASK)

/*! @name FETCHDECODE9_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTBITS0_ITUFormat0_MASK)

/*! @name FETCHDECODE9_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)

/*! @name FETCHDECODE9_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
#define IRIS_MVPL_FETCHDECODE9_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHDECODE9_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYEROFFSET0_LayerXOffset0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHDECODE9_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE9_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYEROFFSET0_LayerYOffset0_MASK)

/*! @name FETCHDECODE9_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
#define IRIS_MVPL_FETCHDECODE9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHDECODE9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
#define IRIS_MVPL_FETCHDECODE9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHDECODE9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE9_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)

/*! @name FETCHDECODE9_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
#define IRIS_MVPL_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
#define IRIS_MVPL_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)

/*! @name FETCHDECODE9_CONSTANTCOLOR0 - Constant color for layer 0. */
#define IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
#define IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CONSTANTCOLOR0_ConstantRed0_MASK)

/*! @name FETCHDECODE9_LAYERPROPERTY0 - Common properties of layer 0. */
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_PaletteEnable0_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_PaletteEnable0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_PaletteEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_PaletteEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_TileMode0_MASK (0x30U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_TileMode0_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_TileMode0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaSrcEnable0_MASK (0x100U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaConstEnable0_MASK (0x200U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaConstEnable0_SHIFT (9U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaMaskEnable0_MASK (0x400U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT (10U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaMaskEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaTransEnable0_MASK (0x800U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaTransEnable0_SHIFT (11U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_AlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK (0x1000U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT (12U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK (0x2000U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT (13U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK (0x4000U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT (14U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK (0x8000U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT (15U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_PremulConstRGB0_MASK (0x10000U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_PremulConstRGB0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_PremulConstRGB0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_YUVConversionMode0_MASK (0x60000U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_YUVConversionMode0_SHIFT (17U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_YUVConversionMode0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_GammaRemoveEnable0_MASK (0x100000U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT (20U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_GammaRemoveEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_ClipWindowEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_LAYERPROPERTY0_SourceBufferEnable0_MASK)

/*! @name FETCHDECODE9_FRAMEDIMENSIONS - Output frame dimension. */
#define IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHDECODE9_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name FETCHDECODE9_FRAMERESAMPLING - Resampling options for output frame. */
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_StartX_MASK (0x3FU)
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_StartX_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_StartX_MASK)
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_StartY_MASK (0xFC0U)
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_StartY_SHIFT (6U)
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_StartY_MASK)
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_DeltaX_SHIFT (12U)
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_DeltaX_MASK)
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_DeltaY_SHIFT (18U)
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_DeltaY_MASK)
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHDECODE9_FRAMERESAMPLING_SwapDirection_MASK)

/*! @name FETCHDECODE9_DECODECONTROL - Control options for RLAD decompression. */
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_CompressionMode_MASK (0x3U)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_CompressionMode_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_DECODECONTROL_CompressionMode_SHIFT)) & IRIS_MVPL_FETCHDECODE9_DECODECONTROL_CompressionMode_MASK)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADEndianness_MASK (0x8000U)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADEndianness_SHIFT (15U)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADEndianness(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADEndianness_SHIFT)) & IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADEndianness_MASK)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsRed_MASK (0xF0000U)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsRed_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsRed_SHIFT)) & IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsRed_MASK)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsGreen_MASK (0xF00000U)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsGreen_SHIFT (20U)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsGreen_SHIFT)) & IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsGreen_MASK)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsBlue_MASK (0xF000000U)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsBlue_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsBlue_SHIFT)) & IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsBlue_MASK)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsAlpha_MASK (0xF0000000U)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsAlpha_SHIFT (28U)
#define IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsAlpha_SHIFT)) & IRIS_MVPL_FETCHDECODE9_DECODECONTROL_RLADCompBitsAlpha_MASK)

/*! @name FETCHDECODE9_SOURCEBUFFERLENGTH - Source buffer length for compressed data. */
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERLENGTH_RLEWords_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERLENGTH_RLEWords_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERLENGTH_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERLENGTH_RLEWords_SHIFT)) & IRIS_MVPL_FETCHDECODE9_SOURCEBUFFERLENGTH_RLEWords_MASK)

/*! @name FETCHDECODE9_CONTROL - Shared common control settings for all layers. */
#define IRIS_MVPL_FETCHDECODE9_CONTROL_RasterMode_MASK (0x7U)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_RasterMode_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CONTROL_RasterMode_MASK)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_InputSelect_MASK (0x18U)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_InputSelect_SHIFT (3U)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CONTROL_InputSelect_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CONTROL_InputSelect_MASK)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_YUV422UpsamplingMode_MASK (0x20U)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_YUV422UpsamplingMode_SHIFT (5U)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CONTROL_YUV422UpsamplingMode_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CONTROL_YUV422UpsamplingMode_MASK)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_RawPixel_MASK (0x80U)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_RawPixel_SHIFT (7U)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CONTROL_RawPixel_MASK)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_PaletteIdxWidth_MASK (0x700U)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_PaletteIdxWidth_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CONTROL_PaletteIdxWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CONTROL_PaletteIdxWidth_MASK)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_ClipColor_MASK (0x10000U)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_ClipColor_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE9_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CONTROL_ClipColor_MASK)

/*! @name FETCHDECODE9_CONTROLTRIGGER - Shadow load trigger. */
#define IRIS_MVPL_FETCHDECODE9_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE9_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHDECODE9_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name FETCHDECODE9_START - Frame start trigger. */
#define IRIS_MVPL_FETCHDECODE9_START_Start_MASK  (0x1U)
#define IRIS_MVPL_FETCHDECODE9_START_Start_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_START_Start(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_START_Start_SHIFT)) & IRIS_MVPL_FETCHDECODE9_START_Start_MASK)

/*! @name FETCHDECODE9_FETCHTYPE - Fetch unit type. */
#define IRIS_MVPL_FETCHDECODE9_FETCHTYPE_FetchType_MASK (0xFU)
#define IRIS_MVPL_FETCHDECODE9_FETCHTYPE_FetchType_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHDECODE9_FETCHTYPE_FetchType_MASK)

/*! @name FETCHDECODE9_DECODERSTATUS - Status information of the RLAD decoder. */
#define IRIS_MVPL_FETCHDECODE9_DECODERSTATUS_BufferTooSmall_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE9_DECODERSTATUS_BufferTooSmall_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_DECODERSTATUS_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_DECODERSTATUS_BufferTooSmall_SHIFT)) & IRIS_MVPL_FETCHDECODE9_DECODERSTATUS_BufferTooSmall_MASK)
#define IRIS_MVPL_FETCHDECODE9_DECODERSTATUS_BufferTooLarge_MASK (0x2U)
#define IRIS_MVPL_FETCHDECODE9_DECODERSTATUS_BufferTooLarge_SHIFT (1U)
#define IRIS_MVPL_FETCHDECODE9_DECODERSTATUS_BufferTooLarge(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_DECODERSTATUS_BufferTooLarge_SHIFT)) & IRIS_MVPL_FETCHDECODE9_DECODERSTATUS_BufferTooLarge_MASK)

/*! @name FETCHDECODE9_READADDRESS0 - Ring buffer synchronization for layer 0. */
#define IRIS_MVPL_FETCHDECODE9_READADDRESS0_ReadAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE9_READADDRESS0_ReadAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_READADDRESS0_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_READADDRESS0_ReadAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE9_READADDRESS0_ReadAddress0_MASK)

/*! @name FETCHDECODE9_BURSTBUFFERPROPERTIES - Burst buffer properties. */
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)

/*! @name FETCHDECODE9_STATUS - Status informations. */
#define IRIS_MVPL_FETCHDECODE9_STATUS_WriteTimeout_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE9_STATUS_WriteTimeout_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE9_STATUS_WriteTimeout_MASK)
#define IRIS_MVPL_FETCHDECODE9_STATUS_ReadTimeout_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE9_STATUS_ReadTimeout_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE9_STATUS_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_STATUS_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE9_STATUS_ReadTimeout_MASK)

/*! @name FETCHDECODE9_HIDDENSTATUS - Hidden status informations. */
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusBusy_MASK)
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusRequest_MASK)
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_StatusComplete_MASK)
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE9_HIDDENSTATUS_ShadowStatus_MASK)

/*! @name FETCHDECODE9_COLORPALETTE - Color palette look up table. */
#define IRIS_MVPL_FETCHDECODE9_COLORPALETTE_ColorPalette_MASK (0xFFFFFFU)
#define IRIS_MVPL_FETCHDECODE9_COLORPALETTE_ColorPalette_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE9_COLORPALETTE_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE9_COLORPALETTE_ColorPalette_SHIFT)) & IRIS_MVPL_FETCHDECODE9_COLORPALETTE_ColorPalette_MASK)

/*! @name FETCHPERSP9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FETCHPERSP9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHPERSP9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FETCHPERSP9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FETCHPERSP9_STATICCONTROL - Common static control options. */
#define IRIS_MVPL_FETCHPERSP9_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_FETCHPERSP9_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHPERSP9_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_FETCHPERSP9_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHPERSP9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
#define IRIS_MVPL_FETCHPERSP9_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHPERSP9_STATICCONTROL_BaseAddressAutoUpdate_MASK)

/*! @name FETCHPERSP9_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHPERSP9_BURSTBUFFERMANAGEMENT_LineMode_MASK)

/*! @name FETCHPERSP9_BASEADDRESS0 - Source buffer base address of layer 0. */
#define IRIS_MVPL_FETCHPERSP9_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHPERSP9_BASEADDRESS0_BaseAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_BASEADDRESS0_BaseAddress0_MASK)

/*! @name FETCHPERSP9_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
#define IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
#define IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
#define IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)

/*! @name FETCHPERSP9_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
#define IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
#define IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
#define IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_SOURCEBUFFERDIMENSION0_LineCount0_MASK)

/*! @name FETCHPERSP9_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTBITS0_ITUFormat0_MASK)

/*! @name FETCHPERSP9_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)

/*! @name FETCHPERSP9_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
#define IRIS_MVPL_FETCHPERSP9_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHPERSP9_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYEROFFSET0_LayerXOffset0_MASK)
#define IRIS_MVPL_FETCHPERSP9_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHPERSP9_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHPERSP9_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYEROFFSET0_LayerYOffset0_MASK)

/*! @name FETCHPERSP9_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
#define IRIS_MVPL_FETCHPERSP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHPERSP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
#define IRIS_MVPL_FETCHPERSP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHPERSP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHPERSP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)

/*! @name FETCHPERSP9_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
#define IRIS_MVPL_FETCHPERSP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHPERSP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
#define IRIS_MVPL_FETCHPERSP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHPERSP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
#define IRIS_MVPL_FETCHPERSP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)

/*! @name FETCHPERSP9_CONSTANTCOLOR0 - Constant color for layer 0. */
#define IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
#define IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantAlpha0_MASK)
#define IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
#define IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantBlue0_MASK)
#define IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantGreen0_MASK)
#define IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CONSTANTCOLOR0_ConstantRed0_MASK)

/*! @name FETCHPERSP9_LAYERPROPERTY0 - Common properties of layer 0. */
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_TileMode0_MASK (0x30U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_TileMode0_SHIFT (4U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_TileMode0_MASK)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaSrcEnable0_MASK (0x100U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT (8U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaConstEnable0_MASK (0x200U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaConstEnable0_SHIFT (9U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaMaskEnable0_MASK (0x400U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT (10U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaMaskEnable0_MASK)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaTransEnable0_MASK (0x800U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaTransEnable0_SHIFT (11U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_AlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK (0x1000U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT (12U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK (0x2000U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT (13U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK (0x4000U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT (14U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK (0x8000U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT (15U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_PremulConstRGB0_MASK (0x10000U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_PremulConstRGB0_SHIFT (16U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_PremulConstRGB0_MASK)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_YUVConversionMode0_MASK (0x60000U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_YUVConversionMode0_SHIFT (17U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_YUVConversionMode0_MASK)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_GammaRemoveEnable0_MASK (0x100000U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT (20U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_GammaRemoveEnable0_MASK)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_ClipWindowEnable0_MASK)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
#define IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHPERSP9_LAYERPROPERTY0_SourceBufferEnable0_MASK)

/*! @name FETCHPERSP9_FRAMEDIMENSIONS - Output frame dimension. */
#define IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name FETCHPERSP9_FRAMERESAMPLING - Resampling options for output frame. */
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_StartX_MASK (0x3FU)
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_StartX_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_StartX_MASK)
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_StartY_MASK (0xFC0U)
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_StartY_SHIFT (6U)
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_StartY_MASK)
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_DeltaX_SHIFT (12U)
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_DeltaX_MASK)
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_DeltaY_SHIFT (18U)
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_DeltaY_MASK)
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
#define IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FRAMERESAMPLING_SwapDirection_MASK)

/*! @name FETCHPERSP9_WARPCONTROL - Warping control options. */
#define IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpBitsPerPixel_MASK (0x3FU)
#define IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpBitsPerPixel_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpBitsPerPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpBitsPerPixel_SHIFT)) & IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpBitsPerPixel_MASK)
#define IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpCoordinateMode_MASK (0x300U)
#define IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpCoordinateMode_SHIFT (8U)
#define IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpCoordinateMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpCoordinateMode_SHIFT)) & IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpCoordinateMode_MASK)
#define IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpSymmetricOffset_MASK (0x1000U)
#define IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpSymmetricOffset_SHIFT (12U)
#define IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpSymmetricOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpSymmetricOffset_SHIFT)) & IRIS_MVPL_FETCHPERSP9_WARPCONTROL_WarpSymmetricOffset_MASK)

/*! @name FETCHPERSP9_PERSPSTARTX - Start value X for affine/perspective warping. */
#define IRIS_MVPL_FETCHPERSP9_PERSPSTARTX_PerspStartX_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHPERSP9_PERSPSTARTX_PerspStartX_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_PERSPSTARTX_PerspStartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_PERSPSTARTX_PerspStartX_SHIFT)) & IRIS_MVPL_FETCHPERSP9_PERSPSTARTX_PerspStartX_MASK)

/*! @name FETCHPERSP9_PERSPSTARTY - Start value Y for affine/perspective warping. */
#define IRIS_MVPL_FETCHPERSP9_PERSPSTARTY_PerspStartY_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHPERSP9_PERSPSTARTY_PerspStartY_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_PERSPSTARTY_PerspStartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_PERSPSTARTY_PerspStartY_SHIFT)) & IRIS_MVPL_FETCHPERSP9_PERSPSTARTY_PerspStartY_MASK)

/*! @name FETCHPERSP9_PERSPSTARTW - Start value W for perspective warping. */
#define IRIS_MVPL_FETCHPERSP9_PERSPSTARTW_PerspStartW_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHPERSP9_PERSPSTARTW_PerspStartW_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_PERSPSTARTW_PerspStartW(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_PERSPSTARTW_PerspStartW_SHIFT)) & IRIS_MVPL_FETCHPERSP9_PERSPSTARTW_PerspStartW_MASK)

/*! @name FETCHPERSP9_PERSPDELTAXX - DeltaXX increment for affine/perspective warping. */
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAXX_PerspDeltaXX_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAXX_PerspDeltaXX_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAXX_PerspDeltaXX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_PERSPDELTAXX_PerspDeltaXX_SHIFT)) & IRIS_MVPL_FETCHPERSP9_PERSPDELTAXX_PerspDeltaXX_MASK)

/*! @name FETCHPERSP9_PERSPDELTAXY - DeltaXY increment for affine/perspective warping. */
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAXY_PerspDeltaXY_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAXY_PerspDeltaXY_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAXY_PerspDeltaXY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_PERSPDELTAXY_PerspDeltaXY_SHIFT)) & IRIS_MVPL_FETCHPERSP9_PERSPDELTAXY_PerspDeltaXY_MASK)

/*! @name FETCHPERSP9_PERSPDELTAXW - DeltaWX increment for perspective warping. */
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAXW_PerspDeltaXW_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAXW_PerspDeltaXW_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAXW_PerspDeltaXW(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_PERSPDELTAXW_PerspDeltaXW_SHIFT)) & IRIS_MVPL_FETCHPERSP9_PERSPDELTAXW_PerspDeltaXW_MASK)

/*! @name FETCHPERSP9_PERSPDELTAYX - DeltaXX increment for affine/perspective warping. */
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAYX_PerspDeltaYX_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAYX_PerspDeltaYX_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAYX_PerspDeltaYX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_PERSPDELTAYX_PerspDeltaYX_SHIFT)) & IRIS_MVPL_FETCHPERSP9_PERSPDELTAYX_PerspDeltaYX_MASK)

/*! @name FETCHPERSP9_PERSPDELTAYY - DeltaYY increment for affine/perspective warping. */
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAYY_PerspDeltaYY_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAYY_PerspDeltaYY_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAYY_PerspDeltaYY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_PERSPDELTAYY_PerspDeltaYY_SHIFT)) & IRIS_MVPL_FETCHPERSP9_PERSPDELTAYY_PerspDeltaYY_MASK)

/*! @name FETCHPERSP9_PERSPDELTAYW - DeltaWY increment for perspective warping. */
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAYW_PerspDeltaYW_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAYW_PerspDeltaYW_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_PERSPDELTAYW_PerspDeltaYW(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_PERSPDELTAYW_PerspDeltaYW_SHIFT)) & IRIS_MVPL_FETCHPERSP9_PERSPDELTAYW_PerspDeltaYW_MASK)

/*! @name FETCHPERSP9_ARBSTARTX - Start value X for arbitrary warping. */
#define IRIS_MVPL_FETCHPERSP9_ARBSTARTX_ArbStartX_MASK (0x1FFFFFU)
#define IRIS_MVPL_FETCHPERSP9_ARBSTARTX_ArbStartX_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_ARBSTARTX_ArbStartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_ARBSTARTX_ArbStartX_SHIFT)) & IRIS_MVPL_FETCHPERSP9_ARBSTARTX_ArbStartX_MASK)

/*! @name FETCHPERSP9_ARBSTARTY - Start value Y for arbitrary warping. */
#define IRIS_MVPL_FETCHPERSP9_ARBSTARTY_ArbStartY_MASK (0x1FFFFFU)
#define IRIS_MVPL_FETCHPERSP9_ARBSTARTY_ArbStartY_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_ARBSTARTY_ArbStartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_ARBSTARTY_ArbStartY_SHIFT)) & IRIS_MVPL_FETCHPERSP9_ARBSTARTY_ArbStartY_MASK)

/*! @name FETCHPERSP9_ARBDELTA - Start values for delta incrementation of arbitrary warping. */
#define IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaXX_MASK (0xFFU)
#define IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaXX_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaXX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaXX_SHIFT)) & IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaXX_MASK)
#define IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaXY_MASK (0xFF00U)
#define IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaXY_SHIFT (8U)
#define IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaXY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaXY_SHIFT)) & IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaXY_MASK)
#define IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaYX_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaYX_SHIFT (16U)
#define IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaYX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaYX_SHIFT)) & IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaYX_MASK)
#define IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaYY_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaYY_SHIFT (24U)
#define IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaYY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaYY_SHIFT)) & IRIS_MVPL_FETCHPERSP9_ARBDELTA_ArbDeltaYY_MASK)

/*! @name FETCHPERSP9_FIRPOSITIONS - FIR sequence control register. */
#define IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR0Position_MASK (0xFU)
#define IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR0Position_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR0Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR0Position_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR0Position_MASK)
#define IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR1Position_MASK (0xF0U)
#define IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR1Position_SHIFT (4U)
#define IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR1Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR1Position_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR1Position_MASK)
#define IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR2Position_MASK (0xF00U)
#define IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR2Position_SHIFT (8U)
#define IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR2Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR2Position_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR2Position_MASK)
#define IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR3Position_MASK (0xF000U)
#define IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR3Position_SHIFT (12U)
#define IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR3Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR3Position_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FIRPOSITIONS_FIR3Position_MASK)

/*! @name FETCHPERSP9_FIRCOEFFICIENTS - FIR coefficients register. */
#define IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR0Coefficient_MASK (0xFFU)
#define IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR0Coefficient_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR0Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR0Coefficient_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR0Coefficient_MASK)
#define IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR1Coefficient_MASK (0xFF00U)
#define IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR1Coefficient_SHIFT (8U)
#define IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR1Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR1Coefficient_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR1Coefficient_MASK)
#define IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR2Coefficient_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR2Coefficient_SHIFT (16U)
#define IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR2Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR2Coefficient_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR2Coefficient_MASK)
#define IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR3Coefficient_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR3Coefficient_SHIFT (24U)
#define IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR3Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR3Coefficient_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FIRCOEFFICIENTS_FIR3Coefficient_MASK)

/*! @name FETCHPERSP9_CONTROL - Shared common control settings for all layers. */
#define IRIS_MVPL_FETCHPERSP9_CONTROL_RasterMode_MASK (0x7U)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_RasterMode_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CONTROL_RasterMode_MASK)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_InputSelect_MASK (0x18U)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_InputSelect_SHIFT (3U)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CONTROL_InputSelect_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CONTROL_InputSelect_MASK)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_YUV422UpsamplingMode_MASK (0x20U)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_YUV422UpsamplingMode_SHIFT (5U)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CONTROL_YUV422UpsamplingMode_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CONTROL_YUV422UpsamplingMode_MASK)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_RawPixel_MASK (0x80U)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_RawPixel_SHIFT (7U)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CONTROL_RawPixel_MASK)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_ClipColor_MASK (0x10000U)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_ClipColor_SHIFT (16U)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CONTROL_ClipColor_MASK)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_FilterMode_MASK (0x700000U)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_FilterMode_SHIFT (20U)
#define IRIS_MVPL_FETCHPERSP9_CONTROL_FilterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CONTROL_FilterMode_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CONTROL_FilterMode_MASK)

/*! @name FETCHPERSP9_CONTROLTRIGGER - Shadow load trigger. */
#define IRIS_MVPL_FETCHPERSP9_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FETCHPERSP9_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHPERSP9_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name FETCHPERSP9_START - Frame start trigger. */
#define IRIS_MVPL_FETCHPERSP9_START_Start_MASK   (0x1U)
#define IRIS_MVPL_FETCHPERSP9_START_Start_SHIFT  (0U)
#define IRIS_MVPL_FETCHPERSP9_START_Start(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_START_Start_SHIFT)) & IRIS_MVPL_FETCHPERSP9_START_Start_MASK)

/*! @name FETCHPERSP9_FETCHTYPE - Fetch unit type. */
#define IRIS_MVPL_FETCHPERSP9_FETCHTYPE_FetchType_MASK (0xFU)
#define IRIS_MVPL_FETCHPERSP9_FETCHTYPE_FetchType_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHPERSP9_FETCHTYPE_FetchType_MASK)

/*! @name FETCHPERSP9_BURSTBUFFERPROPERTIES - Burst buffer properties. */
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHPERSP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
#define IRIS_MVPL_FETCHPERSP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHPERSP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)

/*! @name FETCHPERSP9_HIDDENSTATUS - Hidden status informations. */
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusBusy_MASK)
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusRequest_MASK)
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_StatusComplete_MASK)
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHPERSP9_HIDDENSTATUS_ShadowStatus_MASK)

/*! @name FETCHECO9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FETCHECO9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FETCHECO9_STATICCONTROL - Common static control options. */
#define IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
#define IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate_MASK)

/*! @name FETCHECO9_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode_MASK)

/*! @name FETCHECO9_BASEADDRESS0 - Source buffer base address of layer 0. */
#define IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0_MASK)

/*! @name FETCHECO9_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)

/*! @name FETCHECO9_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0_MASK)

/*! @name FETCHECO9_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0_MASK)

/*! @name FETCHECO9_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)

/*! @name FETCHECO9_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
#define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0_MASK)
#define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0_MASK)

/*! @name FETCHECO9_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
#define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
#define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)

/*! @name FETCHECO9_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
#define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
#define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)

/*! @name FETCHECO9_CONSTANTCOLOR0 - Constant color for layer 0. */
#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0_MASK)
#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0_MASK)
#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0_MASK)
#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0_MASK)

/*! @name FETCHECO9_LAYERPROPERTY0 - Common properties of layer 0. */
#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0_MASK (0x30U)
#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0_SHIFT (4U)
#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0_MASK)
#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0_MASK)
#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0_MASK)

/*! @name FETCHECO9_FRAMEDIMENSIONS - Output frame dimension. */
#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name FETCHECO9_FRAMERESAMPLING - Resampling options for output frame. */
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX_MASK (0x3FU)
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX_MASK)
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY_MASK (0xFC0U)
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY_SHIFT (6U)
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY_MASK)
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX_SHIFT (12U)
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX_MASK)
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY_SHIFT (18U)
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY_MASK)
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection_MASK)

/*! @name FETCHECO9_CONTROL - Shared common control settings for all layers. */
#define IRIS_MVPL_FETCHECO9_CONTROL_RawPixel_MASK (0x80U)
#define IRIS_MVPL_FETCHECO9_CONTROL_RawPixel_SHIFT (7U)
#define IRIS_MVPL_FETCHECO9_CONTROL_RawPixel(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHECO9_CONTROL_RawPixel_MASK)
#define IRIS_MVPL_FETCHECO9_CONTROL_ClipColor_MASK (0x10000U)
#define IRIS_MVPL_FETCHECO9_CONTROL_ClipColor_SHIFT (16U)
#define IRIS_MVPL_FETCHECO9_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHECO9_CONTROL_ClipColor_MASK)

/*! @name FETCHECO9_CONTROLTRIGGER - Shadow load trigger. */
#define IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name FETCHECO9_START - Frame start trigger. */
#define IRIS_MVPL_FETCHECO9_START_Start_MASK     (0x1U)
#define IRIS_MVPL_FETCHECO9_START_Start_SHIFT    (0U)
#define IRIS_MVPL_FETCHECO9_START_Start(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_START_Start_SHIFT)) & IRIS_MVPL_FETCHECO9_START_Start_MASK)

/*! @name FETCHECO9_FETCHTYPE - Fetch unit type. */
#define IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType_MASK (0xFU)
#define IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType_MASK)

/*! @name FETCHECO9_BURSTBUFFERPROPERTIES - Burst buffer properties. */
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
#define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)

/*! @name FETCHECO9_HIDDENSTATUS - Hidden status informations. */
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy_MASK)
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest_MASK)
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete_MASK)
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus_MASK)

/*! @name ROP9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock_MASK)

/*! @name ROP9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus_MASK)

/*! @name ROP9_STATICCONTROL - Raster Operation static control register */
#define IRIS_MVPL_ROP9_STATICCONTROL_ShdEn_MASK  (0x1U)
#define IRIS_MVPL_ROP9_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_ROP9_STATICCONTROL_ShdEn(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_ROP9_STATICCONTROL_ShdEn_MASK)

/*! @name ROP9_CONTROL - Raster Operation control register */
#define IRIS_MVPL_ROP9_CONTROL_Mode_MASK         (0x1U)
#define IRIS_MVPL_ROP9_CONTROL_Mode_SHIFT        (0U)
#define IRIS_MVPL_ROP9_CONTROL_Mode(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_Mode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_Mode_MASK)
#define IRIS_MVPL_ROP9_CONTROL_AlphaMode_MASK    (0x10U)
#define IRIS_MVPL_ROP9_CONTROL_AlphaMode_SHIFT   (4U)
#define IRIS_MVPL_ROP9_CONTROL_AlphaMode(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_AlphaMode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_AlphaMode_MASK)
#define IRIS_MVPL_ROP9_CONTROL_BlueMode_MASK     (0x20U)
#define IRIS_MVPL_ROP9_CONTROL_BlueMode_SHIFT    (5U)
#define IRIS_MVPL_ROP9_CONTROL_BlueMode(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_BlueMode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_BlueMode_MASK)
#define IRIS_MVPL_ROP9_CONTROL_GreenMode_MASK    (0x40U)
#define IRIS_MVPL_ROP9_CONTROL_GreenMode_SHIFT   (6U)
#define IRIS_MVPL_ROP9_CONTROL_GreenMode(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_GreenMode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_GreenMode_MASK)
#define IRIS_MVPL_ROP9_CONTROL_RedMode_MASK      (0x80U)
#define IRIS_MVPL_ROP9_CONTROL_RedMode_SHIFT     (7U)
#define IRIS_MVPL_ROP9_CONTROL_RedMode(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_RedMode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_RedMode_MASK)
#define IRIS_MVPL_ROP9_CONTROL_PrimDiv2_MASK     (0x100U)
#define IRIS_MVPL_ROP9_CONTROL_PrimDiv2_SHIFT    (8U)
#define IRIS_MVPL_ROP9_CONTROL_PrimDiv2(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_PrimDiv2_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_PrimDiv2_MASK)
#define IRIS_MVPL_ROP9_CONTROL_SecDiv2_MASK      (0x200U)
#define IRIS_MVPL_ROP9_CONTROL_SecDiv2_SHIFT     (9U)
#define IRIS_MVPL_ROP9_CONTROL_SecDiv2(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_SecDiv2_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_SecDiv2_MASK)
#define IRIS_MVPL_ROP9_CONTROL_TertDiv2_MASK     (0x400U)
#define IRIS_MVPL_ROP9_CONTROL_TertDiv2_SHIFT    (10U)
#define IRIS_MVPL_ROP9_CONTROL_TertDiv2(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_TertDiv2_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_TertDiv2_MASK)

/*! @name ROP9_RASTEROPERATIONINDICES - ROP operation indices */
#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha_MASK (0xFFU)
#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha_SHIFT (0U)
#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha_SHIFT)) & IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha_MASK)
#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue_MASK (0xFF00U)
#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue_SHIFT (8U)
#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue_SHIFT)) & IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue_MASK)
#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen_MASK (0xFF0000U)
#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen_SHIFT (16U)
#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen_SHIFT)) & IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen_MASK)
#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed_MASK (0xFF000000U)
#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed_SHIFT (24U)
#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed_SHIFT)) & IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed_MASK)

/*! @name ROP9_PRIMCONTROLWORD - Value of last received primary control word */
#define IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL_SHIFT (0U)
#define IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL_MASK)

/*! @name ROP9_SECCONTROLWORD - Value of last received secondary control word */
#define IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL_SHIFT (0U)
#define IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL_MASK)

/*! @name ROP9_TERTCONTROLWORD - Value of last received tertiary control word */
#define IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL_SHIFT (0U)
#define IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL_SHIFT)) & IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL_MASK)

/*! @name CLUT9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock_MASK)

/*! @name CLUT9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus_MASK)

/*! @name CLUT9_STATICCONTROL - CLUT static control register */
#define IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn_MASK)

/*! @name CLUT9_UNSHADOWEDCONTROL - CLUT unshadowed control register */
#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN_MASK (0x1U)
#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN_SHIFT (0U)
#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN_SHIFT)) & IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN_MASK)
#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN_MASK (0x2U)
#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN_SHIFT (1U)
#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN_SHIFT)) & IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN_MASK)
#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN_MASK (0x4U)
#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN_SHIFT (2U)
#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN_SHIFT)) & IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN_MASK)

/*! @name CLUT9_CONTROL - CLUT control register */
#define IRIS_MVPL_CLUT9_CONTROL_MODE_MASK        (0x3U)
#define IRIS_MVPL_CLUT9_CONTROL_MODE_SHIFT       (0U)
#define IRIS_MVPL_CLUT9_CONTROL_MODE(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_MODE_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_MODE_MASK)
#define IRIS_MVPL_CLUT9_CONTROL_COL_8BIT_MASK    (0x10U)
#define IRIS_MVPL_CLUT9_CONTROL_COL_8BIT_SHIFT   (4U)
#define IRIS_MVPL_CLUT9_CONTROL_COL_8BIT(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_COL_8BIT_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_COL_8BIT_MASK)
#define IRIS_MVPL_CLUT9_CONTROL_AlphaMask_MASK   (0x20U)
#define IRIS_MVPL_CLUT9_CONTROL_AlphaMask_SHIFT  (5U)
#define IRIS_MVPL_CLUT9_CONTROL_AlphaMask(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_AlphaMask_MASK)
#define IRIS_MVPL_CLUT9_CONTROL_AlphaInvert_MASK (0x40U)
#define IRIS_MVPL_CLUT9_CONTROL_AlphaInvert_SHIFT (6U)
#define IRIS_MVPL_CLUT9_CONTROL_AlphaInvert(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_AlphaInvert_MASK)
#define IRIS_MVPL_CLUT9_CONTROL_IDX_BITS_MASK    (0xF00U)
#define IRIS_MVPL_CLUT9_CONTROL_IDX_BITS_SHIFT   (8U)
#define IRIS_MVPL_CLUT9_CONTROL_IDX_BITS(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_IDX_BITS_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_IDX_BITS_MASK)

/*! @name CLUT9_STATUS - CLUT status register */
#define IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT_MASK (0x1U)
#define IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT_SHIFT (0U)
#define IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT_SHIFT)) & IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT_MASK)
#define IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT_MASK (0x10U)
#define IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT_SHIFT (4U)
#define IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT_SHIFT)) & IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT_MASK)

/*! @name CLUT9_LASTCONTROLWORD - Value of last received control word, for debugging */
#define IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL_SHIFT (0U)
#define IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL_MASK)

/*! @name CLUT9_LUT - Look Up Table */
#define IRIS_MVPL_CLUT9_LUT_BLUE_MASK            (0x3FFU)
#define IRIS_MVPL_CLUT9_LUT_BLUE_SHIFT           (0U)
#define IRIS_MVPL_CLUT9_LUT_BLUE(x)              (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LUT_BLUE_SHIFT)) & IRIS_MVPL_CLUT9_LUT_BLUE_MASK)
#define IRIS_MVPL_CLUT9_LUT_GREEN_MASK           (0xFFC00U)
#define IRIS_MVPL_CLUT9_LUT_GREEN_SHIFT          (10U)
#define IRIS_MVPL_CLUT9_LUT_GREEN(x)             (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LUT_GREEN_SHIFT)) & IRIS_MVPL_CLUT9_LUT_GREEN_MASK)
#define IRIS_MVPL_CLUT9_LUT_RED_MASK             (0x3FF00000U)
#define IRIS_MVPL_CLUT9_LUT_RED_SHIFT            (20U)
#define IRIS_MVPL_CLUT9_LUT_RED(x)               (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LUT_RED_SHIFT)) & IRIS_MVPL_CLUT9_LUT_RED_MASK)

/*! @name MATRIX9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock_MASK)

/*! @name MATRIX9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus_MASK)

/*! @name MATRIX9_STATICCONTROL - Color Matrix static control register */
#define IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn_MASK)

/*! @name MATRIX9_CONTROL - Color Matrix control register */
#define IRIS_MVPL_MATRIX9_CONTROL_MODE_MASK      (0x3U)
#define IRIS_MVPL_MATRIX9_CONTROL_MODE_SHIFT     (0U)
#define IRIS_MVPL_MATRIX9_CONTROL_MODE(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_CONTROL_MODE_SHIFT)) & IRIS_MVPL_MATRIX9_CONTROL_MODE_MASK)
#define IRIS_MVPL_MATRIX9_CONTROL_AlphaMask_MASK (0x10U)
#define IRIS_MVPL_MATRIX9_CONTROL_AlphaMask_SHIFT (4U)
#define IRIS_MVPL_MATRIX9_CONTROL_AlphaMask(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_MATRIX9_CONTROL_AlphaMask_MASK)
#define IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert_MASK (0x20U)
#define IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert_SHIFT (5U)
#define IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert_MASK)

/*! @name MATRIX9_RED0 - Matrix values for calculation of the red output value. */
#define IRIS_MVPL_MATRIX9_RED0_A11_MASK          (0x1FFFU)
#define IRIS_MVPL_MATRIX9_RED0_A11_SHIFT         (0U)
#define IRIS_MVPL_MATRIX9_RED0_A11(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_RED0_A11_SHIFT)) & IRIS_MVPL_MATRIX9_RED0_A11_MASK)
#define IRIS_MVPL_MATRIX9_RED0_A12_MASK          (0x1FFF0000U)
#define IRIS_MVPL_MATRIX9_RED0_A12_SHIFT         (16U)
#define IRIS_MVPL_MATRIX9_RED0_A12(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_RED0_A12_SHIFT)) & IRIS_MVPL_MATRIX9_RED0_A12_MASK)

/*! @name MATRIX9_RED1 - Matrix values for calculation of the red output value. */
#define IRIS_MVPL_MATRIX9_RED1_A13_MASK          (0x1FFFU)
#define IRIS_MVPL_MATRIX9_RED1_A13_SHIFT         (0U)
#define IRIS_MVPL_MATRIX9_RED1_A13(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_RED1_A13_SHIFT)) & IRIS_MVPL_MATRIX9_RED1_A13_MASK)
#define IRIS_MVPL_MATRIX9_RED1_A14_MASK          (0x1FFF0000U)
#define IRIS_MVPL_MATRIX9_RED1_A14_SHIFT         (16U)
#define IRIS_MVPL_MATRIX9_RED1_A14(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_RED1_A14_SHIFT)) & IRIS_MVPL_MATRIX9_RED1_A14_MASK)

/*! @name MATRIX9_GREEN0 - Matrix values for calculation of the green output value. */
#define IRIS_MVPL_MATRIX9_GREEN0_A21_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX9_GREEN0_A21_SHIFT       (0U)
#define IRIS_MVPL_MATRIX9_GREEN0_A21(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_GREEN0_A21_SHIFT)) & IRIS_MVPL_MATRIX9_GREEN0_A21_MASK)
#define IRIS_MVPL_MATRIX9_GREEN0_A22_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX9_GREEN0_A22_SHIFT       (16U)
#define IRIS_MVPL_MATRIX9_GREEN0_A22(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_GREEN0_A22_SHIFT)) & IRIS_MVPL_MATRIX9_GREEN0_A22_MASK)

/*! @name MATRIX9_GREEN1 - Matrix values for calculation of the green output value. */
#define IRIS_MVPL_MATRIX9_GREEN1_A23_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX9_GREEN1_A23_SHIFT       (0U)
#define IRIS_MVPL_MATRIX9_GREEN1_A23(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_GREEN1_A23_SHIFT)) & IRIS_MVPL_MATRIX9_GREEN1_A23_MASK)
#define IRIS_MVPL_MATRIX9_GREEN1_A24_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX9_GREEN1_A24_SHIFT       (16U)
#define IRIS_MVPL_MATRIX9_GREEN1_A24(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_GREEN1_A24_SHIFT)) & IRIS_MVPL_MATRIX9_GREEN1_A24_MASK)

/*! @name MATRIX9_BLUE0 - Matrix values for calculation of the blue output value. */
#define IRIS_MVPL_MATRIX9_BLUE0_A31_MASK         (0x1FFFU)
#define IRIS_MVPL_MATRIX9_BLUE0_A31_SHIFT        (0U)
#define IRIS_MVPL_MATRIX9_BLUE0_A31(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_BLUE0_A31_SHIFT)) & IRIS_MVPL_MATRIX9_BLUE0_A31_MASK)
#define IRIS_MVPL_MATRIX9_BLUE0_A32_MASK         (0x1FFF0000U)
#define IRIS_MVPL_MATRIX9_BLUE0_A32_SHIFT        (16U)
#define IRIS_MVPL_MATRIX9_BLUE0_A32(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_BLUE0_A32_SHIFT)) & IRIS_MVPL_MATRIX9_BLUE0_A32_MASK)

/*! @name MATRIX9_BLUE1 - Matrix values for calculation of the blue output value. */
#define IRIS_MVPL_MATRIX9_BLUE1_A33_MASK         (0x1FFFU)
#define IRIS_MVPL_MATRIX9_BLUE1_A33_SHIFT        (0U)
#define IRIS_MVPL_MATRIX9_BLUE1_A33(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_BLUE1_A33_SHIFT)) & IRIS_MVPL_MATRIX9_BLUE1_A33_MASK)
#define IRIS_MVPL_MATRIX9_BLUE1_A34_MASK         (0x1FFF0000U)
#define IRIS_MVPL_MATRIX9_BLUE1_A34_SHIFT        (16U)
#define IRIS_MVPL_MATRIX9_BLUE1_A34(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_BLUE1_A34_SHIFT)) & IRIS_MVPL_MATRIX9_BLUE1_A34_MASK)

/*! @name MATRIX9_ALPHA0 - Matrix values for calculation of the alpha output value. */
#define IRIS_MVPL_MATRIX9_ALPHA0_A41_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX9_ALPHA0_A41_SHIFT       (0U)
#define IRIS_MVPL_MATRIX9_ALPHA0_A41(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_ALPHA0_A41_SHIFT)) & IRIS_MVPL_MATRIX9_ALPHA0_A41_MASK)
#define IRIS_MVPL_MATRIX9_ALPHA0_A42_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX9_ALPHA0_A42_SHIFT       (16U)
#define IRIS_MVPL_MATRIX9_ALPHA0_A42(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_ALPHA0_A42_SHIFT)) & IRIS_MVPL_MATRIX9_ALPHA0_A42_MASK)

/*! @name MATRIX9_ALPHA1 - Matrix values for calculation of the alpha output value. */
#define IRIS_MVPL_MATRIX9_ALPHA1_A43_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX9_ALPHA1_A43_SHIFT       (0U)
#define IRIS_MVPL_MATRIX9_ALPHA1_A43(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_ALPHA1_A43_SHIFT)) & IRIS_MVPL_MATRIX9_ALPHA1_A43_MASK)
#define IRIS_MVPL_MATRIX9_ALPHA1_A44_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX9_ALPHA1_A44_SHIFT       (16U)
#define IRIS_MVPL_MATRIX9_ALPHA1_A44(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_ALPHA1_A44_SHIFT)) & IRIS_MVPL_MATRIX9_ALPHA1_A44_MASK)

/*! @name MATRIX9_OFFSETVECTOR0 - Offset vectors for red and green output. */
#define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1_MASK  (0x1FFFU)
#define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1_SHIFT (0U)
#define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1_SHIFT)) & IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1_MASK)
#define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2_MASK  (0x1FFF0000U)
#define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2_SHIFT (16U)
#define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2_SHIFT)) & IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2_MASK)

/*! @name MATRIX9_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */
#define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3_MASK  (0x1FFFU)
#define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3_SHIFT (0U)
#define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3_SHIFT)) & IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3_MASK)
#define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4_MASK  (0x1FFF0000U)
#define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4_SHIFT (16U)
#define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4_SHIFT)) & IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4_MASK)

/*! @name MATRIX9_LASTCONTROLWORD - Value of last received control word, for debugging. */
#define IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL_SHIFT (0U)
#define IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL_MASK)

/*! @name HSCALER9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock_MASK)

/*! @name HSCALER9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus_MASK)

/*! @name HSCALER9_STATICCONTROL - Static control settings that must typically be setup once only. */
#define IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn_MASK)

/*! @name HSCALER9_SETUP1 - Phase interpolator setup. */
#define IRIS_MVPL_HSCALER9_SETUP1_scale_factor_MASK (0xFFFFFU)
#define IRIS_MVPL_HSCALER9_SETUP1_scale_factor_SHIFT (0U)
#define IRIS_MVPL_HSCALER9_SETUP1_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_SETUP1_scale_factor_SHIFT)) & IRIS_MVPL_HSCALER9_SETUP1_scale_factor_MASK)

/*! @name HSCALER9_SETUP2 - Phase interpolator setup. */
#define IRIS_MVPL_HSCALER9_SETUP2_phase_offset_MASK (0x1FFFFFU)
#define IRIS_MVPL_HSCALER9_SETUP2_phase_offset_SHIFT (0U)
#define IRIS_MVPL_HSCALER9_SETUP2_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_SETUP2_phase_offset_SHIFT)) & IRIS_MVPL_HSCALER9_SETUP2_phase_offset_MASK)

/*! @name HSCALER9_CONTROL - Scaler operation control. */
#define IRIS_MVPL_HSCALER9_CONTROL_mode_MASK     (0x1U)
#define IRIS_MVPL_HSCALER9_CONTROL_mode_SHIFT    (0U)
#define IRIS_MVPL_HSCALER9_CONTROL_mode(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_CONTROL_mode_SHIFT)) & IRIS_MVPL_HSCALER9_CONTROL_mode_MASK)
#define IRIS_MVPL_HSCALER9_CONTROL_scale_mode_MASK (0x10U)
#define IRIS_MVPL_HSCALER9_CONTROL_scale_mode_SHIFT (4U)
#define IRIS_MVPL_HSCALER9_CONTROL_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_CONTROL_scale_mode_SHIFT)) & IRIS_MVPL_HSCALER9_CONTROL_scale_mode_MASK)
#define IRIS_MVPL_HSCALER9_CONTROL_filter_mode_MASK (0x100U)
#define IRIS_MVPL_HSCALER9_CONTROL_filter_mode_SHIFT (8U)
#define IRIS_MVPL_HSCALER9_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_HSCALER9_CONTROL_filter_mode_MASK)
#define IRIS_MVPL_HSCALER9_CONTROL_output_size_MASK (0x3FFF0000U)
#define IRIS_MVPL_HSCALER9_CONTROL_output_size_SHIFT (16U)
#define IRIS_MVPL_HSCALER9_CONTROL_output_size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_CONTROL_output_size_SHIFT)) & IRIS_MVPL_HSCALER9_CONTROL_output_size_MASK)

/*! @name VSCALER9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock_MASK)

/*! @name VSCALER9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus_MASK)

/*! @name VSCALER9_STATICCONTROL - Static control settings that must typically be setup once only. */
#define IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn_MASK)

/*! @name VSCALER9_SETUP1 - Phase interpolator setup. */
#define IRIS_MVPL_VSCALER9_SETUP1_scale_factor_MASK (0xFFFFFU)
#define IRIS_MVPL_VSCALER9_SETUP1_scale_factor_SHIFT (0U)
#define IRIS_MVPL_VSCALER9_SETUP1_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP1_scale_factor_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP1_scale_factor_MASK)

/*! @name VSCALER9_SETUP2 - Phase interpolator setup, selected if input and output field polarity is 0. */
#define IRIS_MVPL_VSCALER9_SETUP2_phase_offset_MASK (0x1FFFFFU)
#define IRIS_MVPL_VSCALER9_SETUP2_phase_offset_SHIFT (0U)
#define IRIS_MVPL_VSCALER9_SETUP2_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP2_phase_offset_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP2_phase_offset_MASK)

/*! @name VSCALER9_SETUP3 - Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0. */
#define IRIS_MVPL_VSCALER9_SETUP3_phase_offset1_MASK (0x1FFFFFU)
#define IRIS_MVPL_VSCALER9_SETUP3_phase_offset1_SHIFT (0U)
#define IRIS_MVPL_VSCALER9_SETUP3_phase_offset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP3_phase_offset1_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP3_phase_offset1_MASK)

/*! @name VSCALER9_SETUP4 - Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1. */
#define IRIS_MVPL_VSCALER9_SETUP4_phase_offset2_MASK (0x1FFFFFU)
#define IRIS_MVPL_VSCALER9_SETUP4_phase_offset2_SHIFT (0U)
#define IRIS_MVPL_VSCALER9_SETUP4_phase_offset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP4_phase_offset2_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP4_phase_offset2_MASK)

/*! @name VSCALER9_SETUP5 - Phase interpolator setup, selected if input and output field polarity is 1. */
#define IRIS_MVPL_VSCALER9_SETUP5_phase_offset3_MASK (0x1FFFFFU)
#define IRIS_MVPL_VSCALER9_SETUP5_phase_offset3_SHIFT (0U)
#define IRIS_MVPL_VSCALER9_SETUP5_phase_offset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP5_phase_offset3_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP5_phase_offset3_MASK)

/*! @name VSCALER9_CONTROL - Scaler operation control. */
#define IRIS_MVPL_VSCALER9_CONTROL_mode_MASK     (0x1U)
#define IRIS_MVPL_VSCALER9_CONTROL_mode_SHIFT    (0U)
#define IRIS_MVPL_VSCALER9_CONTROL_mode(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_mode_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_mode_MASK)
#define IRIS_MVPL_VSCALER9_CONTROL_scale_mode_MASK (0x10U)
#define IRIS_MVPL_VSCALER9_CONTROL_scale_mode_SHIFT (4U)
#define IRIS_MVPL_VSCALER9_CONTROL_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_scale_mode_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_scale_mode_MASK)
#define IRIS_MVPL_VSCALER9_CONTROL_filter_mode_MASK (0x100U)
#define IRIS_MVPL_VSCALER9_CONTROL_filter_mode_SHIFT (8U)
#define IRIS_MVPL_VSCALER9_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_filter_mode_MASK)
#define IRIS_MVPL_VSCALER9_CONTROL_field_mode_MASK (0x3000U)
#define IRIS_MVPL_VSCALER9_CONTROL_field_mode_SHIFT (12U)
#define IRIS_MVPL_VSCALER9_CONTROL_field_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_field_mode_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_field_mode_MASK)
#define IRIS_MVPL_VSCALER9_CONTROL_output_size_MASK (0x3FFF0000U)
#define IRIS_MVPL_VSCALER9_CONTROL_output_size_SHIFT (16U)
#define IRIS_MVPL_VSCALER9_CONTROL_output_size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_output_size_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_output_size_MASK)

/*! @name FILTER9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FILTER9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FILTER9_STATICCONTROL - Static control settings that must typically be setup once only. */
#define IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn_MASK)

/*! @name FILTER9_CONTROL - Filter operation main control. */
#define IRIS_MVPL_FILTER9_CONTROL_mode_MASK      (0x1U)
#define IRIS_MVPL_FILTER9_CONTROL_mode_SHIFT     (0U)
#define IRIS_MVPL_FILTER9_CONTROL_mode(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_CONTROL_mode_SHIFT)) & IRIS_MVPL_FILTER9_CONTROL_mode_MASK)
#define IRIS_MVPL_FILTER9_CONTROL_tile_mode_MASK (0x30U)
#define IRIS_MVPL_FILTER9_CONTROL_tile_mode_SHIFT (4U)
#define IRIS_MVPL_FILTER9_CONTROL_tile_mode(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_CONTROL_tile_mode_SHIFT)) & IRIS_MVPL_FILTER9_CONTROL_tile_mode_MASK)
#define IRIS_MVPL_FILTER9_CONTROL_filter_mode_MASK (0xFFFF00U)
#define IRIS_MVPL_FILTER9_CONTROL_filter_mode_SHIFT (8U)
#define IRIS_MVPL_FILTER9_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_FILTER9_CONTROL_filter_mode_MASK)
#define IRIS_MVPL_FILTER9_CONTROL_buffer_format_MASK (0x30000000U)
#define IRIS_MVPL_FILTER9_CONTROL_buffer_format_SHIFT (28U)
#define IRIS_MVPL_FILTER9_CONTROL_buffer_format(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_CONTROL_buffer_format_SHIFT)) & IRIS_MVPL_FILTER9_CONTROL_buffer_format_MASK)

/*! @name FILTER9_FIR_CONTROL - FIR filter operation control. */
#define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select_MASK (0xFU)
#define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select_SHIFT (0U)
#define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select_SHIFT)) & IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select_MASK)
#define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent_MASK (0xF00U)
#define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent_SHIFT (8U)
#define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent_SHIFT)) & IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent_MASK)

/*! @name FILTER9_COEFFICIENTS0 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */
#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0_MASK (0xFFU)
#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0_SHIFT (0U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0_MASK (0xFF00U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0_SHIFT (8U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0_MASK (0xFF0000U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0_SHIFT (16U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0_MASK (0xFF000000U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0_SHIFT (24U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0_MASK)

/*! @name FILTER9_COEFFICIENTS1 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */
#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0_MASK (0xFFU)
#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0_SHIFT (0U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1_MASK (0xFF00U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1_SHIFT (8U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1_MASK (0xFF0000U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1_SHIFT (16U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1_MASK (0xFF000000U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1_SHIFT (24U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1_MASK)

/*! @name FILTER9_COEFFICIENTS2 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */
#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1_MASK (0xFFU)
#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1_SHIFT (0U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1_MASK (0xFF00U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1_SHIFT (8U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2_MASK (0xFF0000U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2_SHIFT (16U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2_MASK (0xFF000000U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2_SHIFT (24U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2_MASK)

/*! @name FILTER9_COEFFICIENTS3 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */
#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2_MASK (0xFFU)
#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2_SHIFT (0U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2_MASK (0xFF00U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2_SHIFT (8U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2_MASK (0xFF0000U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2_SHIFT (16U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3_MASK (0xFF000000U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3_SHIFT (24U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3_MASK)

/*! @name FILTER9_COEFFICIENTS4 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */
#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3_MASK (0xFFU)
#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3_SHIFT (0U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3_MASK (0xFF00U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3_SHIFT (8U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3_MASK (0xFF0000U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3_SHIFT (16U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3_MASK (0xFF000000U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3_SHIFT (24U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3_MASK)

/*! @name FILTER9_COEFFICIENTS5 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */
#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4_MASK (0xFFU)
#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4_SHIFT (0U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4_MASK (0xFF00U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4_SHIFT (8U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4_MASK (0xFF0000U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4_SHIFT (16U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4_MASK)
#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4_MASK (0xFF000000U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4_SHIFT (24U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4_MASK)

/*! @name FILTER9_COEFFICIENTS6 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */
#define IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4_MASK (0xFFU)
#define IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4_SHIFT (0U)
#define IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4_MASK)

/*! @name BLITBLEND9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock_MASK)

/*! @name BLITBLEND9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus_MASK)

/*! @name BLITBLEND9_STATICCONTROL - BlitBlend static control register */
#define IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn_MASK)

/*! @name BLITBLEND9_CONTROL - BlitBlend control register */
#define IRIS_MVPL_BLITBLEND9_CONTROL_Mode_MASK   (0x1U)
#define IRIS_MVPL_BLITBLEND9_CONTROL_Mode_SHIFT  (0U)
#define IRIS_MVPL_BLITBLEND9_CONTROL_Mode(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONTROL_Mode_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONTROL_Mode_MASK)

/*! @name BLITBLEND9_NEUTRALBORDER - Neutral border setup register */
#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode_MASK (0x1U)
#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode_SHIFT (0U)
#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode_SHIFT)) & IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode_MASK)
#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft_MASK (0x700U)
#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft_SHIFT (8U)
#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft_SHIFT)) & IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft_MASK)
#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight_MASK (0x7000U)
#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight_SHIFT (12U)
#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight_SHIFT)) & IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight_MASK)

/*! @name BLITBLEND9_CONSTANTCOLOR - Constant color register */
#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU)
#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U)
#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha_MASK)
#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U)
#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue_SHIFT (8U)
#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue_MASK)
#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U)
#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen_SHIFT (16U)
#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen_MASK)
#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U)
#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed_SHIFT (24U)
#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed_MASK)

/*! @name BLITBLEND9_COLORREDBLENDFUNCTION - Open GL RGB blending factors */
#define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc_MASK (0xFFFFU)
#define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc_SHIFT (0U)
#define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc_MASK)
#define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst_MASK (0xFFFF0000U)
#define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst_SHIFT (16U)
#define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst_MASK)

/*! @name BLITBLEND9_COLORGREENBLENDFUNCTION - Open GL RGB blending factors */
#define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc_MASK (0xFFFFU)
#define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc_SHIFT (0U)
#define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc_MASK)
#define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst_MASK (0xFFFF0000U)
#define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst_SHIFT (16U)
#define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst_MASK)

/*! @name BLITBLEND9_COLORBLUEBLENDFUNCTION - Open GL RGB blending factors */
#define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc_MASK (0xFFFFU)
#define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc_SHIFT (0U)
#define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc_MASK)
#define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst_MASK (0xFFFF0000U)
#define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst_SHIFT (16U)
#define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst_MASK)

/*! @name BLITBLEND9_ALPHABLENDFUNCTION - Open GL alpha blending factors */
#define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc_MASK (0xFFFFU)
#define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc_SHIFT (0U)
#define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc_SHIFT)) & IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc_MASK)
#define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst_MASK (0xFFFF0000U)
#define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst_SHIFT (16U)
#define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst_SHIFT)) & IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst_MASK)

/*! @name BLITBLEND9_BLENDMODE1 - Open GL and Open VG blending modes for colors red and green */
#define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed_MASK (0xFFFFU)
#define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed_SHIFT (0U)
#define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed_SHIFT)) & IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed_MASK)
#define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen_MASK (0xFFFF0000U)
#define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen_SHIFT (16U)
#define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen_SHIFT)) & IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen_MASK)

/*! @name BLITBLEND9_BLENDMODE2 - Open GL and Open VG blending modes for color blue and alpha */
#define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue_MASK (0xFFFFU)
#define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue_SHIFT (0U)
#define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue_SHIFT)) & IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue_MASK)
#define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha_MASK (0xFFFF0000U)
#define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha_SHIFT (16U)
#define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha_SHIFT)) & IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha_MASK)

/*! @name BLITBLEND9_DIRECTSETUP - Direct Control of the BlitBlend Datapath multiplexers, do not change */
#define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug_MASK (0x3FFU)
#define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug_SHIFT (0U)
#define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug_SHIFT)) & IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug_MASK)
#define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug_MASK (0x3FF0000U)
#define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug_SHIFT (16U)
#define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug_SHIFT)) & IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug_MASK)

/*! @name BLITBLEND9_PRIMCONTROLWORD - Value of last received primary control word */
#define IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL_SHIFT (0U)
#define IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL_MASK)

/*! @name BLITBLEND9_SECCONTROLWORD - Value of last received secondary control word */
#define IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL_SHIFT (0U)
#define IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL_MASK)

/*! @name STORE9_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock_MASK)

/*! @name STORE9_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus_MASK)

/*! @name STORE9_STATICCONTROL - Store unit static control register. */
#define IRIS_MVPL_STORE9_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_STORE9_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_STORE9_STATICCONTROL_ShdEn(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_STORE9_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate_MASK (0x100U)
#define IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (8U)
#define IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate_MASK)

/*! @name STORE9_BURSTBUFFERMANAGEMENT - Burst Buffer setup register. */
#define IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)

/*! @name STORE9_RINGBUFSTARTADDR - Ring buffer setup for destination. */
#define IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr_SHIFT (0U)
#define IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr_SHIFT)) & IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr_MASK)

/*! @name STORE9_RINGBUFWRAPADDR - Ring buffer setup for destination. */
#define IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr_SHIFT (0U)
#define IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr_SHIFT)) & IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr_MASK)

/*! @name STORE9_BASEADDRESS - Destination buffer base address. */
#define IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress_SHIFT (0U)
#define IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress_SHIFT)) & IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress_MASK)

/*! @name STORE9_DESTINATIONBUFFERATTRIBUTES - Destination buffer attributes. */
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride_MASK (0x1FFFFU)
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride_SHIFT (0U)
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride_MASK)
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_MASK (0x7F000000U)
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_SHIFT (24U)
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_MASK)

/*! @name STORE9_DESTINATIONBUFFERDIMENSION - Destination buffer dimension. */
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth_MASK (0x3FFFU)
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth_SHIFT (0U)
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth_MASK)
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount_MASK (0x3FFF0000U)
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount_SHIFT (16U)
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount_MASK)

/*! @name STORE9_FRAMEOFFSET - Offset between destination frame and buffer. */
#define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset_MASK (0x7FFFU)
#define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset_SHIFT (0U)
#define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset_SHIFT)) & IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset_MASK)
#define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset_MASK (0x7FFF0000U)
#define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset_SHIFT (16U)
#define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset_SHIFT)) & IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset_MASK)

/*! @name STORE9_COLORCOMPONENTBITS - Color component size of destination buffer */
#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK (0xFU)
#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT (0U)
#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK)
#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue_MASK (0xF00U)
#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT (8U)
#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue_MASK)
#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen_MASK (0xF0000U)
#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT (16U)
#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen_MASK)
#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed_MASK (0xF000000U)
#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT (24U)
#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed_MASK)

/*! @name STORE9_COLORCOMPONENTSHIFT - Color component offset of destination buffer. */
#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK (0x1FU)
#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT (0U)
#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK)
#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK (0x1F00U)
#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT (8U)
#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK)
#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK (0x1F0000U)
#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT (16U)
#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK)
#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK (0x1F000000U)
#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT (24U)
#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK)

/*! @name STORE9_CONTROL - Store unit dynamic control register */
#define IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable_MASK (0x1U)
#define IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable_SHIFT (0U)
#define IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable_MASK)
#define IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable_MASK (0x2U)
#define IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable_SHIFT (1U)
#define IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable_MASK)
#define IRIS_MVPL_STORE9_CONTROL_DitherOffset_MASK (0xF0U)
#define IRIS_MVPL_STORE9_CONTROL_DitherOffset_SHIFT (4U)
#define IRIS_MVPL_STORE9_CONTROL_DitherOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_DitherOffset_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_DitherOffset_MASK)
#define IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable_MASK (0x1000U)
#define IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable_SHIFT (12U)
#define IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable_MASK)
#define IRIS_MVPL_STORE9_CONTROL_YUVConversionMode_MASK (0x30000U)
#define IRIS_MVPL_STORE9_CONTROL_YUVConversionMode_SHIFT (16U)
#define IRIS_MVPL_STORE9_CONTROL_YUVConversionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_YUVConversionMode_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_YUVConversionMode_MASK)
#define IRIS_MVPL_STORE9_CONTROL_RasterMode_MASK (0xC0000U)
#define IRIS_MVPL_STORE9_CONTROL_RasterMode_SHIFT (18U)
#define IRIS_MVPL_STORE9_CONTROL_RasterMode(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_RasterMode_MASK)
#define IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode_MASK (0x300000U)
#define IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode_SHIFT (20U)
#define IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode_MASK)

/*! @name STORE9_ENCODECONTROL - Control options for RLAD compression. */
#define IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode_MASK (0x1U)
#define IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode_SHIFT (0U)
#define IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode_MASK)
#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed_MASK (0xF0000U)
#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed_SHIFT (16U)
#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed_MASK)
#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen_MASK (0xF00000U)
#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen_SHIFT (20U)
#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen_MASK)
#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue_MASK (0xF000000U)
#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue_SHIFT (24U)
#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue_MASK)
#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha_MASK (0xF0000000U)
#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha_SHIFT (28U)
#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha_MASK)

/*! @name STORE9_DESTINATIONBUFFERLENGTH - Destination buffer length for compressed data. */
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax_SHIFT (0U)
#define IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax_MASK)

/*! @name STORE9_START - Store unit start register */
#define IRIS_MVPL_STORE9_START_Start_MASK        (0x1U)
#define IRIS_MVPL_STORE9_START_Start_SHIFT       (0U)
#define IRIS_MVPL_STORE9_START_Start(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_START_Start_SHIFT)) & IRIS_MVPL_STORE9_START_Start_MASK)

/*! @name STORE9_ENCODERSTATUS - Status information of the RLAD encoder. */
#define IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords_SHIFT (0U)
#define IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords_SHIFT)) & IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords_MASK)
#define IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall_MASK (0x80000000U)
#define IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall_SHIFT (31U)
#define IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall_SHIFT)) & IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall_MASK)

/*! @name STORE9_WRITEADDRESS - Ring buffer synchronization. */
#define IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress_SHIFT (0U)
#define IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress_SHIFT)) & IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress_MASK)

/*! @name STORE9_FRAMEPROPERTIES - Ring buffer synchronization. */
#define IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId_MASK (0x1U)
#define IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId_SHIFT (0U)
#define IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId_SHIFT)) & IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId_MASK)

/*! @name STORE9_BURSTBUFFERPROPERTIES - Burst Buffer Property register */
#define IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength_SHIFT (8U)
#define IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength_SHIFT)) & IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength_MASK)

/*! @name STORE9_LASTCONTROLWORD - Shows the last control word received */
#define IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL_SHIFT (0U)
#define IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL_MASK)

/*! @name STORE9_PERFCOUNTER - Performance counter result */
#define IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult_SHIFT (0U)
#define IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult_SHIFT)) & IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult_MASK)

/*! @name STORE9_STATUS - Shows status information */
#define IRIS_MVPL_STORE9_STATUS_StatusBusy_MASK  (0x1U)
#define IRIS_MVPL_STORE9_STATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_STORE9_STATUS_StatusBusy(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_STORE9_STATUS_StatusBusy_MASK)
#define IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_STORE9_STATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_STORE9_STATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_STORE9_STATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_StatusRequest_SHIFT)) & IRIS_MVPL_STORE9_STATUS_StatusRequest_MASK)
#define IRIS_MVPL_STORE9_STATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_STORE9_STATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_STORE9_STATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_StatusComplete_SHIFT)) & IRIS_MVPL_STORE9_STATUS_StatusComplete_MASK)
#define IRIS_MVPL_STORE9_STATUS_PixelbusError_MASK (0x100U)
#define IRIS_MVPL_STORE9_STATUS_PixelbusError_SHIFT (8U)
#define IRIS_MVPL_STORE9_STATUS_PixelbusError(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_PixelbusError_SHIFT)) & IRIS_MVPL_STORE9_STATUS_PixelbusError_MASK)
#define IRIS_MVPL_STORE9_STATUS_EncoderOverflow_MASK (0x10000U)
#define IRIS_MVPL_STORE9_STATUS_EncoderOverflow_SHIFT (16U)
#define IRIS_MVPL_STORE9_STATUS_EncoderOverflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_EncoderOverflow_SHIFT)) & IRIS_MVPL_STORE9_STATUS_EncoderOverflow_MASK)
#define IRIS_MVPL_STORE9_STATUS_EncoderStallPixel_MASK (0x20000U)
#define IRIS_MVPL_STORE9_STATUS_EncoderStallPixel_SHIFT (17U)
#define IRIS_MVPL_STORE9_STATUS_EncoderStallPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_EncoderStallPixel_SHIFT)) & IRIS_MVPL_STORE9_STATUS_EncoderStallPixel_MASK)

/*! @name CONSTFRAME0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock_MASK)

/*! @name CONSTFRAME0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus_MASK)

/*! @name CONSTFRAME0_STATICCONTROL - ConstFrame unit static control register */
#define IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn_MASK)

/*! @name CONSTFRAME0_FRAMEDIMENSIONS - Output frame dimensions. */
#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name CONSTFRAME0_CONSTANTCOLOR - Color of output frame. */
#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU)
#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha_MASK)
#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U)
#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue_SHIFT (8U)
#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue_MASK)
#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U)
#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen_SHIFT (16U)
#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen_MASK)
#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U)
#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed_SHIFT (24U)
#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed_MASK)

/*! @name CONSTFRAME0_CONTROLTRIGGER - ConstFrame unit trigger register */
#define IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name CONSTFRAME0_START - ConstFrame unit start register */
#define IRIS_MVPL_CONSTFRAME0_START_Start_MASK   (0x1U)
#define IRIS_MVPL_CONSTFRAME0_START_Start_SHIFT  (0U)
#define IRIS_MVPL_CONSTFRAME0_START_Start(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_START_Start_SHIFT)) & IRIS_MVPL_CONSTFRAME0_START_Start_MASK)

/*! @name CONSTFRAME0_STATUS - Shows status information */
#define IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy_MASK)
#define IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus_MASK (0x2U)
#define IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus_SHIFT (1U)
#define IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus_MASK)

/*! @name EXTDST0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock_MASK)

/*! @name EXTDST0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus_MASK)

/*! @name EXTDST0_STATICCONTROL - External Destination static control register */
#define IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE_MASK (0x100U)
#define IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE_SHIFT (8U)
#define IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE_SHIFT)) & IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE_MASK)
#define IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode_MASK (0x1000U)
#define IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode_SHIFT (12U)
#define IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode_SHIFT)) & IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode_MASK)

/*! @name EXTDST0_CONTROL - External Destination shadowed control register */
#define IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable_MASK (0x1U)
#define IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable_SHIFT (0U)
#define IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable_SHIFT)) & IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable_MASK)

/*! @name EXTDST0_SOFTWAREKICK - External Destination software kick */
#define IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK_MASK (0x1U)
#define IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK_SHIFT (0U)
#define IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK_SHIFT)) & IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK_MASK)

/*! @name EXTDST0_STATUS - External Destination Unit current status */
#define IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS_MASK (0x1U)
#define IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS_SHIFT (0U)
#define IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS_SHIFT)) & IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS_MASK)

/*! @name EXTDST0_CONTROLWORD - Value of last received control word */
#define IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL_SHIFT (0U)
#define IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL_SHIFT)) & IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL_MASK)

/*! @name EXTDST0_CURPIXELCNT - pixel count of currently running frame */
#define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL_MASK (0xFFFFU)
#define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL_SHIFT (0U)
#define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL_SHIFT)) & IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL_MASK)
#define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL_MASK (0xFFFF0000U)
#define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL_SHIFT (16U)
#define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL_SHIFT)) & IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL_MASK)

/*! @name EXTDST0_LASTPIXELCNT - pixel count between last two control words */
#define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL_MASK (0xFFFFU)
#define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL_SHIFT (0U)
#define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL_SHIFT)) & IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL_MASK)
#define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL_MASK (0xFFFF0000U)
#define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL_SHIFT (16U)
#define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL_SHIFT)) & IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL_MASK)

/*! @name EXTDST0_PERFCOUNTER - Performance counter result */
#define IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult_SHIFT (0U)
#define IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult_SHIFT)) & IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult_MASK)

/*! @name CONSTFRAME4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock_MASK)

/*! @name CONSTFRAME4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus_MASK)

/*! @name CONSTFRAME4_STATICCONTROL - ConstFrame unit static control register */
#define IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn_MASK)

/*! @name CONSTFRAME4_FRAMEDIMENSIONS - Output frame dimensions. */
#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name CONSTFRAME4_CONSTANTCOLOR - Color of output frame. */
#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU)
#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha_MASK)
#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U)
#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue_SHIFT (8U)
#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue_MASK)
#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U)
#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen_SHIFT (16U)
#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen_MASK)
#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U)
#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed_SHIFT (24U)
#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed_MASK)

/*! @name CONSTFRAME4_CONTROLTRIGGER - ConstFrame unit trigger register */
#define IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name CONSTFRAME4_START - ConstFrame unit start register */
#define IRIS_MVPL_CONSTFRAME4_START_Start_MASK   (0x1U)
#define IRIS_MVPL_CONSTFRAME4_START_Start_SHIFT  (0U)
#define IRIS_MVPL_CONSTFRAME4_START_Start(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_START_Start_SHIFT)) & IRIS_MVPL_CONSTFRAME4_START_Start_MASK)

/*! @name CONSTFRAME4_STATUS - Shows status information */
#define IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy_MASK)
#define IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus_MASK (0x2U)
#define IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus_SHIFT (1U)
#define IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus_MASK)

/*! @name EXTDST4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_EXTDST4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTDST4_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_EXTDST4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST4_LOCKUNLOCK_LockUnlock_MASK)

/*! @name EXTDST4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_EXTDST4_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_EXTDST4_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_EXTDST4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST4_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_EXTDST4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_EXTDST4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_EXTDST4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST4_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_EXTDST4_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_EXTDST4_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_EXTDST4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST4_LOCKSTATUS_FreezeStatus_MASK)

/*! @name EXTDST4_STATICCONTROL - External Destination static control register */
#define IRIS_MVPL_EXTDST4_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_EXTDST4_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_EXTDST4_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST4_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_EXTDST4_STATICCONTROL_KICK_MODE_MASK (0x100U)
#define IRIS_MVPL_EXTDST4_STATICCONTROL_KICK_MODE_SHIFT (8U)
#define IRIS_MVPL_EXTDST4_STATICCONTROL_KICK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_STATICCONTROL_KICK_MODE_SHIFT)) & IRIS_MVPL_EXTDST4_STATICCONTROL_KICK_MODE_MASK)
#define IRIS_MVPL_EXTDST4_STATICCONTROL_PerfCountMode_MASK (0x1000U)
#define IRIS_MVPL_EXTDST4_STATICCONTROL_PerfCountMode_SHIFT (12U)
#define IRIS_MVPL_EXTDST4_STATICCONTROL_PerfCountMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_STATICCONTROL_PerfCountMode_SHIFT)) & IRIS_MVPL_EXTDST4_STATICCONTROL_PerfCountMode_MASK)

/*! @name EXTDST4_CONTROL - External Destination shadowed control register */
#define IRIS_MVPL_EXTDST4_CONTROL_GammaApplyEnable_MASK (0x1U)
#define IRIS_MVPL_EXTDST4_CONTROL_GammaApplyEnable_SHIFT (0U)
#define IRIS_MVPL_EXTDST4_CONTROL_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_CONTROL_GammaApplyEnable_SHIFT)) & IRIS_MVPL_EXTDST4_CONTROL_GammaApplyEnable_MASK)

/*! @name EXTDST4_SOFTWAREKICK - External Destination software kick */
#define IRIS_MVPL_EXTDST4_SOFTWAREKICK_KICK_MASK (0x1U)
#define IRIS_MVPL_EXTDST4_SOFTWAREKICK_KICK_SHIFT (0U)
#define IRIS_MVPL_EXTDST4_SOFTWAREKICK_KICK(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_SOFTWAREKICK_KICK_SHIFT)) & IRIS_MVPL_EXTDST4_SOFTWAREKICK_KICK_MASK)

/*! @name EXTDST4_STATUS - External Destination Unit current status */
#define IRIS_MVPL_EXTDST4_STATUS_CNT_ERR_STS_MASK (0x1U)
#define IRIS_MVPL_EXTDST4_STATUS_CNT_ERR_STS_SHIFT (0U)
#define IRIS_MVPL_EXTDST4_STATUS_CNT_ERR_STS(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_STATUS_CNT_ERR_STS_SHIFT)) & IRIS_MVPL_EXTDST4_STATUS_CNT_ERR_STS_MASK)

/*! @name EXTDST4_CONTROLWORD - Value of last received control word */
#define IRIS_MVPL_EXTDST4_CONTROLWORD_CW_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTDST4_CONTROLWORD_CW_VAL_SHIFT (0U)
#define IRIS_MVPL_EXTDST4_CONTROLWORD_CW_VAL(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_CONTROLWORD_CW_VAL_SHIFT)) & IRIS_MVPL_EXTDST4_CONTROLWORD_CW_VAL_MASK)

/*! @name EXTDST4_CURPIXELCNT - pixel count of currently running frame */
#define IRIS_MVPL_EXTDST4_CURPIXELCNT_C_XVAL_MASK (0xFFFFU)
#define IRIS_MVPL_EXTDST4_CURPIXELCNT_C_XVAL_SHIFT (0U)
#define IRIS_MVPL_EXTDST4_CURPIXELCNT_C_XVAL(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_CURPIXELCNT_C_XVAL_SHIFT)) & IRIS_MVPL_EXTDST4_CURPIXELCNT_C_XVAL_MASK)
#define IRIS_MVPL_EXTDST4_CURPIXELCNT_C_YVAL_MASK (0xFFFF0000U)
#define IRIS_MVPL_EXTDST4_CURPIXELCNT_C_YVAL_SHIFT (16U)
#define IRIS_MVPL_EXTDST4_CURPIXELCNT_C_YVAL(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_CURPIXELCNT_C_YVAL_SHIFT)) & IRIS_MVPL_EXTDST4_CURPIXELCNT_C_YVAL_MASK)

/*! @name EXTDST4_LASTPIXELCNT - pixel count between last two control words */
#define IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_XVAL_MASK (0xFFFFU)
#define IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_XVAL_SHIFT (0U)
#define IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_XVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_XVAL_SHIFT)) & IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_XVAL_MASK)
#define IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_YVAL_MASK (0xFFFF0000U)
#define IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_YVAL_SHIFT (16U)
#define IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_YVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_YVAL_SHIFT)) & IRIS_MVPL_EXTDST4_LASTPIXELCNT_L_YVAL_MASK)

/*! @name EXTDST4_PERFCOUNTER - Performance counter result */
#define IRIS_MVPL_EXTDST4_PERFCOUNTER_PerfResult_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTDST4_PERFCOUNTER_PerfResult_SHIFT (0U)
#define IRIS_MVPL_EXTDST4_PERFCOUNTER_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_PERFCOUNTER_PerfResult_SHIFT)) & IRIS_MVPL_EXTDST4_PERFCOUNTER_PerfResult_MASK)

/*! @name CONSTFRAME1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_CONSTFRAME1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_CONSTFRAME1_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME1_LOCKUNLOCK_LockUnlock_MASK)

/*! @name CONSTFRAME1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME1_LOCKSTATUS_FreezeStatus_MASK)

/*! @name CONSTFRAME1_STATICCONTROL - ConstFrame unit static control register */
#define IRIS_MVPL_CONSTFRAME1_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME1_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_CONSTFRAME1_STATICCONTROL_ShdEn_MASK)

/*! @name CONSTFRAME1_FRAMEDIMENSIONS - Output frame dimensions. */
#define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_CONSTFRAME1_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name CONSTFRAME1_CONSTANTCOLOR - Color of output frame. */
#define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU)
#define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantAlpha_MASK)
#define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U)
#define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantBlue_SHIFT (8U)
#define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantBlue_MASK)
#define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U)
#define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantGreen_SHIFT (16U)
#define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantGreen_MASK)
#define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U)
#define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantRed_SHIFT (24U)
#define IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_CONSTFRAME1_CONSTANTCOLOR_ConstantRed_MASK)

/*! @name CONSTFRAME1_CONTROLTRIGGER - ConstFrame unit trigger register */
#define IRIS_MVPL_CONSTFRAME1_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME1_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME1_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_CONSTFRAME1_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name CONSTFRAME1_START - ConstFrame unit start register */
#define IRIS_MVPL_CONSTFRAME1_START_Start_MASK   (0x1U)
#define IRIS_MVPL_CONSTFRAME1_START_Start_SHIFT  (0U)
#define IRIS_MVPL_CONSTFRAME1_START_Start(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_START_Start_SHIFT)) & IRIS_MVPL_CONSTFRAME1_START_Start_MASK)

/*! @name CONSTFRAME1_STATUS - Shows status information */
#define IRIS_MVPL_CONSTFRAME1_STATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME1_STATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME1_STATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_CONSTFRAME1_STATUS_StatusBusy_MASK)
#define IRIS_MVPL_CONSTFRAME1_STATUS_ShadowStatus_MASK (0x2U)
#define IRIS_MVPL_CONSTFRAME1_STATUS_ShadowStatus_SHIFT (1U)
#define IRIS_MVPL_CONSTFRAME1_STATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME1_STATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME1_STATUS_ShadowStatus_MASK)

/*! @name EXTDST1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_EXTDST1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTDST1_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_EXTDST1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST1_LOCKUNLOCK_LockUnlock_MASK)

/*! @name EXTDST1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_EXTDST1_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_EXTDST1_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_EXTDST1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST1_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_EXTDST1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_EXTDST1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_EXTDST1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST1_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_EXTDST1_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_EXTDST1_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_EXTDST1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST1_LOCKSTATUS_FreezeStatus_MASK)

/*! @name EXTDST1_STATICCONTROL - External Destination static control register */
#define IRIS_MVPL_EXTDST1_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_EXTDST1_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_EXTDST1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST1_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_EXTDST1_STATICCONTROL_KICK_MODE_MASK (0x100U)
#define IRIS_MVPL_EXTDST1_STATICCONTROL_KICK_MODE_SHIFT (8U)
#define IRIS_MVPL_EXTDST1_STATICCONTROL_KICK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATICCONTROL_KICK_MODE_SHIFT)) & IRIS_MVPL_EXTDST1_STATICCONTROL_KICK_MODE_MASK)
#define IRIS_MVPL_EXTDST1_STATICCONTROL_PerfCountMode_MASK (0x1000U)
#define IRIS_MVPL_EXTDST1_STATICCONTROL_PerfCountMode_SHIFT (12U)
#define IRIS_MVPL_EXTDST1_STATICCONTROL_PerfCountMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATICCONTROL_PerfCountMode_SHIFT)) & IRIS_MVPL_EXTDST1_STATICCONTROL_PerfCountMode_MASK)

/*! @name EXTDST1_CONTROL - External Destination shadowed control register */
#define IRIS_MVPL_EXTDST1_CONTROL_GammaApplyEnable_MASK (0x1U)
#define IRIS_MVPL_EXTDST1_CONTROL_GammaApplyEnable_SHIFT (0U)
#define IRIS_MVPL_EXTDST1_CONTROL_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_CONTROL_GammaApplyEnable_SHIFT)) & IRIS_MVPL_EXTDST1_CONTROL_GammaApplyEnable_MASK)

/*! @name EXTDST1_SOFTWAREKICK - External Destination software kick */
#define IRIS_MVPL_EXTDST1_SOFTWAREKICK_KICK_MASK (0x1U)
#define IRIS_MVPL_EXTDST1_SOFTWAREKICK_KICK_SHIFT (0U)
#define IRIS_MVPL_EXTDST1_SOFTWAREKICK_KICK(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_SOFTWAREKICK_KICK_SHIFT)) & IRIS_MVPL_EXTDST1_SOFTWAREKICK_KICK_MASK)

/*! @name EXTDST1_STATUS - External Destination Unit current status */
#define IRIS_MVPL_EXTDST1_STATUS_CNT_ERR_STS_MASK (0x1U)
#define IRIS_MVPL_EXTDST1_STATUS_CNT_ERR_STS_SHIFT (0U)
#define IRIS_MVPL_EXTDST1_STATUS_CNT_ERR_STS(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATUS_CNT_ERR_STS_SHIFT)) & IRIS_MVPL_EXTDST1_STATUS_CNT_ERR_STS_MASK)

/*! @name EXTDST1_CONTROLWORD - Value of last received control word */
#define IRIS_MVPL_EXTDST1_CONTROLWORD_CW_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTDST1_CONTROLWORD_CW_VAL_SHIFT (0U)
#define IRIS_MVPL_EXTDST1_CONTROLWORD_CW_VAL(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_CONTROLWORD_CW_VAL_SHIFT)) & IRIS_MVPL_EXTDST1_CONTROLWORD_CW_VAL_MASK)

/*! @name EXTDST1_CURPIXELCNT - pixel count of currently running frame */
#define IRIS_MVPL_EXTDST1_CURPIXELCNT_C_XVAL_MASK (0xFFFFU)
#define IRIS_MVPL_EXTDST1_CURPIXELCNT_C_XVAL_SHIFT (0U)
#define IRIS_MVPL_EXTDST1_CURPIXELCNT_C_XVAL(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_CURPIXELCNT_C_XVAL_SHIFT)) & IRIS_MVPL_EXTDST1_CURPIXELCNT_C_XVAL_MASK)
#define IRIS_MVPL_EXTDST1_CURPIXELCNT_C_YVAL_MASK (0xFFFF0000U)
#define IRIS_MVPL_EXTDST1_CURPIXELCNT_C_YVAL_SHIFT (16U)
#define IRIS_MVPL_EXTDST1_CURPIXELCNT_C_YVAL(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_CURPIXELCNT_C_YVAL_SHIFT)) & IRIS_MVPL_EXTDST1_CURPIXELCNT_C_YVAL_MASK)

/*! @name EXTDST1_LASTPIXELCNT - pixel count between last two control words */
#define IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_XVAL_MASK (0xFFFFU)
#define IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_XVAL_SHIFT (0U)
#define IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_XVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_XVAL_SHIFT)) & IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_XVAL_MASK)
#define IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_YVAL_MASK (0xFFFF0000U)
#define IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_YVAL_SHIFT (16U)
#define IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_YVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_YVAL_SHIFT)) & IRIS_MVPL_EXTDST1_LASTPIXELCNT_L_YVAL_MASK)

/*! @name EXTDST1_PERFCOUNTER - Performance counter result */
#define IRIS_MVPL_EXTDST1_PERFCOUNTER_PerfResult_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTDST1_PERFCOUNTER_PerfResult_SHIFT (0U)
#define IRIS_MVPL_EXTDST1_PERFCOUNTER_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_PERFCOUNTER_PerfResult_SHIFT)) & IRIS_MVPL_EXTDST1_PERFCOUNTER_PerfResult_MASK)

/*! @name CONSTFRAME5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_CONSTFRAME5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_CONSTFRAME5_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME5_LOCKUNLOCK_LockUnlock_MASK)

/*! @name CONSTFRAME5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME5_LOCKSTATUS_FreezeStatus_MASK)

/*! @name CONSTFRAME5_STATICCONTROL - ConstFrame unit static control register */
#define IRIS_MVPL_CONSTFRAME5_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME5_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME5_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_CONSTFRAME5_STATICCONTROL_ShdEn_MASK)

/*! @name CONSTFRAME5_FRAMEDIMENSIONS - Output frame dimensions. */
#define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_CONSTFRAME5_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name CONSTFRAME5_CONSTANTCOLOR - Color of output frame. */
#define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU)
#define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantAlpha_MASK)
#define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U)
#define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantBlue_SHIFT (8U)
#define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantBlue_MASK)
#define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U)
#define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantGreen_SHIFT (16U)
#define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantGreen_MASK)
#define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U)
#define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantRed_SHIFT (24U)
#define IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_CONSTFRAME5_CONSTANTCOLOR_ConstantRed_MASK)

/*! @name CONSTFRAME5_CONTROLTRIGGER - ConstFrame unit trigger register */
#define IRIS_MVPL_CONSTFRAME5_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME5_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME5_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_CONSTFRAME5_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name CONSTFRAME5_START - ConstFrame unit start register */
#define IRIS_MVPL_CONSTFRAME5_START_Start_MASK   (0x1U)
#define IRIS_MVPL_CONSTFRAME5_START_Start_SHIFT  (0U)
#define IRIS_MVPL_CONSTFRAME5_START_Start(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_START_Start_SHIFT)) & IRIS_MVPL_CONSTFRAME5_START_Start_MASK)

/*! @name CONSTFRAME5_STATUS - Shows status information */
#define IRIS_MVPL_CONSTFRAME5_STATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_CONSTFRAME5_STATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_CONSTFRAME5_STATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_CONSTFRAME5_STATUS_StatusBusy_MASK)
#define IRIS_MVPL_CONSTFRAME5_STATUS_ShadowStatus_MASK (0x2U)
#define IRIS_MVPL_CONSTFRAME5_STATUS_ShadowStatus_SHIFT (1U)
#define IRIS_MVPL_CONSTFRAME5_STATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME5_STATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME5_STATUS_ShadowStatus_MASK)

/*! @name EXTDST5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_EXTDST5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTDST5_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_EXTDST5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST5_LOCKUNLOCK_LockUnlock_MASK)

/*! @name EXTDST5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_EXTDST5_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_EXTDST5_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_EXTDST5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST5_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_EXTDST5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_EXTDST5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_EXTDST5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST5_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_EXTDST5_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_EXTDST5_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_EXTDST5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST5_LOCKSTATUS_FreezeStatus_MASK)

/*! @name EXTDST5_STATICCONTROL - External Destination static control register */
#define IRIS_MVPL_EXTDST5_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_EXTDST5_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_EXTDST5_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST5_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_EXTDST5_STATICCONTROL_KICK_MODE_MASK (0x100U)
#define IRIS_MVPL_EXTDST5_STATICCONTROL_KICK_MODE_SHIFT (8U)
#define IRIS_MVPL_EXTDST5_STATICCONTROL_KICK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATICCONTROL_KICK_MODE_SHIFT)) & IRIS_MVPL_EXTDST5_STATICCONTROL_KICK_MODE_MASK)
#define IRIS_MVPL_EXTDST5_STATICCONTROL_PerfCountMode_MASK (0x1000U)
#define IRIS_MVPL_EXTDST5_STATICCONTROL_PerfCountMode_SHIFT (12U)
#define IRIS_MVPL_EXTDST5_STATICCONTROL_PerfCountMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATICCONTROL_PerfCountMode_SHIFT)) & IRIS_MVPL_EXTDST5_STATICCONTROL_PerfCountMode_MASK)

/*! @name EXTDST5_CONTROL - External Destination shadowed control register */
#define IRIS_MVPL_EXTDST5_CONTROL_GammaApplyEnable_MASK (0x1U)
#define IRIS_MVPL_EXTDST5_CONTROL_GammaApplyEnable_SHIFT (0U)
#define IRIS_MVPL_EXTDST5_CONTROL_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_CONTROL_GammaApplyEnable_SHIFT)) & IRIS_MVPL_EXTDST5_CONTROL_GammaApplyEnable_MASK)

/*! @name EXTDST5_SOFTWAREKICK - External Destination software kick */
#define IRIS_MVPL_EXTDST5_SOFTWAREKICK_KICK_MASK (0x1U)
#define IRIS_MVPL_EXTDST5_SOFTWAREKICK_KICK_SHIFT (0U)
#define IRIS_MVPL_EXTDST5_SOFTWAREKICK_KICK(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_SOFTWAREKICK_KICK_SHIFT)) & IRIS_MVPL_EXTDST5_SOFTWAREKICK_KICK_MASK)

/*! @name EXTDST5_STATUS - External Destination Unit current status */
#define IRIS_MVPL_EXTDST5_STATUS_CNT_ERR_STS_MASK (0x1U)
#define IRIS_MVPL_EXTDST5_STATUS_CNT_ERR_STS_SHIFT (0U)
#define IRIS_MVPL_EXTDST5_STATUS_CNT_ERR_STS(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATUS_CNT_ERR_STS_SHIFT)) & IRIS_MVPL_EXTDST5_STATUS_CNT_ERR_STS_MASK)

/*! @name EXTDST5_CONTROLWORD - Value of last received control word */
#define IRIS_MVPL_EXTDST5_CONTROLWORD_CW_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTDST5_CONTROLWORD_CW_VAL_SHIFT (0U)
#define IRIS_MVPL_EXTDST5_CONTROLWORD_CW_VAL(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_CONTROLWORD_CW_VAL_SHIFT)) & IRIS_MVPL_EXTDST5_CONTROLWORD_CW_VAL_MASK)

/*! @name EXTDST5_CURPIXELCNT - pixel count of currently running frame */
#define IRIS_MVPL_EXTDST5_CURPIXELCNT_C_XVAL_MASK (0xFFFFU)
#define IRIS_MVPL_EXTDST5_CURPIXELCNT_C_XVAL_SHIFT (0U)
#define IRIS_MVPL_EXTDST5_CURPIXELCNT_C_XVAL(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_CURPIXELCNT_C_XVAL_SHIFT)) & IRIS_MVPL_EXTDST5_CURPIXELCNT_C_XVAL_MASK)
#define IRIS_MVPL_EXTDST5_CURPIXELCNT_C_YVAL_MASK (0xFFFF0000U)
#define IRIS_MVPL_EXTDST5_CURPIXELCNT_C_YVAL_SHIFT (16U)
#define IRIS_MVPL_EXTDST5_CURPIXELCNT_C_YVAL(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_CURPIXELCNT_C_YVAL_SHIFT)) & IRIS_MVPL_EXTDST5_CURPIXELCNT_C_YVAL_MASK)

/*! @name EXTDST5_LASTPIXELCNT - pixel count between last two control words */
#define IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_XVAL_MASK (0xFFFFU)
#define IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_XVAL_SHIFT (0U)
#define IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_XVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_XVAL_SHIFT)) & IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_XVAL_MASK)
#define IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_YVAL_MASK (0xFFFF0000U)
#define IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_YVAL_SHIFT (16U)
#define IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_YVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_YVAL_SHIFT)) & IRIS_MVPL_EXTDST5_LASTPIXELCNT_L_YVAL_MASK)

/*! @name EXTDST5_PERFCOUNTER - Performance counter result */
#define IRIS_MVPL_EXTDST5_PERFCOUNTER_PerfResult_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTDST5_PERFCOUNTER_PerfResult_SHIFT (0U)
#define IRIS_MVPL_EXTDST5_PERFCOUNTER_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_PERFCOUNTER_PerfResult_SHIFT)) & IRIS_MVPL_EXTDST5_PERFCOUNTER_PerfResult_MASK)

/*! @name EXTSRC4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_EXTSRC4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTSRC4_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_EXTSRC4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_EXTSRC4_LOCKUNLOCK_LockUnlock_MASK)

/*! @name EXTSRC4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_EXTSRC4_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_EXTSRC4_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_EXTSRC4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_EXTSRC4_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_EXTSRC4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_EXTSRC4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_EXTSRC4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTSRC4_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_EXTSRC4_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_EXTSRC4_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_EXTSRC4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTSRC4_LOCKSTATUS_FreezeStatus_MASK)

/*! @name EXTSRC4_STATICCONTROL - ExtSrc static control register */
#define IRIS_MVPL_EXTSRC4_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_EXTSRC4_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_EXTSRC4_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_EXTSRC4_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_EXTSRC4_STATICCONTROL_StartSel_MASK (0x100U)
#define IRIS_MVPL_EXTSRC4_STATICCONTROL_StartSel_SHIFT (8U)
#define IRIS_MVPL_EXTSRC4_STATICCONTROL_StartSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_STATICCONTROL_StartSel_SHIFT)) & IRIS_MVPL_EXTSRC4_STATICCONTROL_StartSel_MASK)

/*! @name EXTSRC4_CLIPWINDOWOFFSET - Clip window offset, to generate a clipping of the frame. It has to be within the input frame. */
#define IRIS_MVPL_EXTSRC4_CLIPWINDOWOFFSET_ClipWindowXOffset_MASK (0x3FFFU)
#define IRIS_MVPL_EXTSRC4_CLIPWINDOWOFFSET_ClipWindowXOffset_SHIFT (0U)
#define IRIS_MVPL_EXTSRC4_CLIPWINDOWOFFSET_ClipWindowXOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CLIPWINDOWOFFSET_ClipWindowXOffset_SHIFT)) & IRIS_MVPL_EXTSRC4_CLIPWINDOWOFFSET_ClipWindowXOffset_MASK)
#define IRIS_MVPL_EXTSRC4_CLIPWINDOWOFFSET_ClipWindowYOffset_MASK (0x3FFF0000U)
#define IRIS_MVPL_EXTSRC4_CLIPWINDOWOFFSET_ClipWindowYOffset_SHIFT (16U)
#define IRIS_MVPL_EXTSRC4_CLIPWINDOWOFFSET_ClipWindowYOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CLIPWINDOWOFFSET_ClipWindowYOffset_SHIFT)) & IRIS_MVPL_EXTSRC4_CLIPWINDOWOFFSET_ClipWindowYOffset_MASK)

/*! @name EXTSRC4_CLIPWINDOWDIMENSION - Define the clip window dimension. If the clip window feature is enabled this dimension is used for the new frame dimension. Note that the clip window has to be smaller or equal to the original frame dimensions. The new frame has to be within the active area of the original frame. */
#define IRIS_MVPL_EXTSRC4_CLIPWINDOWDIMENSION_ClipWindowWidth_MASK (0x3FFFU)
#define IRIS_MVPL_EXTSRC4_CLIPWINDOWDIMENSION_ClipWindowWidth_SHIFT (0U)
#define IRIS_MVPL_EXTSRC4_CLIPWINDOWDIMENSION_ClipWindowWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CLIPWINDOWDIMENSION_ClipWindowWidth_SHIFT)) & IRIS_MVPL_EXTSRC4_CLIPWINDOWDIMENSION_ClipWindowWidth_MASK)
#define IRIS_MVPL_EXTSRC4_CLIPWINDOWDIMENSION_ClipWindowHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_EXTSRC4_CLIPWINDOWDIMENSION_ClipWindowHeight_SHIFT (16U)
#define IRIS_MVPL_EXTSRC4_CLIPWINDOWDIMENSION_ClipWindowHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CLIPWINDOWDIMENSION_ClipWindowHeight_SHIFT)) & IRIS_MVPL_EXTSRC4_CLIPWINDOWDIMENSION_ClipWindowHeight_MASK)

/*! @name EXTSRC4_COLORCOMPONENTBITS - Color component size of raw input data. Please note that the width must be equal or lower than the output width. */
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK (0xFU)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT (0U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT)) & IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsBlue_MASK (0xF00U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT (8U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT)) & IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsBlue_MASK)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsGreen_MASK (0xF0000U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT (16U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT)) & IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsGreen_MASK)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsRed_MASK (0xF000000U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT (24U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT)) & IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ComponentBitsRed_MASK)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ITUFormat_MASK (0x80000000U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ITUFormat_SHIFT (31U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ITUFormat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ITUFormat_SHIFT)) & IRIS_MVPL_EXTSRC4_COLORCOMPONENTBITS_ITUFormat_MASK)

/*! @name EXTSRC4_COLORCOMPONENTSHIFT - Color component offset of raw input data. */
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK (0x3FU)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT (0U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT)) & IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK (0x3F00U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT (8U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT)) & IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK (0x3F0000U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT (16U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT)) & IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK (0x3F000000U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT (24U)
#define IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT)) & IRIS_MVPL_EXTSRC4_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK)

/*! @name EXTSRC4_CONSTANTCOLOR - Constant color register */
#define IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU)
#define IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U)
#define IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantAlpha_MASK)
#define IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U)
#define IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantBlue_SHIFT (8U)
#define IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantBlue_MASK)
#define IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U)
#define IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantGreen_SHIFT (16U)
#define IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantGreen_MASK)
#define IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U)
#define IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantRed_SHIFT (24U)
#define IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_EXTSRC4_CONSTANTCOLOR_ConstantRed_MASK)

/*! @name EXTSRC4_CONTROL - Common control settings. */
#define IRIS_MVPL_EXTSRC4_CONTROL_ClipWindowEnable_MASK (0x1U)
#define IRIS_MVPL_EXTSRC4_CONTROL_ClipWindowEnable_SHIFT (0U)
#define IRIS_MVPL_EXTSRC4_CONTROL_ClipWindowEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONTROL_ClipWindowEnable_SHIFT)) & IRIS_MVPL_EXTSRC4_CONTROL_ClipWindowEnable_MASK)
#define IRIS_MVPL_EXTSRC4_CONTROL_RasterMode_MASK (0x10U)
#define IRIS_MVPL_EXTSRC4_CONTROL_RasterMode_SHIFT (4U)
#define IRIS_MVPL_EXTSRC4_CONTROL_RasterMode(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_EXTSRC4_CONTROL_RasterMode_MASK)
#define IRIS_MVPL_EXTSRC4_CONTROL_YUV422UpsamplingMode_MASK (0x20U)
#define IRIS_MVPL_EXTSRC4_CONTROL_YUV422UpsamplingMode_SHIFT (5U)
#define IRIS_MVPL_EXTSRC4_CONTROL_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONTROL_YUV422UpsamplingMode_SHIFT)) & IRIS_MVPL_EXTSRC4_CONTROL_YUV422UpsamplingMode_MASK)
#define IRIS_MVPL_EXTSRC4_CONTROL_YUVConversionMode_MASK (0xC0U)
#define IRIS_MVPL_EXTSRC4_CONTROL_YUVConversionMode_SHIFT (6U)
#define IRIS_MVPL_EXTSRC4_CONTROL_YUVConversionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONTROL_YUVConversionMode_SHIFT)) & IRIS_MVPL_EXTSRC4_CONTROL_YUVConversionMode_MASK)
#define IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaSrcEnable_MASK (0x100U)
#define IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaSrcEnable_SHIFT (8U)
#define IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaSrcEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaSrcEnable_SHIFT)) & IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaSrcEnable_MASK)
#define IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaConstEnable_MASK (0x200U)
#define IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaConstEnable_SHIFT (9U)
#define IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaConstEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaConstEnable_SHIFT)) & IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaConstEnable_MASK)
#define IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaTransEnable_MASK (0x400U)
#define IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaTransEnable_SHIFT (10U)
#define IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaTransEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaTransEnable_SHIFT)) & IRIS_MVPL_EXTSRC4_CONTROL_RGBAlphaTransEnable_MASK)
#define IRIS_MVPL_EXTSRC4_CONTROL_PremulConstRGB_MASK (0x800U)
#define IRIS_MVPL_EXTSRC4_CONTROL_PremulConstRGB_SHIFT (11U)
#define IRIS_MVPL_EXTSRC4_CONTROL_PremulConstRGB(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONTROL_PremulConstRGB_SHIFT)) & IRIS_MVPL_EXTSRC4_CONTROL_PremulConstRGB_MASK)
#define IRIS_MVPL_EXTSRC4_CONTROL_AlphaSrcEnable_MASK (0x1000U)
#define IRIS_MVPL_EXTSRC4_CONTROL_AlphaSrcEnable_SHIFT (12U)
#define IRIS_MVPL_EXTSRC4_CONTROL_AlphaSrcEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONTROL_AlphaSrcEnable_SHIFT)) & IRIS_MVPL_EXTSRC4_CONTROL_AlphaSrcEnable_MASK)
#define IRIS_MVPL_EXTSRC4_CONTROL_AlphaConstEnable_MASK (0x2000U)
#define IRIS_MVPL_EXTSRC4_CONTROL_AlphaConstEnable_SHIFT (13U)
#define IRIS_MVPL_EXTSRC4_CONTROL_AlphaConstEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONTROL_AlphaConstEnable_SHIFT)) & IRIS_MVPL_EXTSRC4_CONTROL_AlphaConstEnable_MASK)
#define IRIS_MVPL_EXTSRC4_CONTROL_AlphaTransEnable_MASK (0x4000U)
#define IRIS_MVPL_EXTSRC4_CONTROL_AlphaTransEnable_SHIFT (14U)
#define IRIS_MVPL_EXTSRC4_CONTROL_AlphaTransEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONTROL_AlphaTransEnable_SHIFT)) & IRIS_MVPL_EXTSRC4_CONTROL_AlphaTransEnable_MASK)
#define IRIS_MVPL_EXTSRC4_CONTROL_GammaRemoveEnable_MASK (0x10000U)
#define IRIS_MVPL_EXTSRC4_CONTROL_GammaRemoveEnable_SHIFT (16U)
#define IRIS_MVPL_EXTSRC4_CONTROL_GammaRemoveEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONTROL_GammaRemoveEnable_SHIFT)) & IRIS_MVPL_EXTSRC4_CONTROL_GammaRemoveEnable_MASK)

/*! @name EXTSRC4_CONTROLTRIGGER - ExtSrc unit trigger token generation */
#define IRIS_MVPL_EXTSRC4_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_EXTSRC4_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_EXTSRC4_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_EXTSRC4_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name EXTSRC4_START - ExtSrc unit start register */
#define IRIS_MVPL_EXTSRC4_START_Start_MASK       (0x1U)
#define IRIS_MVPL_EXTSRC4_START_Start_SHIFT      (0U)
#define IRIS_MVPL_EXTSRC4_START_Start(x)         (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_START_Start_SHIFT)) & IRIS_MVPL_EXTSRC4_START_Start_MASK)

/*! @name EXTSRC4_LASTCOMMANDWORD - Subset of last input command word with the following mapping: val[31:0]={data[37:22], data[19:12], data[9:2]} */
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_FrameWidth_SHIFT)) & IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_FrameWidth_MASK)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_fld_MASK (0x4000U)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_fld_SHIFT (14U)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_fld(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_fld_SHIFT)) & IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_fld_MASK)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_rld_MASK (0x8000U)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_rld_SHIFT (15U)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_rld(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_rld_SHIFT)) & IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_rld_MASK)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_FrameHeight_SHIFT)) & IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_FrameHeight_MASK)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_ex_MASK (0x40000000U)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_ex_SHIFT (30U)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_ex(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_ex_SHIFT)) & IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_ex_MASK)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_nf_MASK (0x80000000U)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_nf_SHIFT (31U)
#define IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_nf(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_nf_SHIFT)) & IRIS_MVPL_EXTSRC4_LASTCOMMANDWORD_nf_MASK)

/*! @name EXTSRC4_STATUS - Shows status information */
#define IRIS_MVPL_EXTSRC4_STATUS_InputValid_MASK (0x1U)
#define IRIS_MVPL_EXTSRC4_STATUS_InputValid_SHIFT (0U)
#define IRIS_MVPL_EXTSRC4_STATUS_InputValid(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC4_STATUS_InputValid_SHIFT)) & IRIS_MVPL_EXTSRC4_STATUS_InputValid_MASK)

/*! @name STORE4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_STORE4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE4_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_STORE4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_STORE4_LOCKUNLOCK_LockUnlock_MASK)

/*! @name STORE4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_STORE4_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_STORE4_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_STORE4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_STORE4_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_STORE4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_STORE4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_STORE4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_STORE4_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_STORE4_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_STORE4_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_STORE4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_STORE4_LOCKSTATUS_FreezeStatus_MASK)

/*! @name STORE4_STATICCONTROL - Store unit static control register. */
#define IRIS_MVPL_STORE4_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_STORE4_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_STORE4_STATICCONTROL_ShdEn(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_STORE4_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_STORE4_STATICCONTROL_BaseAddressAutoUpdate_MASK (0x100U)
#define IRIS_MVPL_STORE4_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (8U)
#define IRIS_MVPL_STORE4_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_STORE4_STATICCONTROL_BaseAddressAutoUpdate_MASK)

/*! @name STORE4_BURSTBUFFERMANAGEMENT - Burst Buffer setup register. */
#define IRIS_MVPL_STORE4_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_STORE4_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_STORE4_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_STORE4_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)

/*! @name STORE4_RINGBUFSTARTADDR - Ring buffer setup for destination. */
#define IRIS_MVPL_STORE4_RINGBUFSTARTADDR_RingBufStartAddr_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE4_RINGBUFSTARTADDR_RingBufStartAddr_SHIFT (0U)
#define IRIS_MVPL_STORE4_RINGBUFSTARTADDR_RingBufStartAddr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_RINGBUFSTARTADDR_RingBufStartAddr_SHIFT)) & IRIS_MVPL_STORE4_RINGBUFSTARTADDR_RingBufStartAddr_MASK)

/*! @name STORE4_RINGBUFWRAPADDR - Ring buffer setup for destination. */
#define IRIS_MVPL_STORE4_RINGBUFWRAPADDR_RingBufWrapAddr_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE4_RINGBUFWRAPADDR_RingBufWrapAddr_SHIFT (0U)
#define IRIS_MVPL_STORE4_RINGBUFWRAPADDR_RingBufWrapAddr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_RINGBUFWRAPADDR_RingBufWrapAddr_SHIFT)) & IRIS_MVPL_STORE4_RINGBUFWRAPADDR_RingBufWrapAddr_MASK)

/*! @name STORE4_BASEADDRESS - Destination buffer base address. */
#define IRIS_MVPL_STORE4_BASEADDRESS_BaseAddress_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE4_BASEADDRESS_BaseAddress_SHIFT (0U)
#define IRIS_MVPL_STORE4_BASEADDRESS_BaseAddress(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_BASEADDRESS_BaseAddress_SHIFT)) & IRIS_MVPL_STORE4_BASEADDRESS_BaseAddress_MASK)

/*! @name STORE4_DESTINATIONBUFFERATTRIBUTES - Destination buffer attributes. */
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERATTRIBUTES_Stride_MASK (0x1FFFFU)
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERATTRIBUTES_Stride_SHIFT (0U)
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERATTRIBUTES_Stride(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_DESTINATIONBUFFERATTRIBUTES_Stride_SHIFT)) & IRIS_MVPL_STORE4_DESTINATIONBUFFERATTRIBUTES_Stride_MASK)
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_MASK (0x7F000000U)
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_SHIFT (24U)
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_SHIFT)) & IRIS_MVPL_STORE4_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_MASK)

/*! @name STORE4_DESTINATIONBUFFERDIMENSION - Destination buffer dimension. */
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERDIMENSION_LineWidth_MASK (0x3FFFU)
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERDIMENSION_LineWidth_SHIFT (0U)
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERDIMENSION_LineWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_DESTINATIONBUFFERDIMENSION_LineWidth_SHIFT)) & IRIS_MVPL_STORE4_DESTINATIONBUFFERDIMENSION_LineWidth_MASK)
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERDIMENSION_LineCount_MASK (0x3FFF0000U)
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERDIMENSION_LineCount_SHIFT (16U)
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERDIMENSION_LineCount(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_DESTINATIONBUFFERDIMENSION_LineCount_SHIFT)) & IRIS_MVPL_STORE4_DESTINATIONBUFFERDIMENSION_LineCount_MASK)

/*! @name STORE4_FRAMEOFFSET - Offset between destination frame and buffer. */
#define IRIS_MVPL_STORE4_FRAMEOFFSET_FrameXOffset_MASK (0x7FFFU)
#define IRIS_MVPL_STORE4_FRAMEOFFSET_FrameXOffset_SHIFT (0U)
#define IRIS_MVPL_STORE4_FRAMEOFFSET_FrameXOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_FRAMEOFFSET_FrameXOffset_SHIFT)) & IRIS_MVPL_STORE4_FRAMEOFFSET_FrameXOffset_MASK)
#define IRIS_MVPL_STORE4_FRAMEOFFSET_FrameYOffset_MASK (0x7FFF0000U)
#define IRIS_MVPL_STORE4_FRAMEOFFSET_FrameYOffset_SHIFT (16U)
#define IRIS_MVPL_STORE4_FRAMEOFFSET_FrameYOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_FRAMEOFFSET_FrameYOffset_SHIFT)) & IRIS_MVPL_STORE4_FRAMEOFFSET_FrameYOffset_MASK)

/*! @name STORE4_COLORCOMPONENTBITS - Color component size of destination buffer */
#define IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK (0xFU)
#define IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT (0U)
#define IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT)) & IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK)
#define IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsBlue_MASK (0xF00U)
#define IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT (8U)
#define IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT)) & IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsBlue_MASK)
#define IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsGreen_MASK (0xF0000U)
#define IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT (16U)
#define IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT)) & IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsGreen_MASK)
#define IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsRed_MASK (0xF000000U)
#define IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT (24U)
#define IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT)) & IRIS_MVPL_STORE4_COLORCOMPONENTBITS_ComponentBitsRed_MASK)

/*! @name STORE4_COLORCOMPONENTSHIFT - Color component offset of destination buffer. */
#define IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK (0x1FU)
#define IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT (0U)
#define IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT)) & IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK)
#define IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK (0x1F00U)
#define IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT (8U)
#define IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT)) & IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK)
#define IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK (0x1F0000U)
#define IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT (16U)
#define IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT)) & IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK)
#define IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK (0x1F000000U)
#define IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT (24U)
#define IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT)) & IRIS_MVPL_STORE4_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK)

/*! @name STORE4_CONTROL - Store unit dynamic control register */
#define IRIS_MVPL_STORE4_CONTROL_ColorDitherEnable_MASK (0x1U)
#define IRIS_MVPL_STORE4_CONTROL_ColorDitherEnable_SHIFT (0U)
#define IRIS_MVPL_STORE4_CONTROL_ColorDitherEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_CONTROL_ColorDitherEnable_SHIFT)) & IRIS_MVPL_STORE4_CONTROL_ColorDitherEnable_MASK)
#define IRIS_MVPL_STORE4_CONTROL_AlphaDitherEnable_MASK (0x2U)
#define IRIS_MVPL_STORE4_CONTROL_AlphaDitherEnable_SHIFT (1U)
#define IRIS_MVPL_STORE4_CONTROL_AlphaDitherEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_CONTROL_AlphaDitherEnable_SHIFT)) & IRIS_MVPL_STORE4_CONTROL_AlphaDitherEnable_MASK)
#define IRIS_MVPL_STORE4_CONTROL_DitherOffset_MASK (0xF0U)
#define IRIS_MVPL_STORE4_CONTROL_DitherOffset_SHIFT (4U)
#define IRIS_MVPL_STORE4_CONTROL_DitherOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_CONTROL_DitherOffset_SHIFT)) & IRIS_MVPL_STORE4_CONTROL_DitherOffset_MASK)
#define IRIS_MVPL_STORE4_CONTROL_GammaApplyEnable_MASK (0x1000U)
#define IRIS_MVPL_STORE4_CONTROL_GammaApplyEnable_SHIFT (12U)
#define IRIS_MVPL_STORE4_CONTROL_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_CONTROL_GammaApplyEnable_SHIFT)) & IRIS_MVPL_STORE4_CONTROL_GammaApplyEnable_MASK)
#define IRIS_MVPL_STORE4_CONTROL_YUVConversionMode_MASK (0x30000U)
#define IRIS_MVPL_STORE4_CONTROL_YUVConversionMode_SHIFT (16U)
#define IRIS_MVPL_STORE4_CONTROL_YUVConversionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_CONTROL_YUVConversionMode_SHIFT)) & IRIS_MVPL_STORE4_CONTROL_YUVConversionMode_MASK)
#define IRIS_MVPL_STORE4_CONTROL_RasterMode_MASK (0xC0000U)
#define IRIS_MVPL_STORE4_CONTROL_RasterMode_SHIFT (18U)
#define IRIS_MVPL_STORE4_CONTROL_RasterMode(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_STORE4_CONTROL_RasterMode_MASK)
#define IRIS_MVPL_STORE4_CONTROL_YUV422DownsamplingMode_MASK (0x300000U)
#define IRIS_MVPL_STORE4_CONTROL_YUV422DownsamplingMode_SHIFT (20U)
#define IRIS_MVPL_STORE4_CONTROL_YUV422DownsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_CONTROL_YUV422DownsamplingMode_SHIFT)) & IRIS_MVPL_STORE4_CONTROL_YUV422DownsamplingMode_MASK)

/*! @name STORE4_ENCODECONTROL - Control options for RLAD compression. */
#define IRIS_MVPL_STORE4_ENCODECONTROL_CompressionMode_MASK (0x1U)
#define IRIS_MVPL_STORE4_ENCODECONTROL_CompressionMode_SHIFT (0U)
#define IRIS_MVPL_STORE4_ENCODECONTROL_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_ENCODECONTROL_CompressionMode_SHIFT)) & IRIS_MVPL_STORE4_ENCODECONTROL_CompressionMode_MASK)
#define IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsRed_MASK (0xF0000U)
#define IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsRed_SHIFT (16U)
#define IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsRed_SHIFT)) & IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsRed_MASK)
#define IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsGreen_MASK (0xF00000U)
#define IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsGreen_SHIFT (20U)
#define IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsGreen_SHIFT)) & IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsGreen_MASK)
#define IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsBlue_MASK (0xF000000U)
#define IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsBlue_SHIFT (24U)
#define IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsBlue_SHIFT)) & IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsBlue_MASK)
#define IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsAlpha_MASK (0xF0000000U)
#define IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsAlpha_SHIFT (28U)
#define IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsAlpha_SHIFT)) & IRIS_MVPL_STORE4_ENCODECONTROL_RLADCompBitsAlpha_MASK)

/*! @name STORE4_DESTINATIONBUFFERLENGTH - Destination buffer length for compressed data. */
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERLENGTH_RLEWordsMax_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERLENGTH_RLEWordsMax_SHIFT (0U)
#define IRIS_MVPL_STORE4_DESTINATIONBUFFERLENGTH_RLEWordsMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_DESTINATIONBUFFERLENGTH_RLEWordsMax_SHIFT)) & IRIS_MVPL_STORE4_DESTINATIONBUFFERLENGTH_RLEWordsMax_MASK)

/*! @name STORE4_START - Store unit start register */
#define IRIS_MVPL_STORE4_START_Start_MASK        (0x1U)
#define IRIS_MVPL_STORE4_START_Start_SHIFT       (0U)
#define IRIS_MVPL_STORE4_START_Start(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_START_Start_SHIFT)) & IRIS_MVPL_STORE4_START_Start_MASK)

/*! @name STORE4_ENCODERSTATUS - Status information of the RLAD encoder. */
#define IRIS_MVPL_STORE4_ENCODERSTATUS_RLEWords_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_STORE4_ENCODERSTATUS_RLEWords_SHIFT (0U)
#define IRIS_MVPL_STORE4_ENCODERSTATUS_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_ENCODERSTATUS_RLEWords_SHIFT)) & IRIS_MVPL_STORE4_ENCODERSTATUS_RLEWords_MASK)
#define IRIS_MVPL_STORE4_ENCODERSTATUS_BufferTooSmall_MASK (0x80000000U)
#define IRIS_MVPL_STORE4_ENCODERSTATUS_BufferTooSmall_SHIFT (31U)
#define IRIS_MVPL_STORE4_ENCODERSTATUS_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_ENCODERSTATUS_BufferTooSmall_SHIFT)) & IRIS_MVPL_STORE4_ENCODERSTATUS_BufferTooSmall_MASK)

/*! @name STORE4_WRITEADDRESS - Ring buffer synchronization. */
#define IRIS_MVPL_STORE4_WRITEADDRESS_WriteAddress_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE4_WRITEADDRESS_WriteAddress_SHIFT (0U)
#define IRIS_MVPL_STORE4_WRITEADDRESS_WriteAddress(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_WRITEADDRESS_WriteAddress_SHIFT)) & IRIS_MVPL_STORE4_WRITEADDRESS_WriteAddress_MASK)

/*! @name STORE4_FRAMEPROPERTIES - Ring buffer synchronization. */
#define IRIS_MVPL_STORE4_FRAMEPROPERTIES_FieldId_MASK (0x1U)
#define IRIS_MVPL_STORE4_FRAMEPROPERTIES_FieldId_SHIFT (0U)
#define IRIS_MVPL_STORE4_FRAMEPROPERTIES_FieldId(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_FRAMEPROPERTIES_FieldId_SHIFT)) & IRIS_MVPL_STORE4_FRAMEPROPERTIES_FieldId_MASK)

/*! @name STORE4_BURSTBUFFERPROPERTIES - Burst Buffer Property register */
#define IRIS_MVPL_STORE4_BURSTBUFFERPROPERTIES_MaxBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_STORE4_BURSTBUFFERPROPERTIES_MaxBurstLength_SHIFT (8U)
#define IRIS_MVPL_STORE4_BURSTBUFFERPROPERTIES_MaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_BURSTBUFFERPROPERTIES_MaxBurstLength_SHIFT)) & IRIS_MVPL_STORE4_BURSTBUFFERPROPERTIES_MaxBurstLength_MASK)

/*! @name STORE4_LASTCONTROLWORD - Shows the last control word received */
#define IRIS_MVPL_STORE4_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE4_LASTCONTROLWORD_L_VAL_SHIFT (0U)
#define IRIS_MVPL_STORE4_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_STORE4_LASTCONTROLWORD_L_VAL_MASK)

/*! @name STORE4_PERFCOUNTER - Performance counter result */
#define IRIS_MVPL_STORE4_PERFCOUNTER_PerfResult_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE4_PERFCOUNTER_PerfResult_SHIFT (0U)
#define IRIS_MVPL_STORE4_PERFCOUNTER_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_PERFCOUNTER_PerfResult_SHIFT)) & IRIS_MVPL_STORE4_PERFCOUNTER_PerfResult_MASK)

/*! @name STORE4_STATUS - Shows status information */
#define IRIS_MVPL_STORE4_STATUS_StatusBusy_MASK  (0x1U)
#define IRIS_MVPL_STORE4_STATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_STORE4_STATUS_StatusBusy(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_STORE4_STATUS_StatusBusy_MASK)
#define IRIS_MVPL_STORE4_STATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_STORE4_STATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_STORE4_STATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_STATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_STORE4_STATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_STORE4_STATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_STORE4_STATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_STORE4_STATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_STATUS_StatusRequest_SHIFT)) & IRIS_MVPL_STORE4_STATUS_StatusRequest_MASK)
#define IRIS_MVPL_STORE4_STATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_STORE4_STATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_STORE4_STATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_STATUS_StatusComplete_SHIFT)) & IRIS_MVPL_STORE4_STATUS_StatusComplete_MASK)
#define IRIS_MVPL_STORE4_STATUS_PixelbusError_MASK (0x100U)
#define IRIS_MVPL_STORE4_STATUS_PixelbusError_SHIFT (8U)
#define IRIS_MVPL_STORE4_STATUS_PixelbusError(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_STATUS_PixelbusError_SHIFT)) & IRIS_MVPL_STORE4_STATUS_PixelbusError_MASK)
#define IRIS_MVPL_STORE4_STATUS_EncoderOverflow_MASK (0x10000U)
#define IRIS_MVPL_STORE4_STATUS_EncoderOverflow_SHIFT (16U)
#define IRIS_MVPL_STORE4_STATUS_EncoderOverflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_STATUS_EncoderOverflow_SHIFT)) & IRIS_MVPL_STORE4_STATUS_EncoderOverflow_MASK)
#define IRIS_MVPL_STORE4_STATUS_EncoderStallPixel_MASK (0x20000U)
#define IRIS_MVPL_STORE4_STATUS_EncoderStallPixel_SHIFT (17U)
#define IRIS_MVPL_STORE4_STATUS_EncoderStallPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE4_STATUS_EncoderStallPixel_SHIFT)) & IRIS_MVPL_STORE4_STATUS_EncoderStallPixel_MASK)

/*! @name EXTSRC5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_EXTSRC5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTSRC5_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_EXTSRC5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_EXTSRC5_LOCKUNLOCK_LockUnlock_MASK)

/*! @name EXTSRC5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_EXTSRC5_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_EXTSRC5_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_EXTSRC5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_EXTSRC5_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_EXTSRC5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_EXTSRC5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_EXTSRC5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTSRC5_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_EXTSRC5_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_EXTSRC5_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_EXTSRC5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTSRC5_LOCKSTATUS_FreezeStatus_MASK)

/*! @name EXTSRC5_STATICCONTROL - ExtSrc static control register */
#define IRIS_MVPL_EXTSRC5_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_EXTSRC5_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_EXTSRC5_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_EXTSRC5_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_EXTSRC5_STATICCONTROL_StartSel_MASK (0x100U)
#define IRIS_MVPL_EXTSRC5_STATICCONTROL_StartSel_SHIFT (8U)
#define IRIS_MVPL_EXTSRC5_STATICCONTROL_StartSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_STATICCONTROL_StartSel_SHIFT)) & IRIS_MVPL_EXTSRC5_STATICCONTROL_StartSel_MASK)

/*! @name EXTSRC5_CLIPWINDOWOFFSET - Clip window offset, to generate a clipping of the frame. It has to be within the input frame. */
#define IRIS_MVPL_EXTSRC5_CLIPWINDOWOFFSET_ClipWindowXOffset_MASK (0x3FFFU)
#define IRIS_MVPL_EXTSRC5_CLIPWINDOWOFFSET_ClipWindowXOffset_SHIFT (0U)
#define IRIS_MVPL_EXTSRC5_CLIPWINDOWOFFSET_ClipWindowXOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CLIPWINDOWOFFSET_ClipWindowXOffset_SHIFT)) & IRIS_MVPL_EXTSRC5_CLIPWINDOWOFFSET_ClipWindowXOffset_MASK)
#define IRIS_MVPL_EXTSRC5_CLIPWINDOWOFFSET_ClipWindowYOffset_MASK (0x3FFF0000U)
#define IRIS_MVPL_EXTSRC5_CLIPWINDOWOFFSET_ClipWindowYOffset_SHIFT (16U)
#define IRIS_MVPL_EXTSRC5_CLIPWINDOWOFFSET_ClipWindowYOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CLIPWINDOWOFFSET_ClipWindowYOffset_SHIFT)) & IRIS_MVPL_EXTSRC5_CLIPWINDOWOFFSET_ClipWindowYOffset_MASK)

/*! @name EXTSRC5_CLIPWINDOWDIMENSION - Define the clip window dimension. If the clip window feature is enabled this dimension is used for the new frame dimension. Note that the clip window has to be smaller or equal to the original frame dimensions. The new frame has to be within the active area of the original frame. */
#define IRIS_MVPL_EXTSRC5_CLIPWINDOWDIMENSION_ClipWindowWidth_MASK (0x3FFFU)
#define IRIS_MVPL_EXTSRC5_CLIPWINDOWDIMENSION_ClipWindowWidth_SHIFT (0U)
#define IRIS_MVPL_EXTSRC5_CLIPWINDOWDIMENSION_ClipWindowWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CLIPWINDOWDIMENSION_ClipWindowWidth_SHIFT)) & IRIS_MVPL_EXTSRC5_CLIPWINDOWDIMENSION_ClipWindowWidth_MASK)
#define IRIS_MVPL_EXTSRC5_CLIPWINDOWDIMENSION_ClipWindowHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_EXTSRC5_CLIPWINDOWDIMENSION_ClipWindowHeight_SHIFT (16U)
#define IRIS_MVPL_EXTSRC5_CLIPWINDOWDIMENSION_ClipWindowHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CLIPWINDOWDIMENSION_ClipWindowHeight_SHIFT)) & IRIS_MVPL_EXTSRC5_CLIPWINDOWDIMENSION_ClipWindowHeight_MASK)

/*! @name EXTSRC5_COLORCOMPONENTBITS - Color component size of raw input data. Please note that the width must be equal or lower than the output width. */
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK (0xFU)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT (0U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT)) & IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsBlue_MASK (0xF00U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT (8U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT)) & IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsBlue_MASK)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsGreen_MASK (0xF0000U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT (16U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT)) & IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsGreen_MASK)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsRed_MASK (0xF000000U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT (24U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT)) & IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ComponentBitsRed_MASK)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ITUFormat_MASK (0x80000000U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ITUFormat_SHIFT (31U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ITUFormat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ITUFormat_SHIFT)) & IRIS_MVPL_EXTSRC5_COLORCOMPONENTBITS_ITUFormat_MASK)

/*! @name EXTSRC5_COLORCOMPONENTSHIFT - Color component offset of raw input data. */
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK (0x3FU)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT (0U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT)) & IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK (0x3F00U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT (8U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT)) & IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK (0x3F0000U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT (16U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT)) & IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK (0x3F000000U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT (24U)
#define IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT)) & IRIS_MVPL_EXTSRC5_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK)

/*! @name EXTSRC5_CONSTANTCOLOR - Constant color register */
#define IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU)
#define IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U)
#define IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantAlpha_MASK)
#define IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U)
#define IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantBlue_SHIFT (8U)
#define IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantBlue_MASK)
#define IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U)
#define IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantGreen_SHIFT (16U)
#define IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantGreen_MASK)
#define IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U)
#define IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantRed_SHIFT (24U)
#define IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_EXTSRC5_CONSTANTCOLOR_ConstantRed_MASK)

/*! @name EXTSRC5_CONTROL - Common control settings. */
#define IRIS_MVPL_EXTSRC5_CONTROL_ClipWindowEnable_MASK (0x1U)
#define IRIS_MVPL_EXTSRC5_CONTROL_ClipWindowEnable_SHIFT (0U)
#define IRIS_MVPL_EXTSRC5_CONTROL_ClipWindowEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONTROL_ClipWindowEnable_SHIFT)) & IRIS_MVPL_EXTSRC5_CONTROL_ClipWindowEnable_MASK)
#define IRIS_MVPL_EXTSRC5_CONTROL_RasterMode_MASK (0x10U)
#define IRIS_MVPL_EXTSRC5_CONTROL_RasterMode_SHIFT (4U)
#define IRIS_MVPL_EXTSRC5_CONTROL_RasterMode(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_EXTSRC5_CONTROL_RasterMode_MASK)
#define IRIS_MVPL_EXTSRC5_CONTROL_YUV422UpsamplingMode_MASK (0x20U)
#define IRIS_MVPL_EXTSRC5_CONTROL_YUV422UpsamplingMode_SHIFT (5U)
#define IRIS_MVPL_EXTSRC5_CONTROL_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONTROL_YUV422UpsamplingMode_SHIFT)) & IRIS_MVPL_EXTSRC5_CONTROL_YUV422UpsamplingMode_MASK)
#define IRIS_MVPL_EXTSRC5_CONTROL_YUVConversionMode_MASK (0xC0U)
#define IRIS_MVPL_EXTSRC5_CONTROL_YUVConversionMode_SHIFT (6U)
#define IRIS_MVPL_EXTSRC5_CONTROL_YUVConversionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONTROL_YUVConversionMode_SHIFT)) & IRIS_MVPL_EXTSRC5_CONTROL_YUVConversionMode_MASK)
#define IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaSrcEnable_MASK (0x100U)
#define IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaSrcEnable_SHIFT (8U)
#define IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaSrcEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaSrcEnable_SHIFT)) & IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaSrcEnable_MASK)
#define IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaConstEnable_MASK (0x200U)
#define IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaConstEnable_SHIFT (9U)
#define IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaConstEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaConstEnable_SHIFT)) & IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaConstEnable_MASK)
#define IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaTransEnable_MASK (0x400U)
#define IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaTransEnable_SHIFT (10U)
#define IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaTransEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaTransEnable_SHIFT)) & IRIS_MVPL_EXTSRC5_CONTROL_RGBAlphaTransEnable_MASK)
#define IRIS_MVPL_EXTSRC5_CONTROL_PremulConstRGB_MASK (0x800U)
#define IRIS_MVPL_EXTSRC5_CONTROL_PremulConstRGB_SHIFT (11U)
#define IRIS_MVPL_EXTSRC5_CONTROL_PremulConstRGB(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONTROL_PremulConstRGB_SHIFT)) & IRIS_MVPL_EXTSRC5_CONTROL_PremulConstRGB_MASK)
#define IRIS_MVPL_EXTSRC5_CONTROL_AlphaSrcEnable_MASK (0x1000U)
#define IRIS_MVPL_EXTSRC5_CONTROL_AlphaSrcEnable_SHIFT (12U)
#define IRIS_MVPL_EXTSRC5_CONTROL_AlphaSrcEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONTROL_AlphaSrcEnable_SHIFT)) & IRIS_MVPL_EXTSRC5_CONTROL_AlphaSrcEnable_MASK)
#define IRIS_MVPL_EXTSRC5_CONTROL_AlphaConstEnable_MASK (0x2000U)
#define IRIS_MVPL_EXTSRC5_CONTROL_AlphaConstEnable_SHIFT (13U)
#define IRIS_MVPL_EXTSRC5_CONTROL_AlphaConstEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONTROL_AlphaConstEnable_SHIFT)) & IRIS_MVPL_EXTSRC5_CONTROL_AlphaConstEnable_MASK)
#define IRIS_MVPL_EXTSRC5_CONTROL_AlphaTransEnable_MASK (0x4000U)
#define IRIS_MVPL_EXTSRC5_CONTROL_AlphaTransEnable_SHIFT (14U)
#define IRIS_MVPL_EXTSRC5_CONTROL_AlphaTransEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONTROL_AlphaTransEnable_SHIFT)) & IRIS_MVPL_EXTSRC5_CONTROL_AlphaTransEnable_MASK)
#define IRIS_MVPL_EXTSRC5_CONTROL_GammaRemoveEnable_MASK (0x10000U)
#define IRIS_MVPL_EXTSRC5_CONTROL_GammaRemoveEnable_SHIFT (16U)
#define IRIS_MVPL_EXTSRC5_CONTROL_GammaRemoveEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONTROL_GammaRemoveEnable_SHIFT)) & IRIS_MVPL_EXTSRC5_CONTROL_GammaRemoveEnable_MASK)

/*! @name EXTSRC5_CONTROLTRIGGER - ExtSrc unit trigger token generation */
#define IRIS_MVPL_EXTSRC5_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_EXTSRC5_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_EXTSRC5_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_EXTSRC5_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name EXTSRC5_START - ExtSrc unit start register */
#define IRIS_MVPL_EXTSRC5_START_Start_MASK       (0x1U)
#define IRIS_MVPL_EXTSRC5_START_Start_SHIFT      (0U)
#define IRIS_MVPL_EXTSRC5_START_Start(x)         (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_START_Start_SHIFT)) & IRIS_MVPL_EXTSRC5_START_Start_MASK)

/*! @name EXTSRC5_LASTCOMMANDWORD - Subset of last input command word with the following mapping: val[31:0]={data[37:22], data[19:12], data[9:2]} */
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_FrameWidth_SHIFT)) & IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_FrameWidth_MASK)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_fld_MASK (0x4000U)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_fld_SHIFT (14U)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_fld(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_fld_SHIFT)) & IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_fld_MASK)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_rld_MASK (0x8000U)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_rld_SHIFT (15U)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_rld(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_rld_SHIFT)) & IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_rld_MASK)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_FrameHeight_SHIFT)) & IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_FrameHeight_MASK)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_ex_MASK (0x40000000U)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_ex_SHIFT (30U)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_ex(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_ex_SHIFT)) & IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_ex_MASK)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_nf_MASK (0x80000000U)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_nf_SHIFT (31U)
#define IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_nf(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_nf_SHIFT)) & IRIS_MVPL_EXTSRC5_LASTCOMMANDWORD_nf_MASK)

/*! @name EXTSRC5_STATUS - Shows status information */
#define IRIS_MVPL_EXTSRC5_STATUS_InputValid_MASK (0x1U)
#define IRIS_MVPL_EXTSRC5_STATUS_InputValid_SHIFT (0U)
#define IRIS_MVPL_EXTSRC5_STATUS_InputValid(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC5_STATUS_InputValid_SHIFT)) & IRIS_MVPL_EXTSRC5_STATUS_InputValid_MASK)

/*! @name STORE5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_STORE5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE5_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_STORE5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_STORE5_LOCKUNLOCK_LockUnlock_MASK)

/*! @name STORE5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_STORE5_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_STORE5_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_STORE5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_STORE5_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_STORE5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_STORE5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_STORE5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_STORE5_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_STORE5_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_STORE5_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_STORE5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_STORE5_LOCKSTATUS_FreezeStatus_MASK)

/*! @name STORE5_STATICCONTROL - Store unit static control register. */
#define IRIS_MVPL_STORE5_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_STORE5_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_STORE5_STATICCONTROL_ShdEn(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_STORE5_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_STORE5_STATICCONTROL_BaseAddressAutoUpdate_MASK (0x100U)
#define IRIS_MVPL_STORE5_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (8U)
#define IRIS_MVPL_STORE5_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_STORE5_STATICCONTROL_BaseAddressAutoUpdate_MASK)

/*! @name STORE5_BURSTBUFFERMANAGEMENT - Burst Buffer setup register. */
#define IRIS_MVPL_STORE5_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_STORE5_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_STORE5_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_STORE5_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)

/*! @name STORE5_RINGBUFSTARTADDR - Ring buffer setup for destination. */
#define IRIS_MVPL_STORE5_RINGBUFSTARTADDR_RingBufStartAddr_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE5_RINGBUFSTARTADDR_RingBufStartAddr_SHIFT (0U)
#define IRIS_MVPL_STORE5_RINGBUFSTARTADDR_RingBufStartAddr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_RINGBUFSTARTADDR_RingBufStartAddr_SHIFT)) & IRIS_MVPL_STORE5_RINGBUFSTARTADDR_RingBufStartAddr_MASK)

/*! @name STORE5_RINGBUFWRAPADDR - Ring buffer setup for destination. */
#define IRIS_MVPL_STORE5_RINGBUFWRAPADDR_RingBufWrapAddr_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE5_RINGBUFWRAPADDR_RingBufWrapAddr_SHIFT (0U)
#define IRIS_MVPL_STORE5_RINGBUFWRAPADDR_RingBufWrapAddr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_RINGBUFWRAPADDR_RingBufWrapAddr_SHIFT)) & IRIS_MVPL_STORE5_RINGBUFWRAPADDR_RingBufWrapAddr_MASK)

/*! @name STORE5_BASEADDRESS - Destination buffer base address. */
#define IRIS_MVPL_STORE5_BASEADDRESS_BaseAddress_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE5_BASEADDRESS_BaseAddress_SHIFT (0U)
#define IRIS_MVPL_STORE5_BASEADDRESS_BaseAddress(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_BASEADDRESS_BaseAddress_SHIFT)) & IRIS_MVPL_STORE5_BASEADDRESS_BaseAddress_MASK)

/*! @name STORE5_DESTINATIONBUFFERATTRIBUTES - Destination buffer attributes. */
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERATTRIBUTES_Stride_MASK (0x1FFFFU)
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERATTRIBUTES_Stride_SHIFT (0U)
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERATTRIBUTES_Stride(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_DESTINATIONBUFFERATTRIBUTES_Stride_SHIFT)) & IRIS_MVPL_STORE5_DESTINATIONBUFFERATTRIBUTES_Stride_MASK)
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_MASK (0x7F000000U)
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_SHIFT (24U)
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_SHIFT)) & IRIS_MVPL_STORE5_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_MASK)

/*! @name STORE5_DESTINATIONBUFFERDIMENSION - Destination buffer dimension. */
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERDIMENSION_LineWidth_MASK (0x3FFFU)
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERDIMENSION_LineWidth_SHIFT (0U)
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERDIMENSION_LineWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_DESTINATIONBUFFERDIMENSION_LineWidth_SHIFT)) & IRIS_MVPL_STORE5_DESTINATIONBUFFERDIMENSION_LineWidth_MASK)
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERDIMENSION_LineCount_MASK (0x3FFF0000U)
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERDIMENSION_LineCount_SHIFT (16U)
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERDIMENSION_LineCount(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_DESTINATIONBUFFERDIMENSION_LineCount_SHIFT)) & IRIS_MVPL_STORE5_DESTINATIONBUFFERDIMENSION_LineCount_MASK)

/*! @name STORE5_FRAMEOFFSET - Offset between destination frame and buffer. */
#define IRIS_MVPL_STORE5_FRAMEOFFSET_FrameXOffset_MASK (0x7FFFU)
#define IRIS_MVPL_STORE5_FRAMEOFFSET_FrameXOffset_SHIFT (0U)
#define IRIS_MVPL_STORE5_FRAMEOFFSET_FrameXOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_FRAMEOFFSET_FrameXOffset_SHIFT)) & IRIS_MVPL_STORE5_FRAMEOFFSET_FrameXOffset_MASK)
#define IRIS_MVPL_STORE5_FRAMEOFFSET_FrameYOffset_MASK (0x7FFF0000U)
#define IRIS_MVPL_STORE5_FRAMEOFFSET_FrameYOffset_SHIFT (16U)
#define IRIS_MVPL_STORE5_FRAMEOFFSET_FrameYOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_FRAMEOFFSET_FrameYOffset_SHIFT)) & IRIS_MVPL_STORE5_FRAMEOFFSET_FrameYOffset_MASK)

/*! @name STORE5_COLORCOMPONENTBITS - Color component size of destination buffer */
#define IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK (0xFU)
#define IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT (0U)
#define IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT)) & IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK)
#define IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsBlue_MASK (0xF00U)
#define IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT (8U)
#define IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT)) & IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsBlue_MASK)
#define IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsGreen_MASK (0xF0000U)
#define IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT (16U)
#define IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT)) & IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsGreen_MASK)
#define IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsRed_MASK (0xF000000U)
#define IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT (24U)
#define IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT)) & IRIS_MVPL_STORE5_COLORCOMPONENTBITS_ComponentBitsRed_MASK)

/*! @name STORE5_COLORCOMPONENTSHIFT - Color component offset of destination buffer. */
#define IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK (0x1FU)
#define IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT (0U)
#define IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT)) & IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK)
#define IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK (0x1F00U)
#define IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT (8U)
#define IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT)) & IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK)
#define IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK (0x1F0000U)
#define IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT (16U)
#define IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT)) & IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK)
#define IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK (0x1F000000U)
#define IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT (24U)
#define IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT)) & IRIS_MVPL_STORE5_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK)

/*! @name STORE5_CONTROL - Store unit dynamic control register */
#define IRIS_MVPL_STORE5_CONTROL_ColorDitherEnable_MASK (0x1U)
#define IRIS_MVPL_STORE5_CONTROL_ColorDitherEnable_SHIFT (0U)
#define IRIS_MVPL_STORE5_CONTROL_ColorDitherEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_CONTROL_ColorDitherEnable_SHIFT)) & IRIS_MVPL_STORE5_CONTROL_ColorDitherEnable_MASK)
#define IRIS_MVPL_STORE5_CONTROL_AlphaDitherEnable_MASK (0x2U)
#define IRIS_MVPL_STORE5_CONTROL_AlphaDitherEnable_SHIFT (1U)
#define IRIS_MVPL_STORE5_CONTROL_AlphaDitherEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_CONTROL_AlphaDitherEnable_SHIFT)) & IRIS_MVPL_STORE5_CONTROL_AlphaDitherEnable_MASK)
#define IRIS_MVPL_STORE5_CONTROL_DitherOffset_MASK (0xF0U)
#define IRIS_MVPL_STORE5_CONTROL_DitherOffset_SHIFT (4U)
#define IRIS_MVPL_STORE5_CONTROL_DitherOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_CONTROL_DitherOffset_SHIFT)) & IRIS_MVPL_STORE5_CONTROL_DitherOffset_MASK)
#define IRIS_MVPL_STORE5_CONTROL_GammaApplyEnable_MASK (0x1000U)
#define IRIS_MVPL_STORE5_CONTROL_GammaApplyEnable_SHIFT (12U)
#define IRIS_MVPL_STORE5_CONTROL_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_CONTROL_GammaApplyEnable_SHIFT)) & IRIS_MVPL_STORE5_CONTROL_GammaApplyEnable_MASK)
#define IRIS_MVPL_STORE5_CONTROL_YUVConversionMode_MASK (0x30000U)
#define IRIS_MVPL_STORE5_CONTROL_YUVConversionMode_SHIFT (16U)
#define IRIS_MVPL_STORE5_CONTROL_YUVConversionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_CONTROL_YUVConversionMode_SHIFT)) & IRIS_MVPL_STORE5_CONTROL_YUVConversionMode_MASK)
#define IRIS_MVPL_STORE5_CONTROL_RasterMode_MASK (0xC0000U)
#define IRIS_MVPL_STORE5_CONTROL_RasterMode_SHIFT (18U)
#define IRIS_MVPL_STORE5_CONTROL_RasterMode(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_STORE5_CONTROL_RasterMode_MASK)
#define IRIS_MVPL_STORE5_CONTROL_YUV422DownsamplingMode_MASK (0x300000U)
#define IRIS_MVPL_STORE5_CONTROL_YUV422DownsamplingMode_SHIFT (20U)
#define IRIS_MVPL_STORE5_CONTROL_YUV422DownsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_CONTROL_YUV422DownsamplingMode_SHIFT)) & IRIS_MVPL_STORE5_CONTROL_YUV422DownsamplingMode_MASK)

/*! @name STORE5_ENCODECONTROL - Control options for RLAD compression. */
#define IRIS_MVPL_STORE5_ENCODECONTROL_CompressionMode_MASK (0x1U)
#define IRIS_MVPL_STORE5_ENCODECONTROL_CompressionMode_SHIFT (0U)
#define IRIS_MVPL_STORE5_ENCODECONTROL_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_ENCODECONTROL_CompressionMode_SHIFT)) & IRIS_MVPL_STORE5_ENCODECONTROL_CompressionMode_MASK)
#define IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsRed_MASK (0xF0000U)
#define IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsRed_SHIFT (16U)
#define IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsRed_SHIFT)) & IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsRed_MASK)
#define IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsGreen_MASK (0xF00000U)
#define IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsGreen_SHIFT (20U)
#define IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsGreen_SHIFT)) & IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsGreen_MASK)
#define IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsBlue_MASK (0xF000000U)
#define IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsBlue_SHIFT (24U)
#define IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsBlue_SHIFT)) & IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsBlue_MASK)
#define IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsAlpha_MASK (0xF0000000U)
#define IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsAlpha_SHIFT (28U)
#define IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsAlpha_SHIFT)) & IRIS_MVPL_STORE5_ENCODECONTROL_RLADCompBitsAlpha_MASK)

/*! @name STORE5_DESTINATIONBUFFERLENGTH - Destination buffer length for compressed data. */
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERLENGTH_RLEWordsMax_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERLENGTH_RLEWordsMax_SHIFT (0U)
#define IRIS_MVPL_STORE5_DESTINATIONBUFFERLENGTH_RLEWordsMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_DESTINATIONBUFFERLENGTH_RLEWordsMax_SHIFT)) & IRIS_MVPL_STORE5_DESTINATIONBUFFERLENGTH_RLEWordsMax_MASK)

/*! @name STORE5_START - Store unit start register */
#define IRIS_MVPL_STORE5_START_Start_MASK        (0x1U)
#define IRIS_MVPL_STORE5_START_Start_SHIFT       (0U)
#define IRIS_MVPL_STORE5_START_Start(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_START_Start_SHIFT)) & IRIS_MVPL_STORE5_START_Start_MASK)

/*! @name STORE5_ENCODERSTATUS - Status information of the RLAD encoder. */
#define IRIS_MVPL_STORE5_ENCODERSTATUS_RLEWords_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_STORE5_ENCODERSTATUS_RLEWords_SHIFT (0U)
#define IRIS_MVPL_STORE5_ENCODERSTATUS_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_ENCODERSTATUS_RLEWords_SHIFT)) & IRIS_MVPL_STORE5_ENCODERSTATUS_RLEWords_MASK)
#define IRIS_MVPL_STORE5_ENCODERSTATUS_BufferTooSmall_MASK (0x80000000U)
#define IRIS_MVPL_STORE5_ENCODERSTATUS_BufferTooSmall_SHIFT (31U)
#define IRIS_MVPL_STORE5_ENCODERSTATUS_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_ENCODERSTATUS_BufferTooSmall_SHIFT)) & IRIS_MVPL_STORE5_ENCODERSTATUS_BufferTooSmall_MASK)

/*! @name STORE5_WRITEADDRESS - Ring buffer synchronization. */
#define IRIS_MVPL_STORE5_WRITEADDRESS_WriteAddress_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE5_WRITEADDRESS_WriteAddress_SHIFT (0U)
#define IRIS_MVPL_STORE5_WRITEADDRESS_WriteAddress(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_WRITEADDRESS_WriteAddress_SHIFT)) & IRIS_MVPL_STORE5_WRITEADDRESS_WriteAddress_MASK)

/*! @name STORE5_FRAMEPROPERTIES - Ring buffer synchronization. */
#define IRIS_MVPL_STORE5_FRAMEPROPERTIES_FieldId_MASK (0x1U)
#define IRIS_MVPL_STORE5_FRAMEPROPERTIES_FieldId_SHIFT (0U)
#define IRIS_MVPL_STORE5_FRAMEPROPERTIES_FieldId(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_FRAMEPROPERTIES_FieldId_SHIFT)) & IRIS_MVPL_STORE5_FRAMEPROPERTIES_FieldId_MASK)

/*! @name STORE5_BURSTBUFFERPROPERTIES - Burst Buffer Property register */
#define IRIS_MVPL_STORE5_BURSTBUFFERPROPERTIES_MaxBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_STORE5_BURSTBUFFERPROPERTIES_MaxBurstLength_SHIFT (8U)
#define IRIS_MVPL_STORE5_BURSTBUFFERPROPERTIES_MaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_BURSTBUFFERPROPERTIES_MaxBurstLength_SHIFT)) & IRIS_MVPL_STORE5_BURSTBUFFERPROPERTIES_MaxBurstLength_MASK)

/*! @name STORE5_LASTCONTROLWORD - Shows the last control word received */
#define IRIS_MVPL_STORE5_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE5_LASTCONTROLWORD_L_VAL_SHIFT (0U)
#define IRIS_MVPL_STORE5_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_STORE5_LASTCONTROLWORD_L_VAL_MASK)

/*! @name STORE5_PERFCOUNTER - Performance counter result */
#define IRIS_MVPL_STORE5_PERFCOUNTER_PerfResult_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_STORE5_PERFCOUNTER_PerfResult_SHIFT (0U)
#define IRIS_MVPL_STORE5_PERFCOUNTER_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_PERFCOUNTER_PerfResult_SHIFT)) & IRIS_MVPL_STORE5_PERFCOUNTER_PerfResult_MASK)

/*! @name STORE5_STATUS - Shows status information */
#define IRIS_MVPL_STORE5_STATUS_StatusBusy_MASK  (0x1U)
#define IRIS_MVPL_STORE5_STATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_STORE5_STATUS_StatusBusy(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_STORE5_STATUS_StatusBusy_MASK)
#define IRIS_MVPL_STORE5_STATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_STORE5_STATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_STORE5_STATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_STATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_STORE5_STATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_STORE5_STATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_STORE5_STATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_STORE5_STATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_STATUS_StatusRequest_SHIFT)) & IRIS_MVPL_STORE5_STATUS_StatusRequest_MASK)
#define IRIS_MVPL_STORE5_STATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_STORE5_STATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_STORE5_STATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_STATUS_StatusComplete_SHIFT)) & IRIS_MVPL_STORE5_STATUS_StatusComplete_MASK)
#define IRIS_MVPL_STORE5_STATUS_PixelbusError_MASK (0x100U)
#define IRIS_MVPL_STORE5_STATUS_PixelbusError_SHIFT (8U)
#define IRIS_MVPL_STORE5_STATUS_PixelbusError(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_STATUS_PixelbusError_SHIFT)) & IRIS_MVPL_STORE5_STATUS_PixelbusError_MASK)
#define IRIS_MVPL_STORE5_STATUS_EncoderOverflow_MASK (0x10000U)
#define IRIS_MVPL_STORE5_STATUS_EncoderOverflow_SHIFT (16U)
#define IRIS_MVPL_STORE5_STATUS_EncoderOverflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_STATUS_EncoderOverflow_SHIFT)) & IRIS_MVPL_STORE5_STATUS_EncoderOverflow_MASK)
#define IRIS_MVPL_STORE5_STATUS_EncoderStallPixel_MASK (0x20000U)
#define IRIS_MVPL_STORE5_STATUS_EncoderStallPixel_SHIFT (17U)
#define IRIS_MVPL_STORE5_STATUS_EncoderStallPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE5_STATUS_EncoderStallPixel_SHIFT)) & IRIS_MVPL_STORE5_STATUS_EncoderStallPixel_MASK)

/*! @name FETCHDECODE2_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FETCHDECODE2_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE2_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FETCHDECODE2_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FETCHDECODE2_STATICCONTROL - Common static control options. */
#define IRIS_MVPL_FETCHDECODE2_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE2_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHDECODE2_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_FETCHDECODE2_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHDECODE2_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE2_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHDECODE2_STATICCONTROL_BaseAddressAutoUpdate_MASK)

/*! @name FETCHDECODE2_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHDECODE2_BURSTBUFFERMANAGEMENT_LineMode_MASK)

/*! @name FETCHDECODE2_RINGBUFSTARTADDR0 - Ring buffer setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE2_RINGBUFSTARTADDR0_RingBufStartAddr0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE2_RINGBUFSTARTADDR0_RingBufStartAddr0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_RINGBUFSTARTADDR0_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_RINGBUFSTARTADDR0_RingBufStartAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_RINGBUFSTARTADDR0_RingBufStartAddr0_MASK)

/*! @name FETCHDECODE2_RINGBUFWRAPADDR0 - Ring buffer setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE2_RINGBUFWRAPADDR0_RingBufWrapAddr0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE2_RINGBUFWRAPADDR0_RingBufWrapAddr0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_RINGBUFWRAPADDR0_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_RINGBUFWRAPADDR0_RingBufWrapAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_RINGBUFWRAPADDR0_RingBufWrapAddr0_MASK)

/*! @name FETCHDECODE2_FRAMEPROPERTIES0 - Frame property setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE2_FRAMEPROPERTIES0_FieldId0_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE2_FRAMEPROPERTIES0_FieldId0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_FRAMEPROPERTIES0_FieldId0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_FRAMEPROPERTIES0_FieldId0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_FRAMEPROPERTIES0_FieldId0_MASK)

/*! @name FETCHDECODE2_BASEADDRESS0 - Source buffer base address of layer 0. */
#define IRIS_MVPL_FETCHDECODE2_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE2_BASEADDRESS0_BaseAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_BASEADDRESS0_BaseAddress0_MASK)

/*! @name FETCHDECODE2_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)

/*! @name FETCHDECODE2_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERDIMENSION0_LineCount0_MASK)

/*! @name FETCHDECODE2_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTBITS0_ITUFormat0_MASK)

/*! @name FETCHDECODE2_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)

/*! @name FETCHDECODE2_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
#define IRIS_MVPL_FETCHDECODE2_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHDECODE2_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYEROFFSET0_LayerXOffset0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHDECODE2_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE2_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYEROFFSET0_LayerYOffset0_MASK)

/*! @name FETCHDECODE2_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
#define IRIS_MVPL_FETCHDECODE2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHDECODE2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
#define IRIS_MVPL_FETCHDECODE2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHDECODE2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE2_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)

/*! @name FETCHDECODE2_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
#define IRIS_MVPL_FETCHDECODE2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
#define IRIS_MVPL_FETCHDECODE2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)

/*! @name FETCHDECODE2_CONSTANTCOLOR0 - Constant color for layer 0. */
#define IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
#define IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CONSTANTCOLOR0_ConstantRed0_MASK)

/*! @name FETCHDECODE2_LAYERPROPERTY0 - Common properties of layer 0. */
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_PaletteEnable0_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_PaletteEnable0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_PaletteEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_PaletteEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_TileMode0_MASK (0x30U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_TileMode0_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_TileMode0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaSrcEnable0_MASK (0x100U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaConstEnable0_MASK (0x200U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaConstEnable0_SHIFT (9U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaMaskEnable0_MASK (0x400U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT (10U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaMaskEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaTransEnable0_MASK (0x800U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaTransEnable0_SHIFT (11U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_AlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK (0x1000U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT (12U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK (0x2000U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT (13U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK (0x4000U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT (14U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK (0x8000U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT (15U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_PremulConstRGB0_MASK (0x10000U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_PremulConstRGB0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_PremulConstRGB0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_YUVConversionMode0_MASK (0x60000U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_YUVConversionMode0_SHIFT (17U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_YUVConversionMode0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_GammaRemoveEnable0_MASK (0x100000U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT (20U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_GammaRemoveEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_ClipWindowEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_LAYERPROPERTY0_SourceBufferEnable0_MASK)

/*! @name FETCHDECODE2_FRAMEDIMENSIONS - Output frame dimension. */
#define IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHDECODE2_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name FETCHDECODE2_FRAMERESAMPLING - Resampling options for output frame. */
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_StartX_MASK (0x3FU)
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_StartX_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_StartX_MASK)
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_StartY_MASK (0xFC0U)
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_StartY_SHIFT (6U)
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_StartY_MASK)
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_DeltaX_SHIFT (12U)
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_DeltaX_MASK)
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_DeltaY_SHIFT (18U)
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_DeltaY_MASK)
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHDECODE2_FRAMERESAMPLING_SwapDirection_MASK)

/*! @name FETCHDECODE2_DECODECONTROL - Control options for RLAD decompression. */
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_CompressionMode_MASK (0x3U)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_CompressionMode_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_DECODECONTROL_CompressionMode_SHIFT)) & IRIS_MVPL_FETCHDECODE2_DECODECONTROL_CompressionMode_MASK)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADEndianness_MASK (0x8000U)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADEndianness_SHIFT (15U)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADEndianness(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADEndianness_SHIFT)) & IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADEndianness_MASK)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsRed_MASK (0xF0000U)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsRed_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsRed_SHIFT)) & IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsRed_MASK)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsGreen_MASK (0xF00000U)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsGreen_SHIFT (20U)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsGreen_SHIFT)) & IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsGreen_MASK)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsBlue_MASK (0xF000000U)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsBlue_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsBlue_SHIFT)) & IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsBlue_MASK)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsAlpha_MASK (0xF0000000U)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsAlpha_SHIFT (28U)
#define IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsAlpha_SHIFT)) & IRIS_MVPL_FETCHDECODE2_DECODECONTROL_RLADCompBitsAlpha_MASK)

/*! @name FETCHDECODE2_SOURCEBUFFERLENGTH - Source buffer length for compressed data. */
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERLENGTH_RLEWords_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERLENGTH_RLEWords_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERLENGTH_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERLENGTH_RLEWords_SHIFT)) & IRIS_MVPL_FETCHDECODE2_SOURCEBUFFERLENGTH_RLEWords_MASK)

/*! @name FETCHDECODE2_CONTROL - Shared common control settings for all layers. */
#define IRIS_MVPL_FETCHDECODE2_CONTROL_RasterMode_MASK (0x7U)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_RasterMode_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CONTROL_RasterMode_MASK)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_InputSelect_MASK (0x18U)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_InputSelect_SHIFT (3U)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CONTROL_InputSelect_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CONTROL_InputSelect_MASK)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_YUV422UpsamplingMode_MASK (0x20U)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_YUV422UpsamplingMode_SHIFT (5U)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CONTROL_YUV422UpsamplingMode_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CONTROL_YUV422UpsamplingMode_MASK)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_RawPixel_MASK (0x80U)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_RawPixel_SHIFT (7U)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CONTROL_RawPixel_MASK)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_PaletteIdxWidth_MASK (0x700U)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_PaletteIdxWidth_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CONTROL_PaletteIdxWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CONTROL_PaletteIdxWidth_MASK)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_ClipColor_MASK (0x10000U)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_ClipColor_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE2_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CONTROL_ClipColor_MASK)

/*! @name FETCHDECODE2_CONTROLTRIGGER - Shadow load trigger. */
#define IRIS_MVPL_FETCHDECODE2_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE2_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHDECODE2_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name FETCHDECODE2_START - Frame start trigger. */
#define IRIS_MVPL_FETCHDECODE2_START_Start_MASK  (0x1U)
#define IRIS_MVPL_FETCHDECODE2_START_Start_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_START_Start(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_START_Start_SHIFT)) & IRIS_MVPL_FETCHDECODE2_START_Start_MASK)

/*! @name FETCHDECODE2_FETCHTYPE - Fetch unit type. */
#define IRIS_MVPL_FETCHDECODE2_FETCHTYPE_FetchType_MASK (0xFU)
#define IRIS_MVPL_FETCHDECODE2_FETCHTYPE_FetchType_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHDECODE2_FETCHTYPE_FetchType_MASK)

/*! @name FETCHDECODE2_DECODERSTATUS - Status information of the RLAD decoder. */
#define IRIS_MVPL_FETCHDECODE2_DECODERSTATUS_BufferTooSmall_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE2_DECODERSTATUS_BufferTooSmall_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_DECODERSTATUS_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_DECODERSTATUS_BufferTooSmall_SHIFT)) & IRIS_MVPL_FETCHDECODE2_DECODERSTATUS_BufferTooSmall_MASK)
#define IRIS_MVPL_FETCHDECODE2_DECODERSTATUS_BufferTooLarge_MASK (0x2U)
#define IRIS_MVPL_FETCHDECODE2_DECODERSTATUS_BufferTooLarge_SHIFT (1U)
#define IRIS_MVPL_FETCHDECODE2_DECODERSTATUS_BufferTooLarge(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_DECODERSTATUS_BufferTooLarge_SHIFT)) & IRIS_MVPL_FETCHDECODE2_DECODERSTATUS_BufferTooLarge_MASK)

/*! @name FETCHDECODE2_READADDRESS0 - Ring buffer synchronization for layer 0. */
#define IRIS_MVPL_FETCHDECODE2_READADDRESS0_ReadAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE2_READADDRESS0_ReadAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_READADDRESS0_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_READADDRESS0_ReadAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE2_READADDRESS0_ReadAddress0_MASK)

/*! @name FETCHDECODE2_BURSTBUFFERPROPERTIES - Burst buffer properties. */
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)

/*! @name FETCHDECODE2_STATUS - Status informations. */
#define IRIS_MVPL_FETCHDECODE2_STATUS_WriteTimeout_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE2_STATUS_WriteTimeout_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE2_STATUS_WriteTimeout_MASK)
#define IRIS_MVPL_FETCHDECODE2_STATUS_ReadTimeout_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE2_STATUS_ReadTimeout_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE2_STATUS_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_STATUS_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE2_STATUS_ReadTimeout_MASK)

/*! @name FETCHDECODE2_HIDDENSTATUS - Hidden status informations. */
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusBusy_MASK)
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusRequest_MASK)
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_StatusComplete_MASK)
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE2_HIDDENSTATUS_ShadowStatus_MASK)

/*! @name FETCHDECODE2_COLORPALETTE - Color palette look up table. */
#define IRIS_MVPL_FETCHDECODE2_COLORPALETTE_ColorPalette_MASK (0xFFFFFFU)
#define IRIS_MVPL_FETCHDECODE2_COLORPALETTE_ColorPalette_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE2_COLORPALETTE_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE2_COLORPALETTE_ColorPalette_SHIFT)) & IRIS_MVPL_FETCHDECODE2_COLORPALETTE_ColorPalette_MASK)

/*! @name FETCHDECODE3_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FETCHDECODE3_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE3_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FETCHDECODE3_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FETCHDECODE3_STATICCONTROL - Common static control options. */
#define IRIS_MVPL_FETCHDECODE3_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE3_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHDECODE3_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_FETCHDECODE3_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHDECODE3_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE3_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHDECODE3_STATICCONTROL_BaseAddressAutoUpdate_MASK)

/*! @name FETCHDECODE3_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHDECODE3_BURSTBUFFERMANAGEMENT_LineMode_MASK)

/*! @name FETCHDECODE3_RINGBUFSTARTADDR0 - Ring buffer setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE3_RINGBUFSTARTADDR0_RingBufStartAddr0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE3_RINGBUFSTARTADDR0_RingBufStartAddr0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_RINGBUFSTARTADDR0_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_RINGBUFSTARTADDR0_RingBufStartAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_RINGBUFSTARTADDR0_RingBufStartAddr0_MASK)

/*! @name FETCHDECODE3_RINGBUFWRAPADDR0 - Ring buffer setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE3_RINGBUFWRAPADDR0_RingBufWrapAddr0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE3_RINGBUFWRAPADDR0_RingBufWrapAddr0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_RINGBUFWRAPADDR0_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_RINGBUFWRAPADDR0_RingBufWrapAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_RINGBUFWRAPADDR0_RingBufWrapAddr0_MASK)

/*! @name FETCHDECODE3_FRAMEPROPERTIES0 - Frame property setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE3_FRAMEPROPERTIES0_FieldId0_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE3_FRAMEPROPERTIES0_FieldId0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_FRAMEPROPERTIES0_FieldId0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_FRAMEPROPERTIES0_FieldId0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_FRAMEPROPERTIES0_FieldId0_MASK)

/*! @name FETCHDECODE3_BASEADDRESS0 - Source buffer base address of layer 0. */
#define IRIS_MVPL_FETCHDECODE3_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE3_BASEADDRESS0_BaseAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_BASEADDRESS0_BaseAddress0_MASK)

/*! @name FETCHDECODE3_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)

/*! @name FETCHDECODE3_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERDIMENSION0_LineCount0_MASK)

/*! @name FETCHDECODE3_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTBITS0_ITUFormat0_MASK)

/*! @name FETCHDECODE3_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)

/*! @name FETCHDECODE3_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
#define IRIS_MVPL_FETCHDECODE3_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHDECODE3_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYEROFFSET0_LayerXOffset0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHDECODE3_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE3_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYEROFFSET0_LayerYOffset0_MASK)

/*! @name FETCHDECODE3_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
#define IRIS_MVPL_FETCHDECODE3_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHDECODE3_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
#define IRIS_MVPL_FETCHDECODE3_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHDECODE3_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE3_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)

/*! @name FETCHDECODE3_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
#define IRIS_MVPL_FETCHDECODE3_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE3_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
#define IRIS_MVPL_FETCHDECODE3_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE3_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE3_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)

/*! @name FETCHDECODE3_CONSTANTCOLOR0 - Constant color for layer 0. */
#define IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
#define IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CONSTANTCOLOR0_ConstantRed0_MASK)

/*! @name FETCHDECODE3_LAYERPROPERTY0 - Common properties of layer 0. */
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_PaletteEnable0_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_PaletteEnable0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_PaletteEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_PaletteEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_TileMode0_MASK (0x30U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_TileMode0_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_TileMode0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaSrcEnable0_MASK (0x100U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaConstEnable0_MASK (0x200U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaConstEnable0_SHIFT (9U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaMaskEnable0_MASK (0x400U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT (10U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaMaskEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaTransEnable0_MASK (0x800U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaTransEnable0_SHIFT (11U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_AlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK (0x1000U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT (12U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK (0x2000U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT (13U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK (0x4000U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT (14U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK (0x8000U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT (15U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_PremulConstRGB0_MASK (0x10000U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_PremulConstRGB0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_PremulConstRGB0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_YUVConversionMode0_MASK (0x60000U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_YUVConversionMode0_SHIFT (17U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_YUVConversionMode0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_GammaRemoveEnable0_MASK (0x100000U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT (20U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_GammaRemoveEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_ClipWindowEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_LAYERPROPERTY0_SourceBufferEnable0_MASK)

/*! @name FETCHDECODE3_FRAMEDIMENSIONS - Output frame dimension. */
#define IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHDECODE3_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name FETCHDECODE3_FRAMERESAMPLING - Resampling options for output frame. */
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_StartX_MASK (0x3FU)
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_StartX_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_StartX_MASK)
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_StartY_MASK (0xFC0U)
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_StartY_SHIFT (6U)
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_StartY_MASK)
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_DeltaX_SHIFT (12U)
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_DeltaX_MASK)
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_DeltaY_SHIFT (18U)
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_DeltaY_MASK)
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHDECODE3_FRAMERESAMPLING_SwapDirection_MASK)

/*! @name FETCHDECODE3_DECODECONTROL - Control options for RLAD decompression. */
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_CompressionMode_MASK (0x3U)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_CompressionMode_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_DECODECONTROL_CompressionMode_SHIFT)) & IRIS_MVPL_FETCHDECODE3_DECODECONTROL_CompressionMode_MASK)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADEndianness_MASK (0x8000U)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADEndianness_SHIFT (15U)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADEndianness(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADEndianness_SHIFT)) & IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADEndianness_MASK)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsRed_MASK (0xF0000U)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsRed_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsRed_SHIFT)) & IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsRed_MASK)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsGreen_MASK (0xF00000U)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsGreen_SHIFT (20U)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsGreen_SHIFT)) & IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsGreen_MASK)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsBlue_MASK (0xF000000U)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsBlue_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsBlue_SHIFT)) & IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsBlue_MASK)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsAlpha_MASK (0xF0000000U)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsAlpha_SHIFT (28U)
#define IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsAlpha_SHIFT)) & IRIS_MVPL_FETCHDECODE3_DECODECONTROL_RLADCompBitsAlpha_MASK)

/*! @name FETCHDECODE3_SOURCEBUFFERLENGTH - Source buffer length for compressed data. */
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERLENGTH_RLEWords_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERLENGTH_RLEWords_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERLENGTH_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERLENGTH_RLEWords_SHIFT)) & IRIS_MVPL_FETCHDECODE3_SOURCEBUFFERLENGTH_RLEWords_MASK)

/*! @name FETCHDECODE3_CONTROL - Shared common control settings for all layers. */
#define IRIS_MVPL_FETCHDECODE3_CONTROL_RasterMode_MASK (0x7U)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_RasterMode_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CONTROL_RasterMode_MASK)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_InputSelect_MASK (0x18U)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_InputSelect_SHIFT (3U)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CONTROL_InputSelect_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CONTROL_InputSelect_MASK)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_YUV422UpsamplingMode_MASK (0x20U)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_YUV422UpsamplingMode_SHIFT (5U)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CONTROL_YUV422UpsamplingMode_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CONTROL_YUV422UpsamplingMode_MASK)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_RawPixel_MASK (0x80U)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_RawPixel_SHIFT (7U)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CONTROL_RawPixel_MASK)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_PaletteIdxWidth_MASK (0x700U)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_PaletteIdxWidth_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CONTROL_PaletteIdxWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CONTROL_PaletteIdxWidth_MASK)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_ClipColor_MASK (0x10000U)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_ClipColor_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE3_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CONTROL_ClipColor_MASK)

/*! @name FETCHDECODE3_CONTROLTRIGGER - Shadow load trigger. */
#define IRIS_MVPL_FETCHDECODE3_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE3_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHDECODE3_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name FETCHDECODE3_START - Frame start trigger. */
#define IRIS_MVPL_FETCHDECODE3_START_Start_MASK  (0x1U)
#define IRIS_MVPL_FETCHDECODE3_START_Start_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_START_Start(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_START_Start_SHIFT)) & IRIS_MVPL_FETCHDECODE3_START_Start_MASK)

/*! @name FETCHDECODE3_FETCHTYPE - Fetch unit type. */
#define IRIS_MVPL_FETCHDECODE3_FETCHTYPE_FetchType_MASK (0xFU)
#define IRIS_MVPL_FETCHDECODE3_FETCHTYPE_FetchType_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHDECODE3_FETCHTYPE_FetchType_MASK)

/*! @name FETCHDECODE3_DECODERSTATUS - Status information of the RLAD decoder. */
#define IRIS_MVPL_FETCHDECODE3_DECODERSTATUS_BufferTooSmall_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE3_DECODERSTATUS_BufferTooSmall_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_DECODERSTATUS_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_DECODERSTATUS_BufferTooSmall_SHIFT)) & IRIS_MVPL_FETCHDECODE3_DECODERSTATUS_BufferTooSmall_MASK)
#define IRIS_MVPL_FETCHDECODE3_DECODERSTATUS_BufferTooLarge_MASK (0x2U)
#define IRIS_MVPL_FETCHDECODE3_DECODERSTATUS_BufferTooLarge_SHIFT (1U)
#define IRIS_MVPL_FETCHDECODE3_DECODERSTATUS_BufferTooLarge(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_DECODERSTATUS_BufferTooLarge_SHIFT)) & IRIS_MVPL_FETCHDECODE3_DECODERSTATUS_BufferTooLarge_MASK)

/*! @name FETCHDECODE3_READADDRESS0 - Ring buffer synchronization for layer 0. */
#define IRIS_MVPL_FETCHDECODE3_READADDRESS0_ReadAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE3_READADDRESS0_ReadAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_READADDRESS0_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_READADDRESS0_ReadAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE3_READADDRESS0_ReadAddress0_MASK)

/*! @name FETCHDECODE3_BURSTBUFFERPROPERTIES - Burst buffer properties. */
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE3_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE3_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE3_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)

/*! @name FETCHDECODE3_STATUS - Status informations. */
#define IRIS_MVPL_FETCHDECODE3_STATUS_WriteTimeout_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE3_STATUS_WriteTimeout_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE3_STATUS_WriteTimeout_MASK)
#define IRIS_MVPL_FETCHDECODE3_STATUS_ReadTimeout_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE3_STATUS_ReadTimeout_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE3_STATUS_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_STATUS_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE3_STATUS_ReadTimeout_MASK)

/*! @name FETCHDECODE3_HIDDENSTATUS - Hidden status informations. */
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusBusy_MASK)
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusRequest_MASK)
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_StatusComplete_MASK)
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE3_HIDDENSTATUS_ShadowStatus_MASK)

/*! @name FETCHDECODE3_COLORPALETTE - Color palette look up table. */
#define IRIS_MVPL_FETCHDECODE3_COLORPALETTE_ColorPalette_MASK (0xFFFFFFU)
#define IRIS_MVPL_FETCHDECODE3_COLORPALETTE_ColorPalette_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE3_COLORPALETTE_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE3_COLORPALETTE_ColorPalette_SHIFT)) & IRIS_MVPL_FETCHDECODE3_COLORPALETTE_ColorPalette_MASK)

/*! @name FETCHWARP2_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FETCHWARP2_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHWARP2_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHWARP2_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FETCHWARP2_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHWARP2_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP2_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP2_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FETCHWARP2_STATICCONTROL - Common static control options. */
#define IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_FETCHWARP2_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHWARP2_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHWARP2_STATICCONTROL_BaseAddressAutoUpdate_MASK)
#define IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdLdReqSticky_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdLdReqSticky_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdLdReqSticky(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdLdReqSticky_SHIFT)) & IRIS_MVPL_FETCHWARP2_STATICCONTROL_ShdLdReqSticky_MASK)

/*! @name FETCHWARP2_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHWARP2_BURSTBUFFERMANAGEMENT_LineMode_MASK)

/*! @name FETCHWARP2_BASEADDRESS0 - Source buffer base address of layer 0. */
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS0_BaseAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS0_BaseAddress0_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION0_LineCount0_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS0_ITUFormat0_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)

/*! @name FETCHWARP2_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerXOffset0_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET0_LayerYOffset0_MASK)

/*! @name FETCHWARP2_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)

/*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)

/*! @name FETCHWARP2_CONSTANTCOLOR0 - Constant color for layer 0. */
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantAlpha0_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantBlue0_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantGreen0_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR0_ConstantRed0_MASK)

/*! @name FETCHWARP2_LAYERPROPERTY0 - Common properties of layer 0. */
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_TileMode0_MASK (0x30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_TileMode0_SHIFT (4U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_TileMode0_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaSrcEnable0_MASK (0x100U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaConstEnable0_MASK (0x200U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaConstEnable0_SHIFT (9U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaMaskEnable0_MASK (0x400U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT (10U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaMaskEnable0_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaTransEnable0_MASK (0x800U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaTransEnable0_SHIFT (11U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_AlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK (0x1000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT (12U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK (0x2000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT (13U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK (0x4000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT (14U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK (0x8000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT (15U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_PremulConstRGB0_MASK (0x10000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_PremulConstRGB0_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_PremulConstRGB0_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_YUVConversionMode0_MASK (0x60000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_YUVConversionMode0_SHIFT (17U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_YUVConversionMode0_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_GammaRemoveEnable0_MASK (0x100000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT (20U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_GammaRemoveEnable0_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_ClipWindowEnable0_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY0_SourceBufferEnable0_MASK)

/*! @name FETCHWARP2_BASEADDRESS1 - Source buffer base address of layer 1. */
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS1_BaseAddress1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS1_BaseAddress1_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS1_BaseAddress1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS1_BaseAddress1_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS1_BaseAddress1_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES1 - Source buffer attributes for layer 1. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_Stride1_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_Stride1_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_Stride1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_Stride1_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_Stride1_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERDIMENSION1 - Source buffer dimensions of layer 1, */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineWidth1_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineWidth1_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineWidth1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineWidth1_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineWidth1_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineCount1_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineCount1_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineCount1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineCount1_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION1_LineCount1_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTBITS1 - Size of color components for RGB, YUV and index formats (layer 1). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsAlpha1_MASK (0xFU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsAlpha1_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsAlpha1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsAlpha1_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsBlue1_MASK (0xF00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsBlue1_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsBlue1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsBlue1_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsGreen1_MASK (0xF0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsGreen1_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsGreen1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsGreen1_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsRed1_MASK (0xF000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsRed1_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsRed1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ComponentBitsRed1_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ITUFormat1_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ITUFormat1_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ITUFormat1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ITUFormat1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS1_ITUFormat1_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTSHIFT1 - Bit position of color components for RGB, YUV and index formats (layer 1). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_MASK (0x1FU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_MASK (0x1F00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftRed1_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftRed1_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftRed1_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT1_ComponentShiftRed1_MASK)

/*! @name FETCHWARP2_LAYEROFFSET1 - Position of layer 1 within the destination frame. */
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerXOffset1_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerXOffset1_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerXOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerXOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerXOffset1_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerYOffset1_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerYOffset1_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerYOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerYOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET1_LayerYOffset1_MASK)

/*! @name FETCHWARP2_CLIPWINDOWOFFSET1 - Clip window position for layer 1. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowXOffset1_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowXOffset1_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowXOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowXOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowXOffset1_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowYOffset1_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowYOffset1_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowYOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowYOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET1_ClipWindowYOffset1_MASK)

/*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS1 - Clip window size for layer 1. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_MASK)

/*! @name FETCHWARP2_CONSTANTCOLOR1 - Constant color for layer 1. */
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantAlpha1_MASK (0xFFU)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantAlpha1_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantAlpha1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantAlpha1_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantBlue1_MASK (0xFF00U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantBlue1_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantBlue1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantBlue1_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantGreen1_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantGreen1_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantGreen1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantGreen1_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantRed1_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantRed1_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantRed1_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR1_ConstantRed1_MASK)

/*! @name FETCHWARP2_LAYERPROPERTY1 - Common properties of layer 1. */
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_TileMode1_MASK (0x30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_TileMode1_SHIFT (4U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_TileMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_TileMode1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_TileMode1_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaSrcEnable1_MASK (0x100U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaSrcEnable1_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaSrcEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaSrcEnable1_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaConstEnable1_MASK (0x200U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaConstEnable1_SHIFT (9U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaConstEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaConstEnable1_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaMaskEnable1_MASK (0x400U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaMaskEnable1_SHIFT (10U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaMaskEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaMaskEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaMaskEnable1_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaTransEnable1_MASK (0x800U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaTransEnable1_SHIFT (11U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaTransEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_AlphaTransEnable1_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaSrcEnable1_MASK (0x1000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaSrcEnable1_SHIFT (12U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaSrcEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaSrcEnable1_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaConstEnable1_MASK (0x2000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaConstEnable1_SHIFT (13U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaConstEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaConstEnable1_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaMaskEnable1_MASK (0x4000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaMaskEnable1_SHIFT (14U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaMaskEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaMaskEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaMaskEnable1_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaTransEnable1_MASK (0x8000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaTransEnable1_SHIFT (15U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaTransEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_RGBAlphaTransEnable1_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_PremulConstRGB1_MASK (0x10000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_PremulConstRGB1_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_PremulConstRGB1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_PremulConstRGB1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_PremulConstRGB1_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_YUVConversionMode1_MASK (0x60000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_YUVConversionMode1_SHIFT (17U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_YUVConversionMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_YUVConversionMode1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_YUVConversionMode1_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_GammaRemoveEnable1_MASK (0x100000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_GammaRemoveEnable1_SHIFT (20U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_GammaRemoveEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_GammaRemoveEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_GammaRemoveEnable1_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_ClipWindowEnable1_MASK (0x40000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_ClipWindowEnable1_SHIFT (30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_ClipWindowEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_ClipWindowEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_ClipWindowEnable1_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_SourceBufferEnable1_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_SourceBufferEnable1_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_SourceBufferEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_SourceBufferEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY1_SourceBufferEnable1_MASK)

/*! @name FETCHWARP2_BASEADDRESS2 - Source buffer base address of layer 2. */
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS2_BaseAddress2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS2_BaseAddress2_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS2_BaseAddress2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS2_BaseAddress2_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS2_BaseAddress2_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES2 - Source buffer attributes for layer 2. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_Stride2_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_Stride2_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_Stride2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_Stride2_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_Stride2_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERDIMENSION2 - Source buffer dimension of layer 2. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineWidth2_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineWidth2_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineWidth2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineWidth2_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineWidth2_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineCount2_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineCount2_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineCount2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineCount2_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION2_LineCount2_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTBITS2 - Size of color components for RGB, YUV and index formats (layer 2). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsAlpha2_MASK (0xFU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsAlpha2_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsAlpha2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsAlpha2_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsBlue2_MASK (0xF00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsBlue2_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsBlue2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsBlue2_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsGreen2_MASK (0xF0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsGreen2_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsGreen2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsGreen2_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsRed2_MASK (0xF000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsRed2_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsRed2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ComponentBitsRed2_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ITUFormat2_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ITUFormat2_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ITUFormat2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ITUFormat2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS2_ITUFormat2_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTSHIFT2 - Bit position of color components for RGB, YUV and index formats (layer 2). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_MASK (0x1FU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_MASK (0x1F00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftRed2_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftRed2_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftRed2_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT2_ComponentShiftRed2_MASK)

/*! @name FETCHWARP2_LAYEROFFSET2 - Position of layer 2 within the destination frame. */
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerXOffset2_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerXOffset2_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerXOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerXOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerXOffset2_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerYOffset2_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerYOffset2_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerYOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerYOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET2_LayerYOffset2_MASK)

/*! @name FETCHWARP2_CLIPWINDOWOFFSET2 - Clip window position for layer 2. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowXOffset2_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowXOffset2_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowXOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowXOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowXOffset2_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowYOffset2_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowYOffset2_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowYOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowYOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET2_ClipWindowYOffset2_MASK)

/*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS2 - Clip window size for layer 2. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_MASK)

/*! @name FETCHWARP2_CONSTANTCOLOR2 - Constant color for layer 2. */
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantAlpha2_MASK (0xFFU)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantAlpha2_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantAlpha2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantAlpha2_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantBlue2_MASK (0xFF00U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantBlue2_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantBlue2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantBlue2_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantGreen2_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantGreen2_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantGreen2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantGreen2_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantRed2_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantRed2_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantRed2_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR2_ConstantRed2_MASK)

/*! @name FETCHWARP2_LAYERPROPERTY2 - Common properties of layer 2. */
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_TileMode2_MASK (0x30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_TileMode2_SHIFT (4U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_TileMode2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_TileMode2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_TileMode2_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaSrcEnable2_MASK (0x100U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaSrcEnable2_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaSrcEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaSrcEnable2_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaConstEnable2_MASK (0x200U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaConstEnable2_SHIFT (9U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaConstEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaConstEnable2_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaMaskEnable2_MASK (0x400U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaMaskEnable2_SHIFT (10U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaMaskEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaMaskEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaMaskEnable2_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaTransEnable2_MASK (0x800U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaTransEnable2_SHIFT (11U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaTransEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_AlphaTransEnable2_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaSrcEnable2_MASK (0x1000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaSrcEnable2_SHIFT (12U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaSrcEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaSrcEnable2_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaConstEnable2_MASK (0x2000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaConstEnable2_SHIFT (13U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaConstEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaConstEnable2_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaMaskEnable2_MASK (0x4000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaMaskEnable2_SHIFT (14U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaMaskEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaMaskEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaMaskEnable2_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaTransEnable2_MASK (0x8000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaTransEnable2_SHIFT (15U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaTransEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_RGBAlphaTransEnable2_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_PremulConstRGB2_MASK (0x10000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_PremulConstRGB2_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_PremulConstRGB2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_PremulConstRGB2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_PremulConstRGB2_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_YUVConversionMode2_MASK (0x60000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_YUVConversionMode2_SHIFT (17U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_YUVConversionMode2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_YUVConversionMode2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_YUVConversionMode2_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_GammaRemoveEnable2_MASK (0x100000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_GammaRemoveEnable2_SHIFT (20U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_GammaRemoveEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_GammaRemoveEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_GammaRemoveEnable2_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_ClipWindowEnable2_MASK (0x40000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_ClipWindowEnable2_SHIFT (30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_ClipWindowEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_ClipWindowEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_ClipWindowEnable2_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_SourceBufferEnable2_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_SourceBufferEnable2_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_SourceBufferEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_SourceBufferEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY2_SourceBufferEnable2_MASK)

/*! @name FETCHWARP2_BASEADDRESS3 - Source buffer base address of layer 3. */
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS3_BaseAddress3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS3_BaseAddress3_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS3_BaseAddress3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS3_BaseAddress3_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS3_BaseAddress3_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES3 - Source buffer attributes for layer 3. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_Stride3_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_Stride3_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_Stride3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_Stride3_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_Stride3_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERDIMENSION3 - Source buffer dimension of layer 3. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineWidth3_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineWidth3_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineWidth3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineWidth3_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineWidth3_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineCount3_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineCount3_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineCount3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineCount3_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION3_LineCount3_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTBITS3 - Size of color components for RGB, YUV and index formats (layer 3). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsAlpha3_MASK (0xFU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsAlpha3_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsAlpha3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsAlpha3_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsBlue3_MASK (0xF00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsBlue3_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsBlue3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsBlue3_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsGreen3_MASK (0xF0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsGreen3_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsGreen3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsGreen3_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsRed3_MASK (0xF000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsRed3_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsRed3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ComponentBitsRed3_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ITUFormat3_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ITUFormat3_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ITUFormat3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ITUFormat3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS3_ITUFormat3_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTSHIFT3 - Bit position of color components for RGB, YUV and index formats (layer 3). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_MASK (0x1FU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_MASK (0x1F00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftRed3_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftRed3_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftRed3_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT3_ComponentShiftRed3_MASK)

/*! @name FETCHWARP2_LAYEROFFSET3 - Position of layer 3 within the destination frame. */
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerXOffset3_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerXOffset3_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerXOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerXOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerXOffset3_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerYOffset3_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerYOffset3_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerYOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerYOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET3_LayerYOffset3_MASK)

/*! @name FETCHWARP2_CLIPWINDOWOFFSET3 - Clip window position for layer 3. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowXOffset3_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowXOffset3_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowXOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowXOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowXOffset3_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowYOffset3_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowYOffset3_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowYOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowYOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET3_ClipWindowYOffset3_MASK)

/*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS3 - Clip window size for layer 3. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_MASK)

/*! @name FETCHWARP2_CONSTANTCOLOR3 - Constant color for layer 3. */
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantAlpha3_MASK (0xFFU)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantAlpha3_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantAlpha3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantAlpha3_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantBlue3_MASK (0xFF00U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantBlue3_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantBlue3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantBlue3_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantGreen3_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantGreen3_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantGreen3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantGreen3_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantRed3_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantRed3_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantRed3_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR3_ConstantRed3_MASK)

/*! @name FETCHWARP2_LAYERPROPERTY3 - Common properties of layer 3. */
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_TileMode3_MASK (0x30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_TileMode3_SHIFT (4U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_TileMode3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_TileMode3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_TileMode3_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaSrcEnable3_MASK (0x100U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaSrcEnable3_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaSrcEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaSrcEnable3_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaConstEnable3_MASK (0x200U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaConstEnable3_SHIFT (9U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaConstEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaConstEnable3_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaMaskEnable3_MASK (0x400U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaMaskEnable3_SHIFT (10U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaMaskEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaMaskEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaMaskEnable3_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaTransEnable3_MASK (0x800U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaTransEnable3_SHIFT (11U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaTransEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_AlphaTransEnable3_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaSrcEnable3_MASK (0x1000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaSrcEnable3_SHIFT (12U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaSrcEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaSrcEnable3_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaConstEnable3_MASK (0x2000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaConstEnable3_SHIFT (13U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaConstEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaConstEnable3_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaMaskEnable3_MASK (0x4000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaMaskEnable3_SHIFT (14U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaMaskEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaMaskEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaMaskEnable3_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaTransEnable3_MASK (0x8000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaTransEnable3_SHIFT (15U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaTransEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_RGBAlphaTransEnable3_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_PremulConstRGB3_MASK (0x10000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_PremulConstRGB3_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_PremulConstRGB3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_PremulConstRGB3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_PremulConstRGB3_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_YUVConversionMode3_MASK (0x60000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_YUVConversionMode3_SHIFT (17U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_YUVConversionMode3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_YUVConversionMode3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_YUVConversionMode3_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_GammaRemoveEnable3_MASK (0x100000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_GammaRemoveEnable3_SHIFT (20U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_GammaRemoveEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_GammaRemoveEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_GammaRemoveEnable3_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_ClipWindowEnable3_MASK (0x40000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_ClipWindowEnable3_SHIFT (30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_ClipWindowEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_ClipWindowEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_ClipWindowEnable3_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_SourceBufferEnable3_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_SourceBufferEnable3_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_SourceBufferEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_SourceBufferEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY3_SourceBufferEnable3_MASK)

/*! @name FETCHWARP2_BASEADDRESS4 - Source buffer base address of layer 4. */
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS4_BaseAddress4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS4_BaseAddress4_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS4_BaseAddress4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS4_BaseAddress4_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS4_BaseAddress4_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES4 - Source buffer attributes for layer 4. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_Stride4_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_Stride4_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_Stride4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_Stride4_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_Stride4_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERDIMENSION4 - Source buffer dimension of layer 4. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineWidth4_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineWidth4_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineWidth4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineWidth4_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineWidth4_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineCount4_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineCount4_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineCount4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineCount4_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION4_LineCount4_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTBITS4 - Size of color components for RGB, YUV and index formats (layer 4). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsAlpha4_MASK (0xFU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsAlpha4_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsAlpha4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsAlpha4_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsBlue4_MASK (0xF00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsBlue4_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsBlue4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsBlue4_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsGreen4_MASK (0xF0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsGreen4_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsGreen4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsGreen4_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsRed4_MASK (0xF000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsRed4_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsRed4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ComponentBitsRed4_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ITUFormat4_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ITUFormat4_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ITUFormat4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ITUFormat4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS4_ITUFormat4_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTSHIFT4 - Bit position of color components for RGB, YUV and index formats (layer 4). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_MASK (0x1FU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_MASK (0x1F00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftRed4_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftRed4_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftRed4_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT4_ComponentShiftRed4_MASK)

/*! @name FETCHWARP2_LAYEROFFSET4 - Position of layer 4 within the destination frame. */
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerXOffset4_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerXOffset4_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerXOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerXOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerXOffset4_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerYOffset4_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerYOffset4_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerYOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerYOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET4_LayerYOffset4_MASK)

/*! @name FETCHWARP2_CLIPWINDOWOFFSET4 - Clip window position for layer 4. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowXOffset4_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowXOffset4_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowXOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowXOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowXOffset4_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowYOffset4_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowYOffset4_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowYOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowYOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET4_ClipWindowYOffset4_MASK)

/*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS4 - Clip window size for layer 4. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_MASK)

/*! @name FETCHWARP2_CONSTANTCOLOR4 - Constant color for layer 4. */
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantAlpha4_MASK (0xFFU)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantAlpha4_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantAlpha4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantAlpha4_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantBlue4_MASK (0xFF00U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantBlue4_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantBlue4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantBlue4_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantGreen4_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantGreen4_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantGreen4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantGreen4_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantRed4_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantRed4_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantRed4_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR4_ConstantRed4_MASK)

/*! @name FETCHWARP2_LAYERPROPERTY4 - Common properties of layer 4. */
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_TileMode4_MASK (0x30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_TileMode4_SHIFT (4U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_TileMode4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_TileMode4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_TileMode4_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaSrcEnable4_MASK (0x100U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaSrcEnable4_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaSrcEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaSrcEnable4_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaConstEnable4_MASK (0x200U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaConstEnable4_SHIFT (9U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaConstEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaConstEnable4_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaMaskEnable4_MASK (0x400U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaMaskEnable4_SHIFT (10U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaMaskEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaMaskEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaMaskEnable4_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaTransEnable4_MASK (0x800U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaTransEnable4_SHIFT (11U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaTransEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_AlphaTransEnable4_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaSrcEnable4_MASK (0x1000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaSrcEnable4_SHIFT (12U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaSrcEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaSrcEnable4_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaConstEnable4_MASK (0x2000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaConstEnable4_SHIFT (13U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaConstEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaConstEnable4_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaMaskEnable4_MASK (0x4000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaMaskEnable4_SHIFT (14U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaMaskEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaMaskEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaMaskEnable4_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaTransEnable4_MASK (0x8000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaTransEnable4_SHIFT (15U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaTransEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_RGBAlphaTransEnable4_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_PremulConstRGB4_MASK (0x10000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_PremulConstRGB4_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_PremulConstRGB4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_PremulConstRGB4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_PremulConstRGB4_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_YUVConversionMode4_MASK (0x60000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_YUVConversionMode4_SHIFT (17U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_YUVConversionMode4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_YUVConversionMode4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_YUVConversionMode4_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_GammaRemoveEnable4_MASK (0x100000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_GammaRemoveEnable4_SHIFT (20U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_GammaRemoveEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_GammaRemoveEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_GammaRemoveEnable4_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_ClipWindowEnable4_MASK (0x40000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_ClipWindowEnable4_SHIFT (30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_ClipWindowEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_ClipWindowEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_ClipWindowEnable4_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_SourceBufferEnable4_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_SourceBufferEnable4_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_SourceBufferEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_SourceBufferEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY4_SourceBufferEnable4_MASK)

/*! @name FETCHWARP2_BASEADDRESS5 - Source buffer base address of layer 5. */
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS5_BaseAddress5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS5_BaseAddress5_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS5_BaseAddress5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS5_BaseAddress5_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS5_BaseAddress5_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES5 - Source buffer attributes for layer 5. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_Stride5_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_Stride5_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_Stride5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_Stride5_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_Stride5_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERDIMENSION5 - Source buffer dimension of layer 5. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineWidth5_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineWidth5_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineWidth5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineWidth5_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineWidth5_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineCount5_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineCount5_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineCount5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineCount5_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION5_LineCount5_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTBITS5 - Size of color components for RGB, YUV and index formats (layer 5). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsAlpha5_MASK (0xFU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsAlpha5_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsAlpha5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsAlpha5_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsBlue5_MASK (0xF00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsBlue5_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsBlue5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsBlue5_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsGreen5_MASK (0xF0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsGreen5_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsGreen5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsGreen5_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsRed5_MASK (0xF000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsRed5_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsRed5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ComponentBitsRed5_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ITUFormat5_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ITUFormat5_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ITUFormat5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ITUFormat5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS5_ITUFormat5_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTSHIFT5 - Bit position of color components for RGB, YUV and index formats (layer 5). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_MASK (0x1FU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_MASK (0x1F00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftRed5_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftRed5_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftRed5_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT5_ComponentShiftRed5_MASK)

/*! @name FETCHWARP2_LAYEROFFSET5 - Position of layer 5 within the destination frame. */
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerXOffset5_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerXOffset5_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerXOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerXOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerXOffset5_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerYOffset5_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerYOffset5_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerYOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerYOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET5_LayerYOffset5_MASK)

/*! @name FETCHWARP2_CLIPWINDOWOFFSET5 - Clip window position for layer 5. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowXOffset5_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowXOffset5_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowXOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowXOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowXOffset5_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowYOffset5_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowYOffset5_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowYOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowYOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET5_ClipWindowYOffset5_MASK)

/*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS5 - Clip window size for layer 5. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_MASK)

/*! @name FETCHWARP2_CONSTANTCOLOR5 - Constant color for layer 5. */
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantAlpha5_MASK (0xFFU)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantAlpha5_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantAlpha5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantAlpha5_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantBlue5_MASK (0xFF00U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantBlue5_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantBlue5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantBlue5_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantGreen5_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantGreen5_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantGreen5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantGreen5_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantRed5_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantRed5_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantRed5_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR5_ConstantRed5_MASK)

/*! @name FETCHWARP2_LAYERPROPERTY5 - Common properties of layer 5. */
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_TileMode5_MASK (0x30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_TileMode5_SHIFT (4U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_TileMode5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_TileMode5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_TileMode5_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaSrcEnable5_MASK (0x100U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaSrcEnable5_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaSrcEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaSrcEnable5_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaConstEnable5_MASK (0x200U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaConstEnable5_SHIFT (9U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaConstEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaConstEnable5_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaMaskEnable5_MASK (0x400U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaMaskEnable5_SHIFT (10U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaMaskEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaMaskEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaMaskEnable5_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaTransEnable5_MASK (0x800U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaTransEnable5_SHIFT (11U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaTransEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_AlphaTransEnable5_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaSrcEnable5_MASK (0x1000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaSrcEnable5_SHIFT (12U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaSrcEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaSrcEnable5_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaConstEnable5_MASK (0x2000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaConstEnable5_SHIFT (13U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaConstEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaConstEnable5_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaMaskEnable5_MASK (0x4000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaMaskEnable5_SHIFT (14U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaMaskEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaMaskEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaMaskEnable5_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaTransEnable5_MASK (0x8000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaTransEnable5_SHIFT (15U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaTransEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_RGBAlphaTransEnable5_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_PremulConstRGB5_MASK (0x10000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_PremulConstRGB5_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_PremulConstRGB5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_PremulConstRGB5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_PremulConstRGB5_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_YUVConversionMode5_MASK (0x60000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_YUVConversionMode5_SHIFT (17U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_YUVConversionMode5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_YUVConversionMode5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_YUVConversionMode5_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_GammaRemoveEnable5_MASK (0x100000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_GammaRemoveEnable5_SHIFT (20U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_GammaRemoveEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_GammaRemoveEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_GammaRemoveEnable5_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_ClipWindowEnable5_MASK (0x40000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_ClipWindowEnable5_SHIFT (30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_ClipWindowEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_ClipWindowEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_ClipWindowEnable5_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_SourceBufferEnable5_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_SourceBufferEnable5_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_SourceBufferEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_SourceBufferEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY5_SourceBufferEnable5_MASK)

/*! @name FETCHWARP2_BASEADDRESS6 - Source buffer base address of layer 6. */
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS6_BaseAddress6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS6_BaseAddress6_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS6_BaseAddress6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS6_BaseAddress6_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS6_BaseAddress6_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES6 - Source buffer attributes for layer 6. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_Stride6_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_Stride6_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_Stride6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_Stride6_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_Stride6_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERDIMENSION6 - Source buffer dimension of layer 6. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineWidth6_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineWidth6_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineWidth6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineWidth6_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineWidth6_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineCount6_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineCount6_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineCount6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineCount6_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION6_LineCount6_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTBITS6 - Size of color components for RGB, YUV and index formats (layer 6). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsAlpha6_MASK (0xFU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsAlpha6_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsAlpha6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsAlpha6_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsBlue6_MASK (0xF00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsBlue6_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsBlue6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsBlue6_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsGreen6_MASK (0xF0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsGreen6_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsGreen6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsGreen6_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsRed6_MASK (0xF000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsRed6_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsRed6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ComponentBitsRed6_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ITUFormat6_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ITUFormat6_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ITUFormat6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ITUFormat6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS6_ITUFormat6_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTSHIFT6 - Bit position of color components for RGB, YUV and index formats (layer 6). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_MASK (0x1FU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_MASK (0x1F00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftRed6_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftRed6_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftRed6_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT6_ComponentShiftRed6_MASK)

/*! @name FETCHWARP2_LAYEROFFSET6 - Position of layer 1 within the destination frame. */
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerXOffset6_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerXOffset6_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerXOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerXOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerXOffset6_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerYOffset6_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerYOffset6_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerYOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerYOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET6_LayerYOffset6_MASK)

/*! @name FETCHWARP2_CLIPWINDOWOFFSET6 - Clip window position for layer 6. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowXOffset6_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowXOffset6_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowXOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowXOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowXOffset6_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowYOffset6_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowYOffset6_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowYOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowYOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET6_ClipWindowYOffset6_MASK)

/*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS6 - Clip window size for layer 6. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_MASK)

/*! @name FETCHWARP2_CONSTANTCOLOR6 - Constant color for layer 6. */
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantAlpha6_MASK (0xFFU)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantAlpha6_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantAlpha6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantAlpha6_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantBlue6_MASK (0xFF00U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantBlue6_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantBlue6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantBlue6_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantGreen6_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantGreen6_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantGreen6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantGreen6_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantRed6_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantRed6_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantRed6_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR6_ConstantRed6_MASK)

/*! @name FETCHWARP2_LAYERPROPERTY6 - Common properties of layer 6. */
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_TileMode6_MASK (0x30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_TileMode6_SHIFT (4U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_TileMode6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_TileMode6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_TileMode6_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaSrcEnable6_MASK (0x100U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaSrcEnable6_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaSrcEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaSrcEnable6_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaConstEnable6_MASK (0x200U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaConstEnable6_SHIFT (9U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaConstEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaConstEnable6_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaMaskEnable6_MASK (0x400U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaMaskEnable6_SHIFT (10U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaMaskEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaMaskEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaMaskEnable6_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaTransEnable6_MASK (0x800U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaTransEnable6_SHIFT (11U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaTransEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_AlphaTransEnable6_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaSrcEnable6_MASK (0x1000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaSrcEnable6_SHIFT (12U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaSrcEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaSrcEnable6_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaConstEnable6_MASK (0x2000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaConstEnable6_SHIFT (13U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaConstEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaConstEnable6_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaMaskEnable6_MASK (0x4000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaMaskEnable6_SHIFT (14U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaMaskEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaMaskEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaMaskEnable6_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaTransEnable6_MASK (0x8000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaTransEnable6_SHIFT (15U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaTransEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_RGBAlphaTransEnable6_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_PremulConstRGB6_MASK (0x10000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_PremulConstRGB6_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_PremulConstRGB6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_PremulConstRGB6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_PremulConstRGB6_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_YUVConversionMode6_MASK (0x60000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_YUVConversionMode6_SHIFT (17U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_YUVConversionMode6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_YUVConversionMode6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_YUVConversionMode6_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_GammaRemoveEnable6_MASK (0x100000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_GammaRemoveEnable6_SHIFT (20U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_GammaRemoveEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_GammaRemoveEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_GammaRemoveEnable6_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_ClipWindowEnable6_MASK (0x40000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_ClipWindowEnable6_SHIFT (30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_ClipWindowEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_ClipWindowEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_ClipWindowEnable6_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_SourceBufferEnable6_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_SourceBufferEnable6_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_SourceBufferEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_SourceBufferEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY6_SourceBufferEnable6_MASK)

/*! @name FETCHWARP2_BASEADDRESS7 - Source buffer base address of layer 7. */
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS7_BaseAddress7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS7_BaseAddress7_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_BASEADDRESS7_BaseAddress7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BASEADDRESS7_BaseAddress7_SHIFT)) & IRIS_MVPL_FETCHWARP2_BASEADDRESS7_BaseAddress7_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERATTRIBUTES7 - Source buffer stride for layer 7. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_Stride7_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_Stride7_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_Stride7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_Stride7_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_Stride7_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_MASK)

/*! @name FETCHWARP2_SOURCEBUFFERDIMENSION7 - Source buffer dimension of layer 7. */
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineWidth7_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineWidth7_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineWidth7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineWidth7_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineWidth7_MASK)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineCount7_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineCount7_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineCount7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineCount7_SHIFT)) & IRIS_MVPL_FETCHWARP2_SOURCEBUFFERDIMENSION7_LineCount7_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTBITS7 - Size of color components for RGB, YUV and index formats (layer 7). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsAlpha7_MASK (0xFU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsAlpha7_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsAlpha7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsAlpha7_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsBlue7_MASK (0xF00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsBlue7_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsBlue7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsBlue7_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsGreen7_MASK (0xF0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsGreen7_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsGreen7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsGreen7_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsRed7_MASK (0xF000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsRed7_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsRed7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ComponentBitsRed7_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ITUFormat7_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ITUFormat7_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ITUFormat7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ITUFormat7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTBITS7_ITUFormat7_MASK)

/*! @name FETCHWARP2_COLORCOMPONENTSHIFT7 - Bit position of color components for RGB, YUV and index formats (layer 7). */
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_MASK (0x1FU)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_MASK (0x1F00U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_MASK)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftRed7_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftRed7_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftRed7_SHIFT)) & IRIS_MVPL_FETCHWARP2_COLORCOMPONENTSHIFT7_ComponentShiftRed7_MASK)

/*! @name FETCHWARP2_LAYEROFFSET7 - Position of layer 7 within the destination frame. */
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerXOffset7_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerXOffset7_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerXOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerXOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerXOffset7_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerYOffset7_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerYOffset7_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerYOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerYOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYEROFFSET7_LayerYOffset7_MASK)

/*! @name FETCHWARP2_CLIPWINDOWOFFSET7 - Clip window position for layer 7. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowXOffset7_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowXOffset7_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowXOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowXOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowXOffset7_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowYOffset7_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowYOffset7_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowYOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowYOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWOFFSET7_ClipWindowYOffset7_MASK)

/*! @name FETCHWARP2_CLIPWINDOWDIMENSIONS7 - Clip window size for layer 7. */
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_MASK)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_MASK)

/*! @name FETCHWARP2_CONSTANTCOLOR7 - Constant color for layer 7. */
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantAlpha7_MASK (0xFFU)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantAlpha7_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantAlpha7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantAlpha7_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantBlue7_MASK (0xFF00U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantBlue7_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantBlue7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantBlue7_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantGreen7_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantGreen7_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantGreen7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantGreen7_MASK)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantRed7_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantRed7_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantRed7_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONSTANTCOLOR7_ConstantRed7_MASK)

/*! @name FETCHWARP2_LAYERPROPERTY7 - Common properties of layer 7. */
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_TileMode7_MASK (0x30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_TileMode7_SHIFT (4U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_TileMode7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_TileMode7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_TileMode7_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaSrcEnable7_MASK (0x100U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaSrcEnable7_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaSrcEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaSrcEnable7_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaConstEnable7_MASK (0x200U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaConstEnable7_SHIFT (9U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaConstEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaConstEnable7_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaMaskEnable7_MASK (0x400U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaMaskEnable7_SHIFT (10U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaMaskEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaMaskEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaMaskEnable7_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaTransEnable7_MASK (0x800U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaTransEnable7_SHIFT (11U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaTransEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_AlphaTransEnable7_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaSrcEnable7_MASK (0x1000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaSrcEnable7_SHIFT (12U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaSrcEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaSrcEnable7_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaConstEnable7_MASK (0x2000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaConstEnable7_SHIFT (13U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaConstEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaConstEnable7_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaMaskEnable7_MASK (0x4000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaMaskEnable7_SHIFT (14U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaMaskEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaMaskEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaMaskEnable7_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaTransEnable7_MASK (0x8000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaTransEnable7_SHIFT (15U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaTransEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_RGBAlphaTransEnable7_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_PremulConstRGB7_MASK (0x10000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_PremulConstRGB7_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_PremulConstRGB7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_PremulConstRGB7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_PremulConstRGB7_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_YUVConversionMode7_MASK (0x60000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_YUVConversionMode7_SHIFT (17U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_YUVConversionMode7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_YUVConversionMode7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_YUVConversionMode7_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_GammaRemoveEnable7_MASK (0x100000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_GammaRemoveEnable7_SHIFT (20U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_GammaRemoveEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_GammaRemoveEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_GammaRemoveEnable7_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_ClipWindowEnable7_MASK (0x40000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_ClipWindowEnable7_SHIFT (30U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_ClipWindowEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_ClipWindowEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_ClipWindowEnable7_MASK)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_SourceBufferEnable7_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_SourceBufferEnable7_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_SourceBufferEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_SourceBufferEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP2_LAYERPROPERTY7_SourceBufferEnable7_MASK)

/*! @name FETCHWARP2_FRAMEDIMENSIONS - Output frame dimension. */
#define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name FETCHWARP2_FRAMERESAMPLING - Resampling options for output frame. */
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartX_MASK (0x3FU)
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartX_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartX_MASK)
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartY_MASK (0xFC0U)
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartY_SHIFT (6U)
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_StartY_MASK)
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaX_SHIFT (12U)
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaX_MASK)
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaY_SHIFT (18U)
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_DeltaY_MASK)
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHWARP2_FRAMERESAMPLING_SwapDirection_MASK)

/*! @name FETCHWARP2_WARPCONTROL - Warping control options. */
#define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpBitsPerPixel_MASK (0x3FU)
#define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpBitsPerPixel_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpBitsPerPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpBitsPerPixel_SHIFT)) & IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpBitsPerPixel_MASK)
#define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpCoordinateMode_MASK (0x300U)
#define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpCoordinateMode_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpCoordinateMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpCoordinateMode_SHIFT)) & IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpCoordinateMode_MASK)
#define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpSymmetricOffset_MASK (0x1000U)
#define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpSymmetricOffset_SHIFT (12U)
#define IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpSymmetricOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpSymmetricOffset_SHIFT)) & IRIS_MVPL_FETCHWARP2_WARPCONTROL_WarpSymmetricOffset_MASK)

/*! @name FETCHWARP2_ARBSTARTX - Start value X for arbitrary warping. */
#define IRIS_MVPL_FETCHWARP2_ARBSTARTX_ArbStartX_MASK (0x1FFFFFU)
#define IRIS_MVPL_FETCHWARP2_ARBSTARTX_ArbStartX_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_ARBSTARTX_ArbStartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_ARBSTARTX_ArbStartX_SHIFT)) & IRIS_MVPL_FETCHWARP2_ARBSTARTX_ArbStartX_MASK)

/*! @name FETCHWARP2_ARBSTARTY - Start value Y for arbitrary warping. */
#define IRIS_MVPL_FETCHWARP2_ARBSTARTY_ArbStartY_MASK (0x1FFFFFU)
#define IRIS_MVPL_FETCHWARP2_ARBSTARTY_ArbStartY_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_ARBSTARTY_ArbStartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_ARBSTARTY_ArbStartY_SHIFT)) & IRIS_MVPL_FETCHWARP2_ARBSTARTY_ArbStartY_MASK)

/*! @name FETCHWARP2_ARBDELTA - Start values for delta incrementation of arbitrary warping. */
#define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXX_MASK (0xFFU)
#define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXX_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXX_SHIFT)) & IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXX_MASK)
#define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXY_MASK (0xFF00U)
#define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXY_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXY_SHIFT)) & IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaXY_MASK)
#define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYX_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYX_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYX_SHIFT)) & IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYX_MASK)
#define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYY_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYY_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYY_SHIFT)) & IRIS_MVPL_FETCHWARP2_ARBDELTA_ArbDeltaYY_MASK)

/*! @name FETCHWARP2_FIRPOSITIONS - FIR sequence control register. */
#define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR0Position_MASK (0xFU)
#define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR0Position_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR0Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR0Position_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR0Position_MASK)
#define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR1Position_MASK (0xF0U)
#define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR1Position_SHIFT (4U)
#define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR1Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR1Position_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR1Position_MASK)
#define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR2Position_MASK (0xF00U)
#define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR2Position_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR2Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR2Position_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR2Position_MASK)
#define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR3Position_MASK (0xF000U)
#define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR3Position_SHIFT (12U)
#define IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR3Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR3Position_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRPOSITIONS_FIR3Position_MASK)

/*! @name FETCHWARP2_FIRCOEFFICIENTS - FIR coefficients register. */
#define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR0Coefficient_MASK (0xFFU)
#define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR0Coefficient_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR0Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR0Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR0Coefficient_MASK)
#define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR1Coefficient_MASK (0xFF00U)
#define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR1Coefficient_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR1Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR1Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR1Coefficient_MASK)
#define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR2Coefficient_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR2Coefficient_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR2Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR2Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR2Coefficient_MASK)
#define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR3Coefficient_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR3Coefficient_SHIFT (24U)
#define IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR3Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR3Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP2_FIRCOEFFICIENTS_FIR3Coefficient_MASK)

/*! @name FETCHWARP2_CONTROL - Shared common control settings for all layers. */
#define IRIS_MVPL_FETCHWARP2_CONTROL_RasterMode_MASK (0x7U)
#define IRIS_MVPL_FETCHWARP2_CONTROL_RasterMode_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CONTROL_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONTROL_RasterMode_MASK)
#define IRIS_MVPL_FETCHWARP2_CONTROL_InputSelect_MASK (0x18U)
#define IRIS_MVPL_FETCHWARP2_CONTROL_InputSelect_SHIFT (3U)
#define IRIS_MVPL_FETCHWARP2_CONTROL_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONTROL_InputSelect_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONTROL_InputSelect_MASK)
#define IRIS_MVPL_FETCHWARP2_CONTROL_RawPixel_MASK (0x80U)
#define IRIS_MVPL_FETCHWARP2_CONTROL_RawPixel_SHIFT (7U)
#define IRIS_MVPL_FETCHWARP2_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONTROL_RawPixel_MASK)
#define IRIS_MVPL_FETCHWARP2_CONTROL_ClipColor_MASK (0x10000U)
#define IRIS_MVPL_FETCHWARP2_CONTROL_ClipColor_SHIFT (16U)
#define IRIS_MVPL_FETCHWARP2_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONTROL_ClipColor_MASK)
#define IRIS_MVPL_FETCHWARP2_CONTROL_ClipLayer_MASK (0xE0000U)
#define IRIS_MVPL_FETCHWARP2_CONTROL_ClipLayer_SHIFT (17U)
#define IRIS_MVPL_FETCHWARP2_CONTROL_ClipLayer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONTROL_ClipLayer_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONTROL_ClipLayer_MASK)
#define IRIS_MVPL_FETCHWARP2_CONTROL_FilterMode_MASK (0x700000U)
#define IRIS_MVPL_FETCHWARP2_CONTROL_FilterMode_SHIFT (20U)
#define IRIS_MVPL_FETCHWARP2_CONTROL_FilterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONTROL_FilterMode_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONTROL_FilterMode_MASK)

/*! @name FETCHWARP2_TRIGGERENABLE - Shadow load enable flags for all layers. */
#define IRIS_MVPL_FETCHWARP2_TRIGGERENABLE_ShdLdReq_MASK (0xFFU)
#define IRIS_MVPL_FETCHWARP2_TRIGGERENABLE_ShdLdReq_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_TRIGGERENABLE_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_TRIGGERENABLE_ShdLdReq_SHIFT)) & IRIS_MVPL_FETCHWARP2_TRIGGERENABLE_ShdLdReq_MASK)

/*! @name FETCHWARP2_CONTROLTRIGGER - Shadow load trigger. */
#define IRIS_MVPL_FETCHWARP2_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FETCHWARP2_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHWARP2_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name FETCHWARP2_START - Frame start trigger. */
#define IRIS_MVPL_FETCHWARP2_START_Start_MASK    (0x1U)
#define IRIS_MVPL_FETCHWARP2_START_Start_SHIFT   (0U)
#define IRIS_MVPL_FETCHWARP2_START_Start(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_START_Start_SHIFT)) & IRIS_MVPL_FETCHWARP2_START_Start_MASK)

/*! @name FETCHWARP2_FETCHTYPE - Fetch unit type. */
#define IRIS_MVPL_FETCHWARP2_FETCHTYPE_FetchType_MASK (0xFU)
#define IRIS_MVPL_FETCHWARP2_FETCHTYPE_FetchType_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHWARP2_FETCHTYPE_FetchType_MASK)

/*! @name FETCHWARP2_BURSTBUFFERPROPERTIES - Burst buffer properties. */
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHWARP2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)

/*! @name FETCHWARP2_STATUS - Status informations. */
#define IRIS_MVPL_FETCHWARP2_STATUS_WriteTimeout_MASK (0x1U)
#define IRIS_MVPL_FETCHWARP2_STATUS_WriteTimeout_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHWARP2_STATUS_WriteTimeout_MASK)
#define IRIS_MVPL_FETCHWARP2_STATUS_ReadTimeout_MASK (0x10U)
#define IRIS_MVPL_FETCHWARP2_STATUS_ReadTimeout_SHIFT (4U)
#define IRIS_MVPL_FETCHWARP2_STATUS_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_STATUS_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHWARP2_STATUS_ReadTimeout_MASK)

/*! @name FETCHWARP2_HIDDENSTATUS - Hidden status informations. */
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBusy_MASK)
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusRequest_MASK)
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_StatusComplete_MASK)
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHWARP2_HIDDENSTATUS_ShadowStatus_MASK)

/*! @name FETCHECO2_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FETCHECO2_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHECO2_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO2_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FETCHECO2_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FETCHECO2_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FETCHECO2_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO2_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FETCHECO2_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FETCHECO2_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FETCHECO2_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO2_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FETCHECO2_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FETCHECO2_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHECO2_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO2_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FETCHECO2_STATICCONTROL - Common static control options. */
#define IRIS_MVPL_FETCHECO2_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_FETCHECO2_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHECO2_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_FETCHECO2_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHECO2_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
#define IRIS_MVPL_FETCHECO2_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHECO2_STATICCONTROL_BaseAddressAutoUpdate_MASK)

/*! @name FETCHECO2_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHECO2_BURSTBUFFERMANAGEMENT_LineMode_MASK)

/*! @name FETCHECO2_BASEADDRESS0 - Source buffer base address of layer 0. */
#define IRIS_MVPL_FETCHECO2_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHECO2_BASEADDRESS0_BaseAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHECO2_BASEADDRESS0_BaseAddress0_MASK)

/*! @name FETCHECO2_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
#define IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
#define IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)

/*! @name FETCHECO2_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
#define IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
#define IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHECO2_SOURCEBUFFERDIMENSION0_LineCount0_MASK)

/*! @name FETCHECO2_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTBITS0_ITUFormat0_MASK)

/*! @name FETCHECO2_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHECO2_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)

/*! @name FETCHECO2_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
#define IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerXOffset0_MASK)
#define IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO2_LAYEROFFSET0_LayerYOffset0_MASK)

/*! @name FETCHECO2_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
#define IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
#define IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO2_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)

/*! @name FETCHECO2_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
#define IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
#define IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHECO2_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)

/*! @name FETCHECO2_CONSTANTCOLOR0 - Constant color for layer 0. */
#define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
#define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantAlpha0_MASK)
#define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
#define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantBlue0_MASK)
#define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantGreen0_MASK)
#define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHECO2_CONSTANTCOLOR0_ConstantRed0_MASK)

/*! @name FETCHECO2_LAYERPROPERTY0 - Common properties of layer 0. */
#define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_TileMode0_MASK (0x30U)
#define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_TileMode0_SHIFT (4U)
#define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_TileMode0_MASK)
#define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
#define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
#define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_ClipWindowEnable0_MASK)
#define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
#define IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHECO2_LAYERPROPERTY0_SourceBufferEnable0_MASK)

/*! @name FETCHECO2_FRAMEDIMENSIONS - Output frame dimension. */
#define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name FETCHECO2_FRAMERESAMPLING - Resampling options for output frame. */
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartX_MASK (0x3FU)
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartX_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartX_MASK)
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartY_MASK (0xFC0U)
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartY_SHIFT (6U)
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_StartY_MASK)
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaX_SHIFT (12U)
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaX_MASK)
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaY_SHIFT (18U)
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_DeltaY_MASK)
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
#define IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHECO2_FRAMERESAMPLING_SwapDirection_MASK)

/*! @name FETCHECO2_CONTROL - Shared common control settings for all layers. */
#define IRIS_MVPL_FETCHECO2_CONTROL_RawPixel_MASK (0x80U)
#define IRIS_MVPL_FETCHECO2_CONTROL_RawPixel_SHIFT (7U)
#define IRIS_MVPL_FETCHECO2_CONTROL_RawPixel(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHECO2_CONTROL_RawPixel_MASK)
#define IRIS_MVPL_FETCHECO2_CONTROL_ClipColor_MASK (0x10000U)
#define IRIS_MVPL_FETCHECO2_CONTROL_ClipColor_SHIFT (16U)
#define IRIS_MVPL_FETCHECO2_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHECO2_CONTROL_ClipColor_MASK)

/*! @name FETCHECO2_CONTROLTRIGGER - Shadow load trigger. */
#define IRIS_MVPL_FETCHECO2_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FETCHECO2_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHECO2_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name FETCHECO2_START - Frame start trigger. */
#define IRIS_MVPL_FETCHECO2_START_Start_MASK     (0x1U)
#define IRIS_MVPL_FETCHECO2_START_Start_SHIFT    (0U)
#define IRIS_MVPL_FETCHECO2_START_Start(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_START_Start_SHIFT)) & IRIS_MVPL_FETCHECO2_START_Start_MASK)

/*! @name FETCHECO2_FETCHTYPE - Fetch unit type. */
#define IRIS_MVPL_FETCHECO2_FETCHTYPE_FetchType_MASK (0xFU)
#define IRIS_MVPL_FETCHECO2_FETCHTYPE_FetchType_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHECO2_FETCHTYPE_FetchType_MASK)

/*! @name FETCHECO2_BURSTBUFFERPROPERTIES - Burst buffer properties. */
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
#define IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHECO2_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)

/*! @name FETCHECO2_HIDDENSTATUS - Hidden status informations. */
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBusy_MASK)
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusRequest_MASK)
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHECO2_HIDDENSTATUS_StatusComplete_MASK)
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHECO2_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHECO2_HIDDENSTATUS_ShadowStatus_MASK)

/*! @name FETCHDECODE0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FETCHDECODE0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FETCHDECODE0_STATICCONTROL - Common static control options. */
#define IRIS_MVPL_FETCHDECODE0_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE0_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHDECODE0_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_FETCHDECODE0_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHDECODE0_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE0_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHDECODE0_STATICCONTROL_BaseAddressAutoUpdate_MASK)

/*! @name FETCHDECODE0_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LineMode_MASK)

/*! @name FETCHDECODE0_RINGBUFSTARTADDR0 - Ring buffer setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE0_RINGBUFSTARTADDR0_RingBufStartAddr0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE0_RINGBUFSTARTADDR0_RingBufStartAddr0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_RINGBUFSTARTADDR0_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_RINGBUFSTARTADDR0_RingBufStartAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_RINGBUFSTARTADDR0_RingBufStartAddr0_MASK)

/*! @name FETCHDECODE0_RINGBUFWRAPADDR0 - Ring buffer setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE0_RINGBUFWRAPADDR0_RingBufWrapAddr0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE0_RINGBUFWRAPADDR0_RingBufWrapAddr0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_RINGBUFWRAPADDR0_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_RINGBUFWRAPADDR0_RingBufWrapAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_RINGBUFWRAPADDR0_RingBufWrapAddr0_MASK)

/*! @name FETCHDECODE0_FRAMEPROPERTIES0 - Frame property setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE0_FRAMEPROPERTIES0_FieldId0_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE0_FRAMEPROPERTIES0_FieldId0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_FRAMEPROPERTIES0_FieldId0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_FRAMEPROPERTIES0_FieldId0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_FRAMEPROPERTIES0_FieldId0_MASK)

/*! @name FETCHDECODE0_BASEADDRESS0 - Source buffer base address of layer 0. */
#define IRIS_MVPL_FETCHDECODE0_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE0_BASEADDRESS0_BaseAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_BASEADDRESS0_BaseAddress0_MASK)

/*! @name FETCHDECODE0_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)

/*! @name FETCHDECODE0_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LineCount0_MASK)

/*! @name FETCHDECODE0_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTBITS0_ITUFormat0_MASK)

/*! @name FETCHDECODE0_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)

/*! @name FETCHDECODE0_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
#define IRIS_MVPL_FETCHDECODE0_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHDECODE0_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYEROFFSET0_LayerXOffset0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHDECODE0_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE0_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYEROFFSET0_LayerYOffset0_MASK)

/*! @name FETCHDECODE0_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
#define IRIS_MVPL_FETCHDECODE0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHDECODE0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
#define IRIS_MVPL_FETCHDECODE0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHDECODE0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE0_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)

/*! @name FETCHDECODE0_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
#define IRIS_MVPL_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
#define IRIS_MVPL_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)

/*! @name FETCHDECODE0_CONSTANTCOLOR0 - Constant color for layer 0. */
#define IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
#define IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CONSTANTCOLOR0_ConstantRed0_MASK)

/*! @name FETCHDECODE0_LAYERPROPERTY0 - Common properties of layer 0. */
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_PaletteEnable0_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_PaletteEnable0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_PaletteEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_PaletteEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_TileMode0_MASK (0x30U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_TileMode0_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_TileMode0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaSrcEnable0_MASK (0x100U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaConstEnable0_MASK (0x200U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaConstEnable0_SHIFT (9U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaMaskEnable0_MASK (0x400U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT (10U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaMaskEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaTransEnable0_MASK (0x800U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaTransEnable0_SHIFT (11U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_AlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK (0x1000U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT (12U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK (0x2000U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT (13U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK (0x4000U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT (14U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK (0x8000U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT (15U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_PremulConstRGB0_MASK (0x10000U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_PremulConstRGB0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_PremulConstRGB0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_YUVConversionMode0_MASK (0x60000U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_YUVConversionMode0_SHIFT (17U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_YUVConversionMode0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_GammaRemoveEnable0_MASK (0x100000U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT (20U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_GammaRemoveEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_ClipWindowEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LAYERPROPERTY0_SourceBufferEnable0_MASK)

/*! @name FETCHDECODE0_FRAMEDIMENSIONS - Output frame dimension. */
#define IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHDECODE0_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name FETCHDECODE0_FRAMERESAMPLING - Resampling options for output frame. */
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_StartX_MASK (0x3FU)
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_StartX_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_StartX_MASK)
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_StartY_MASK (0xFC0U)
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_StartY_SHIFT (6U)
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_StartY_MASK)
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_DeltaX_SHIFT (12U)
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_DeltaX_MASK)
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_DeltaY_SHIFT (18U)
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_DeltaY_MASK)
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHDECODE0_FRAMERESAMPLING_SwapDirection_MASK)

/*! @name FETCHDECODE0_DECODECONTROL - Control options for RLAD decompression. */
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_CompressionMode_MASK (0x3U)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_CompressionMode_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_DECODECONTROL_CompressionMode_SHIFT)) & IRIS_MVPL_FETCHDECODE0_DECODECONTROL_CompressionMode_MASK)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADEndianness_MASK (0x8000U)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADEndianness_SHIFT (15U)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADEndianness(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADEndianness_SHIFT)) & IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADEndianness_MASK)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsRed_MASK (0xF0000U)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsRed_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsRed_SHIFT)) & IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsRed_MASK)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsGreen_MASK (0xF00000U)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsGreen_SHIFT (20U)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsGreen_SHIFT)) & IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsGreen_MASK)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsBlue_MASK (0xF000000U)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsBlue_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsBlue_SHIFT)) & IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsBlue_MASK)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsAlpha_MASK (0xF0000000U)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsAlpha_SHIFT (28U)
#define IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsAlpha_SHIFT)) & IRIS_MVPL_FETCHDECODE0_DECODECONTROL_RLADCompBitsAlpha_MASK)

/*! @name FETCHDECODE0_SOURCEBUFFERLENGTH - Source buffer length for compressed data. */
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERLENGTH_RLEWords_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERLENGTH_RLEWords_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERLENGTH_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERLENGTH_RLEWords_SHIFT)) & IRIS_MVPL_FETCHDECODE0_SOURCEBUFFERLENGTH_RLEWords_MASK)

/*! @name FETCHDECODE0_CONTROL - Shared common control settings for all layers. */
#define IRIS_MVPL_FETCHDECODE0_CONTROL_RasterMode_MASK (0x7U)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_RasterMode_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CONTROL_RasterMode_MASK)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_InputSelect_MASK (0x18U)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_InputSelect_SHIFT (3U)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CONTROL_InputSelect_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CONTROL_InputSelect_MASK)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_YUV422UpsamplingMode_MASK (0x20U)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_YUV422UpsamplingMode_SHIFT (5U)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CONTROL_YUV422UpsamplingMode_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CONTROL_YUV422UpsamplingMode_MASK)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_RawPixel_MASK (0x80U)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_RawPixel_SHIFT (7U)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CONTROL_RawPixel_MASK)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_PaletteIdxWidth_MASK (0x700U)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_PaletteIdxWidth_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CONTROL_PaletteIdxWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CONTROL_PaletteIdxWidth_MASK)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_ClipColor_MASK (0x10000U)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_ClipColor_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE0_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CONTROL_ClipColor_MASK)

/*! @name FETCHDECODE0_CONTROLTRIGGER - Shadow load trigger. */
#define IRIS_MVPL_FETCHDECODE0_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE0_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHDECODE0_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name FETCHDECODE0_START - Frame start trigger. */
#define IRIS_MVPL_FETCHDECODE0_START_Start_MASK  (0x1U)
#define IRIS_MVPL_FETCHDECODE0_START_Start_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_START_Start(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_START_Start_SHIFT)) & IRIS_MVPL_FETCHDECODE0_START_Start_MASK)

/*! @name FETCHDECODE0_FETCHTYPE - Fetch unit type. */
#define IRIS_MVPL_FETCHDECODE0_FETCHTYPE_FetchType_MASK (0xFU)
#define IRIS_MVPL_FETCHDECODE0_FETCHTYPE_FetchType_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHDECODE0_FETCHTYPE_FetchType_MASK)

/*! @name FETCHDECODE0_DECODERSTATUS - Status information of the RLAD decoder. */
#define IRIS_MVPL_FETCHDECODE0_DECODERSTATUS_BufferTooSmall_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE0_DECODERSTATUS_BufferTooSmall_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_DECODERSTATUS_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_DECODERSTATUS_BufferTooSmall_SHIFT)) & IRIS_MVPL_FETCHDECODE0_DECODERSTATUS_BufferTooSmall_MASK)
#define IRIS_MVPL_FETCHDECODE0_DECODERSTATUS_BufferTooLarge_MASK (0x2U)
#define IRIS_MVPL_FETCHDECODE0_DECODERSTATUS_BufferTooLarge_SHIFT (1U)
#define IRIS_MVPL_FETCHDECODE0_DECODERSTATUS_BufferTooLarge(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_DECODERSTATUS_BufferTooLarge_SHIFT)) & IRIS_MVPL_FETCHDECODE0_DECODERSTATUS_BufferTooLarge_MASK)

/*! @name FETCHDECODE0_READADDRESS0 - Ring buffer synchronization for layer 0. */
#define IRIS_MVPL_FETCHDECODE0_READADDRESS0_ReadAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE0_READADDRESS0_ReadAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_READADDRESS0_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_READADDRESS0_ReadAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE0_READADDRESS0_ReadAddress0_MASK)

/*! @name FETCHDECODE0_BURSTBUFFERPROPERTIES - Burst buffer properties. */
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)

/*! @name FETCHDECODE0_STATUS - Status informations. */
#define IRIS_MVPL_FETCHDECODE0_STATUS_WriteTimeout_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE0_STATUS_WriteTimeout_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE0_STATUS_WriteTimeout_MASK)
#define IRIS_MVPL_FETCHDECODE0_STATUS_ReadTimeout_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE0_STATUS_ReadTimeout_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE0_STATUS_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_STATUS_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE0_STATUS_ReadTimeout_MASK)

/*! @name FETCHDECODE0_HIDDENSTATUS - Hidden status informations. */
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusBusy_MASK)
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusRequest_MASK)
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_StatusComplete_MASK)
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE0_HIDDENSTATUS_ShadowStatus_MASK)

/*! @name FETCHDECODE0_COLORPALETTE - Color palette look up table. */
#define IRIS_MVPL_FETCHDECODE0_COLORPALETTE_ColorPalette_MASK (0xFFFFFFU)
#define IRIS_MVPL_FETCHDECODE0_COLORPALETTE_ColorPalette_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE0_COLORPALETTE_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_COLORPALETTE_ColorPalette_SHIFT)) & IRIS_MVPL_FETCHDECODE0_COLORPALETTE_ColorPalette_MASK)

/*! @name FETCHECO0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FETCHECO0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHECO0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO0_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FETCHECO0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FETCHECO0_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FETCHECO0_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO0_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FETCHECO0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FETCHECO0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FETCHECO0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO0_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FETCHECO0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FETCHECO0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHECO0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO0_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FETCHECO0_STATICCONTROL - Common static control options. */
#define IRIS_MVPL_FETCHECO0_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_FETCHECO0_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHECO0_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_FETCHECO0_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHECO0_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
#define IRIS_MVPL_FETCHECO0_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHECO0_STATICCONTROL_BaseAddressAutoUpdate_MASK)

/*! @name FETCHECO0_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHECO0_BURSTBUFFERMANAGEMENT_LineMode_MASK)

/*! @name FETCHECO0_BASEADDRESS0 - Source buffer base address of layer 0. */
#define IRIS_MVPL_FETCHECO0_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHECO0_BASEADDRESS0_BaseAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHECO0_BASEADDRESS0_BaseAddress0_MASK)

/*! @name FETCHECO0_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
#define IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
#define IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)

/*! @name FETCHECO0_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
#define IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
#define IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHECO0_SOURCEBUFFERDIMENSION0_LineCount0_MASK)

/*! @name FETCHECO0_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTBITS0_ITUFormat0_MASK)

/*! @name FETCHECO0_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHECO0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)

/*! @name FETCHECO0_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
#define IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerXOffset0_MASK)
#define IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO0_LAYEROFFSET0_LayerYOffset0_MASK)

/*! @name FETCHECO0_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
#define IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
#define IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)

/*! @name FETCHECO0_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
#define IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
#define IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHECO0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)

/*! @name FETCHECO0_CONSTANTCOLOR0 - Constant color for layer 0. */
#define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
#define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantAlpha0_MASK)
#define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
#define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantBlue0_MASK)
#define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantGreen0_MASK)
#define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHECO0_CONSTANTCOLOR0_ConstantRed0_MASK)

/*! @name FETCHECO0_LAYERPROPERTY0 - Common properties of layer 0. */
#define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_TileMode0_MASK (0x30U)
#define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_TileMode0_SHIFT (4U)
#define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_TileMode0_MASK)
#define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
#define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
#define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_ClipWindowEnable0_MASK)
#define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
#define IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHECO0_LAYERPROPERTY0_SourceBufferEnable0_MASK)

/*! @name FETCHECO0_FRAMEDIMENSIONS - Output frame dimension. */
#define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name FETCHECO0_FRAMERESAMPLING - Resampling options for output frame. */
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartX_MASK (0x3FU)
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartX_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartX_MASK)
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartY_MASK (0xFC0U)
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartY_SHIFT (6U)
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_StartY_MASK)
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaX_SHIFT (12U)
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaX_MASK)
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaY_SHIFT (18U)
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_DeltaY_MASK)
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
#define IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHECO0_FRAMERESAMPLING_SwapDirection_MASK)

/*! @name FETCHECO0_CONTROL - Shared common control settings for all layers. */
#define IRIS_MVPL_FETCHECO0_CONTROL_RawPixel_MASK (0x80U)
#define IRIS_MVPL_FETCHECO0_CONTROL_RawPixel_SHIFT (7U)
#define IRIS_MVPL_FETCHECO0_CONTROL_RawPixel(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHECO0_CONTROL_RawPixel_MASK)
#define IRIS_MVPL_FETCHECO0_CONTROL_ClipColor_MASK (0x10000U)
#define IRIS_MVPL_FETCHECO0_CONTROL_ClipColor_SHIFT (16U)
#define IRIS_MVPL_FETCHECO0_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHECO0_CONTROL_ClipColor_MASK)

/*! @name FETCHECO0_CONTROLTRIGGER - Shadow load trigger. */
#define IRIS_MVPL_FETCHECO0_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FETCHECO0_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHECO0_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name FETCHECO0_START - Frame start trigger. */
#define IRIS_MVPL_FETCHECO0_START_Start_MASK     (0x1U)
#define IRIS_MVPL_FETCHECO0_START_Start_SHIFT    (0U)
#define IRIS_MVPL_FETCHECO0_START_Start(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_START_Start_SHIFT)) & IRIS_MVPL_FETCHECO0_START_Start_MASK)

/*! @name FETCHECO0_FETCHTYPE - Fetch unit type. */
#define IRIS_MVPL_FETCHECO0_FETCHTYPE_FetchType_MASK (0xFU)
#define IRIS_MVPL_FETCHECO0_FETCHTYPE_FetchType_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHECO0_FETCHTYPE_FetchType_MASK)

/*! @name FETCHECO0_BURSTBUFFERPROPERTIES - Burst buffer properties. */
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
#define IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHECO0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)

/*! @name FETCHECO0_HIDDENSTATUS - Hidden status informations. */
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBusy_MASK)
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusRequest_MASK)
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHECO0_HIDDENSTATUS_StatusComplete_MASK)
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHECO0_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHECO0_HIDDENSTATUS_ShadowStatus_MASK)

/*! @name FETCHDECODE1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FETCHDECODE1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE1_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FETCHDECODE1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FETCHDECODE1_STATICCONTROL - Common static control options. */
#define IRIS_MVPL_FETCHDECODE1_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE1_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHDECODE1_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_FETCHDECODE1_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHDECODE1_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE1_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHDECODE1_STATICCONTROL_BaseAddressAutoUpdate_MASK)

/*! @name FETCHDECODE1_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LineMode_MASK)

/*! @name FETCHDECODE1_RINGBUFSTARTADDR0 - Ring buffer setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE1_RINGBUFSTARTADDR0_RingBufStartAddr0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE1_RINGBUFSTARTADDR0_RingBufStartAddr0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_RINGBUFSTARTADDR0_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_RINGBUFSTARTADDR0_RingBufStartAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_RINGBUFSTARTADDR0_RingBufStartAddr0_MASK)

/*! @name FETCHDECODE1_RINGBUFWRAPADDR0 - Ring buffer setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE1_RINGBUFWRAPADDR0_RingBufWrapAddr0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE1_RINGBUFWRAPADDR0_RingBufWrapAddr0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_RINGBUFWRAPADDR0_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_RINGBUFWRAPADDR0_RingBufWrapAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_RINGBUFWRAPADDR0_RingBufWrapAddr0_MASK)

/*! @name FETCHDECODE1_FRAMEPROPERTIES0 - Frame property setup for layer 0. */
#define IRIS_MVPL_FETCHDECODE1_FRAMEPROPERTIES0_FieldId0_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE1_FRAMEPROPERTIES0_FieldId0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_FRAMEPROPERTIES0_FieldId0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_FRAMEPROPERTIES0_FieldId0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_FRAMEPROPERTIES0_FieldId0_MASK)

/*! @name FETCHDECODE1_BASEADDRESS0 - Source buffer base address of layer 0. */
#define IRIS_MVPL_FETCHDECODE1_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE1_BASEADDRESS0_BaseAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_BASEADDRESS0_BaseAddress0_MASK)

/*! @name FETCHDECODE1_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)

/*! @name FETCHDECODE1_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LineCount0_MASK)

/*! @name FETCHDECODE1_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTBITS0_ITUFormat0_MASK)

/*! @name FETCHDECODE1_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)

/*! @name FETCHDECODE1_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
#define IRIS_MVPL_FETCHDECODE1_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHDECODE1_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYEROFFSET0_LayerXOffset0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHDECODE1_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE1_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYEROFFSET0_LayerYOffset0_MASK)

/*! @name FETCHDECODE1_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
#define IRIS_MVPL_FETCHDECODE1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHDECODE1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
#define IRIS_MVPL_FETCHDECODE1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHDECODE1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE1_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)

/*! @name FETCHDECODE1_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
#define IRIS_MVPL_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
#define IRIS_MVPL_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)

/*! @name FETCHDECODE1_CONSTANTCOLOR0 - Constant color for layer 0. */
#define IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantAlpha0_MASK)
#define IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
#define IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantBlue0_MASK)
#define IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantGreen0_MASK)
#define IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CONSTANTCOLOR0_ConstantRed0_MASK)

/*! @name FETCHDECODE1_LAYERPROPERTY0 - Common properties of layer 0. */
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_PaletteEnable0_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_PaletteEnable0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_PaletteEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_PaletteEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_TileMode0_MASK (0x30U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_TileMode0_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_TileMode0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaSrcEnable0_MASK (0x100U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaConstEnable0_MASK (0x200U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaConstEnable0_SHIFT (9U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaMaskEnable0_MASK (0x400U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT (10U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaMaskEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaTransEnable0_MASK (0x800U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaTransEnable0_SHIFT (11U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_AlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK (0x1000U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT (12U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK (0x2000U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT (13U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK (0x4000U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT (14U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK (0x8000U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT (15U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_PremulConstRGB0_MASK (0x10000U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_PremulConstRGB0_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_PremulConstRGB0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_YUVConversionMode0_MASK (0x60000U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_YUVConversionMode0_SHIFT (17U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_YUVConversionMode0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_GammaRemoveEnable0_MASK (0x100000U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT (20U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_GammaRemoveEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_ClipWindowEnable0_MASK)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_LAYERPROPERTY0_SourceBufferEnable0_MASK)

/*! @name FETCHDECODE1_FRAMEDIMENSIONS - Output frame dimension. */
#define IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHDECODE1_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name FETCHDECODE1_FRAMERESAMPLING - Resampling options for output frame. */
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_StartX_MASK (0x3FU)
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_StartX_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_StartX_MASK)
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_StartY_MASK (0xFC0U)
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_StartY_SHIFT (6U)
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_StartY_MASK)
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_DeltaX_SHIFT (12U)
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_DeltaX_MASK)
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_DeltaY_SHIFT (18U)
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_DeltaY_MASK)
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHDECODE1_FRAMERESAMPLING_SwapDirection_MASK)

/*! @name FETCHDECODE1_DECODECONTROL - Control options for RLAD decompression. */
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_CompressionMode_MASK (0x3U)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_CompressionMode_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_DECODECONTROL_CompressionMode_SHIFT)) & IRIS_MVPL_FETCHDECODE1_DECODECONTROL_CompressionMode_MASK)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADEndianness_MASK (0x8000U)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADEndianness_SHIFT (15U)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADEndianness(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADEndianness_SHIFT)) & IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADEndianness_MASK)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsRed_MASK (0xF0000U)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsRed_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsRed_SHIFT)) & IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsRed_MASK)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsGreen_MASK (0xF00000U)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsGreen_SHIFT (20U)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsGreen_SHIFT)) & IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsGreen_MASK)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsBlue_MASK (0xF000000U)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsBlue_SHIFT (24U)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsBlue_SHIFT)) & IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsBlue_MASK)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsAlpha_MASK (0xF0000000U)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsAlpha_SHIFT (28U)
#define IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsAlpha_SHIFT)) & IRIS_MVPL_FETCHDECODE1_DECODECONTROL_RLADCompBitsAlpha_MASK)

/*! @name FETCHDECODE1_SOURCEBUFFERLENGTH - Source buffer length for compressed data. */
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERLENGTH_RLEWords_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERLENGTH_RLEWords_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERLENGTH_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERLENGTH_RLEWords_SHIFT)) & IRIS_MVPL_FETCHDECODE1_SOURCEBUFFERLENGTH_RLEWords_MASK)

/*! @name FETCHDECODE1_CONTROL - Shared common control settings for all layers. */
#define IRIS_MVPL_FETCHDECODE1_CONTROL_RasterMode_MASK (0x7U)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_RasterMode_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CONTROL_RasterMode_MASK)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_InputSelect_MASK (0x18U)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_InputSelect_SHIFT (3U)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CONTROL_InputSelect_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CONTROL_InputSelect_MASK)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_YUV422UpsamplingMode_MASK (0x20U)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_YUV422UpsamplingMode_SHIFT (5U)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CONTROL_YUV422UpsamplingMode_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CONTROL_YUV422UpsamplingMode_MASK)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_RawPixel_MASK (0x80U)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_RawPixel_SHIFT (7U)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CONTROL_RawPixel_MASK)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_PaletteIdxWidth_MASK (0x700U)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_PaletteIdxWidth_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CONTROL_PaletteIdxWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CONTROL_PaletteIdxWidth_MASK)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_ClipColor_MASK (0x10000U)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_ClipColor_SHIFT (16U)
#define IRIS_MVPL_FETCHDECODE1_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CONTROL_ClipColor_MASK)

/*! @name FETCHDECODE1_CONTROLTRIGGER - Shadow load trigger. */
#define IRIS_MVPL_FETCHDECODE1_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE1_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHDECODE1_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name FETCHDECODE1_START - Frame start trigger. */
#define IRIS_MVPL_FETCHDECODE1_START_Start_MASK  (0x1U)
#define IRIS_MVPL_FETCHDECODE1_START_Start_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_START_Start(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_START_Start_SHIFT)) & IRIS_MVPL_FETCHDECODE1_START_Start_MASK)

/*! @name FETCHDECODE1_FETCHTYPE - Fetch unit type. */
#define IRIS_MVPL_FETCHDECODE1_FETCHTYPE_FetchType_MASK (0xFU)
#define IRIS_MVPL_FETCHDECODE1_FETCHTYPE_FetchType_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHDECODE1_FETCHTYPE_FetchType_MASK)

/*! @name FETCHDECODE1_DECODERSTATUS - Status information of the RLAD decoder. */
#define IRIS_MVPL_FETCHDECODE1_DECODERSTATUS_BufferTooSmall_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE1_DECODERSTATUS_BufferTooSmall_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_DECODERSTATUS_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_DECODERSTATUS_BufferTooSmall_SHIFT)) & IRIS_MVPL_FETCHDECODE1_DECODERSTATUS_BufferTooSmall_MASK)
#define IRIS_MVPL_FETCHDECODE1_DECODERSTATUS_BufferTooLarge_MASK (0x2U)
#define IRIS_MVPL_FETCHDECODE1_DECODERSTATUS_BufferTooLarge_SHIFT (1U)
#define IRIS_MVPL_FETCHDECODE1_DECODERSTATUS_BufferTooLarge(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_DECODERSTATUS_BufferTooLarge_SHIFT)) & IRIS_MVPL_FETCHDECODE1_DECODERSTATUS_BufferTooLarge_MASK)

/*! @name FETCHDECODE1_READADDRESS0 - Ring buffer synchronization for layer 0. */
#define IRIS_MVPL_FETCHDECODE1_READADDRESS0_ReadAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHDECODE1_READADDRESS0_ReadAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_READADDRESS0_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_READADDRESS0_ReadAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE1_READADDRESS0_ReadAddress0_MASK)

/*! @name FETCHDECODE1_BURSTBUFFERPROPERTIES - Burst buffer properties. */
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)

/*! @name FETCHDECODE1_STATUS - Status informations. */
#define IRIS_MVPL_FETCHDECODE1_STATUS_WriteTimeout_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE1_STATUS_WriteTimeout_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE1_STATUS_WriteTimeout_MASK)
#define IRIS_MVPL_FETCHDECODE1_STATUS_ReadTimeout_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE1_STATUS_ReadTimeout_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE1_STATUS_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_STATUS_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE1_STATUS_ReadTimeout_MASK)

/*! @name FETCHDECODE1_HIDDENSTATUS - Hidden status informations. */
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusBusy_MASK)
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusRequest_MASK)
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_StatusComplete_MASK)
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE1_HIDDENSTATUS_ShadowStatus_MASK)

/*! @name FETCHDECODE1_COLORPALETTE - Color palette look up table. */
#define IRIS_MVPL_FETCHDECODE1_COLORPALETTE_ColorPalette_MASK (0xFFFFFFU)
#define IRIS_MVPL_FETCHDECODE1_COLORPALETTE_ColorPalette_SHIFT (0U)
#define IRIS_MVPL_FETCHDECODE1_COLORPALETTE_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_COLORPALETTE_ColorPalette_SHIFT)) & IRIS_MVPL_FETCHDECODE1_COLORPALETTE_ColorPalette_MASK)

/*! @name FETCHECO1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FETCHECO1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHECO1_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO1_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FETCHECO1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FETCHECO1_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FETCHECO1_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO1_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FETCHECO1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FETCHECO1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FETCHECO1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO1_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FETCHECO1_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FETCHECO1_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHECO1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO1_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FETCHECO1_STATICCONTROL - Common static control options. */
#define IRIS_MVPL_FETCHECO1_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_FETCHECO1_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHECO1_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_FETCHECO1_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHECO1_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
#define IRIS_MVPL_FETCHECO1_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHECO1_STATICCONTROL_BaseAddressAutoUpdate_MASK)

/*! @name FETCHECO1_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHECO1_BURSTBUFFERMANAGEMENT_LineMode_MASK)

/*! @name FETCHECO1_BASEADDRESS0 - Source buffer base address of layer 0. */
#define IRIS_MVPL_FETCHECO1_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHECO1_BASEADDRESS0_BaseAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHECO1_BASEADDRESS0_BaseAddress0_MASK)

/*! @name FETCHECO1_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
#define IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
#define IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)

/*! @name FETCHECO1_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
#define IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
#define IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHECO1_SOURCEBUFFERDIMENSION0_LineCount0_MASK)

/*! @name FETCHECO1_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTBITS0_ITUFormat0_MASK)

/*! @name FETCHECO1_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHECO1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)

/*! @name FETCHECO1_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
#define IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerXOffset0_MASK)
#define IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO1_LAYEROFFSET0_LayerYOffset0_MASK)

/*! @name FETCHECO1_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
#define IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
#define IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)

/*! @name FETCHECO1_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
#define IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
#define IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHECO1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)

/*! @name FETCHECO1_CONSTANTCOLOR0 - Constant color for layer 0. */
#define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
#define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantAlpha0_MASK)
#define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
#define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantBlue0_MASK)
#define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantGreen0_MASK)
#define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHECO1_CONSTANTCOLOR0_ConstantRed0_MASK)

/*! @name FETCHECO1_LAYERPROPERTY0 - Common properties of layer 0. */
#define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_TileMode0_MASK (0x30U)
#define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_TileMode0_SHIFT (4U)
#define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_TileMode0_MASK)
#define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
#define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
#define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_ClipWindowEnable0_MASK)
#define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
#define IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHECO1_LAYERPROPERTY0_SourceBufferEnable0_MASK)

/*! @name FETCHECO1_FRAMEDIMENSIONS - Output frame dimension. */
#define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name FETCHECO1_FRAMERESAMPLING - Resampling options for output frame. */
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartX_MASK (0x3FU)
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartX_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartX_MASK)
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartY_MASK (0xFC0U)
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartY_SHIFT (6U)
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_StartY_MASK)
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaX_SHIFT (12U)
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaX_MASK)
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaY_SHIFT (18U)
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_DeltaY_MASK)
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
#define IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHECO1_FRAMERESAMPLING_SwapDirection_MASK)

/*! @name FETCHECO1_CONTROL - Shared common control settings for all layers. */
#define IRIS_MVPL_FETCHECO1_CONTROL_RawPixel_MASK (0x80U)
#define IRIS_MVPL_FETCHECO1_CONTROL_RawPixel_SHIFT (7U)
#define IRIS_MVPL_FETCHECO1_CONTROL_RawPixel(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHECO1_CONTROL_RawPixel_MASK)
#define IRIS_MVPL_FETCHECO1_CONTROL_ClipColor_MASK (0x10000U)
#define IRIS_MVPL_FETCHECO1_CONTROL_ClipColor_SHIFT (16U)
#define IRIS_MVPL_FETCHECO1_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHECO1_CONTROL_ClipColor_MASK)

/*! @name FETCHECO1_CONTROLTRIGGER - Shadow load trigger. */
#define IRIS_MVPL_FETCHECO1_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FETCHECO1_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHECO1_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name FETCHECO1_START - Frame start trigger. */
#define IRIS_MVPL_FETCHECO1_START_Start_MASK     (0x1U)
#define IRIS_MVPL_FETCHECO1_START_Start_SHIFT    (0U)
#define IRIS_MVPL_FETCHECO1_START_Start(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_START_Start_SHIFT)) & IRIS_MVPL_FETCHECO1_START_Start_MASK)

/*! @name FETCHECO1_FETCHTYPE - Fetch unit type. */
#define IRIS_MVPL_FETCHECO1_FETCHTYPE_FetchType_MASK (0xFU)
#define IRIS_MVPL_FETCHECO1_FETCHTYPE_FetchType_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHECO1_FETCHTYPE_FetchType_MASK)

/*! @name FETCHECO1_BURSTBUFFERPROPERTIES - Burst buffer properties. */
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
#define IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHECO1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)

/*! @name FETCHECO1_HIDDENSTATUS - Hidden status informations. */
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBusy_MASK)
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusRequest_MASK)
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHECO1_HIDDENSTATUS_StatusComplete_MASK)
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHECO1_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHECO1_HIDDENSTATUS_ShadowStatus_MASK)

/*! @name FETCHLAYER0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FETCHLAYER0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FETCHLAYER0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FETCHLAYER0_STATICCONTROL - Common static control options. */
#define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHLAYER0_STATICCONTROL_BaseAddressAutoUpdate_MASK)
#define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdLdReqSticky_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdLdReqSticky_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdLdReqSticky(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdLdReqSticky_SHIFT)) & IRIS_MVPL_FETCHLAYER0_STATICCONTROL_ShdLdReqSticky_MASK)

/*! @name FETCHLAYER0_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LineMode_MASK)

/*! @name FETCHLAYER0_BASEADDRESS0 - Source buffer base address of layer 0. */
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS0_BaseAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS0_BaseAddress0_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LineCount0_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFormat0_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)

/*! @name FETCHLAYER0_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerXOffset0_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET0_LayerYOffset0_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)

/*! @name FETCHLAYER0_CONSTANTCOLOR0 - Constant color for layer 0. */
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantAlpha0_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantBlue0_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantGreen0_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR0_ConstantRed0_MASK)

/*! @name FETCHLAYER0_LAYERPROPERTY0 - Common properties of layer 0. */
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PaletteEnable0_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PaletteEnable0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PaletteEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PaletteEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_TileMode0_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_TileMode0_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_TileMode0_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaSrcEnable0_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaConstEnable0_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaConstEnable0_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaTransEnable0_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaTransEnable0_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_AlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PremulConstRGB0_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PremulConstRGB0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_PremulConstRGB0_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_YUVConversionMode0_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_YUVConversionMode0_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_YUVConversionMode0_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_GammaRemoveEnable0_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_GammaRemoveEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_ClipWindowEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY0_SourceBufferEnable0_MASK)

/*! @name FETCHLAYER0_BASEADDRESS1 - Source buffer base address of layer 1. */
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS1_BaseAddress1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS1_BaseAddress1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS1_BaseAddress1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS1_BaseAddress1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS1_BaseAddress1_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES1 - Source buffer attributes for layer 1. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_Stride1_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_Stride1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_Stride1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_Stride1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_Stride1_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION1 - Source buffer dimensions of layer 1, */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineWidth1_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineWidth1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineWidth1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineWidth1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineWidth1_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineCount1_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineCount1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineCount1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineCount1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LineCount1_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTBITS1 - Size of color components for RGB, YUV and index formats (layer 1). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsAlpha1_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsAlpha1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsAlpha1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsAlpha1_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsBlue1_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsBlue1_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsBlue1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsBlue1_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsGreen1_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsGreen1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsGreen1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsGreen1_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsRed1_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsRed1_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsRed1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ComponentBitsRed1_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFormat1_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFormat1_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFormat1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFormat1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFormat1_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTSHIFT1 - Bit position of color components for RGB, YUV and index formats (layer 1). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftRed1_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftRed1_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftRed1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT1_ComponentShiftRed1_MASK)

/*! @name FETCHLAYER0_LAYEROFFSET1 - Position of layer 1 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerXOffset1_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerXOffset1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerXOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerXOffset1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerXOffset1_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerYOffset1_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerYOffset1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerYOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerYOffset1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET1_LayerYOffset1_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWOFFSET1 - Clip window position for layer 1. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowXOffset1_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowXOffset1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowXOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowXOffset1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowXOffset1_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowYOffset1_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowYOffset1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowYOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowYOffset1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET1_ClipWindowYOffset1_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS1 - Clip window size for layer 1. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_MASK)

/*! @name FETCHLAYER0_CONSTANTCOLOR1 - Constant color for layer 1. */
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantAlpha1_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantAlpha1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantAlpha1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantAlpha1_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantBlue1_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantBlue1_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantBlue1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantBlue1_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantGreen1_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantGreen1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantGreen1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantGreen1_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantRed1_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantRed1_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantRed1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR1_ConstantRed1_MASK)

/*! @name FETCHLAYER0_LAYERPROPERTY1 - Common properties of layer 1. */
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PaletteEnable1_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PaletteEnable1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PaletteEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PaletteEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PaletteEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_TileMode1_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_TileMode1_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_TileMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_TileMode1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_TileMode1_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaSrcEnable1_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaSrcEnable1_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaSrcEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaSrcEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaConstEnable1_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaConstEnable1_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaConstEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaConstEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaTransEnable1_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaTransEnable1_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaTransEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_AlphaTransEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaSrcEnable1_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaSrcEnable1_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaSrcEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaSrcEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaConstEnable1_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaConstEnable1_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaConstEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaConstEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaTransEnable1_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaTransEnable1_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaTransEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_RGBAlphaTransEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PremulConstRGB1_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PremulConstRGB1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PremulConstRGB1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PremulConstRGB1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_PremulConstRGB1_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_YUVConversionMode1_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_YUVConversionMode1_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_YUVConversionMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_YUVConversionMode1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_YUVConversionMode1_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_GammaRemoveEnable1_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_GammaRemoveEnable1_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_GammaRemoveEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_GammaRemoveEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_GammaRemoveEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_ClipWindowEnable1_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_ClipWindowEnable1_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_ClipWindowEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_ClipWindowEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_ClipWindowEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_SourceBufferEnable1_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_SourceBufferEnable1_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_SourceBufferEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_SourceBufferEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY1_SourceBufferEnable1_MASK)

/*! @name FETCHLAYER0_BASEADDRESS2 - Source buffer base address of layer 2. */
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS2_BaseAddress2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS2_BaseAddress2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS2_BaseAddress2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS2_BaseAddress2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS2_BaseAddress2_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES2 - Source buffer attributes for layer 2. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_Stride2_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_Stride2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_Stride2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_Stride2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_Stride2_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION2 - Source buffer dimension of layer 2. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineWidth2_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineWidth2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineWidth2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineWidth2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineWidth2_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineCount2_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineCount2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineCount2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineCount2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LineCount2_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTBITS2 - Size of color components for RGB, YUV and index formats (layer 2). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsAlpha2_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsAlpha2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsAlpha2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsAlpha2_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsBlue2_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsBlue2_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsBlue2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsBlue2_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsGreen2_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsGreen2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsGreen2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsGreen2_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsRed2_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsRed2_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsRed2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ComponentBitsRed2_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFormat2_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFormat2_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFormat2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFormat2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFormat2_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTSHIFT2 - Bit position of color components for RGB, YUV and index formats (layer 2). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftRed2_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftRed2_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftRed2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT2_ComponentShiftRed2_MASK)

/*! @name FETCHLAYER0_LAYEROFFSET2 - Position of layer 2 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerXOffset2_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerXOffset2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerXOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerXOffset2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerXOffset2_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerYOffset2_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerYOffset2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerYOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerYOffset2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET2_LayerYOffset2_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWOFFSET2 - Clip window position for layer 2. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowXOffset2_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowXOffset2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowXOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowXOffset2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowXOffset2_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowYOffset2_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowYOffset2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowYOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowYOffset2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET2_ClipWindowYOffset2_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS2 - Clip window size for layer 2. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_MASK)

/*! @name FETCHLAYER0_CONSTANTCOLOR2 - Constant color for layer 2. */
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantAlpha2_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantAlpha2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantAlpha2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantAlpha2_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantBlue2_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantBlue2_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantBlue2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantBlue2_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantGreen2_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantGreen2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantGreen2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantGreen2_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantRed2_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantRed2_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantRed2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR2_ConstantRed2_MASK)

/*! @name FETCHLAYER0_LAYERPROPERTY2 - Common properties of layer 2. */
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PaletteEnable2_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PaletteEnable2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PaletteEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PaletteEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PaletteEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_TileMode2_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_TileMode2_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_TileMode2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_TileMode2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_TileMode2_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaSrcEnable2_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaSrcEnable2_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaSrcEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaSrcEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaConstEnable2_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaConstEnable2_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaConstEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaConstEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaTransEnable2_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaTransEnable2_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaTransEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_AlphaTransEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaSrcEnable2_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaSrcEnable2_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaSrcEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaSrcEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaConstEnable2_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaConstEnable2_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaConstEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaConstEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaTransEnable2_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaTransEnable2_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaTransEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_RGBAlphaTransEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PremulConstRGB2_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PremulConstRGB2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PremulConstRGB2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PremulConstRGB2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_PremulConstRGB2_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_YUVConversionMode2_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_YUVConversionMode2_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_YUVConversionMode2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_YUVConversionMode2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_YUVConversionMode2_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_GammaRemoveEnable2_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_GammaRemoveEnable2_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_GammaRemoveEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_GammaRemoveEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_GammaRemoveEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_ClipWindowEnable2_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_ClipWindowEnable2_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_ClipWindowEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_ClipWindowEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_ClipWindowEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_SourceBufferEnable2_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_SourceBufferEnable2_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_SourceBufferEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_SourceBufferEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY2_SourceBufferEnable2_MASK)

/*! @name FETCHLAYER0_BASEADDRESS3 - Source buffer base address of layer 3. */
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS3_BaseAddress3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS3_BaseAddress3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS3_BaseAddress3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS3_BaseAddress3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS3_BaseAddress3_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES3 - Source buffer attributes for layer 3. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_Stride3_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_Stride3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_Stride3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_Stride3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_Stride3_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION3 - Source buffer dimension of layer 3. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineWidth3_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineWidth3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineWidth3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineWidth3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineWidth3_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineCount3_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineCount3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineCount3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineCount3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LineCount3_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTBITS3 - Size of color components for RGB, YUV and index formats (layer 3). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsAlpha3_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsAlpha3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsAlpha3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsAlpha3_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsBlue3_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsBlue3_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsBlue3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsBlue3_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsGreen3_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsGreen3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsGreen3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsGreen3_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsRed3_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsRed3_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsRed3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ComponentBitsRed3_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFormat3_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFormat3_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFormat3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFormat3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFormat3_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTSHIFT3 - Bit position of color components for RGB, YUV and index formats (layer 3). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftRed3_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftRed3_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftRed3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT3_ComponentShiftRed3_MASK)

/*! @name FETCHLAYER0_LAYEROFFSET3 - Position of layer 3 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerXOffset3_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerXOffset3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerXOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerXOffset3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerXOffset3_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerYOffset3_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerYOffset3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerYOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerYOffset3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET3_LayerYOffset3_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWOFFSET3 - Clip window position for layer 3. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowXOffset3_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowXOffset3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowXOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowXOffset3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowXOffset3_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowYOffset3_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowYOffset3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowYOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowYOffset3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET3_ClipWindowYOffset3_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS3 - Clip window size for layer 3. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_MASK)

/*! @name FETCHLAYER0_CONSTANTCOLOR3 - Constant color for layer 3. */
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantAlpha3_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantAlpha3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantAlpha3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantAlpha3_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantBlue3_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantBlue3_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantBlue3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantBlue3_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantGreen3_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantGreen3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantGreen3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantGreen3_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantRed3_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantRed3_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantRed3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR3_ConstantRed3_MASK)

/*! @name FETCHLAYER0_LAYERPROPERTY3 - Common properties of layer 3. */
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PaletteEnable3_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PaletteEnable3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PaletteEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PaletteEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PaletteEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_TileMode3_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_TileMode3_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_TileMode3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_TileMode3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_TileMode3_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaSrcEnable3_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaSrcEnable3_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaSrcEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaSrcEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaConstEnable3_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaConstEnable3_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaConstEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaConstEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaTransEnable3_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaTransEnable3_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaTransEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_AlphaTransEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaSrcEnable3_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaSrcEnable3_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaSrcEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaSrcEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaConstEnable3_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaConstEnable3_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaConstEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaConstEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaTransEnable3_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaTransEnable3_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaTransEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_RGBAlphaTransEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PremulConstRGB3_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PremulConstRGB3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PremulConstRGB3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PremulConstRGB3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_PremulConstRGB3_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_YUVConversionMode3_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_YUVConversionMode3_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_YUVConversionMode3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_YUVConversionMode3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_YUVConversionMode3_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_GammaRemoveEnable3_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_GammaRemoveEnable3_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_GammaRemoveEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_GammaRemoveEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_GammaRemoveEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_ClipWindowEnable3_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_ClipWindowEnable3_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_ClipWindowEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_ClipWindowEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_ClipWindowEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_SourceBufferEnable3_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_SourceBufferEnable3_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_SourceBufferEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_SourceBufferEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY3_SourceBufferEnable3_MASK)

/*! @name FETCHLAYER0_BASEADDRESS4 - Source buffer base address of layer 4. */
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS4_BaseAddress4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS4_BaseAddress4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS4_BaseAddress4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS4_BaseAddress4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS4_BaseAddress4_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES4 - Source buffer attributes for layer 4. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_Stride4_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_Stride4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_Stride4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_Stride4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_Stride4_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION4 - Source buffer dimension of layer 4. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineWidth4_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineWidth4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineWidth4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineWidth4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineWidth4_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineCount4_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineCount4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineCount4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineCount4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LineCount4_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTBITS4 - Size of color components for RGB, YUV and index formats (layer 4). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsAlpha4_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsAlpha4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsAlpha4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsAlpha4_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsBlue4_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsBlue4_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsBlue4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsBlue4_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsGreen4_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsGreen4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsGreen4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsGreen4_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsRed4_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsRed4_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsRed4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ComponentBitsRed4_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFormat4_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFormat4_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFormat4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFormat4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFormat4_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTSHIFT4 - Bit position of color components for RGB, YUV and index formats (layer 4). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftRed4_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftRed4_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftRed4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT4_ComponentShiftRed4_MASK)

/*! @name FETCHLAYER0_LAYEROFFSET4 - Position of layer 4 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerXOffset4_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerXOffset4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerXOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerXOffset4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerXOffset4_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerYOffset4_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerYOffset4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerYOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerYOffset4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET4_LayerYOffset4_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWOFFSET4 - Clip window position for layer 4. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowXOffset4_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowXOffset4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowXOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowXOffset4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowXOffset4_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowYOffset4_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowYOffset4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowYOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowYOffset4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET4_ClipWindowYOffset4_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS4 - Clip window size for layer 4. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_MASK)

/*! @name FETCHLAYER0_CONSTANTCOLOR4 - Constant color for layer 4. */
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantAlpha4_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantAlpha4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantAlpha4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantAlpha4_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantBlue4_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantBlue4_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantBlue4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantBlue4_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantGreen4_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantGreen4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantGreen4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantGreen4_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantRed4_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantRed4_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantRed4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR4_ConstantRed4_MASK)

/*! @name FETCHLAYER0_LAYERPROPERTY4 - Common properties of layer 4. */
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PaletteEnable4_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PaletteEnable4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PaletteEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PaletteEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PaletteEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_TileMode4_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_TileMode4_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_TileMode4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_TileMode4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_TileMode4_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaSrcEnable4_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaSrcEnable4_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaSrcEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaSrcEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaConstEnable4_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaConstEnable4_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaConstEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaConstEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaTransEnable4_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaTransEnable4_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaTransEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_AlphaTransEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaSrcEnable4_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaSrcEnable4_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaSrcEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaSrcEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaConstEnable4_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaConstEnable4_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaConstEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaConstEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaTransEnable4_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaTransEnable4_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaTransEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_RGBAlphaTransEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PremulConstRGB4_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PremulConstRGB4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PremulConstRGB4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PremulConstRGB4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_PremulConstRGB4_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_YUVConversionMode4_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_YUVConversionMode4_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_YUVConversionMode4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_YUVConversionMode4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_YUVConversionMode4_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_GammaRemoveEnable4_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_GammaRemoveEnable4_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_GammaRemoveEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_GammaRemoveEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_GammaRemoveEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_ClipWindowEnable4_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_ClipWindowEnable4_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_ClipWindowEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_ClipWindowEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_ClipWindowEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_SourceBufferEnable4_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_SourceBufferEnable4_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_SourceBufferEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_SourceBufferEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY4_SourceBufferEnable4_MASK)

/*! @name FETCHLAYER0_BASEADDRESS5 - Source buffer base address of layer 5. */
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS5_BaseAddress5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS5_BaseAddress5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS5_BaseAddress5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS5_BaseAddress5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS5_BaseAddress5_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES5 - Source buffer attributes for layer 5. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_Stride5_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_Stride5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_Stride5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_Stride5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_Stride5_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION5 - Source buffer dimension of layer 5. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineWidth5_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineWidth5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineWidth5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineWidth5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineWidth5_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineCount5_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineCount5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineCount5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineCount5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LineCount5_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTBITS5 - Size of color components for RGB, YUV and index formats (layer 5). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsAlpha5_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsAlpha5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsAlpha5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsAlpha5_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsBlue5_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsBlue5_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsBlue5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsBlue5_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsGreen5_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsGreen5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsGreen5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsGreen5_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsRed5_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsRed5_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsRed5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ComponentBitsRed5_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFormat5_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFormat5_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFormat5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFormat5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFormat5_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTSHIFT5 - Bit position of color components for RGB, YUV and index formats (layer 5). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftRed5_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftRed5_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftRed5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT5_ComponentShiftRed5_MASK)

/*! @name FETCHLAYER0_LAYEROFFSET5 - Position of layer 5 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerXOffset5_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerXOffset5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerXOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerXOffset5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerXOffset5_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerYOffset5_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerYOffset5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerYOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerYOffset5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET5_LayerYOffset5_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWOFFSET5 - Clip window position for layer 5. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowXOffset5_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowXOffset5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowXOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowXOffset5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowXOffset5_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowYOffset5_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowYOffset5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowYOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowYOffset5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET5_ClipWindowYOffset5_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS5 - Clip window size for layer 5. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_MASK)

/*! @name FETCHLAYER0_CONSTANTCOLOR5 - Constant color for layer 5. */
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantAlpha5_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantAlpha5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantAlpha5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantAlpha5_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantBlue5_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantBlue5_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantBlue5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantBlue5_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantGreen5_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantGreen5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantGreen5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantGreen5_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantRed5_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantRed5_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantRed5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR5_ConstantRed5_MASK)

/*! @name FETCHLAYER0_LAYERPROPERTY5 - Common properties of layer 5. */
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PaletteEnable5_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PaletteEnable5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PaletteEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PaletteEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PaletteEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_TileMode5_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_TileMode5_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_TileMode5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_TileMode5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_TileMode5_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaSrcEnable5_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaSrcEnable5_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaSrcEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaSrcEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaConstEnable5_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaConstEnable5_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaConstEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaConstEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaTransEnable5_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaTransEnable5_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaTransEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_AlphaTransEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaSrcEnable5_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaSrcEnable5_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaSrcEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaSrcEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaConstEnable5_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaConstEnable5_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaConstEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaConstEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaTransEnable5_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaTransEnable5_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaTransEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_RGBAlphaTransEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PremulConstRGB5_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PremulConstRGB5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PremulConstRGB5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PremulConstRGB5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_PremulConstRGB5_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_YUVConversionMode5_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_YUVConversionMode5_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_YUVConversionMode5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_YUVConversionMode5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_YUVConversionMode5_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_GammaRemoveEnable5_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_GammaRemoveEnable5_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_GammaRemoveEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_GammaRemoveEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_GammaRemoveEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_ClipWindowEnable5_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_ClipWindowEnable5_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_ClipWindowEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_ClipWindowEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_ClipWindowEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_SourceBufferEnable5_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_SourceBufferEnable5_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_SourceBufferEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_SourceBufferEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY5_SourceBufferEnable5_MASK)

/*! @name FETCHLAYER0_BASEADDRESS6 - Source buffer base address of layer 6. */
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS6_BaseAddress6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS6_BaseAddress6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS6_BaseAddress6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS6_BaseAddress6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS6_BaseAddress6_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES6 - Source buffer attributes for layer 6. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_Stride6_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_Stride6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_Stride6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_Stride6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_Stride6_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION6 - Source buffer dimension of layer 6. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineWidth6_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineWidth6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineWidth6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineWidth6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineWidth6_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineCount6_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineCount6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineCount6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineCount6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LineCount6_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTBITS6 - Size of color components for RGB, YUV and index formats (layer 6). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsAlpha6_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsAlpha6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsAlpha6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsAlpha6_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsBlue6_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsBlue6_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsBlue6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsBlue6_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsGreen6_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsGreen6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsGreen6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsGreen6_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsRed6_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsRed6_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsRed6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ComponentBitsRed6_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFormat6_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFormat6_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFormat6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFormat6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFormat6_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTSHIFT6 - Bit position of color components for RGB, YUV and index formats (layer 6). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftRed6_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftRed6_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftRed6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT6_ComponentShiftRed6_MASK)

/*! @name FETCHLAYER0_LAYEROFFSET6 - Position of layer 1 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerXOffset6_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerXOffset6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerXOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerXOffset6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerXOffset6_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerYOffset6_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerYOffset6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerYOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerYOffset6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET6_LayerYOffset6_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWOFFSET6 - Clip window position for layer 6. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowXOffset6_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowXOffset6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowXOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowXOffset6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowXOffset6_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowYOffset6_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowYOffset6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowYOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowYOffset6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET6_ClipWindowYOffset6_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS6 - Clip window size for layer 6. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_MASK)

/*! @name FETCHLAYER0_CONSTANTCOLOR6 - Constant color for layer 6. */
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantAlpha6_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantAlpha6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantAlpha6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantAlpha6_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantBlue6_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantBlue6_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantBlue6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantBlue6_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantGreen6_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantGreen6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantGreen6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantGreen6_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantRed6_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantRed6_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantRed6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR6_ConstantRed6_MASK)

/*! @name FETCHLAYER0_LAYERPROPERTY6 - Common properties of layer 6. */
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PaletteEnable6_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PaletteEnable6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PaletteEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PaletteEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PaletteEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_TileMode6_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_TileMode6_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_TileMode6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_TileMode6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_TileMode6_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaSrcEnable6_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaSrcEnable6_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaSrcEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaSrcEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaConstEnable6_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaConstEnable6_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaConstEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaConstEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaTransEnable6_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaTransEnable6_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaTransEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_AlphaTransEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaSrcEnable6_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaSrcEnable6_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaSrcEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaSrcEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaConstEnable6_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaConstEnable6_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaConstEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaConstEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaTransEnable6_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaTransEnable6_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaTransEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_RGBAlphaTransEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PremulConstRGB6_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PremulConstRGB6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PremulConstRGB6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PremulConstRGB6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_PremulConstRGB6_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_YUVConversionMode6_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_YUVConversionMode6_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_YUVConversionMode6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_YUVConversionMode6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_YUVConversionMode6_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_GammaRemoveEnable6_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_GammaRemoveEnable6_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_GammaRemoveEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_GammaRemoveEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_GammaRemoveEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_ClipWindowEnable6_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_ClipWindowEnable6_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_ClipWindowEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_ClipWindowEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_ClipWindowEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_SourceBufferEnable6_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_SourceBufferEnable6_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_SourceBufferEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_SourceBufferEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY6_SourceBufferEnable6_MASK)

/*! @name FETCHLAYER0_BASEADDRESS7 - Source buffer base address of layer 7. */
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS7_BaseAddress7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS7_BaseAddress7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_BASEADDRESS7_BaseAddress7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BASEADDRESS7_BaseAddress7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BASEADDRESS7_BaseAddress7_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERATTRIBUTES7 - Source buffer stride for layer 7. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_Stride7_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_Stride7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_Stride7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_Stride7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_Stride7_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_MASK)

/*! @name FETCHLAYER0_SOURCEBUFFERDIMENSION7 - Source buffer dimension of layer 7. */
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineWidth7_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineWidth7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineWidth7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineWidth7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineWidth7_MASK)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineCount7_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineCount7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineCount7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineCount7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LineCount7_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTBITS7 - Size of color components for RGB, YUV and index formats (layer 7). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsAlpha7_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsAlpha7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsAlpha7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsAlpha7_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsBlue7_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsBlue7_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsBlue7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsBlue7_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsGreen7_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsGreen7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsGreen7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsGreen7_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsRed7_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsRed7_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsRed7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ComponentBitsRed7_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFormat7_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFormat7_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFormat7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFormat7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFormat7_MASK)

/*! @name FETCHLAYER0_COLORCOMPONENTSHIFT7 - Bit position of color components for RGB, YUV and index formats (layer 7). */
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_MASK)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftRed7_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftRed7_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftRed7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORCOMPONENTSHIFT7_ComponentShiftRed7_MASK)

/*! @name FETCHLAYER0_LAYEROFFSET7 - Position of layer 7 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerXOffset7_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerXOffset7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerXOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerXOffset7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerXOffset7_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerYOffset7_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerYOffset7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerYOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerYOffset7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYEROFFSET7_LayerYOffset7_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWOFFSET7 - Clip window position for layer 7. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowXOffset7_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowXOffset7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowXOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowXOffset7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowXOffset7_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowYOffset7_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowYOffset7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowYOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowYOffset7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWOFFSET7_ClipWindowYOffset7_MASK)

/*! @name FETCHLAYER0_CLIPWINDOWDIMENSIONS7 - Clip window size for layer 7. */
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_MASK)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_MASK)

/*! @name FETCHLAYER0_CONSTANTCOLOR7 - Constant color for layer 7. */
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantAlpha7_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantAlpha7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantAlpha7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantAlpha7_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantBlue7_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantBlue7_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantBlue7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantBlue7_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantGreen7_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantGreen7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantGreen7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantGreen7_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantRed7_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantRed7_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantRed7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONSTANTCOLOR7_ConstantRed7_MASK)

/*! @name FETCHLAYER0_LAYERPROPERTY7 - Common properties of layer 7. */
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PaletteEnable7_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PaletteEnable7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PaletteEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PaletteEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PaletteEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_TileMode7_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_TileMode7_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_TileMode7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_TileMode7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_TileMode7_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaSrcEnable7_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaSrcEnable7_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaSrcEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaSrcEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaConstEnable7_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaConstEnable7_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaConstEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaConstEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaTransEnable7_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaTransEnable7_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaTransEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_AlphaTransEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaSrcEnable7_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaSrcEnable7_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaSrcEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaSrcEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaConstEnable7_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaConstEnable7_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaConstEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaConstEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaTransEnable7_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaTransEnable7_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaTransEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_RGBAlphaTransEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PremulConstRGB7_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PremulConstRGB7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PremulConstRGB7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PremulConstRGB7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_PremulConstRGB7_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_YUVConversionMode7_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_YUVConversionMode7_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_YUVConversionMode7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_YUVConversionMode7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_YUVConversionMode7_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_GammaRemoveEnable7_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_GammaRemoveEnable7_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_GammaRemoveEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_GammaRemoveEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_GammaRemoveEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_ClipWindowEnable7_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_ClipWindowEnable7_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_ClipWindowEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_ClipWindowEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_ClipWindowEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_SourceBufferEnable7_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_SourceBufferEnable7_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_SourceBufferEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_SourceBufferEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER0_LAYERPROPERTY7_SourceBufferEnable7_MASK)

/*! @name FETCHLAYER0_FRAMEDIMENSIONS - Output frame dimension. */
#define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name FETCHLAYER0_FRAMERESAMPLING - Resampling options for output frame. */
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartX_MASK (0x3FU)
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartX_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartX_MASK)
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartY_MASK (0xFC0U)
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartY_SHIFT (6U)
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_StartY_MASK)
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaX_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaX_MASK)
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaY_SHIFT (18U)
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_DeltaY_MASK)
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FRAMERESAMPLING_SwapDirection_MASK)

/*! @name FETCHLAYER0_CONTROL - Shared common control settings for all layers. */
#define IRIS_MVPL_FETCHLAYER0_CONTROL_RawPixel_MASK (0x80U)
#define IRIS_MVPL_FETCHLAYER0_CONTROL_RawPixel_SHIFT (7U)
#define IRIS_MVPL_FETCHLAYER0_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONTROL_RawPixel_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONTROL_PaletteIdxWidth_MASK (0x700U)
#define IRIS_MVPL_FETCHLAYER0_CONTROL_PaletteIdxWidth_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_CONTROL_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONTROL_PaletteIdxWidth_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONTROL_PaletteIdxWidth_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONTROL_ClipColor_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER0_CONTROL_ClipColor_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER0_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONTROL_ClipColor_MASK)
#define IRIS_MVPL_FETCHLAYER0_CONTROL_ClipLayer_MASK (0xE0000U)
#define IRIS_MVPL_FETCHLAYER0_CONTROL_ClipLayer_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER0_CONTROL_ClipLayer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONTROL_ClipLayer_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONTROL_ClipLayer_MASK)

/*! @name FETCHLAYER0_TRIGGERENABLE - Shadow load enable flags for all layers. */
#define IRIS_MVPL_FETCHLAYER0_TRIGGERENABLE_ShdLdReq_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER0_TRIGGERENABLE_ShdLdReq_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_TRIGGERENABLE_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_TRIGGERENABLE_ShdLdReq_SHIFT)) & IRIS_MVPL_FETCHLAYER0_TRIGGERENABLE_ShdLdReq_MASK)

/*! @name FETCHLAYER0_CONTROLTRIGGER - Shadow load trigger. */
#define IRIS_MVPL_FETCHLAYER0_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER0_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHLAYER0_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name FETCHLAYER0_START - Frame start trigger. */
#define IRIS_MVPL_FETCHLAYER0_START_Start_MASK   (0x1U)
#define IRIS_MVPL_FETCHLAYER0_START_Start_SHIFT  (0U)
#define IRIS_MVPL_FETCHLAYER0_START_Start(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_START_Start_SHIFT)) & IRIS_MVPL_FETCHLAYER0_START_Start_MASK)

/*! @name FETCHLAYER0_FETCHTYPE - Fetch unit type. */
#define IRIS_MVPL_FETCHLAYER0_FETCHTYPE_FetchType_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER0_FETCHTYPE_FetchType_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHLAYER0_FETCHTYPE_FetchType_MASK)

/*! @name FETCHLAYER0_BURSTBUFFERPROPERTIES - Burst buffer properties. */
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHLAYER0_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)

/*! @name FETCHLAYER0_STATUS - Status informations. */
#define IRIS_MVPL_FETCHLAYER0_STATUS_WriteTimeout_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER0_STATUS_WriteTimeout_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHLAYER0_STATUS_WriteTimeout_MASK)
#define IRIS_MVPL_FETCHLAYER0_STATUS_ReadTimeout_MASK (0x10U)
#define IRIS_MVPL_FETCHLAYER0_STATUS_ReadTimeout_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER0_STATUS_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_STATUS_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHLAYER0_STATUS_ReadTimeout_MASK)

/*! @name FETCHLAYER0_HIDDENSTATUS - Hidden status informations. */
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBusy_MASK)
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusRequest_MASK)
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_StatusComplete_MASK)
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER0_HIDDENSTATUS_ShadowStatus_MASK)

/*! @name FETCHLAYER0_COLORPALETTE - Color palette look up table. */
#define IRIS_MVPL_FETCHLAYER0_COLORPALETTE_ColorPalette_MASK (0xFFFFFFU)
#define IRIS_MVPL_FETCHLAYER0_COLORPALETTE_ColorPalette_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER0_COLORPALETTE_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER0_COLORPALETTE_ColorPalette_SHIFT)) & IRIS_MVPL_FETCHLAYER0_COLORPALETTE_ColorPalette_MASK)

/*! @name FETCHLAYER1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FETCHLAYER1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER1_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FETCHLAYER1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FETCHLAYER1_STATICCONTROL - Common static control options. */
#define IRIS_MVPL_FETCHLAYER1_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER1_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHLAYER1_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_FETCHLAYER1_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER1_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHLAYER1_STATICCONTROL_BaseAddressAutoUpdate_MASK)
#define IRIS_MVPL_FETCHLAYER1_STATICCONTROL_ShdLdReqSticky_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER1_STATICCONTROL_ShdLdReqSticky_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_STATICCONTROL_ShdLdReqSticky(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_STATICCONTROL_ShdLdReqSticky_SHIFT)) & IRIS_MVPL_FETCHLAYER1_STATICCONTROL_ShdLdReqSticky_MASK)

/*! @name FETCHLAYER1_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHLAYER1_BURSTBUFFERMANAGEMENT_LineMode_MASK)

/*! @name FETCHLAYER1_BASEADDRESS0 - Source buffer base address of layer 0. */
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS0_BaseAddress0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_BASEADDRESS0_BaseAddress0_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION0_LineCount0_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS0_ITUFormat0_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)

/*! @name FETCHLAYER1_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET0_LayerXOffset0_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET0_LayerYOffset0_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)

/*! @name FETCHLAYER1_CONSTANTCOLOR0 - Constant color for layer 0. */
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantAlpha0_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantBlue0_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantGreen0_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR0_ConstantRed0_MASK)

/*! @name FETCHLAYER1_LAYERPROPERTY0 - Common properties of layer 0. */
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_PaletteEnable0_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_PaletteEnable0_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_PaletteEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_PaletteEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_TileMode0_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_TileMode0_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_TileMode0_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaSrcEnable0_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaConstEnable0_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaConstEnable0_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaTransEnable0_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaTransEnable0_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_AlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_PremulConstRGB0_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_PremulConstRGB0_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_PremulConstRGB0_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_YUVConversionMode0_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_YUVConversionMode0_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_YUVConversionMode0_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_GammaRemoveEnable0_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_GammaRemoveEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_ClipWindowEnable0_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY0_SourceBufferEnable0_MASK)

/*! @name FETCHLAYER1_BASEADDRESS1 - Source buffer base address of layer 1. */
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS1_BaseAddress1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS1_BaseAddress1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS1_BaseAddress1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_BASEADDRESS1_BaseAddress1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_BASEADDRESS1_BaseAddress1_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERATTRIBUTES1 - Source buffer attributes for layer 1. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_Stride1_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_Stride1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_Stride1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_Stride1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_Stride1_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERDIMENSION1 - Source buffer dimensions of layer 1, */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION1_LineWidth1_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION1_LineWidth1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION1_LineWidth1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION1_LineWidth1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION1_LineWidth1_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION1_LineCount1_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION1_LineCount1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION1_LineCount1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION1_LineCount1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION1_LineCount1_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTBITS1 - Size of color components for RGB, YUV and index formats (layer 1). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsAlpha1_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsAlpha1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsAlpha1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsAlpha1_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsBlue1_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsBlue1_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsBlue1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsBlue1_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsGreen1_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsGreen1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsGreen1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsGreen1_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsRed1_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsRed1_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsRed1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ComponentBitsRed1_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ITUFormat1_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ITUFormat1_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ITUFormat1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ITUFormat1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS1_ITUFormat1_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTSHIFT1 - Bit position of color components for RGB, YUV and index formats (layer 1). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftRed1_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftRed1_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftRed1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT1_ComponentShiftRed1_MASK)

/*! @name FETCHLAYER1_LAYEROFFSET1 - Position of layer 1 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET1_LayerXOffset1_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET1_LayerXOffset1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET1_LayerXOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET1_LayerXOffset1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET1_LayerXOffset1_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET1_LayerYOffset1_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET1_LayerYOffset1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET1_LayerYOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET1_LayerYOffset1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET1_LayerYOffset1_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWOFFSET1 - Clip window position for layer 1. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET1_ClipWindowXOffset1_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET1_ClipWindowXOffset1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET1_ClipWindowXOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET1_ClipWindowXOffset1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET1_ClipWindowXOffset1_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET1_ClipWindowYOffset1_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET1_ClipWindowYOffset1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET1_ClipWindowYOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET1_ClipWindowYOffset1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET1_ClipWindowYOffset1_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWDIMENSIONS1 - Clip window size for layer 1. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_MASK)

/*! @name FETCHLAYER1_CONSTANTCOLOR1 - Constant color for layer 1. */
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantAlpha1_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantAlpha1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantAlpha1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantAlpha1_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantBlue1_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantBlue1_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantBlue1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantBlue1_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantGreen1_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantGreen1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantGreen1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantGreen1_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantRed1_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantRed1_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantRed1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR1_ConstantRed1_MASK)

/*! @name FETCHLAYER1_LAYERPROPERTY1 - Common properties of layer 1. */
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_PaletteEnable1_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_PaletteEnable1_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_PaletteEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_PaletteEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_PaletteEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_TileMode1_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_TileMode1_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_TileMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_TileMode1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_TileMode1_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaSrcEnable1_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaSrcEnable1_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaSrcEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaSrcEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaConstEnable1_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaConstEnable1_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaConstEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaConstEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaTransEnable1_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaTransEnable1_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaTransEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_AlphaTransEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaSrcEnable1_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaSrcEnable1_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaSrcEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaSrcEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaConstEnable1_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaConstEnable1_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaConstEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaConstEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaTransEnable1_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaTransEnable1_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaTransEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_RGBAlphaTransEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_PremulConstRGB1_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_PremulConstRGB1_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_PremulConstRGB1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_PremulConstRGB1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_PremulConstRGB1_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_YUVConversionMode1_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_YUVConversionMode1_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_YUVConversionMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_YUVConversionMode1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_YUVConversionMode1_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_GammaRemoveEnable1_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_GammaRemoveEnable1_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_GammaRemoveEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_GammaRemoveEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_GammaRemoveEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_ClipWindowEnable1_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_ClipWindowEnable1_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_ClipWindowEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_ClipWindowEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_ClipWindowEnable1_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_SourceBufferEnable1_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_SourceBufferEnable1_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_SourceBufferEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_SourceBufferEnable1_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY1_SourceBufferEnable1_MASK)

/*! @name FETCHLAYER1_BASEADDRESS2 - Source buffer base address of layer 2. */
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS2_BaseAddress2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS2_BaseAddress2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS2_BaseAddress2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_BASEADDRESS2_BaseAddress2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_BASEADDRESS2_BaseAddress2_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERATTRIBUTES2 - Source buffer attributes for layer 2. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_Stride2_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_Stride2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_Stride2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_Stride2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_Stride2_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERDIMENSION2 - Source buffer dimension of layer 2. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION2_LineWidth2_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION2_LineWidth2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION2_LineWidth2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION2_LineWidth2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION2_LineWidth2_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION2_LineCount2_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION2_LineCount2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION2_LineCount2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION2_LineCount2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION2_LineCount2_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTBITS2 - Size of color components for RGB, YUV and index formats (layer 2). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsAlpha2_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsAlpha2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsAlpha2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsAlpha2_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsBlue2_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsBlue2_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsBlue2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsBlue2_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsGreen2_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsGreen2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsGreen2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsGreen2_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsRed2_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsRed2_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsRed2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ComponentBitsRed2_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ITUFormat2_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ITUFormat2_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ITUFormat2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ITUFormat2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS2_ITUFormat2_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTSHIFT2 - Bit position of color components for RGB, YUV and index formats (layer 2). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftRed2_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftRed2_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftRed2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT2_ComponentShiftRed2_MASK)

/*! @name FETCHLAYER1_LAYEROFFSET2 - Position of layer 2 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET2_LayerXOffset2_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET2_LayerXOffset2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET2_LayerXOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET2_LayerXOffset2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET2_LayerXOffset2_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET2_LayerYOffset2_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET2_LayerYOffset2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET2_LayerYOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET2_LayerYOffset2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET2_LayerYOffset2_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWOFFSET2 - Clip window position for layer 2. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET2_ClipWindowXOffset2_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET2_ClipWindowXOffset2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET2_ClipWindowXOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET2_ClipWindowXOffset2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET2_ClipWindowXOffset2_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET2_ClipWindowYOffset2_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET2_ClipWindowYOffset2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET2_ClipWindowYOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET2_ClipWindowYOffset2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET2_ClipWindowYOffset2_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWDIMENSIONS2 - Clip window size for layer 2. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_MASK)

/*! @name FETCHLAYER1_CONSTANTCOLOR2 - Constant color for layer 2. */
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantAlpha2_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantAlpha2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantAlpha2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantAlpha2_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantBlue2_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantBlue2_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantBlue2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantBlue2_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantGreen2_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantGreen2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantGreen2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantGreen2_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantRed2_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantRed2_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantRed2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR2_ConstantRed2_MASK)

/*! @name FETCHLAYER1_LAYERPROPERTY2 - Common properties of layer 2. */
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_PaletteEnable2_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_PaletteEnable2_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_PaletteEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_PaletteEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_PaletteEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_TileMode2_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_TileMode2_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_TileMode2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_TileMode2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_TileMode2_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaSrcEnable2_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaSrcEnable2_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaSrcEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaSrcEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaConstEnable2_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaConstEnable2_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaConstEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaConstEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaTransEnable2_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaTransEnable2_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaTransEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_AlphaTransEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaSrcEnable2_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaSrcEnable2_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaSrcEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaSrcEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaConstEnable2_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaConstEnable2_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaConstEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaConstEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaTransEnable2_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaTransEnable2_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaTransEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_RGBAlphaTransEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_PremulConstRGB2_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_PremulConstRGB2_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_PremulConstRGB2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_PremulConstRGB2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_PremulConstRGB2_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_YUVConversionMode2_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_YUVConversionMode2_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_YUVConversionMode2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_YUVConversionMode2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_YUVConversionMode2_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_GammaRemoveEnable2_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_GammaRemoveEnable2_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_GammaRemoveEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_GammaRemoveEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_GammaRemoveEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_ClipWindowEnable2_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_ClipWindowEnable2_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_ClipWindowEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_ClipWindowEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_ClipWindowEnable2_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_SourceBufferEnable2_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_SourceBufferEnable2_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_SourceBufferEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_SourceBufferEnable2_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY2_SourceBufferEnable2_MASK)

/*! @name FETCHLAYER1_BASEADDRESS3 - Source buffer base address of layer 3. */
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS3_BaseAddress3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS3_BaseAddress3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS3_BaseAddress3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_BASEADDRESS3_BaseAddress3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_BASEADDRESS3_BaseAddress3_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERATTRIBUTES3 - Source buffer attributes for layer 3. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_Stride3_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_Stride3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_Stride3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_Stride3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_Stride3_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERDIMENSION3 - Source buffer dimension of layer 3. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION3_LineWidth3_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION3_LineWidth3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION3_LineWidth3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION3_LineWidth3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION3_LineWidth3_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION3_LineCount3_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION3_LineCount3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION3_LineCount3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION3_LineCount3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION3_LineCount3_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTBITS3 - Size of color components for RGB, YUV and index formats (layer 3). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsAlpha3_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsAlpha3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsAlpha3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsAlpha3_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsBlue3_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsBlue3_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsBlue3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsBlue3_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsGreen3_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsGreen3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsGreen3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsGreen3_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsRed3_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsRed3_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsRed3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ComponentBitsRed3_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ITUFormat3_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ITUFormat3_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ITUFormat3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ITUFormat3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS3_ITUFormat3_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTSHIFT3 - Bit position of color components for RGB, YUV and index formats (layer 3). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftRed3_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftRed3_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftRed3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT3_ComponentShiftRed3_MASK)

/*! @name FETCHLAYER1_LAYEROFFSET3 - Position of layer 3 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET3_LayerXOffset3_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET3_LayerXOffset3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET3_LayerXOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET3_LayerXOffset3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET3_LayerXOffset3_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET3_LayerYOffset3_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET3_LayerYOffset3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET3_LayerYOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET3_LayerYOffset3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET3_LayerYOffset3_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWOFFSET3 - Clip window position for layer 3. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET3_ClipWindowXOffset3_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET3_ClipWindowXOffset3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET3_ClipWindowXOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET3_ClipWindowXOffset3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET3_ClipWindowXOffset3_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET3_ClipWindowYOffset3_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET3_ClipWindowYOffset3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET3_ClipWindowYOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET3_ClipWindowYOffset3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET3_ClipWindowYOffset3_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWDIMENSIONS3 - Clip window size for layer 3. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_MASK)

/*! @name FETCHLAYER1_CONSTANTCOLOR3 - Constant color for layer 3. */
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantAlpha3_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantAlpha3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantAlpha3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantAlpha3_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantBlue3_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantBlue3_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantBlue3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantBlue3_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantGreen3_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantGreen3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantGreen3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantGreen3_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantRed3_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantRed3_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantRed3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR3_ConstantRed3_MASK)

/*! @name FETCHLAYER1_LAYERPROPERTY3 - Common properties of layer 3. */
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_PaletteEnable3_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_PaletteEnable3_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_PaletteEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_PaletteEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_PaletteEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_TileMode3_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_TileMode3_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_TileMode3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_TileMode3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_TileMode3_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaSrcEnable3_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaSrcEnable3_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaSrcEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaSrcEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaConstEnable3_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaConstEnable3_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaConstEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaConstEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaTransEnable3_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaTransEnable3_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaTransEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_AlphaTransEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaSrcEnable3_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaSrcEnable3_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaSrcEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaSrcEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaConstEnable3_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaConstEnable3_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaConstEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaConstEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaTransEnable3_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaTransEnable3_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaTransEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_RGBAlphaTransEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_PremulConstRGB3_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_PremulConstRGB3_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_PremulConstRGB3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_PremulConstRGB3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_PremulConstRGB3_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_YUVConversionMode3_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_YUVConversionMode3_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_YUVConversionMode3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_YUVConversionMode3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_YUVConversionMode3_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_GammaRemoveEnable3_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_GammaRemoveEnable3_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_GammaRemoveEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_GammaRemoveEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_GammaRemoveEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_ClipWindowEnable3_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_ClipWindowEnable3_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_ClipWindowEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_ClipWindowEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_ClipWindowEnable3_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_SourceBufferEnable3_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_SourceBufferEnable3_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_SourceBufferEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_SourceBufferEnable3_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY3_SourceBufferEnable3_MASK)

/*! @name FETCHLAYER1_BASEADDRESS4 - Source buffer base address of layer 4. */
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS4_BaseAddress4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS4_BaseAddress4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS4_BaseAddress4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_BASEADDRESS4_BaseAddress4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_BASEADDRESS4_BaseAddress4_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERATTRIBUTES4 - Source buffer attributes for layer 4. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_Stride4_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_Stride4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_Stride4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_Stride4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_Stride4_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERDIMENSION4 - Source buffer dimension of layer 4. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION4_LineWidth4_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION4_LineWidth4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION4_LineWidth4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION4_LineWidth4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION4_LineWidth4_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION4_LineCount4_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION4_LineCount4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION4_LineCount4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION4_LineCount4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION4_LineCount4_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTBITS4 - Size of color components for RGB, YUV and index formats (layer 4). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsAlpha4_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsAlpha4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsAlpha4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsAlpha4_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsBlue4_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsBlue4_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsBlue4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsBlue4_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsGreen4_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsGreen4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsGreen4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsGreen4_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsRed4_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsRed4_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsRed4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ComponentBitsRed4_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ITUFormat4_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ITUFormat4_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ITUFormat4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ITUFormat4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS4_ITUFormat4_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTSHIFT4 - Bit position of color components for RGB, YUV and index formats (layer 4). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftRed4_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftRed4_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftRed4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT4_ComponentShiftRed4_MASK)

/*! @name FETCHLAYER1_LAYEROFFSET4 - Position of layer 4 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET4_LayerXOffset4_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET4_LayerXOffset4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET4_LayerXOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET4_LayerXOffset4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET4_LayerXOffset4_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET4_LayerYOffset4_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET4_LayerYOffset4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET4_LayerYOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET4_LayerYOffset4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET4_LayerYOffset4_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWOFFSET4 - Clip window position for layer 4. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET4_ClipWindowXOffset4_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET4_ClipWindowXOffset4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET4_ClipWindowXOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET4_ClipWindowXOffset4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET4_ClipWindowXOffset4_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET4_ClipWindowYOffset4_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET4_ClipWindowYOffset4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET4_ClipWindowYOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET4_ClipWindowYOffset4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET4_ClipWindowYOffset4_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWDIMENSIONS4 - Clip window size for layer 4. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_MASK)

/*! @name FETCHLAYER1_CONSTANTCOLOR4 - Constant color for layer 4. */
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantAlpha4_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantAlpha4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantAlpha4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantAlpha4_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantBlue4_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantBlue4_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantBlue4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantBlue4_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantGreen4_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantGreen4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantGreen4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantGreen4_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantRed4_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantRed4_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantRed4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR4_ConstantRed4_MASK)

/*! @name FETCHLAYER1_LAYERPROPERTY4 - Common properties of layer 4. */
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_PaletteEnable4_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_PaletteEnable4_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_PaletteEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_PaletteEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_PaletteEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_TileMode4_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_TileMode4_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_TileMode4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_TileMode4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_TileMode4_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaSrcEnable4_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaSrcEnable4_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaSrcEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaSrcEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaConstEnable4_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaConstEnable4_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaConstEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaConstEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaTransEnable4_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaTransEnable4_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaTransEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_AlphaTransEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaSrcEnable4_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaSrcEnable4_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaSrcEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaSrcEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaConstEnable4_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaConstEnable4_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaConstEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaConstEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaTransEnable4_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaTransEnable4_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaTransEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_RGBAlphaTransEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_PremulConstRGB4_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_PremulConstRGB4_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_PremulConstRGB4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_PremulConstRGB4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_PremulConstRGB4_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_YUVConversionMode4_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_YUVConversionMode4_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_YUVConversionMode4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_YUVConversionMode4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_YUVConversionMode4_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_GammaRemoveEnable4_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_GammaRemoveEnable4_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_GammaRemoveEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_GammaRemoveEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_GammaRemoveEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_ClipWindowEnable4_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_ClipWindowEnable4_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_ClipWindowEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_ClipWindowEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_ClipWindowEnable4_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_SourceBufferEnable4_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_SourceBufferEnable4_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_SourceBufferEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_SourceBufferEnable4_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY4_SourceBufferEnable4_MASK)

/*! @name FETCHLAYER1_BASEADDRESS5 - Source buffer base address of layer 5. */
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS5_BaseAddress5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS5_BaseAddress5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS5_BaseAddress5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_BASEADDRESS5_BaseAddress5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_BASEADDRESS5_BaseAddress5_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERATTRIBUTES5 - Source buffer attributes for layer 5. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_Stride5_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_Stride5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_Stride5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_Stride5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_Stride5_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERDIMENSION5 - Source buffer dimension of layer 5. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION5_LineWidth5_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION5_LineWidth5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION5_LineWidth5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION5_LineWidth5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION5_LineWidth5_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION5_LineCount5_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION5_LineCount5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION5_LineCount5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION5_LineCount5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION5_LineCount5_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTBITS5 - Size of color components for RGB, YUV and index formats (layer 5). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsAlpha5_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsAlpha5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsAlpha5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsAlpha5_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsBlue5_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsBlue5_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsBlue5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsBlue5_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsGreen5_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsGreen5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsGreen5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsGreen5_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsRed5_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsRed5_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsRed5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ComponentBitsRed5_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ITUFormat5_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ITUFormat5_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ITUFormat5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ITUFormat5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS5_ITUFormat5_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTSHIFT5 - Bit position of color components for RGB, YUV and index formats (layer 5). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftRed5_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftRed5_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftRed5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT5_ComponentShiftRed5_MASK)

/*! @name FETCHLAYER1_LAYEROFFSET5 - Position of layer 5 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET5_LayerXOffset5_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET5_LayerXOffset5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET5_LayerXOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET5_LayerXOffset5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET5_LayerXOffset5_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET5_LayerYOffset5_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET5_LayerYOffset5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET5_LayerYOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET5_LayerYOffset5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET5_LayerYOffset5_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWOFFSET5 - Clip window position for layer 5. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET5_ClipWindowXOffset5_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET5_ClipWindowXOffset5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET5_ClipWindowXOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET5_ClipWindowXOffset5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET5_ClipWindowXOffset5_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET5_ClipWindowYOffset5_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET5_ClipWindowYOffset5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET5_ClipWindowYOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET5_ClipWindowYOffset5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET5_ClipWindowYOffset5_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWDIMENSIONS5 - Clip window size for layer 5. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_MASK)

/*! @name FETCHLAYER1_CONSTANTCOLOR5 - Constant color for layer 5. */
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantAlpha5_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantAlpha5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantAlpha5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantAlpha5_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantBlue5_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantBlue5_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantBlue5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantBlue5_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantGreen5_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantGreen5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantGreen5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantGreen5_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantRed5_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantRed5_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantRed5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR5_ConstantRed5_MASK)

/*! @name FETCHLAYER1_LAYERPROPERTY5 - Common properties of layer 5. */
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_PaletteEnable5_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_PaletteEnable5_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_PaletteEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_PaletteEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_PaletteEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_TileMode5_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_TileMode5_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_TileMode5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_TileMode5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_TileMode5_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaSrcEnable5_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaSrcEnable5_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaSrcEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaSrcEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaConstEnable5_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaConstEnable5_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaConstEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaConstEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaTransEnable5_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaTransEnable5_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaTransEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_AlphaTransEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaSrcEnable5_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaSrcEnable5_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaSrcEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaSrcEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaConstEnable5_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaConstEnable5_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaConstEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaConstEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaTransEnable5_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaTransEnable5_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaTransEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_RGBAlphaTransEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_PremulConstRGB5_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_PremulConstRGB5_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_PremulConstRGB5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_PremulConstRGB5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_PremulConstRGB5_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_YUVConversionMode5_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_YUVConversionMode5_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_YUVConversionMode5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_YUVConversionMode5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_YUVConversionMode5_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_GammaRemoveEnable5_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_GammaRemoveEnable5_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_GammaRemoveEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_GammaRemoveEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_GammaRemoveEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_ClipWindowEnable5_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_ClipWindowEnable5_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_ClipWindowEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_ClipWindowEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_ClipWindowEnable5_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_SourceBufferEnable5_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_SourceBufferEnable5_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_SourceBufferEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_SourceBufferEnable5_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY5_SourceBufferEnable5_MASK)

/*! @name FETCHLAYER1_BASEADDRESS6 - Source buffer base address of layer 6. */
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS6_BaseAddress6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS6_BaseAddress6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS6_BaseAddress6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_BASEADDRESS6_BaseAddress6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_BASEADDRESS6_BaseAddress6_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERATTRIBUTES6 - Source buffer attributes for layer 6. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_Stride6_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_Stride6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_Stride6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_Stride6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_Stride6_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERDIMENSION6 - Source buffer dimension of layer 6. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION6_LineWidth6_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION6_LineWidth6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION6_LineWidth6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION6_LineWidth6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION6_LineWidth6_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION6_LineCount6_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION6_LineCount6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION6_LineCount6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION6_LineCount6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION6_LineCount6_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTBITS6 - Size of color components for RGB, YUV and index formats (layer 6). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsAlpha6_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsAlpha6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsAlpha6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsAlpha6_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsBlue6_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsBlue6_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsBlue6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsBlue6_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsGreen6_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsGreen6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsGreen6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsGreen6_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsRed6_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsRed6_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsRed6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ComponentBitsRed6_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ITUFormat6_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ITUFormat6_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ITUFormat6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ITUFormat6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS6_ITUFormat6_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTSHIFT6 - Bit position of color components for RGB, YUV and index formats (layer 6). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftRed6_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftRed6_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftRed6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT6_ComponentShiftRed6_MASK)

/*! @name FETCHLAYER1_LAYEROFFSET6 - Position of layer 1 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET6_LayerXOffset6_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET6_LayerXOffset6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET6_LayerXOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET6_LayerXOffset6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET6_LayerXOffset6_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET6_LayerYOffset6_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET6_LayerYOffset6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET6_LayerYOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET6_LayerYOffset6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET6_LayerYOffset6_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWOFFSET6 - Clip window position for layer 6. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET6_ClipWindowXOffset6_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET6_ClipWindowXOffset6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET6_ClipWindowXOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET6_ClipWindowXOffset6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET6_ClipWindowXOffset6_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET6_ClipWindowYOffset6_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET6_ClipWindowYOffset6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET6_ClipWindowYOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET6_ClipWindowYOffset6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET6_ClipWindowYOffset6_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWDIMENSIONS6 - Clip window size for layer 6. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_MASK)

/*! @name FETCHLAYER1_CONSTANTCOLOR6 - Constant color for layer 6. */
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantAlpha6_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantAlpha6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantAlpha6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantAlpha6_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantBlue6_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantBlue6_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantBlue6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantBlue6_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantGreen6_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantGreen6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantGreen6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantGreen6_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantRed6_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantRed6_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantRed6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR6_ConstantRed6_MASK)

/*! @name FETCHLAYER1_LAYERPROPERTY6 - Common properties of layer 6. */
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_PaletteEnable6_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_PaletteEnable6_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_PaletteEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_PaletteEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_PaletteEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_TileMode6_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_TileMode6_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_TileMode6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_TileMode6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_TileMode6_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaSrcEnable6_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaSrcEnable6_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaSrcEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaSrcEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaConstEnable6_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaConstEnable6_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaConstEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaConstEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaTransEnable6_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaTransEnable6_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaTransEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_AlphaTransEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaSrcEnable6_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaSrcEnable6_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaSrcEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaSrcEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaConstEnable6_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaConstEnable6_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaConstEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaConstEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaTransEnable6_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaTransEnable6_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaTransEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_RGBAlphaTransEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_PremulConstRGB6_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_PremulConstRGB6_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_PremulConstRGB6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_PremulConstRGB6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_PremulConstRGB6_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_YUVConversionMode6_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_YUVConversionMode6_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_YUVConversionMode6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_YUVConversionMode6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_YUVConversionMode6_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_GammaRemoveEnable6_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_GammaRemoveEnable6_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_GammaRemoveEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_GammaRemoveEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_GammaRemoveEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_ClipWindowEnable6_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_ClipWindowEnable6_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_ClipWindowEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_ClipWindowEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_ClipWindowEnable6_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_SourceBufferEnable6_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_SourceBufferEnable6_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_SourceBufferEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_SourceBufferEnable6_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY6_SourceBufferEnable6_MASK)

/*! @name FETCHLAYER1_BASEADDRESS7 - Source buffer base address of layer 7. */
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS7_BaseAddress7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS7_BaseAddress7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_BASEADDRESS7_BaseAddress7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_BASEADDRESS7_BaseAddress7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_BASEADDRESS7_BaseAddress7_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERATTRIBUTES7 - Source buffer stride for layer 7. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_Stride7_MASK (0xFFFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_Stride7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_Stride7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_Stride7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_Stride7_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_MASK (0x3F0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_MASK)

/*! @name FETCHLAYER1_SOURCEBUFFERDIMENSION7 - Source buffer dimension of layer 7. */
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION7_LineWidth7_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION7_LineWidth7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION7_LineWidth7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION7_LineWidth7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION7_LineWidth7_MASK)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION7_LineCount7_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION7_LineCount7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION7_LineCount7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION7_LineCount7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_SOURCEBUFFERDIMENSION7_LineCount7_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTBITS7 - Size of color components for RGB, YUV and index formats (layer 7). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsAlpha7_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsAlpha7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsAlpha7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsAlpha7_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsBlue7_MASK (0xF00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsBlue7_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsBlue7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsBlue7_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsGreen7_MASK (0xF0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsGreen7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsGreen7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsGreen7_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsRed7_MASK (0xF000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsRed7_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsRed7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ComponentBitsRed7_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ITUFormat7_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ITUFormat7_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ITUFormat7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ITUFormat7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTBITS7_ITUFormat7_MASK)

/*! @name FETCHLAYER1_COLORCOMPONENTSHIFT7 - Bit position of color components for RGB, YUV and index formats (layer 7). */
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_MASK (0x1FU)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_MASK (0x1F0000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_MASK)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftRed7_MASK (0x1F000000U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftRed7_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftRed7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORCOMPONENTSHIFT7_ComponentShiftRed7_MASK)

/*! @name FETCHLAYER1_LAYEROFFSET7 - Position of layer 7 within the destination frame. */
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET7_LayerXOffset7_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET7_LayerXOffset7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET7_LayerXOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET7_LayerXOffset7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET7_LayerXOffset7_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET7_LayerYOffset7_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET7_LayerYOffset7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYEROFFSET7_LayerYOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYEROFFSET7_LayerYOffset7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYEROFFSET7_LayerYOffset7_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWOFFSET7 - Clip window position for layer 7. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET7_ClipWindowXOffset7_MASK (0x7FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET7_ClipWindowXOffset7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET7_ClipWindowXOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET7_ClipWindowXOffset7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET7_ClipWindowXOffset7_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET7_ClipWindowYOffset7_MASK (0x7FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET7_ClipWindowYOffset7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET7_ClipWindowYOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET7_ClipWindowYOffset7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWOFFSET7_ClipWindowYOffset7_MASK)

/*! @name FETCHLAYER1_CLIPWINDOWDIMENSIONS7 - Clip window size for layer 7. */
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_MASK)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_MASK)

/*! @name FETCHLAYER1_CONSTANTCOLOR7 - Constant color for layer 7. */
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantAlpha7_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantAlpha7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantAlpha7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantAlpha7_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantBlue7_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantBlue7_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantBlue7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantBlue7_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantGreen7_MASK (0xFF0000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantGreen7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantGreen7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantGreen7_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantRed7_MASK (0xFF000000U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantRed7_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantRed7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONSTANTCOLOR7_ConstantRed7_MASK)

/*! @name FETCHLAYER1_LAYERPROPERTY7 - Common properties of layer 7. */
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_PaletteEnable7_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_PaletteEnable7_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_PaletteEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_PaletteEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_PaletteEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_TileMode7_MASK (0x30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_TileMode7_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_TileMode7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_TileMode7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_TileMode7_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaSrcEnable7_MASK (0x100U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaSrcEnable7_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaSrcEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaSrcEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaConstEnable7_MASK (0x200U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaConstEnable7_SHIFT (9U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaConstEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaConstEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaTransEnable7_MASK (0x800U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaTransEnable7_SHIFT (11U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaTransEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_AlphaTransEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaSrcEnable7_MASK (0x1000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaSrcEnable7_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaSrcEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaSrcEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaConstEnable7_MASK (0x2000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaConstEnable7_SHIFT (13U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaConstEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaConstEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaTransEnable7_MASK (0x8000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaTransEnable7_SHIFT (15U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaTransEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_RGBAlphaTransEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_PremulConstRGB7_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_PremulConstRGB7_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_PremulConstRGB7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_PremulConstRGB7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_PremulConstRGB7_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_YUVConversionMode7_MASK (0x60000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_YUVConversionMode7_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_YUVConversionMode7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_YUVConversionMode7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_YUVConversionMode7_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_GammaRemoveEnable7_MASK (0x100000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_GammaRemoveEnable7_SHIFT (20U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_GammaRemoveEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_GammaRemoveEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_GammaRemoveEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_ClipWindowEnable7_MASK (0x40000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_ClipWindowEnable7_SHIFT (30U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_ClipWindowEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_ClipWindowEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_ClipWindowEnable7_MASK)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_SourceBufferEnable7_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_SourceBufferEnable7_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_SourceBufferEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_SourceBufferEnable7_SHIFT)) & IRIS_MVPL_FETCHLAYER1_LAYERPROPERTY7_SourceBufferEnable7_MASK)

/*! @name FETCHLAYER1_FRAMEDIMENSIONS - Output frame dimension. */
#define IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_FrameWidth_MASK)
#define IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_FrameHeight_MASK)
#define IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
#define IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
#define IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHLAYER1_FRAMEDIMENSIONS_EmptyFrame_MASK)

/*! @name FETCHLAYER1_FRAMERESAMPLING - Resampling options for output frame. */
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_StartX_MASK (0x3FU)
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_StartX_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_StartX_MASK)
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_StartY_MASK (0xFC0U)
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_StartY_SHIFT (6U)
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_StartY_MASK)
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_DeltaX_SHIFT (12U)
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_DeltaX_MASK)
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_DeltaY_SHIFT (18U)
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_DeltaY_MASK)
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
#define IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHLAYER1_FRAMERESAMPLING_SwapDirection_MASK)

/*! @name FETCHLAYER1_CONTROL - Shared common control settings for all layers. */
#define IRIS_MVPL_FETCHLAYER1_CONTROL_RawPixel_MASK (0x80U)
#define IRIS_MVPL_FETCHLAYER1_CONTROL_RawPixel_SHIFT (7U)
#define IRIS_MVPL_FETCHLAYER1_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONTROL_RawPixel_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONTROL_PaletteIdxWidth_MASK (0x700U)
#define IRIS_MVPL_FETCHLAYER1_CONTROL_PaletteIdxWidth_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_CONTROL_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONTROL_PaletteIdxWidth_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONTROL_PaletteIdxWidth_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONTROL_ClipColor_MASK (0x10000U)
#define IRIS_MVPL_FETCHLAYER1_CONTROL_ClipColor_SHIFT (16U)
#define IRIS_MVPL_FETCHLAYER1_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONTROL_ClipColor_MASK)
#define IRIS_MVPL_FETCHLAYER1_CONTROL_ClipLayer_MASK (0xE0000U)
#define IRIS_MVPL_FETCHLAYER1_CONTROL_ClipLayer_SHIFT (17U)
#define IRIS_MVPL_FETCHLAYER1_CONTROL_ClipLayer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONTROL_ClipLayer_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONTROL_ClipLayer_MASK)

/*! @name FETCHLAYER1_TRIGGERENABLE - Shadow load enable flags for all layers. */
#define IRIS_MVPL_FETCHLAYER1_TRIGGERENABLE_ShdLdReq_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER1_TRIGGERENABLE_ShdLdReq_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_TRIGGERENABLE_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_TRIGGERENABLE_ShdLdReq_SHIFT)) & IRIS_MVPL_FETCHLAYER1_TRIGGERENABLE_ShdLdReq_MASK)

/*! @name FETCHLAYER1_CONTROLTRIGGER - Shadow load trigger. */
#define IRIS_MVPL_FETCHLAYER1_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER1_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHLAYER1_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name FETCHLAYER1_START - Frame start trigger. */
#define IRIS_MVPL_FETCHLAYER1_START_Start_MASK   (0x1U)
#define IRIS_MVPL_FETCHLAYER1_START_Start_SHIFT  (0U)
#define IRIS_MVPL_FETCHLAYER1_START_Start(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_START_Start_SHIFT)) & IRIS_MVPL_FETCHLAYER1_START_Start_MASK)

/*! @name FETCHLAYER1_FETCHTYPE - Fetch unit type. */
#define IRIS_MVPL_FETCHLAYER1_FETCHTYPE_FetchType_MASK (0xFU)
#define IRIS_MVPL_FETCHLAYER1_FETCHTYPE_FetchType_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHLAYER1_FETCHTYPE_FetchType_MASK)

/*! @name FETCHLAYER1_BURSTBUFFERPROPERTIES - Burst buffer properties. */
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHLAYER1_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHLAYER1_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)

/*! @name FETCHLAYER1_STATUS - Status informations. */
#define IRIS_MVPL_FETCHLAYER1_STATUS_WriteTimeout_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER1_STATUS_WriteTimeout_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHLAYER1_STATUS_WriteTimeout_MASK)
#define IRIS_MVPL_FETCHLAYER1_STATUS_ReadTimeout_MASK (0x10U)
#define IRIS_MVPL_FETCHLAYER1_STATUS_ReadTimeout_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER1_STATUS_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_STATUS_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHLAYER1_STATUS_ReadTimeout_MASK)

/*! @name FETCHLAYER1_HIDDENSTATUS - Hidden status informations. */
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusBusy_MASK (0x1U)
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusBusy_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusBusy_MASK)
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusBuffersIdle_MASK)
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusRequest_MASK (0x20U)
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusRequest_SHIFT (5U)
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusRequest_MASK)
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusComplete_MASK (0x40U)
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusComplete_SHIFT (6U)
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_StatusComplete_MASK)
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
#define IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER1_HIDDENSTATUS_ShadowStatus_MASK)

/*! @name FETCHLAYER1_COLORPALETTE - Color palette look up table. */
#define IRIS_MVPL_FETCHLAYER1_COLORPALETTE_ColorPalette_MASK (0xFFFFFFU)
#define IRIS_MVPL_FETCHLAYER1_COLORPALETTE_ColorPalette_SHIFT (0U)
#define IRIS_MVPL_FETCHLAYER1_COLORPALETTE_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER1_COLORPALETTE_ColorPalette_SHIFT)) & IRIS_MVPL_FETCHLAYER1_COLORPALETTE_ColorPalette_MASK)

/*! @name GAMMACOR4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_GAMMACOR4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_GAMMACOR4_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_GAMMACOR4_LOCKUNLOCK_LockUnlock_MASK)

/*! @name GAMMACOR4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_GAMMACOR4_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_GAMMACOR4_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_GAMMACOR4_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_GAMMACOR4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_GAMMACOR4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_GAMMACOR4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_GAMMACOR4_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_GAMMACOR4_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_GAMMACOR4_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_GAMMACOR4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_GAMMACOR4_LOCKSTATUS_FreezeStatus_MASK)

/*! @name GAMMACOR4_STATICCONTROL - Static control settings. */
#define IRIS_MVPL_GAMMACOR4_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_GAMMACOR4_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR4_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_GAMMACOR4_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_GAMMACOR4_STATICCONTROL_BlueWriteEnable_MASK (0x2U)
#define IRIS_MVPL_GAMMACOR4_STATICCONTROL_BlueWriteEnable_SHIFT (1U)
#define IRIS_MVPL_GAMMACOR4_STATICCONTROL_BlueWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_STATICCONTROL_BlueWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR4_STATICCONTROL_BlueWriteEnable_MASK)
#define IRIS_MVPL_GAMMACOR4_STATICCONTROL_GreenWriteEnable_MASK (0x4U)
#define IRIS_MVPL_GAMMACOR4_STATICCONTROL_GreenWriteEnable_SHIFT (2U)
#define IRIS_MVPL_GAMMACOR4_STATICCONTROL_GreenWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_STATICCONTROL_GreenWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR4_STATICCONTROL_GreenWriteEnable_MASK)
#define IRIS_MVPL_GAMMACOR4_STATICCONTROL_RedWriteEnable_MASK (0x8U)
#define IRIS_MVPL_GAMMACOR4_STATICCONTROL_RedWriteEnable_SHIFT (3U)
#define IRIS_MVPL_GAMMACOR4_STATICCONTROL_RedWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_STATICCONTROL_RedWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR4_STATICCONTROL_RedWriteEnable_MASK)

/*! @name GAMMACOR4_LUTSTART - Start values for look-up table programming. */
#define IRIS_MVPL_GAMMACOR4_LUTSTART_StartBlue_MASK (0x3FFU)
#define IRIS_MVPL_GAMMACOR4_LUTSTART_StartBlue_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR4_LUTSTART_StartBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_LUTSTART_StartBlue_SHIFT)) & IRIS_MVPL_GAMMACOR4_LUTSTART_StartBlue_MASK)
#define IRIS_MVPL_GAMMACOR4_LUTSTART_StartGreen_MASK (0xFFC00U)
#define IRIS_MVPL_GAMMACOR4_LUTSTART_StartGreen_SHIFT (10U)
#define IRIS_MVPL_GAMMACOR4_LUTSTART_StartGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_LUTSTART_StartGreen_SHIFT)) & IRIS_MVPL_GAMMACOR4_LUTSTART_StartGreen_MASK)
#define IRIS_MVPL_GAMMACOR4_LUTSTART_StartRed_MASK (0x3FF00000U)
#define IRIS_MVPL_GAMMACOR4_LUTSTART_StartRed_SHIFT (20U)
#define IRIS_MVPL_GAMMACOR4_LUTSTART_StartRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_LUTSTART_StartRed_SHIFT)) & IRIS_MVPL_GAMMACOR4_LUTSTART_StartRed_MASK)

/*! @name GAMMACOR4_LUTDELTAS - Delta values for look-up table programming. */
#define IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaBlue_MASK (0x3FFU)
#define IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaBlue_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaBlue_SHIFT)) & IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaBlue_MASK)
#define IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaGreen_MASK (0xFFC00U)
#define IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaGreen_SHIFT (10U)
#define IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaGreen_SHIFT)) & IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaGreen_MASK)
#define IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaRed_MASK (0x3FF00000U)
#define IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaRed_SHIFT (20U)
#define IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaRed_SHIFT)) & IRIS_MVPL_GAMMACOR4_LUTDELTAS_DeltaRed_MASK)

/*! @name GAMMACOR4_CONTROL - Dynamic control settings. */
#define IRIS_MVPL_GAMMACOR4_CONTROL_Mode_MASK    (0x1U)
#define IRIS_MVPL_GAMMACOR4_CONTROL_Mode_SHIFT   (0U)
#define IRIS_MVPL_GAMMACOR4_CONTROL_Mode(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_CONTROL_Mode_SHIFT)) & IRIS_MVPL_GAMMACOR4_CONTROL_Mode_MASK)
#define IRIS_MVPL_GAMMACOR4_CONTROL_AlphaMask_MASK (0x10U)
#define IRIS_MVPL_GAMMACOR4_CONTROL_AlphaMask_SHIFT (4U)
#define IRIS_MVPL_GAMMACOR4_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_GAMMACOR4_CONTROL_AlphaMask_MASK)
#define IRIS_MVPL_GAMMACOR4_CONTROL_AlphaInvert_MASK (0x20U)
#define IRIS_MVPL_GAMMACOR4_CONTROL_AlphaInvert_SHIFT (5U)
#define IRIS_MVPL_GAMMACOR4_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_GAMMACOR4_CONTROL_AlphaInvert_MASK)

/*! @name GAMMACOR4_STATUS - Internal status bits. */
#define IRIS_MVPL_GAMMACOR4_STATUS_WriteTimeout_MASK (0x1U)
#define IRIS_MVPL_GAMMACOR4_STATUS_WriteTimeout_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR4_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_GAMMACOR4_STATUS_WriteTimeout_MASK)

/*! @name GAMMACOR4_LASTCONTROLWORD - Value of last received control word. */
#define IRIS_MVPL_GAMMACOR4_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_GAMMACOR4_LASTCONTROLWORD_L_VAL_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR4_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR4_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_GAMMACOR4_LASTCONTROLWORD_L_VAL_MASK)

/*! @name MATRIX4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_MATRIX4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_MATRIX4_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_MATRIX4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX4_LOCKUNLOCK_LockUnlock_MASK)

/*! @name MATRIX4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_MATRIX4_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_MATRIX4_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_MATRIX4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX4_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_MATRIX4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_MATRIX4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_MATRIX4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX4_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_MATRIX4_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_MATRIX4_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_MATRIX4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX4_LOCKSTATUS_FreezeStatus_MASK)

/*! @name MATRIX4_STATICCONTROL - Color Matrix static control register */
#define IRIS_MVPL_MATRIX4_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_MATRIX4_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_MATRIX4_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_MATRIX4_STATICCONTROL_ShdEn_MASK)

/*! @name MATRIX4_CONTROL - Color Matrix control register */
#define IRIS_MVPL_MATRIX4_CONTROL_MODE_MASK      (0x3U)
#define IRIS_MVPL_MATRIX4_CONTROL_MODE_SHIFT     (0U)
#define IRIS_MVPL_MATRIX4_CONTROL_MODE(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_CONTROL_MODE_SHIFT)) & IRIS_MVPL_MATRIX4_CONTROL_MODE_MASK)
#define IRIS_MVPL_MATRIX4_CONTROL_AlphaMask_MASK (0x10U)
#define IRIS_MVPL_MATRIX4_CONTROL_AlphaMask_SHIFT (4U)
#define IRIS_MVPL_MATRIX4_CONTROL_AlphaMask(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_MATRIX4_CONTROL_AlphaMask_MASK)
#define IRIS_MVPL_MATRIX4_CONTROL_AlphaInvert_MASK (0x20U)
#define IRIS_MVPL_MATRIX4_CONTROL_AlphaInvert_SHIFT (5U)
#define IRIS_MVPL_MATRIX4_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_MATRIX4_CONTROL_AlphaInvert_MASK)

/*! @name MATRIX4_RED0 - Matrix values for calculation of the red output value. */
#define IRIS_MVPL_MATRIX4_RED0_A11_MASK          (0x1FFFU)
#define IRIS_MVPL_MATRIX4_RED0_A11_SHIFT         (0U)
#define IRIS_MVPL_MATRIX4_RED0_A11(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_RED0_A11_SHIFT)) & IRIS_MVPL_MATRIX4_RED0_A11_MASK)
#define IRIS_MVPL_MATRIX4_RED0_A12_MASK          (0x1FFF0000U)
#define IRIS_MVPL_MATRIX4_RED0_A12_SHIFT         (16U)
#define IRIS_MVPL_MATRIX4_RED0_A12(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_RED0_A12_SHIFT)) & IRIS_MVPL_MATRIX4_RED0_A12_MASK)

/*! @name MATRIX4_RED1 - Matrix values for calculation of the red output value. */
#define IRIS_MVPL_MATRIX4_RED1_A13_MASK          (0x1FFFU)
#define IRIS_MVPL_MATRIX4_RED1_A13_SHIFT         (0U)
#define IRIS_MVPL_MATRIX4_RED1_A13(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_RED1_A13_SHIFT)) & IRIS_MVPL_MATRIX4_RED1_A13_MASK)
#define IRIS_MVPL_MATRIX4_RED1_A14_MASK          (0x1FFF0000U)
#define IRIS_MVPL_MATRIX4_RED1_A14_SHIFT         (16U)
#define IRIS_MVPL_MATRIX4_RED1_A14(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_RED1_A14_SHIFT)) & IRIS_MVPL_MATRIX4_RED1_A14_MASK)

/*! @name MATRIX4_GREEN0 - Matrix values for calculation of the green output value. */
#define IRIS_MVPL_MATRIX4_GREEN0_A21_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX4_GREEN0_A21_SHIFT       (0U)
#define IRIS_MVPL_MATRIX4_GREEN0_A21(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_GREEN0_A21_SHIFT)) & IRIS_MVPL_MATRIX4_GREEN0_A21_MASK)
#define IRIS_MVPL_MATRIX4_GREEN0_A22_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX4_GREEN0_A22_SHIFT       (16U)
#define IRIS_MVPL_MATRIX4_GREEN0_A22(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_GREEN0_A22_SHIFT)) & IRIS_MVPL_MATRIX4_GREEN0_A22_MASK)

/*! @name MATRIX4_GREEN1 - Matrix values for calculation of the green output value. */
#define IRIS_MVPL_MATRIX4_GREEN1_A23_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX4_GREEN1_A23_SHIFT       (0U)
#define IRIS_MVPL_MATRIX4_GREEN1_A23(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_GREEN1_A23_SHIFT)) & IRIS_MVPL_MATRIX4_GREEN1_A23_MASK)
#define IRIS_MVPL_MATRIX4_GREEN1_A24_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX4_GREEN1_A24_SHIFT       (16U)
#define IRIS_MVPL_MATRIX4_GREEN1_A24(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_GREEN1_A24_SHIFT)) & IRIS_MVPL_MATRIX4_GREEN1_A24_MASK)

/*! @name MATRIX4_BLUE0 - Matrix values for calculation of the blue output value. */
#define IRIS_MVPL_MATRIX4_BLUE0_A31_MASK         (0x1FFFU)
#define IRIS_MVPL_MATRIX4_BLUE0_A31_SHIFT        (0U)
#define IRIS_MVPL_MATRIX4_BLUE0_A31(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_BLUE0_A31_SHIFT)) & IRIS_MVPL_MATRIX4_BLUE0_A31_MASK)
#define IRIS_MVPL_MATRIX4_BLUE0_A32_MASK         (0x1FFF0000U)
#define IRIS_MVPL_MATRIX4_BLUE0_A32_SHIFT        (16U)
#define IRIS_MVPL_MATRIX4_BLUE0_A32(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_BLUE0_A32_SHIFT)) & IRIS_MVPL_MATRIX4_BLUE0_A32_MASK)

/*! @name MATRIX4_BLUE1 - Matrix values for calculation of the blue output value. */
#define IRIS_MVPL_MATRIX4_BLUE1_A33_MASK         (0x1FFFU)
#define IRIS_MVPL_MATRIX4_BLUE1_A33_SHIFT        (0U)
#define IRIS_MVPL_MATRIX4_BLUE1_A33(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_BLUE1_A33_SHIFT)) & IRIS_MVPL_MATRIX4_BLUE1_A33_MASK)
#define IRIS_MVPL_MATRIX4_BLUE1_A34_MASK         (0x1FFF0000U)
#define IRIS_MVPL_MATRIX4_BLUE1_A34_SHIFT        (16U)
#define IRIS_MVPL_MATRIX4_BLUE1_A34(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_BLUE1_A34_SHIFT)) & IRIS_MVPL_MATRIX4_BLUE1_A34_MASK)

/*! @name MATRIX4_ALPHA0 - Matrix values for calculation of the alpha output value. */
#define IRIS_MVPL_MATRIX4_ALPHA0_A41_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX4_ALPHA0_A41_SHIFT       (0U)
#define IRIS_MVPL_MATRIX4_ALPHA0_A41(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_ALPHA0_A41_SHIFT)) & IRIS_MVPL_MATRIX4_ALPHA0_A41_MASK)
#define IRIS_MVPL_MATRIX4_ALPHA0_A42_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX4_ALPHA0_A42_SHIFT       (16U)
#define IRIS_MVPL_MATRIX4_ALPHA0_A42(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_ALPHA0_A42_SHIFT)) & IRIS_MVPL_MATRIX4_ALPHA0_A42_MASK)

/*! @name MATRIX4_ALPHA1 - Matrix values for calculation of the alpha output value. */
#define IRIS_MVPL_MATRIX4_ALPHA1_A43_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX4_ALPHA1_A43_SHIFT       (0U)
#define IRIS_MVPL_MATRIX4_ALPHA1_A43(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_ALPHA1_A43_SHIFT)) & IRIS_MVPL_MATRIX4_ALPHA1_A43_MASK)
#define IRIS_MVPL_MATRIX4_ALPHA1_A44_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX4_ALPHA1_A44_SHIFT       (16U)
#define IRIS_MVPL_MATRIX4_ALPHA1_A44(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_ALPHA1_A44_SHIFT)) & IRIS_MVPL_MATRIX4_ALPHA1_A44_MASK)

/*! @name MATRIX4_OFFSETVECTOR0 - Offset vectors for red and green output. */
#define IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C1_MASK  (0x1FFFU)
#define IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C1_SHIFT (0U)
#define IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C1(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C1_SHIFT)) & IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C1_MASK)
#define IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C2_MASK  (0x1FFF0000U)
#define IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C2_SHIFT (16U)
#define IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C2(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C2_SHIFT)) & IRIS_MVPL_MATRIX4_OFFSETVECTOR0_C2_MASK)

/*! @name MATRIX4_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */
#define IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C3_MASK  (0x1FFFU)
#define IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C3_SHIFT (0U)
#define IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C3(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C3_SHIFT)) & IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C3_MASK)
#define IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C4_MASK  (0x1FFF0000U)
#define IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C4_SHIFT (16U)
#define IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C4(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C4_SHIFT)) & IRIS_MVPL_MATRIX4_OFFSETVECTOR1_C4_MASK)

/*! @name MATRIX4_LASTCONTROLWORD - Value of last received control word, for debugging. */
#define IRIS_MVPL_MATRIX4_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_MATRIX4_LASTCONTROLWORD_L_VAL_SHIFT (0U)
#define IRIS_MVPL_MATRIX4_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_MATRIX4_LASTCONTROLWORD_L_VAL_MASK)

/*! @name HSCALER4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_HSCALER4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_HSCALER4_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_HSCALER4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_HSCALER4_LOCKUNLOCK_LockUnlock_MASK)

/*! @name HSCALER4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_HSCALER4_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_HSCALER4_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_HSCALER4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_HSCALER4_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_HSCALER4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_HSCALER4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_HSCALER4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_HSCALER4_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_HSCALER4_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_HSCALER4_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_HSCALER4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_HSCALER4_LOCKSTATUS_FreezeStatus_MASK)

/*! @name HSCALER4_STATICCONTROL - Static control settings that must typically be setup once only. */
#define IRIS_MVPL_HSCALER4_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_HSCALER4_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_HSCALER4_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_HSCALER4_STATICCONTROL_ShdEn_MASK)

/*! @name HSCALER4_SETUP1 - Phase interpolator setup. */
#define IRIS_MVPL_HSCALER4_SETUP1_scale_factor_MASK (0xFFFFFU)
#define IRIS_MVPL_HSCALER4_SETUP1_scale_factor_SHIFT (0U)
#define IRIS_MVPL_HSCALER4_SETUP1_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_SETUP1_scale_factor_SHIFT)) & IRIS_MVPL_HSCALER4_SETUP1_scale_factor_MASK)

/*! @name HSCALER4_SETUP2 - Phase interpolator setup. */
#define IRIS_MVPL_HSCALER4_SETUP2_phase_offset_MASK (0x1FFFFFU)
#define IRIS_MVPL_HSCALER4_SETUP2_phase_offset_SHIFT (0U)
#define IRIS_MVPL_HSCALER4_SETUP2_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_SETUP2_phase_offset_SHIFT)) & IRIS_MVPL_HSCALER4_SETUP2_phase_offset_MASK)

/*! @name HSCALER4_CONTROL - Scaler operation control. */
#define IRIS_MVPL_HSCALER4_CONTROL_mode_MASK     (0x1U)
#define IRIS_MVPL_HSCALER4_CONTROL_mode_SHIFT    (0U)
#define IRIS_MVPL_HSCALER4_CONTROL_mode(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_CONTROL_mode_SHIFT)) & IRIS_MVPL_HSCALER4_CONTROL_mode_MASK)
#define IRIS_MVPL_HSCALER4_CONTROL_scale_mode_MASK (0x10U)
#define IRIS_MVPL_HSCALER4_CONTROL_scale_mode_SHIFT (4U)
#define IRIS_MVPL_HSCALER4_CONTROL_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_CONTROL_scale_mode_SHIFT)) & IRIS_MVPL_HSCALER4_CONTROL_scale_mode_MASK)
#define IRIS_MVPL_HSCALER4_CONTROL_filter_mode_MASK (0x100U)
#define IRIS_MVPL_HSCALER4_CONTROL_filter_mode_SHIFT (8U)
#define IRIS_MVPL_HSCALER4_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_HSCALER4_CONTROL_filter_mode_MASK)
#define IRIS_MVPL_HSCALER4_CONTROL_output_size_MASK (0x3FFF0000U)
#define IRIS_MVPL_HSCALER4_CONTROL_output_size_SHIFT (16U)
#define IRIS_MVPL_HSCALER4_CONTROL_output_size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_CONTROL_output_size_SHIFT)) & IRIS_MVPL_HSCALER4_CONTROL_output_size_MASK)

/*! @name VSCALER4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_VSCALER4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_VSCALER4_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_VSCALER4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_VSCALER4_LOCKUNLOCK_LockUnlock_MASK)

/*! @name VSCALER4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_VSCALER4_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_VSCALER4_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_VSCALER4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_VSCALER4_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_VSCALER4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_VSCALER4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_VSCALER4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_VSCALER4_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_VSCALER4_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_VSCALER4_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_VSCALER4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_VSCALER4_LOCKSTATUS_FreezeStatus_MASK)

/*! @name VSCALER4_STATICCONTROL - Static control settings that must typically be setup once only. */
#define IRIS_MVPL_VSCALER4_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_VSCALER4_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_VSCALER4_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_VSCALER4_STATICCONTROL_ShdEn_MASK)

/*! @name VSCALER4_SETUP1 - Phase interpolator setup. */
#define IRIS_MVPL_VSCALER4_SETUP1_scale_factor_MASK (0xFFFFFU)
#define IRIS_MVPL_VSCALER4_SETUP1_scale_factor_SHIFT (0U)
#define IRIS_MVPL_VSCALER4_SETUP1_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_SETUP1_scale_factor_SHIFT)) & IRIS_MVPL_VSCALER4_SETUP1_scale_factor_MASK)

/*! @name VSCALER4_SETUP2 - Phase interpolator setup, selected if input and output field polarity is 0. */
#define IRIS_MVPL_VSCALER4_SETUP2_phase_offset_MASK (0x1FFFFFU)
#define IRIS_MVPL_VSCALER4_SETUP2_phase_offset_SHIFT (0U)
#define IRIS_MVPL_VSCALER4_SETUP2_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_SETUP2_phase_offset_SHIFT)) & IRIS_MVPL_VSCALER4_SETUP2_phase_offset_MASK)

/*! @name VSCALER4_SETUP3 - Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0. */
#define IRIS_MVPL_VSCALER4_SETUP3_phase_offset1_MASK (0x1FFFFFU)
#define IRIS_MVPL_VSCALER4_SETUP3_phase_offset1_SHIFT (0U)
#define IRIS_MVPL_VSCALER4_SETUP3_phase_offset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_SETUP3_phase_offset1_SHIFT)) & IRIS_MVPL_VSCALER4_SETUP3_phase_offset1_MASK)

/*! @name VSCALER4_SETUP4 - Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1. */
#define IRIS_MVPL_VSCALER4_SETUP4_phase_offset2_MASK (0x1FFFFFU)
#define IRIS_MVPL_VSCALER4_SETUP4_phase_offset2_SHIFT (0U)
#define IRIS_MVPL_VSCALER4_SETUP4_phase_offset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_SETUP4_phase_offset2_SHIFT)) & IRIS_MVPL_VSCALER4_SETUP4_phase_offset2_MASK)

/*! @name VSCALER4_SETUP5 - Phase interpolator setup, selected if input and output field polarity is 1. */
#define IRIS_MVPL_VSCALER4_SETUP5_phase_offset3_MASK (0x1FFFFFU)
#define IRIS_MVPL_VSCALER4_SETUP5_phase_offset3_SHIFT (0U)
#define IRIS_MVPL_VSCALER4_SETUP5_phase_offset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_SETUP5_phase_offset3_SHIFT)) & IRIS_MVPL_VSCALER4_SETUP5_phase_offset3_MASK)

/*! @name VSCALER4_CONTROL - Scaler operation control. */
#define IRIS_MVPL_VSCALER4_CONTROL_mode_MASK     (0x1U)
#define IRIS_MVPL_VSCALER4_CONTROL_mode_SHIFT    (0U)
#define IRIS_MVPL_VSCALER4_CONTROL_mode(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_CONTROL_mode_SHIFT)) & IRIS_MVPL_VSCALER4_CONTROL_mode_MASK)
#define IRIS_MVPL_VSCALER4_CONTROL_scale_mode_MASK (0x10U)
#define IRIS_MVPL_VSCALER4_CONTROL_scale_mode_SHIFT (4U)
#define IRIS_MVPL_VSCALER4_CONTROL_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_CONTROL_scale_mode_SHIFT)) & IRIS_MVPL_VSCALER4_CONTROL_scale_mode_MASK)
#define IRIS_MVPL_VSCALER4_CONTROL_filter_mode_MASK (0x100U)
#define IRIS_MVPL_VSCALER4_CONTROL_filter_mode_SHIFT (8U)
#define IRIS_MVPL_VSCALER4_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_VSCALER4_CONTROL_filter_mode_MASK)
#define IRIS_MVPL_VSCALER4_CONTROL_field_mode_MASK (0x3000U)
#define IRIS_MVPL_VSCALER4_CONTROL_field_mode_SHIFT (12U)
#define IRIS_MVPL_VSCALER4_CONTROL_field_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_CONTROL_field_mode_SHIFT)) & IRIS_MVPL_VSCALER4_CONTROL_field_mode_MASK)
#define IRIS_MVPL_VSCALER4_CONTROL_output_size_MASK (0x3FFF0000U)
#define IRIS_MVPL_VSCALER4_CONTROL_output_size_SHIFT (16U)
#define IRIS_MVPL_VSCALER4_CONTROL_output_size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_CONTROL_output_size_SHIFT)) & IRIS_MVPL_VSCALER4_CONTROL_output_size_MASK)

/*! @name HISTOGRAM4_CONTROL - Controls some settings concerning input components and alpha mask. */
#define IRIS_MVPL_HISTOGRAM4_CONTROL_clip_en_MASK (0x1U)
#define IRIS_MVPL_HISTOGRAM4_CONTROL_clip_en_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_CONTROL_clip_en(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_CONTROL_clip_en_SHIFT)) & IRIS_MVPL_HISTOGRAM4_CONTROL_clip_en_MASK)
#define IRIS_MVPL_HISTOGRAM4_CONTROL_color_space_mode_MASK (0x30U)
#define IRIS_MVPL_HISTOGRAM4_CONTROL_color_space_mode_SHIFT (4U)
#define IRIS_MVPL_HISTOGRAM4_CONTROL_color_space_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_CONTROL_color_space_mode_SHIFT)) & IRIS_MVPL_HISTOGRAM4_CONTROL_color_space_mode_MASK)
#define IRIS_MVPL_HISTOGRAM4_CONTROL_lum_mode_MASK (0x300U)
#define IRIS_MVPL_HISTOGRAM4_CONTROL_lum_mode_SHIFT (8U)
#define IRIS_MVPL_HISTOGRAM4_CONTROL_lum_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_CONTROL_lum_mode_SHIFT)) & IRIS_MVPL_HISTOGRAM4_CONTROL_lum_mode_MASK)
#define IRIS_MVPL_HISTOGRAM4_CONTROL_AlphaMask_MASK (0x1000U)
#define IRIS_MVPL_HISTOGRAM4_CONTROL_AlphaMask_SHIFT (12U)
#define IRIS_MVPL_HISTOGRAM4_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_HISTOGRAM4_CONTROL_AlphaMask_MASK)
#define IRIS_MVPL_HISTOGRAM4_CONTROL_AlphaInvert_MASK (0x2000U)
#define IRIS_MVPL_HISTOGRAM4_CONTROL_AlphaInvert_SHIFT (13U)
#define IRIS_MVPL_HISTOGRAM4_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_HISTOGRAM4_CONTROL_AlphaInvert_MASK)

/*! @name HISTOGRAM4_BINPROPERTIES - Configures the histogram bins. */
#define IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_binnum_width_MASK (0x7U)
#define IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_binnum_width_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_binnum_width(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_binnum_width_SHIFT)) & IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_binnum_width_MASK)
#define IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_cnt_mode_MASK (0x10U)
#define IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_cnt_mode_SHIFT (4U)
#define IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_cnt_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_cnt_mode_SHIFT)) & IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_cnt_mode_MASK)
#define IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_bincnt_rd_mode_MASK (0x100U)
#define IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_bincnt_rd_mode_SHIFT (8U)
#define IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_bincnt_rd_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_bincnt_rd_mode_SHIFT)) & IRIS_MVPL_HISTOGRAM4_BINPROPERTIES_bincnt_rd_mode_MASK)

/*! @name HISTOGRAM4_BINCNTTHRESH - Bin counter threshold value. */
#define IRIS_MVPL_HISTOGRAM4_BINCNTTHRESH_bincnt_thresh_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_HISTOGRAM4_BINCNTTHRESH_bincnt_thresh_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_BINCNTTHRESH_bincnt_thresh(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_BINCNTTHRESH_bincnt_thresh_SHIFT)) & IRIS_MVPL_HISTOGRAM4_BINCNTTHRESH_bincnt_thresh_MASK)

/*! @name HISTOGRAM4_CLIPWINUPPERLEFT - Coordinates of upper left corner of clip window. */
#define IRIS_MVPL_HISTOGRAM4_CLIPWINUPPERLEFT_clip_x_MASK (0x3FFFU)
#define IRIS_MVPL_HISTOGRAM4_CLIPWINUPPERLEFT_clip_x_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_CLIPWINUPPERLEFT_clip_x(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_CLIPWINUPPERLEFT_clip_x_SHIFT)) & IRIS_MVPL_HISTOGRAM4_CLIPWINUPPERLEFT_clip_x_MASK)
#define IRIS_MVPL_HISTOGRAM4_CLIPWINUPPERLEFT_clip_y_MASK (0x3FFF0000U)
#define IRIS_MVPL_HISTOGRAM4_CLIPWINUPPERLEFT_clip_y_SHIFT (16U)
#define IRIS_MVPL_HISTOGRAM4_CLIPWINUPPERLEFT_clip_y(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_CLIPWINUPPERLEFT_clip_y_SHIFT)) & IRIS_MVPL_HISTOGRAM4_CLIPWINUPPERLEFT_clip_y_MASK)

/*! @name HISTOGRAM4_CLIPWINSIZE - Dimensions of clip window. */
#define IRIS_MVPL_HISTOGRAM4_CLIPWINSIZE_clip_width_MASK (0x3FFFU)
#define IRIS_MVPL_HISTOGRAM4_CLIPWINSIZE_clip_width_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_CLIPWINSIZE_clip_width(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_CLIPWINSIZE_clip_width_SHIFT)) & IRIS_MVPL_HISTOGRAM4_CLIPWINSIZE_clip_width_MASK)
#define IRIS_MVPL_HISTOGRAM4_CLIPWINSIZE_clip_height_MASK (0x3FFF0000U)
#define IRIS_MVPL_HISTOGRAM4_CLIPWINSIZE_clip_height_SHIFT (16U)
#define IRIS_MVPL_HISTOGRAM4_CLIPWINSIZE_clip_height(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_CLIPWINSIZE_clip_height_SHIFT)) & IRIS_MVPL_HISTOGRAM4_CLIPWINSIZE_clip_height_MASK)

/*! @name HISTOGRAM4_RSLTRDY - Measurement result status. */
#define IRIS_MVPL_HISTOGRAM4_RSLTRDY_rslt_rdy_MASK (0x1U)
#define IRIS_MVPL_HISTOGRAM4_RSLTRDY_rslt_rdy_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_RSLTRDY_rslt_rdy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTRDY_rslt_rdy_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTRDY_rslt_rdy_MASK)

/*! @name HISTOGRAM4_RSLTFRMINF - Additional information on the measurement results. */
#define IRIS_MVPL_HISTOGRAM4_RSLTFRMINF_frm_idx_MASK (0xFFU)
#define IRIS_MVPL_HISTOGRAM4_RSLTFRMINF_frm_idx_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_RSLTFRMINF_frm_idx(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTFRMINF_frm_idx_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTFRMINF_frm_idx_MASK)
#define IRIS_MVPL_HISTOGRAM4_RSLTFRMINF_fld_polarity_MASK (0x10000U)
#define IRIS_MVPL_HISTOGRAM4_RSLTFRMINF_fld_polarity_SHIFT (16U)
#define IRIS_MVPL_HISTOGRAM4_RSLTFRMINF_fld_polarity(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTFRMINF_fld_polarity_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTFRMINF_fld_polarity_MASK)

/*! @name HISTOGRAM4_RSLTCOMP0BINIDX - Results of frame measurement for component 0. */
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINIDX_comp0_binidx_maxcnt_MASK (0x3FU)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINIDX_comp0_binidx_maxcnt_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINIDX_comp0_binidx_maxcnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINIDX_comp0_binidx_maxcnt_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINIDX_comp0_binidx_maxcnt_MASK)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINIDX_comp0_binidx_nxt_MASK (0x3F0000U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINIDX_comp0_binidx_nxt_SHIFT (16U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINIDX_comp0_binidx_nxt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINIDX_comp0_binidx_nxt_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINIDX_comp0_binidx_nxt_MASK)

/*! @name HISTOGRAM4_RSLTCOMP1BINIDX - Results of frame measurement for component 1. */
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINIDX_comp1_binidx_maxcnt_MASK (0x3FU)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINIDX_comp1_binidx_maxcnt_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINIDX_comp1_binidx_maxcnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINIDX_comp1_binidx_maxcnt_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINIDX_comp1_binidx_maxcnt_MASK)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINIDX_comp1_binidx_nxt_MASK (0x3F0000U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINIDX_comp1_binidx_nxt_SHIFT (16U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINIDX_comp1_binidx_nxt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINIDX_comp1_binidx_nxt_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINIDX_comp1_binidx_nxt_MASK)

/*! @name HISTOGRAM4_RSLTCOMP2BINIDX - Results of frame measurement for component 2. */
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINIDX_comp2_binidx_maxcnt_MASK (0x3FU)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINIDX_comp2_binidx_maxcnt_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINIDX_comp2_binidx_maxcnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINIDX_comp2_binidx_maxcnt_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINIDX_comp2_binidx_maxcnt_MASK)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINIDX_comp2_binidx_nxt_MASK (0x3F0000U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINIDX_comp2_binidx_nxt_SHIFT (16U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINIDX_comp2_binidx_nxt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINIDX_comp2_binidx_nxt_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINIDX_comp2_binidx_nxt_MASK)

/*! @name HISTOGRAM4_RSLTCOMP0SUM - Sum of all component 0 values. */
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP0SUM_comp0_sum_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP0SUM_comp0_sum_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP0SUM_comp0_sum(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTCOMP0SUM_comp0_sum_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTCOMP0SUM_comp0_sum_MASK)

/*! @name HISTOGRAM4_RSLTCOMP1SUM - Sum of all component 1 values. */
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP1SUM_comp1_sum_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP1SUM_comp1_sum_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP1SUM_comp1_sum(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTCOMP1SUM_comp1_sum_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTCOMP1SUM_comp1_sum_MASK)

/*! @name HISTOGRAM4_RSLTCOMP2SUM - Sum of all component 2 values. */
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP2SUM_comp2_sum_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP2SUM_comp2_sum_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP2SUM_comp2_sum(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTCOMP2SUM_comp2_sum_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTCOMP2SUM_comp2_sum_MASK)

/*! @name HISTOGRAM4_RSLTCOMP0BINCNT - Bin counters of component 0 histogram. */
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINCNT_comp0_bincnt_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINCNT_comp0_bincnt_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINCNT_comp0_bincnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINCNT_comp0_bincnt_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTCOMP0BINCNT_comp0_bincnt_MASK)

/*! @name HISTOGRAM4_RSLTCOMP1BINCNT - Bin counters of component 1 histogram. */
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINCNT_comp1_bincnt_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINCNT_comp1_bincnt_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINCNT_comp1_bincnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINCNT_comp1_bincnt_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTCOMP1BINCNT_comp1_bincnt_MASK)

/*! @name HISTOGRAM4_RSLTCOMP2BINCNT - Bin counters of component 2 histogram. */
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINCNT_comp2_bincnt_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINCNT_comp2_bincnt_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINCNT_comp2_bincnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINCNT_comp2_bincnt_SHIFT)) & IRIS_MVPL_HISTOGRAM4_RSLTCOMP2BINCNT_comp2_bincnt_MASK)

/*! @name HISTOGRAM4_FRMSTRTTRIG - Triggers for loading shadow registers and starting measurement with next input frame. */
#define IRIS_MVPL_HISTOGRAM4_FRMSTRTTRIG_msrmnt_strt_trig_MASK (0x1U)
#define IRIS_MVPL_HISTOGRAM4_FRMSTRTTRIG_msrmnt_strt_trig_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM4_FRMSTRTTRIG_msrmnt_strt_trig(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM4_FRMSTRTTRIG_msrmnt_strt_trig_SHIFT)) & IRIS_MVPL_HISTOGRAM4_FRMSTRTTRIG_msrmnt_strt_trig_MASK)

/*! @name GAMMACOR5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_GAMMACOR5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_GAMMACOR5_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_GAMMACOR5_LOCKUNLOCK_LockUnlock_MASK)

/*! @name GAMMACOR5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_GAMMACOR5_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_GAMMACOR5_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_GAMMACOR5_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_GAMMACOR5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_GAMMACOR5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_GAMMACOR5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_GAMMACOR5_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_GAMMACOR5_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_GAMMACOR5_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_GAMMACOR5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_GAMMACOR5_LOCKSTATUS_FreezeStatus_MASK)

/*! @name GAMMACOR5_STATICCONTROL - Static control settings. */
#define IRIS_MVPL_GAMMACOR5_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_GAMMACOR5_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR5_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_GAMMACOR5_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_GAMMACOR5_STATICCONTROL_BlueWriteEnable_MASK (0x2U)
#define IRIS_MVPL_GAMMACOR5_STATICCONTROL_BlueWriteEnable_SHIFT (1U)
#define IRIS_MVPL_GAMMACOR5_STATICCONTROL_BlueWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_STATICCONTROL_BlueWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR5_STATICCONTROL_BlueWriteEnable_MASK)
#define IRIS_MVPL_GAMMACOR5_STATICCONTROL_GreenWriteEnable_MASK (0x4U)
#define IRIS_MVPL_GAMMACOR5_STATICCONTROL_GreenWriteEnable_SHIFT (2U)
#define IRIS_MVPL_GAMMACOR5_STATICCONTROL_GreenWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_STATICCONTROL_GreenWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR5_STATICCONTROL_GreenWriteEnable_MASK)
#define IRIS_MVPL_GAMMACOR5_STATICCONTROL_RedWriteEnable_MASK (0x8U)
#define IRIS_MVPL_GAMMACOR5_STATICCONTROL_RedWriteEnable_SHIFT (3U)
#define IRIS_MVPL_GAMMACOR5_STATICCONTROL_RedWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_STATICCONTROL_RedWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR5_STATICCONTROL_RedWriteEnable_MASK)

/*! @name GAMMACOR5_LUTSTART - Start values for look-up table programming. */
#define IRIS_MVPL_GAMMACOR5_LUTSTART_StartBlue_MASK (0x3FFU)
#define IRIS_MVPL_GAMMACOR5_LUTSTART_StartBlue_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR5_LUTSTART_StartBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_LUTSTART_StartBlue_SHIFT)) & IRIS_MVPL_GAMMACOR5_LUTSTART_StartBlue_MASK)
#define IRIS_MVPL_GAMMACOR5_LUTSTART_StartGreen_MASK (0xFFC00U)
#define IRIS_MVPL_GAMMACOR5_LUTSTART_StartGreen_SHIFT (10U)
#define IRIS_MVPL_GAMMACOR5_LUTSTART_StartGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_LUTSTART_StartGreen_SHIFT)) & IRIS_MVPL_GAMMACOR5_LUTSTART_StartGreen_MASK)
#define IRIS_MVPL_GAMMACOR5_LUTSTART_StartRed_MASK (0x3FF00000U)
#define IRIS_MVPL_GAMMACOR5_LUTSTART_StartRed_SHIFT (20U)
#define IRIS_MVPL_GAMMACOR5_LUTSTART_StartRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_LUTSTART_StartRed_SHIFT)) & IRIS_MVPL_GAMMACOR5_LUTSTART_StartRed_MASK)

/*! @name GAMMACOR5_LUTDELTAS - Delta values for look-up table programming. */
#define IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaBlue_MASK (0x3FFU)
#define IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaBlue_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaBlue_SHIFT)) & IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaBlue_MASK)
#define IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaGreen_MASK (0xFFC00U)
#define IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaGreen_SHIFT (10U)
#define IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaGreen_SHIFT)) & IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaGreen_MASK)
#define IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaRed_MASK (0x3FF00000U)
#define IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaRed_SHIFT (20U)
#define IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaRed_SHIFT)) & IRIS_MVPL_GAMMACOR5_LUTDELTAS_DeltaRed_MASK)

/*! @name GAMMACOR5_CONTROL - Dynamic control settings. */
#define IRIS_MVPL_GAMMACOR5_CONTROL_Mode_MASK    (0x1U)
#define IRIS_MVPL_GAMMACOR5_CONTROL_Mode_SHIFT   (0U)
#define IRIS_MVPL_GAMMACOR5_CONTROL_Mode(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_CONTROL_Mode_SHIFT)) & IRIS_MVPL_GAMMACOR5_CONTROL_Mode_MASK)
#define IRIS_MVPL_GAMMACOR5_CONTROL_AlphaMask_MASK (0x10U)
#define IRIS_MVPL_GAMMACOR5_CONTROL_AlphaMask_SHIFT (4U)
#define IRIS_MVPL_GAMMACOR5_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_GAMMACOR5_CONTROL_AlphaMask_MASK)
#define IRIS_MVPL_GAMMACOR5_CONTROL_AlphaInvert_MASK (0x20U)
#define IRIS_MVPL_GAMMACOR5_CONTROL_AlphaInvert_SHIFT (5U)
#define IRIS_MVPL_GAMMACOR5_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_GAMMACOR5_CONTROL_AlphaInvert_MASK)

/*! @name GAMMACOR5_STATUS - Internal status bits. */
#define IRIS_MVPL_GAMMACOR5_STATUS_WriteTimeout_MASK (0x1U)
#define IRIS_MVPL_GAMMACOR5_STATUS_WriteTimeout_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR5_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_GAMMACOR5_STATUS_WriteTimeout_MASK)

/*! @name GAMMACOR5_LASTCONTROLWORD - Value of last received control word. */
#define IRIS_MVPL_GAMMACOR5_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_GAMMACOR5_LASTCONTROLWORD_L_VAL_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR5_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR5_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_GAMMACOR5_LASTCONTROLWORD_L_VAL_MASK)

/*! @name MATRIX5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_MATRIX5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_MATRIX5_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_MATRIX5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX5_LOCKUNLOCK_LockUnlock_MASK)

/*! @name MATRIX5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_MATRIX5_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_MATRIX5_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_MATRIX5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX5_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_MATRIX5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_MATRIX5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_MATRIX5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX5_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_MATRIX5_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_MATRIX5_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_MATRIX5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX5_LOCKSTATUS_FreezeStatus_MASK)

/*! @name MATRIX5_STATICCONTROL - Color Matrix static control register */
#define IRIS_MVPL_MATRIX5_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_MATRIX5_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_MATRIX5_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_MATRIX5_STATICCONTROL_ShdEn_MASK)

/*! @name MATRIX5_CONTROL - Color Matrix control register */
#define IRIS_MVPL_MATRIX5_CONTROL_MODE_MASK      (0x3U)
#define IRIS_MVPL_MATRIX5_CONTROL_MODE_SHIFT     (0U)
#define IRIS_MVPL_MATRIX5_CONTROL_MODE(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_CONTROL_MODE_SHIFT)) & IRIS_MVPL_MATRIX5_CONTROL_MODE_MASK)
#define IRIS_MVPL_MATRIX5_CONTROL_AlphaMask_MASK (0x10U)
#define IRIS_MVPL_MATRIX5_CONTROL_AlphaMask_SHIFT (4U)
#define IRIS_MVPL_MATRIX5_CONTROL_AlphaMask(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_MATRIX5_CONTROL_AlphaMask_MASK)
#define IRIS_MVPL_MATRIX5_CONTROL_AlphaInvert_MASK (0x20U)
#define IRIS_MVPL_MATRIX5_CONTROL_AlphaInvert_SHIFT (5U)
#define IRIS_MVPL_MATRIX5_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_MATRIX5_CONTROL_AlphaInvert_MASK)

/*! @name MATRIX5_RED0 - Matrix values for calculation of the red output value. */
#define IRIS_MVPL_MATRIX5_RED0_A11_MASK          (0x1FFFU)
#define IRIS_MVPL_MATRIX5_RED0_A11_SHIFT         (0U)
#define IRIS_MVPL_MATRIX5_RED0_A11(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_RED0_A11_SHIFT)) & IRIS_MVPL_MATRIX5_RED0_A11_MASK)
#define IRIS_MVPL_MATRIX5_RED0_A12_MASK          (0x1FFF0000U)
#define IRIS_MVPL_MATRIX5_RED0_A12_SHIFT         (16U)
#define IRIS_MVPL_MATRIX5_RED0_A12(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_RED0_A12_SHIFT)) & IRIS_MVPL_MATRIX5_RED0_A12_MASK)

/*! @name MATRIX5_RED1 - Matrix values for calculation of the red output value. */
#define IRIS_MVPL_MATRIX5_RED1_A13_MASK          (0x1FFFU)
#define IRIS_MVPL_MATRIX5_RED1_A13_SHIFT         (0U)
#define IRIS_MVPL_MATRIX5_RED1_A13(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_RED1_A13_SHIFT)) & IRIS_MVPL_MATRIX5_RED1_A13_MASK)
#define IRIS_MVPL_MATRIX5_RED1_A14_MASK          (0x1FFF0000U)
#define IRIS_MVPL_MATRIX5_RED1_A14_SHIFT         (16U)
#define IRIS_MVPL_MATRIX5_RED1_A14(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_RED1_A14_SHIFT)) & IRIS_MVPL_MATRIX5_RED1_A14_MASK)

/*! @name MATRIX5_GREEN0 - Matrix values for calculation of the green output value. */
#define IRIS_MVPL_MATRIX5_GREEN0_A21_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX5_GREEN0_A21_SHIFT       (0U)
#define IRIS_MVPL_MATRIX5_GREEN0_A21(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_GREEN0_A21_SHIFT)) & IRIS_MVPL_MATRIX5_GREEN0_A21_MASK)
#define IRIS_MVPL_MATRIX5_GREEN0_A22_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX5_GREEN0_A22_SHIFT       (16U)
#define IRIS_MVPL_MATRIX5_GREEN0_A22(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_GREEN0_A22_SHIFT)) & IRIS_MVPL_MATRIX5_GREEN0_A22_MASK)

/*! @name MATRIX5_GREEN1 - Matrix values for calculation of the green output value. */
#define IRIS_MVPL_MATRIX5_GREEN1_A23_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX5_GREEN1_A23_SHIFT       (0U)
#define IRIS_MVPL_MATRIX5_GREEN1_A23(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_GREEN1_A23_SHIFT)) & IRIS_MVPL_MATRIX5_GREEN1_A23_MASK)
#define IRIS_MVPL_MATRIX5_GREEN1_A24_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX5_GREEN1_A24_SHIFT       (16U)
#define IRIS_MVPL_MATRIX5_GREEN1_A24(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_GREEN1_A24_SHIFT)) & IRIS_MVPL_MATRIX5_GREEN1_A24_MASK)

/*! @name MATRIX5_BLUE0 - Matrix values for calculation of the blue output value. */
#define IRIS_MVPL_MATRIX5_BLUE0_A31_MASK         (0x1FFFU)
#define IRIS_MVPL_MATRIX5_BLUE0_A31_SHIFT        (0U)
#define IRIS_MVPL_MATRIX5_BLUE0_A31(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_BLUE0_A31_SHIFT)) & IRIS_MVPL_MATRIX5_BLUE0_A31_MASK)
#define IRIS_MVPL_MATRIX5_BLUE0_A32_MASK         (0x1FFF0000U)
#define IRIS_MVPL_MATRIX5_BLUE0_A32_SHIFT        (16U)
#define IRIS_MVPL_MATRIX5_BLUE0_A32(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_BLUE0_A32_SHIFT)) & IRIS_MVPL_MATRIX5_BLUE0_A32_MASK)

/*! @name MATRIX5_BLUE1 - Matrix values for calculation of the blue output value. */
#define IRIS_MVPL_MATRIX5_BLUE1_A33_MASK         (0x1FFFU)
#define IRIS_MVPL_MATRIX5_BLUE1_A33_SHIFT        (0U)
#define IRIS_MVPL_MATRIX5_BLUE1_A33(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_BLUE1_A33_SHIFT)) & IRIS_MVPL_MATRIX5_BLUE1_A33_MASK)
#define IRIS_MVPL_MATRIX5_BLUE1_A34_MASK         (0x1FFF0000U)
#define IRIS_MVPL_MATRIX5_BLUE1_A34_SHIFT        (16U)
#define IRIS_MVPL_MATRIX5_BLUE1_A34(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_BLUE1_A34_SHIFT)) & IRIS_MVPL_MATRIX5_BLUE1_A34_MASK)

/*! @name MATRIX5_ALPHA0 - Matrix values for calculation of the alpha output value. */
#define IRIS_MVPL_MATRIX5_ALPHA0_A41_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX5_ALPHA0_A41_SHIFT       (0U)
#define IRIS_MVPL_MATRIX5_ALPHA0_A41(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_ALPHA0_A41_SHIFT)) & IRIS_MVPL_MATRIX5_ALPHA0_A41_MASK)
#define IRIS_MVPL_MATRIX5_ALPHA0_A42_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX5_ALPHA0_A42_SHIFT       (16U)
#define IRIS_MVPL_MATRIX5_ALPHA0_A42(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_ALPHA0_A42_SHIFT)) & IRIS_MVPL_MATRIX5_ALPHA0_A42_MASK)

/*! @name MATRIX5_ALPHA1 - Matrix values for calculation of the alpha output value. */
#define IRIS_MVPL_MATRIX5_ALPHA1_A43_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX5_ALPHA1_A43_SHIFT       (0U)
#define IRIS_MVPL_MATRIX5_ALPHA1_A43(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_ALPHA1_A43_SHIFT)) & IRIS_MVPL_MATRIX5_ALPHA1_A43_MASK)
#define IRIS_MVPL_MATRIX5_ALPHA1_A44_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX5_ALPHA1_A44_SHIFT       (16U)
#define IRIS_MVPL_MATRIX5_ALPHA1_A44(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_ALPHA1_A44_SHIFT)) & IRIS_MVPL_MATRIX5_ALPHA1_A44_MASK)

/*! @name MATRIX5_OFFSETVECTOR0 - Offset vectors for red and green output. */
#define IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C1_MASK  (0x1FFFU)
#define IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C1_SHIFT (0U)
#define IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C1(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C1_SHIFT)) & IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C1_MASK)
#define IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C2_MASK  (0x1FFF0000U)
#define IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C2_SHIFT (16U)
#define IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C2(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C2_SHIFT)) & IRIS_MVPL_MATRIX5_OFFSETVECTOR0_C2_MASK)

/*! @name MATRIX5_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */
#define IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C3_MASK  (0x1FFFU)
#define IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C3_SHIFT (0U)
#define IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C3(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C3_SHIFT)) & IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C3_MASK)
#define IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C4_MASK  (0x1FFF0000U)
#define IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C4_SHIFT (16U)
#define IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C4(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C4_SHIFT)) & IRIS_MVPL_MATRIX5_OFFSETVECTOR1_C4_MASK)

/*! @name MATRIX5_LASTCONTROLWORD - Value of last received control word, for debugging. */
#define IRIS_MVPL_MATRIX5_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_MATRIX5_LASTCONTROLWORD_L_VAL_SHIFT (0U)
#define IRIS_MVPL_MATRIX5_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_MATRIX5_LASTCONTROLWORD_L_VAL_MASK)

/*! @name HSCALER5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_HSCALER5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_HSCALER5_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_HSCALER5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_HSCALER5_LOCKUNLOCK_LockUnlock_MASK)

/*! @name HSCALER5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_HSCALER5_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_HSCALER5_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_HSCALER5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_HSCALER5_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_HSCALER5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_HSCALER5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_HSCALER5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_HSCALER5_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_HSCALER5_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_HSCALER5_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_HSCALER5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_HSCALER5_LOCKSTATUS_FreezeStatus_MASK)

/*! @name HSCALER5_STATICCONTROL - Static control settings that must typically be setup once only. */
#define IRIS_MVPL_HSCALER5_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_HSCALER5_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_HSCALER5_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_HSCALER5_STATICCONTROL_ShdEn_MASK)

/*! @name HSCALER5_SETUP1 - Phase interpolator setup. */
#define IRIS_MVPL_HSCALER5_SETUP1_scale_factor_MASK (0xFFFFFU)
#define IRIS_MVPL_HSCALER5_SETUP1_scale_factor_SHIFT (0U)
#define IRIS_MVPL_HSCALER5_SETUP1_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_SETUP1_scale_factor_SHIFT)) & IRIS_MVPL_HSCALER5_SETUP1_scale_factor_MASK)

/*! @name HSCALER5_SETUP2 - Phase interpolator setup. */
#define IRIS_MVPL_HSCALER5_SETUP2_phase_offset_MASK (0x1FFFFFU)
#define IRIS_MVPL_HSCALER5_SETUP2_phase_offset_SHIFT (0U)
#define IRIS_MVPL_HSCALER5_SETUP2_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_SETUP2_phase_offset_SHIFT)) & IRIS_MVPL_HSCALER5_SETUP2_phase_offset_MASK)

/*! @name HSCALER5_CONTROL - Scaler operation control. */
#define IRIS_MVPL_HSCALER5_CONTROL_mode_MASK     (0x1U)
#define IRIS_MVPL_HSCALER5_CONTROL_mode_SHIFT    (0U)
#define IRIS_MVPL_HSCALER5_CONTROL_mode(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_CONTROL_mode_SHIFT)) & IRIS_MVPL_HSCALER5_CONTROL_mode_MASK)
#define IRIS_MVPL_HSCALER5_CONTROL_scale_mode_MASK (0x10U)
#define IRIS_MVPL_HSCALER5_CONTROL_scale_mode_SHIFT (4U)
#define IRIS_MVPL_HSCALER5_CONTROL_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_CONTROL_scale_mode_SHIFT)) & IRIS_MVPL_HSCALER5_CONTROL_scale_mode_MASK)
#define IRIS_MVPL_HSCALER5_CONTROL_filter_mode_MASK (0x100U)
#define IRIS_MVPL_HSCALER5_CONTROL_filter_mode_SHIFT (8U)
#define IRIS_MVPL_HSCALER5_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_HSCALER5_CONTROL_filter_mode_MASK)
#define IRIS_MVPL_HSCALER5_CONTROL_output_size_MASK (0x3FFF0000U)
#define IRIS_MVPL_HSCALER5_CONTROL_output_size_SHIFT (16U)
#define IRIS_MVPL_HSCALER5_CONTROL_output_size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_CONTROL_output_size_SHIFT)) & IRIS_MVPL_HSCALER5_CONTROL_output_size_MASK)

/*! @name VSCALER5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_VSCALER5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_VSCALER5_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_VSCALER5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_VSCALER5_LOCKUNLOCK_LockUnlock_MASK)

/*! @name VSCALER5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_VSCALER5_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_VSCALER5_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_VSCALER5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_VSCALER5_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_VSCALER5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_VSCALER5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_VSCALER5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_VSCALER5_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_VSCALER5_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_VSCALER5_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_VSCALER5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_VSCALER5_LOCKSTATUS_FreezeStatus_MASK)

/*! @name VSCALER5_STATICCONTROL - Static control settings that must typically be setup once only. */
#define IRIS_MVPL_VSCALER5_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_VSCALER5_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_VSCALER5_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_VSCALER5_STATICCONTROL_ShdEn_MASK)

/*! @name VSCALER5_SETUP1 - Phase interpolator setup. */
#define IRIS_MVPL_VSCALER5_SETUP1_scale_factor_MASK (0xFFFFFU)
#define IRIS_MVPL_VSCALER5_SETUP1_scale_factor_SHIFT (0U)
#define IRIS_MVPL_VSCALER5_SETUP1_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_SETUP1_scale_factor_SHIFT)) & IRIS_MVPL_VSCALER5_SETUP1_scale_factor_MASK)

/*! @name VSCALER5_SETUP2 - Phase interpolator setup, selected if input and output field polarity is 0. */
#define IRIS_MVPL_VSCALER5_SETUP2_phase_offset_MASK (0x1FFFFFU)
#define IRIS_MVPL_VSCALER5_SETUP2_phase_offset_SHIFT (0U)
#define IRIS_MVPL_VSCALER5_SETUP2_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_SETUP2_phase_offset_SHIFT)) & IRIS_MVPL_VSCALER5_SETUP2_phase_offset_MASK)

/*! @name VSCALER5_SETUP3 - Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0. */
#define IRIS_MVPL_VSCALER5_SETUP3_phase_offset1_MASK (0x1FFFFFU)
#define IRIS_MVPL_VSCALER5_SETUP3_phase_offset1_SHIFT (0U)
#define IRIS_MVPL_VSCALER5_SETUP3_phase_offset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_SETUP3_phase_offset1_SHIFT)) & IRIS_MVPL_VSCALER5_SETUP3_phase_offset1_MASK)

/*! @name VSCALER5_SETUP4 - Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1. */
#define IRIS_MVPL_VSCALER5_SETUP4_phase_offset2_MASK (0x1FFFFFU)
#define IRIS_MVPL_VSCALER5_SETUP4_phase_offset2_SHIFT (0U)
#define IRIS_MVPL_VSCALER5_SETUP4_phase_offset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_SETUP4_phase_offset2_SHIFT)) & IRIS_MVPL_VSCALER5_SETUP4_phase_offset2_MASK)

/*! @name VSCALER5_SETUP5 - Phase interpolator setup, selected if input and output field polarity is 1. */
#define IRIS_MVPL_VSCALER5_SETUP5_phase_offset3_MASK (0x1FFFFFU)
#define IRIS_MVPL_VSCALER5_SETUP5_phase_offset3_SHIFT (0U)
#define IRIS_MVPL_VSCALER5_SETUP5_phase_offset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_SETUP5_phase_offset3_SHIFT)) & IRIS_MVPL_VSCALER5_SETUP5_phase_offset3_MASK)

/*! @name VSCALER5_CONTROL - Scaler operation control. */
#define IRIS_MVPL_VSCALER5_CONTROL_mode_MASK     (0x1U)
#define IRIS_MVPL_VSCALER5_CONTROL_mode_SHIFT    (0U)
#define IRIS_MVPL_VSCALER5_CONTROL_mode(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_CONTROL_mode_SHIFT)) & IRIS_MVPL_VSCALER5_CONTROL_mode_MASK)
#define IRIS_MVPL_VSCALER5_CONTROL_scale_mode_MASK (0x10U)
#define IRIS_MVPL_VSCALER5_CONTROL_scale_mode_SHIFT (4U)
#define IRIS_MVPL_VSCALER5_CONTROL_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_CONTROL_scale_mode_SHIFT)) & IRIS_MVPL_VSCALER5_CONTROL_scale_mode_MASK)
#define IRIS_MVPL_VSCALER5_CONTROL_filter_mode_MASK (0x100U)
#define IRIS_MVPL_VSCALER5_CONTROL_filter_mode_SHIFT (8U)
#define IRIS_MVPL_VSCALER5_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_VSCALER5_CONTROL_filter_mode_MASK)
#define IRIS_MVPL_VSCALER5_CONTROL_field_mode_MASK (0x3000U)
#define IRIS_MVPL_VSCALER5_CONTROL_field_mode_SHIFT (12U)
#define IRIS_MVPL_VSCALER5_CONTROL_field_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_CONTROL_field_mode_SHIFT)) & IRIS_MVPL_VSCALER5_CONTROL_field_mode_MASK)
#define IRIS_MVPL_VSCALER5_CONTROL_output_size_MASK (0x3FFF0000U)
#define IRIS_MVPL_VSCALER5_CONTROL_output_size_SHIFT (16U)
#define IRIS_MVPL_VSCALER5_CONTROL_output_size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_CONTROL_output_size_SHIFT)) & IRIS_MVPL_VSCALER5_CONTROL_output_size_MASK)

/*! @name HISTOGRAM5_CONTROL - Controls some settings concerning input components and alpha mask. */
#define IRIS_MVPL_HISTOGRAM5_CONTROL_clip_en_MASK (0x1U)
#define IRIS_MVPL_HISTOGRAM5_CONTROL_clip_en_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_CONTROL_clip_en(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_CONTROL_clip_en_SHIFT)) & IRIS_MVPL_HISTOGRAM5_CONTROL_clip_en_MASK)
#define IRIS_MVPL_HISTOGRAM5_CONTROL_color_space_mode_MASK (0x30U)
#define IRIS_MVPL_HISTOGRAM5_CONTROL_color_space_mode_SHIFT (4U)
#define IRIS_MVPL_HISTOGRAM5_CONTROL_color_space_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_CONTROL_color_space_mode_SHIFT)) & IRIS_MVPL_HISTOGRAM5_CONTROL_color_space_mode_MASK)
#define IRIS_MVPL_HISTOGRAM5_CONTROL_lum_mode_MASK (0x300U)
#define IRIS_MVPL_HISTOGRAM5_CONTROL_lum_mode_SHIFT (8U)
#define IRIS_MVPL_HISTOGRAM5_CONTROL_lum_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_CONTROL_lum_mode_SHIFT)) & IRIS_MVPL_HISTOGRAM5_CONTROL_lum_mode_MASK)
#define IRIS_MVPL_HISTOGRAM5_CONTROL_AlphaMask_MASK (0x1000U)
#define IRIS_MVPL_HISTOGRAM5_CONTROL_AlphaMask_SHIFT (12U)
#define IRIS_MVPL_HISTOGRAM5_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_HISTOGRAM5_CONTROL_AlphaMask_MASK)
#define IRIS_MVPL_HISTOGRAM5_CONTROL_AlphaInvert_MASK (0x2000U)
#define IRIS_MVPL_HISTOGRAM5_CONTROL_AlphaInvert_SHIFT (13U)
#define IRIS_MVPL_HISTOGRAM5_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_HISTOGRAM5_CONTROL_AlphaInvert_MASK)

/*! @name HISTOGRAM5_BINPROPERTIES - Configures the histogram bins. */
#define IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_binnum_width_MASK (0x7U)
#define IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_binnum_width_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_binnum_width(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_binnum_width_SHIFT)) & IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_binnum_width_MASK)
#define IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_cnt_mode_MASK (0x10U)
#define IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_cnt_mode_SHIFT (4U)
#define IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_cnt_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_cnt_mode_SHIFT)) & IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_cnt_mode_MASK)
#define IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_bincnt_rd_mode_MASK (0x100U)
#define IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_bincnt_rd_mode_SHIFT (8U)
#define IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_bincnt_rd_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_bincnt_rd_mode_SHIFT)) & IRIS_MVPL_HISTOGRAM5_BINPROPERTIES_bincnt_rd_mode_MASK)

/*! @name HISTOGRAM5_BINCNTTHRESH - Bin counter threshold value. */
#define IRIS_MVPL_HISTOGRAM5_BINCNTTHRESH_bincnt_thresh_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_HISTOGRAM5_BINCNTTHRESH_bincnt_thresh_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_BINCNTTHRESH_bincnt_thresh(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_BINCNTTHRESH_bincnt_thresh_SHIFT)) & IRIS_MVPL_HISTOGRAM5_BINCNTTHRESH_bincnt_thresh_MASK)

/*! @name HISTOGRAM5_CLIPWINUPPERLEFT - Coordinates of upper left corner of clip window. */
#define IRIS_MVPL_HISTOGRAM5_CLIPWINUPPERLEFT_clip_x_MASK (0x3FFFU)
#define IRIS_MVPL_HISTOGRAM5_CLIPWINUPPERLEFT_clip_x_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_CLIPWINUPPERLEFT_clip_x(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_CLIPWINUPPERLEFT_clip_x_SHIFT)) & IRIS_MVPL_HISTOGRAM5_CLIPWINUPPERLEFT_clip_x_MASK)
#define IRIS_MVPL_HISTOGRAM5_CLIPWINUPPERLEFT_clip_y_MASK (0x3FFF0000U)
#define IRIS_MVPL_HISTOGRAM5_CLIPWINUPPERLEFT_clip_y_SHIFT (16U)
#define IRIS_MVPL_HISTOGRAM5_CLIPWINUPPERLEFT_clip_y(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_CLIPWINUPPERLEFT_clip_y_SHIFT)) & IRIS_MVPL_HISTOGRAM5_CLIPWINUPPERLEFT_clip_y_MASK)

/*! @name HISTOGRAM5_CLIPWINSIZE - Dimensions of clip window. */
#define IRIS_MVPL_HISTOGRAM5_CLIPWINSIZE_clip_width_MASK (0x3FFFU)
#define IRIS_MVPL_HISTOGRAM5_CLIPWINSIZE_clip_width_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_CLIPWINSIZE_clip_width(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_CLIPWINSIZE_clip_width_SHIFT)) & IRIS_MVPL_HISTOGRAM5_CLIPWINSIZE_clip_width_MASK)
#define IRIS_MVPL_HISTOGRAM5_CLIPWINSIZE_clip_height_MASK (0x3FFF0000U)
#define IRIS_MVPL_HISTOGRAM5_CLIPWINSIZE_clip_height_SHIFT (16U)
#define IRIS_MVPL_HISTOGRAM5_CLIPWINSIZE_clip_height(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_CLIPWINSIZE_clip_height_SHIFT)) & IRIS_MVPL_HISTOGRAM5_CLIPWINSIZE_clip_height_MASK)

/*! @name HISTOGRAM5_RSLTRDY - Measurement result status. */
#define IRIS_MVPL_HISTOGRAM5_RSLTRDY_rslt_rdy_MASK (0x1U)
#define IRIS_MVPL_HISTOGRAM5_RSLTRDY_rslt_rdy_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_RSLTRDY_rslt_rdy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTRDY_rslt_rdy_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTRDY_rslt_rdy_MASK)

/*! @name HISTOGRAM5_RSLTFRMINF - Additional information on the measurement results. */
#define IRIS_MVPL_HISTOGRAM5_RSLTFRMINF_frm_idx_MASK (0xFFU)
#define IRIS_MVPL_HISTOGRAM5_RSLTFRMINF_frm_idx_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_RSLTFRMINF_frm_idx(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTFRMINF_frm_idx_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTFRMINF_frm_idx_MASK)
#define IRIS_MVPL_HISTOGRAM5_RSLTFRMINF_fld_polarity_MASK (0x10000U)
#define IRIS_MVPL_HISTOGRAM5_RSLTFRMINF_fld_polarity_SHIFT (16U)
#define IRIS_MVPL_HISTOGRAM5_RSLTFRMINF_fld_polarity(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTFRMINF_fld_polarity_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTFRMINF_fld_polarity_MASK)

/*! @name HISTOGRAM5_RSLTCOMP0BINIDX - Results of frame measurement for component 0. */
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINIDX_comp0_binidx_maxcnt_MASK (0x3FU)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINIDX_comp0_binidx_maxcnt_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINIDX_comp0_binidx_maxcnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINIDX_comp0_binidx_maxcnt_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINIDX_comp0_binidx_maxcnt_MASK)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINIDX_comp0_binidx_nxt_MASK (0x3F0000U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINIDX_comp0_binidx_nxt_SHIFT (16U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINIDX_comp0_binidx_nxt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINIDX_comp0_binidx_nxt_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINIDX_comp0_binidx_nxt_MASK)

/*! @name HISTOGRAM5_RSLTCOMP1BINIDX - Results of frame measurement for component 1. */
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINIDX_comp1_binidx_maxcnt_MASK (0x3FU)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINIDX_comp1_binidx_maxcnt_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINIDX_comp1_binidx_maxcnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINIDX_comp1_binidx_maxcnt_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINIDX_comp1_binidx_maxcnt_MASK)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINIDX_comp1_binidx_nxt_MASK (0x3F0000U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINIDX_comp1_binidx_nxt_SHIFT (16U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINIDX_comp1_binidx_nxt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINIDX_comp1_binidx_nxt_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINIDX_comp1_binidx_nxt_MASK)

/*! @name HISTOGRAM5_RSLTCOMP2BINIDX - Results of frame measurement for component 2. */
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINIDX_comp2_binidx_maxcnt_MASK (0x3FU)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINIDX_comp2_binidx_maxcnt_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINIDX_comp2_binidx_maxcnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINIDX_comp2_binidx_maxcnt_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINIDX_comp2_binidx_maxcnt_MASK)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINIDX_comp2_binidx_nxt_MASK (0x3F0000U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINIDX_comp2_binidx_nxt_SHIFT (16U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINIDX_comp2_binidx_nxt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINIDX_comp2_binidx_nxt_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINIDX_comp2_binidx_nxt_MASK)

/*! @name HISTOGRAM5_RSLTCOMP0SUM - Sum of all component 0 values. */
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP0SUM_comp0_sum_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP0SUM_comp0_sum_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP0SUM_comp0_sum(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTCOMP0SUM_comp0_sum_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTCOMP0SUM_comp0_sum_MASK)

/*! @name HISTOGRAM5_RSLTCOMP1SUM - Sum of all component 1 values. */
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP1SUM_comp1_sum_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP1SUM_comp1_sum_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP1SUM_comp1_sum(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTCOMP1SUM_comp1_sum_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTCOMP1SUM_comp1_sum_MASK)

/*! @name HISTOGRAM5_RSLTCOMP2SUM - Sum of all component 2 values. */
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP2SUM_comp2_sum_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP2SUM_comp2_sum_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP2SUM_comp2_sum(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTCOMP2SUM_comp2_sum_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTCOMP2SUM_comp2_sum_MASK)

/*! @name HISTOGRAM5_RSLTCOMP0BINCNT - Bin counters of component 0 histogram. */
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINCNT_comp0_bincnt_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINCNT_comp0_bincnt_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINCNT_comp0_bincnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINCNT_comp0_bincnt_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTCOMP0BINCNT_comp0_bincnt_MASK)

/*! @name HISTOGRAM5_RSLTCOMP1BINCNT - Bin counters of component 1 histogram. */
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINCNT_comp1_bincnt_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINCNT_comp1_bincnt_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINCNT_comp1_bincnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINCNT_comp1_bincnt_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTCOMP1BINCNT_comp1_bincnt_MASK)

/*! @name HISTOGRAM5_RSLTCOMP2BINCNT - Bin counters of component 2 histogram. */
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINCNT_comp2_bincnt_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINCNT_comp2_bincnt_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINCNT_comp2_bincnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINCNT_comp2_bincnt_SHIFT)) & IRIS_MVPL_HISTOGRAM5_RSLTCOMP2BINCNT_comp2_bincnt_MASK)

/*! @name HISTOGRAM5_FRMSTRTTRIG - Triggers for loading shadow registers and starting measurement with next input frame. */
#define IRIS_MVPL_HISTOGRAM5_FRMSTRTTRIG_msrmnt_strt_trig_MASK (0x1U)
#define IRIS_MVPL_HISTOGRAM5_FRMSTRTTRIG_msrmnt_strt_trig_SHIFT (0U)
#define IRIS_MVPL_HISTOGRAM5_FRMSTRTTRIG_msrmnt_strt_trig(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HISTOGRAM5_FRMSTRTTRIG_msrmnt_strt_trig_SHIFT)) & IRIS_MVPL_HISTOGRAM5_FRMSTRTTRIG_msrmnt_strt_trig_MASK)

/*! @name LAYERBLEND0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_LAYERBLEND0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND0_LOCKUNLOCK_LockUnlock_MASK)

/*! @name LAYERBLEND0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND0_LOCKSTATUS_FreezeStatus_MASK)

/*! @name LAYERBLEND0_STATICCONTROL - Static control settings. */
#define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdLdSel_MASK (0x6U)
#define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdLdSel_SHIFT (1U)
#define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdLdSel_MASK)
#define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdTokSel_MASK (0x18U)
#define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdTokSel_SHIFT (3U)
#define IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdTokSel_SHIFT)) & IRIS_MVPL_LAYERBLEND0_STATICCONTROL_ShdTokSel_MASK)

/*! @name LAYERBLEND0_CONTROL - Common control settings. */
#define IRIS_MVPL_LAYERBLEND0_CONTROL_MODE_MASK  (0x1U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_MODE_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_MODE(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_MODE_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_MODE_MASK)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskEnable_MASK (0x4U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskEnable_SHIFT (2U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskEnable_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskEnable_MASK)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskMode_MASK (0x70U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskMode_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskMode_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_AlphaMaskMode_MASK)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecLowPassEn_MASK (0x100U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecLowPassEn_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_SecLowPassEn_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_SecLowPassEn_MASK)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecReplicateEn_MASK (0x200U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecReplicateEn_SHIFT (9U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_SecReplicateEn_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_SecReplicateEn_MASK)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowEvenColDis_MASK (0x3C00U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowEvenColDis_SHIFT (10U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowEvenColDis_MASK)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowOddColDis_MASK (0x3C000U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowOddColDis_SHIFT (14U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_SecEvenRowOddColDis_MASK)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowEvenColDis_MASK (0x3C0000U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowEvenColDis_SHIFT (18U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowEvenColDis_MASK)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowOddColDis_MASK (0x3C00000U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowOddColDis_SHIFT (22U)
#define IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND0_CONTROL_SecOddRowOddColDis_MASK)

/*! @name LAYERBLEND0_BLENDCONTROL - Options for blend operations */
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK (0x7U)
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_MASK (0x70U)
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK (0x700U)
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_MASK (0x7000U)
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT (12U)
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_BlendAlpha_MASK (0xFF0000U)
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_BlendAlpha_SHIFT (16U)
#define IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_BlendAlpha_SHIFT)) & IRIS_MVPL_LAYERBLEND0_BLENDCONTROL_BlendAlpha_MASK)

/*! @name LAYERBLEND0_POSITION - Position of secondary (overlay) input frame */
#define IRIS_MVPL_LAYERBLEND0_POSITION_XPOS_MASK (0xFFFFU)
#define IRIS_MVPL_LAYERBLEND0_POSITION_XPOS_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND0_POSITION_XPOS(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_POSITION_XPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND0_POSITION_XPOS_MASK)
#define IRIS_MVPL_LAYERBLEND0_POSITION_YPOS_MASK (0xFFFF0000U)
#define IRIS_MVPL_LAYERBLEND0_POSITION_YPOS_SHIFT (16U)
#define IRIS_MVPL_LAYERBLEND0_POSITION_YPOS(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_POSITION_YPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND0_POSITION_YPOS_MASK)

/*! @name LAYERBLEND0_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */
#define IRIS_MVPL_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND0_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_MASK)

/*! @name LAYERBLEND0_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */
#define IRIS_MVPL_LAYERBLEND0_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND0_SECCONTROLWORD_S_VAL_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND0_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND0_SECCONTROLWORD_S_VAL_MASK)

/*! @name LAYERBLEND1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_LAYERBLEND1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND1_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND1_LOCKUNLOCK_LockUnlock_MASK)

/*! @name LAYERBLEND1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND1_LOCKSTATUS_FreezeStatus_MASK)

/*! @name LAYERBLEND1_STATICCONTROL - Static control settings. */
#define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdLdSel_MASK (0x6U)
#define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdLdSel_SHIFT (1U)
#define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdLdSel_MASK)
#define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdTokSel_MASK (0x18U)
#define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdTokSel_SHIFT (3U)
#define IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdTokSel_SHIFT)) & IRIS_MVPL_LAYERBLEND1_STATICCONTROL_ShdTokSel_MASK)

/*! @name LAYERBLEND1_CONTROL - Common control settings. */
#define IRIS_MVPL_LAYERBLEND1_CONTROL_MODE_MASK  (0x1U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_MODE_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_MODE(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_MODE_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_MODE_MASK)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskEnable_MASK (0x4U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskEnable_SHIFT (2U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskEnable_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskEnable_MASK)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskMode_MASK (0x70U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskMode_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskMode_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_AlphaMaskMode_MASK)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecLowPassEn_MASK (0x100U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecLowPassEn_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_SecLowPassEn_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_SecLowPassEn_MASK)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecReplicateEn_MASK (0x200U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecReplicateEn_SHIFT (9U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_SecReplicateEn_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_SecReplicateEn_MASK)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowEvenColDis_MASK (0x3C00U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowEvenColDis_SHIFT (10U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowEvenColDis_MASK)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowOddColDis_MASK (0x3C000U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowOddColDis_SHIFT (14U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_SecEvenRowOddColDis_MASK)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowEvenColDis_MASK (0x3C0000U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowEvenColDis_SHIFT (18U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowEvenColDis_MASK)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowOddColDis_MASK (0x3C00000U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowOddColDis_SHIFT (22U)
#define IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND1_CONTROL_SecOddRowOddColDis_MASK)

/*! @name LAYERBLEND1_BLENDCONTROL - Options for blend operations */
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK (0x7U)
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_MASK (0x70U)
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK (0x700U)
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_MASK (0x7000U)
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT (12U)
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_BlendAlpha_MASK (0xFF0000U)
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_BlendAlpha_SHIFT (16U)
#define IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_BlendAlpha_SHIFT)) & IRIS_MVPL_LAYERBLEND1_BLENDCONTROL_BlendAlpha_MASK)

/*! @name LAYERBLEND1_POSITION - Position of secondary (overlay) input frame */
#define IRIS_MVPL_LAYERBLEND1_POSITION_XPOS_MASK (0xFFFFU)
#define IRIS_MVPL_LAYERBLEND1_POSITION_XPOS_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND1_POSITION_XPOS(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_POSITION_XPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND1_POSITION_XPOS_MASK)
#define IRIS_MVPL_LAYERBLEND1_POSITION_YPOS_MASK (0xFFFF0000U)
#define IRIS_MVPL_LAYERBLEND1_POSITION_YPOS_SHIFT (16U)
#define IRIS_MVPL_LAYERBLEND1_POSITION_YPOS(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_POSITION_YPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND1_POSITION_YPOS_MASK)

/*! @name LAYERBLEND1_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */
#define IRIS_MVPL_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND1_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_MASK)

/*! @name LAYERBLEND1_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */
#define IRIS_MVPL_LAYERBLEND1_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND1_SECCONTROLWORD_S_VAL_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND1_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND1_SECCONTROLWORD_S_VAL_MASK)

/*! @name LAYERBLEND2_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_LAYERBLEND2_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND2_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND2_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND2_LOCKUNLOCK_LockUnlock_MASK)

/*! @name LAYERBLEND2_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND2_LOCKSTATUS_FreezeStatus_MASK)

/*! @name LAYERBLEND2_STATICCONTROL - Static control settings. */
#define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdLdSel_MASK (0x6U)
#define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdLdSel_SHIFT (1U)
#define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdLdSel_MASK)
#define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdTokSel_MASK (0x18U)
#define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdTokSel_SHIFT (3U)
#define IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdTokSel_SHIFT)) & IRIS_MVPL_LAYERBLEND2_STATICCONTROL_ShdTokSel_MASK)

/*! @name LAYERBLEND2_CONTROL - Common control settings. */
#define IRIS_MVPL_LAYERBLEND2_CONTROL_MODE_MASK  (0x1U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_MODE_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_MODE(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_MODE_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_MODE_MASK)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskEnable_MASK (0x4U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskEnable_SHIFT (2U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskEnable_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskEnable_MASK)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskMode_MASK (0x70U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskMode_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskMode_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_AlphaMaskMode_MASK)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecLowPassEn_MASK (0x100U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecLowPassEn_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_SecLowPassEn_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_SecLowPassEn_MASK)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecReplicateEn_MASK (0x200U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecReplicateEn_SHIFT (9U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_SecReplicateEn_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_SecReplicateEn_MASK)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowEvenColDis_MASK (0x3C00U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowEvenColDis_SHIFT (10U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowEvenColDis_MASK)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowOddColDis_MASK (0x3C000U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowOddColDis_SHIFT (14U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_SecEvenRowOddColDis_MASK)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowEvenColDis_MASK (0x3C0000U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowEvenColDis_SHIFT (18U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowEvenColDis_MASK)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowOddColDis_MASK (0x3C00000U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowOddColDis_SHIFT (22U)
#define IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND2_CONTROL_SecOddRowOddColDis_MASK)

/*! @name LAYERBLEND2_BLENDCONTROL - Options for blend operations */
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK (0x7U)
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_MASK (0x70U)
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK (0x700U)
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_MASK (0x7000U)
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT (12U)
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_BlendAlpha_MASK (0xFF0000U)
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_BlendAlpha_SHIFT (16U)
#define IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_BlendAlpha_SHIFT)) & IRIS_MVPL_LAYERBLEND2_BLENDCONTROL_BlendAlpha_MASK)

/*! @name LAYERBLEND2_POSITION - Position of secondary (overlay) input frame */
#define IRIS_MVPL_LAYERBLEND2_POSITION_XPOS_MASK (0xFFFFU)
#define IRIS_MVPL_LAYERBLEND2_POSITION_XPOS_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND2_POSITION_XPOS(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_POSITION_XPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND2_POSITION_XPOS_MASK)
#define IRIS_MVPL_LAYERBLEND2_POSITION_YPOS_MASK (0xFFFF0000U)
#define IRIS_MVPL_LAYERBLEND2_POSITION_YPOS_SHIFT (16U)
#define IRIS_MVPL_LAYERBLEND2_POSITION_YPOS(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_POSITION_YPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND2_POSITION_YPOS_MASK)

/*! @name LAYERBLEND2_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */
#define IRIS_MVPL_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND2_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_MASK)

/*! @name LAYERBLEND2_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */
#define IRIS_MVPL_LAYERBLEND2_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND2_SECCONTROLWORD_S_VAL_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND2_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND2_SECCONTROLWORD_S_VAL_MASK)

/*! @name LAYERBLEND3_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_LAYERBLEND3_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND3_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND3_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND3_LOCKUNLOCK_LockUnlock_MASK)

/*! @name LAYERBLEND3_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND3_LOCKSTATUS_FreezeStatus_MASK)

/*! @name LAYERBLEND3_STATICCONTROL - Static control settings. */
#define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdLdSel_MASK (0x6U)
#define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdLdSel_SHIFT (1U)
#define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdLdSel_MASK)
#define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdTokSel_MASK (0x18U)
#define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdTokSel_SHIFT (3U)
#define IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdTokSel_SHIFT)) & IRIS_MVPL_LAYERBLEND3_STATICCONTROL_ShdTokSel_MASK)

/*! @name LAYERBLEND3_CONTROL - Common control settings. */
#define IRIS_MVPL_LAYERBLEND3_CONTROL_MODE_MASK  (0x1U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_MODE_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_MODE(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_MODE_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_MODE_MASK)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskEnable_MASK (0x4U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskEnable_SHIFT (2U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskEnable_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskEnable_MASK)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskMode_MASK (0x70U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskMode_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskMode_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_AlphaMaskMode_MASK)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecLowPassEn_MASK (0x100U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecLowPassEn_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_SecLowPassEn_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_SecLowPassEn_MASK)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecReplicateEn_MASK (0x200U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecReplicateEn_SHIFT (9U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_SecReplicateEn_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_SecReplicateEn_MASK)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowEvenColDis_MASK (0x3C00U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowEvenColDis_SHIFT (10U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowEvenColDis_MASK)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowOddColDis_MASK (0x3C000U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowOddColDis_SHIFT (14U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_SecEvenRowOddColDis_MASK)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowEvenColDis_MASK (0x3C0000U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowEvenColDis_SHIFT (18U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowEvenColDis_MASK)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowOddColDis_MASK (0x3C00000U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowOddColDis_SHIFT (22U)
#define IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND3_CONTROL_SecOddRowOddColDis_MASK)

/*! @name LAYERBLEND3_BLENDCONTROL - Options for blend operations */
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK (0x7U)
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_MASK (0x70U)
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK (0x700U)
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_MASK (0x7000U)
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT (12U)
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_BlendAlpha_MASK (0xFF0000U)
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_BlendAlpha_SHIFT (16U)
#define IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_BlendAlpha_SHIFT)) & IRIS_MVPL_LAYERBLEND3_BLENDCONTROL_BlendAlpha_MASK)

/*! @name LAYERBLEND3_POSITION - Position of secondary (overlay) input frame */
#define IRIS_MVPL_LAYERBLEND3_POSITION_XPOS_MASK (0xFFFFU)
#define IRIS_MVPL_LAYERBLEND3_POSITION_XPOS_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND3_POSITION_XPOS(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_POSITION_XPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND3_POSITION_XPOS_MASK)
#define IRIS_MVPL_LAYERBLEND3_POSITION_YPOS_MASK (0xFFFF0000U)
#define IRIS_MVPL_LAYERBLEND3_POSITION_YPOS_SHIFT (16U)
#define IRIS_MVPL_LAYERBLEND3_POSITION_YPOS(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_POSITION_YPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND3_POSITION_YPOS_MASK)

/*! @name LAYERBLEND3_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */
#define IRIS_MVPL_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND3_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_MASK)

/*! @name LAYERBLEND3_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */
#define IRIS_MVPL_LAYERBLEND3_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND3_SECCONTROLWORD_S_VAL_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND3_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND3_SECCONTROLWORD_S_VAL_MASK)

/*! @name LAYERBLEND4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_LAYERBLEND4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND4_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND4_LOCKUNLOCK_LockUnlock_MASK)

/*! @name LAYERBLEND4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND4_LOCKSTATUS_FreezeStatus_MASK)

/*! @name LAYERBLEND4_STATICCONTROL - Static control settings. */
#define IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdLdSel_MASK (0x6U)
#define IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdLdSel_SHIFT (1U)
#define IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdLdSel_MASK)
#define IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdTokSel_MASK (0x18U)
#define IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdTokSel_SHIFT (3U)
#define IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdTokSel_SHIFT)) & IRIS_MVPL_LAYERBLEND4_STATICCONTROL_ShdTokSel_MASK)

/*! @name LAYERBLEND4_CONTROL - Common control settings. */
#define IRIS_MVPL_LAYERBLEND4_CONTROL_MODE_MASK  (0x1U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_MODE_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_MODE(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_CONTROL_MODE_SHIFT)) & IRIS_MVPL_LAYERBLEND4_CONTROL_MODE_MASK)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_AlphaMaskEnable_MASK (0x4U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_AlphaMaskEnable_SHIFT (2U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_CONTROL_AlphaMaskEnable_SHIFT)) & IRIS_MVPL_LAYERBLEND4_CONTROL_AlphaMaskEnable_MASK)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_AlphaMaskMode_MASK (0x70U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_AlphaMaskMode_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_CONTROL_AlphaMaskMode_SHIFT)) & IRIS_MVPL_LAYERBLEND4_CONTROL_AlphaMaskMode_MASK)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecLowPassEn_MASK (0x100U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecLowPassEn_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_CONTROL_SecLowPassEn_SHIFT)) & IRIS_MVPL_LAYERBLEND4_CONTROL_SecLowPassEn_MASK)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecReplicateEn_MASK (0x200U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecReplicateEn_SHIFT (9U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_CONTROL_SecReplicateEn_SHIFT)) & IRIS_MVPL_LAYERBLEND4_CONTROL_SecReplicateEn_MASK)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecEvenRowEvenColDis_MASK (0x3C00U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecEvenRowEvenColDis_SHIFT (10U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_CONTROL_SecEvenRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND4_CONTROL_SecEvenRowEvenColDis_MASK)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecEvenRowOddColDis_MASK (0x3C000U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecEvenRowOddColDis_SHIFT (14U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_CONTROL_SecEvenRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND4_CONTROL_SecEvenRowOddColDis_MASK)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecOddRowEvenColDis_MASK (0x3C0000U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecOddRowEvenColDis_SHIFT (18U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_CONTROL_SecOddRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND4_CONTROL_SecOddRowEvenColDis_MASK)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecOddRowOddColDis_MASK (0x3C00000U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecOddRowOddColDis_SHIFT (22U)
#define IRIS_MVPL_LAYERBLEND4_CONTROL_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_CONTROL_SecOddRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND4_CONTROL_SecOddRowOddColDis_MASK)

/*! @name LAYERBLEND4_BLENDCONTROL - Options for blend operations */
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK (0x7U)
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_SEC_C_BLD_FUNC_MASK (0x70U)
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_SEC_C_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK (0x700U)
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_SEC_A_BLD_FUNC_MASK (0x7000U)
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT (12U)
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_SEC_A_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_BlendAlpha_MASK (0xFF0000U)
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_BlendAlpha_SHIFT (16U)
#define IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_BlendAlpha_SHIFT)) & IRIS_MVPL_LAYERBLEND4_BLENDCONTROL_BlendAlpha_MASK)

/*! @name LAYERBLEND4_POSITION - Position of secondary (overlay) input frame */
#define IRIS_MVPL_LAYERBLEND4_POSITION_XPOS_MASK (0xFFFFU)
#define IRIS_MVPL_LAYERBLEND4_POSITION_XPOS_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND4_POSITION_XPOS(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_POSITION_XPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND4_POSITION_XPOS_MASK)
#define IRIS_MVPL_LAYERBLEND4_POSITION_YPOS_MASK (0xFFFF0000U)
#define IRIS_MVPL_LAYERBLEND4_POSITION_YPOS_SHIFT (16U)
#define IRIS_MVPL_LAYERBLEND4_POSITION_YPOS(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_POSITION_YPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND4_POSITION_YPOS_MASK)

/*! @name LAYERBLEND4_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */
#define IRIS_MVPL_LAYERBLEND4_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND4_PRIMCONTROLWORD_P_VAL_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND4_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND4_PRIMCONTROLWORD_P_VAL_MASK)

/*! @name LAYERBLEND4_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */
#define IRIS_MVPL_LAYERBLEND4_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND4_SECCONTROLWORD_S_VAL_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND4_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND4_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND4_SECCONTROLWORD_S_VAL_MASK)

/*! @name LAYERBLEND5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_LAYERBLEND5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND5_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND5_LOCKUNLOCK_LockUnlock_MASK)

/*! @name LAYERBLEND5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND5_LOCKSTATUS_FreezeStatus_MASK)

/*! @name LAYERBLEND5_STATICCONTROL - Static control settings. */
#define IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdLdSel_MASK (0x6U)
#define IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdLdSel_SHIFT (1U)
#define IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdLdSel_MASK)
#define IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdTokSel_MASK (0x18U)
#define IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdTokSel_SHIFT (3U)
#define IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdTokSel_SHIFT)) & IRIS_MVPL_LAYERBLEND5_STATICCONTROL_ShdTokSel_MASK)

/*! @name LAYERBLEND5_CONTROL - Common control settings. */
#define IRIS_MVPL_LAYERBLEND5_CONTROL_MODE_MASK  (0x1U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_MODE_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_MODE(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_CONTROL_MODE_SHIFT)) & IRIS_MVPL_LAYERBLEND5_CONTROL_MODE_MASK)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_AlphaMaskEnable_MASK (0x4U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_AlphaMaskEnable_SHIFT (2U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_CONTROL_AlphaMaskEnable_SHIFT)) & IRIS_MVPL_LAYERBLEND5_CONTROL_AlphaMaskEnable_MASK)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_AlphaMaskMode_MASK (0x70U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_AlphaMaskMode_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_CONTROL_AlphaMaskMode_SHIFT)) & IRIS_MVPL_LAYERBLEND5_CONTROL_AlphaMaskMode_MASK)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecLowPassEn_MASK (0x100U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecLowPassEn_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_CONTROL_SecLowPassEn_SHIFT)) & IRIS_MVPL_LAYERBLEND5_CONTROL_SecLowPassEn_MASK)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecReplicateEn_MASK (0x200U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecReplicateEn_SHIFT (9U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_CONTROL_SecReplicateEn_SHIFT)) & IRIS_MVPL_LAYERBLEND5_CONTROL_SecReplicateEn_MASK)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecEvenRowEvenColDis_MASK (0x3C00U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecEvenRowEvenColDis_SHIFT (10U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_CONTROL_SecEvenRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND5_CONTROL_SecEvenRowEvenColDis_MASK)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecEvenRowOddColDis_MASK (0x3C000U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecEvenRowOddColDis_SHIFT (14U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_CONTROL_SecEvenRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND5_CONTROL_SecEvenRowOddColDis_MASK)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecOddRowEvenColDis_MASK (0x3C0000U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecOddRowEvenColDis_SHIFT (18U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_CONTROL_SecOddRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND5_CONTROL_SecOddRowEvenColDis_MASK)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecOddRowOddColDis_MASK (0x3C00000U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecOddRowOddColDis_SHIFT (22U)
#define IRIS_MVPL_LAYERBLEND5_CONTROL_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_CONTROL_SecOddRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND5_CONTROL_SecOddRowOddColDis_MASK)

/*! @name LAYERBLEND5_BLENDCONTROL - Options for blend operations */
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK (0x7U)
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_SEC_C_BLD_FUNC_MASK (0x70U)
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_SEC_C_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK (0x700U)
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_SEC_A_BLD_FUNC_MASK (0x7000U)
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT (12U)
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_SEC_A_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_BlendAlpha_MASK (0xFF0000U)
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_BlendAlpha_SHIFT (16U)
#define IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_BlendAlpha_SHIFT)) & IRIS_MVPL_LAYERBLEND5_BLENDCONTROL_BlendAlpha_MASK)

/*! @name LAYERBLEND5_POSITION - Position of secondary (overlay) input frame */
#define IRIS_MVPL_LAYERBLEND5_POSITION_XPOS_MASK (0xFFFFU)
#define IRIS_MVPL_LAYERBLEND5_POSITION_XPOS_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND5_POSITION_XPOS(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_POSITION_XPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND5_POSITION_XPOS_MASK)
#define IRIS_MVPL_LAYERBLEND5_POSITION_YPOS_MASK (0xFFFF0000U)
#define IRIS_MVPL_LAYERBLEND5_POSITION_YPOS_SHIFT (16U)
#define IRIS_MVPL_LAYERBLEND5_POSITION_YPOS(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_POSITION_YPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND5_POSITION_YPOS_MASK)

/*! @name LAYERBLEND5_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */
#define IRIS_MVPL_LAYERBLEND5_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND5_PRIMCONTROLWORD_P_VAL_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND5_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND5_PRIMCONTROLWORD_P_VAL_MASK)

/*! @name LAYERBLEND5_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */
#define IRIS_MVPL_LAYERBLEND5_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND5_SECCONTROLWORD_S_VAL_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND5_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND5_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND5_SECCONTROLWORD_S_VAL_MASK)

/*! @name LAYERBLEND6_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_LAYERBLEND6_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND6_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND6_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND6_LOCKUNLOCK_LockUnlock_MASK)

/*! @name LAYERBLEND6_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND6_LOCKSTATUS_FreezeStatus_MASK)

/*! @name LAYERBLEND6_STATICCONTROL - Static control settings. */
#define IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdLdSel_MASK (0x6U)
#define IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdLdSel_SHIFT (1U)
#define IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdLdSel_MASK)
#define IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdTokSel_MASK (0x18U)
#define IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdTokSel_SHIFT (3U)
#define IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdTokSel_SHIFT)) & IRIS_MVPL_LAYERBLEND6_STATICCONTROL_ShdTokSel_MASK)

/*! @name LAYERBLEND6_CONTROL - Common control settings. */
#define IRIS_MVPL_LAYERBLEND6_CONTROL_MODE_MASK  (0x1U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_MODE_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_MODE(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_CONTROL_MODE_SHIFT)) & IRIS_MVPL_LAYERBLEND6_CONTROL_MODE_MASK)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_AlphaMaskEnable_MASK (0x4U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_AlphaMaskEnable_SHIFT (2U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_CONTROL_AlphaMaskEnable_SHIFT)) & IRIS_MVPL_LAYERBLEND6_CONTROL_AlphaMaskEnable_MASK)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_AlphaMaskMode_MASK (0x70U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_AlphaMaskMode_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_CONTROL_AlphaMaskMode_SHIFT)) & IRIS_MVPL_LAYERBLEND6_CONTROL_AlphaMaskMode_MASK)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecLowPassEn_MASK (0x100U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecLowPassEn_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_CONTROL_SecLowPassEn_SHIFT)) & IRIS_MVPL_LAYERBLEND6_CONTROL_SecLowPassEn_MASK)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecReplicateEn_MASK (0x200U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecReplicateEn_SHIFT (9U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_CONTROL_SecReplicateEn_SHIFT)) & IRIS_MVPL_LAYERBLEND6_CONTROL_SecReplicateEn_MASK)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecEvenRowEvenColDis_MASK (0x3C00U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecEvenRowEvenColDis_SHIFT (10U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_CONTROL_SecEvenRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND6_CONTROL_SecEvenRowEvenColDis_MASK)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecEvenRowOddColDis_MASK (0x3C000U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecEvenRowOddColDis_SHIFT (14U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_CONTROL_SecEvenRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND6_CONTROL_SecEvenRowOddColDis_MASK)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecOddRowEvenColDis_MASK (0x3C0000U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecOddRowEvenColDis_SHIFT (18U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_CONTROL_SecOddRowEvenColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND6_CONTROL_SecOddRowEvenColDis_MASK)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecOddRowOddColDis_MASK (0x3C00000U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecOddRowOddColDis_SHIFT (22U)
#define IRIS_MVPL_LAYERBLEND6_CONTROL_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_CONTROL_SecOddRowOddColDis_SHIFT)) & IRIS_MVPL_LAYERBLEND6_CONTROL_SecOddRowOddColDis_MASK)

/*! @name LAYERBLEND6_BLENDCONTROL - Options for blend operations */
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK (0x7U)
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_SEC_C_BLD_FUNC_MASK (0x70U)
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT (4U)
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_SEC_C_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK (0x700U)
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT (8U)
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_SEC_A_BLD_FUNC_MASK (0x7000U)
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT (12U)
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT)) & IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_SEC_A_BLD_FUNC_MASK)
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_BlendAlpha_MASK (0xFF0000U)
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_BlendAlpha_SHIFT (16U)
#define IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_BlendAlpha_SHIFT)) & IRIS_MVPL_LAYERBLEND6_BLENDCONTROL_BlendAlpha_MASK)

/*! @name LAYERBLEND6_POSITION - Position of secondary (overlay) input frame */
#define IRIS_MVPL_LAYERBLEND6_POSITION_XPOS_MASK (0xFFFFU)
#define IRIS_MVPL_LAYERBLEND6_POSITION_XPOS_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND6_POSITION_XPOS(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_POSITION_XPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND6_POSITION_XPOS_MASK)
#define IRIS_MVPL_LAYERBLEND6_POSITION_YPOS_MASK (0xFFFF0000U)
#define IRIS_MVPL_LAYERBLEND6_POSITION_YPOS_SHIFT (16U)
#define IRIS_MVPL_LAYERBLEND6_POSITION_YPOS(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_POSITION_YPOS_SHIFT)) & IRIS_MVPL_LAYERBLEND6_POSITION_YPOS_MASK)

/*! @name LAYERBLEND6_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */
#define IRIS_MVPL_LAYERBLEND6_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND6_PRIMCONTROLWORD_P_VAL_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND6_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND6_PRIMCONTROLWORD_P_VAL_MASK)

/*! @name LAYERBLEND6_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */
#define IRIS_MVPL_LAYERBLEND6_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_LAYERBLEND6_SECCONTROLWORD_S_VAL_SHIFT (0U)
#define IRIS_MVPL_LAYERBLEND6_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND6_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_LAYERBLEND6_SECCONTROLWORD_S_VAL_MASK)

/*! @name EXTSRC0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_EXTSRC0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTSRC0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_EXTSRC0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_EXTSRC0_LOCKUNLOCK_LockUnlock_MASK)

/*! @name EXTSRC0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_EXTSRC0_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_EXTSRC0_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_EXTSRC0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_EXTSRC0_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_EXTSRC0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_EXTSRC0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_EXTSRC0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTSRC0_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_EXTSRC0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_EXTSRC0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_EXTSRC0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTSRC0_LOCKSTATUS_FreezeStatus_MASK)

/*! @name EXTSRC0_STATICCONTROL - ExtSrc static control register */
#define IRIS_MVPL_EXTSRC0_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_EXTSRC0_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_EXTSRC0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_EXTSRC0_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_EXTSRC0_STATICCONTROL_StartSel_MASK (0x100U)
#define IRIS_MVPL_EXTSRC0_STATICCONTROL_StartSel_SHIFT (8U)
#define IRIS_MVPL_EXTSRC0_STATICCONTROL_StartSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_STATICCONTROL_StartSel_SHIFT)) & IRIS_MVPL_EXTSRC0_STATICCONTROL_StartSel_MASK)

/*! @name EXTSRC0_CLIPWINDOWOFFSET - Clip window offset, to generate a clipping of the frame. It has to be within the input frame. */
#define IRIS_MVPL_EXTSRC0_CLIPWINDOWOFFSET_ClipWindowXOffset_MASK (0x3FFFU)
#define IRIS_MVPL_EXTSRC0_CLIPWINDOWOFFSET_ClipWindowXOffset_SHIFT (0U)
#define IRIS_MVPL_EXTSRC0_CLIPWINDOWOFFSET_ClipWindowXOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CLIPWINDOWOFFSET_ClipWindowXOffset_SHIFT)) & IRIS_MVPL_EXTSRC0_CLIPWINDOWOFFSET_ClipWindowXOffset_MASK)
#define IRIS_MVPL_EXTSRC0_CLIPWINDOWOFFSET_ClipWindowYOffset_MASK (0x3FFF0000U)
#define IRIS_MVPL_EXTSRC0_CLIPWINDOWOFFSET_ClipWindowYOffset_SHIFT (16U)
#define IRIS_MVPL_EXTSRC0_CLIPWINDOWOFFSET_ClipWindowYOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CLIPWINDOWOFFSET_ClipWindowYOffset_SHIFT)) & IRIS_MVPL_EXTSRC0_CLIPWINDOWOFFSET_ClipWindowYOffset_MASK)

/*! @name EXTSRC0_CLIPWINDOWDIMENSION - Define the clip window dimension. If the clip window feature is enabled this dimension is used for the new frame dimension. Note that the clip window has to be smaller or equal to the original frame dimensions. The new frame has to be within the active area of the original frame. */
#define IRIS_MVPL_EXTSRC0_CLIPWINDOWDIMENSION_ClipWindowWidth_MASK (0x3FFFU)
#define IRIS_MVPL_EXTSRC0_CLIPWINDOWDIMENSION_ClipWindowWidth_SHIFT (0U)
#define IRIS_MVPL_EXTSRC0_CLIPWINDOWDIMENSION_ClipWindowWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CLIPWINDOWDIMENSION_ClipWindowWidth_SHIFT)) & IRIS_MVPL_EXTSRC0_CLIPWINDOWDIMENSION_ClipWindowWidth_MASK)
#define IRIS_MVPL_EXTSRC0_CLIPWINDOWDIMENSION_ClipWindowHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_EXTSRC0_CLIPWINDOWDIMENSION_ClipWindowHeight_SHIFT (16U)
#define IRIS_MVPL_EXTSRC0_CLIPWINDOWDIMENSION_ClipWindowHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CLIPWINDOWDIMENSION_ClipWindowHeight_SHIFT)) & IRIS_MVPL_EXTSRC0_CLIPWINDOWDIMENSION_ClipWindowHeight_MASK)

/*! @name EXTSRC0_COLORCOMPONENTBITS - Color component size of raw input data. Please note that the width must be equal or lower than the output width. */
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK (0xFU)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT (0U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT)) & IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsBlue_MASK (0xF00U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT (8U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT)) & IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsBlue_MASK)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsGreen_MASK (0xF0000U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT (16U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT)) & IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsGreen_MASK)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsRed_MASK (0xF000000U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT (24U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT)) & IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ComponentBitsRed_MASK)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ITUFormat_MASK (0x80000000U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ITUFormat_SHIFT (31U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ITUFormat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ITUFormat_SHIFT)) & IRIS_MVPL_EXTSRC0_COLORCOMPONENTBITS_ITUFormat_MASK)

/*! @name EXTSRC0_COLORCOMPONENTSHIFT - Color component offset of raw input data. */
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK (0x3FU)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT (0U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT)) & IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK (0x3F00U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT (8U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT)) & IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK (0x3F0000U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT (16U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT)) & IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK (0x3F000000U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT (24U)
#define IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT)) & IRIS_MVPL_EXTSRC0_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK)

/*! @name EXTSRC0_CONSTANTCOLOR - Constant color register */
#define IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU)
#define IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U)
#define IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantAlpha_MASK)
#define IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U)
#define IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantBlue_SHIFT (8U)
#define IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantBlue_MASK)
#define IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U)
#define IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantGreen_SHIFT (16U)
#define IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantGreen_MASK)
#define IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U)
#define IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantRed_SHIFT (24U)
#define IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_EXTSRC0_CONSTANTCOLOR_ConstantRed_MASK)

/*! @name EXTSRC0_CONTROL - Common control settings. */
#define IRIS_MVPL_EXTSRC0_CONTROL_ClipWindowEnable_MASK (0x1U)
#define IRIS_MVPL_EXTSRC0_CONTROL_ClipWindowEnable_SHIFT (0U)
#define IRIS_MVPL_EXTSRC0_CONTROL_ClipWindowEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONTROL_ClipWindowEnable_SHIFT)) & IRIS_MVPL_EXTSRC0_CONTROL_ClipWindowEnable_MASK)
#define IRIS_MVPL_EXTSRC0_CONTROL_RasterMode_MASK (0x10U)
#define IRIS_MVPL_EXTSRC0_CONTROL_RasterMode_SHIFT (4U)
#define IRIS_MVPL_EXTSRC0_CONTROL_RasterMode(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_EXTSRC0_CONTROL_RasterMode_MASK)
#define IRIS_MVPL_EXTSRC0_CONTROL_YUV422UpsamplingMode_MASK (0x20U)
#define IRIS_MVPL_EXTSRC0_CONTROL_YUV422UpsamplingMode_SHIFT (5U)
#define IRIS_MVPL_EXTSRC0_CONTROL_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONTROL_YUV422UpsamplingMode_SHIFT)) & IRIS_MVPL_EXTSRC0_CONTROL_YUV422UpsamplingMode_MASK)
#define IRIS_MVPL_EXTSRC0_CONTROL_YUVConversionMode_MASK (0xC0U)
#define IRIS_MVPL_EXTSRC0_CONTROL_YUVConversionMode_SHIFT (6U)
#define IRIS_MVPL_EXTSRC0_CONTROL_YUVConversionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONTROL_YUVConversionMode_SHIFT)) & IRIS_MVPL_EXTSRC0_CONTROL_YUVConversionMode_MASK)
#define IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaSrcEnable_MASK (0x100U)
#define IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaSrcEnable_SHIFT (8U)
#define IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaSrcEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaSrcEnable_SHIFT)) & IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaSrcEnable_MASK)
#define IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaConstEnable_MASK (0x200U)
#define IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaConstEnable_SHIFT (9U)
#define IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaConstEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaConstEnable_SHIFT)) & IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaConstEnable_MASK)
#define IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaTransEnable_MASK (0x400U)
#define IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaTransEnable_SHIFT (10U)
#define IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaTransEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaTransEnable_SHIFT)) & IRIS_MVPL_EXTSRC0_CONTROL_RGBAlphaTransEnable_MASK)
#define IRIS_MVPL_EXTSRC0_CONTROL_PremulConstRGB_MASK (0x800U)
#define IRIS_MVPL_EXTSRC0_CONTROL_PremulConstRGB_SHIFT (11U)
#define IRIS_MVPL_EXTSRC0_CONTROL_PremulConstRGB(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONTROL_PremulConstRGB_SHIFT)) & IRIS_MVPL_EXTSRC0_CONTROL_PremulConstRGB_MASK)
#define IRIS_MVPL_EXTSRC0_CONTROL_AlphaSrcEnable_MASK (0x1000U)
#define IRIS_MVPL_EXTSRC0_CONTROL_AlphaSrcEnable_SHIFT (12U)
#define IRIS_MVPL_EXTSRC0_CONTROL_AlphaSrcEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONTROL_AlphaSrcEnable_SHIFT)) & IRIS_MVPL_EXTSRC0_CONTROL_AlphaSrcEnable_MASK)
#define IRIS_MVPL_EXTSRC0_CONTROL_AlphaConstEnable_MASK (0x2000U)
#define IRIS_MVPL_EXTSRC0_CONTROL_AlphaConstEnable_SHIFT (13U)
#define IRIS_MVPL_EXTSRC0_CONTROL_AlphaConstEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONTROL_AlphaConstEnable_SHIFT)) & IRIS_MVPL_EXTSRC0_CONTROL_AlphaConstEnable_MASK)
#define IRIS_MVPL_EXTSRC0_CONTROL_AlphaTransEnable_MASK (0x4000U)
#define IRIS_MVPL_EXTSRC0_CONTROL_AlphaTransEnable_SHIFT (14U)
#define IRIS_MVPL_EXTSRC0_CONTROL_AlphaTransEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONTROL_AlphaTransEnable_SHIFT)) & IRIS_MVPL_EXTSRC0_CONTROL_AlphaTransEnable_MASK)
#define IRIS_MVPL_EXTSRC0_CONTROL_GammaRemoveEnable_MASK (0x10000U)
#define IRIS_MVPL_EXTSRC0_CONTROL_GammaRemoveEnable_SHIFT (16U)
#define IRIS_MVPL_EXTSRC0_CONTROL_GammaRemoveEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONTROL_GammaRemoveEnable_SHIFT)) & IRIS_MVPL_EXTSRC0_CONTROL_GammaRemoveEnable_MASK)

/*! @name EXTSRC0_CONTROLTRIGGER - ExtSrc unit trigger token generation */
#define IRIS_MVPL_EXTSRC0_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_EXTSRC0_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_EXTSRC0_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_EXTSRC0_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name EXTSRC0_START - ExtSrc unit start register */
#define IRIS_MVPL_EXTSRC0_START_Start_MASK       (0x1U)
#define IRIS_MVPL_EXTSRC0_START_Start_SHIFT      (0U)
#define IRIS_MVPL_EXTSRC0_START_Start(x)         (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_START_Start_SHIFT)) & IRIS_MVPL_EXTSRC0_START_Start_MASK)

/*! @name EXTSRC0_LASTCOMMANDWORD - Subset of last input command word with the following mapping: val[31:0]={data[37:22], data[19:12], data[9:2]} */
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_FrameWidth_SHIFT)) & IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_FrameWidth_MASK)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_fld_MASK (0x4000U)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_fld_SHIFT (14U)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_fld(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_fld_SHIFT)) & IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_fld_MASK)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_rld_MASK (0x8000U)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_rld_SHIFT (15U)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_rld(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_rld_SHIFT)) & IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_rld_MASK)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_FrameHeight_SHIFT)) & IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_FrameHeight_MASK)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_ex_MASK (0x40000000U)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_ex_SHIFT (30U)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_ex(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_ex_SHIFT)) & IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_ex_MASK)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_nf_MASK (0x80000000U)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_nf_SHIFT (31U)
#define IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_nf(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_nf_SHIFT)) & IRIS_MVPL_EXTSRC0_LASTCOMMANDWORD_nf_MASK)

/*! @name EXTSRC0_STATUS - Shows status information */
#define IRIS_MVPL_EXTSRC0_STATUS_InputValid_MASK (0x1U)
#define IRIS_MVPL_EXTSRC0_STATUS_InputValid_SHIFT (0U)
#define IRIS_MVPL_EXTSRC0_STATUS_InputValid(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC0_STATUS_InputValid_SHIFT)) & IRIS_MVPL_EXTSRC0_STATUS_InputValid_MASK)

/*! @name EXTSRC1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_EXTSRC1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_EXTSRC1_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_EXTSRC1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_EXTSRC1_LOCKUNLOCK_LockUnlock_MASK)

/*! @name EXTSRC1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_EXTSRC1_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_EXTSRC1_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_EXTSRC1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_EXTSRC1_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_EXTSRC1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_EXTSRC1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_EXTSRC1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTSRC1_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_EXTSRC1_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_EXTSRC1_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_EXTSRC1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTSRC1_LOCKSTATUS_FreezeStatus_MASK)

/*! @name EXTSRC1_STATICCONTROL - ExtSrc static control register */
#define IRIS_MVPL_EXTSRC1_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_EXTSRC1_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_EXTSRC1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_EXTSRC1_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_EXTSRC1_STATICCONTROL_StartSel_MASK (0x100U)
#define IRIS_MVPL_EXTSRC1_STATICCONTROL_StartSel_SHIFT (8U)
#define IRIS_MVPL_EXTSRC1_STATICCONTROL_StartSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_STATICCONTROL_StartSel_SHIFT)) & IRIS_MVPL_EXTSRC1_STATICCONTROL_StartSel_MASK)

/*! @name EXTSRC1_CLIPWINDOWOFFSET - Clip window offset, to generate a clipping of the frame. It has to be within the input frame. */
#define IRIS_MVPL_EXTSRC1_CLIPWINDOWOFFSET_ClipWindowXOffset_MASK (0x3FFFU)
#define IRIS_MVPL_EXTSRC1_CLIPWINDOWOFFSET_ClipWindowXOffset_SHIFT (0U)
#define IRIS_MVPL_EXTSRC1_CLIPWINDOWOFFSET_ClipWindowXOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CLIPWINDOWOFFSET_ClipWindowXOffset_SHIFT)) & IRIS_MVPL_EXTSRC1_CLIPWINDOWOFFSET_ClipWindowXOffset_MASK)
#define IRIS_MVPL_EXTSRC1_CLIPWINDOWOFFSET_ClipWindowYOffset_MASK (0x3FFF0000U)
#define IRIS_MVPL_EXTSRC1_CLIPWINDOWOFFSET_ClipWindowYOffset_SHIFT (16U)
#define IRIS_MVPL_EXTSRC1_CLIPWINDOWOFFSET_ClipWindowYOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CLIPWINDOWOFFSET_ClipWindowYOffset_SHIFT)) & IRIS_MVPL_EXTSRC1_CLIPWINDOWOFFSET_ClipWindowYOffset_MASK)

/*! @name EXTSRC1_CLIPWINDOWDIMENSION - Define the clip window dimension. If the clip window feature is enabled this dimension is used for the new frame dimension. Note that the clip window has to be smaller or equal to the original frame dimensions. The new frame has to be within the active area of the original frame. */
#define IRIS_MVPL_EXTSRC1_CLIPWINDOWDIMENSION_ClipWindowWidth_MASK (0x3FFFU)
#define IRIS_MVPL_EXTSRC1_CLIPWINDOWDIMENSION_ClipWindowWidth_SHIFT (0U)
#define IRIS_MVPL_EXTSRC1_CLIPWINDOWDIMENSION_ClipWindowWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CLIPWINDOWDIMENSION_ClipWindowWidth_SHIFT)) & IRIS_MVPL_EXTSRC1_CLIPWINDOWDIMENSION_ClipWindowWidth_MASK)
#define IRIS_MVPL_EXTSRC1_CLIPWINDOWDIMENSION_ClipWindowHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_EXTSRC1_CLIPWINDOWDIMENSION_ClipWindowHeight_SHIFT (16U)
#define IRIS_MVPL_EXTSRC1_CLIPWINDOWDIMENSION_ClipWindowHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CLIPWINDOWDIMENSION_ClipWindowHeight_SHIFT)) & IRIS_MVPL_EXTSRC1_CLIPWINDOWDIMENSION_ClipWindowHeight_MASK)

/*! @name EXTSRC1_COLORCOMPONENTBITS - Color component size of raw input data. Please note that the width must be equal or lower than the output width. */
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK (0xFU)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT (0U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT)) & IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsBlue_MASK (0xF00U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT (8U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT)) & IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsBlue_MASK)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsGreen_MASK (0xF0000U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT (16U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT)) & IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsGreen_MASK)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsRed_MASK (0xF000000U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT (24U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT)) & IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ComponentBitsRed_MASK)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ITUFormat_MASK (0x80000000U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ITUFormat_SHIFT (31U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ITUFormat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ITUFormat_SHIFT)) & IRIS_MVPL_EXTSRC1_COLORCOMPONENTBITS_ITUFormat_MASK)

/*! @name EXTSRC1_COLORCOMPONENTSHIFT - Color component offset of raw input data. */
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK (0x3FU)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT (0U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT)) & IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK (0x3F00U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT (8U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT)) & IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK (0x3F0000U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT (16U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT)) & IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK (0x3F000000U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT (24U)
#define IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT)) & IRIS_MVPL_EXTSRC1_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK)

/*! @name EXTSRC1_CONSTANTCOLOR - Constant color register */
#define IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU)
#define IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U)
#define IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantAlpha_MASK)
#define IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U)
#define IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantBlue_SHIFT (8U)
#define IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantBlue_MASK)
#define IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U)
#define IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantGreen_SHIFT (16U)
#define IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantGreen_MASK)
#define IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U)
#define IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantRed_SHIFT (24U)
#define IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_EXTSRC1_CONSTANTCOLOR_ConstantRed_MASK)

/*! @name EXTSRC1_CONTROL - Common control settings. */
#define IRIS_MVPL_EXTSRC1_CONTROL_ClipWindowEnable_MASK (0x1U)
#define IRIS_MVPL_EXTSRC1_CONTROL_ClipWindowEnable_SHIFT (0U)
#define IRIS_MVPL_EXTSRC1_CONTROL_ClipWindowEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONTROL_ClipWindowEnable_SHIFT)) & IRIS_MVPL_EXTSRC1_CONTROL_ClipWindowEnable_MASK)
#define IRIS_MVPL_EXTSRC1_CONTROL_RasterMode_MASK (0x10U)
#define IRIS_MVPL_EXTSRC1_CONTROL_RasterMode_SHIFT (4U)
#define IRIS_MVPL_EXTSRC1_CONTROL_RasterMode(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_EXTSRC1_CONTROL_RasterMode_MASK)
#define IRIS_MVPL_EXTSRC1_CONTROL_YUV422UpsamplingMode_MASK (0x20U)
#define IRIS_MVPL_EXTSRC1_CONTROL_YUV422UpsamplingMode_SHIFT (5U)
#define IRIS_MVPL_EXTSRC1_CONTROL_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONTROL_YUV422UpsamplingMode_SHIFT)) & IRIS_MVPL_EXTSRC1_CONTROL_YUV422UpsamplingMode_MASK)
#define IRIS_MVPL_EXTSRC1_CONTROL_YUVConversionMode_MASK (0xC0U)
#define IRIS_MVPL_EXTSRC1_CONTROL_YUVConversionMode_SHIFT (6U)
#define IRIS_MVPL_EXTSRC1_CONTROL_YUVConversionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONTROL_YUVConversionMode_SHIFT)) & IRIS_MVPL_EXTSRC1_CONTROL_YUVConversionMode_MASK)
#define IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaSrcEnable_MASK (0x100U)
#define IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaSrcEnable_SHIFT (8U)
#define IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaSrcEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaSrcEnable_SHIFT)) & IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaSrcEnable_MASK)
#define IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaConstEnable_MASK (0x200U)
#define IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaConstEnable_SHIFT (9U)
#define IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaConstEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaConstEnable_SHIFT)) & IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaConstEnable_MASK)
#define IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaTransEnable_MASK (0x400U)
#define IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaTransEnable_SHIFT (10U)
#define IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaTransEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaTransEnable_SHIFT)) & IRIS_MVPL_EXTSRC1_CONTROL_RGBAlphaTransEnable_MASK)
#define IRIS_MVPL_EXTSRC1_CONTROL_PremulConstRGB_MASK (0x800U)
#define IRIS_MVPL_EXTSRC1_CONTROL_PremulConstRGB_SHIFT (11U)
#define IRIS_MVPL_EXTSRC1_CONTROL_PremulConstRGB(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONTROL_PremulConstRGB_SHIFT)) & IRIS_MVPL_EXTSRC1_CONTROL_PremulConstRGB_MASK)
#define IRIS_MVPL_EXTSRC1_CONTROL_AlphaSrcEnable_MASK (0x1000U)
#define IRIS_MVPL_EXTSRC1_CONTROL_AlphaSrcEnable_SHIFT (12U)
#define IRIS_MVPL_EXTSRC1_CONTROL_AlphaSrcEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONTROL_AlphaSrcEnable_SHIFT)) & IRIS_MVPL_EXTSRC1_CONTROL_AlphaSrcEnable_MASK)
#define IRIS_MVPL_EXTSRC1_CONTROL_AlphaConstEnable_MASK (0x2000U)
#define IRIS_MVPL_EXTSRC1_CONTROL_AlphaConstEnable_SHIFT (13U)
#define IRIS_MVPL_EXTSRC1_CONTROL_AlphaConstEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONTROL_AlphaConstEnable_SHIFT)) & IRIS_MVPL_EXTSRC1_CONTROL_AlphaConstEnable_MASK)
#define IRIS_MVPL_EXTSRC1_CONTROL_AlphaTransEnable_MASK (0x4000U)
#define IRIS_MVPL_EXTSRC1_CONTROL_AlphaTransEnable_SHIFT (14U)
#define IRIS_MVPL_EXTSRC1_CONTROL_AlphaTransEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONTROL_AlphaTransEnable_SHIFT)) & IRIS_MVPL_EXTSRC1_CONTROL_AlphaTransEnable_MASK)
#define IRIS_MVPL_EXTSRC1_CONTROL_GammaRemoveEnable_MASK (0x10000U)
#define IRIS_MVPL_EXTSRC1_CONTROL_GammaRemoveEnable_SHIFT (16U)
#define IRIS_MVPL_EXTSRC1_CONTROL_GammaRemoveEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONTROL_GammaRemoveEnable_SHIFT)) & IRIS_MVPL_EXTSRC1_CONTROL_GammaRemoveEnable_MASK)

/*! @name EXTSRC1_CONTROLTRIGGER - ExtSrc unit trigger token generation */
#define IRIS_MVPL_EXTSRC1_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_EXTSRC1_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_EXTSRC1_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_EXTSRC1_CONTROLTRIGGER_ShdTokGen_MASK)

/*! @name EXTSRC1_START - ExtSrc unit start register */
#define IRIS_MVPL_EXTSRC1_START_Start_MASK       (0x1U)
#define IRIS_MVPL_EXTSRC1_START_Start_SHIFT      (0U)
#define IRIS_MVPL_EXTSRC1_START_Start(x)         (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_START_Start_SHIFT)) & IRIS_MVPL_EXTSRC1_START_Start_MASK)

/*! @name EXTSRC1_LASTCOMMANDWORD - Subset of last input command word with the following mapping: val[31:0]={data[37:22], data[19:12], data[9:2]} */
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_FrameWidth_SHIFT)) & IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_FrameWidth_MASK)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_fld_MASK (0x4000U)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_fld_SHIFT (14U)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_fld(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_fld_SHIFT)) & IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_fld_MASK)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_rld_MASK (0x8000U)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_rld_SHIFT (15U)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_rld(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_rld_SHIFT)) & IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_rld_MASK)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_FrameHeight_SHIFT)) & IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_FrameHeight_MASK)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_ex_MASK (0x40000000U)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_ex_SHIFT (30U)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_ex(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_ex_SHIFT)) & IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_ex_MASK)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_nf_MASK (0x80000000U)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_nf_SHIFT (31U)
#define IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_nf(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_nf_SHIFT)) & IRIS_MVPL_EXTSRC1_LASTCOMMANDWORD_nf_MASK)

/*! @name EXTSRC1_STATUS - Shows status information */
#define IRIS_MVPL_EXTSRC1_STATUS_InputValid_MASK (0x1U)
#define IRIS_MVPL_EXTSRC1_STATUS_InputValid_SHIFT (0U)
#define IRIS_MVPL_EXTSRC1_STATUS_InputValid(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTSRC1_STATUS_InputValid_SHIFT)) & IRIS_MVPL_EXTSRC1_STATUS_InputValid_MASK)

/*! @name DISENGCFG_LOCKUNLOCK0 - Register to change the protection status of this address block. */
#define IRIS_MVPL_DISENGCFG_LOCKUNLOCK0_LockUnlock0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DISENGCFG_LOCKUNLOCK0_LockUnlock0_SHIFT (0U)
#define IRIS_MVPL_DISENGCFG_LOCKUNLOCK0_LockUnlock0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_LOCKUNLOCK0_LockUnlock0_SHIFT)) & IRIS_MVPL_DISENGCFG_LOCKUNLOCK0_LockUnlock0_MASK)

/*! @name DISENGCFG_LOCKSTATUS0 - Protection status of this address block. */
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS0_LockStatus0_MASK (0x1U)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS0_LockStatus0_SHIFT (0U)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS0_LockStatus0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_LOCKSTATUS0_LockStatus0_SHIFT)) & IRIS_MVPL_DISENGCFG_LOCKSTATUS0_LockStatus0_MASK)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS0_PrivilegeStatus0_MASK (0x10U)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS0_PrivilegeStatus0_SHIFT (4U)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS0_PrivilegeStatus0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_LOCKSTATUS0_PrivilegeStatus0_SHIFT)) & IRIS_MVPL_DISENGCFG_LOCKSTATUS0_PrivilegeStatus0_MASK)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS0_FreezeStatus0_MASK (0x100U)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS0_FreezeStatus0_SHIFT (8U)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS0_FreezeStatus0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_LOCKSTATUS0_FreezeStatus0_SHIFT)) & IRIS_MVPL_DISENGCFG_LOCKSTATUS0_FreezeStatus0_MASK)

/*! @name DISENGCFG_CLOCKCTRL0 - Controls generation of display clock signals for display stream 0. */
#define IRIS_MVPL_DISENGCFG_CLOCKCTRL0_DspClkDivide0_MASK (0x1U)
#define IRIS_MVPL_DISENGCFG_CLOCKCTRL0_DspClkDivide0_SHIFT (0U)
#define IRIS_MVPL_DISENGCFG_CLOCKCTRL0_DspClkDivide0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_CLOCKCTRL0_DspClkDivide0_SHIFT)) & IRIS_MVPL_DISENGCFG_CLOCKCTRL0_DspClkDivide0_MASK)

/*! @name DISENGCFG_POLARITYCTRL0 - Polarity control for TCon#0 input and corresponding top-level output (TCon by-pass port). */
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolHs0_MASK (0x1U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolHs0_SHIFT (0U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolHs0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolHs0_SHIFT)) & IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolHs0_MASK)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolVs0_MASK (0x2U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolVs0_SHIFT (1U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolVs0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolVs0_SHIFT)) & IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolVs0_MASK)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolEn0_MASK (0x4U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolEn0_SHIFT (2U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolEn0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolEn0_SHIFT)) & IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PolEn0_MASK)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PixInv0_MASK (0x8U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PixInv0_SHIFT (3U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PixInv0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PixInv0_SHIFT)) & IRIS_MVPL_DISENGCFG_POLARITYCTRL0_PixInv0_MASK)

/*! @name DISENGCFG_SRCSELECT0 - Tap selection for Signature and Frame Dump (display stream 0). */
#define IRIS_MVPL_DISENGCFG_SRCSELECT0_sig_select0_MASK (0x3U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT0_sig_select0_SHIFT (0U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT0_sig_select0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_SRCSELECT0_sig_select0_SHIFT)) & IRIS_MVPL_DISENGCFG_SRCSELECT0_sig_select0_MASK)
#define IRIS_MVPL_DISENGCFG_SRCSELECT0_path_select0_MASK (0x10U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT0_path_select0_SHIFT (4U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT0_path_select0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_SRCSELECT0_path_select0_SHIFT)) & IRIS_MVPL_DISENGCFG_SRCSELECT0_path_select0_MASK)
#define IRIS_MVPL_DISENGCFG_SRCSELECT0_dump0_select0_MASK (0x300U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT0_dump0_select0_SHIFT (8U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT0_dump0_select0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_SRCSELECT0_dump0_select0_SHIFT)) & IRIS_MVPL_DISENGCFG_SRCSELECT0_dump0_select0_MASK)
#define IRIS_MVPL_DISENGCFG_SRCSELECT0_dump1_select0_MASK (0xC00U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT0_dump1_select0_SHIFT (10U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT0_dump1_select0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_SRCSELECT0_dump1_select0_SHIFT)) & IRIS_MVPL_DISENGCFG_SRCSELECT0_dump1_select0_MASK)

/*! @name DISENGCFG_LOCKUNLOCK1 - Register to change the protection status of this address block. */
#define IRIS_MVPL_DISENGCFG_LOCKUNLOCK1_LockUnlock1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DISENGCFG_LOCKUNLOCK1_LockUnlock1_SHIFT (0U)
#define IRIS_MVPL_DISENGCFG_LOCKUNLOCK1_LockUnlock1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_LOCKUNLOCK1_LockUnlock1_SHIFT)) & IRIS_MVPL_DISENGCFG_LOCKUNLOCK1_LockUnlock1_MASK)

/*! @name DISENGCFG_LOCKSTATUS1 - Protection status of this address block. */
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS1_LockStatus1_MASK (0x1U)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS1_LockStatus1_SHIFT (0U)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS1_LockStatus1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_LOCKSTATUS1_LockStatus1_SHIFT)) & IRIS_MVPL_DISENGCFG_LOCKSTATUS1_LockStatus1_MASK)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS1_PrivilegeStatus1_MASK (0x10U)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS1_PrivilegeStatus1_SHIFT (4U)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS1_PrivilegeStatus1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_LOCKSTATUS1_PrivilegeStatus1_SHIFT)) & IRIS_MVPL_DISENGCFG_LOCKSTATUS1_PrivilegeStatus1_MASK)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS1_FreezeStatus1_MASK (0x100U)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS1_FreezeStatus1_SHIFT (8U)
#define IRIS_MVPL_DISENGCFG_LOCKSTATUS1_FreezeStatus1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_LOCKSTATUS1_FreezeStatus1_SHIFT)) & IRIS_MVPL_DISENGCFG_LOCKSTATUS1_FreezeStatus1_MASK)

/*! @name DISENGCFG_CLOCKCTRL1 - Controls generation of display clock signals for display stream 1. */
#define IRIS_MVPL_DISENGCFG_CLOCKCTRL1_DspClkDivide1_MASK (0x1U)
#define IRIS_MVPL_DISENGCFG_CLOCKCTRL1_DspClkDivide1_SHIFT (0U)
#define IRIS_MVPL_DISENGCFG_CLOCKCTRL1_DspClkDivide1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_CLOCKCTRL1_DspClkDivide1_SHIFT)) & IRIS_MVPL_DISENGCFG_CLOCKCTRL1_DspClkDivide1_MASK)

/*! @name DISENGCFG_POLARITYCTRL1 - Polarity control for TCon#1 input and corresponding top-level output (TCon by-pass port). */
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolHs1_MASK (0x1U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolHs1_SHIFT (0U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolHs1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolHs1_SHIFT)) & IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolHs1_MASK)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolVs1_MASK (0x2U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolVs1_SHIFT (1U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolVs1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolVs1_SHIFT)) & IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolVs1_MASK)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolEn1_MASK (0x4U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolEn1_SHIFT (2U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolEn1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolEn1_SHIFT)) & IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PolEn1_MASK)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PixInv1_MASK (0x8U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PixInv1_SHIFT (3U)
#define IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PixInv1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PixInv1_SHIFT)) & IRIS_MVPL_DISENGCFG_POLARITYCTRL1_PixInv1_MASK)

/*! @name DISENGCFG_SRCSELECT1 - Tap selection for Signature and Frame Dump (display stream 1). */
#define IRIS_MVPL_DISENGCFG_SRCSELECT1_sig_select1_MASK (0x3U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT1_sig_select1_SHIFT (0U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT1_sig_select1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_SRCSELECT1_sig_select1_SHIFT)) & IRIS_MVPL_DISENGCFG_SRCSELECT1_sig_select1_MASK)
#define IRIS_MVPL_DISENGCFG_SRCSELECT1_path_select1_MASK (0x10U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT1_path_select1_SHIFT (4U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT1_path_select1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_SRCSELECT1_path_select1_SHIFT)) & IRIS_MVPL_DISENGCFG_SRCSELECT1_path_select1_MASK)
#define IRIS_MVPL_DISENGCFG_SRCSELECT1_dump0_select1_MASK (0x300U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT1_dump0_select1_SHIFT (8U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT1_dump0_select1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_SRCSELECT1_dump0_select1_SHIFT)) & IRIS_MVPL_DISENGCFG_SRCSELECT1_dump0_select1_MASK)
#define IRIS_MVPL_DISENGCFG_SRCSELECT1_dump1_select1_MASK (0xC00U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT1_dump1_select1_SHIFT (10U)
#define IRIS_MVPL_DISENGCFG_SRCSELECT1_dump1_select1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DISENGCFG_SRCSELECT1_dump1_select1_SHIFT)) & IRIS_MVPL_DISENGCFG_SRCSELECT1_dump1_select1_MASK)

/*! @name FRAMEDUMP0_CONTROL - Control settings. */
#define IRIS_MVPL_FRAMEDUMP0_CONTROL_InputSelect_MASK (0x1U)
#define IRIS_MVPL_FRAMEDUMP0_CONTROL_InputSelect_SHIFT (0U)
#define IRIS_MVPL_FRAMEDUMP0_CONTROL_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP0_CONTROL_InputSelect_SHIFT)) & IRIS_MVPL_FRAMEDUMP0_CONTROL_InputSelect_MASK)
#define IRIS_MVPL_FRAMEDUMP0_CONTROL_SetField_MASK (0x1000000U)
#define IRIS_MVPL_FRAMEDUMP0_CONTROL_SetField_SHIFT (24U)
#define IRIS_MVPL_FRAMEDUMP0_CONTROL_SetField(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP0_CONTROL_SetField_SHIFT)) & IRIS_MVPL_FRAMEDUMP0_CONTROL_SetField_MASK)
#define IRIS_MVPL_FRAMEDUMP0_CONTROL_ToggleField_MASK (0x2000000U)
#define IRIS_MVPL_FRAMEDUMP0_CONTROL_ToggleField_SHIFT (25U)
#define IRIS_MVPL_FRAMEDUMP0_CONTROL_ToggleField(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP0_CONTROL_ToggleField_SHIFT)) & IRIS_MVPL_FRAMEDUMP0_CONTROL_ToggleField_MASK)

/*! @name FRAMEDUMP0_FRAMESIZE - Dump window size. */
#define IRIS_MVPL_FRAMEDUMP0_FRAMESIZE_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEDUMP0_FRAMESIZE_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FRAMEDUMP0_FRAMESIZE_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP0_FRAMESIZE_FrameWidth_SHIFT)) & IRIS_MVPL_FRAMEDUMP0_FRAMESIZE_FrameWidth_MASK)
#define IRIS_MVPL_FRAMEDUMP0_FRAMESIZE_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEDUMP0_FRAMESIZE_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FRAMEDUMP0_FRAMESIZE_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP0_FRAMESIZE_FrameHeight_SHIFT)) & IRIS_MVPL_FRAMEDUMP0_FRAMESIZE_FrameHeight_MASK)

/*! @name FRAMEDUMP0_INPUTSETUP - Dump window position. */
#define IRIS_MVPL_FRAMEDUMP0_INPUTSETUP_InputCaptureXOffset_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEDUMP0_INPUTSETUP_InputCaptureXOffset_SHIFT (0U)
#define IRIS_MVPL_FRAMEDUMP0_INPUTSETUP_InputCaptureXOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP0_INPUTSETUP_InputCaptureXOffset_SHIFT)) & IRIS_MVPL_FRAMEDUMP0_INPUTSETUP_InputCaptureXOffset_MASK)
#define IRIS_MVPL_FRAMEDUMP0_INPUTSETUP_InputCaptureYOffset_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEDUMP0_INPUTSETUP_InputCaptureYOffset_SHIFT (16U)
#define IRIS_MVPL_FRAMEDUMP0_INPUTSETUP_InputCaptureYOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP0_INPUTSETUP_InputCaptureYOffset_SHIFT)) & IRIS_MVPL_FRAMEDUMP0_INPUTSETUP_InputCaptureYOffset_MASK)

/*! @name FRAMEDUMP0_ENABLE - Enable register. */
#define IRIS_MVPL_FRAMEDUMP0_ENABLE_DumpEn_MASK  (0x1U)
#define IRIS_MVPL_FRAMEDUMP0_ENABLE_DumpEn_SHIFT (0U)
#define IRIS_MVPL_FRAMEDUMP0_ENABLE_DumpEn(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP0_ENABLE_DumpEn_SHIFT)) & IRIS_MVPL_FRAMEDUMP0_ENABLE_DumpEn_MASK)

/*! @name FRAMEDUMP0_TRIGGER - Trigger bits. */
#define IRIS_MVPL_FRAMEDUMP0_TRIGGER_DumpReq_MASK (0x1U)
#define IRIS_MVPL_FRAMEDUMP0_TRIGGER_DumpReq_SHIFT (0U)
#define IRIS_MVPL_FRAMEDUMP0_TRIGGER_DumpReq(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP0_TRIGGER_DumpReq_SHIFT)) & IRIS_MVPL_FRAMEDUMP0_TRIGGER_DumpReq_MASK)

/*! @name FRAMEDUMP0_STATUS - Status register. */
#define IRIS_MVPL_FRAMEDUMP0_STATUS_DumpIdle_MASK (0x1U)
#define IRIS_MVPL_FRAMEDUMP0_STATUS_DumpIdle_SHIFT (0U)
#define IRIS_MVPL_FRAMEDUMP0_STATUS_DumpIdle(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP0_STATUS_DumpIdle_SHIFT)) & IRIS_MVPL_FRAMEDUMP0_STATUS_DumpIdle_MASK)

/*! @name FRAMEDUMP1_CONTROL - Control settings. */
#define IRIS_MVPL_FRAMEDUMP1_CONTROL_InputSelect_MASK (0x1U)
#define IRIS_MVPL_FRAMEDUMP1_CONTROL_InputSelect_SHIFT (0U)
#define IRIS_MVPL_FRAMEDUMP1_CONTROL_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP1_CONTROL_InputSelect_SHIFT)) & IRIS_MVPL_FRAMEDUMP1_CONTROL_InputSelect_MASK)
#define IRIS_MVPL_FRAMEDUMP1_CONTROL_SetField_MASK (0x1000000U)
#define IRIS_MVPL_FRAMEDUMP1_CONTROL_SetField_SHIFT (24U)
#define IRIS_MVPL_FRAMEDUMP1_CONTROL_SetField(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP1_CONTROL_SetField_SHIFT)) & IRIS_MVPL_FRAMEDUMP1_CONTROL_SetField_MASK)
#define IRIS_MVPL_FRAMEDUMP1_CONTROL_ToggleField_MASK (0x2000000U)
#define IRIS_MVPL_FRAMEDUMP1_CONTROL_ToggleField_SHIFT (25U)
#define IRIS_MVPL_FRAMEDUMP1_CONTROL_ToggleField(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP1_CONTROL_ToggleField_SHIFT)) & IRIS_MVPL_FRAMEDUMP1_CONTROL_ToggleField_MASK)

/*! @name FRAMEDUMP1_FRAMESIZE - Dump window size. */
#define IRIS_MVPL_FRAMEDUMP1_FRAMESIZE_FrameWidth_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEDUMP1_FRAMESIZE_FrameWidth_SHIFT (0U)
#define IRIS_MVPL_FRAMEDUMP1_FRAMESIZE_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP1_FRAMESIZE_FrameWidth_SHIFT)) & IRIS_MVPL_FRAMEDUMP1_FRAMESIZE_FrameWidth_MASK)
#define IRIS_MVPL_FRAMEDUMP1_FRAMESIZE_FrameHeight_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEDUMP1_FRAMESIZE_FrameHeight_SHIFT (16U)
#define IRIS_MVPL_FRAMEDUMP1_FRAMESIZE_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP1_FRAMESIZE_FrameHeight_SHIFT)) & IRIS_MVPL_FRAMEDUMP1_FRAMESIZE_FrameHeight_MASK)

/*! @name FRAMEDUMP1_INPUTSETUP - Dump window position. */
#define IRIS_MVPL_FRAMEDUMP1_INPUTSETUP_InputCaptureXOffset_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEDUMP1_INPUTSETUP_InputCaptureXOffset_SHIFT (0U)
#define IRIS_MVPL_FRAMEDUMP1_INPUTSETUP_InputCaptureXOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP1_INPUTSETUP_InputCaptureXOffset_SHIFT)) & IRIS_MVPL_FRAMEDUMP1_INPUTSETUP_InputCaptureXOffset_MASK)
#define IRIS_MVPL_FRAMEDUMP1_INPUTSETUP_InputCaptureYOffset_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEDUMP1_INPUTSETUP_InputCaptureYOffset_SHIFT (16U)
#define IRIS_MVPL_FRAMEDUMP1_INPUTSETUP_InputCaptureYOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP1_INPUTSETUP_InputCaptureYOffset_SHIFT)) & IRIS_MVPL_FRAMEDUMP1_INPUTSETUP_InputCaptureYOffset_MASK)

/*! @name FRAMEDUMP1_ENABLE - Enable register. */
#define IRIS_MVPL_FRAMEDUMP1_ENABLE_DumpEn_MASK  (0x1U)
#define IRIS_MVPL_FRAMEDUMP1_ENABLE_DumpEn_SHIFT (0U)
#define IRIS_MVPL_FRAMEDUMP1_ENABLE_DumpEn(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP1_ENABLE_DumpEn_SHIFT)) & IRIS_MVPL_FRAMEDUMP1_ENABLE_DumpEn_MASK)

/*! @name FRAMEDUMP1_TRIGGER - Trigger bits. */
#define IRIS_MVPL_FRAMEDUMP1_TRIGGER_DumpReq_MASK (0x1U)
#define IRIS_MVPL_FRAMEDUMP1_TRIGGER_DumpReq_SHIFT (0U)
#define IRIS_MVPL_FRAMEDUMP1_TRIGGER_DumpReq(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP1_TRIGGER_DumpReq_SHIFT)) & IRIS_MVPL_FRAMEDUMP1_TRIGGER_DumpReq_MASK)

/*! @name FRAMEDUMP1_STATUS - Status register. */
#define IRIS_MVPL_FRAMEDUMP1_STATUS_DumpIdle_MASK (0x1U)
#define IRIS_MVPL_FRAMEDUMP1_STATUS_DumpIdle_SHIFT (0U)
#define IRIS_MVPL_FRAMEDUMP1_STATUS_DumpIdle(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEDUMP1_STATUS_DumpIdle_SHIFT)) & IRIS_MVPL_FRAMEDUMP1_STATUS_DumpIdle_MASK)

/*! @name FRAMEGEN0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FRAMEGEN0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FRAMEGEN0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FRAMEGEN0_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FRAMEGEN0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FRAMEGEN0_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FRAMEGEN0_FGSTCTRL - FrameGen Static Control Register */
#define IRIS_MVPL_FRAMEGEN0_FGSTCTRL_ShdEn_MASK  (0x1U)
#define IRIS_MVPL_FRAMEGEN0_FGSTCTRL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGSTCTRL_ShdEn(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSTCTRL_ShdEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSTCTRL_ShdEn_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGSTCTRL_FgSyncMode_MASK (0x6U)
#define IRIS_MVPL_FRAMEGEN0_FGSTCTRL_FgSyncMode_SHIFT (1U)
#define IRIS_MVPL_FRAMEGEN0_FGSTCTRL_FgSyncMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSTCTRL_FgSyncMode_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSTCTRL_FgSyncMode_MASK)

/*! @name FRAMEGEN0_HTCFG1 - FrameGen Horizontal Timing Config Register 1 */
#define IRIS_MVPL_FRAMEGEN0_HTCFG1_Hact_MASK     (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_HTCFG1_Hact_SHIFT    (0U)
#define IRIS_MVPL_FRAMEGEN0_HTCFG1_Hact(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_HTCFG1_Hact_SHIFT)) & IRIS_MVPL_FRAMEGEN0_HTCFG1_Hact_MASK)
#define IRIS_MVPL_FRAMEGEN0_HTCFG1_Htotal_MASK   (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN0_HTCFG1_Htotal_SHIFT  (16U)
#define IRIS_MVPL_FRAMEGEN0_HTCFG1_Htotal(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_HTCFG1_Htotal_SHIFT)) & IRIS_MVPL_FRAMEGEN0_HTCFG1_Htotal_MASK)

/*! @name FRAMEGEN0_HTCFG2 - FrameGen Horizontal Timing Config Register 2 */
#define IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsync_MASK    (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsync_SHIFT   (0U)
#define IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsync(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsync_SHIFT)) & IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsync_MASK)
#define IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsbp_MASK     (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsbp_SHIFT    (16U)
#define IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsbp(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsbp_SHIFT)) & IRIS_MVPL_FRAMEGEN0_HTCFG2_Hsbp_MASK)
#define IRIS_MVPL_FRAMEGEN0_HTCFG2_HsEn_MASK     (0x80000000U)
#define IRIS_MVPL_FRAMEGEN0_HTCFG2_HsEn_SHIFT    (31U)
#define IRIS_MVPL_FRAMEGEN0_HTCFG2_HsEn(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_HTCFG2_HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_HTCFG2_HsEn_MASK)

/*! @name FRAMEGEN0_VTCFG1 - FrameGen Vertical Timing Config Register 1 */
#define IRIS_MVPL_FRAMEGEN0_VTCFG1_Vact_MASK     (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_VTCFG1_Vact_SHIFT    (0U)
#define IRIS_MVPL_FRAMEGEN0_VTCFG1_Vact(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_VTCFG1_Vact_SHIFT)) & IRIS_MVPL_FRAMEGEN0_VTCFG1_Vact_MASK)
#define IRIS_MVPL_FRAMEGEN0_VTCFG1_Vtotal_MASK   (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN0_VTCFG1_Vtotal_SHIFT  (16U)
#define IRIS_MVPL_FRAMEGEN0_VTCFG1_Vtotal(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_VTCFG1_Vtotal_SHIFT)) & IRIS_MVPL_FRAMEGEN0_VTCFG1_Vtotal_MASK)

/*! @name FRAMEGEN0_VTCFG2 - FrameGen Vertical Timing Config Register 2 */
#define IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsync_MASK    (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsync_SHIFT   (0U)
#define IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsync(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsync_SHIFT)) & IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsync_MASK)
#define IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsbp_MASK     (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsbp_SHIFT    (16U)
#define IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsbp(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsbp_SHIFT)) & IRIS_MVPL_FRAMEGEN0_VTCFG2_Vsbp_MASK)
#define IRIS_MVPL_FRAMEGEN0_VTCFG2_VsEn_MASK     (0x80000000U)
#define IRIS_MVPL_FRAMEGEN0_VTCFG2_VsEn_SHIFT    (31U)
#define IRIS_MVPL_FRAMEGEN0_VTCFG2_VsEn(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_VTCFG2_VsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_VTCFG2_VsEn_MASK)

/*! @name FRAMEGEN0_INT0CONFIG - Coordinates of the trigger point for generation of the Int0 interrupt signal */
#define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Col_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Col_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Col_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Col_MASK)
#define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0HsEn_MASK (0x8000U)
#define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0HsEn_SHIFT (15U)
#define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0HsEn_MASK)
#define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Row_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Row_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Row_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0Row_MASK)
#define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0En_MASK (0x80000000U)
#define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0En_SHIFT (31U)
#define IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0En_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT0CONFIG_Int0En_MASK)

/*! @name FRAMEGEN0_INT1CONFIG - Coordinates of the trigger point for generation of the Int1 interrupt signal */
#define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Col_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Col_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Col_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Col_MASK)
#define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1HsEn_MASK (0x8000U)
#define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1HsEn_SHIFT (15U)
#define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1HsEn_MASK)
#define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Row_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Row_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Row_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1Row_MASK)
#define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1En_MASK (0x80000000U)
#define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1En_SHIFT (31U)
#define IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1En_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT1CONFIG_Int1En_MASK)

/*! @name FRAMEGEN0_INT2CONFIG - Coordinates of the trigger point for generation of the Int2 interrupt signal */
#define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Col_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Col_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Col_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Col_MASK)
#define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2HsEn_MASK (0x8000U)
#define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2HsEn_SHIFT (15U)
#define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2HsEn_MASK)
#define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Row_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Row_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Row_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2Row_MASK)
#define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2En_MASK (0x80000000U)
#define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2En_SHIFT (31U)
#define IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2En_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT2CONFIG_Int2En_MASK)

/*! @name FRAMEGEN0_INT3CONFIG - Coordinates of the trigger point for generation of the Int3 interrupt signal */
#define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Col_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Col_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Col_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Col_MASK)
#define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3HsEn_MASK (0x8000U)
#define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3HsEn_SHIFT (15U)
#define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3HsEn_MASK)
#define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Row_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Row_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Row_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3Row_MASK)
#define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3En_MASK (0x80000000U)
#define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3En_SHIFT (31U)
#define IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3En_SHIFT)) & IRIS_MVPL_FRAMEGEN0_INT3CONFIG_Int3En_MASK)

/*! @name FRAMEGEN0_PKICKCONFIG - Coordinates of the trigger point for generation of the primary kick signal */
#define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickCol_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickCol_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickCol(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickCol_SHIFT)) & IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickCol_MASK)
#define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickInt0En_MASK (0x8000U)
#define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickInt0En_SHIFT (15U)
#define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickInt0En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickInt0En_SHIFT)) & IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickInt0En_MASK)
#define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickRow_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickRow_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickRow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickRow_SHIFT)) & IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickRow_MASK)
#define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickEn_MASK (0x80000000U)
#define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickEn_SHIFT (31U)
#define IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_PKICKCONFIG_PKickEn_MASK)

/*! @name FRAMEGEN0_SKICKCONFIG - Coordinates of the trigger point for generation of the secondary kick signal */
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickCol_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickCol_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickCol(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickCol_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickCol_MASK)
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickInt1En_MASK (0x8000U)
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickInt1En_SHIFT (15U)
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickInt1En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickInt1En_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickInt1En_MASK)
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickRow_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickRow_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickRow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickRow_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickRow_MASK)
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickTrig_MASK (0x40000000U)
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickTrig_SHIFT (30U)
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickTrig(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickTrig_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickTrig_MASK)
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickEn_MASK (0x80000000U)
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickEn_SHIFT (31U)
#define IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SKICKCONFIG_SKickEn_MASK)

/*! @name FRAMEGEN0_SECSTATCONFIG - Configuration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register. */
#define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevGoodFrames_MASK (0xFU)
#define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevGoodFrames_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevGoodFrames(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevGoodFrames_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevGoodFrames_MASK)
#define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevBadFrames_MASK (0xF0U)
#define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevBadFrames_SHIFT (4U)
#define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevBadFrames(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevBadFrames_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevBadFrames_MASK)
#define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevSkewInRange_MASK (0xF00U)
#define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevSkewInRange_SHIFT (8U)
#define IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevSkewInRange(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevSkewInRange_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SECSTATCONFIG_LevSkewInRange_MASK)

/*! @name FRAMEGEN0_FGSRCR1 - FrameGen Skew Regulation Control Register 1. */
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREn_MASK    (0x1U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREn_SHIFT   (0U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREn(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREn_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRMode_MASK  (0x6U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRMode_SHIFT (1U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRMode(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRMode_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRMode_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRAdj_MASK   (0x8U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRAdj_SHIFT  (3U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRAdj(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRAdj_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRAdj_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREven_MASK  (0x10U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREven_SHIFT (4U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREven(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREven_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREven_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRFastSync_MASK (0x20U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRFastSync_SHIFT (5U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRFastSync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRFastSync_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRFastSync_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQAlign_MASK (0x40U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQAlign_SHIFT (6U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQAlign(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQAlign_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQAlign_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQVal_MASK  (0x180U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQVal_SHIFT (7U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQVal(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQVal_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRQVal_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRDbgDisp_MASK (0x10000U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRDbgDisp_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRDbgDisp(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRDbgDisp_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SRDbgDisp_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREpOff_MASK (0x20000U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREpOff_SHIFT (17U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREpOff(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREpOff_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR1_SREpOff_MASK)

/*! @name FRAMEGEN0_FGSRCR2 - FrameGen Skew Regulation Control Register 2 */
#define IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMin_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMin_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMin(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMin_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMin_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMax_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMax_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMax_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR2_HTotalMax_MASK)

/*! @name FRAMEGEN0_FGSRCR3 - FrameGen Skew Regulation Control Register 3 */
#define IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMin_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMin_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMin(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMin_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMin_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMax_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMax_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMax_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR3_VTotalMax_MASK)

/*! @name FRAMEGEN0_FGSRCR4 - FrameGen Skew Regulation Control Register 4 */
#define IRIS_MVPL_FRAMEGEN0_FGSRCR4_TargetSkew_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR4_TargetSkew_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR4_TargetSkew(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR4_TargetSkew_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR4_TargetSkew_MASK)

/*! @name FRAMEGEN0_FGSRCR5 - FrameGen Skew Regulation Control Register 5 */
#define IRIS_MVPL_FRAMEGEN0_FGSRCR5_SyncRangeLow_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR5_SyncRangeLow_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR5_SyncRangeLow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR5_SyncRangeLow_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR5_SyncRangeLow_MASK)

/*! @name FRAMEGEN0_FGSRCR6 - FrameGen Skew Regulation Control Register 6 */
#define IRIS_MVPL_FRAMEGEN0_FGSRCR6_SyncRangeHigh_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR6_SyncRangeHigh_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGSRCR6_SyncRangeHigh(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRCR6_SyncRangeHigh_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRCR6_SyncRangeHigh_MASK)

/*! @name FRAMEGEN0_FGKSDR - FrameGen Kick System Debug Register */
#define IRIS_MVPL_FRAMEGEN0_FGKSDR_PCntCplMax_MASK (0x7U)
#define IRIS_MVPL_FRAMEGEN0_FGKSDR_PCntCplMax_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGKSDR_PCntCplMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGKSDR_PCntCplMax_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGKSDR_PCntCplMax_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGKSDR_SCntCplMax_MASK (0x70000U)
#define IRIS_MVPL_FRAMEGEN0_FGKSDR_SCntCplMax_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN0_FGKSDR_SCntCplMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGKSDR_SCntCplMax_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGKSDR_SCntCplMax_MASK)

/*! @name FRAMEGEN0_PACFG - FrameGen Primary Area Config Register 1 (shadowed) */
#define IRIS_MVPL_FRAMEGEN0_PACFG_Pstartx_MASK   (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_PACFG_Pstartx_SHIFT  (0U)
#define IRIS_MVPL_FRAMEGEN0_PACFG_Pstartx(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_PACFG_Pstartx_SHIFT)) & IRIS_MVPL_FRAMEGEN0_PACFG_Pstartx_MASK)
#define IRIS_MVPL_FRAMEGEN0_PACFG_Pstarty_MASK   (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN0_PACFG_Pstarty_SHIFT  (16U)
#define IRIS_MVPL_FRAMEGEN0_PACFG_Pstarty(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_PACFG_Pstarty_SHIFT)) & IRIS_MVPL_FRAMEGEN0_PACFG_Pstarty_MASK)

/*! @name FRAMEGEN0_SACFG - FrameGen Secondary Area Config Register 1 (shadowed) */
#define IRIS_MVPL_FRAMEGEN0_SACFG_Sstartx_MASK   (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_SACFG_Sstartx_SHIFT  (0U)
#define IRIS_MVPL_FRAMEGEN0_SACFG_Sstartx(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SACFG_Sstartx_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SACFG_Sstartx_MASK)
#define IRIS_MVPL_FRAMEGEN0_SACFG_Sstarty_MASK   (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN0_SACFG_Sstarty_SHIFT  (16U)
#define IRIS_MVPL_FRAMEGEN0_SACFG_Sstarty(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_SACFG_Sstarty_SHIFT)) & IRIS_MVPL_FRAMEGEN0_SACFG_Sstarty_MASK)

/*! @name FRAMEGEN0_FGINCTRL - FrameGen Input Control Register (shadowed) */
#define IRIS_MVPL_FRAMEGEN0_FGINCTRL_FgDm_MASK   (0x7U)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRL_FgDm_SHIFT  (0U)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRL_FgDm(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGINCTRL_FgDm_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGINCTRL_FgDm_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnPrimAlpha_MASK (0x8U)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnPrimAlpha_SHIFT (3U)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnPrimAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnPrimAlpha_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnPrimAlpha_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnSecAlpha_MASK (0x10U)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnSecAlpha_SHIFT (4U)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnSecAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnSecAlpha_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGINCTRL_EnSecAlpha_MASK)

/*! @name FRAMEGEN0_FGINCTRLPANIC - FrameGen Input Control Panic Register (shadowed) */
#define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_FgDmPanic_MASK (0x7U)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_FgDmPanic_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_FgDmPanic(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_FgDmPanic_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_FgDmPanic_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnPrimAlphaPanic_MASK (0x8U)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnPrimAlphaPanic_SHIFT (3U)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnPrimAlphaPanic(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnPrimAlphaPanic_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnPrimAlphaPanic_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnSecAlphaPanic_MASK (0x10U)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnSecAlphaPanic_SHIFT (4U)
#define IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnSecAlphaPanic(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnSecAlphaPanic_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGINCTRLPANIC_EnSecAlphaPanic_MASK)

/*! @name FRAMEGEN0_FGCCR - FrameGen Constant Color Register (shadowed) */
#define IRIS_MVPL_FRAMEGEN0_FGCCR_CcBlue_MASK    (0x3FFU)
#define IRIS_MVPL_FRAMEGEN0_FGCCR_CcBlue_SHIFT   (0U)
#define IRIS_MVPL_FRAMEGEN0_FGCCR_CcBlue(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCCR_CcBlue_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCCR_CcBlue_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGCCR_CcGreen_MASK   (0xFFC00U)
#define IRIS_MVPL_FRAMEGEN0_FGCCR_CcGreen_SHIFT  (10U)
#define IRIS_MVPL_FRAMEGEN0_FGCCR_CcGreen(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCCR_CcGreen_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCCR_CcGreen_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGCCR_CcRed_MASK     (0x3FF00000U)
#define IRIS_MVPL_FRAMEGEN0_FGCCR_CcRed_SHIFT    (20U)
#define IRIS_MVPL_FRAMEGEN0_FGCCR_CcRed(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCCR_CcRed_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCCR_CcRed_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGCCR_CcAlpha_MASK   (0x40000000U)
#define IRIS_MVPL_FRAMEGEN0_FGCCR_CcAlpha_SHIFT  (30U)
#define IRIS_MVPL_FRAMEGEN0_FGCCR_CcAlpha(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCCR_CcAlpha_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCCR_CcAlpha_MASK)

/*! @name FRAMEGEN0_FGENABLE - FrameGen Enable Register */
#define IRIS_MVPL_FRAMEGEN0_FGENABLE_FgEn_MASK   (0x1U)
#define IRIS_MVPL_FRAMEGEN0_FGENABLE_FgEn_SHIFT  (0U)
#define IRIS_MVPL_FRAMEGEN0_FGENABLE_FgEn(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGENABLE_FgEn_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGENABLE_FgEn_MASK)

/*! @name FRAMEGEN0_FGSLR - FrameGen Shadow Load Register */
#define IRIS_MVPL_FRAMEGEN0_FGSLR_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FRAMEGEN0_FGSLR_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGSLR_ShdTokGen(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSLR_ShdTokGen_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSLR_ShdTokGen_MASK)

/*! @name FRAMEGEN0_FGENSTS - FrameGen Enable Status Register */
#define IRIS_MVPL_FRAMEGEN0_FGENSTS_EnSts_MASK   (0x1U)
#define IRIS_MVPL_FRAMEGEN0_FGENSTS_EnSts_SHIFT  (0U)
#define IRIS_MVPL_FRAMEGEN0_FGENSTS_EnSts(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGENSTS_EnSts_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGENSTS_EnSts_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGENSTS_PanicStat_MASK (0x2U)
#define IRIS_MVPL_FRAMEGEN0_FGENSTS_PanicStat_SHIFT (1U)
#define IRIS_MVPL_FRAMEGEN0_FGENSTS_PanicStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGENSTS_PanicStat_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGENSTS_PanicStat_MASK)

/*! @name FRAMEGEN0_FGTIMESTAMP - Time stamp status. */
#define IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_LineIndex_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_LineIndex_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_LineIndex(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_LineIndex_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_LineIndex_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_FrameIndex_MASK (0xFFFFC000U)
#define IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_FrameIndex_SHIFT (14U)
#define IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_FrameIndex(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_FrameIndex_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGTIMESTAMP_FrameIndex_MASK)

/*! @name FRAMEGEN0_FGCHSTAT - FrameGen Channel Status Register */
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PFifoEmpty_MASK (0x1U)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PFifoEmpty_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PFifoEmpty(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PFifoEmpty_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PFifoEmpty_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PrimSyncStat_MASK (0x100U)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PrimSyncStat_SHIFT (8U)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PrimSyncStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PrimSyncStat_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCHSTAT_PrimSyncStat_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SFifoEmpty_MASK (0x10000U)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SFifoEmpty_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SFifoEmpty(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SFifoEmpty_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SFifoEmpty_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SkewRangeErr_MASK (0x20000U)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SkewRangeErr_SHIFT (17U)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SkewRangeErr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SkewRangeErr_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SkewRangeErr_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SecSyncStat_MASK (0x1000000U)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SecSyncStat_SHIFT (24U)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SecSyncStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SecSyncStat_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCHSTAT_SecSyncStat_MASK)

/*! @name FRAMEGEN0_FGCHSTATCLR - FrameGen Channel Status Clear Register */
#define IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrPrimStat_MASK (0x1U)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrPrimStat_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrPrimStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrPrimStat_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrPrimStat_MASK)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrSecStat_MASK (0x10000U)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrSecStat_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrSecStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrSecStat_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGCHSTATCLR_ClrSecStat_MASK)

/*! @name FRAMEGEN0_FGSKEWMON - FrameGen Skew Monitor Register for Secondary Channel Skew Control */
#define IRIS_MVPL_FRAMEGEN0_FGSKEWMON_SkewMon_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_FRAMEGEN0_FGSKEWMON_SkewMon_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGSKEWMON_SkewMon(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSKEWMON_SkewMon_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSKEWMON_SkewMon_MASK)

/*! @name FRAMEGEN0_FGSFIFOMIN - FrameGen Secondary FIFO Min Fill Register */
#define IRIS_MVPL_FRAMEGEN0_FGSFIFOMIN_SFifoMin_MASK (0xFFFU)
#define IRIS_MVPL_FRAMEGEN0_FGSFIFOMIN_SFifoMin_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGSFIFOMIN_SFifoMin(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSFIFOMIN_SFifoMin_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSFIFOMIN_SFifoMin_MASK)

/*! @name FRAMEGEN0_FGSFIFOMAX - FrameGen Secondary FIFO Max Fill Register */
#define IRIS_MVPL_FRAMEGEN0_FGSFIFOMAX_SFifoMax_MASK (0xFFFU)
#define IRIS_MVPL_FRAMEGEN0_FGSFIFOMAX_SFifoMax_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGSFIFOMAX_SFifoMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSFIFOMAX_SFifoMax_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSFIFOMAX_SFifoMax_MASK)

/*! @name FRAMEGEN0_FGSFIFOFILLCLR - FrameGen Secondary FIFO Fill Clear Register */
#define IRIS_MVPL_FRAMEGEN0_FGSFIFOFILLCLR_SFifoFillClr_MASK (0x1U)
#define IRIS_MVPL_FRAMEGEN0_FGSFIFOFILLCLR_SFifoFillClr_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN0_FGSFIFOFILLCLR_SFifoFillClr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSFIFOFILLCLR_SFifoFillClr_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSFIFOFILLCLR_SFifoFillClr_MASK)

/*! @name FRAMEGEN0_FGSREPD - FrameGen Skew Regulation ExtraPolation Debug Register */
#define IRIS_MVPL_FRAMEGEN0_FGSREPD_EpVal_MASK   (0x1FFFFFFFU)
#define IRIS_MVPL_FRAMEGEN0_FGSREPD_EpVal_SHIFT  (0U)
#define IRIS_MVPL_FRAMEGEN0_FGSREPD_EpVal(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSREPD_EpVal_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSREPD_EpVal_MASK)

/*! @name FRAMEGEN0_FGSRFTD - FrameGen Skew Regulation Frame Total Debug Register */
#define IRIS_MVPL_FRAMEGEN0_FGSRFTD_FrTot_MASK   (0xFFFFFFFU)
#define IRIS_MVPL_FRAMEGEN0_FGSRFTD_FrTot_SHIFT  (0U)
#define IRIS_MVPL_FRAMEGEN0_FGSRFTD_FrTot(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN0_FGSRFTD_FrTot_SHIFT)) & IRIS_MVPL_FRAMEGEN0_FGSRFTD_FrTot_MASK)

/*! @name MATRIX0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_MATRIX0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_MATRIX0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_MATRIX0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX0_LOCKUNLOCK_LockUnlock_MASK)

/*! @name MATRIX0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_MATRIX0_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_MATRIX0_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_MATRIX0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX0_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_MATRIX0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_MATRIX0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_MATRIX0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX0_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_MATRIX0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_MATRIX0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_MATRIX0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX0_LOCKSTATUS_FreezeStatus_MASK)

/*! @name MATRIX0_STATICCONTROL - Color Matrix static control register */
#define IRIS_MVPL_MATRIX0_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_MATRIX0_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_MATRIX0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_MATRIX0_STATICCONTROL_ShdEn_MASK)

/*! @name MATRIX0_CONTROL - Color Matrix control register */
#define IRIS_MVPL_MATRIX0_CONTROL_MODE_MASK      (0x3U)
#define IRIS_MVPL_MATRIX0_CONTROL_MODE_SHIFT     (0U)
#define IRIS_MVPL_MATRIX0_CONTROL_MODE(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_CONTROL_MODE_SHIFT)) & IRIS_MVPL_MATRIX0_CONTROL_MODE_MASK)
#define IRIS_MVPL_MATRIX0_CONTROL_AlphaMask_MASK (0x10U)
#define IRIS_MVPL_MATRIX0_CONTROL_AlphaMask_SHIFT (4U)
#define IRIS_MVPL_MATRIX0_CONTROL_AlphaMask(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_MATRIX0_CONTROL_AlphaMask_MASK)
#define IRIS_MVPL_MATRIX0_CONTROL_AlphaInvert_MASK (0x20U)
#define IRIS_MVPL_MATRIX0_CONTROL_AlphaInvert_SHIFT (5U)
#define IRIS_MVPL_MATRIX0_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_MATRIX0_CONTROL_AlphaInvert_MASK)

/*! @name MATRIX0_RED0 - Matrix values for calculation of the red output value. */
#define IRIS_MVPL_MATRIX0_RED0_A11_MASK          (0x1FFFU)
#define IRIS_MVPL_MATRIX0_RED0_A11_SHIFT         (0U)
#define IRIS_MVPL_MATRIX0_RED0_A11(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_RED0_A11_SHIFT)) & IRIS_MVPL_MATRIX0_RED0_A11_MASK)
#define IRIS_MVPL_MATRIX0_RED0_A12_MASK          (0x1FFF0000U)
#define IRIS_MVPL_MATRIX0_RED0_A12_SHIFT         (16U)
#define IRIS_MVPL_MATRIX0_RED0_A12(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_RED0_A12_SHIFT)) & IRIS_MVPL_MATRIX0_RED0_A12_MASK)

/*! @name MATRIX0_RED1 - Matrix values for calculation of the red output value. */
#define IRIS_MVPL_MATRIX0_RED1_A13_MASK          (0x1FFFU)
#define IRIS_MVPL_MATRIX0_RED1_A13_SHIFT         (0U)
#define IRIS_MVPL_MATRIX0_RED1_A13(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_RED1_A13_SHIFT)) & IRIS_MVPL_MATRIX0_RED1_A13_MASK)
#define IRIS_MVPL_MATRIX0_RED1_A14_MASK          (0x1FFF0000U)
#define IRIS_MVPL_MATRIX0_RED1_A14_SHIFT         (16U)
#define IRIS_MVPL_MATRIX0_RED1_A14(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_RED1_A14_SHIFT)) & IRIS_MVPL_MATRIX0_RED1_A14_MASK)

/*! @name MATRIX0_GREEN0 - Matrix values for calculation of the green output value. */
#define IRIS_MVPL_MATRIX0_GREEN0_A21_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX0_GREEN0_A21_SHIFT       (0U)
#define IRIS_MVPL_MATRIX0_GREEN0_A21(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_GREEN0_A21_SHIFT)) & IRIS_MVPL_MATRIX0_GREEN0_A21_MASK)
#define IRIS_MVPL_MATRIX0_GREEN0_A22_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX0_GREEN0_A22_SHIFT       (16U)
#define IRIS_MVPL_MATRIX0_GREEN0_A22(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_GREEN0_A22_SHIFT)) & IRIS_MVPL_MATRIX0_GREEN0_A22_MASK)

/*! @name MATRIX0_GREEN1 - Matrix values for calculation of the green output value. */
#define IRIS_MVPL_MATRIX0_GREEN1_A23_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX0_GREEN1_A23_SHIFT       (0U)
#define IRIS_MVPL_MATRIX0_GREEN1_A23(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_GREEN1_A23_SHIFT)) & IRIS_MVPL_MATRIX0_GREEN1_A23_MASK)
#define IRIS_MVPL_MATRIX0_GREEN1_A24_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX0_GREEN1_A24_SHIFT       (16U)
#define IRIS_MVPL_MATRIX0_GREEN1_A24(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_GREEN1_A24_SHIFT)) & IRIS_MVPL_MATRIX0_GREEN1_A24_MASK)

/*! @name MATRIX0_BLUE0 - Matrix values for calculation of the blue output value. */
#define IRIS_MVPL_MATRIX0_BLUE0_A31_MASK         (0x1FFFU)
#define IRIS_MVPL_MATRIX0_BLUE0_A31_SHIFT        (0U)
#define IRIS_MVPL_MATRIX0_BLUE0_A31(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_BLUE0_A31_SHIFT)) & IRIS_MVPL_MATRIX0_BLUE0_A31_MASK)
#define IRIS_MVPL_MATRIX0_BLUE0_A32_MASK         (0x1FFF0000U)
#define IRIS_MVPL_MATRIX0_BLUE0_A32_SHIFT        (16U)
#define IRIS_MVPL_MATRIX0_BLUE0_A32(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_BLUE0_A32_SHIFT)) & IRIS_MVPL_MATRIX0_BLUE0_A32_MASK)

/*! @name MATRIX0_BLUE1 - Matrix values for calculation of the blue output value. */
#define IRIS_MVPL_MATRIX0_BLUE1_A33_MASK         (0x1FFFU)
#define IRIS_MVPL_MATRIX0_BLUE1_A33_SHIFT        (0U)
#define IRIS_MVPL_MATRIX0_BLUE1_A33(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_BLUE1_A33_SHIFT)) & IRIS_MVPL_MATRIX0_BLUE1_A33_MASK)
#define IRIS_MVPL_MATRIX0_BLUE1_A34_MASK         (0x1FFF0000U)
#define IRIS_MVPL_MATRIX0_BLUE1_A34_SHIFT        (16U)
#define IRIS_MVPL_MATRIX0_BLUE1_A34(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_BLUE1_A34_SHIFT)) & IRIS_MVPL_MATRIX0_BLUE1_A34_MASK)

/*! @name MATRIX0_ALPHA0 - Matrix values for calculation of the alpha output value. */
#define IRIS_MVPL_MATRIX0_ALPHA0_A41_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX0_ALPHA0_A41_SHIFT       (0U)
#define IRIS_MVPL_MATRIX0_ALPHA0_A41(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_ALPHA0_A41_SHIFT)) & IRIS_MVPL_MATRIX0_ALPHA0_A41_MASK)
#define IRIS_MVPL_MATRIX0_ALPHA0_A42_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX0_ALPHA0_A42_SHIFT       (16U)
#define IRIS_MVPL_MATRIX0_ALPHA0_A42(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_ALPHA0_A42_SHIFT)) & IRIS_MVPL_MATRIX0_ALPHA0_A42_MASK)

/*! @name MATRIX0_ALPHA1 - Matrix values for calculation of the alpha output value. */
#define IRIS_MVPL_MATRIX0_ALPHA1_A43_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX0_ALPHA1_A43_SHIFT       (0U)
#define IRIS_MVPL_MATRIX0_ALPHA1_A43(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_ALPHA1_A43_SHIFT)) & IRIS_MVPL_MATRIX0_ALPHA1_A43_MASK)
#define IRIS_MVPL_MATRIX0_ALPHA1_A44_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX0_ALPHA1_A44_SHIFT       (16U)
#define IRIS_MVPL_MATRIX0_ALPHA1_A44(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_ALPHA1_A44_SHIFT)) & IRIS_MVPL_MATRIX0_ALPHA1_A44_MASK)

/*! @name MATRIX0_OFFSETVECTOR0 - Offset vectors for red and green output. */
#define IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C1_MASK  (0x1FFFU)
#define IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C1_SHIFT (0U)
#define IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C1(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C1_SHIFT)) & IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C1_MASK)
#define IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C2_MASK  (0x1FFF0000U)
#define IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C2_SHIFT (16U)
#define IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C2(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C2_SHIFT)) & IRIS_MVPL_MATRIX0_OFFSETVECTOR0_C2_MASK)

/*! @name MATRIX0_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */
#define IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C3_MASK  (0x1FFFU)
#define IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C3_SHIFT (0U)
#define IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C3(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C3_SHIFT)) & IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C3_MASK)
#define IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C4_MASK  (0x1FFF0000U)
#define IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C4_SHIFT (16U)
#define IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C4(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C4_SHIFT)) & IRIS_MVPL_MATRIX0_OFFSETVECTOR1_C4_MASK)

/*! @name MATRIX0_LASTCONTROLWORD - Value of last received control word, for debugging. */
#define IRIS_MVPL_MATRIX0_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_MATRIX0_LASTCONTROLWORD_L_VAL_SHIFT (0U)
#define IRIS_MVPL_MATRIX0_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX0_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_MATRIX0_LASTCONTROLWORD_L_VAL_MASK)

/*! @name GAMMACOR0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_GAMMACOR0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_GAMMACOR0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_GAMMACOR0_LOCKUNLOCK_LockUnlock_MASK)

/*! @name GAMMACOR0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_GAMMACOR0_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_GAMMACOR0_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_GAMMACOR0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_GAMMACOR0_LOCKSTATUS_FreezeStatus_MASK)

/*! @name GAMMACOR0_STATICCONTROL - Static control settings. */
#define IRIS_MVPL_GAMMACOR0_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_GAMMACOR0_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_GAMMACOR0_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_GAMMACOR0_STATICCONTROL_BlueWriteEnable_MASK (0x2U)
#define IRIS_MVPL_GAMMACOR0_STATICCONTROL_BlueWriteEnable_SHIFT (1U)
#define IRIS_MVPL_GAMMACOR0_STATICCONTROL_BlueWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_STATICCONTROL_BlueWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR0_STATICCONTROL_BlueWriteEnable_MASK)
#define IRIS_MVPL_GAMMACOR0_STATICCONTROL_GreenWriteEnable_MASK (0x4U)
#define IRIS_MVPL_GAMMACOR0_STATICCONTROL_GreenWriteEnable_SHIFT (2U)
#define IRIS_MVPL_GAMMACOR0_STATICCONTROL_GreenWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_STATICCONTROL_GreenWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR0_STATICCONTROL_GreenWriteEnable_MASK)
#define IRIS_MVPL_GAMMACOR0_STATICCONTROL_RedWriteEnable_MASK (0x8U)
#define IRIS_MVPL_GAMMACOR0_STATICCONTROL_RedWriteEnable_SHIFT (3U)
#define IRIS_MVPL_GAMMACOR0_STATICCONTROL_RedWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_STATICCONTROL_RedWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR0_STATICCONTROL_RedWriteEnable_MASK)

/*! @name GAMMACOR0_LUTSTART - Start values for look-up table programming. */
#define IRIS_MVPL_GAMMACOR0_LUTSTART_StartBlue_MASK (0x3FFU)
#define IRIS_MVPL_GAMMACOR0_LUTSTART_StartBlue_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR0_LUTSTART_StartBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LUTSTART_StartBlue_SHIFT)) & IRIS_MVPL_GAMMACOR0_LUTSTART_StartBlue_MASK)
#define IRIS_MVPL_GAMMACOR0_LUTSTART_StartGreen_MASK (0xFFC00U)
#define IRIS_MVPL_GAMMACOR0_LUTSTART_StartGreen_SHIFT (10U)
#define IRIS_MVPL_GAMMACOR0_LUTSTART_StartGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LUTSTART_StartGreen_SHIFT)) & IRIS_MVPL_GAMMACOR0_LUTSTART_StartGreen_MASK)
#define IRIS_MVPL_GAMMACOR0_LUTSTART_StartRed_MASK (0x3FF00000U)
#define IRIS_MVPL_GAMMACOR0_LUTSTART_StartRed_SHIFT (20U)
#define IRIS_MVPL_GAMMACOR0_LUTSTART_StartRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LUTSTART_StartRed_SHIFT)) & IRIS_MVPL_GAMMACOR0_LUTSTART_StartRed_MASK)

/*! @name GAMMACOR0_LUTDELTAS - Delta values for look-up table programming. */
#define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaBlue_MASK (0x3FFU)
#define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaBlue_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaBlue_SHIFT)) & IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaBlue_MASK)
#define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaGreen_MASK (0xFFC00U)
#define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaGreen_SHIFT (10U)
#define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaGreen_SHIFT)) & IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaGreen_MASK)
#define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaRed_MASK (0x3FF00000U)
#define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaRed_SHIFT (20U)
#define IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaRed_SHIFT)) & IRIS_MVPL_GAMMACOR0_LUTDELTAS_DeltaRed_MASK)

/*! @name GAMMACOR0_CONTROL - Dynamic control settings. */
#define IRIS_MVPL_GAMMACOR0_CONTROL_Mode_MASK    (0x1U)
#define IRIS_MVPL_GAMMACOR0_CONTROL_Mode_SHIFT   (0U)
#define IRIS_MVPL_GAMMACOR0_CONTROL_Mode(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_CONTROL_Mode_SHIFT)) & IRIS_MVPL_GAMMACOR0_CONTROL_Mode_MASK)
#define IRIS_MVPL_GAMMACOR0_CONTROL_AlphaMask_MASK (0x10U)
#define IRIS_MVPL_GAMMACOR0_CONTROL_AlphaMask_SHIFT (4U)
#define IRIS_MVPL_GAMMACOR0_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_GAMMACOR0_CONTROL_AlphaMask_MASK)
#define IRIS_MVPL_GAMMACOR0_CONTROL_AlphaInvert_MASK (0x20U)
#define IRIS_MVPL_GAMMACOR0_CONTROL_AlphaInvert_SHIFT (5U)
#define IRIS_MVPL_GAMMACOR0_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_GAMMACOR0_CONTROL_AlphaInvert_MASK)

/*! @name GAMMACOR0_STATUS - Internal status bits. */
#define IRIS_MVPL_GAMMACOR0_STATUS_WriteTimeout_MASK (0x1U)
#define IRIS_MVPL_GAMMACOR0_STATUS_WriteTimeout_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR0_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_GAMMACOR0_STATUS_WriteTimeout_MASK)

/*! @name GAMMACOR0_LASTCONTROLWORD - Value of last received control word. */
#define IRIS_MVPL_GAMMACOR0_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_GAMMACOR0_LASTCONTROLWORD_L_VAL_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR0_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR0_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_GAMMACOR0_LASTCONTROLWORD_L_VAL_MASK)

/*! @name DITHER0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_DITHER0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DITHER0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_DITHER0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_DITHER0_LOCKUNLOCK_LockUnlock_MASK)

/*! @name DITHER0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_DITHER0_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_DITHER0_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_DITHER0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_DITHER0_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_DITHER0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_DITHER0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_DITHER0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_DITHER0_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_DITHER0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_DITHER0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_DITHER0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_DITHER0_LOCKSTATUS_FreezeStatus_MASK)

/*! @name DITHER0_CONTROL - Dither Unit common control. */
#define IRIS_MVPL_DITHER0_CONTROL_mode_MASK      (0x1U)
#define IRIS_MVPL_DITHER0_CONTROL_mode_SHIFT     (0U)
#define IRIS_MVPL_DITHER0_CONTROL_mode(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_CONTROL_mode_SHIFT)) & IRIS_MVPL_DITHER0_CONTROL_mode_MASK)

/*! @name DITHER0_DITHERCONTROL - Dither Unit processing control. */
#define IRIS_MVPL_DITHER0_DITHERCONTROL_blue_range_select_MASK (0x7U)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_blue_range_select_SHIFT (0U)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_blue_range_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_DITHERCONTROL_blue_range_select_SHIFT)) & IRIS_MVPL_DITHER0_DITHERCONTROL_blue_range_select_MASK)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_green_range_select_MASK (0x70U)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_green_range_select_SHIFT (4U)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_green_range_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_DITHERCONTROL_green_range_select_SHIFT)) & IRIS_MVPL_DITHER0_DITHERCONTROL_green_range_select_MASK)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_red_range_select_MASK (0x700U)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_red_range_select_SHIFT (8U)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_red_range_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_DITHERCONTROL_red_range_select_SHIFT)) & IRIS_MVPL_DITHER0_DITHERCONTROL_red_range_select_MASK)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_offset_select_MASK (0x10000U)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_offset_select_SHIFT (16U)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_offset_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_DITHERCONTROL_offset_select_SHIFT)) & IRIS_MVPL_DITHER0_DITHERCONTROL_offset_select_MASK)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_algo_select_MASK (0x300000U)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_algo_select_SHIFT (20U)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_algo_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_DITHERCONTROL_algo_select_SHIFT)) & IRIS_MVPL_DITHER0_DITHERCONTROL_algo_select_MASK)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_alpha_mode_MASK (0x3000000U)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_alpha_mode_SHIFT (24U)
#define IRIS_MVPL_DITHER0_DITHERCONTROL_alpha_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_DITHERCONTROL_alpha_mode_SHIFT)) & IRIS_MVPL_DITHER0_DITHERCONTROL_alpha_mode_MASK)

/*! @name DITHER0_RELEASE - Dither Unit release. */
#define IRIS_MVPL_DITHER0_RELEASE_subversion_MASK (0xFFU)
#define IRIS_MVPL_DITHER0_RELEASE_subversion_SHIFT (0U)
#define IRIS_MVPL_DITHER0_RELEASE_subversion(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_RELEASE_subversion_SHIFT)) & IRIS_MVPL_DITHER0_RELEASE_subversion_MASK)
#define IRIS_MVPL_DITHER0_RELEASE_version_MASK   (0xFF00U)
#define IRIS_MVPL_DITHER0_RELEASE_version_SHIFT  (8U)
#define IRIS_MVPL_DITHER0_RELEASE_version(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER0_RELEASE_version_SHIFT)) & IRIS_MVPL_DITHER0_RELEASE_version_MASK)

/*! @name TCON0_SSQCNTS - The 64 Sequencer Position Definitions registers define the X/Y scan positions of the sequencers, hold their output value and assign the sequencer to an odd/even field */
#define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQY_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQY_SHIFT (0U)
#define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQY(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQY_SHIFT)) & IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQY_MASK)
#define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_FIELD_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_FIELD_SHIFT (15U)
#define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_FIELD_SHIFT)) & IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_FIELD_MASK)
#define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQX_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQX_SHIFT (16U)
#define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQX(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQX_SHIFT)) & IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_SEQX_MASK)
#define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_OUT_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_OUT_SHIFT (31U)
#define IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_OUT(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_OUT_SHIFT)) & IRIS_MVPL_TCON0_SSQCNTS_SSQCNTS_OUT_MASK)

/*! @name TCON0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_TCON0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_TCON0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_TCON0_LOCKUNLOCK_LockUnlock_MASK)

/*! @name TCON0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_TCON0_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_TCON0_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_TCON0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_TCON0_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_TCON0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_TCON0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_TCON0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_TCON0_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_TCON0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_TCON0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_TCON0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_TCON0_LOCKSTATUS_FreezeStatus_MASK)

/*! @name TCON0_SSQCYCLE - This bitfield sets the sequencer cycle length. The value set here -1 is the number of sequencer cycles */
#define IRIS_MVPL_TCON0_SSQCYCLE_SSQCYCLE_MASK   (0x3FU)
#define IRIS_MVPL_TCON0_SSQCYCLE_SSQCYCLE_SHIFT  (0U)
#define IRIS_MVPL_TCON0_SSQCYCLE_SSQCYCLE(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SSQCYCLE_SSQCYCLE_SHIFT)) & IRIS_MVPL_TCON0_SSQCYCLE_SSQCYCLE_MASK)

/*! @name TCON0_SWRESET - TCON Software Reset - Reset all tcon registers except configuration registers. Detailed description in specification document */
#define IRIS_MVPL_TCON0_SWRESET_SWReset_MASK     (0x1U)
#define IRIS_MVPL_TCON0_SWRESET_SWReset_SHIFT    (0U)
#define IRIS_MVPL_TCON0_SWRESET_SWReset(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SWRESET_SWReset_SHIFT)) & IRIS_MVPL_TCON0_SWRESET_SWReset_MASK)
#define IRIS_MVPL_TCON0_SWRESET_EnResetWord_MASK (0xFFF0U)
#define IRIS_MVPL_TCON0_SWRESET_EnResetWord_SHIFT (4U)
#define IRIS_MVPL_TCON0_SWRESET_EnResetWord(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SWRESET_EnResetWord_SHIFT)) & IRIS_MVPL_TCON0_SWRESET_EnResetWord_MASK)
#define IRIS_MVPL_TCON0_SWRESET_ResetWordEnd_MASK (0xFF0000U)
#define IRIS_MVPL_TCON0_SWRESET_ResetWordEnd_SHIFT (16U)
#define IRIS_MVPL_TCON0_SWRESET_ResetWordEnd(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SWRESET_ResetWordEnd_SHIFT)) & IRIS_MVPL_TCON0_SWRESET_ResetWordEnd_MASK)
#define IRIS_MVPL_TCON0_SWRESET_ResetWordStart_MASK (0xFF000000U)
#define IRIS_MVPL_TCON0_SWRESET_ResetWordStart_SHIFT (24U)
#define IRIS_MVPL_TCON0_SWRESET_ResetWordStart(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SWRESET_ResetWordStart_SHIFT)) & IRIS_MVPL_TCON0_SWRESET_ResetWordStart_MASK)

/*! @name TCON0_TCON_CTRL - TCON Control register */
#define IRIS_MVPL_TCON0_TCON_CTRL_ChannelMode_MASK (0x3U)
#define IRIS_MVPL_TCON0_TCON_CTRL_ChannelMode_SHIFT (0U)
#define IRIS_MVPL_TCON0_TCON_CTRL_ChannelMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_TCON_CTRL_ChannelMode_SHIFT)) & IRIS_MVPL_TCON0_TCON_CTRL_ChannelMode_MASK)
#define IRIS_MVPL_TCON0_TCON_CTRL_tcon_sync_MASK (0x4U)
#define IRIS_MVPL_TCON0_TCON_CTRL_tcon_sync_SHIFT (2U)
#define IRIS_MVPL_TCON0_TCON_CTRL_tcon_sync(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_TCON_CTRL_tcon_sync_SHIFT)) & IRIS_MVPL_TCON0_TCON_CTRL_tcon_sync_MASK)
#define IRIS_MVPL_TCON0_TCON_CTRL_Bypass_MASK    (0x8U)
#define IRIS_MVPL_TCON0_TCON_CTRL_Bypass_SHIFT   (3U)
#define IRIS_MVPL_TCON0_TCON_CTRL_Bypass(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_TCON_CTRL_Bypass_SHIFT)) & IRIS_MVPL_TCON0_TCON_CTRL_Bypass_MASK)
#define IRIS_MVPL_TCON0_TCON_CTRL_Inv_Ctrl_MASK  (0xF0U)
#define IRIS_MVPL_TCON0_TCON_CTRL_Inv_Ctrl_SHIFT (4U)
#define IRIS_MVPL_TCON0_TCON_CTRL_Inv_Ctrl(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_TCON_CTRL_Inv_Ctrl_SHIFT)) & IRIS_MVPL_TCON0_TCON_CTRL_Inv_Ctrl_MASK)
#define IRIS_MVPL_TCON0_TCON_CTRL_EnLVDS_MASK    (0x100U)
#define IRIS_MVPL_TCON0_TCON_CTRL_EnLVDS_SHIFT   (8U)
#define IRIS_MVPL_TCON0_TCON_CTRL_EnLVDS(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_TCON_CTRL_EnLVDS_SHIFT)) & IRIS_MVPL_TCON0_TCON_CTRL_EnLVDS_MASK)
#define IRIS_MVPL_TCON0_TCON_CTRL_LVDSMode_MASK  (0x200U)
#define IRIS_MVPL_TCON0_TCON_CTRL_LVDSMode_SHIFT (9U)
#define IRIS_MVPL_TCON0_TCON_CTRL_LVDSMode(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_TCON_CTRL_LVDSMode_SHIFT)) & IRIS_MVPL_TCON0_TCON_CTRL_LVDSMode_MASK)
#define IRIS_MVPL_TCON0_TCON_CTRL_LVDS_Balance_MASK (0x400U)
#define IRIS_MVPL_TCON0_TCON_CTRL_LVDS_Balance_SHIFT (10U)
#define IRIS_MVPL_TCON0_TCON_CTRL_LVDS_Balance(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_TCON_CTRL_LVDS_Balance_SHIFT)) & IRIS_MVPL_TCON0_TCON_CTRL_LVDS_Balance_MASK)
#define IRIS_MVPL_TCON0_TCON_CTRL_LVDS_CLOCK_INV_MASK (0x800U)
#define IRIS_MVPL_TCON0_TCON_CTRL_LVDS_CLOCK_INV_SHIFT (11U)
#define IRIS_MVPL_TCON0_TCON_CTRL_LVDS_CLOCK_INV(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_TCON_CTRL_LVDS_CLOCK_INV_SHIFT)) & IRIS_MVPL_TCON0_TCON_CTRL_LVDS_CLOCK_INV_MASK)
#define IRIS_MVPL_TCON0_TCON_CTRL_MiniLVDS_OpCode_MASK (0x7000U)
#define IRIS_MVPL_TCON0_TCON_CTRL_MiniLVDS_OpCode_SHIFT (12U)
#define IRIS_MVPL_TCON0_TCON_CTRL_MiniLVDS_OpCode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_TCON_CTRL_MiniLVDS_OpCode_SHIFT)) & IRIS_MVPL_TCON0_TCON_CTRL_MiniLVDS_OpCode_MASK)
#define IRIS_MVPL_TCON0_TCON_CTRL_DUAL_SWAP_MASK (0x8000U)
#define IRIS_MVPL_TCON0_TCON_CTRL_DUAL_SWAP_SHIFT (15U)
#define IRIS_MVPL_TCON0_TCON_CTRL_DUAL_SWAP(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_TCON_CTRL_DUAL_SWAP_SHIFT)) & IRIS_MVPL_TCON0_TCON_CTRL_DUAL_SWAP_MASK)
#define IRIS_MVPL_TCON0_TCON_CTRL_SplitPosition_MASK (0x3FFF0000U)
#define IRIS_MVPL_TCON0_TCON_CTRL_SplitPosition_SHIFT (16U)
#define IRIS_MVPL_TCON0_TCON_CTRL_SplitPosition(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_TCON_CTRL_SplitPosition_SHIFT)) & IRIS_MVPL_TCON0_TCON_CTRL_SplitPosition_MASK)

/*! @name TCON0_RSDSINVCTRL - Controls inversion of output polarity when connected IO cells operate in RSDS mode */
#define IRIS_MVPL_TCON0_RSDSINVCTRL_RSDS_Inv_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_RSDSINVCTRL_RSDS_Inv_SHIFT (0U)
#define IRIS_MVPL_TCON0_RSDSINVCTRL_RSDS_Inv(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_RSDSINVCTRL_RSDS_Inv_SHIFT)) & IRIS_MVPL_TCON0_RSDSINVCTRL_RSDS_Inv_MASK)
#define IRIS_MVPL_TCON0_RSDSINVCTRL_RSDS_Inv_Dual_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_RSDSINVCTRL_RSDS_Inv_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON0_RSDSINVCTRL_RSDS_Inv_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_RSDSINVCTRL_RSDS_Inv_Dual_SHIFT)) & IRIS_MVPL_TCON0_RSDSINVCTRL_RSDS_Inv_Dual_MASK)

/*! @name TCON0_MAPBIT3_0 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3 */
#define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit0_MASK   (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit0_SHIFT  (0U)
#define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit0(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_MapBit0_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_MapBit0_MASK)
#define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit1_MASK   (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit1_SHIFT  (8U)
#define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit1(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_MapBit1_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_MapBit1_MASK)
#define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit2_MASK   (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit2_SHIFT  (16U)
#define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit2(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_MapBit2_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_MapBit2_MASK)
#define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit3_MASK   (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit3_SHIFT  (24U)
#define IRIS_MVPL_TCON0_MAPBIT3_0_MapBit3(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_MapBit3_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_MapBit3_MASK)

/*! @name TCON0_MAPBIT7_4 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7 */
#define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit4_MASK   (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit4_SHIFT  (0U)
#define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit4(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_MapBit4_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_MapBit4_MASK)
#define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit5_MASK   (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit5_SHIFT  (8U)
#define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit5(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_MapBit5_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_MapBit5_MASK)
#define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit6_MASK   (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit6_SHIFT  (16U)
#define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit6(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_MapBit6_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_MapBit6_MASK)
#define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit7_MASK   (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit7_SHIFT  (24U)
#define IRIS_MVPL_TCON0_MAPBIT7_4_MapBit7(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_MapBit7_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_MapBit7_MASK)

/*! @name TCON0_MAPBIT11_8 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11 */
#define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit8_MASK  (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit8_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit8(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_MapBit8_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_MapBit8_MASK)
#define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit9_MASK  (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit9_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit9(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_MapBit9_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_MapBit9_MASK)
#define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit10_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit10_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit10(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_MapBit10_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_MapBit10_MASK)
#define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit11_MASK (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit11_SHIFT (24U)
#define IRIS_MVPL_TCON0_MAPBIT11_8_MapBit11(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_MapBit11_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_MapBit11_MASK)

/*! @name TCON0_MAPBIT15_12 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15 */
#define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit12_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit12_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit12(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_MapBit12_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_MapBit12_MASK)
#define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit13_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit13_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit13(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_MapBit13_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_MapBit13_MASK)
#define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit14_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit14_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit14(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_MapBit14_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_MapBit14_MASK)
#define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit15_MASK (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit15_SHIFT (24U)
#define IRIS_MVPL_TCON0_MAPBIT15_12_MapBit15(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_MapBit15_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_MapBit15_MASK)

/*! @name TCON0_MAPBIT19_16 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19 */
#define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit16_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit16_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit16(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_MapBit16_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_MapBit16_MASK)
#define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit17_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit17_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit17(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_MapBit17_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_MapBit17_MASK)
#define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit18_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit18_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit18(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_MapBit18_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_MapBit18_MASK)
#define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit19_MASK (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit19_SHIFT (24U)
#define IRIS_MVPL_TCON0_MAPBIT19_16_MapBit19(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_MapBit19_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_MapBit19_MASK)

/*! @name TCON0_MAPBIT23_20 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23 */
#define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit20_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit20_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit20(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_MapBit20_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_MapBit20_MASK)
#define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit21_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit21_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit21(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_MapBit21_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_MapBit21_MASK)
#define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit22_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit22_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit22(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_MapBit22_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_MapBit22_MASK)
#define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit23_MASK (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit23_SHIFT (24U)
#define IRIS_MVPL_TCON0_MAPBIT23_20_MapBit23(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_MapBit23_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_MapBit23_MASK)

/*! @name TCON0_MAPBIT27_24 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27 */
#define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit24_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit24_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit24(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_MapBit24_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_MapBit24_MASK)
#define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit25_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit25_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit25(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_MapBit25_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_MapBit25_MASK)
#define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit26_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit26_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit26(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_MapBit26_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_MapBit26_MASK)
#define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit27_MASK (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit27_SHIFT (24U)
#define IRIS_MVPL_TCON0_MAPBIT27_24_MapBit27(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_MapBit27_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_MapBit27_MASK)

/*! @name TCON0_MAPBIT31_28 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31 */
#define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit28_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit28_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit28(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_MapBit28_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_MapBit28_MASK)
#define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit29_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit29_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit29(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_MapBit29_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_MapBit29_MASK)
#define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit30_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit30_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit30(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_MapBit30_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_MapBit30_MASK)
#define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit31_MASK (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit31_SHIFT (24U)
#define IRIS_MVPL_TCON0_MAPBIT31_28_MapBit31(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_MapBit31_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_MapBit31_MASK)

/*! @name TCON0_MAPBIT34_32 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34 */
#define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit32_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit32_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit32(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT34_32_MapBit32_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT34_32_MapBit32_MASK)
#define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit33_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit33_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit33(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT34_32_MapBit33_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT34_32_MapBit33_MASK)
#define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit34_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit34_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT34_32_MapBit34(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT34_32_MapBit34_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT34_32_MapBit34_MASK)

/*! @name TCON0_MAPBIT3_0_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3 2nd channel */
#define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit0_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit0_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit0_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit0_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit0_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit1_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit1_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit1_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit1_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit1_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit2_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit2_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit2_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit2_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit2_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit3_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit3_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit3_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit3_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT3_0_DUAL_MapBit3_Dual_MASK)

/*! @name TCON0_MAPBIT7_4_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7 2nd channel */
#define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit4_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit4_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit4_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit4_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit4_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit5_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit5_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit5_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit5_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit5_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit6_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit6_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit6_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit6_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit6_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit7_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit7_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit7_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit7_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT7_4_DUAL_MapBit7_Dual_MASK)

/*! @name TCON0_MAPBIT11_8_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11 2nd channel */
#define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit8_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit8_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit8_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit8_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit8_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit9_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit9_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit9_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit9_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit9_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit10_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit10_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit10_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit10_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit10_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit11_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit11_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit11_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit11_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT11_8_DUAL_MapBit11_Dual_MASK)

/*! @name TCON0_MAPBIT15_12_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15 2nd channel */
#define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit12_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit12_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit12_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit12_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit12_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit13_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit13_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit13_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit13_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit13_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit14_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit14_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit14_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit14_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit14_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit15_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit15_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit15_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit15_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT15_12_DUAL_MapBit15_Dual_MASK)

/*! @name TCON0_MAPBIT19_16_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19 2nd channel */
#define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit16_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit16_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit16_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit16_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit16_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit17_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit17_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit17_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit17_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit17_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit18_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit18_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit18_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit18_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit18_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit19_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit19_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit19_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit19_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT19_16_DUAL_MapBit19_Dual_MASK)

/*! @name TCON0_MAPBIT23_20_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23 2nd channel */
#define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit20_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit20_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit20_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit20_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit20_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit21_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit21_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit21_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit21_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit21_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit22_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit22_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit22_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit22_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit22_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit23_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit23_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit23_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit23_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT23_20_DUAL_MapBit23_Dual_MASK)

/*! @name TCON0_MAPBIT27_24_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27 2nd channel */
#define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit24_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit24_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit24_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit24_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit24_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit25_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit25_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit25_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit25_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit25_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit26_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit26_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit26_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit26_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit26_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit27_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit27_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit27_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit27_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT27_24_DUAL_MapBit27_Dual_MASK)

/*! @name TCON0_MAPBIT31_28_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31 2nd channel */
#define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit28_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit28_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit28_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit28_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit28_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit29_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit29_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit29_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit29_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit29_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit30_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit30_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit30_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit30_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit30_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit31_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit31_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit31_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit31_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT31_28_DUAL_MapBit31_Dual_MASK)

/*! @name TCON0_MAPBIT34_32_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34 2nd channel */
#define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit32_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit32_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit32_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit32_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit32_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit33_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit33_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit33_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit33_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit33_Dual_MASK)
#define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit34_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit34_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit34_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit34_Dual_SHIFT)) & IRIS_MVPL_TCON0_MAPBIT34_32_DUAL_MapBit34_Dual_MASK)

/*! @name TCON0_SPG0POSON - Sync pulse generator 0, 'Switch on' position */
#define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_Y0_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_Y0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_Y0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_Y0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_Y0_MASK)
#define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_FIELD0_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_FIELD0_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_FIELD0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_FIELD0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_FIELD0_MASK)
#define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_X0_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_X0_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_X0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_X0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_X0_MASK)
#define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_TOGGLE0_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_TOGGLE0_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_TOGGLE0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_TOGGLE0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSON_SPGPSON_TOGGLE0_MASK)

/*! @name TCON0_SPG0MASKON - The Sequencer Pulse Generator 0 Mask Enable register is used to mask the enable of SPG 0 */
#define IRIS_MVPL_TCON0_SPG0MASKON_SPGMKON0_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG0MASKON_SPGMKON0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG0MASKON_SPGMKON0(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0MASKON_SPGMKON0_SHIFT)) & IRIS_MVPL_TCON0_SPG0MASKON_SPGMKON0_MASK)

/*! @name TCON0_SPG0POSOFF - Sync pulse generator 0, 'Switch off' position */
#define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_Y0_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_Y0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_Y0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_Y0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_Y0_MASK)
#define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_MASK)
#define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_X0_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_X0_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_X0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_X0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_X0_MASK)
#define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT)) & IRIS_MVPL_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK)

/*! @name TCON0_SPG0MASKOFF - The Sequencer Pulse Generator 0 Mask Enable register is used to mask the disable of SPG 0 */
#define IRIS_MVPL_TCON0_SPG0MASKOFF_SPGMKOFF0_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG0MASKOFF_SPGMKOFF0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG0MASKOFF_SPGMKOFF0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG0MASKOFF_SPGMKOFF0_SHIFT)) & IRIS_MVPL_TCON0_SPG0MASKOFF_SPGMKOFF0_MASK)

/*! @name TCON0_SPG1POSON - Sync pulse generator 1, 'Switch on' position */
#define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_Y1_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_Y1_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_Y1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_Y1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_Y1_MASK)
#define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_FIELD1_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_FIELD1_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_FIELD1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_FIELD1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_FIELD1_MASK)
#define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_X1_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_X1_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_X1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_X1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_X1_MASK)
#define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_TOGGLE1_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_TOGGLE1_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_TOGGLE1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_TOGGLE1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSON_SPGPSON_TOGGLE1_MASK)

/*! @name TCON0_SPG1MASKON - The Sequencer Pulse Generator 1 Mask Enable register is used to mask the enable of SPG 1 */
#define IRIS_MVPL_TCON0_SPG1MASKON_SPGMKON1_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG1MASKON_SPGMKON1_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG1MASKON_SPGMKON1(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1MASKON_SPGMKON1_SHIFT)) & IRIS_MVPL_TCON0_SPG1MASKON_SPGMKON1_MASK)

/*! @name TCON0_SPG1POSOFF - Sync pulse generator 1, 'Switch off' position */
#define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_Y1_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_Y1_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_Y1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_Y1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_Y1_MASK)
#define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_MASK)
#define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_X1_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_X1_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_X1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_X1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_X1_MASK)
#define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT)) & IRIS_MVPL_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK)

/*! @name TCON0_SPG1MASKOFF - The Sequencer Pulse Generator 1 Mask Enable register is used to mask the disable of SPG 1 */
#define IRIS_MVPL_TCON0_SPG1MASKOFF_SPGMKOFF1_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG1MASKOFF_SPGMKOFF1_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG1MASKOFF_SPGMKOFF1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG1MASKOFF_SPGMKOFF1_SHIFT)) & IRIS_MVPL_TCON0_SPG1MASKOFF_SPGMKOFF1_MASK)

/*! @name TCON0_SPG2POSON - Sync pulse generator 2, 'Switch on' position */
#define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_Y2_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_Y2_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_Y2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_Y2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_Y2_MASK)
#define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_FIELD2_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_FIELD2_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_FIELD2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_FIELD2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_FIELD2_MASK)
#define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_X2_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_X2_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_X2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_X2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_X2_MASK)
#define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_TOGGLE2_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_TOGGLE2_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_TOGGLE2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_TOGGLE2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSON_SPGPSON_TOGGLE2_MASK)

/*! @name TCON0_SPG2MASKON - The Sequencer Pulse Generator 2 Mask Enable register is used to mask the enable of SPG 2 */
#define IRIS_MVPL_TCON0_SPG2MASKON_SPGMKON2_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG2MASKON_SPGMKON2_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG2MASKON_SPGMKON2(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2MASKON_SPGMKON2_SHIFT)) & IRIS_MVPL_TCON0_SPG2MASKON_SPGMKON2_MASK)

/*! @name TCON0_SPG2POSOFF - Sync pulse generator 2, 'Switch off' position */
#define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_Y2_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_Y2_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_Y2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_Y2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_Y2_MASK)
#define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_MASK)
#define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_X2_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_X2_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_X2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_X2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_X2_MASK)
#define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT)) & IRIS_MVPL_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK)

/*! @name TCON0_SPG2MASKOFF - The Sequencer Pulse Generator 2 Mask Enable register is used to mask the disable of SPG 2 */
#define IRIS_MVPL_TCON0_SPG2MASKOFF_SPGMKOFF2_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG2MASKOFF_SPGMKOFF2_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG2MASKOFF_SPGMKOFF2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG2MASKOFF_SPGMKOFF2_SHIFT)) & IRIS_MVPL_TCON0_SPG2MASKOFF_SPGMKOFF2_MASK)

/*! @name TCON0_SPG3POSON - Sync pulse generator 3, 'Switch on' position */
#define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_Y3_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_Y3_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_Y3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_Y3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_Y3_MASK)
#define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_FIELD3_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_FIELD3_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_FIELD3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_FIELD3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_FIELD3_MASK)
#define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_X3_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_X3_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_X3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_X3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_X3_MASK)
#define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_TOGGLE3_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_TOGGLE3_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_TOGGLE3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_TOGGLE3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSON_SPGPSON_TOGGLE3_MASK)

/*! @name TCON0_SPG3MASKON - The Sequencer Pulse Generator 3 Mask Enable register is used to mask the enable of SPG 3 */
#define IRIS_MVPL_TCON0_SPG3MASKON_SPGMKON3_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG3MASKON_SPGMKON3_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG3MASKON_SPGMKON3(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3MASKON_SPGMKON3_SHIFT)) & IRIS_MVPL_TCON0_SPG3MASKON_SPGMKON3_MASK)

/*! @name TCON0_SPG3POSOFF - Sync pulse generator 3, 'Switch off' position */
#define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_Y3_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_Y3_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_Y3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_Y3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_Y3_MASK)
#define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_MASK)
#define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_X3_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_X3_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_X3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_X3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_X3_MASK)
#define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT)) & IRIS_MVPL_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK)

/*! @name TCON0_SPG3MASKOFF - The Sequencer Pulse Generator 3 Mask Enable register is used to mask the disable of SPG 3 */
#define IRIS_MVPL_TCON0_SPG3MASKOFF_SPGMKOFF3_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG3MASKOFF_SPGMKOFF3_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG3MASKOFF_SPGMKOFF3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG3MASKOFF_SPGMKOFF3_SHIFT)) & IRIS_MVPL_TCON0_SPG3MASKOFF_SPGMKOFF3_MASK)

/*! @name TCON0_SPG4POSON - Sync pulse generator 4, 'Switch on' position */
#define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_Y4_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_Y4_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_Y4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_Y4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_Y4_MASK)
#define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_FIELD4_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_FIELD4_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_FIELD4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_FIELD4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_FIELD4_MASK)
#define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_X4_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_X4_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_X4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_X4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_X4_MASK)
#define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_TOGGLE4_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_TOGGLE4_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_TOGGLE4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_TOGGLE4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSON_SPGPSON_TOGGLE4_MASK)

/*! @name TCON0_SPG4MASKON - The Sequencer Pulse Generator 4 Mask Enable register is used to mask the enable of SPG 4 */
#define IRIS_MVPL_TCON0_SPG4MASKON_SPGMKON4_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG4MASKON_SPGMKON4_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG4MASKON_SPGMKON4(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4MASKON_SPGMKON4_SHIFT)) & IRIS_MVPL_TCON0_SPG4MASKON_SPGMKON4_MASK)

/*! @name TCON0_SPG4POSOFF - Sync pulse generator 4, 'Switch off' position */
#define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_Y4_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_Y4_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_Y4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_Y4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_Y4_MASK)
#define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_MASK)
#define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_X4_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_X4_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_X4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_X4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_X4_MASK)
#define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT)) & IRIS_MVPL_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK)

/*! @name TCON0_SPG4MASKOFF - The Sequencer Pulse Generator 4 Mask Enable register is used to mask the disable of SPG 4 */
#define IRIS_MVPL_TCON0_SPG4MASKOFF_SPGMKOFF4_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG4MASKOFF_SPGMKOFF4_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG4MASKOFF_SPGMKOFF4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG4MASKOFF_SPGMKOFF4_SHIFT)) & IRIS_MVPL_TCON0_SPG4MASKOFF_SPGMKOFF4_MASK)

/*! @name TCON0_SPG5POSON - Sync pulse generator 5, 'Switch on' position */
#define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_Y5_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_Y5_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_Y5(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_Y5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_Y5_MASK)
#define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_FIELD5_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_FIELD5_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_FIELD5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_FIELD5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_FIELD5_MASK)
#define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_X5_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_X5_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_X5(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_X5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_X5_MASK)
#define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_TOGGLE5_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_TOGGLE5_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_TOGGLE5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_TOGGLE5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSON_SPGPSON_TOGGLE5_MASK)

/*! @name TCON0_SPG5MASKON - The Sequencer Pulse Generator 5 Mask Enable register is used to mask the enable of SPG 5 */
#define IRIS_MVPL_TCON0_SPG5MASKON_SPGMKON5_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG5MASKON_SPGMKON5_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG5MASKON_SPGMKON5(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5MASKON_SPGMKON5_SHIFT)) & IRIS_MVPL_TCON0_SPG5MASKON_SPGMKON5_MASK)

/*! @name TCON0_SPG5POSOFF - Sync pulse generator 5, 'Switch off' position */
#define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_Y5_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_Y5_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_Y5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_Y5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_Y5_MASK)
#define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_MASK)
#define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_X5_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_X5_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_X5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_X5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_X5_MASK)
#define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT)) & IRIS_MVPL_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK)

/*! @name TCON0_SPG5MASKOFF - The Sequencer Pulse Generator 5 Mask Enable register is used to mask the disable of SPG 5 */
#define IRIS_MVPL_TCON0_SPG5MASKOFF_SPGMKOFF5_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG5MASKOFF_SPGMKOFF5_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG5MASKOFF_SPGMKOFF5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG5MASKOFF_SPGMKOFF5_SHIFT)) & IRIS_MVPL_TCON0_SPG5MASKOFF_SPGMKOFF5_MASK)

/*! @name TCON0_SPG6POSON - Sync pulse generator 6, 'Switch on' position */
#define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_Y6_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_Y6_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_Y6(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_Y6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_Y6_MASK)
#define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_FIELD6_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_FIELD6_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_FIELD6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_FIELD6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_FIELD6_MASK)
#define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_X6_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_X6_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_X6(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_X6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_X6_MASK)
#define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_TOGGLE6_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_TOGGLE6_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_TOGGLE6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_TOGGLE6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSON_SPGPSON_TOGGLE6_MASK)

/*! @name TCON0_SPG6MASKON - The Sequencer Pulse Generator 6 Mask Enable register is used to mask the enable of SPG 6 */
#define IRIS_MVPL_TCON0_SPG6MASKON_SPGMKON6_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG6MASKON_SPGMKON6_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG6MASKON_SPGMKON6(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6MASKON_SPGMKON6_SHIFT)) & IRIS_MVPL_TCON0_SPG6MASKON_SPGMKON6_MASK)

/*! @name TCON0_SPG6POSOFF - Sync pulse generator 6, 'Switch off' position */
#define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_Y6_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_Y6_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_Y6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_Y6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_Y6_MASK)
#define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_MASK)
#define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_X6_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_X6_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_X6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_X6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_X6_MASK)
#define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT)) & IRIS_MVPL_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK)

/*! @name TCON0_SPG6MASKOFF - The Sequencer Pulse Generator 6 Mask Enable register is used to mask the disable of SPG 6 */
#define IRIS_MVPL_TCON0_SPG6MASKOFF_SPGMKOFF6_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG6MASKOFF_SPGMKOFF6_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG6MASKOFF_SPGMKOFF6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG6MASKOFF_SPGMKOFF6_SHIFT)) & IRIS_MVPL_TCON0_SPG6MASKOFF_SPGMKOFF6_MASK)

/*! @name TCON0_SPG7POSON - Sync pulse generator 7, 'Switch on' position */
#define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_Y7_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_Y7_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_Y7(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_Y7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_Y7_MASK)
#define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_FIELD7_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_FIELD7_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_FIELD7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_FIELD7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_FIELD7_MASK)
#define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_X7_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_X7_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_X7(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_X7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_X7_MASK)
#define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_TOGGLE7_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_TOGGLE7_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_TOGGLE7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_TOGGLE7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSON_SPGPSON_TOGGLE7_MASK)

/*! @name TCON0_SPG7MASKON - The Sequencer Pulse Generator 7 Mask Enable register is used to mask the enable of SPG 7 */
#define IRIS_MVPL_TCON0_SPG7MASKON_SPGMKON7_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG7MASKON_SPGMKON7_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG7MASKON_SPGMKON7(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7MASKON_SPGMKON7_SHIFT)) & IRIS_MVPL_TCON0_SPG7MASKON_SPGMKON7_MASK)

/*! @name TCON0_SPG7POSOFF - Sync pulse generator 7, 'Switch off' position */
#define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_Y7_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_Y7_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_Y7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_Y7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_Y7_MASK)
#define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_MASK)
#define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_X7_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_X7_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_X7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_X7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_X7_MASK)
#define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT)) & IRIS_MVPL_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK)

/*! @name TCON0_SPG7MASKOFF - The Sequencer Pulse Generator 7 Mask Enable register is used to mask the disable of SPG 7 */
#define IRIS_MVPL_TCON0_SPG7MASKOFF_SPGMKOFF7_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG7MASKOFF_SPGMKOFF7_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG7MASKOFF_SPGMKOFF7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG7MASKOFF_SPGMKOFF7_SHIFT)) & IRIS_MVPL_TCON0_SPG7MASKOFF_SPGMKOFF7_MASK)

/*! @name TCON0_SPG8POSON - Sync pulse generator 8, 'Switch on' position */
#define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_Y8_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_Y8_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_Y8(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_Y8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_Y8_MASK)
#define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_FIELD8_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_FIELD8_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_FIELD8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_FIELD8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_FIELD8_MASK)
#define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_X8_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_X8_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_X8(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_X8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_X8_MASK)
#define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_TOGGLE8_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_TOGGLE8_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_TOGGLE8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_TOGGLE8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSON_SPGPSON_TOGGLE8_MASK)

/*! @name TCON0_SPG8MASKON - The Sequencer Pulse Generator 8 Mask Enable register is used to mask the enable of SPG 8 */
#define IRIS_MVPL_TCON0_SPG8MASKON_SPGMKON8_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG8MASKON_SPGMKON8_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG8MASKON_SPGMKON8(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8MASKON_SPGMKON8_SHIFT)) & IRIS_MVPL_TCON0_SPG8MASKON_SPGMKON8_MASK)

/*! @name TCON0_SPG8POSOFF - Sync pulse generator 8, 'Switch off' position */
#define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_Y8_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_Y8_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_Y8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_Y8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_Y8_MASK)
#define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_MASK)
#define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_X8_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_X8_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_X8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_X8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_X8_MASK)
#define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT)) & IRIS_MVPL_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK)

/*! @name TCON0_SPG8MASKOFF - The Sequencer Pulse Generator 8 Mask Enable register is used to mask the disable of SPG 8 */
#define IRIS_MVPL_TCON0_SPG8MASKOFF_SPGMKOFF8_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG8MASKOFF_SPGMKOFF8_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG8MASKOFF_SPGMKOFF8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG8MASKOFF_SPGMKOFF8_SHIFT)) & IRIS_MVPL_TCON0_SPG8MASKOFF_SPGMKOFF8_MASK)

/*! @name TCON0_SPG9POSON - Sync pulse generator 9, 'Switch on' position */
#define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_Y9_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_Y9_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_Y9(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_Y9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_Y9_MASK)
#define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_FIELD9_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_FIELD9_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_FIELD9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_FIELD9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_FIELD9_MASK)
#define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_X9_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_X9_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_X9(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_X9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_X9_MASK)
#define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_TOGGLE9_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_TOGGLE9_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_TOGGLE9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_TOGGLE9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSON_SPGPSON_TOGGLE9_MASK)

/*! @name TCON0_SPG9MASKON - The Sequencer Pulse Generator 9 Mask Enable register is used to mask the enable of SPG 9 */
#define IRIS_MVPL_TCON0_SPG9MASKON_SPGMKON9_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG9MASKON_SPGMKON9_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG9MASKON_SPGMKON9(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9MASKON_SPGMKON9_SHIFT)) & IRIS_MVPL_TCON0_SPG9MASKON_SPGMKON9_MASK)

/*! @name TCON0_SPG9POSOFF - Sync pulse generator 9, 'Switch off' position */
#define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_Y9_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_Y9_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_Y9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_Y9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_Y9_MASK)
#define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_MASK)
#define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_X9_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_X9_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_X9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_X9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_X9_MASK)
#define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT)) & IRIS_MVPL_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK)

/*! @name TCON0_SPG9MASKOFF - The Sequencer Pulse Generator 9 Mask Enable register is used to mask the disable of SPG 9 */
#define IRIS_MVPL_TCON0_SPG9MASKOFF_SPGMKOFF9_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG9MASKOFF_SPGMKOFF9_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG9MASKOFF_SPGMKOFF9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG9MASKOFF_SPGMKOFF9_SHIFT)) & IRIS_MVPL_TCON0_SPG9MASKOFF_SPGMKOFF9_MASK)

/*! @name TCON0_SPG10POSON - Sync pulse generator 10, 'Switch on' position */
#define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_Y10_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_Y10_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_Y10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_Y10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_Y10_MASK)
#define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_FIELD10_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_FIELD10_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_FIELD10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_FIELD10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_FIELD10_MASK)
#define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_X10_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_X10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_X10_MASK)
#define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_TOGGLE10_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_TOGGLE10_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_TOGGLE10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_TOGGLE10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSON_SPGPSON_TOGGLE10_MASK)

/*! @name TCON0_SPG10MASKON - The Sequencer Pulse Generator 10 Mask Enable register is used to mask the enable of SPG 10 */
#define IRIS_MVPL_TCON0_SPG10MASKON_SPGMKON10_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG10MASKON_SPGMKON10_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG10MASKON_SPGMKON10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10MASKON_SPGMKON10_SHIFT)) & IRIS_MVPL_TCON0_SPG10MASKON_SPGMKON10_MASK)

/*! @name TCON0_SPG10POSOFF - Sync pulse generator 10, 'Switch off' position */
#define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_Y10_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_Y10_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_Y10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_Y10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_Y10_MASK)
#define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_MASK)
#define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_X10_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_X10_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_X10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_X10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_X10_MASK)
#define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT)) & IRIS_MVPL_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK)

/*! @name TCON0_SPG10MASKOFF - The Sequencer Pulse Generator 10 Mask Enable register is used to mask the disable of SPG 10 */
#define IRIS_MVPL_TCON0_SPG10MASKOFF_SPGMKOFF10_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG10MASKOFF_SPGMKOFF10_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG10MASKOFF_SPGMKOFF10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG10MASKOFF_SPGMKOFF10_SHIFT)) & IRIS_MVPL_TCON0_SPG10MASKOFF_SPGMKOFF10_MASK)

/*! @name TCON0_SPG11POSON - Sync pulse generator 11, 'Switch on' position */
#define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_Y11_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_Y11_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_Y11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_Y11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_Y11_MASK)
#define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_FIELD11_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_FIELD11_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_FIELD11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_FIELD11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_FIELD11_MASK)
#define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_X11_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_X11_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_X11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_X11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_X11_MASK)
#define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_TOGGLE11_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_TOGGLE11_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_TOGGLE11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_TOGGLE11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSON_SPGPSON_TOGGLE11_MASK)

/*! @name TCON0_SPG11MASKON - The Sequencer Pulse Generator 11 Mask Enable register is used to mask the enable of SPG 11 */
#define IRIS_MVPL_TCON0_SPG11MASKON_SPGMKON11_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG11MASKON_SPGMKON11_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG11MASKON_SPGMKON11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11MASKON_SPGMKON11_SHIFT)) & IRIS_MVPL_TCON0_SPG11MASKON_SPGMKON11_MASK)

/*! @name TCON0_SPG11POSOFF - Sync pulse generator 11, 'Switch off' position */
#define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_Y11_MASK (0x7FFFU)
#define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_Y11_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_Y11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_Y11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_Y11_MASK)
#define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_MASK (0x8000U)
#define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT (15U)
#define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_MASK)
#define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_X11_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_X11_SHIFT (16U)
#define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_X11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_X11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_X11_MASK)
#define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK (0x80000000U)
#define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT (31U)
#define IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT)) & IRIS_MVPL_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK)

/*! @name TCON0_SPG11MASKOFF - The Sequencer Pulse Generator 11 Mask Enable register is used to mask the disable of SPG 11 */
#define IRIS_MVPL_TCON0_SPG11MASKOFF_SPGMKOFF11_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON0_SPG11MASKOFF_SPGMKOFF11_SHIFT (0U)
#define IRIS_MVPL_TCON0_SPG11MASKOFF_SPGMKOFF11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SPG11MASKOFF_SPGMKOFF11_SHIFT)) & IRIS_MVPL_TCON0_SPG11MASKOFF_SPGMKOFF11_MASK)

/*! @name TCON0_SMX0SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S0_MASK)
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S1_MASK)
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S2_MASK)
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S3_MASK)
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX0SIGS_SMX0SIGS_S4_MASK)

/*! @name TCON0_SMX0FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON0_SMX0FCTTABLE_SMXFCT0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON0_SMX0FCTTABLE_SMXFCT0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX0FCTTABLE_SMXFCT0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX0FCTTABLE_SMXFCT0_SHIFT)) & IRIS_MVPL_TCON0_SMX0FCTTABLE_SMXFCT0_MASK)

/*! @name TCON0_SMX1SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S0_MASK)
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S1_MASK)
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S2_MASK)
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S3_MASK)
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX1SIGS_SMX1SIGS_S4_MASK)

/*! @name TCON0_SMX1FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON0_SMX1FCTTABLE_SMXFCT1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON0_SMX1FCTTABLE_SMXFCT1_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX1FCTTABLE_SMXFCT1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX1FCTTABLE_SMXFCT1_SHIFT)) & IRIS_MVPL_TCON0_SMX1FCTTABLE_SMXFCT1_MASK)

/*! @name TCON0_SMX2SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S0_MASK)
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S1_MASK)
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S2_MASK)
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S3_MASK)
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX2SIGS_SMX2SIGS_S4_MASK)

/*! @name TCON0_SMX2FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s**3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON0_SMX2FCTTABLE_SMXFCT2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON0_SMX2FCTTABLE_SMXFCT2_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX2FCTTABLE_SMXFCT2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX2FCTTABLE_SMXFCT2_SHIFT)) & IRIS_MVPL_TCON0_SMX2FCTTABLE_SMXFCT2_MASK)

/*! @name TCON0_SMX3SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S0_MASK)
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S1_MASK)
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S2_MASK)
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S3_MASK)
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX3SIGS_SMX3SIGS_S4_MASK)

/*! @name TCON0_SMX3FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON0_SMX3FCTTABLE_SMXFCT3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON0_SMX3FCTTABLE_SMXFCT3_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX3FCTTABLE_SMXFCT3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX3FCTTABLE_SMXFCT3_SHIFT)) & IRIS_MVPL_TCON0_SMX3FCTTABLE_SMXFCT3_MASK)

/*! @name TCON0_SMX4SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S0_MASK)
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S1_MASK)
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S2_MASK)
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S3_MASK)
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX4SIGS_SMX4SIGS_S4_MASK)

/*! @name TCON0_SMX4FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON0_SMX4FCTTABLE_SMXFCT4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON0_SMX4FCTTABLE_SMXFCT4_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX4FCTTABLE_SMXFCT4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX4FCTTABLE_SMXFCT4_SHIFT)) & IRIS_MVPL_TCON0_SMX4FCTTABLE_SMXFCT4_MASK)

/*! @name TCON0_SMX5SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S0_MASK)
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S1_MASK)
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S2_MASK)
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S3_MASK)
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX5SIGS_SMX5SIGS_S4_MASK)

/*! @name TCON0_SMX5FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON0_SMX5FCTTABLE_SMXFCT5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON0_SMX5FCTTABLE_SMXFCT5_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX5FCTTABLE_SMXFCT5(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX5FCTTABLE_SMXFCT5_SHIFT)) & IRIS_MVPL_TCON0_SMX5FCTTABLE_SMXFCT5_MASK)

/*! @name TCON0_SMX6SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S0_MASK)
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S1_MASK)
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S2_MASK)
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S3_MASK)
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX6SIGS_SMX6SIGS_S4_MASK)

/*! @name TCON0_SMX6FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON0_SMX6FCTTABLE_SMXFCT6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON0_SMX6FCTTABLE_SMXFCT6_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX6FCTTABLE_SMXFCT6(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX6FCTTABLE_SMXFCT6_SHIFT)) & IRIS_MVPL_TCON0_SMX6FCTTABLE_SMXFCT6_MASK)

/*! @name TCON0_SMX7SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S0_MASK)
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S1_MASK)
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S2_MASK)
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S3_MASK)
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX7SIGS_SMX7SIGS_S4_MASK)

/*! @name TCON0_SMX7FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON0_SMX7FCTTABLE_SMXFCT7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON0_SMX7FCTTABLE_SMXFCT7_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX7FCTTABLE_SMXFCT7(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX7FCTTABLE_SMXFCT7_SHIFT)) & IRIS_MVPL_TCON0_SMX7FCTTABLE_SMXFCT7_MASK)

/*! @name TCON0_SMX8SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S0_MASK)
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S1_MASK)
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S2_MASK)
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S3_MASK)
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX8SIGS_SMX8SIGS_S4_MASK)

/*! @name TCON0_SMX8FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON0_SMX8FCTTABLE_SMXFCT8_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON0_SMX8FCTTABLE_SMXFCT8_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX8FCTTABLE_SMXFCT8(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX8FCTTABLE_SMXFCT8_SHIFT)) & IRIS_MVPL_TCON0_SMX8FCTTABLE_SMXFCT8_MASK)

/*! @name TCON0_SMX9SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S0_MASK)
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S1_MASK)
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S2_MASK)
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S3_MASK)
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX9SIGS_SMX9SIGS_S4_MASK)

/*! @name TCON0_SMX9FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON0_SMX9FCTTABLE_SMXFCT9_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON0_SMX9FCTTABLE_SMXFCT9_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX9FCTTABLE_SMXFCT9(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX9FCTTABLE_SMXFCT9_SHIFT)) & IRIS_MVPL_TCON0_SMX9FCTTABLE_SMXFCT9_MASK)

/*! @name TCON0_SMX10SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S0_MASK)
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S1_MASK)
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S2_MASK)
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S3_MASK)
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX10SIGS_SMX10SIGS_S4_MASK)

/*! @name TCON0_SMX10FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON0_SMX10FCTTABLE_SMXFCT10_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON0_SMX10FCTTABLE_SMXFCT10_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX10FCTTABLE_SMXFCT10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX10FCTTABLE_SMXFCT10_SHIFT)) & IRIS_MVPL_TCON0_SMX10FCTTABLE_SMXFCT10_MASK)

/*! @name TCON0_SMX11SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S0_SHIFT)) & IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S0_MASK)
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S1_SHIFT)) & IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S1_MASK)
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S2_SHIFT)) & IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S2_MASK)
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S3_SHIFT)) & IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S3_MASK)
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S4_SHIFT)) & IRIS_MVPL_TCON0_SMX11SIGS_SMX11SIGS_S4_MASK)

/*! @name TCON0_SMX11FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON0_SMX11FCTTABLE_SMXFCT11_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON0_SMX11FCTTABLE_SMXFCT11_SHIFT (0U)
#define IRIS_MVPL_TCON0_SMX11FCTTABLE_SMXFCT11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_SMX11FCTTABLE_SMXFCT11_SHIFT)) & IRIS_MVPL_TCON0_SMX11FCTTABLE_SMXFCT11_MASK)

/*! @name TCON0_RESET_OVER_UNFERFLOW - reset status overflow and underflow of both dual channel fifos */
#define IRIS_MVPL_TCON0_RESET_OVER_UNFERFLOW_reset_status_MASK (0x1U)
#define IRIS_MVPL_TCON0_RESET_OVER_UNFERFLOW_reset_status_SHIFT (0U)
#define IRIS_MVPL_TCON0_RESET_OVER_UNFERFLOW_reset_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_RESET_OVER_UNFERFLOW_reset_status_SHIFT)) & IRIS_MVPL_TCON0_RESET_OVER_UNFERFLOW_reset_status_MASK)

/*! @name TCON0_DUAL_DEBUG - Status of fifo during dual channel operation. They are only available in Split Mode */
#define IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_overflow_MASK (0x1U)
#define IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_overflow_SHIFT (0U)
#define IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_overflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_overflow_SHIFT)) & IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_overflow_MASK)
#define IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_underflow_MASK (0x2U)
#define IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_underflow_SHIFT (1U)
#define IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_underflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_underflow_SHIFT)) & IRIS_MVPL_TCON0_DUAL_DEBUG_lower_fifo_underflow_MASK)
#define IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_overflow_MASK (0x10U)
#define IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_overflow_SHIFT (4U)
#define IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_overflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_overflow_SHIFT)) & IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_overflow_MASK)
#define IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_underflow_MASK (0x20U)
#define IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_underflow_SHIFT (5U)
#define IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_underflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_underflow_SHIFT)) & IRIS_MVPL_TCON0_DUAL_DEBUG_upper_fifo_underflow_MASK)

/*! @name SIG0_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_SIG0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_SIG0_LOCKUNLOCK_LockUnlock(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_SIG0_LOCKUNLOCK_LockUnlock_MASK)

/*! @name SIG0_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_SIG0_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_SIG0_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_SIG0_LOCKSTATUS_LockStatus(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_SIG0_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_SIG0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_SIG0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_SIG0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_SIG0_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_SIG0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_SIG0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_SIG0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_SIG0_LOCKSTATUS_FreezeStatus_MASK)

/*! @name SIG0_STATICCONTROL - Global configuration shared by all evaluation windows. */
#define IRIS_MVPL_SIG0_STATICCONTROL_ShdEn_MASK  (0x1U)
#define IRIS_MVPL_SIG0_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_SIG0_STATICCONTROL_ShdEn(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_SIG0_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_SIG0_STATICCONTROL_ShdLdSel_MASK (0x10U)
#define IRIS_MVPL_SIG0_STATICCONTROL_ShdLdSel_SHIFT (4U)
#define IRIS_MVPL_SIG0_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_SIG0_STATICCONTROL_ShdLdSel_MASK)
#define IRIS_MVPL_SIG0_STATICCONTROL_ErrThres_MASK (0xFF0000U)
#define IRIS_MVPL_SIG0_STATICCONTROL_ErrThres_SHIFT (16U)
#define IRIS_MVPL_SIG0_STATICCONTROL_ErrThres(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_STATICCONTROL_ErrThres_SHIFT)) & IRIS_MVPL_SIG0_STATICCONTROL_ErrThres_MASK)
#define IRIS_MVPL_SIG0_STATICCONTROL_ErrThresReset_MASK (0xFF000000U)
#define IRIS_MVPL_SIG0_STATICCONTROL_ErrThresReset_SHIFT (24U)
#define IRIS_MVPL_SIG0_STATICCONTROL_ErrThresReset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_STATICCONTROL_ErrThresReset_SHIFT)) & IRIS_MVPL_SIG0_STATICCONTROL_ErrThresReset_MASK)

/*! @name SIG0_PANICCOLOR - Overlay color for evaluation windows in panic mode. */
#define IRIS_MVPL_SIG0_PANICCOLOR_PanicAlpha_MASK (0x80U)
#define IRIS_MVPL_SIG0_PANICCOLOR_PanicAlpha_SHIFT (7U)
#define IRIS_MVPL_SIG0_PANICCOLOR_PanicAlpha(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_PANICCOLOR_PanicAlpha_SHIFT)) & IRIS_MVPL_SIG0_PANICCOLOR_PanicAlpha_MASK)
#define IRIS_MVPL_SIG0_PANICCOLOR_PanicBlue_MASK (0xFF00U)
#define IRIS_MVPL_SIG0_PANICCOLOR_PanicBlue_SHIFT (8U)
#define IRIS_MVPL_SIG0_PANICCOLOR_PanicBlue(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_PANICCOLOR_PanicBlue_SHIFT)) & IRIS_MVPL_SIG0_PANICCOLOR_PanicBlue_MASK)
#define IRIS_MVPL_SIG0_PANICCOLOR_PanicGreen_MASK (0xFF0000U)
#define IRIS_MVPL_SIG0_PANICCOLOR_PanicGreen_SHIFT (16U)
#define IRIS_MVPL_SIG0_PANICCOLOR_PanicGreen(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_PANICCOLOR_PanicGreen_SHIFT)) & IRIS_MVPL_SIG0_PANICCOLOR_PanicGreen_MASK)
#define IRIS_MVPL_SIG0_PANICCOLOR_PanicRed_MASK  (0xFF000000U)
#define IRIS_MVPL_SIG0_PANICCOLOR_PanicRed_SHIFT (24U)
#define IRIS_MVPL_SIG0_PANICCOLOR_PanicRed(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_PANICCOLOR_PanicRed_SHIFT)) & IRIS_MVPL_SIG0_PANICCOLOR_PanicRed_MASK)

/*! @name SIG0_EVALCONTROL0 - Control settings for evaluation window 0. */
#define IRIS_MVPL_SIG0_EVALCONTROL0_EnEvalWin0_MASK (0x1U)
#define IRIS_MVPL_SIG0_EVALCONTROL0_EnEvalWin0_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALCONTROL0_EnEvalWin0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL0_EnEvalWin0_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL0_EnEvalWin0_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL0_EnCRC0_MASK  (0x2U)
#define IRIS_MVPL_SIG0_EVALCONTROL0_EnCRC0_SHIFT (1U)
#define IRIS_MVPL_SIG0_EVALCONTROL0_EnCRC0(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL0_EnCRC0_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL0_EnCRC0_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL0_AlphaMask0_MASK (0x100U)
#define IRIS_MVPL_SIG0_EVALCONTROL0_AlphaMask0_SHIFT (8U)
#define IRIS_MVPL_SIG0_EVALCONTROL0_AlphaMask0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL0_AlphaMask0_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL0_AlphaMask0_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL0_AlphaInv0_MASK (0x200U)
#define IRIS_MVPL_SIG0_EVALCONTROL0_AlphaInv0_SHIFT (9U)
#define IRIS_MVPL_SIG0_EVALCONTROL0_AlphaInv0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL0_AlphaInv0_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL0_AlphaInv0_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL0_EnLocalPanic0_MASK (0x10000U)
#define IRIS_MVPL_SIG0_EVALCONTROL0_EnLocalPanic0_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALCONTROL0_EnLocalPanic0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL0_EnLocalPanic0_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL0_EnLocalPanic0_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL0_EnGlobalPanic0_MASK (0x20000U)
#define IRIS_MVPL_SIG0_EVALCONTROL0_EnGlobalPanic0_SHIFT (17U)
#define IRIS_MVPL_SIG0_EVALCONTROL0_EnGlobalPanic0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL0_EnGlobalPanic0_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL0_EnGlobalPanic0_MASK)

/*! @name SIG0_EVALUPPERLEFT0 - Upper left corner of evaluation window 0. */
#define IRIS_MVPL_SIG0_EVALUPPERLEFT0_XEvalUpperLeft0_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT0_XEvalUpperLeft0_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT0_XEvalUpperLeft0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT0_XEvalUpperLeft0_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT0_XEvalUpperLeft0_MASK)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT0_YEvalUpperLeft0_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT0_YEvalUpperLeft0_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT0_YEvalUpperLeft0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT0_YEvalUpperLeft0_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT0_YEvalUpperLeft0_MASK)

/*! @name SIG0_EVALLOWERRIGHT0 - Lower right corner of evaluation window 0. */
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT0_XEvalLowerRight0_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT0_XEvalLowerRight0_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT0_XEvalLowerRight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT0_XEvalLowerRight0_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT0_XEvalLowerRight0_MASK)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT0_YEvalLowerRight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT0_YEvalLowerRight0_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT0_YEvalLowerRight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT0_YEvalLowerRight0_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT0_YEvalLowerRight0_MASK)

/*! @name SIG0_SIGCRCREDREF0 - Reference signature of red channel for evaluation window 0. */
#define IRIS_MVPL_SIG0_SIGCRCREDREF0_SigCRCRedRef0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCREDREF0_SigCRCRedRef0_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCREDREF0_SigCRCRedRef0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF0_SigCRCRedRef0_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF0_SigCRCRedRef0_MASK)

/*! @name SIG0_SIGCRCGREENREF0 - Reference signature of green channel for evaluation window 0. */
#define IRIS_MVPL_SIG0_SIGCRCGREENREF0_SigCRCGreenRef0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF0_SigCRCGreenRef0_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF0_SigCRCGreenRef0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF0_SigCRCGreenRef0_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF0_SigCRCGreenRef0_MASK)

/*! @name SIG0_SIGCRCBLUEREF0 - Reference signature of blue channel for evaluation window 0. */
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF0_SigCRCBlueRef0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF0_SigCRCBlueRef0_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF0_SigCRCBlueRef0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF0_SigCRCBlueRef0_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF0_SigCRCBlueRef0_MASK)

/*! @name SIG0_SIGCRCRED0 - Measured signature of red channel for evaluation window 0. */
#define IRIS_MVPL_SIG0_SIGCRCRED0_SigCRCRed0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCRED0_SigCRCRed0_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCRED0_SigCRCRed0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED0_SigCRCRed0_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED0_SigCRCRed0_MASK)

/*! @name SIG0_SIGCRCGREEN0 - Measured signature of green channel for evaluation window 0. */
#define IRIS_MVPL_SIG0_SIGCRCGREEN0_SigCRCGreen0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREEN0_SigCRCGreen0_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREEN0_SigCRCGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN0_SigCRCGreen0_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN0_SigCRCGreen0_MASK)

/*! @name SIG0_SIGCRCBLUE0 - Measured signature of blue channel for evaluation window 0. */
#define IRIS_MVPL_SIG0_SIGCRCBLUE0_SigCRCBlue0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUE0_SigCRCBlue0_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUE0_SigCRCBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE0_SigCRCBlue0_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE0_SigCRCBlue0_MASK)

/*! @name SIG0_EVALCONTROL1 - Control settings for evaluation window 1. */
#define IRIS_MVPL_SIG0_EVALCONTROL1_EnEvalWin1_MASK (0x1U)
#define IRIS_MVPL_SIG0_EVALCONTROL1_EnEvalWin1_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALCONTROL1_EnEvalWin1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL1_EnEvalWin1_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL1_EnEvalWin1_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL1_EnCRC1_MASK  (0x2U)
#define IRIS_MVPL_SIG0_EVALCONTROL1_EnCRC1_SHIFT (1U)
#define IRIS_MVPL_SIG0_EVALCONTROL1_EnCRC1(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL1_EnCRC1_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL1_EnCRC1_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL1_AlphaMask1_MASK (0x100U)
#define IRIS_MVPL_SIG0_EVALCONTROL1_AlphaMask1_SHIFT (8U)
#define IRIS_MVPL_SIG0_EVALCONTROL1_AlphaMask1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL1_AlphaMask1_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL1_AlphaMask1_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL1_AlphaInv1_MASK (0x200U)
#define IRIS_MVPL_SIG0_EVALCONTROL1_AlphaInv1_SHIFT (9U)
#define IRIS_MVPL_SIG0_EVALCONTROL1_AlphaInv1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL1_AlphaInv1_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL1_AlphaInv1_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL1_EnLocalPanic1_MASK (0x10000U)
#define IRIS_MVPL_SIG0_EVALCONTROL1_EnLocalPanic1_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALCONTROL1_EnLocalPanic1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL1_EnLocalPanic1_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL1_EnLocalPanic1_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL1_EnGlobalPanic1_MASK (0x20000U)
#define IRIS_MVPL_SIG0_EVALCONTROL1_EnGlobalPanic1_SHIFT (17U)
#define IRIS_MVPL_SIG0_EVALCONTROL1_EnGlobalPanic1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL1_EnGlobalPanic1_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL1_EnGlobalPanic1_MASK)

/*! @name SIG0_EVALUPPERLEFT1 - Upper left corner of evaluation window 1. */
#define IRIS_MVPL_SIG0_EVALUPPERLEFT1_XEvalUpperLeft1_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT1_XEvalUpperLeft1_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT1_XEvalUpperLeft1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT1_XEvalUpperLeft1_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT1_XEvalUpperLeft1_MASK)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT1_YEvalUpperLeft1_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT1_YEvalUpperLeft1_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT1_YEvalUpperLeft1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT1_YEvalUpperLeft1_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT1_YEvalUpperLeft1_MASK)

/*! @name SIG0_EVALLOWERRIGHT1 - Lower right corner of evaluation window 1. */
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT1_XEvalLowerRight1_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT1_XEvalLowerRight1_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT1_XEvalLowerRight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT1_XEvalLowerRight1_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT1_XEvalLowerRight1_MASK)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT1_YEvalLowerRight1_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT1_YEvalLowerRight1_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT1_YEvalLowerRight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT1_YEvalLowerRight1_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT1_YEvalLowerRight1_MASK)

/*! @name SIG0_SIGCRCREDREF1 - Reference signature of red channel for evaluation window 1. */
#define IRIS_MVPL_SIG0_SIGCRCREDREF1_SigCRCRedRef1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCREDREF1_SigCRCRedRef1_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCREDREF1_SigCRCRedRef1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF1_SigCRCRedRef1_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF1_SigCRCRedRef1_MASK)

/*! @name SIG0_SIGCRCGREENREF1 - Reference signature of green channel for evaluation window 1. */
#define IRIS_MVPL_SIG0_SIGCRCGREENREF1_SigCRCGreenRef1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF1_SigCRCGreenRef1_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF1_SigCRCGreenRef1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF1_SigCRCGreenRef1_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF1_SigCRCGreenRef1_MASK)

/*! @name SIG0_SIGCRCBLUEREF1 - Reference signature of blue channel for evaluation window 1. */
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF1_SigCRCBlueRef1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF1_SigCRCBlueRef1_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF1_SigCRCBlueRef1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF1_SigCRCBlueRef1_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF1_SigCRCBlueRef1_MASK)

/*! @name SIG0_SIGCRCRED1 - Measured signature of red channel for evaluation window 1. */
#define IRIS_MVPL_SIG0_SIGCRCRED1_SigCRCRed1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCRED1_SigCRCRed1_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCRED1_SigCRCRed1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED1_SigCRCRed1_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED1_SigCRCRed1_MASK)

/*! @name SIG0_SIGCRCGREEN1 - Measured signature of green channel for evaluation window 1. */
#define IRIS_MVPL_SIG0_SIGCRCGREEN1_SigCRCGreen1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREEN1_SigCRCGreen1_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREEN1_SigCRCGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN1_SigCRCGreen1_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN1_SigCRCGreen1_MASK)

/*! @name SIG0_SIGCRCBLUE1 - Measured signature of blue channel for evaluation window 1. */
#define IRIS_MVPL_SIG0_SIGCRCBLUE1_SigCRCBlue1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUE1_SigCRCBlue1_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUE1_SigCRCBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE1_SigCRCBlue1_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE1_SigCRCBlue1_MASK)

/*! @name SIG0_EVALCONTROL2 - Control settings for evaluation window 2. */
#define IRIS_MVPL_SIG0_EVALCONTROL2_EnEvalWin2_MASK (0x1U)
#define IRIS_MVPL_SIG0_EVALCONTROL2_EnEvalWin2_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALCONTROL2_EnEvalWin2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL2_EnEvalWin2_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL2_EnEvalWin2_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL2_EnCRC2_MASK  (0x2U)
#define IRIS_MVPL_SIG0_EVALCONTROL2_EnCRC2_SHIFT (1U)
#define IRIS_MVPL_SIG0_EVALCONTROL2_EnCRC2(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL2_EnCRC2_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL2_EnCRC2_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL2_AlphaMask2_MASK (0x100U)
#define IRIS_MVPL_SIG0_EVALCONTROL2_AlphaMask2_SHIFT (8U)
#define IRIS_MVPL_SIG0_EVALCONTROL2_AlphaMask2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL2_AlphaMask2_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL2_AlphaMask2_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL2_AlphaInv2_MASK (0x200U)
#define IRIS_MVPL_SIG0_EVALCONTROL2_AlphaInv2_SHIFT (9U)
#define IRIS_MVPL_SIG0_EVALCONTROL2_AlphaInv2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL2_AlphaInv2_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL2_AlphaInv2_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL2_EnLocalPanic2_MASK (0x10000U)
#define IRIS_MVPL_SIG0_EVALCONTROL2_EnLocalPanic2_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALCONTROL2_EnLocalPanic2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL2_EnLocalPanic2_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL2_EnLocalPanic2_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL2_EnGlobalPanic2_MASK (0x20000U)
#define IRIS_MVPL_SIG0_EVALCONTROL2_EnGlobalPanic2_SHIFT (17U)
#define IRIS_MVPL_SIG0_EVALCONTROL2_EnGlobalPanic2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL2_EnGlobalPanic2_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL2_EnGlobalPanic2_MASK)

/*! @name SIG0_EVALUPPERLEFT2 - Upper left corner of evaluation window 2. */
#define IRIS_MVPL_SIG0_EVALUPPERLEFT2_XEvalUpperLeft2_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT2_XEvalUpperLeft2_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT2_XEvalUpperLeft2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT2_XEvalUpperLeft2_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT2_XEvalUpperLeft2_MASK)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT2_YEvalUpperLeft2_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT2_YEvalUpperLeft2_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT2_YEvalUpperLeft2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT2_YEvalUpperLeft2_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT2_YEvalUpperLeft2_MASK)

/*! @name SIG0_EVALLOWERRIGHT2 - Lower right corner of evaluation window 2. */
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT2_XEvalLowerRight2_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT2_XEvalLowerRight2_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT2_XEvalLowerRight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT2_XEvalLowerRight2_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT2_XEvalLowerRight2_MASK)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT2_YEvalLowerRight2_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT2_YEvalLowerRight2_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT2_YEvalLowerRight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT2_YEvalLowerRight2_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT2_YEvalLowerRight2_MASK)

/*! @name SIG0_SIGCRCREDREF2 - Reference signature of red channel for evaluation window 2. */
#define IRIS_MVPL_SIG0_SIGCRCREDREF2_SigCRCRedRef2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCREDREF2_SigCRCRedRef2_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCREDREF2_SigCRCRedRef2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF2_SigCRCRedRef2_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF2_SigCRCRedRef2_MASK)

/*! @name SIG0_SIGCRCGREENREF2 - Reference signature of green channel for evaluation window 2. */
#define IRIS_MVPL_SIG0_SIGCRCGREENREF2_SigCRCGreenRef2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF2_SigCRCGreenRef2_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF2_SigCRCGreenRef2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF2_SigCRCGreenRef2_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF2_SigCRCGreenRef2_MASK)

/*! @name SIG0_SIGCRCBLUEREF2 - Reference signature of blue channel for evaluation window 2. */
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF2_SigCRCBlueRef2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF2_SigCRCBlueRef2_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF2_SigCRCBlueRef2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF2_SigCRCBlueRef2_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF2_SigCRCBlueRef2_MASK)

/*! @name SIG0_SIGCRCRED2 - Measured signature of red channel for evaluation window 2. */
#define IRIS_MVPL_SIG0_SIGCRCRED2_SigCRCRed2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCRED2_SigCRCRed2_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCRED2_SigCRCRed2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED2_SigCRCRed2_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED2_SigCRCRed2_MASK)

/*! @name SIG0_SIGCRCGREEN2 - Measured signature of green channel for evaluation window 2. */
#define IRIS_MVPL_SIG0_SIGCRCGREEN2_SigCRCGreen2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREEN2_SigCRCGreen2_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREEN2_SigCRCGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN2_SigCRCGreen2_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN2_SigCRCGreen2_MASK)

/*! @name SIG0_SIGCRCBLUE2 - Measured signature of blue channel for evaluation window 2. */
#define IRIS_MVPL_SIG0_SIGCRCBLUE2_SigCRCBlue2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUE2_SigCRCBlue2_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUE2_SigCRCBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE2_SigCRCBlue2_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE2_SigCRCBlue2_MASK)

/*! @name SIG0_EVALCONTROL3 - Control settings for evaluation window 3. */
#define IRIS_MVPL_SIG0_EVALCONTROL3_EnEvalWin3_MASK (0x1U)
#define IRIS_MVPL_SIG0_EVALCONTROL3_EnEvalWin3_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALCONTROL3_EnEvalWin3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL3_EnEvalWin3_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL3_EnEvalWin3_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL3_EnCRC3_MASK  (0x2U)
#define IRIS_MVPL_SIG0_EVALCONTROL3_EnCRC3_SHIFT (1U)
#define IRIS_MVPL_SIG0_EVALCONTROL3_EnCRC3(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL3_EnCRC3_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL3_EnCRC3_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL3_AlphaMask3_MASK (0x100U)
#define IRIS_MVPL_SIG0_EVALCONTROL3_AlphaMask3_SHIFT (8U)
#define IRIS_MVPL_SIG0_EVALCONTROL3_AlphaMask3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL3_AlphaMask3_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL3_AlphaMask3_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL3_AlphaInv3_MASK (0x200U)
#define IRIS_MVPL_SIG0_EVALCONTROL3_AlphaInv3_SHIFT (9U)
#define IRIS_MVPL_SIG0_EVALCONTROL3_AlphaInv3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL3_AlphaInv3_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL3_AlphaInv3_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL3_EnLocalPanic3_MASK (0x10000U)
#define IRIS_MVPL_SIG0_EVALCONTROL3_EnLocalPanic3_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALCONTROL3_EnLocalPanic3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL3_EnLocalPanic3_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL3_EnLocalPanic3_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL3_EnGlobalPanic3_MASK (0x20000U)
#define IRIS_MVPL_SIG0_EVALCONTROL3_EnGlobalPanic3_SHIFT (17U)
#define IRIS_MVPL_SIG0_EVALCONTROL3_EnGlobalPanic3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL3_EnGlobalPanic3_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL3_EnGlobalPanic3_MASK)

/*! @name SIG0_EVALUPPERLEFT3 - Upper left corner of evaluation window 3. */
#define IRIS_MVPL_SIG0_EVALUPPERLEFT3_XEvalUpperLeft3_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT3_XEvalUpperLeft3_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT3_XEvalUpperLeft3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT3_XEvalUpperLeft3_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT3_XEvalUpperLeft3_MASK)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT3_YEvalUpperLeft3_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT3_YEvalUpperLeft3_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT3_YEvalUpperLeft3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT3_YEvalUpperLeft3_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT3_YEvalUpperLeft3_MASK)

/*! @name SIG0_EVALLOWERRIGHT3 - Lower right corner of evaluation window 3. */
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT3_XEvalLowerRight3_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT3_XEvalLowerRight3_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT3_XEvalLowerRight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT3_XEvalLowerRight3_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT3_XEvalLowerRight3_MASK)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT3_YEvalLowerRight3_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT3_YEvalLowerRight3_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT3_YEvalLowerRight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT3_YEvalLowerRight3_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT3_YEvalLowerRight3_MASK)

/*! @name SIG0_SIGCRCREDREF3 - Reference signature of red channel for evaluation window 3. */
#define IRIS_MVPL_SIG0_SIGCRCREDREF3_SigCRCRedRef3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCREDREF3_SigCRCRedRef3_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCREDREF3_SigCRCRedRef3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF3_SigCRCRedRef3_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF3_SigCRCRedRef3_MASK)

/*! @name SIG0_SIGCRCGREENREF3 - Reference signature of green channel for evaluation window 3. */
#define IRIS_MVPL_SIG0_SIGCRCGREENREF3_SigCRCGreenRef3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF3_SigCRCGreenRef3_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF3_SigCRCGreenRef3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF3_SigCRCGreenRef3_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF3_SigCRCGreenRef3_MASK)

/*! @name SIG0_SIGCRCBLUEREF3 - Reference signature of blue channel for evaluation window 3. */
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF3_SigCRCBlueRef3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF3_SigCRCBlueRef3_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF3_SigCRCBlueRef3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF3_SigCRCBlueRef3_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF3_SigCRCBlueRef3_MASK)

/*! @name SIG0_SIGCRCRED3 - Measured signature of red channel for evaluation window 3. */
#define IRIS_MVPL_SIG0_SIGCRCRED3_SigCRCRed3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCRED3_SigCRCRed3_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCRED3_SigCRCRed3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED3_SigCRCRed3_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED3_SigCRCRed3_MASK)

/*! @name SIG0_SIGCRCGREEN3 - Measured signature of green channel for evaluation window 3. */
#define IRIS_MVPL_SIG0_SIGCRCGREEN3_SigCRCGreen3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREEN3_SigCRCGreen3_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREEN3_SigCRCGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN3_SigCRCGreen3_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN3_SigCRCGreen3_MASK)

/*! @name SIG0_SIGCRCBLUE3 - Measured signature of blue channel for evaluation window 3. */
#define IRIS_MVPL_SIG0_SIGCRCBLUE3_SigCRCBlue3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUE3_SigCRCBlue3_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUE3_SigCRCBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE3_SigCRCBlue3_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE3_SigCRCBlue3_MASK)

/*! @name SIG0_EVALCONTROL4 - Control settings for evaluation window 4. */
#define IRIS_MVPL_SIG0_EVALCONTROL4_EnEvalWin4_MASK (0x1U)
#define IRIS_MVPL_SIG0_EVALCONTROL4_EnEvalWin4_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALCONTROL4_EnEvalWin4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL4_EnEvalWin4_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL4_EnEvalWin4_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL4_EnCRC4_MASK  (0x2U)
#define IRIS_MVPL_SIG0_EVALCONTROL4_EnCRC4_SHIFT (1U)
#define IRIS_MVPL_SIG0_EVALCONTROL4_EnCRC4(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL4_EnCRC4_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL4_EnCRC4_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL4_AlphaMask4_MASK (0x100U)
#define IRIS_MVPL_SIG0_EVALCONTROL4_AlphaMask4_SHIFT (8U)
#define IRIS_MVPL_SIG0_EVALCONTROL4_AlphaMask4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL4_AlphaMask4_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL4_AlphaMask4_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL4_AlphaInv4_MASK (0x200U)
#define IRIS_MVPL_SIG0_EVALCONTROL4_AlphaInv4_SHIFT (9U)
#define IRIS_MVPL_SIG0_EVALCONTROL4_AlphaInv4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL4_AlphaInv4_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL4_AlphaInv4_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL4_EnLocalPanic4_MASK (0x10000U)
#define IRIS_MVPL_SIG0_EVALCONTROL4_EnLocalPanic4_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALCONTROL4_EnLocalPanic4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL4_EnLocalPanic4_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL4_EnLocalPanic4_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL4_EnGlobalPanic4_MASK (0x20000U)
#define IRIS_MVPL_SIG0_EVALCONTROL4_EnGlobalPanic4_SHIFT (17U)
#define IRIS_MVPL_SIG0_EVALCONTROL4_EnGlobalPanic4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL4_EnGlobalPanic4_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL4_EnGlobalPanic4_MASK)

/*! @name SIG0_EVALUPPERLEFT4 - Upper left corner of evaluation window 4. */
#define IRIS_MVPL_SIG0_EVALUPPERLEFT4_XEvalUpperLeft4_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT4_XEvalUpperLeft4_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT4_XEvalUpperLeft4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT4_XEvalUpperLeft4_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT4_XEvalUpperLeft4_MASK)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT4_YEvalUpperLeft4_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT4_YEvalUpperLeft4_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT4_YEvalUpperLeft4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT4_YEvalUpperLeft4_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT4_YEvalUpperLeft4_MASK)

/*! @name SIG0_EVALLOWERRIGHT4 - Lower right corner of evaluation window 4. */
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT4_XEvalLowerRight4_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT4_XEvalLowerRight4_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT4_XEvalLowerRight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT4_XEvalLowerRight4_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT4_XEvalLowerRight4_MASK)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT4_YEvalLowerRight4_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT4_YEvalLowerRight4_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT4_YEvalLowerRight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT4_YEvalLowerRight4_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT4_YEvalLowerRight4_MASK)

/*! @name SIG0_SIGCRCREDREF4 - Reference signature of red channel for evaluation window 4. */
#define IRIS_MVPL_SIG0_SIGCRCREDREF4_SigCRCRedRef4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCREDREF4_SigCRCRedRef4_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCREDREF4_SigCRCRedRef4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF4_SigCRCRedRef4_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF4_SigCRCRedRef4_MASK)

/*! @name SIG0_SIGCRCGREENREF4 - Reference signature of green channel for evaluation window 4. */
#define IRIS_MVPL_SIG0_SIGCRCGREENREF4_SigCRCGreenRef4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF4_SigCRCGreenRef4_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF4_SigCRCGreenRef4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF4_SigCRCGreenRef4_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF4_SigCRCGreenRef4_MASK)

/*! @name SIG0_SIGCRCBLUEREF4 - Reference signature of blue channel for evaluation window 4. */
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF4_SigCRCBlueRef4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF4_SigCRCBlueRef4_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF4_SigCRCBlueRef4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF4_SigCRCBlueRef4_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF4_SigCRCBlueRef4_MASK)

/*! @name SIG0_SIGCRCRED4 - Measured signature of red channel for evaluation window 4. */
#define IRIS_MVPL_SIG0_SIGCRCRED4_SigCRCRed4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCRED4_SigCRCRed4_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCRED4_SigCRCRed4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED4_SigCRCRed4_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED4_SigCRCRed4_MASK)

/*! @name SIG0_SIGCRCGREEN4 - Measured signature of green channel for evaluation window 4. */
#define IRIS_MVPL_SIG0_SIGCRCGREEN4_SigCRCGreen4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREEN4_SigCRCGreen4_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREEN4_SigCRCGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN4_SigCRCGreen4_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN4_SigCRCGreen4_MASK)

/*! @name SIG0_SIGCRCBLUE4 - Measured signature of blue channel for evaluation window 4. */
#define IRIS_MVPL_SIG0_SIGCRCBLUE4_SigCRCBlue4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUE4_SigCRCBlue4_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUE4_SigCRCBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE4_SigCRCBlue4_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE4_SigCRCBlue4_MASK)

/*! @name SIG0_EVALCONTROL5 - Control settings for evaluation window 5. */
#define IRIS_MVPL_SIG0_EVALCONTROL5_EnEvalWin5_MASK (0x1U)
#define IRIS_MVPL_SIG0_EVALCONTROL5_EnEvalWin5_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALCONTROL5_EnEvalWin5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL5_EnEvalWin5_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL5_EnEvalWin5_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL5_EnCRC5_MASK  (0x2U)
#define IRIS_MVPL_SIG0_EVALCONTROL5_EnCRC5_SHIFT (1U)
#define IRIS_MVPL_SIG0_EVALCONTROL5_EnCRC5(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL5_EnCRC5_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL5_EnCRC5_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL5_AlphaMask5_MASK (0x100U)
#define IRIS_MVPL_SIG0_EVALCONTROL5_AlphaMask5_SHIFT (8U)
#define IRIS_MVPL_SIG0_EVALCONTROL5_AlphaMask5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL5_AlphaMask5_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL5_AlphaMask5_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL5_AlphaInv5_MASK (0x200U)
#define IRIS_MVPL_SIG0_EVALCONTROL5_AlphaInv5_SHIFT (9U)
#define IRIS_MVPL_SIG0_EVALCONTROL5_AlphaInv5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL5_AlphaInv5_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL5_AlphaInv5_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL5_EnLocalPanic5_MASK (0x10000U)
#define IRIS_MVPL_SIG0_EVALCONTROL5_EnLocalPanic5_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALCONTROL5_EnLocalPanic5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL5_EnLocalPanic5_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL5_EnLocalPanic5_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL5_EnGlobalPanic5_MASK (0x20000U)
#define IRIS_MVPL_SIG0_EVALCONTROL5_EnGlobalPanic5_SHIFT (17U)
#define IRIS_MVPL_SIG0_EVALCONTROL5_EnGlobalPanic5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL5_EnGlobalPanic5_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL5_EnGlobalPanic5_MASK)

/*! @name SIG0_EVALUPPERLEFT5 - Upper left corner of evaluation window 5. */
#define IRIS_MVPL_SIG0_EVALUPPERLEFT5_XEvalUpperLeft5_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT5_XEvalUpperLeft5_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT5_XEvalUpperLeft5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT5_XEvalUpperLeft5_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT5_XEvalUpperLeft5_MASK)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT5_YEvalUpperLeft5_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT5_YEvalUpperLeft5_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT5_YEvalUpperLeft5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT5_YEvalUpperLeft5_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT5_YEvalUpperLeft5_MASK)

/*! @name SIG0_EVALLOWERRIGHT5 - Lower right corner of evaluation window 5. */
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT5_XEvalLowerRight5_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT5_XEvalLowerRight5_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT5_XEvalLowerRight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT5_XEvalLowerRight5_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT5_XEvalLowerRight5_MASK)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT5_YEvalLowerRight5_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT5_YEvalLowerRight5_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT5_YEvalLowerRight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT5_YEvalLowerRight5_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT5_YEvalLowerRight5_MASK)

/*! @name SIG0_SIGCRCREDREF5 - Reference signature of red channel for evaluation window 5. */
#define IRIS_MVPL_SIG0_SIGCRCREDREF5_SigCRCRedRef5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCREDREF5_SigCRCRedRef5_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCREDREF5_SigCRCRedRef5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF5_SigCRCRedRef5_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF5_SigCRCRedRef5_MASK)

/*! @name SIG0_SIGCRCGREENREF5 - Reference signature of green channel for evaluation window 5. */
#define IRIS_MVPL_SIG0_SIGCRCGREENREF5_SigCRCGreenRef5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF5_SigCRCGreenRef5_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF5_SigCRCGreenRef5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF5_SigCRCGreenRef5_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF5_SigCRCGreenRef5_MASK)

/*! @name SIG0_SIGCRCBLUEREF5 - Reference signature of blue channel for evaluation window 5. */
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF5_SigCRCBlueRef5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF5_SigCRCBlueRef5_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF5_SigCRCBlueRef5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF5_SigCRCBlueRef5_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF5_SigCRCBlueRef5_MASK)

/*! @name SIG0_SIGCRCRED5 - Measured signature of red channel for evaluation window 5. */
#define IRIS_MVPL_SIG0_SIGCRCRED5_SigCRCRed5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCRED5_SigCRCRed5_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCRED5_SigCRCRed5(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED5_SigCRCRed5_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED5_SigCRCRed5_MASK)

/*! @name SIG0_SIGCRCGREEN5 - Measured signature of green channel for evaluation window 5. */
#define IRIS_MVPL_SIG0_SIGCRCGREEN5_SigCRCGreen5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREEN5_SigCRCGreen5_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREEN5_SigCRCGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN5_SigCRCGreen5_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN5_SigCRCGreen5_MASK)

/*! @name SIG0_SIGCRCBLUE5 - Measured signature of blue channel for evaluation window 5. */
#define IRIS_MVPL_SIG0_SIGCRCBLUE5_SigCRCBlue5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUE5_SigCRCBlue5_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUE5_SigCRCBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE5_SigCRCBlue5_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE5_SigCRCBlue5_MASK)

/*! @name SIG0_EVALCONTROL6 - Control settings for evaluation window 6. */
#define IRIS_MVPL_SIG0_EVALCONTROL6_EnEvalWin6_MASK (0x1U)
#define IRIS_MVPL_SIG0_EVALCONTROL6_EnEvalWin6_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALCONTROL6_EnEvalWin6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL6_EnEvalWin6_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL6_EnEvalWin6_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL6_EnCRC6_MASK  (0x2U)
#define IRIS_MVPL_SIG0_EVALCONTROL6_EnCRC6_SHIFT (1U)
#define IRIS_MVPL_SIG0_EVALCONTROL6_EnCRC6(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL6_EnCRC6_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL6_EnCRC6_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL6_AlphaMask6_MASK (0x100U)
#define IRIS_MVPL_SIG0_EVALCONTROL6_AlphaMask6_SHIFT (8U)
#define IRIS_MVPL_SIG0_EVALCONTROL6_AlphaMask6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL6_AlphaMask6_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL6_AlphaMask6_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL6_AlphaInv6_MASK (0x200U)
#define IRIS_MVPL_SIG0_EVALCONTROL6_AlphaInv6_SHIFT (9U)
#define IRIS_MVPL_SIG0_EVALCONTROL6_AlphaInv6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL6_AlphaInv6_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL6_AlphaInv6_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL6_EnLocalPanic6_MASK (0x10000U)
#define IRIS_MVPL_SIG0_EVALCONTROL6_EnLocalPanic6_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALCONTROL6_EnLocalPanic6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL6_EnLocalPanic6_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL6_EnLocalPanic6_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL6_EnGlobalPanic6_MASK (0x20000U)
#define IRIS_MVPL_SIG0_EVALCONTROL6_EnGlobalPanic6_SHIFT (17U)
#define IRIS_MVPL_SIG0_EVALCONTROL6_EnGlobalPanic6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL6_EnGlobalPanic6_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL6_EnGlobalPanic6_MASK)

/*! @name SIG0_EVALUPPERLEFT6 - Upper left corner of evaluation window 6. */
#define IRIS_MVPL_SIG0_EVALUPPERLEFT6_XEvalUpperLeft6_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT6_XEvalUpperLeft6_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT6_XEvalUpperLeft6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT6_XEvalUpperLeft6_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT6_XEvalUpperLeft6_MASK)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT6_YEvalUpperLeft6_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT6_YEvalUpperLeft6_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT6_YEvalUpperLeft6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT6_YEvalUpperLeft6_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT6_YEvalUpperLeft6_MASK)

/*! @name SIG0_EVALLOWERRIGHT6 - Lower right corner of evaluation window 6. */
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT6_XEvalLowerRight6_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT6_XEvalLowerRight6_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT6_XEvalLowerRight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT6_XEvalLowerRight6_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT6_XEvalLowerRight6_MASK)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT6_YEvalLowerRight6_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT6_YEvalLowerRight6_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT6_YEvalLowerRight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT6_YEvalLowerRight6_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT6_YEvalLowerRight6_MASK)

/*! @name SIG0_SIGCRCREDREF6 - Reference signature of red channel for evaluation window 6. */
#define IRIS_MVPL_SIG0_SIGCRCREDREF6_SigCRCRedRef6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCREDREF6_SigCRCRedRef6_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCREDREF6_SigCRCRedRef6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF6_SigCRCRedRef6_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF6_SigCRCRedRef6_MASK)

/*! @name SIG0_SIGCRCGREENREF6 - Reference signature of green channel for evaluation window 6. */
#define IRIS_MVPL_SIG0_SIGCRCGREENREF6_SigCRCGreenRef6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF6_SigCRCGreenRef6_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF6_SigCRCGreenRef6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF6_SigCRCGreenRef6_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF6_SigCRCGreenRef6_MASK)

/*! @name SIG0_SIGCRCBLUEREF6 - Reference signature of blue channel for evaluation window 6. */
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF6_SigCRCBlueRef6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF6_SigCRCBlueRef6_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF6_SigCRCBlueRef6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF6_SigCRCBlueRef6_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF6_SigCRCBlueRef6_MASK)

/*! @name SIG0_SIGCRCRED6 - Measured signature of red channel for evaluation window 6. */
#define IRIS_MVPL_SIG0_SIGCRCRED6_SigCRCRed6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCRED6_SigCRCRed6_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCRED6_SigCRCRed6(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED6_SigCRCRed6_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED6_SigCRCRed6_MASK)

/*! @name SIG0_SIGCRCGREEN6 - Measured signature of green channel for evaluation window 6. */
#define IRIS_MVPL_SIG0_SIGCRCGREEN6_SigCRCGreen6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREEN6_SigCRCGreen6_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREEN6_SigCRCGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN6_SigCRCGreen6_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN6_SigCRCGreen6_MASK)

/*! @name SIG0_SIGCRCBLUE6 - Measured signature of blue channel for evaluation window 6. */
#define IRIS_MVPL_SIG0_SIGCRCBLUE6_SigCRCBlue6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUE6_SigCRCBlue6_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUE6_SigCRCBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE6_SigCRCBlue6_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE6_SigCRCBlue6_MASK)

/*! @name SIG0_EVALCONTROL7 - Control settings for evaluation window 7. */
#define IRIS_MVPL_SIG0_EVALCONTROL7_EnEvalWin7_MASK (0x1U)
#define IRIS_MVPL_SIG0_EVALCONTROL7_EnEvalWin7_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALCONTROL7_EnEvalWin7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL7_EnEvalWin7_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL7_EnEvalWin7_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL7_EnCRC7_MASK  (0x2U)
#define IRIS_MVPL_SIG0_EVALCONTROL7_EnCRC7_SHIFT (1U)
#define IRIS_MVPL_SIG0_EVALCONTROL7_EnCRC7(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL7_EnCRC7_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL7_EnCRC7_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL7_AlphaMask7_MASK (0x100U)
#define IRIS_MVPL_SIG0_EVALCONTROL7_AlphaMask7_SHIFT (8U)
#define IRIS_MVPL_SIG0_EVALCONTROL7_AlphaMask7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL7_AlphaMask7_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL7_AlphaMask7_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL7_AlphaInv7_MASK (0x200U)
#define IRIS_MVPL_SIG0_EVALCONTROL7_AlphaInv7_SHIFT (9U)
#define IRIS_MVPL_SIG0_EVALCONTROL7_AlphaInv7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL7_AlphaInv7_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL7_AlphaInv7_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL7_EnLocalPanic7_MASK (0x10000U)
#define IRIS_MVPL_SIG0_EVALCONTROL7_EnLocalPanic7_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALCONTROL7_EnLocalPanic7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL7_EnLocalPanic7_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL7_EnLocalPanic7_MASK)
#define IRIS_MVPL_SIG0_EVALCONTROL7_EnGlobalPanic7_MASK (0x20000U)
#define IRIS_MVPL_SIG0_EVALCONTROL7_EnGlobalPanic7_SHIFT (17U)
#define IRIS_MVPL_SIG0_EVALCONTROL7_EnGlobalPanic7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALCONTROL7_EnGlobalPanic7_SHIFT)) & IRIS_MVPL_SIG0_EVALCONTROL7_EnGlobalPanic7_MASK)

/*! @name SIG0_EVALUPPERLEFT7 - Upper left corner of evaluation window 7. */
#define IRIS_MVPL_SIG0_EVALUPPERLEFT7_XEvalUpperLeft7_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT7_XEvalUpperLeft7_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT7_XEvalUpperLeft7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT7_XEvalUpperLeft7_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT7_XEvalUpperLeft7_MASK)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT7_YEvalUpperLeft7_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT7_YEvalUpperLeft7_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALUPPERLEFT7_YEvalUpperLeft7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALUPPERLEFT7_YEvalUpperLeft7_SHIFT)) & IRIS_MVPL_SIG0_EVALUPPERLEFT7_YEvalUpperLeft7_MASK)

/*! @name SIG0_EVALLOWERRIGHT7 - Lower right corner of evaluation window 7. */
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT7_XEvalLowerRight7_MASK (0x3FFFU)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT7_XEvalLowerRight7_SHIFT (0U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT7_XEvalLowerRight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT7_XEvalLowerRight7_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT7_XEvalLowerRight7_MASK)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT7_YEvalLowerRight7_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT7_YEvalLowerRight7_SHIFT (16U)
#define IRIS_MVPL_SIG0_EVALLOWERRIGHT7_YEvalLowerRight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_EVALLOWERRIGHT7_YEvalLowerRight7_SHIFT)) & IRIS_MVPL_SIG0_EVALLOWERRIGHT7_YEvalLowerRight7_MASK)

/*! @name SIG0_SIGCRCREDREF7 - Reference signature of red channel for evaluation window 7. */
#define IRIS_MVPL_SIG0_SIGCRCREDREF7_SigCRCRedRef7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCREDREF7_SigCRCRedRef7_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCREDREF7_SigCRCRedRef7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCREDREF7_SigCRCRedRef7_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCREDREF7_SigCRCRedRef7_MASK)

/*! @name SIG0_SIGCRCGREENREF7 - Reference signature of green channel for evaluation window 7. */
#define IRIS_MVPL_SIG0_SIGCRCGREENREF7_SigCRCGreenRef7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF7_SigCRCGreenRef7_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREENREF7_SigCRCGreenRef7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREENREF7_SigCRCGreenRef7_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREENREF7_SigCRCGreenRef7_MASK)

/*! @name SIG0_SIGCRCBLUEREF7 - Reference signature of blue channel for evaluation window 7. */
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF7_SigCRCBlueRef7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF7_SigCRCBlueRef7_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUEREF7_SigCRCBlueRef7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUEREF7_SigCRCBlueRef7_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUEREF7_SigCRCBlueRef7_MASK)

/*! @name SIG0_SIGCRCRED7 - Measured signature of red channel for evaluation window 7. */
#define IRIS_MVPL_SIG0_SIGCRCRED7_SigCRCRed7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCRED7_SigCRCRed7_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCRED7_SigCRCRed7(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCRED7_SigCRCRed7_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCRED7_SigCRCRed7_MASK)

/*! @name SIG0_SIGCRCGREEN7 - Measured signature of green channel for evaluation window 7. */
#define IRIS_MVPL_SIG0_SIGCRCGREEN7_SigCRCGreen7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCGREEN7_SigCRCGreen7_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCGREEN7_SigCRCGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCGREEN7_SigCRCGreen7_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCGREEN7_SigCRCGreen7_MASK)

/*! @name SIG0_SIGCRCBLUE7 - Measured signature of blue channel for evaluation window 7. */
#define IRIS_MVPL_SIG0_SIGCRCBLUE7_SigCRCBlue7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG0_SIGCRCBLUE7_SigCRCBlue7_SHIFT (0U)
#define IRIS_MVPL_SIG0_SIGCRCBLUE7_SigCRCBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SIGCRCBLUE7_SigCRCBlue7_SHIFT)) & IRIS_MVPL_SIG0_SIGCRCBLUE7_SigCRCBlue7_MASK)

/*! @name SIG0_SHADOWLOAD - Shadow load control register. */
#define IRIS_MVPL_SIG0_SHADOWLOAD_ShdLdReq_MASK  (0xFFU)
#define IRIS_MVPL_SIG0_SHADOWLOAD_ShdLdReq_SHIFT (0U)
#define IRIS_MVPL_SIG0_SHADOWLOAD_ShdLdReq(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SHADOWLOAD_ShdLdReq_SHIFT)) & IRIS_MVPL_SIG0_SHADOWLOAD_ShdLdReq_MASK)

/*! @name SIG0_CONTINUOUSMODE - Signature operation mode control. */
#define IRIS_MVPL_SIG0_CONTINUOUSMODE_EnCont_MASK (0x1U)
#define IRIS_MVPL_SIG0_CONTINUOUSMODE_EnCont_SHIFT (0U)
#define IRIS_MVPL_SIG0_CONTINUOUSMODE_EnCont(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_CONTINUOUSMODE_EnCont_SHIFT)) & IRIS_MVPL_SIG0_CONTINUOUSMODE_EnCont_MASK)

/*! @name SIG0_SOFTWAREKICK - Signature measurement trigger. */
#define IRIS_MVPL_SIG0_SOFTWAREKICK_Kick_MASK    (0x1U)
#define IRIS_MVPL_SIG0_SOFTWAREKICK_Kick_SHIFT   (0U)
#define IRIS_MVPL_SIG0_SOFTWAREKICK_Kick(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_SOFTWAREKICK_Kick_SHIFT)) & IRIS_MVPL_SIG0_SOFTWAREKICK_Kick_MASK)

/*! @name SIG0_STATUS - Module status. */
#define IRIS_MVPL_SIG0_STATUS_StsSigError_MASK   (0xFFU)
#define IRIS_MVPL_SIG0_STATUS_StsSigError_SHIFT  (0U)
#define IRIS_MVPL_SIG0_STATUS_StsSigError(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_STATUS_StsSigError_SHIFT)) & IRIS_MVPL_SIG0_STATUS_StsSigError_MASK)
#define IRIS_MVPL_SIG0_STATUS_StsSigValid_MASK   (0x10000U)
#define IRIS_MVPL_SIG0_STATUS_StsSigValid_SHIFT  (16U)
#define IRIS_MVPL_SIG0_STATUS_StsSigValid(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_STATUS_StsSigValid_SHIFT)) & IRIS_MVPL_SIG0_STATUS_StsSigValid_MASK)
#define IRIS_MVPL_SIG0_STATUS_StsSigIdle_MASK    (0x100000U)
#define IRIS_MVPL_SIG0_STATUS_StsSigIdle_SHIFT   (20U)
#define IRIS_MVPL_SIG0_STATUS_StsSigIdle(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG0_STATUS_StsSigIdle_SHIFT)) & IRIS_MVPL_SIG0_STATUS_StsSigIdle_MASK)

/*! @name FRAMEGEN1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FRAMEGEN1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FRAMEGEN1_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FRAMEGEN1_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FRAMEGEN1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FRAMEGEN1_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FRAMEGEN1_FGSTCTRL - FrameGen Static Control Register */
#define IRIS_MVPL_FRAMEGEN1_FGSTCTRL_ShdEn_MASK  (0x1U)
#define IRIS_MVPL_FRAMEGEN1_FGSTCTRL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGSTCTRL_ShdEn(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSTCTRL_ShdEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSTCTRL_ShdEn_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGSTCTRL_FgSyncMode_MASK (0x6U)
#define IRIS_MVPL_FRAMEGEN1_FGSTCTRL_FgSyncMode_SHIFT (1U)
#define IRIS_MVPL_FRAMEGEN1_FGSTCTRL_FgSyncMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSTCTRL_FgSyncMode_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSTCTRL_FgSyncMode_MASK)

/*! @name FRAMEGEN1_HTCFG1 - FrameGen Horizontal Timing Config Register 1 */
#define IRIS_MVPL_FRAMEGEN1_HTCFG1_Hact_MASK     (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_HTCFG1_Hact_SHIFT    (0U)
#define IRIS_MVPL_FRAMEGEN1_HTCFG1_Hact(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_HTCFG1_Hact_SHIFT)) & IRIS_MVPL_FRAMEGEN1_HTCFG1_Hact_MASK)
#define IRIS_MVPL_FRAMEGEN1_HTCFG1_Htotal_MASK   (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN1_HTCFG1_Htotal_SHIFT  (16U)
#define IRIS_MVPL_FRAMEGEN1_HTCFG1_Htotal(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_HTCFG1_Htotal_SHIFT)) & IRIS_MVPL_FRAMEGEN1_HTCFG1_Htotal_MASK)

/*! @name FRAMEGEN1_HTCFG2 - FrameGen Horizontal Timing Config Register 2 */
#define IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsync_MASK    (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsync_SHIFT   (0U)
#define IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsync(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsync_SHIFT)) & IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsync_MASK)
#define IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsbp_MASK     (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsbp_SHIFT    (16U)
#define IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsbp(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsbp_SHIFT)) & IRIS_MVPL_FRAMEGEN1_HTCFG2_Hsbp_MASK)
#define IRIS_MVPL_FRAMEGEN1_HTCFG2_HsEn_MASK     (0x80000000U)
#define IRIS_MVPL_FRAMEGEN1_HTCFG2_HsEn_SHIFT    (31U)
#define IRIS_MVPL_FRAMEGEN1_HTCFG2_HsEn(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_HTCFG2_HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_HTCFG2_HsEn_MASK)

/*! @name FRAMEGEN1_VTCFG1 - FrameGen Vertical Timing Config Register 1 */
#define IRIS_MVPL_FRAMEGEN1_VTCFG1_Vact_MASK     (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_VTCFG1_Vact_SHIFT    (0U)
#define IRIS_MVPL_FRAMEGEN1_VTCFG1_Vact(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_VTCFG1_Vact_SHIFT)) & IRIS_MVPL_FRAMEGEN1_VTCFG1_Vact_MASK)
#define IRIS_MVPL_FRAMEGEN1_VTCFG1_Vtotal_MASK   (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN1_VTCFG1_Vtotal_SHIFT  (16U)
#define IRIS_MVPL_FRAMEGEN1_VTCFG1_Vtotal(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_VTCFG1_Vtotal_SHIFT)) & IRIS_MVPL_FRAMEGEN1_VTCFG1_Vtotal_MASK)

/*! @name FRAMEGEN1_VTCFG2 - FrameGen Vertical Timing Config Register 2 */
#define IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsync_MASK    (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsync_SHIFT   (0U)
#define IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsync(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsync_SHIFT)) & IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsync_MASK)
#define IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsbp_MASK     (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsbp_SHIFT    (16U)
#define IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsbp(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsbp_SHIFT)) & IRIS_MVPL_FRAMEGEN1_VTCFG2_Vsbp_MASK)
#define IRIS_MVPL_FRAMEGEN1_VTCFG2_VsEn_MASK     (0x80000000U)
#define IRIS_MVPL_FRAMEGEN1_VTCFG2_VsEn_SHIFT    (31U)
#define IRIS_MVPL_FRAMEGEN1_VTCFG2_VsEn(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_VTCFG2_VsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_VTCFG2_VsEn_MASK)

/*! @name FRAMEGEN1_INT0CONFIG - Coordinates of the trigger point for generation of the Int0 interrupt signal */
#define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Col_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Col_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Col_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Col_MASK)
#define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0HsEn_MASK (0x8000U)
#define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0HsEn_SHIFT (15U)
#define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0HsEn_MASK)
#define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Row_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Row_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Row_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0Row_MASK)
#define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0En_MASK (0x80000000U)
#define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0En_SHIFT (31U)
#define IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0En_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT0CONFIG_Int0En_MASK)

/*! @name FRAMEGEN1_INT1CONFIG - Coordinates of the trigger point for generation of the Int1 interrupt signal */
#define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Col_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Col_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Col_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Col_MASK)
#define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1HsEn_MASK (0x8000U)
#define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1HsEn_SHIFT (15U)
#define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1HsEn_MASK)
#define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Row_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Row_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Row_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1Row_MASK)
#define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1En_MASK (0x80000000U)
#define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1En_SHIFT (31U)
#define IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1En_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT1CONFIG_Int1En_MASK)

/*! @name FRAMEGEN1_INT2CONFIG - Coordinates of the trigger point for generation of the Int2 interrupt signal */
#define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Col_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Col_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Col_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Col_MASK)
#define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2HsEn_MASK (0x8000U)
#define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2HsEn_SHIFT (15U)
#define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2HsEn_MASK)
#define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Row_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Row_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Row_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2Row_MASK)
#define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2En_MASK (0x80000000U)
#define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2En_SHIFT (31U)
#define IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2En_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT2CONFIG_Int2En_MASK)

/*! @name FRAMEGEN1_INT3CONFIG - Coordinates of the trigger point for generation of the Int3 interrupt signal */
#define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Col_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Col_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Col(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Col_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Col_MASK)
#define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3HsEn_MASK (0x8000U)
#define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3HsEn_SHIFT (15U)
#define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3HsEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3HsEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3HsEn_MASK)
#define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Row_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Row_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Row(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Row_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3Row_MASK)
#define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3En_MASK (0x80000000U)
#define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3En_SHIFT (31U)
#define IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3En_SHIFT)) & IRIS_MVPL_FRAMEGEN1_INT3CONFIG_Int3En_MASK)

/*! @name FRAMEGEN1_PKICKCONFIG - Coordinates of the trigger point for generation of the primary kick signal */
#define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickCol_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickCol_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickCol(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickCol_SHIFT)) & IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickCol_MASK)
#define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickInt0En_MASK (0x8000U)
#define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickInt0En_SHIFT (15U)
#define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickInt0En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickInt0En_SHIFT)) & IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickInt0En_MASK)
#define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickRow_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickRow_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickRow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickRow_SHIFT)) & IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickRow_MASK)
#define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickEn_MASK (0x80000000U)
#define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickEn_SHIFT (31U)
#define IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_PKICKCONFIG_PKickEn_MASK)

/*! @name FRAMEGEN1_SKICKCONFIG - Coordinates of the trigger point for generation of the secondary kick signal */
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickCol_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickCol_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickCol(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickCol_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickCol_MASK)
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickInt1En_MASK (0x8000U)
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickInt1En_SHIFT (15U)
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickInt1En(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickInt1En_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickInt1En_MASK)
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickRow_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickRow_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickRow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickRow_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickRow_MASK)
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickTrig_MASK (0x40000000U)
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickTrig_SHIFT (30U)
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickTrig(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickTrig_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickTrig_MASK)
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickEn_MASK (0x80000000U)
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickEn_SHIFT (31U)
#define IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SKICKCONFIG_SKickEn_MASK)

/*! @name FRAMEGEN1_SECSTATCONFIG - Configuration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register. */
#define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevGoodFrames_MASK (0xFU)
#define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevGoodFrames_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevGoodFrames(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevGoodFrames_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevGoodFrames_MASK)
#define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevBadFrames_MASK (0xF0U)
#define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevBadFrames_SHIFT (4U)
#define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevBadFrames(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevBadFrames_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevBadFrames_MASK)
#define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevSkewInRange_MASK (0xF00U)
#define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevSkewInRange_SHIFT (8U)
#define IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevSkewInRange(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevSkewInRange_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SECSTATCONFIG_LevSkewInRange_MASK)

/*! @name FRAMEGEN1_FGSRCR1 - FrameGen Skew Regulation Control Register 1. */
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREn_MASK    (0x1U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREn_SHIFT   (0U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREn(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREn_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRMode_MASK  (0x6U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRMode_SHIFT (1U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRMode(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRMode_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRMode_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRAdj_MASK   (0x8U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRAdj_SHIFT  (3U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRAdj(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRAdj_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRAdj_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREven_MASK  (0x10U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREven_SHIFT (4U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREven(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREven_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREven_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRFastSync_MASK (0x20U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRFastSync_SHIFT (5U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRFastSync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRFastSync_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRFastSync_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQAlign_MASK (0x40U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQAlign_SHIFT (6U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQAlign(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQAlign_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQAlign_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQVal_MASK  (0x180U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQVal_SHIFT (7U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQVal(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQVal_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRQVal_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRDbgDisp_MASK (0x10000U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRDbgDisp_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRDbgDisp(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRDbgDisp_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SRDbgDisp_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_MASK (0x20000U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_MASK)

/*! @name FRAMEGEN1_FGSRCR2 - FrameGen Skew Regulation Control Register 2 */
#define IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMin_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMin_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMin(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMin_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMin_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMax_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMax_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMax_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR2_HTotalMax_MASK)

/*! @name FRAMEGEN1_FGSRCR3 - FrameGen Skew Regulation Control Register 3 */
#define IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMin_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMin_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMin(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMin_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMin_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMax_MASK (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMax_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMax_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR3_VTotalMax_MASK)

/*! @name FRAMEGEN1_FGSRCR4 - FrameGen Skew Regulation Control Register 4 */
#define IRIS_MVPL_FRAMEGEN1_FGSRCR4_TargetSkew_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR4_TargetSkew_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR4_TargetSkew(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR4_TargetSkew_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR4_TargetSkew_MASK)

/*! @name FRAMEGEN1_FGSRCR5 - FrameGen Skew Regulation Control Register 5 */
#define IRIS_MVPL_FRAMEGEN1_FGSRCR5_SyncRangeLow_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR5_SyncRangeLow_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR5_SyncRangeLow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR5_SyncRangeLow_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR5_SyncRangeLow_MASK)

/*! @name FRAMEGEN1_FGSRCR6 - FrameGen Skew Regulation Control Register 6 */
#define IRIS_MVPL_FRAMEGEN1_FGSRCR6_SyncRangeHigh_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR6_SyncRangeHigh_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGSRCR6_SyncRangeHigh(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR6_SyncRangeHigh_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRCR6_SyncRangeHigh_MASK)

/*! @name FRAMEGEN1_FGKSDR - FrameGen Kick System Debug Register */
#define IRIS_MVPL_FRAMEGEN1_FGKSDR_PCntCplMax_MASK (0x7U)
#define IRIS_MVPL_FRAMEGEN1_FGKSDR_PCntCplMax_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGKSDR_PCntCplMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGKSDR_PCntCplMax_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGKSDR_PCntCplMax_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGKSDR_SCntCplMax_MASK (0x70000U)
#define IRIS_MVPL_FRAMEGEN1_FGKSDR_SCntCplMax_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN1_FGKSDR_SCntCplMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGKSDR_SCntCplMax_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGKSDR_SCntCplMax_MASK)

/*! @name FRAMEGEN1_PACFG - FrameGen Primary Area Config Register 1 (shadowed) */
#define IRIS_MVPL_FRAMEGEN1_PACFG_Pstartx_MASK   (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_PACFG_Pstartx_SHIFT  (0U)
#define IRIS_MVPL_FRAMEGEN1_PACFG_Pstartx(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_PACFG_Pstartx_SHIFT)) & IRIS_MVPL_FRAMEGEN1_PACFG_Pstartx_MASK)
#define IRIS_MVPL_FRAMEGEN1_PACFG_Pstarty_MASK   (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN1_PACFG_Pstarty_SHIFT  (16U)
#define IRIS_MVPL_FRAMEGEN1_PACFG_Pstarty(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_PACFG_Pstarty_SHIFT)) & IRIS_MVPL_FRAMEGEN1_PACFG_Pstarty_MASK)

/*! @name FRAMEGEN1_SACFG - FrameGen Secondary Area Config Register 1 (shadowed) */
#define IRIS_MVPL_FRAMEGEN1_SACFG_Sstartx_MASK   (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_SACFG_Sstartx_SHIFT  (0U)
#define IRIS_MVPL_FRAMEGEN1_SACFG_Sstartx(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SACFG_Sstartx_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SACFG_Sstartx_MASK)
#define IRIS_MVPL_FRAMEGEN1_SACFG_Sstarty_MASK   (0x3FFF0000U)
#define IRIS_MVPL_FRAMEGEN1_SACFG_Sstarty_SHIFT  (16U)
#define IRIS_MVPL_FRAMEGEN1_SACFG_Sstarty(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_SACFG_Sstarty_SHIFT)) & IRIS_MVPL_FRAMEGEN1_SACFG_Sstarty_MASK)

/*! @name FRAMEGEN1_FGINCTRL - FrameGen Input Control Register (shadowed) */
#define IRIS_MVPL_FRAMEGEN1_FGINCTRL_FgDm_MASK   (0x7U)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRL_FgDm_SHIFT  (0U)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRL_FgDm(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGINCTRL_FgDm_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGINCTRL_FgDm_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnPrimAlpha_MASK (0x8U)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnPrimAlpha_SHIFT (3U)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnPrimAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnPrimAlpha_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnPrimAlpha_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnSecAlpha_MASK (0x10U)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnSecAlpha_SHIFT (4U)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnSecAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnSecAlpha_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGINCTRL_EnSecAlpha_MASK)

/*! @name FRAMEGEN1_FGINCTRLPANIC - FrameGen Input Control Panic Register (shadowed) */
#define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_FgDmPanic_MASK (0x7U)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_FgDmPanic_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_FgDmPanic(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_FgDmPanic_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_FgDmPanic_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnPrimAlphaPanic_MASK (0x8U)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnPrimAlphaPanic_SHIFT (3U)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnPrimAlphaPanic(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnPrimAlphaPanic_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnPrimAlphaPanic_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnSecAlphaPanic_MASK (0x10U)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnSecAlphaPanic_SHIFT (4U)
#define IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnSecAlphaPanic(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnSecAlphaPanic_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGINCTRLPANIC_EnSecAlphaPanic_MASK)

/*! @name FRAMEGEN1_FGCCR - FrameGen Constant Color Register (shadowed) */
#define IRIS_MVPL_FRAMEGEN1_FGCCR_CcBlue_MASK    (0x3FFU)
#define IRIS_MVPL_FRAMEGEN1_FGCCR_CcBlue_SHIFT   (0U)
#define IRIS_MVPL_FRAMEGEN1_FGCCR_CcBlue(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCCR_CcBlue_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCCR_CcBlue_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGCCR_CcGreen_MASK   (0xFFC00U)
#define IRIS_MVPL_FRAMEGEN1_FGCCR_CcGreen_SHIFT  (10U)
#define IRIS_MVPL_FRAMEGEN1_FGCCR_CcGreen(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCCR_CcGreen_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCCR_CcGreen_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGCCR_CcRed_MASK     (0x3FF00000U)
#define IRIS_MVPL_FRAMEGEN1_FGCCR_CcRed_SHIFT    (20U)
#define IRIS_MVPL_FRAMEGEN1_FGCCR_CcRed(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCCR_CcRed_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCCR_CcRed_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGCCR_CcAlpha_MASK   (0x40000000U)
#define IRIS_MVPL_FRAMEGEN1_FGCCR_CcAlpha_SHIFT  (30U)
#define IRIS_MVPL_FRAMEGEN1_FGCCR_CcAlpha(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCCR_CcAlpha_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCCR_CcAlpha_MASK)

/*! @name FRAMEGEN1_FGENABLE - FrameGen Enable Register */
#define IRIS_MVPL_FRAMEGEN1_FGENABLE_FgEn_MASK   (0x1U)
#define IRIS_MVPL_FRAMEGEN1_FGENABLE_FgEn_SHIFT  (0U)
#define IRIS_MVPL_FRAMEGEN1_FGENABLE_FgEn(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGENABLE_FgEn_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGENABLE_FgEn_MASK)

/*! @name FRAMEGEN1_FGSLR - FrameGen Shadow Load Register */
#define IRIS_MVPL_FRAMEGEN1_FGSLR_ShdTokGen_MASK (0x1U)
#define IRIS_MVPL_FRAMEGEN1_FGSLR_ShdTokGen_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGSLR_ShdTokGen(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSLR_ShdTokGen_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSLR_ShdTokGen_MASK)

/*! @name FRAMEGEN1_FGENSTS - FrameGen Enable Status Register */
#define IRIS_MVPL_FRAMEGEN1_FGENSTS_EnSts_MASK   (0x1U)
#define IRIS_MVPL_FRAMEGEN1_FGENSTS_EnSts_SHIFT  (0U)
#define IRIS_MVPL_FRAMEGEN1_FGENSTS_EnSts(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGENSTS_EnSts_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGENSTS_EnSts_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGENSTS_PanicStat_MASK (0x2U)
#define IRIS_MVPL_FRAMEGEN1_FGENSTS_PanicStat_SHIFT (1U)
#define IRIS_MVPL_FRAMEGEN1_FGENSTS_PanicStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGENSTS_PanicStat_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGENSTS_PanicStat_MASK)

/*! @name FRAMEGEN1_FGTIMESTAMP - Time stamp status. */
#define IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_LineIndex_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_LineIndex_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_LineIndex(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_LineIndex_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_LineIndex_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_FrameIndex_MASK (0xFFFFC000U)
#define IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_FrameIndex_SHIFT (14U)
#define IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_FrameIndex(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_FrameIndex_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGTIMESTAMP_FrameIndex_MASK)

/*! @name FRAMEGEN1_FGCHSTAT - FrameGen Channel Status Register */
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PFifoEmpty_MASK (0x1U)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PFifoEmpty_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PFifoEmpty(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PFifoEmpty_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PFifoEmpty_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PrimSyncStat_MASK (0x100U)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PrimSyncStat_SHIFT (8U)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PrimSyncStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PrimSyncStat_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCHSTAT_PrimSyncStat_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SFifoEmpty_MASK (0x10000U)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SFifoEmpty_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SFifoEmpty(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SFifoEmpty_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SFifoEmpty_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SkewRangeErr_MASK (0x20000U)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SkewRangeErr_SHIFT (17U)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SkewRangeErr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SkewRangeErr_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SkewRangeErr_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SecSyncStat_MASK (0x1000000U)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SecSyncStat_SHIFT (24U)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SecSyncStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SecSyncStat_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCHSTAT_SecSyncStat_MASK)

/*! @name FRAMEGEN1_FGCHSTATCLR - FrameGen Channel Status Clear Register */
#define IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrPrimStat_MASK (0x1U)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrPrimStat_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrPrimStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrPrimStat_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrPrimStat_MASK)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrSecStat_MASK (0x10000U)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrSecStat_SHIFT (16U)
#define IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrSecStat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrSecStat_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGCHSTATCLR_ClrSecStat_MASK)

/*! @name FRAMEGEN1_FGSKEWMON - FrameGen Skew Monitor Register for Secondary Channel Skew Control */
#define IRIS_MVPL_FRAMEGEN1_FGSKEWMON_SkewMon_MASK (0x1FFFFFFFU)
#define IRIS_MVPL_FRAMEGEN1_FGSKEWMON_SkewMon_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGSKEWMON_SkewMon(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSKEWMON_SkewMon_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSKEWMON_SkewMon_MASK)

/*! @name FRAMEGEN1_FGSFIFOMIN - FrameGen Secondary FIFO Min Fill Register */
#define IRIS_MVPL_FRAMEGEN1_FGSFIFOMIN_SFifoMin_MASK (0xFFFU)
#define IRIS_MVPL_FRAMEGEN1_FGSFIFOMIN_SFifoMin_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGSFIFOMIN_SFifoMin(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSFIFOMIN_SFifoMin_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSFIFOMIN_SFifoMin_MASK)

/*! @name FRAMEGEN1_FGSFIFOMAX - FrameGen Secondary FIFO Max Fill Register */
#define IRIS_MVPL_FRAMEGEN1_FGSFIFOMAX_SFifoMax_MASK (0xFFFU)
#define IRIS_MVPL_FRAMEGEN1_FGSFIFOMAX_SFifoMax_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGSFIFOMAX_SFifoMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSFIFOMAX_SFifoMax_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSFIFOMAX_SFifoMax_MASK)

/*! @name FRAMEGEN1_FGSFIFOFILLCLR - FrameGen Secondary FIFO Fill Clear Register */
#define IRIS_MVPL_FRAMEGEN1_FGSFIFOFILLCLR_SFifoFillClr_MASK (0x1U)
#define IRIS_MVPL_FRAMEGEN1_FGSFIFOFILLCLR_SFifoFillClr_SHIFT (0U)
#define IRIS_MVPL_FRAMEGEN1_FGSFIFOFILLCLR_SFifoFillClr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSFIFOFILLCLR_SFifoFillClr_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSFIFOFILLCLR_SFifoFillClr_MASK)

/*! @name FRAMEGEN1_FGSREPD - FrameGen Skew Regulation ExtraPolation Debug Register */
#define IRIS_MVPL_FRAMEGEN1_FGSREPD_EpVal_MASK   (0x1FFFFFFFU)
#define IRIS_MVPL_FRAMEGEN1_FGSREPD_EpVal_SHIFT  (0U)
#define IRIS_MVPL_FRAMEGEN1_FGSREPD_EpVal(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSREPD_EpVal_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSREPD_EpVal_MASK)

/*! @name FRAMEGEN1_FGSRFTD - FrameGen Skew Regulation Frame Total Debug Register */
#define IRIS_MVPL_FRAMEGEN1_FGSRFTD_FrTot_MASK   (0xFFFFFFFU)
#define IRIS_MVPL_FRAMEGEN1_FGSRFTD_FrTot_SHIFT  (0U)
#define IRIS_MVPL_FRAMEGEN1_FGSRFTD_FrTot(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRFTD_FrTot_SHIFT)) & IRIS_MVPL_FRAMEGEN1_FGSRFTD_FrTot_MASK)

/*! @name MATRIX1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_MATRIX1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_MATRIX1_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_MATRIX1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX1_LOCKUNLOCK_LockUnlock_MASK)

/*! @name MATRIX1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_MATRIX1_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_MATRIX1_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_MATRIX1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX1_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_MATRIX1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_MATRIX1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_MATRIX1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX1_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_MATRIX1_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_MATRIX1_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_MATRIX1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX1_LOCKSTATUS_FreezeStatus_MASK)

/*! @name MATRIX1_STATICCONTROL - Color Matrix static control register */
#define IRIS_MVPL_MATRIX1_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_MATRIX1_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_MATRIX1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_MATRIX1_STATICCONTROL_ShdEn_MASK)

/*! @name MATRIX1_CONTROL - Color Matrix control register */
#define IRIS_MVPL_MATRIX1_CONTROL_MODE_MASK      (0x3U)
#define IRIS_MVPL_MATRIX1_CONTROL_MODE_SHIFT     (0U)
#define IRIS_MVPL_MATRIX1_CONTROL_MODE(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_CONTROL_MODE_SHIFT)) & IRIS_MVPL_MATRIX1_CONTROL_MODE_MASK)
#define IRIS_MVPL_MATRIX1_CONTROL_AlphaMask_MASK (0x10U)
#define IRIS_MVPL_MATRIX1_CONTROL_AlphaMask_SHIFT (4U)
#define IRIS_MVPL_MATRIX1_CONTROL_AlphaMask(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_MATRIX1_CONTROL_AlphaMask_MASK)
#define IRIS_MVPL_MATRIX1_CONTROL_AlphaInvert_MASK (0x20U)
#define IRIS_MVPL_MATRIX1_CONTROL_AlphaInvert_SHIFT (5U)
#define IRIS_MVPL_MATRIX1_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_MATRIX1_CONTROL_AlphaInvert_MASK)

/*! @name MATRIX1_RED0 - Matrix values for calculation of the red output value. */
#define IRIS_MVPL_MATRIX1_RED0_A11_MASK          (0x1FFFU)
#define IRIS_MVPL_MATRIX1_RED0_A11_SHIFT         (0U)
#define IRIS_MVPL_MATRIX1_RED0_A11(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_RED0_A11_SHIFT)) & IRIS_MVPL_MATRIX1_RED0_A11_MASK)
#define IRIS_MVPL_MATRIX1_RED0_A12_MASK          (0x1FFF0000U)
#define IRIS_MVPL_MATRIX1_RED0_A12_SHIFT         (16U)
#define IRIS_MVPL_MATRIX1_RED0_A12(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_RED0_A12_SHIFT)) & IRIS_MVPL_MATRIX1_RED0_A12_MASK)

/*! @name MATRIX1_RED1 - Matrix values for calculation of the red output value. */
#define IRIS_MVPL_MATRIX1_RED1_A13_MASK          (0x1FFFU)
#define IRIS_MVPL_MATRIX1_RED1_A13_SHIFT         (0U)
#define IRIS_MVPL_MATRIX1_RED1_A13(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_RED1_A13_SHIFT)) & IRIS_MVPL_MATRIX1_RED1_A13_MASK)
#define IRIS_MVPL_MATRIX1_RED1_A14_MASK          (0x1FFF0000U)
#define IRIS_MVPL_MATRIX1_RED1_A14_SHIFT         (16U)
#define IRIS_MVPL_MATRIX1_RED1_A14(x)            (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_RED1_A14_SHIFT)) & IRIS_MVPL_MATRIX1_RED1_A14_MASK)

/*! @name MATRIX1_GREEN0 - Matrix values for calculation of the green output value. */
#define IRIS_MVPL_MATRIX1_GREEN0_A21_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX1_GREEN0_A21_SHIFT       (0U)
#define IRIS_MVPL_MATRIX1_GREEN0_A21(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_GREEN0_A21_SHIFT)) & IRIS_MVPL_MATRIX1_GREEN0_A21_MASK)
#define IRIS_MVPL_MATRIX1_GREEN0_A22_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX1_GREEN0_A22_SHIFT       (16U)
#define IRIS_MVPL_MATRIX1_GREEN0_A22(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_GREEN0_A22_SHIFT)) & IRIS_MVPL_MATRIX1_GREEN0_A22_MASK)

/*! @name MATRIX1_GREEN1 - Matrix values for calculation of the green output value. */
#define IRIS_MVPL_MATRIX1_GREEN1_A23_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX1_GREEN1_A23_SHIFT       (0U)
#define IRIS_MVPL_MATRIX1_GREEN1_A23(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_GREEN1_A23_SHIFT)) & IRIS_MVPL_MATRIX1_GREEN1_A23_MASK)
#define IRIS_MVPL_MATRIX1_GREEN1_A24_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX1_GREEN1_A24_SHIFT       (16U)
#define IRIS_MVPL_MATRIX1_GREEN1_A24(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_GREEN1_A24_SHIFT)) & IRIS_MVPL_MATRIX1_GREEN1_A24_MASK)

/*! @name MATRIX1_BLUE0 - Matrix values for calculation of the blue output value. */
#define IRIS_MVPL_MATRIX1_BLUE0_A31_MASK         (0x1FFFU)
#define IRIS_MVPL_MATRIX1_BLUE0_A31_SHIFT        (0U)
#define IRIS_MVPL_MATRIX1_BLUE0_A31(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_BLUE0_A31_SHIFT)) & IRIS_MVPL_MATRIX1_BLUE0_A31_MASK)
#define IRIS_MVPL_MATRIX1_BLUE0_A32_MASK         (0x1FFF0000U)
#define IRIS_MVPL_MATRIX1_BLUE0_A32_SHIFT        (16U)
#define IRIS_MVPL_MATRIX1_BLUE0_A32(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_BLUE0_A32_SHIFT)) & IRIS_MVPL_MATRIX1_BLUE0_A32_MASK)

/*! @name MATRIX1_BLUE1 - Matrix values for calculation of the blue output value. */
#define IRIS_MVPL_MATRIX1_BLUE1_A33_MASK         (0x1FFFU)
#define IRIS_MVPL_MATRIX1_BLUE1_A33_SHIFT        (0U)
#define IRIS_MVPL_MATRIX1_BLUE1_A33(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_BLUE1_A33_SHIFT)) & IRIS_MVPL_MATRIX1_BLUE1_A33_MASK)
#define IRIS_MVPL_MATRIX1_BLUE1_A34_MASK         (0x1FFF0000U)
#define IRIS_MVPL_MATRIX1_BLUE1_A34_SHIFT        (16U)
#define IRIS_MVPL_MATRIX1_BLUE1_A34(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_BLUE1_A34_SHIFT)) & IRIS_MVPL_MATRIX1_BLUE1_A34_MASK)

/*! @name MATRIX1_ALPHA0 - Matrix values for calculation of the alpha output value. */
#define IRIS_MVPL_MATRIX1_ALPHA0_A41_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX1_ALPHA0_A41_SHIFT       (0U)
#define IRIS_MVPL_MATRIX1_ALPHA0_A41(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_ALPHA0_A41_SHIFT)) & IRIS_MVPL_MATRIX1_ALPHA0_A41_MASK)
#define IRIS_MVPL_MATRIX1_ALPHA0_A42_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX1_ALPHA0_A42_SHIFT       (16U)
#define IRIS_MVPL_MATRIX1_ALPHA0_A42(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_ALPHA0_A42_SHIFT)) & IRIS_MVPL_MATRIX1_ALPHA0_A42_MASK)

/*! @name MATRIX1_ALPHA1 - Matrix values for calculation of the alpha output value. */
#define IRIS_MVPL_MATRIX1_ALPHA1_A43_MASK        (0x1FFFU)
#define IRIS_MVPL_MATRIX1_ALPHA1_A43_SHIFT       (0U)
#define IRIS_MVPL_MATRIX1_ALPHA1_A43(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_ALPHA1_A43_SHIFT)) & IRIS_MVPL_MATRIX1_ALPHA1_A43_MASK)
#define IRIS_MVPL_MATRIX1_ALPHA1_A44_MASK        (0x1FFF0000U)
#define IRIS_MVPL_MATRIX1_ALPHA1_A44_SHIFT       (16U)
#define IRIS_MVPL_MATRIX1_ALPHA1_A44(x)          (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_ALPHA1_A44_SHIFT)) & IRIS_MVPL_MATRIX1_ALPHA1_A44_MASK)

/*! @name MATRIX1_OFFSETVECTOR0 - Offset vectors for red and green output. */
#define IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C1_MASK  (0x1FFFU)
#define IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C1_SHIFT (0U)
#define IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C1(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C1_SHIFT)) & IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C1_MASK)
#define IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C2_MASK  (0x1FFF0000U)
#define IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C2_SHIFT (16U)
#define IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C2(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C2_SHIFT)) & IRIS_MVPL_MATRIX1_OFFSETVECTOR0_C2_MASK)

/*! @name MATRIX1_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */
#define IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C3_MASK  (0x1FFFU)
#define IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C3_SHIFT (0U)
#define IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C3(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C3_SHIFT)) & IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C3_MASK)
#define IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C4_MASK  (0x1FFF0000U)
#define IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C4_SHIFT (16U)
#define IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C4(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C4_SHIFT)) & IRIS_MVPL_MATRIX1_OFFSETVECTOR1_C4_MASK)

/*! @name MATRIX1_LASTCONTROLWORD - Value of last received control word, for debugging. */
#define IRIS_MVPL_MATRIX1_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_MATRIX1_LASTCONTROLWORD_L_VAL_SHIFT (0U)
#define IRIS_MVPL_MATRIX1_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX1_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_MATRIX1_LASTCONTROLWORD_L_VAL_MASK)

/*! @name GAMMACOR1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_GAMMACOR1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_GAMMACOR1_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_GAMMACOR1_LOCKUNLOCK_LockUnlock_MASK)

/*! @name GAMMACOR1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_GAMMACOR1_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_GAMMACOR1_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_GAMMACOR1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_GAMMACOR1_LOCKSTATUS_FreezeStatus_MASK)

/*! @name GAMMACOR1_STATICCONTROL - Static control settings. */
#define IRIS_MVPL_GAMMACOR1_STATICCONTROL_ShdEn_MASK (0x1U)
#define IRIS_MVPL_GAMMACOR1_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR1_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_GAMMACOR1_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_GAMMACOR1_STATICCONTROL_BlueWriteEnable_MASK (0x2U)
#define IRIS_MVPL_GAMMACOR1_STATICCONTROL_BlueWriteEnable_SHIFT (1U)
#define IRIS_MVPL_GAMMACOR1_STATICCONTROL_BlueWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_STATICCONTROL_BlueWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR1_STATICCONTROL_BlueWriteEnable_MASK)
#define IRIS_MVPL_GAMMACOR1_STATICCONTROL_GreenWriteEnable_MASK (0x4U)
#define IRIS_MVPL_GAMMACOR1_STATICCONTROL_GreenWriteEnable_SHIFT (2U)
#define IRIS_MVPL_GAMMACOR1_STATICCONTROL_GreenWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_STATICCONTROL_GreenWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR1_STATICCONTROL_GreenWriteEnable_MASK)
#define IRIS_MVPL_GAMMACOR1_STATICCONTROL_RedWriteEnable_MASK (0x8U)
#define IRIS_MVPL_GAMMACOR1_STATICCONTROL_RedWriteEnable_SHIFT (3U)
#define IRIS_MVPL_GAMMACOR1_STATICCONTROL_RedWriteEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_STATICCONTROL_RedWriteEnable_SHIFT)) & IRIS_MVPL_GAMMACOR1_STATICCONTROL_RedWriteEnable_MASK)

/*! @name GAMMACOR1_LUTSTART - Start values for look-up table programming. */
#define IRIS_MVPL_GAMMACOR1_LUTSTART_StartBlue_MASK (0x3FFU)
#define IRIS_MVPL_GAMMACOR1_LUTSTART_StartBlue_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR1_LUTSTART_StartBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LUTSTART_StartBlue_SHIFT)) & IRIS_MVPL_GAMMACOR1_LUTSTART_StartBlue_MASK)
#define IRIS_MVPL_GAMMACOR1_LUTSTART_StartGreen_MASK (0xFFC00U)
#define IRIS_MVPL_GAMMACOR1_LUTSTART_StartGreen_SHIFT (10U)
#define IRIS_MVPL_GAMMACOR1_LUTSTART_StartGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LUTSTART_StartGreen_SHIFT)) & IRIS_MVPL_GAMMACOR1_LUTSTART_StartGreen_MASK)
#define IRIS_MVPL_GAMMACOR1_LUTSTART_StartRed_MASK (0x3FF00000U)
#define IRIS_MVPL_GAMMACOR1_LUTSTART_StartRed_SHIFT (20U)
#define IRIS_MVPL_GAMMACOR1_LUTSTART_StartRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LUTSTART_StartRed_SHIFT)) & IRIS_MVPL_GAMMACOR1_LUTSTART_StartRed_MASK)

/*! @name GAMMACOR1_LUTDELTAS - Delta values for look-up table programming. */
#define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaBlue_MASK (0x3FFU)
#define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaBlue_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaBlue_SHIFT)) & IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaBlue_MASK)
#define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaGreen_MASK (0xFFC00U)
#define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaGreen_SHIFT (10U)
#define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaGreen_SHIFT)) & IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaGreen_MASK)
#define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaRed_MASK (0x3FF00000U)
#define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaRed_SHIFT (20U)
#define IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaRed_SHIFT)) & IRIS_MVPL_GAMMACOR1_LUTDELTAS_DeltaRed_MASK)

/*! @name GAMMACOR1_CONTROL - Dynamic control settings. */
#define IRIS_MVPL_GAMMACOR1_CONTROL_Mode_MASK    (0x1U)
#define IRIS_MVPL_GAMMACOR1_CONTROL_Mode_SHIFT   (0U)
#define IRIS_MVPL_GAMMACOR1_CONTROL_Mode(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_CONTROL_Mode_SHIFT)) & IRIS_MVPL_GAMMACOR1_CONTROL_Mode_MASK)
#define IRIS_MVPL_GAMMACOR1_CONTROL_AlphaMask_MASK (0x10U)
#define IRIS_MVPL_GAMMACOR1_CONTROL_AlphaMask_SHIFT (4U)
#define IRIS_MVPL_GAMMACOR1_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_GAMMACOR1_CONTROL_AlphaMask_MASK)
#define IRIS_MVPL_GAMMACOR1_CONTROL_AlphaInvert_MASK (0x20U)
#define IRIS_MVPL_GAMMACOR1_CONTROL_AlphaInvert_SHIFT (5U)
#define IRIS_MVPL_GAMMACOR1_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_GAMMACOR1_CONTROL_AlphaInvert_MASK)

/*! @name GAMMACOR1_STATUS - Internal status bits. */
#define IRIS_MVPL_GAMMACOR1_STATUS_WriteTimeout_MASK (0x1U)
#define IRIS_MVPL_GAMMACOR1_STATUS_WriteTimeout_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR1_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_GAMMACOR1_STATUS_WriteTimeout_MASK)

/*! @name GAMMACOR1_LASTCONTROLWORD - Value of last received control word. */
#define IRIS_MVPL_GAMMACOR1_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_GAMMACOR1_LASTCONTROLWORD_L_VAL_SHIFT (0U)
#define IRIS_MVPL_GAMMACOR1_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GAMMACOR1_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_GAMMACOR1_LASTCONTROLWORD_L_VAL_MASK)

/*! @name DITHER1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_DITHER1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DITHER1_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_DITHER1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_DITHER1_LOCKUNLOCK_LockUnlock_MASK)

/*! @name DITHER1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_DITHER1_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_DITHER1_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_DITHER1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_DITHER1_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_DITHER1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_DITHER1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_DITHER1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_DITHER1_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_DITHER1_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_DITHER1_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_DITHER1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_DITHER1_LOCKSTATUS_FreezeStatus_MASK)

/*! @name DITHER1_CONTROL - Dither Unit common control. */
#define IRIS_MVPL_DITHER1_CONTROL_mode_MASK      (0x1U)
#define IRIS_MVPL_DITHER1_CONTROL_mode_SHIFT     (0U)
#define IRIS_MVPL_DITHER1_CONTROL_mode(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_CONTROL_mode_SHIFT)) & IRIS_MVPL_DITHER1_CONTROL_mode_MASK)

/*! @name DITHER1_DITHERCONTROL - Dither Unit processing control. */
#define IRIS_MVPL_DITHER1_DITHERCONTROL_blue_range_select_MASK (0x7U)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_blue_range_select_SHIFT (0U)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_blue_range_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_DITHERCONTROL_blue_range_select_SHIFT)) & IRIS_MVPL_DITHER1_DITHERCONTROL_blue_range_select_MASK)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_green_range_select_MASK (0x70U)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_green_range_select_SHIFT (4U)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_green_range_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_DITHERCONTROL_green_range_select_SHIFT)) & IRIS_MVPL_DITHER1_DITHERCONTROL_green_range_select_MASK)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_red_range_select_MASK (0x700U)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_red_range_select_SHIFT (8U)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_red_range_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_DITHERCONTROL_red_range_select_SHIFT)) & IRIS_MVPL_DITHER1_DITHERCONTROL_red_range_select_MASK)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_offset_select_MASK (0x10000U)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_offset_select_SHIFT (16U)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_offset_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_DITHERCONTROL_offset_select_SHIFT)) & IRIS_MVPL_DITHER1_DITHERCONTROL_offset_select_MASK)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_algo_select_MASK (0x300000U)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_algo_select_SHIFT (20U)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_algo_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_DITHERCONTROL_algo_select_SHIFT)) & IRIS_MVPL_DITHER1_DITHERCONTROL_algo_select_MASK)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_alpha_mode_MASK (0x3000000U)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_alpha_mode_SHIFT (24U)
#define IRIS_MVPL_DITHER1_DITHERCONTROL_alpha_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_DITHERCONTROL_alpha_mode_SHIFT)) & IRIS_MVPL_DITHER1_DITHERCONTROL_alpha_mode_MASK)

/*! @name DITHER1_RELEASE - Dither Unit release. */
#define IRIS_MVPL_DITHER1_RELEASE_subversion_MASK (0xFFU)
#define IRIS_MVPL_DITHER1_RELEASE_subversion_SHIFT (0U)
#define IRIS_MVPL_DITHER1_RELEASE_subversion(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_RELEASE_subversion_SHIFT)) & IRIS_MVPL_DITHER1_RELEASE_subversion_MASK)
#define IRIS_MVPL_DITHER1_RELEASE_version_MASK   (0xFF00U)
#define IRIS_MVPL_DITHER1_RELEASE_version_SHIFT  (8U)
#define IRIS_MVPL_DITHER1_RELEASE_version(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DITHER1_RELEASE_version_SHIFT)) & IRIS_MVPL_DITHER1_RELEASE_version_MASK)

/*! @name TCON1_SSQCNTS - The 64 Sequencer Position Definitions registers define the X/Y scan positions of the sequencers, hold their output value and assign the sequencer to an odd/even field */
#define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQY_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQY_SHIFT (0U)
#define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQY(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQY_SHIFT)) & IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQY_MASK)
#define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_FIELD_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_FIELD_SHIFT (15U)
#define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_FIELD_SHIFT)) & IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_FIELD_MASK)
#define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQX_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQX_SHIFT (16U)
#define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQX(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQX_SHIFT)) & IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_SEQX_MASK)
#define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_OUT_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_OUT_SHIFT (31U)
#define IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_OUT(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_OUT_SHIFT)) & IRIS_MVPL_TCON1_SSQCNTS_SSQCNTS_OUT_MASK)

/*! @name TCON1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_TCON1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON1_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_TCON1_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_TCON1_LOCKUNLOCK_LockUnlock_MASK)

/*! @name TCON1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_TCON1_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_TCON1_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_TCON1_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_TCON1_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_TCON1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_TCON1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_TCON1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_TCON1_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_TCON1_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_TCON1_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_TCON1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_TCON1_LOCKSTATUS_FreezeStatus_MASK)

/*! @name TCON1_SSQCYCLE - This bitfield sets the sequencer cycle length. The value set here -1 is the number of sequencer cycles */
#define IRIS_MVPL_TCON1_SSQCYCLE_SSQCYCLE_MASK   (0x3FU)
#define IRIS_MVPL_TCON1_SSQCYCLE_SSQCYCLE_SHIFT  (0U)
#define IRIS_MVPL_TCON1_SSQCYCLE_SSQCYCLE(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SSQCYCLE_SSQCYCLE_SHIFT)) & IRIS_MVPL_TCON1_SSQCYCLE_SSQCYCLE_MASK)

/*! @name TCON1_SWRESET - TCON Software Reset - Reset all tcon registers except configuration registers. Detailed description in specification document */
#define IRIS_MVPL_TCON1_SWRESET_SWReset_MASK     (0x1U)
#define IRIS_MVPL_TCON1_SWRESET_SWReset_SHIFT    (0U)
#define IRIS_MVPL_TCON1_SWRESET_SWReset(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SWRESET_SWReset_SHIFT)) & IRIS_MVPL_TCON1_SWRESET_SWReset_MASK)
#define IRIS_MVPL_TCON1_SWRESET_EnResetWord_MASK (0xFFF0U)
#define IRIS_MVPL_TCON1_SWRESET_EnResetWord_SHIFT (4U)
#define IRIS_MVPL_TCON1_SWRESET_EnResetWord(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SWRESET_EnResetWord_SHIFT)) & IRIS_MVPL_TCON1_SWRESET_EnResetWord_MASK)
#define IRIS_MVPL_TCON1_SWRESET_ResetWordEnd_MASK (0xFF0000U)
#define IRIS_MVPL_TCON1_SWRESET_ResetWordEnd_SHIFT (16U)
#define IRIS_MVPL_TCON1_SWRESET_ResetWordEnd(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SWRESET_ResetWordEnd_SHIFT)) & IRIS_MVPL_TCON1_SWRESET_ResetWordEnd_MASK)
#define IRIS_MVPL_TCON1_SWRESET_ResetWordStart_MASK (0xFF000000U)
#define IRIS_MVPL_TCON1_SWRESET_ResetWordStart_SHIFT (24U)
#define IRIS_MVPL_TCON1_SWRESET_ResetWordStart(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SWRESET_ResetWordStart_SHIFT)) & IRIS_MVPL_TCON1_SWRESET_ResetWordStart_MASK)

/*! @name TCON1_TCON_CTRL - TCON Control register */
#define IRIS_MVPL_TCON1_TCON_CTRL_ChannelMode_MASK (0x3U)
#define IRIS_MVPL_TCON1_TCON_CTRL_ChannelMode_SHIFT (0U)
#define IRIS_MVPL_TCON1_TCON_CTRL_ChannelMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_TCON_CTRL_ChannelMode_SHIFT)) & IRIS_MVPL_TCON1_TCON_CTRL_ChannelMode_MASK)
#define IRIS_MVPL_TCON1_TCON_CTRL_tcon_sync_MASK (0x4U)
#define IRIS_MVPL_TCON1_TCON_CTRL_tcon_sync_SHIFT (2U)
#define IRIS_MVPL_TCON1_TCON_CTRL_tcon_sync(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_TCON_CTRL_tcon_sync_SHIFT)) & IRIS_MVPL_TCON1_TCON_CTRL_tcon_sync_MASK)
#define IRIS_MVPL_TCON1_TCON_CTRL_Bypass_MASK    (0x8U)
#define IRIS_MVPL_TCON1_TCON_CTRL_Bypass_SHIFT   (3U)
#define IRIS_MVPL_TCON1_TCON_CTRL_Bypass(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_TCON_CTRL_Bypass_SHIFT)) & IRIS_MVPL_TCON1_TCON_CTRL_Bypass_MASK)
#define IRIS_MVPL_TCON1_TCON_CTRL_Inv_Ctrl_MASK  (0xF0U)
#define IRIS_MVPL_TCON1_TCON_CTRL_Inv_Ctrl_SHIFT (4U)
#define IRIS_MVPL_TCON1_TCON_CTRL_Inv_Ctrl(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_TCON_CTRL_Inv_Ctrl_SHIFT)) & IRIS_MVPL_TCON1_TCON_CTRL_Inv_Ctrl_MASK)
#define IRIS_MVPL_TCON1_TCON_CTRL_EnLVDS_MASK    (0x100U)
#define IRIS_MVPL_TCON1_TCON_CTRL_EnLVDS_SHIFT   (8U)
#define IRIS_MVPL_TCON1_TCON_CTRL_EnLVDS(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_TCON_CTRL_EnLVDS_SHIFT)) & IRIS_MVPL_TCON1_TCON_CTRL_EnLVDS_MASK)
#define IRIS_MVPL_TCON1_TCON_CTRL_LVDSMode_MASK  (0x200U)
#define IRIS_MVPL_TCON1_TCON_CTRL_LVDSMode_SHIFT (9U)
#define IRIS_MVPL_TCON1_TCON_CTRL_LVDSMode(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_TCON_CTRL_LVDSMode_SHIFT)) & IRIS_MVPL_TCON1_TCON_CTRL_LVDSMode_MASK)
#define IRIS_MVPL_TCON1_TCON_CTRL_LVDS_Balance_MASK (0x400U)
#define IRIS_MVPL_TCON1_TCON_CTRL_LVDS_Balance_SHIFT (10U)
#define IRIS_MVPL_TCON1_TCON_CTRL_LVDS_Balance(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_TCON_CTRL_LVDS_Balance_SHIFT)) & IRIS_MVPL_TCON1_TCON_CTRL_LVDS_Balance_MASK)
#define IRIS_MVPL_TCON1_TCON_CTRL_LVDS_CLOCK_INV_MASK (0x800U)
#define IRIS_MVPL_TCON1_TCON_CTRL_LVDS_CLOCK_INV_SHIFT (11U)
#define IRIS_MVPL_TCON1_TCON_CTRL_LVDS_CLOCK_INV(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_TCON_CTRL_LVDS_CLOCK_INV_SHIFT)) & IRIS_MVPL_TCON1_TCON_CTRL_LVDS_CLOCK_INV_MASK)
#define IRIS_MVPL_TCON1_TCON_CTRL_MiniLVDS_OpCode_MASK (0x7000U)
#define IRIS_MVPL_TCON1_TCON_CTRL_MiniLVDS_OpCode_SHIFT (12U)
#define IRIS_MVPL_TCON1_TCON_CTRL_MiniLVDS_OpCode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_TCON_CTRL_MiniLVDS_OpCode_SHIFT)) & IRIS_MVPL_TCON1_TCON_CTRL_MiniLVDS_OpCode_MASK)
#define IRIS_MVPL_TCON1_TCON_CTRL_DUAL_SWAP_MASK (0x8000U)
#define IRIS_MVPL_TCON1_TCON_CTRL_DUAL_SWAP_SHIFT (15U)
#define IRIS_MVPL_TCON1_TCON_CTRL_DUAL_SWAP(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_TCON_CTRL_DUAL_SWAP_SHIFT)) & IRIS_MVPL_TCON1_TCON_CTRL_DUAL_SWAP_MASK)
#define IRIS_MVPL_TCON1_TCON_CTRL_SplitPosition_MASK (0x3FFF0000U)
#define IRIS_MVPL_TCON1_TCON_CTRL_SplitPosition_SHIFT (16U)
#define IRIS_MVPL_TCON1_TCON_CTRL_SplitPosition(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_TCON_CTRL_SplitPosition_SHIFT)) & IRIS_MVPL_TCON1_TCON_CTRL_SplitPosition_MASK)

/*! @name TCON1_RSDSINVCTRL - Controls inversion of output polarity when connected IO cells operate in RSDS mode */
#define IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_SHIFT (0U)
#define IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_SHIFT)) & IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_MASK)
#define IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_Dual_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_Dual_SHIFT)) & IRIS_MVPL_TCON1_RSDSINVCTRL_RSDS_Inv_Dual_MASK)

/*! @name TCON1_MAPBIT3_0 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3 */
#define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit0_MASK   (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit0_SHIFT  (0U)
#define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit0(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_MapBit0_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_MapBit0_MASK)
#define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit1_MASK   (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit1_SHIFT  (8U)
#define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit1(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_MapBit1_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_MapBit1_MASK)
#define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit2_MASK   (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit2_SHIFT  (16U)
#define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit2(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_MapBit2_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_MapBit2_MASK)
#define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit3_MASK   (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit3_SHIFT  (24U)
#define IRIS_MVPL_TCON1_MAPBIT3_0_MapBit3(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_MapBit3_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_MapBit3_MASK)

/*! @name TCON1_MAPBIT7_4 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7 */
#define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit4_MASK   (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit4_SHIFT  (0U)
#define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit4(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_MapBit4_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_MapBit4_MASK)
#define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit5_MASK   (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit5_SHIFT  (8U)
#define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit5(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_MapBit5_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_MapBit5_MASK)
#define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit6_MASK   (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit6_SHIFT  (16U)
#define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit6(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_MapBit6_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_MapBit6_MASK)
#define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit7_MASK   (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit7_SHIFT  (24U)
#define IRIS_MVPL_TCON1_MAPBIT7_4_MapBit7(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_MapBit7_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_MapBit7_MASK)

/*! @name TCON1_MAPBIT11_8 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11 */
#define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit8_MASK  (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit8_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit8(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_MapBit8_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_MapBit8_MASK)
#define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit9_MASK  (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit9_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit9(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_MapBit9_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_MapBit9_MASK)
#define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit10_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit10_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit10(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_MapBit10_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_MapBit10_MASK)
#define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit11_MASK (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit11_SHIFT (24U)
#define IRIS_MVPL_TCON1_MAPBIT11_8_MapBit11(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_MapBit11_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_MapBit11_MASK)

/*! @name TCON1_MAPBIT15_12 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15 */
#define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit12_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit12_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit12(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_MapBit12_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_MapBit12_MASK)
#define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit13_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit13_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit13(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_MapBit13_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_MapBit13_MASK)
#define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit14_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit14_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit14(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_MapBit14_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_MapBit14_MASK)
#define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit15_MASK (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit15_SHIFT (24U)
#define IRIS_MVPL_TCON1_MAPBIT15_12_MapBit15(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_MapBit15_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_MapBit15_MASK)

/*! @name TCON1_MAPBIT19_16 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19 */
#define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit16_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit16_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit16(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_MapBit16_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_MapBit16_MASK)
#define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit17_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit17_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit17(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_MapBit17_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_MapBit17_MASK)
#define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit18_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit18_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit18(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_MapBit18_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_MapBit18_MASK)
#define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit19_MASK (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit19_SHIFT (24U)
#define IRIS_MVPL_TCON1_MAPBIT19_16_MapBit19(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_MapBit19_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_MapBit19_MASK)

/*! @name TCON1_MAPBIT23_20 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23 */
#define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit20_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit20_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit20(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_MapBit20_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_MapBit20_MASK)
#define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit21_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit21_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit21(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_MapBit21_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_MapBit21_MASK)
#define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit22_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit22_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit22(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_MapBit22_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_MapBit22_MASK)
#define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit23_MASK (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit23_SHIFT (24U)
#define IRIS_MVPL_TCON1_MAPBIT23_20_MapBit23(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_MapBit23_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_MapBit23_MASK)

/*! @name TCON1_MAPBIT27_24 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27 */
#define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit24_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit24_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit24(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_MapBit24_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_MapBit24_MASK)
#define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit25_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit25_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit25(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_MapBit25_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_MapBit25_MASK)
#define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit26_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit26_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit26(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_MapBit26_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_MapBit26_MASK)
#define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit27_MASK (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit27_SHIFT (24U)
#define IRIS_MVPL_TCON1_MAPBIT27_24_MapBit27(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_MapBit27_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_MapBit27_MASK)

/*! @name TCON1_MAPBIT31_28 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31 */
#define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit28_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit28_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit28(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_MapBit28_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_MapBit28_MASK)
#define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit29_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit29_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit29(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_MapBit29_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_MapBit29_MASK)
#define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit30_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit30_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit30(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_MapBit30_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_MapBit30_MASK)
#define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit31_MASK (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit31_SHIFT (24U)
#define IRIS_MVPL_TCON1_MAPBIT31_28_MapBit31(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_MapBit31_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_MapBit31_MASK)

/*! @name TCON1_MAPBIT34_32 - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34 */
#define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit32_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit32_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit32(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT34_32_MapBit32_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT34_32_MapBit32_MASK)
#define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit33_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit33_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit33(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT34_32_MapBit33_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT34_32_MapBit33_MASK)
#define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit34_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit34_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT34_32_MapBit34(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT34_32_MapBit34_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT34_32_MapBit34_MASK)

/*! @name TCON1_MAPBIT3_0_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3 2nd channel */
#define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit0_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit0_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit0_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit0_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit0_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit1_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit1_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit1_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit1_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit1_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit2_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit2_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit2_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit2_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit2_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit3_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit3_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit3_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit3_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT3_0_DUAL_MapBit3_Dual_MASK)

/*! @name TCON1_MAPBIT7_4_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7 2nd channel */
#define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit4_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit4_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit4_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit4_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit4_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit5_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit5_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit5_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit5_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit5_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit6_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit6_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit6_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit6_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit6_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit7_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit7_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit7_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit7_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT7_4_DUAL_MapBit7_Dual_MASK)

/*! @name TCON1_MAPBIT11_8_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11 2nd channel */
#define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit8_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit8_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit8_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit8_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit8_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit9_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit9_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit9_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit9_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit9_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit10_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit10_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit10_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit10_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit10_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit11_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit11_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit11_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit11_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT11_8_DUAL_MapBit11_Dual_MASK)

/*! @name TCON1_MAPBIT15_12_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15 2nd channel */
#define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit12_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit12_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit12_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit12_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit12_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit13_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit13_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit13_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit13_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit13_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit14_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit14_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit14_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit14_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit14_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit15_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit15_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit15_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit15_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT15_12_DUAL_MapBit15_Dual_MASK)

/*! @name TCON1_MAPBIT19_16_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19 2nd channel */
#define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit16_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit16_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit16_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit16_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit16_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit17_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit17_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit17_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit17_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit17_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit18_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit18_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit18_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit18_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit18_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit19_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit19_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit19_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit19_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT19_16_DUAL_MapBit19_Dual_MASK)

/*! @name TCON1_MAPBIT23_20_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23 2nd channel */
#define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit20_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit20_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit20_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit20_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit20_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit21_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit21_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit21_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit21_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit21_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit22_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit22_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit22_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit22_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit22_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit23_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit23_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit23_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit23_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT23_20_DUAL_MapBit23_Dual_MASK)

/*! @name TCON1_MAPBIT27_24_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27 2nd channel */
#define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit24_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit24_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit24_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit24_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit24_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit25_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit25_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit25_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit25_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit25_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit26_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit26_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit26_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit26_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit26_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit27_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit27_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit27_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit27_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT27_24_DUAL_MapBit27_Dual_MASK)

/*! @name TCON1_MAPBIT31_28_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31 2nd channel */
#define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit28_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit28_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit28_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit28_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit28_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit29_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit29_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit29_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit29_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit29_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit30_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit30_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit30_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit30_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit30_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit31_Dual_MASK (0x3F000000U)
#define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit31_Dual_SHIFT (24U)
#define IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit31_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit31_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT31_28_DUAL_MapBit31_Dual_MASK)

/*! @name TCON1_MAPBIT34_32_DUAL - Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34 2nd channel */
#define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit32_Dual_MASK (0x3FU)
#define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit32_Dual_SHIFT (0U)
#define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit32_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit32_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit32_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit33_Dual_MASK (0x3F00U)
#define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit33_Dual_SHIFT (8U)
#define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit33_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit33_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit33_Dual_MASK)
#define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit34_Dual_MASK (0x3F0000U)
#define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit34_Dual_SHIFT (16U)
#define IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit34_Dual(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit34_Dual_SHIFT)) & IRIS_MVPL_TCON1_MAPBIT34_32_DUAL_MapBit34_Dual_MASK)

/*! @name TCON1_SPG0POSON - Sync pulse generator 0, 'Switch on' position */
#define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_Y0_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_Y0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_Y0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_Y0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_Y0_MASK)
#define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_FIELD0_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_FIELD0_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_FIELD0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_FIELD0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_FIELD0_MASK)
#define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_X0_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_X0_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_X0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_X0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_X0_MASK)
#define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_TOGGLE0_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_TOGGLE0_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_TOGGLE0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_TOGGLE0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSON_SPGPSON_TOGGLE0_MASK)

/*! @name TCON1_SPG0MASKON - The Sequencer Pulse Generator 0 Mask Enable register is used to mask the enable of SPG 0 */
#define IRIS_MVPL_TCON1_SPG0MASKON_SPGMKON0_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG0MASKON_SPGMKON0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG0MASKON_SPGMKON0(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0MASKON_SPGMKON0_SHIFT)) & IRIS_MVPL_TCON1_SPG0MASKON_SPGMKON0_MASK)

/*! @name TCON1_SPG0POSOFF - Sync pulse generator 0, 'Switch off' position */
#define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_Y0_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_Y0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_Y0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_Y0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_Y0_MASK)
#define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_MASK)
#define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_X0_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_X0_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_X0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_X0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_X0_MASK)
#define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT)) & IRIS_MVPL_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK)

/*! @name TCON1_SPG0MASKOFF - The Sequencer Pulse Generator 0 Mask Enable register is used to mask the disable of SPG 0 */
#define IRIS_MVPL_TCON1_SPG0MASKOFF_SPGMKOFF0_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG0MASKOFF_SPGMKOFF0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG0MASKOFF_SPGMKOFF0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG0MASKOFF_SPGMKOFF0_SHIFT)) & IRIS_MVPL_TCON1_SPG0MASKOFF_SPGMKOFF0_MASK)

/*! @name TCON1_SPG1POSON - Sync pulse generator 1, 'Switch on' position */
#define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_Y1_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_Y1_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_Y1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_Y1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_Y1_MASK)
#define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_FIELD1_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_FIELD1_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_FIELD1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_FIELD1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_FIELD1_MASK)
#define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_X1_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_X1_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_X1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_X1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_X1_MASK)
#define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_TOGGLE1_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_TOGGLE1_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_TOGGLE1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_TOGGLE1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSON_SPGPSON_TOGGLE1_MASK)

/*! @name TCON1_SPG1MASKON - The Sequencer Pulse Generator 1 Mask Enable register is used to mask the enable of SPG 1 */
#define IRIS_MVPL_TCON1_SPG1MASKON_SPGMKON1_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG1MASKON_SPGMKON1_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG1MASKON_SPGMKON1(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1MASKON_SPGMKON1_SHIFT)) & IRIS_MVPL_TCON1_SPG1MASKON_SPGMKON1_MASK)

/*! @name TCON1_SPG1POSOFF - Sync pulse generator 1, 'Switch off' position */
#define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_Y1_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_Y1_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_Y1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_Y1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_Y1_MASK)
#define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_MASK)
#define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_X1_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_X1_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_X1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_X1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_X1_MASK)
#define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT)) & IRIS_MVPL_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK)

/*! @name TCON1_SPG1MASKOFF - The Sequencer Pulse Generator 1 Mask Enable register is used to mask the disable of SPG 1 */
#define IRIS_MVPL_TCON1_SPG1MASKOFF_SPGMKOFF1_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG1MASKOFF_SPGMKOFF1_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG1MASKOFF_SPGMKOFF1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG1MASKOFF_SPGMKOFF1_SHIFT)) & IRIS_MVPL_TCON1_SPG1MASKOFF_SPGMKOFF1_MASK)

/*! @name TCON1_SPG2POSON - Sync pulse generator 2, 'Switch on' position */
#define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_Y2_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_Y2_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_Y2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_Y2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_Y2_MASK)
#define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_FIELD2_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_FIELD2_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_FIELD2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_FIELD2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_FIELD2_MASK)
#define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_X2_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_X2_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_X2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_X2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_X2_MASK)
#define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_TOGGLE2_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_TOGGLE2_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_TOGGLE2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_TOGGLE2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSON_SPGPSON_TOGGLE2_MASK)

/*! @name TCON1_SPG2MASKON - The Sequencer Pulse Generator 2 Mask Enable register is used to mask the enable of SPG 2 */
#define IRIS_MVPL_TCON1_SPG2MASKON_SPGMKON2_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG2MASKON_SPGMKON2_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG2MASKON_SPGMKON2(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2MASKON_SPGMKON2_SHIFT)) & IRIS_MVPL_TCON1_SPG2MASKON_SPGMKON2_MASK)

/*! @name TCON1_SPG2POSOFF - Sync pulse generator 2, 'Switch off' position */
#define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_Y2_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_Y2_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_Y2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_Y2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_Y2_MASK)
#define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_MASK)
#define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_X2_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_X2_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_X2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_X2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_X2_MASK)
#define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT)) & IRIS_MVPL_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK)

/*! @name TCON1_SPG2MASKOFF - The Sequencer Pulse Generator 2 Mask Enable register is used to mask the disable of SPG 2 */
#define IRIS_MVPL_TCON1_SPG2MASKOFF_SPGMKOFF2_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG2MASKOFF_SPGMKOFF2_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG2MASKOFF_SPGMKOFF2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG2MASKOFF_SPGMKOFF2_SHIFT)) & IRIS_MVPL_TCON1_SPG2MASKOFF_SPGMKOFF2_MASK)

/*! @name TCON1_SPG3POSON - Sync pulse generator 3, 'Switch on' position */
#define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_Y3_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_Y3_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_Y3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_Y3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_Y3_MASK)
#define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_FIELD3_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_FIELD3_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_FIELD3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_FIELD3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_FIELD3_MASK)
#define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_X3_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_X3_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_X3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_X3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_X3_MASK)
#define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_TOGGLE3_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_TOGGLE3_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_TOGGLE3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_TOGGLE3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSON_SPGPSON_TOGGLE3_MASK)

/*! @name TCON1_SPG3MASKON - The Sequencer Pulse Generator 3 Mask Enable register is used to mask the enable of SPG 3 */
#define IRIS_MVPL_TCON1_SPG3MASKON_SPGMKON3_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG3MASKON_SPGMKON3_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG3MASKON_SPGMKON3(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3MASKON_SPGMKON3_SHIFT)) & IRIS_MVPL_TCON1_SPG3MASKON_SPGMKON3_MASK)

/*! @name TCON1_SPG3POSOFF - Sync pulse generator 3, 'Switch off' position */
#define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_Y3_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_Y3_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_Y3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_Y3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_Y3_MASK)
#define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_MASK)
#define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_X3_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_X3_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_X3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_X3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_X3_MASK)
#define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT)) & IRIS_MVPL_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK)

/*! @name TCON1_SPG3MASKOFF - The Sequencer Pulse Generator 3 Mask Enable register is used to mask the disable of SPG 3 */
#define IRIS_MVPL_TCON1_SPG3MASKOFF_SPGMKOFF3_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG3MASKOFF_SPGMKOFF3_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG3MASKOFF_SPGMKOFF3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG3MASKOFF_SPGMKOFF3_SHIFT)) & IRIS_MVPL_TCON1_SPG3MASKOFF_SPGMKOFF3_MASK)

/*! @name TCON1_SPG4POSON - Sync pulse generator 4, 'Switch on' position */
#define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_Y4_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_Y4_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_Y4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_Y4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_Y4_MASK)
#define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_FIELD4_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_FIELD4_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_FIELD4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_FIELD4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_FIELD4_MASK)
#define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_X4_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_X4_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_X4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_X4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_X4_MASK)
#define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_TOGGLE4_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_TOGGLE4_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_TOGGLE4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_TOGGLE4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSON_SPGPSON_TOGGLE4_MASK)

/*! @name TCON1_SPG4MASKON - The Sequencer Pulse Generator 4 Mask Enable register is used to mask the enable of SPG 4 */
#define IRIS_MVPL_TCON1_SPG4MASKON_SPGMKON4_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG4MASKON_SPGMKON4_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG4MASKON_SPGMKON4(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4MASKON_SPGMKON4_SHIFT)) & IRIS_MVPL_TCON1_SPG4MASKON_SPGMKON4_MASK)

/*! @name TCON1_SPG4POSOFF - Sync pulse generator 4, 'Switch off' position */
#define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_Y4_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_Y4_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_Y4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_Y4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_Y4_MASK)
#define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_MASK)
#define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_X4_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_X4_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_X4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_X4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_X4_MASK)
#define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT)) & IRIS_MVPL_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK)

/*! @name TCON1_SPG4MASKOFF - The Sequencer Pulse Generator 4 Mask Enable register is used to mask the disable of SPG 4 */
#define IRIS_MVPL_TCON1_SPG4MASKOFF_SPGMKOFF4_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG4MASKOFF_SPGMKOFF4_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG4MASKOFF_SPGMKOFF4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG4MASKOFF_SPGMKOFF4_SHIFT)) & IRIS_MVPL_TCON1_SPG4MASKOFF_SPGMKOFF4_MASK)

/*! @name TCON1_SPG5POSON - Sync pulse generator 5, 'Switch on' position */
#define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_Y5_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_Y5_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_Y5(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_Y5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_Y5_MASK)
#define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_FIELD5_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_FIELD5_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_FIELD5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_FIELD5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_FIELD5_MASK)
#define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_X5_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_X5_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_X5(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_X5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_X5_MASK)
#define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_TOGGLE5_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_TOGGLE5_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_TOGGLE5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_TOGGLE5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSON_SPGPSON_TOGGLE5_MASK)

/*! @name TCON1_SPG5MASKON - The Sequencer Pulse Generator 5 Mask Enable register is used to mask the enable of SPG 5 */
#define IRIS_MVPL_TCON1_SPG5MASKON_SPGMKON5_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG5MASKON_SPGMKON5_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG5MASKON_SPGMKON5(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5MASKON_SPGMKON5_SHIFT)) & IRIS_MVPL_TCON1_SPG5MASKON_SPGMKON5_MASK)

/*! @name TCON1_SPG5POSOFF - Sync pulse generator 5, 'Switch off' position */
#define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_Y5_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_Y5_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_Y5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_Y5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_Y5_MASK)
#define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_MASK)
#define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_X5_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_X5_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_X5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_X5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_X5_MASK)
#define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT)) & IRIS_MVPL_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK)

/*! @name TCON1_SPG5MASKOFF - The Sequencer Pulse Generator 5 Mask Enable register is used to mask the disable of SPG 5 */
#define IRIS_MVPL_TCON1_SPG5MASKOFF_SPGMKOFF5_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG5MASKOFF_SPGMKOFF5_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG5MASKOFF_SPGMKOFF5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG5MASKOFF_SPGMKOFF5_SHIFT)) & IRIS_MVPL_TCON1_SPG5MASKOFF_SPGMKOFF5_MASK)

/*! @name TCON1_SPG6POSON - Sync pulse generator 6, 'Switch on' position */
#define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_Y6_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_Y6_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_Y6(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_Y6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_Y6_MASK)
#define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_FIELD6_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_FIELD6_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_FIELD6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_FIELD6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_FIELD6_MASK)
#define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_X6_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_X6_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_X6(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_X6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_X6_MASK)
#define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_TOGGLE6_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_TOGGLE6_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_TOGGLE6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_TOGGLE6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSON_SPGPSON_TOGGLE6_MASK)

/*! @name TCON1_SPG6MASKON - The Sequencer Pulse Generator 6 Mask Enable register is used to mask the enable of SPG 6 */
#define IRIS_MVPL_TCON1_SPG6MASKON_SPGMKON6_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG6MASKON_SPGMKON6_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG6MASKON_SPGMKON6(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6MASKON_SPGMKON6_SHIFT)) & IRIS_MVPL_TCON1_SPG6MASKON_SPGMKON6_MASK)

/*! @name TCON1_SPG6POSOFF - Sync pulse generator 6, 'Switch off' position */
#define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_Y6_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_Y6_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_Y6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_Y6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_Y6_MASK)
#define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_MASK)
#define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_X6_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_X6_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_X6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_X6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_X6_MASK)
#define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT)) & IRIS_MVPL_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK)

/*! @name TCON1_SPG6MASKOFF - The Sequencer Pulse Generator 6 Mask Enable register is used to mask the disable of SPG 6 */
#define IRIS_MVPL_TCON1_SPG6MASKOFF_SPGMKOFF6_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG6MASKOFF_SPGMKOFF6_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG6MASKOFF_SPGMKOFF6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG6MASKOFF_SPGMKOFF6_SHIFT)) & IRIS_MVPL_TCON1_SPG6MASKOFF_SPGMKOFF6_MASK)

/*! @name TCON1_SPG7POSON - Sync pulse generator 7, 'Switch on' position */
#define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_Y7_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_Y7_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_Y7(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_Y7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_Y7_MASK)
#define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_FIELD7_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_FIELD7_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_FIELD7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_FIELD7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_FIELD7_MASK)
#define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_X7_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_X7_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_X7(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_X7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_X7_MASK)
#define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_TOGGLE7_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_TOGGLE7_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_TOGGLE7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_TOGGLE7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSON_SPGPSON_TOGGLE7_MASK)

/*! @name TCON1_SPG7MASKON - The Sequencer Pulse Generator 7 Mask Enable register is used to mask the enable of SPG 7 */
#define IRIS_MVPL_TCON1_SPG7MASKON_SPGMKON7_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG7MASKON_SPGMKON7_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG7MASKON_SPGMKON7(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7MASKON_SPGMKON7_SHIFT)) & IRIS_MVPL_TCON1_SPG7MASKON_SPGMKON7_MASK)

/*! @name TCON1_SPG7POSOFF - Sync pulse generator 7, 'Switch off' position */
#define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_Y7_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_Y7_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_Y7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_Y7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_Y7_MASK)
#define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_MASK)
#define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_X7_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_X7_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_X7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_X7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_X7_MASK)
#define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT)) & IRIS_MVPL_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK)

/*! @name TCON1_SPG7MASKOFF - The Sequencer Pulse Generator 7 Mask Enable register is used to mask the disable of SPG 7 */
#define IRIS_MVPL_TCON1_SPG7MASKOFF_SPGMKOFF7_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG7MASKOFF_SPGMKOFF7_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG7MASKOFF_SPGMKOFF7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG7MASKOFF_SPGMKOFF7_SHIFT)) & IRIS_MVPL_TCON1_SPG7MASKOFF_SPGMKOFF7_MASK)

/*! @name TCON1_SPG8POSON - Sync pulse generator 8, 'Switch on' position */
#define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_Y8_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_Y8_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_Y8(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_Y8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_Y8_MASK)
#define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_FIELD8_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_FIELD8_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_FIELD8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_FIELD8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_FIELD8_MASK)
#define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_X8_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_X8_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_X8(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_X8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_X8_MASK)
#define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_TOGGLE8_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_TOGGLE8_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_TOGGLE8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_TOGGLE8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSON_SPGPSON_TOGGLE8_MASK)

/*! @name TCON1_SPG8MASKON - The Sequencer Pulse Generator 8 Mask Enable register is used to mask the enable of SPG 8 */
#define IRIS_MVPL_TCON1_SPG8MASKON_SPGMKON8_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG8MASKON_SPGMKON8_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG8MASKON_SPGMKON8(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8MASKON_SPGMKON8_SHIFT)) & IRIS_MVPL_TCON1_SPG8MASKON_SPGMKON8_MASK)

/*! @name TCON1_SPG8POSOFF - Sync pulse generator 8, 'Switch off' position */
#define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_Y8_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_Y8_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_Y8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_Y8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_Y8_MASK)
#define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_MASK)
#define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_X8_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_X8_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_X8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_X8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_X8_MASK)
#define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT)) & IRIS_MVPL_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK)

/*! @name TCON1_SPG8MASKOFF - The Sequencer Pulse Generator 8 Mask Enable register is used to mask the disable of SPG 8 */
#define IRIS_MVPL_TCON1_SPG8MASKOFF_SPGMKOFF8_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG8MASKOFF_SPGMKOFF8_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG8MASKOFF_SPGMKOFF8(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG8MASKOFF_SPGMKOFF8_SHIFT)) & IRIS_MVPL_TCON1_SPG8MASKOFF_SPGMKOFF8_MASK)

/*! @name TCON1_SPG9POSON - Sync pulse generator 9, 'Switch on' position */
#define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_Y9_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_Y9_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_Y9(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_Y9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_Y9_MASK)
#define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_FIELD9_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_FIELD9_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_FIELD9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_FIELD9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_FIELD9_MASK)
#define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_X9_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_X9_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_X9(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_X9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_X9_MASK)
#define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_TOGGLE9_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_TOGGLE9_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_TOGGLE9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_TOGGLE9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSON_SPGPSON_TOGGLE9_MASK)

/*! @name TCON1_SPG9MASKON - The Sequencer Pulse Generator 9 Mask Enable register is used to mask the enable of SPG 9 */
#define IRIS_MVPL_TCON1_SPG9MASKON_SPGMKON9_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG9MASKON_SPGMKON9_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG9MASKON_SPGMKON9(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9MASKON_SPGMKON9_SHIFT)) & IRIS_MVPL_TCON1_SPG9MASKON_SPGMKON9_MASK)

/*! @name TCON1_SPG9POSOFF - Sync pulse generator 9, 'Switch off' position */
#define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_Y9_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_Y9_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_Y9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_Y9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_Y9_MASK)
#define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_MASK)
#define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_X9_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_X9_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_X9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_X9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_X9_MASK)
#define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT)) & IRIS_MVPL_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK)

/*! @name TCON1_SPG9MASKOFF - The Sequencer Pulse Generator 9 Mask Enable register is used to mask the disable of SPG 9 */
#define IRIS_MVPL_TCON1_SPG9MASKOFF_SPGMKOFF9_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG9MASKOFF_SPGMKOFF9_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG9MASKOFF_SPGMKOFF9(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG9MASKOFF_SPGMKOFF9_SHIFT)) & IRIS_MVPL_TCON1_SPG9MASKOFF_SPGMKOFF9_MASK)

/*! @name TCON1_SPG10POSON - Sync pulse generator 10, 'Switch on' position */
#define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_Y10_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_Y10_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_Y10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_Y10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_Y10_MASK)
#define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_FIELD10_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_FIELD10_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_FIELD10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_FIELD10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_FIELD10_MASK)
#define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK)
#define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_TOGGLE10_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_TOGGLE10_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_TOGGLE10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_TOGGLE10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_TOGGLE10_MASK)

/*! @name TCON1_SPG10MASKON - The Sequencer Pulse Generator 10 Mask Enable register is used to mask the enable of SPG 10 */
#define IRIS_MVPL_TCON1_SPG10MASKON_SPGMKON10_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG10MASKON_SPGMKON10_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG10MASKON_SPGMKON10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10MASKON_SPGMKON10_SHIFT)) & IRIS_MVPL_TCON1_SPG10MASKON_SPGMKON10_MASK)

/*! @name TCON1_SPG10POSOFF - Sync pulse generator 10, 'Switch off' position */
#define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_Y10_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_Y10_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_Y10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_Y10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_Y10_MASK)
#define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_MASK)
#define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_X10_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_X10_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_X10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_X10_MASK)
#define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK)

/*! @name TCON1_SPG10MASKOFF - The Sequencer Pulse Generator 10 Mask Enable register is used to mask the disable of SPG 10 */
#define IRIS_MVPL_TCON1_SPG10MASKOFF_SPGMKOFF10_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG10MASKOFF_SPGMKOFF10_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG10MASKOFF_SPGMKOFF10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG10MASKOFF_SPGMKOFF10_SHIFT)) & IRIS_MVPL_TCON1_SPG10MASKOFF_SPGMKOFF10_MASK)

/*! @name TCON1_SPG11POSON - Sync pulse generator 11, 'Switch on' position */
#define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_Y11_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_Y11_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_Y11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_Y11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_Y11_MASK)
#define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_FIELD11_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_FIELD11_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_FIELD11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_FIELD11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_FIELD11_MASK)
#define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_X11_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_X11_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_X11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_X11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_X11_MASK)
#define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_TOGGLE11_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_TOGGLE11_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_TOGGLE11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_TOGGLE11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSON_SPGPSON_TOGGLE11_MASK)

/*! @name TCON1_SPG11MASKON - The Sequencer Pulse Generator 11 Mask Enable register is used to mask the enable of SPG 11 */
#define IRIS_MVPL_TCON1_SPG11MASKON_SPGMKON11_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG11MASKON_SPGMKON11_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG11MASKON_SPGMKON11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11MASKON_SPGMKON11_SHIFT)) & IRIS_MVPL_TCON1_SPG11MASKON_SPGMKON11_MASK)

/*! @name TCON1_SPG11POSOFF - Sync pulse generator 11, 'Switch off' position */
#define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_Y11_MASK (0x7FFFU)
#define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_Y11_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_Y11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_Y11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_Y11_MASK)
#define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_MASK (0x8000U)
#define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT (15U)
#define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_MASK)
#define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_X11_MASK (0x7FFF0000U)
#define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_X11_SHIFT (16U)
#define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_X11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_X11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_X11_MASK)
#define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK (0x80000000U)
#define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT (31U)
#define IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT)) & IRIS_MVPL_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK)

/*! @name TCON1_SPG11MASKOFF - The Sequencer Pulse Generator 11 Mask Enable register is used to mask the disable of SPG 11 */
#define IRIS_MVPL_TCON1_SPG11MASKOFF_SPGMKOFF11_MASK (0x7FFFFFFFU)
#define IRIS_MVPL_TCON1_SPG11MASKOFF_SPGMKOFF11_SHIFT (0U)
#define IRIS_MVPL_TCON1_SPG11MASKOFF_SPGMKOFF11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SPG11MASKOFF_SPGMKOFF11_SHIFT)) & IRIS_MVPL_TCON1_SPG11MASKOFF_SPGMKOFF11_MASK)

/*! @name TCON1_SMX0SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S0_MASK)
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S1_MASK)
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S2_MASK)
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S3_MASK)
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX0SIGS_SMX0SIGS_S4_MASK)

/*! @name TCON1_SMX0FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON1_SMX0FCTTABLE_SMXFCT0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON1_SMX0FCTTABLE_SMXFCT0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX0FCTTABLE_SMXFCT0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX0FCTTABLE_SMXFCT0_SHIFT)) & IRIS_MVPL_TCON1_SMX0FCTTABLE_SMXFCT0_MASK)

/*! @name TCON1_SMX1SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S0_MASK)
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S1_MASK)
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S2_MASK)
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S3_MASK)
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX1SIGS_SMX1SIGS_S4_MASK)

/*! @name TCON1_SMX1FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON1_SMX1FCTTABLE_SMXFCT1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON1_SMX1FCTTABLE_SMXFCT1_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX1FCTTABLE_SMXFCT1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX1FCTTABLE_SMXFCT1_SHIFT)) & IRIS_MVPL_TCON1_SMX1FCTTABLE_SMXFCT1_MASK)

/*! @name TCON1_SMX2SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S0_MASK)
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S1_MASK)
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S2_MASK)
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S3_MASK)
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX2SIGS_SMX2SIGS_S4_MASK)

/*! @name TCON1_SMX2FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s**3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON1_SMX2FCTTABLE_SMXFCT2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON1_SMX2FCTTABLE_SMXFCT2_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX2FCTTABLE_SMXFCT2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX2FCTTABLE_SMXFCT2_SHIFT)) & IRIS_MVPL_TCON1_SMX2FCTTABLE_SMXFCT2_MASK)

/*! @name TCON1_SMX3SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S0_MASK)
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S1_MASK)
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S2_MASK)
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S3_MASK)
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX3SIGS_SMX3SIGS_S4_MASK)

/*! @name TCON1_SMX3FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON1_SMX3FCTTABLE_SMXFCT3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON1_SMX3FCTTABLE_SMXFCT3_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX3FCTTABLE_SMXFCT3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX3FCTTABLE_SMXFCT3_SHIFT)) & IRIS_MVPL_TCON1_SMX3FCTTABLE_SMXFCT3_MASK)

/*! @name TCON1_SMX4SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S0_MASK)
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S1_MASK)
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S2_MASK)
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S3_MASK)
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX4SIGS_SMX4SIGS_S4_MASK)

/*! @name TCON1_SMX4FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON1_SMX4FCTTABLE_SMXFCT4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON1_SMX4FCTTABLE_SMXFCT4_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX4FCTTABLE_SMXFCT4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX4FCTTABLE_SMXFCT4_SHIFT)) & IRIS_MVPL_TCON1_SMX4FCTTABLE_SMXFCT4_MASK)

/*! @name TCON1_SMX5SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S0_MASK)
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S1_MASK)
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S2_MASK)
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S3_MASK)
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX5SIGS_SMX5SIGS_S4_MASK)

/*! @name TCON1_SMX5FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON1_SMX5FCTTABLE_SMXFCT5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON1_SMX5FCTTABLE_SMXFCT5_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX5FCTTABLE_SMXFCT5(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX5FCTTABLE_SMXFCT5_SHIFT)) & IRIS_MVPL_TCON1_SMX5FCTTABLE_SMXFCT5_MASK)

/*! @name TCON1_SMX6SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S0_MASK)
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S1_MASK)
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S2_MASK)
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S3_MASK)
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX6SIGS_SMX6SIGS_S4_MASK)

/*! @name TCON1_SMX6FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON1_SMX6FCTTABLE_SMXFCT6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON1_SMX6FCTTABLE_SMXFCT6_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX6FCTTABLE_SMXFCT6(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX6FCTTABLE_SMXFCT6_SHIFT)) & IRIS_MVPL_TCON1_SMX6FCTTABLE_SMXFCT6_MASK)

/*! @name TCON1_SMX7SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S0_MASK)
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S1_MASK)
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S2_MASK)
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S3_MASK)
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX7SIGS_SMX7SIGS_S4_MASK)

/*! @name TCON1_SMX7FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON1_SMX7FCTTABLE_SMXFCT7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON1_SMX7FCTTABLE_SMXFCT7_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX7FCTTABLE_SMXFCT7(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX7FCTTABLE_SMXFCT7_SHIFT)) & IRIS_MVPL_TCON1_SMX7FCTTABLE_SMXFCT7_MASK)

/*! @name TCON1_SMX8SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S0_MASK)
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S1_MASK)
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S2_MASK)
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S3_MASK)
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX8SIGS_SMX8SIGS_S4_MASK)

/*! @name TCON1_SMX8FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON1_SMX8FCTTABLE_SMXFCT8_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON1_SMX8FCTTABLE_SMXFCT8_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX8FCTTABLE_SMXFCT8(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX8FCTTABLE_SMXFCT8_SHIFT)) & IRIS_MVPL_TCON1_SMX8FCTTABLE_SMXFCT8_MASK)

/*! @name TCON1_SMX9SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S0_MASK)
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S1_MASK)
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S2_MASK)
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S3_MASK)
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX9SIGS_SMX9SIGS_S4_MASK)

/*! @name TCON1_SMX9FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON1_SMX9FCTTABLE_SMXFCT9_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON1_SMX9FCTTABLE_SMXFCT9_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX9FCTTABLE_SMXFCT9(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX9FCTTABLE_SMXFCT9_SHIFT)) & IRIS_MVPL_TCON1_SMX9FCTTABLE_SMXFCT9_MASK)

/*! @name TCON1_SMX10SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S0_MASK)
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S1_MASK)
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S2_MASK)
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S3_MASK)
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX10SIGS_SMX10SIGS_S4_MASK)

/*! @name TCON1_SMX10FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON1_SMX10FCTTABLE_SMXFCT10_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON1_SMX10FCTTABLE_SMXFCT10_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX10FCTTABLE_SMXFCT10(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX10FCTTABLE_SMXFCT10_SHIFT)) & IRIS_MVPL_TCON1_SMX10FCTTABLE_SMXFCT10_MASK)

/*! @name TCON1_SMX11SIGS - Selection of input signals of sync mixer */
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S0_MASK (0x7U)
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S0_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S0_SHIFT)) & IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S0_MASK)
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S1_MASK (0x38U)
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S1_SHIFT (3U)
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S1_SHIFT)) & IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S1_MASK)
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S2_MASK (0x1C0U)
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S2_SHIFT (6U)
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S2_SHIFT)) & IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S2_MASK)
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S3_MASK (0xE00U)
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S3_SHIFT (9U)
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S3_SHIFT)) & IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S3_MASK)
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S4_MASK (0x7000U)
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S4_SHIFT (12U)
#define IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S4_SHIFT)) & IRIS_MVPL_TCON1_SMX11SIGS_SMX11SIGS_S4_MASK)

/*! @name TCON1_SMX11FCTTABLE - The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection */
#define IRIS_MVPL_TCON1_SMX11FCTTABLE_SMXFCT11_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_TCON1_SMX11FCTTABLE_SMXFCT11_SHIFT (0U)
#define IRIS_MVPL_TCON1_SMX11FCTTABLE_SMXFCT11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_SMX11FCTTABLE_SMXFCT11_SHIFT)) & IRIS_MVPL_TCON1_SMX11FCTTABLE_SMXFCT11_MASK)

/*! @name TCON1_RESET_OVER_UNFERFLOW - reset status overflow and underflow of both dual channel fifos */
#define IRIS_MVPL_TCON1_RESET_OVER_UNFERFLOW_reset_status_MASK (0x1U)
#define IRIS_MVPL_TCON1_RESET_OVER_UNFERFLOW_reset_status_SHIFT (0U)
#define IRIS_MVPL_TCON1_RESET_OVER_UNFERFLOW_reset_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_RESET_OVER_UNFERFLOW_reset_status_SHIFT)) & IRIS_MVPL_TCON1_RESET_OVER_UNFERFLOW_reset_status_MASK)

/*! @name TCON1_DUAL_DEBUG - Status of fifo during dual channel operation. They are only available in Split Mode */
#define IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_overflow_MASK (0x1U)
#define IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_overflow_SHIFT (0U)
#define IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_overflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_overflow_SHIFT)) & IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_overflow_MASK)
#define IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_underflow_MASK (0x2U)
#define IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_underflow_SHIFT (1U)
#define IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_underflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_underflow_SHIFT)) & IRIS_MVPL_TCON1_DUAL_DEBUG_lower_fifo_underflow_MASK)
#define IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_overflow_MASK (0x10U)
#define IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_overflow_SHIFT (4U)
#define IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_overflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_overflow_SHIFT)) & IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_overflow_MASK)
#define IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_underflow_MASK (0x20U)
#define IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_underflow_SHIFT (5U)
#define IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_underflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_underflow_SHIFT)) & IRIS_MVPL_TCON1_DUAL_DEBUG_upper_fifo_underflow_MASK)

/*! @name SIG1_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_SIG1_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_SIG1_LOCKUNLOCK_LockUnlock(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_SIG1_LOCKUNLOCK_LockUnlock_MASK)

/*! @name SIG1_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_SIG1_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_SIG1_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_SIG1_LOCKSTATUS_LockStatus(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_SIG1_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_SIG1_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_SIG1_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_SIG1_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_SIG1_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_SIG1_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_SIG1_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_SIG1_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_SIG1_LOCKSTATUS_FreezeStatus_MASK)

/*! @name SIG1_STATICCONTROL - Global configuration shared by all evaluation windows. */
#define IRIS_MVPL_SIG1_STATICCONTROL_ShdEn_MASK  (0x1U)
#define IRIS_MVPL_SIG1_STATICCONTROL_ShdEn_SHIFT (0U)
#define IRIS_MVPL_SIG1_STATICCONTROL_ShdEn(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_SIG1_STATICCONTROL_ShdEn_MASK)
#define IRIS_MVPL_SIG1_STATICCONTROL_ShdLdSel_MASK (0x10U)
#define IRIS_MVPL_SIG1_STATICCONTROL_ShdLdSel_SHIFT (4U)
#define IRIS_MVPL_SIG1_STATICCONTROL_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_STATICCONTROL_ShdLdSel_SHIFT)) & IRIS_MVPL_SIG1_STATICCONTROL_ShdLdSel_MASK)
#define IRIS_MVPL_SIG1_STATICCONTROL_ErrThres_MASK (0xFF0000U)
#define IRIS_MVPL_SIG1_STATICCONTROL_ErrThres_SHIFT (16U)
#define IRIS_MVPL_SIG1_STATICCONTROL_ErrThres(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_STATICCONTROL_ErrThres_SHIFT)) & IRIS_MVPL_SIG1_STATICCONTROL_ErrThres_MASK)
#define IRIS_MVPL_SIG1_STATICCONTROL_ErrThresReset_MASK (0xFF000000U)
#define IRIS_MVPL_SIG1_STATICCONTROL_ErrThresReset_SHIFT (24U)
#define IRIS_MVPL_SIG1_STATICCONTROL_ErrThresReset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_STATICCONTROL_ErrThresReset_SHIFT)) & IRIS_MVPL_SIG1_STATICCONTROL_ErrThresReset_MASK)

/*! @name SIG1_PANICCOLOR - Overlay color for evaluation windows in panic mode. */
#define IRIS_MVPL_SIG1_PANICCOLOR_PanicAlpha_MASK (0x80U)
#define IRIS_MVPL_SIG1_PANICCOLOR_PanicAlpha_SHIFT (7U)
#define IRIS_MVPL_SIG1_PANICCOLOR_PanicAlpha(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_PANICCOLOR_PanicAlpha_SHIFT)) & IRIS_MVPL_SIG1_PANICCOLOR_PanicAlpha_MASK)
#define IRIS_MVPL_SIG1_PANICCOLOR_PanicBlue_MASK (0xFF00U)
#define IRIS_MVPL_SIG1_PANICCOLOR_PanicBlue_SHIFT (8U)
#define IRIS_MVPL_SIG1_PANICCOLOR_PanicBlue(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_PANICCOLOR_PanicBlue_SHIFT)) & IRIS_MVPL_SIG1_PANICCOLOR_PanicBlue_MASK)
#define IRIS_MVPL_SIG1_PANICCOLOR_PanicGreen_MASK (0xFF0000U)
#define IRIS_MVPL_SIG1_PANICCOLOR_PanicGreen_SHIFT (16U)
#define IRIS_MVPL_SIG1_PANICCOLOR_PanicGreen(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_PANICCOLOR_PanicGreen_SHIFT)) & IRIS_MVPL_SIG1_PANICCOLOR_PanicGreen_MASK)
#define IRIS_MVPL_SIG1_PANICCOLOR_PanicRed_MASK  (0xFF000000U)
#define IRIS_MVPL_SIG1_PANICCOLOR_PanicRed_SHIFT (24U)
#define IRIS_MVPL_SIG1_PANICCOLOR_PanicRed(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_PANICCOLOR_PanicRed_SHIFT)) & IRIS_MVPL_SIG1_PANICCOLOR_PanicRed_MASK)

/*! @name SIG1_EVALCONTROL0 - Control settings for evaluation window 0. */
#define IRIS_MVPL_SIG1_EVALCONTROL0_EnEvalWin0_MASK (0x1U)
#define IRIS_MVPL_SIG1_EVALCONTROL0_EnEvalWin0_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALCONTROL0_EnEvalWin0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL0_EnEvalWin0_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL0_EnEvalWin0_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL0_EnCRC0_MASK  (0x2U)
#define IRIS_MVPL_SIG1_EVALCONTROL0_EnCRC0_SHIFT (1U)
#define IRIS_MVPL_SIG1_EVALCONTROL0_EnCRC0(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL0_EnCRC0_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL0_EnCRC0_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL0_AlphaMask0_MASK (0x100U)
#define IRIS_MVPL_SIG1_EVALCONTROL0_AlphaMask0_SHIFT (8U)
#define IRIS_MVPL_SIG1_EVALCONTROL0_AlphaMask0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL0_AlphaMask0_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL0_AlphaMask0_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL0_AlphaInv0_MASK (0x200U)
#define IRIS_MVPL_SIG1_EVALCONTROL0_AlphaInv0_SHIFT (9U)
#define IRIS_MVPL_SIG1_EVALCONTROL0_AlphaInv0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL0_AlphaInv0_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL0_AlphaInv0_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL0_EnLocalPanic0_MASK (0x10000U)
#define IRIS_MVPL_SIG1_EVALCONTROL0_EnLocalPanic0_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALCONTROL0_EnLocalPanic0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL0_EnLocalPanic0_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL0_EnLocalPanic0_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL0_EnGlobalPanic0_MASK (0x20000U)
#define IRIS_MVPL_SIG1_EVALCONTROL0_EnGlobalPanic0_SHIFT (17U)
#define IRIS_MVPL_SIG1_EVALCONTROL0_EnGlobalPanic0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL0_EnGlobalPanic0_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL0_EnGlobalPanic0_MASK)

/*! @name SIG1_EVALUPPERLEFT0 - Upper left corner of evaluation window 0. */
#define IRIS_MVPL_SIG1_EVALUPPERLEFT0_XEvalUpperLeft0_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT0_XEvalUpperLeft0_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT0_XEvalUpperLeft0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT0_XEvalUpperLeft0_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT0_XEvalUpperLeft0_MASK)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT0_YEvalUpperLeft0_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT0_YEvalUpperLeft0_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT0_YEvalUpperLeft0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT0_YEvalUpperLeft0_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT0_YEvalUpperLeft0_MASK)

/*! @name SIG1_EVALLOWERRIGHT0 - Lower right corner of evaluation window 0. */
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT0_XEvalLowerRight0_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT0_XEvalLowerRight0_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT0_XEvalLowerRight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT0_XEvalLowerRight0_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT0_XEvalLowerRight0_MASK)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT0_YEvalLowerRight0_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT0_YEvalLowerRight0_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT0_YEvalLowerRight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT0_YEvalLowerRight0_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT0_YEvalLowerRight0_MASK)

/*! @name SIG1_SIGCRCREDREF0 - Reference signature of red channel for evaluation window 0. */
#define IRIS_MVPL_SIG1_SIGCRCREDREF0_SigCRCRedRef0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCREDREF0_SigCRCRedRef0_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCREDREF0_SigCRCRedRef0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF0_SigCRCRedRef0_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF0_SigCRCRedRef0_MASK)

/*! @name SIG1_SIGCRCGREENREF0 - Reference signature of green channel for evaluation window 0. */
#define IRIS_MVPL_SIG1_SIGCRCGREENREF0_SigCRCGreenRef0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF0_SigCRCGreenRef0_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF0_SigCRCGreenRef0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF0_SigCRCGreenRef0_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF0_SigCRCGreenRef0_MASK)

/*! @name SIG1_SIGCRCBLUEREF0 - Reference signature of blue channel for evaluation window 0. */
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF0_SigCRCBlueRef0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF0_SigCRCBlueRef0_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF0_SigCRCBlueRef0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF0_SigCRCBlueRef0_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF0_SigCRCBlueRef0_MASK)

/*! @name SIG1_SIGCRCRED0 - Measured signature of red channel for evaluation window 0. */
#define IRIS_MVPL_SIG1_SIGCRCRED0_SigCRCRed0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCRED0_SigCRCRed0_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCRED0_SigCRCRed0(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED0_SigCRCRed0_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED0_SigCRCRed0_MASK)

/*! @name SIG1_SIGCRCGREEN0 - Measured signature of green channel for evaluation window 0. */
#define IRIS_MVPL_SIG1_SIGCRCGREEN0_SigCRCGreen0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREEN0_SigCRCGreen0_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREEN0_SigCRCGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN0_SigCRCGreen0_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN0_SigCRCGreen0_MASK)

/*! @name SIG1_SIGCRCBLUE0 - Measured signature of blue channel for evaluation window 0. */
#define IRIS_MVPL_SIG1_SIGCRCBLUE0_SigCRCBlue0_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUE0_SigCRCBlue0_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUE0_SigCRCBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE0_SigCRCBlue0_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE0_SigCRCBlue0_MASK)

/*! @name SIG1_EVALCONTROL1 - Control settings for evaluation window 1. */
#define IRIS_MVPL_SIG1_EVALCONTROL1_EnEvalWin1_MASK (0x1U)
#define IRIS_MVPL_SIG1_EVALCONTROL1_EnEvalWin1_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALCONTROL1_EnEvalWin1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL1_EnEvalWin1_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL1_EnEvalWin1_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL1_EnCRC1_MASK  (0x2U)
#define IRIS_MVPL_SIG1_EVALCONTROL1_EnCRC1_SHIFT (1U)
#define IRIS_MVPL_SIG1_EVALCONTROL1_EnCRC1(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL1_EnCRC1_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL1_EnCRC1_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL1_AlphaMask1_MASK (0x100U)
#define IRIS_MVPL_SIG1_EVALCONTROL1_AlphaMask1_SHIFT (8U)
#define IRIS_MVPL_SIG1_EVALCONTROL1_AlphaMask1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL1_AlphaMask1_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL1_AlphaMask1_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL1_AlphaInv1_MASK (0x200U)
#define IRIS_MVPL_SIG1_EVALCONTROL1_AlphaInv1_SHIFT (9U)
#define IRIS_MVPL_SIG1_EVALCONTROL1_AlphaInv1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL1_AlphaInv1_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL1_AlphaInv1_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL1_EnLocalPanic1_MASK (0x10000U)
#define IRIS_MVPL_SIG1_EVALCONTROL1_EnLocalPanic1_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALCONTROL1_EnLocalPanic1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL1_EnLocalPanic1_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL1_EnLocalPanic1_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL1_EnGlobalPanic1_MASK (0x20000U)
#define IRIS_MVPL_SIG1_EVALCONTROL1_EnGlobalPanic1_SHIFT (17U)
#define IRIS_MVPL_SIG1_EVALCONTROL1_EnGlobalPanic1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL1_EnGlobalPanic1_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL1_EnGlobalPanic1_MASK)

/*! @name SIG1_EVALUPPERLEFT1 - Upper left corner of evaluation window 1. */
#define IRIS_MVPL_SIG1_EVALUPPERLEFT1_XEvalUpperLeft1_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT1_XEvalUpperLeft1_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT1_XEvalUpperLeft1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT1_XEvalUpperLeft1_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT1_XEvalUpperLeft1_MASK)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT1_YEvalUpperLeft1_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT1_YEvalUpperLeft1_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT1_YEvalUpperLeft1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT1_YEvalUpperLeft1_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT1_YEvalUpperLeft1_MASK)

/*! @name SIG1_EVALLOWERRIGHT1 - Lower right corner of evaluation window 1. */
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT1_XEvalLowerRight1_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT1_XEvalLowerRight1_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT1_XEvalLowerRight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT1_XEvalLowerRight1_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT1_XEvalLowerRight1_MASK)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT1_YEvalLowerRight1_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT1_YEvalLowerRight1_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT1_YEvalLowerRight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT1_YEvalLowerRight1_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT1_YEvalLowerRight1_MASK)

/*! @name SIG1_SIGCRCREDREF1 - Reference signature of red channel for evaluation window 1. */
#define IRIS_MVPL_SIG1_SIGCRCREDREF1_SigCRCRedRef1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCREDREF1_SigCRCRedRef1_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCREDREF1_SigCRCRedRef1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF1_SigCRCRedRef1_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF1_SigCRCRedRef1_MASK)

/*! @name SIG1_SIGCRCGREENREF1 - Reference signature of green channel for evaluation window 1. */
#define IRIS_MVPL_SIG1_SIGCRCGREENREF1_SigCRCGreenRef1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF1_SigCRCGreenRef1_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF1_SigCRCGreenRef1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF1_SigCRCGreenRef1_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF1_SigCRCGreenRef1_MASK)

/*! @name SIG1_SIGCRCBLUEREF1 - Reference signature of blue channel for evaluation window 1. */
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF1_SigCRCBlueRef1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF1_SigCRCBlueRef1_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF1_SigCRCBlueRef1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF1_SigCRCBlueRef1_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF1_SigCRCBlueRef1_MASK)

/*! @name SIG1_SIGCRCRED1 - Measured signature of red channel for evaluation window 1. */
#define IRIS_MVPL_SIG1_SIGCRCRED1_SigCRCRed1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCRED1_SigCRCRed1_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCRED1_SigCRCRed1(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED1_SigCRCRed1_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED1_SigCRCRed1_MASK)

/*! @name SIG1_SIGCRCGREEN1 - Measured signature of green channel for evaluation window 1. */
#define IRIS_MVPL_SIG1_SIGCRCGREEN1_SigCRCGreen1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREEN1_SigCRCGreen1_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREEN1_SigCRCGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN1_SigCRCGreen1_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN1_SigCRCGreen1_MASK)

/*! @name SIG1_SIGCRCBLUE1 - Measured signature of blue channel for evaluation window 1. */
#define IRIS_MVPL_SIG1_SIGCRCBLUE1_SigCRCBlue1_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUE1_SigCRCBlue1_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUE1_SigCRCBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE1_SigCRCBlue1_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE1_SigCRCBlue1_MASK)

/*! @name SIG1_EVALCONTROL2 - Control settings for evaluation window 2. */
#define IRIS_MVPL_SIG1_EVALCONTROL2_EnEvalWin2_MASK (0x1U)
#define IRIS_MVPL_SIG1_EVALCONTROL2_EnEvalWin2_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALCONTROL2_EnEvalWin2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL2_EnEvalWin2_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL2_EnEvalWin2_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL2_EnCRC2_MASK  (0x2U)
#define IRIS_MVPL_SIG1_EVALCONTROL2_EnCRC2_SHIFT (1U)
#define IRIS_MVPL_SIG1_EVALCONTROL2_EnCRC2(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL2_EnCRC2_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL2_EnCRC2_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL2_AlphaMask2_MASK (0x100U)
#define IRIS_MVPL_SIG1_EVALCONTROL2_AlphaMask2_SHIFT (8U)
#define IRIS_MVPL_SIG1_EVALCONTROL2_AlphaMask2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL2_AlphaMask2_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL2_AlphaMask2_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL2_AlphaInv2_MASK (0x200U)
#define IRIS_MVPL_SIG1_EVALCONTROL2_AlphaInv2_SHIFT (9U)
#define IRIS_MVPL_SIG1_EVALCONTROL2_AlphaInv2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL2_AlphaInv2_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL2_AlphaInv2_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL2_EnLocalPanic2_MASK (0x10000U)
#define IRIS_MVPL_SIG1_EVALCONTROL2_EnLocalPanic2_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALCONTROL2_EnLocalPanic2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL2_EnLocalPanic2_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL2_EnLocalPanic2_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL2_EnGlobalPanic2_MASK (0x20000U)
#define IRIS_MVPL_SIG1_EVALCONTROL2_EnGlobalPanic2_SHIFT (17U)
#define IRIS_MVPL_SIG1_EVALCONTROL2_EnGlobalPanic2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL2_EnGlobalPanic2_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL2_EnGlobalPanic2_MASK)

/*! @name SIG1_EVALUPPERLEFT2 - Upper left corner of evaluation window 2. */
#define IRIS_MVPL_SIG1_EVALUPPERLEFT2_XEvalUpperLeft2_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT2_XEvalUpperLeft2_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT2_XEvalUpperLeft2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT2_XEvalUpperLeft2_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT2_XEvalUpperLeft2_MASK)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT2_YEvalUpperLeft2_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT2_YEvalUpperLeft2_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT2_YEvalUpperLeft2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT2_YEvalUpperLeft2_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT2_YEvalUpperLeft2_MASK)

/*! @name SIG1_EVALLOWERRIGHT2 - Lower right corner of evaluation window 2. */
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT2_XEvalLowerRight2_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT2_XEvalLowerRight2_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT2_XEvalLowerRight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT2_XEvalLowerRight2_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT2_XEvalLowerRight2_MASK)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT2_YEvalLowerRight2_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT2_YEvalLowerRight2_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT2_YEvalLowerRight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT2_YEvalLowerRight2_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT2_YEvalLowerRight2_MASK)

/*! @name SIG1_SIGCRCREDREF2 - Reference signature of red channel for evaluation window 2. */
#define IRIS_MVPL_SIG1_SIGCRCREDREF2_SigCRCRedRef2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCREDREF2_SigCRCRedRef2_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCREDREF2_SigCRCRedRef2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF2_SigCRCRedRef2_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF2_SigCRCRedRef2_MASK)

/*! @name SIG1_SIGCRCGREENREF2 - Reference signature of green channel for evaluation window 2. */
#define IRIS_MVPL_SIG1_SIGCRCGREENREF2_SigCRCGreenRef2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF2_SigCRCGreenRef2_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF2_SigCRCGreenRef2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF2_SigCRCGreenRef2_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF2_SigCRCGreenRef2_MASK)

/*! @name SIG1_SIGCRCBLUEREF2 - Reference signature of blue channel for evaluation window 2. */
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF2_SigCRCBlueRef2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF2_SigCRCBlueRef2_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF2_SigCRCBlueRef2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF2_SigCRCBlueRef2_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF2_SigCRCBlueRef2_MASK)

/*! @name SIG1_SIGCRCRED2 - Measured signature of red channel for evaluation window 2. */
#define IRIS_MVPL_SIG1_SIGCRCRED2_SigCRCRed2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCRED2_SigCRCRed2_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCRED2_SigCRCRed2(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED2_SigCRCRed2_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED2_SigCRCRed2_MASK)

/*! @name SIG1_SIGCRCGREEN2 - Measured signature of green channel for evaluation window 2. */
#define IRIS_MVPL_SIG1_SIGCRCGREEN2_SigCRCGreen2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREEN2_SigCRCGreen2_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREEN2_SigCRCGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN2_SigCRCGreen2_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN2_SigCRCGreen2_MASK)

/*! @name SIG1_SIGCRCBLUE2 - Measured signature of blue channel for evaluation window 2. */
#define IRIS_MVPL_SIG1_SIGCRCBLUE2_SigCRCBlue2_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUE2_SigCRCBlue2_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUE2_SigCRCBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE2_SigCRCBlue2_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE2_SigCRCBlue2_MASK)

/*! @name SIG1_EVALCONTROL3 - Control settings for evaluation window 3. */
#define IRIS_MVPL_SIG1_EVALCONTROL3_EnEvalWin3_MASK (0x1U)
#define IRIS_MVPL_SIG1_EVALCONTROL3_EnEvalWin3_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALCONTROL3_EnEvalWin3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL3_EnEvalWin3_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL3_EnEvalWin3_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL3_EnCRC3_MASK  (0x2U)
#define IRIS_MVPL_SIG1_EVALCONTROL3_EnCRC3_SHIFT (1U)
#define IRIS_MVPL_SIG1_EVALCONTROL3_EnCRC3(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL3_EnCRC3_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL3_EnCRC3_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL3_AlphaMask3_MASK (0x100U)
#define IRIS_MVPL_SIG1_EVALCONTROL3_AlphaMask3_SHIFT (8U)
#define IRIS_MVPL_SIG1_EVALCONTROL3_AlphaMask3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL3_AlphaMask3_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL3_AlphaMask3_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL3_AlphaInv3_MASK (0x200U)
#define IRIS_MVPL_SIG1_EVALCONTROL3_AlphaInv3_SHIFT (9U)
#define IRIS_MVPL_SIG1_EVALCONTROL3_AlphaInv3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL3_AlphaInv3_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL3_AlphaInv3_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL3_EnLocalPanic3_MASK (0x10000U)
#define IRIS_MVPL_SIG1_EVALCONTROL3_EnLocalPanic3_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALCONTROL3_EnLocalPanic3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL3_EnLocalPanic3_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL3_EnLocalPanic3_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL3_EnGlobalPanic3_MASK (0x20000U)
#define IRIS_MVPL_SIG1_EVALCONTROL3_EnGlobalPanic3_SHIFT (17U)
#define IRIS_MVPL_SIG1_EVALCONTROL3_EnGlobalPanic3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL3_EnGlobalPanic3_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL3_EnGlobalPanic3_MASK)

/*! @name SIG1_EVALUPPERLEFT3 - Upper left corner of evaluation window 3. */
#define IRIS_MVPL_SIG1_EVALUPPERLEFT3_XEvalUpperLeft3_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT3_XEvalUpperLeft3_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT3_XEvalUpperLeft3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT3_XEvalUpperLeft3_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT3_XEvalUpperLeft3_MASK)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT3_YEvalUpperLeft3_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT3_YEvalUpperLeft3_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT3_YEvalUpperLeft3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT3_YEvalUpperLeft3_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT3_YEvalUpperLeft3_MASK)

/*! @name SIG1_EVALLOWERRIGHT3 - Lower right corner of evaluation window 3. */
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT3_XEvalLowerRight3_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT3_XEvalLowerRight3_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT3_XEvalLowerRight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT3_XEvalLowerRight3_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT3_XEvalLowerRight3_MASK)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT3_YEvalLowerRight3_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT3_YEvalLowerRight3_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT3_YEvalLowerRight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT3_YEvalLowerRight3_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT3_YEvalLowerRight3_MASK)

/*! @name SIG1_SIGCRCREDREF3 - Reference signature of red channel for evaluation window 3. */
#define IRIS_MVPL_SIG1_SIGCRCREDREF3_SigCRCRedRef3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCREDREF3_SigCRCRedRef3_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCREDREF3_SigCRCRedRef3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF3_SigCRCRedRef3_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF3_SigCRCRedRef3_MASK)

/*! @name SIG1_SIGCRCGREENREF3 - Reference signature of green channel for evaluation window 3. */
#define IRIS_MVPL_SIG1_SIGCRCGREENREF3_SigCRCGreenRef3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF3_SigCRCGreenRef3_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF3_SigCRCGreenRef3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF3_SigCRCGreenRef3_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF3_SigCRCGreenRef3_MASK)

/*! @name SIG1_SIGCRCBLUEREF3 - Reference signature of blue channel for evaluation window 3. */
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF3_SigCRCBlueRef3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF3_SigCRCBlueRef3_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF3_SigCRCBlueRef3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF3_SigCRCBlueRef3_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF3_SigCRCBlueRef3_MASK)

/*! @name SIG1_SIGCRCRED3 - Measured signature of red channel for evaluation window 3. */
#define IRIS_MVPL_SIG1_SIGCRCRED3_SigCRCRed3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCRED3_SigCRCRed3_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCRED3_SigCRCRed3(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED3_SigCRCRed3_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED3_SigCRCRed3_MASK)

/*! @name SIG1_SIGCRCGREEN3 - Measured signature of green channel for evaluation window 3. */
#define IRIS_MVPL_SIG1_SIGCRCGREEN3_SigCRCGreen3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREEN3_SigCRCGreen3_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREEN3_SigCRCGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN3_SigCRCGreen3_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN3_SigCRCGreen3_MASK)

/*! @name SIG1_SIGCRCBLUE3 - Measured signature of blue channel for evaluation window 3. */
#define IRIS_MVPL_SIG1_SIGCRCBLUE3_SigCRCBlue3_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUE3_SigCRCBlue3_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUE3_SigCRCBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE3_SigCRCBlue3_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE3_SigCRCBlue3_MASK)

/*! @name SIG1_EVALCONTROL4 - Control settings for evaluation window 4. */
#define IRIS_MVPL_SIG1_EVALCONTROL4_EnEvalWin4_MASK (0x1U)
#define IRIS_MVPL_SIG1_EVALCONTROL4_EnEvalWin4_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALCONTROL4_EnEvalWin4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL4_EnEvalWin4_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL4_EnEvalWin4_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL4_EnCRC4_MASK  (0x2U)
#define IRIS_MVPL_SIG1_EVALCONTROL4_EnCRC4_SHIFT (1U)
#define IRIS_MVPL_SIG1_EVALCONTROL4_EnCRC4(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL4_EnCRC4_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL4_EnCRC4_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL4_AlphaMask4_MASK (0x100U)
#define IRIS_MVPL_SIG1_EVALCONTROL4_AlphaMask4_SHIFT (8U)
#define IRIS_MVPL_SIG1_EVALCONTROL4_AlphaMask4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL4_AlphaMask4_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL4_AlphaMask4_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL4_AlphaInv4_MASK (0x200U)
#define IRIS_MVPL_SIG1_EVALCONTROL4_AlphaInv4_SHIFT (9U)
#define IRIS_MVPL_SIG1_EVALCONTROL4_AlphaInv4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL4_AlphaInv4_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL4_AlphaInv4_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL4_EnLocalPanic4_MASK (0x10000U)
#define IRIS_MVPL_SIG1_EVALCONTROL4_EnLocalPanic4_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALCONTROL4_EnLocalPanic4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL4_EnLocalPanic4_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL4_EnLocalPanic4_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL4_EnGlobalPanic4_MASK (0x20000U)
#define IRIS_MVPL_SIG1_EVALCONTROL4_EnGlobalPanic4_SHIFT (17U)
#define IRIS_MVPL_SIG1_EVALCONTROL4_EnGlobalPanic4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL4_EnGlobalPanic4_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL4_EnGlobalPanic4_MASK)

/*! @name SIG1_EVALUPPERLEFT4 - Upper left corner of evaluation window 4. */
#define IRIS_MVPL_SIG1_EVALUPPERLEFT4_XEvalUpperLeft4_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT4_XEvalUpperLeft4_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT4_XEvalUpperLeft4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT4_XEvalUpperLeft4_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT4_XEvalUpperLeft4_MASK)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT4_YEvalUpperLeft4_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT4_YEvalUpperLeft4_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT4_YEvalUpperLeft4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT4_YEvalUpperLeft4_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT4_YEvalUpperLeft4_MASK)

/*! @name SIG1_EVALLOWERRIGHT4 - Lower right corner of evaluation window 4. */
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT4_XEvalLowerRight4_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT4_XEvalLowerRight4_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT4_XEvalLowerRight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT4_XEvalLowerRight4_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT4_XEvalLowerRight4_MASK)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT4_YEvalLowerRight4_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT4_YEvalLowerRight4_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT4_YEvalLowerRight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT4_YEvalLowerRight4_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT4_YEvalLowerRight4_MASK)

/*! @name SIG1_SIGCRCREDREF4 - Reference signature of red channel for evaluation window 4. */
#define IRIS_MVPL_SIG1_SIGCRCREDREF4_SigCRCRedRef4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCREDREF4_SigCRCRedRef4_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCREDREF4_SigCRCRedRef4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF4_SigCRCRedRef4_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF4_SigCRCRedRef4_MASK)

/*! @name SIG1_SIGCRCGREENREF4 - Reference signature of green channel for evaluation window 4. */
#define IRIS_MVPL_SIG1_SIGCRCGREENREF4_SigCRCGreenRef4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF4_SigCRCGreenRef4_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF4_SigCRCGreenRef4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF4_SigCRCGreenRef4_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF4_SigCRCGreenRef4_MASK)

/*! @name SIG1_SIGCRCBLUEREF4 - Reference signature of blue channel for evaluation window 4. */
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF4_SigCRCBlueRef4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF4_SigCRCBlueRef4_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF4_SigCRCBlueRef4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF4_SigCRCBlueRef4_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF4_SigCRCBlueRef4_MASK)

/*! @name SIG1_SIGCRCRED4 - Measured signature of red channel for evaluation window 4. */
#define IRIS_MVPL_SIG1_SIGCRCRED4_SigCRCRed4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCRED4_SigCRCRed4_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCRED4_SigCRCRed4(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED4_SigCRCRed4_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED4_SigCRCRed4_MASK)

/*! @name SIG1_SIGCRCGREEN4 - Measured signature of green channel for evaluation window 4. */
#define IRIS_MVPL_SIG1_SIGCRCGREEN4_SigCRCGreen4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREEN4_SigCRCGreen4_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREEN4_SigCRCGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN4_SigCRCGreen4_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN4_SigCRCGreen4_MASK)

/*! @name SIG1_SIGCRCBLUE4 - Measured signature of blue channel for evaluation window 4. */
#define IRIS_MVPL_SIG1_SIGCRCBLUE4_SigCRCBlue4_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUE4_SigCRCBlue4_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUE4_SigCRCBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE4_SigCRCBlue4_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE4_SigCRCBlue4_MASK)

/*! @name SIG1_EVALCONTROL5 - Control settings for evaluation window 5. */
#define IRIS_MVPL_SIG1_EVALCONTROL5_EnEvalWin5_MASK (0x1U)
#define IRIS_MVPL_SIG1_EVALCONTROL5_EnEvalWin5_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALCONTROL5_EnEvalWin5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL5_EnEvalWin5_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL5_EnEvalWin5_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL5_EnCRC5_MASK  (0x2U)
#define IRIS_MVPL_SIG1_EVALCONTROL5_EnCRC5_SHIFT (1U)
#define IRIS_MVPL_SIG1_EVALCONTROL5_EnCRC5(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL5_EnCRC5_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL5_EnCRC5_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL5_AlphaMask5_MASK (0x100U)
#define IRIS_MVPL_SIG1_EVALCONTROL5_AlphaMask5_SHIFT (8U)
#define IRIS_MVPL_SIG1_EVALCONTROL5_AlphaMask5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL5_AlphaMask5_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL5_AlphaMask5_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL5_AlphaInv5_MASK (0x200U)
#define IRIS_MVPL_SIG1_EVALCONTROL5_AlphaInv5_SHIFT (9U)
#define IRIS_MVPL_SIG1_EVALCONTROL5_AlphaInv5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL5_AlphaInv5_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL5_AlphaInv5_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL5_EnLocalPanic5_MASK (0x10000U)
#define IRIS_MVPL_SIG1_EVALCONTROL5_EnLocalPanic5_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALCONTROL5_EnLocalPanic5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL5_EnLocalPanic5_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL5_EnLocalPanic5_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL5_EnGlobalPanic5_MASK (0x20000U)
#define IRIS_MVPL_SIG1_EVALCONTROL5_EnGlobalPanic5_SHIFT (17U)
#define IRIS_MVPL_SIG1_EVALCONTROL5_EnGlobalPanic5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL5_EnGlobalPanic5_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL5_EnGlobalPanic5_MASK)

/*! @name SIG1_EVALUPPERLEFT5 - Upper left corner of evaluation window 5. */
#define IRIS_MVPL_SIG1_EVALUPPERLEFT5_XEvalUpperLeft5_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT5_XEvalUpperLeft5_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT5_XEvalUpperLeft5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT5_XEvalUpperLeft5_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT5_XEvalUpperLeft5_MASK)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT5_YEvalUpperLeft5_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT5_YEvalUpperLeft5_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT5_YEvalUpperLeft5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT5_YEvalUpperLeft5_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT5_YEvalUpperLeft5_MASK)

/*! @name SIG1_EVALLOWERRIGHT5 - Lower right corner of evaluation window 5. */
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT5_XEvalLowerRight5_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT5_XEvalLowerRight5_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT5_XEvalLowerRight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT5_XEvalLowerRight5_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT5_XEvalLowerRight5_MASK)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT5_YEvalLowerRight5_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT5_YEvalLowerRight5_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT5_YEvalLowerRight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT5_YEvalLowerRight5_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT5_YEvalLowerRight5_MASK)

/*! @name SIG1_SIGCRCREDREF5 - Reference signature of red channel for evaluation window 5. */
#define IRIS_MVPL_SIG1_SIGCRCREDREF5_SigCRCRedRef5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCREDREF5_SigCRCRedRef5_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCREDREF5_SigCRCRedRef5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF5_SigCRCRedRef5_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF5_SigCRCRedRef5_MASK)

/*! @name SIG1_SIGCRCGREENREF5 - Reference signature of green channel for evaluation window 5. */
#define IRIS_MVPL_SIG1_SIGCRCGREENREF5_SigCRCGreenRef5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF5_SigCRCGreenRef5_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF5_SigCRCGreenRef5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF5_SigCRCGreenRef5_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF5_SigCRCGreenRef5_MASK)

/*! @name SIG1_SIGCRCBLUEREF5 - Reference signature of blue channel for evaluation window 5. */
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF5_SigCRCBlueRef5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF5_SigCRCBlueRef5_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF5_SigCRCBlueRef5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF5_SigCRCBlueRef5_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF5_SigCRCBlueRef5_MASK)

/*! @name SIG1_SIGCRCRED5 - Measured signature of red channel for evaluation window 5. */
#define IRIS_MVPL_SIG1_SIGCRCRED5_SigCRCRed5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCRED5_SigCRCRed5_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCRED5_SigCRCRed5(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED5_SigCRCRed5_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED5_SigCRCRed5_MASK)

/*! @name SIG1_SIGCRCGREEN5 - Measured signature of green channel for evaluation window 5. */
#define IRIS_MVPL_SIG1_SIGCRCGREEN5_SigCRCGreen5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREEN5_SigCRCGreen5_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREEN5_SigCRCGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN5_SigCRCGreen5_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN5_SigCRCGreen5_MASK)

/*! @name SIG1_SIGCRCBLUE5 - Measured signature of blue channel for evaluation window 5. */
#define IRIS_MVPL_SIG1_SIGCRCBLUE5_SigCRCBlue5_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUE5_SigCRCBlue5_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUE5_SigCRCBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE5_SigCRCBlue5_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE5_SigCRCBlue5_MASK)

/*! @name SIG1_EVALCONTROL6 - Control settings for evaluation window 6. */
#define IRIS_MVPL_SIG1_EVALCONTROL6_EnEvalWin6_MASK (0x1U)
#define IRIS_MVPL_SIG1_EVALCONTROL6_EnEvalWin6_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALCONTROL6_EnEvalWin6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL6_EnEvalWin6_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL6_EnEvalWin6_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL6_EnCRC6_MASK  (0x2U)
#define IRIS_MVPL_SIG1_EVALCONTROL6_EnCRC6_SHIFT (1U)
#define IRIS_MVPL_SIG1_EVALCONTROL6_EnCRC6(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL6_EnCRC6_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL6_EnCRC6_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL6_AlphaMask6_MASK (0x100U)
#define IRIS_MVPL_SIG1_EVALCONTROL6_AlphaMask6_SHIFT (8U)
#define IRIS_MVPL_SIG1_EVALCONTROL6_AlphaMask6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL6_AlphaMask6_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL6_AlphaMask6_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL6_AlphaInv6_MASK (0x200U)
#define IRIS_MVPL_SIG1_EVALCONTROL6_AlphaInv6_SHIFT (9U)
#define IRIS_MVPL_SIG1_EVALCONTROL6_AlphaInv6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL6_AlphaInv6_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL6_AlphaInv6_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL6_EnLocalPanic6_MASK (0x10000U)
#define IRIS_MVPL_SIG1_EVALCONTROL6_EnLocalPanic6_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALCONTROL6_EnLocalPanic6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL6_EnLocalPanic6_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL6_EnLocalPanic6_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL6_EnGlobalPanic6_MASK (0x20000U)
#define IRIS_MVPL_SIG1_EVALCONTROL6_EnGlobalPanic6_SHIFT (17U)
#define IRIS_MVPL_SIG1_EVALCONTROL6_EnGlobalPanic6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL6_EnGlobalPanic6_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL6_EnGlobalPanic6_MASK)

/*! @name SIG1_EVALUPPERLEFT6 - Upper left corner of evaluation window 6. */
#define IRIS_MVPL_SIG1_EVALUPPERLEFT6_XEvalUpperLeft6_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT6_XEvalUpperLeft6_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT6_XEvalUpperLeft6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT6_XEvalUpperLeft6_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT6_XEvalUpperLeft6_MASK)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT6_YEvalUpperLeft6_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT6_YEvalUpperLeft6_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT6_YEvalUpperLeft6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT6_YEvalUpperLeft6_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT6_YEvalUpperLeft6_MASK)

/*! @name SIG1_EVALLOWERRIGHT6 - Lower right corner of evaluation window 6. */
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT6_XEvalLowerRight6_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT6_XEvalLowerRight6_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT6_XEvalLowerRight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT6_XEvalLowerRight6_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT6_XEvalLowerRight6_MASK)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT6_YEvalLowerRight6_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT6_YEvalLowerRight6_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT6_YEvalLowerRight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT6_YEvalLowerRight6_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT6_YEvalLowerRight6_MASK)

/*! @name SIG1_SIGCRCREDREF6 - Reference signature of red channel for evaluation window 6. */
#define IRIS_MVPL_SIG1_SIGCRCREDREF6_SigCRCRedRef6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCREDREF6_SigCRCRedRef6_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCREDREF6_SigCRCRedRef6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF6_SigCRCRedRef6_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF6_SigCRCRedRef6_MASK)

/*! @name SIG1_SIGCRCGREENREF6 - Reference signature of green channel for evaluation window 6. */
#define IRIS_MVPL_SIG1_SIGCRCGREENREF6_SigCRCGreenRef6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF6_SigCRCGreenRef6_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF6_SigCRCGreenRef6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF6_SigCRCGreenRef6_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF6_SigCRCGreenRef6_MASK)

/*! @name SIG1_SIGCRCBLUEREF6 - Reference signature of blue channel for evaluation window 6. */
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF6_SigCRCBlueRef6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF6_SigCRCBlueRef6_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF6_SigCRCBlueRef6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF6_SigCRCBlueRef6_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF6_SigCRCBlueRef6_MASK)

/*! @name SIG1_SIGCRCRED6 - Measured signature of red channel for evaluation window 6. */
#define IRIS_MVPL_SIG1_SIGCRCRED6_SigCRCRed6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCRED6_SigCRCRed6_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCRED6_SigCRCRed6(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED6_SigCRCRed6_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED6_SigCRCRed6_MASK)

/*! @name SIG1_SIGCRCGREEN6 - Measured signature of green channel for evaluation window 6. */
#define IRIS_MVPL_SIG1_SIGCRCGREEN6_SigCRCGreen6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREEN6_SigCRCGreen6_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREEN6_SigCRCGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN6_SigCRCGreen6_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN6_SigCRCGreen6_MASK)

/*! @name SIG1_SIGCRCBLUE6 - Measured signature of blue channel for evaluation window 6. */
#define IRIS_MVPL_SIG1_SIGCRCBLUE6_SigCRCBlue6_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUE6_SigCRCBlue6_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUE6_SigCRCBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE6_SigCRCBlue6_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE6_SigCRCBlue6_MASK)

/*! @name SIG1_EVALCONTROL7 - Control settings for evaluation window 7. */
#define IRIS_MVPL_SIG1_EVALCONTROL7_EnEvalWin7_MASK (0x1U)
#define IRIS_MVPL_SIG1_EVALCONTROL7_EnEvalWin7_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALCONTROL7_EnEvalWin7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL7_EnEvalWin7_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL7_EnEvalWin7_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL7_EnCRC7_MASK  (0x2U)
#define IRIS_MVPL_SIG1_EVALCONTROL7_EnCRC7_SHIFT (1U)
#define IRIS_MVPL_SIG1_EVALCONTROL7_EnCRC7(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL7_EnCRC7_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL7_EnCRC7_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL7_AlphaMask7_MASK (0x100U)
#define IRIS_MVPL_SIG1_EVALCONTROL7_AlphaMask7_SHIFT (8U)
#define IRIS_MVPL_SIG1_EVALCONTROL7_AlphaMask7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL7_AlphaMask7_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL7_AlphaMask7_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL7_AlphaInv7_MASK (0x200U)
#define IRIS_MVPL_SIG1_EVALCONTROL7_AlphaInv7_SHIFT (9U)
#define IRIS_MVPL_SIG1_EVALCONTROL7_AlphaInv7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL7_AlphaInv7_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL7_AlphaInv7_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL7_EnLocalPanic7_MASK (0x10000U)
#define IRIS_MVPL_SIG1_EVALCONTROL7_EnLocalPanic7_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALCONTROL7_EnLocalPanic7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL7_EnLocalPanic7_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL7_EnLocalPanic7_MASK)
#define IRIS_MVPL_SIG1_EVALCONTROL7_EnGlobalPanic7_MASK (0x20000U)
#define IRIS_MVPL_SIG1_EVALCONTROL7_EnGlobalPanic7_SHIFT (17U)
#define IRIS_MVPL_SIG1_EVALCONTROL7_EnGlobalPanic7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALCONTROL7_EnGlobalPanic7_SHIFT)) & IRIS_MVPL_SIG1_EVALCONTROL7_EnGlobalPanic7_MASK)

/*! @name SIG1_EVALUPPERLEFT7 - Upper left corner of evaluation window 7. */
#define IRIS_MVPL_SIG1_EVALUPPERLEFT7_XEvalUpperLeft7_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT7_XEvalUpperLeft7_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT7_XEvalUpperLeft7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT7_XEvalUpperLeft7_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT7_XEvalUpperLeft7_MASK)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT7_YEvalUpperLeft7_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT7_YEvalUpperLeft7_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALUPPERLEFT7_YEvalUpperLeft7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALUPPERLEFT7_YEvalUpperLeft7_SHIFT)) & IRIS_MVPL_SIG1_EVALUPPERLEFT7_YEvalUpperLeft7_MASK)

/*! @name SIG1_EVALLOWERRIGHT7 - Lower right corner of evaluation window 7. */
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT7_XEvalLowerRight7_MASK (0x3FFFU)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT7_XEvalLowerRight7_SHIFT (0U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT7_XEvalLowerRight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT7_XEvalLowerRight7_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT7_XEvalLowerRight7_MASK)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT7_YEvalLowerRight7_MASK (0x3FFF0000U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT7_YEvalLowerRight7_SHIFT (16U)
#define IRIS_MVPL_SIG1_EVALLOWERRIGHT7_YEvalLowerRight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_EVALLOWERRIGHT7_YEvalLowerRight7_SHIFT)) & IRIS_MVPL_SIG1_EVALLOWERRIGHT7_YEvalLowerRight7_MASK)

/*! @name SIG1_SIGCRCREDREF7 - Reference signature of red channel for evaluation window 7. */
#define IRIS_MVPL_SIG1_SIGCRCREDREF7_SigCRCRedRef7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCREDREF7_SigCRCRedRef7_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCREDREF7_SigCRCRedRef7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCREDREF7_SigCRCRedRef7_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCREDREF7_SigCRCRedRef7_MASK)

/*! @name SIG1_SIGCRCGREENREF7 - Reference signature of green channel for evaluation window 7. */
#define IRIS_MVPL_SIG1_SIGCRCGREENREF7_SigCRCGreenRef7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF7_SigCRCGreenRef7_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREENREF7_SigCRCGreenRef7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREENREF7_SigCRCGreenRef7_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREENREF7_SigCRCGreenRef7_MASK)

/*! @name SIG1_SIGCRCBLUEREF7 - Reference signature of blue channel for evaluation window 7. */
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF7_SigCRCBlueRef7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF7_SigCRCBlueRef7_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUEREF7_SigCRCBlueRef7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUEREF7_SigCRCBlueRef7_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUEREF7_SigCRCBlueRef7_MASK)

/*! @name SIG1_SIGCRCRED7 - Measured signature of red channel for evaluation window 7. */
#define IRIS_MVPL_SIG1_SIGCRCRED7_SigCRCRed7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCRED7_SigCRCRed7_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCRED7_SigCRCRed7(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCRED7_SigCRCRed7_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCRED7_SigCRCRed7_MASK)

/*! @name SIG1_SIGCRCGREEN7 - Measured signature of green channel for evaluation window 7. */
#define IRIS_MVPL_SIG1_SIGCRCGREEN7_SigCRCGreen7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCGREEN7_SigCRCGreen7_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCGREEN7_SigCRCGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCGREEN7_SigCRCGreen7_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCGREEN7_SigCRCGreen7_MASK)

/*! @name SIG1_SIGCRCBLUE7 - Measured signature of blue channel for evaluation window 7. */
#define IRIS_MVPL_SIG1_SIGCRCBLUE7_SigCRCBlue7_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_SIG1_SIGCRCBLUE7_SigCRCBlue7_SHIFT (0U)
#define IRIS_MVPL_SIG1_SIGCRCBLUE7_SigCRCBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SIGCRCBLUE7_SigCRCBlue7_SHIFT)) & IRIS_MVPL_SIG1_SIGCRCBLUE7_SigCRCBlue7_MASK)

/*! @name SIG1_SHADOWLOAD - Shadow load control register. */
#define IRIS_MVPL_SIG1_SHADOWLOAD_ShdLdReq_MASK  (0xFFU)
#define IRIS_MVPL_SIG1_SHADOWLOAD_ShdLdReq_SHIFT (0U)
#define IRIS_MVPL_SIG1_SHADOWLOAD_ShdLdReq(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SHADOWLOAD_ShdLdReq_SHIFT)) & IRIS_MVPL_SIG1_SHADOWLOAD_ShdLdReq_MASK)

/*! @name SIG1_CONTINUOUSMODE - Signature operation mode control. */
#define IRIS_MVPL_SIG1_CONTINUOUSMODE_EnCont_MASK (0x1U)
#define IRIS_MVPL_SIG1_CONTINUOUSMODE_EnCont_SHIFT (0U)
#define IRIS_MVPL_SIG1_CONTINUOUSMODE_EnCont(x)  (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_CONTINUOUSMODE_EnCont_SHIFT)) & IRIS_MVPL_SIG1_CONTINUOUSMODE_EnCont_MASK)

/*! @name SIG1_SOFTWAREKICK - Signature measurement trigger. */
#define IRIS_MVPL_SIG1_SOFTWAREKICK_Kick_MASK    (0x1U)
#define IRIS_MVPL_SIG1_SOFTWAREKICK_Kick_SHIFT   (0U)
#define IRIS_MVPL_SIG1_SOFTWAREKICK_Kick(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_SOFTWAREKICK_Kick_SHIFT)) & IRIS_MVPL_SIG1_SOFTWAREKICK_Kick_MASK)

/*! @name SIG1_STATUS - Module status. */
#define IRIS_MVPL_SIG1_STATUS_StsSigError_MASK   (0xFFU)
#define IRIS_MVPL_SIG1_STATUS_StsSigError_SHIFT  (0U)
#define IRIS_MVPL_SIG1_STATUS_StsSigError(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_STATUS_StsSigError_SHIFT)) & IRIS_MVPL_SIG1_STATUS_StsSigError_MASK)
#define IRIS_MVPL_SIG1_STATUS_StsSigValid_MASK   (0x10000U)
#define IRIS_MVPL_SIG1_STATUS_StsSigValid_SHIFT  (16U)
#define IRIS_MVPL_SIG1_STATUS_StsSigValid(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_STATUS_StsSigValid_SHIFT)) & IRIS_MVPL_SIG1_STATUS_StsSigValid_MASK)
#define IRIS_MVPL_SIG1_STATUS_StsSigIdle_MASK    (0x100000U)
#define IRIS_MVPL_SIG1_STATUS_StsSigIdle_SHIFT   (20U)
#define IRIS_MVPL_SIG1_STATUS_StsSigIdle(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SIG1_STATUS_StsSigIdle_SHIFT)) & IRIS_MVPL_SIG1_STATUS_StsSigIdle_MASK)

/*! @name CAPENGCFG_CAPTUREINPUT0 - Capture status fields. */
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_CaptureMode0_MASK (0x3U)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_CaptureMode0_SHIFT (0U)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_CaptureMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_CaptureMode0_SHIFT)) & IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_CaptureMode0_MASK)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_ITUProtectionOneBitError0_MASK (0x100U)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_ITUProtectionOneBitError0_SHIFT (8U)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_ITUProtectionOneBitError0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_ITUProtectionOneBitError0_SHIFT)) & IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_ITUProtectionOneBitError0_MASK)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_ITUProtectionTwoBitError0_MASK (0x200U)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_ITUProtectionTwoBitError0_SHIFT (9U)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_ITUProtectionTwoBitError0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_ITUProtectionTwoBitError0_SHIFT)) & IRIS_MVPL_CAPENGCFG_CAPTUREINPUT0_ITUProtectionTwoBitError0_MASK)

/*! @name CAPENGCFG_CAPTUREINPUT1 - Capture status fields. */
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_CaptureMode1_MASK (0x3U)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_CaptureMode1_SHIFT (0U)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_CaptureMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_CaptureMode1_SHIFT)) & IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_CaptureMode1_MASK)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_ITUProtectionOneBitError1_MASK (0x100U)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_ITUProtectionOneBitError1_SHIFT (8U)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_ITUProtectionOneBitError1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_ITUProtectionOneBitError1_SHIFT)) & IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_ITUProtectionOneBitError1_MASK)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_ITUProtectionTwoBitError1_MASK (0x200U)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_ITUProtectionTwoBitError1_SHIFT (9U)
#define IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_ITUProtectionTwoBitError1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_ITUProtectionTwoBitError1_SHIFT)) & IRIS_MVPL_CAPENGCFG_CAPTUREINPUT1_ITUProtectionTwoBitError1_MASK)

/*! @name FRAMECAP4_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FRAMECAP4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FRAMECAP4_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FRAMECAP4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FRAMECAP4_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FRAMECAP4_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FRAMECAP4_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FRAMECAP4_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FRAMECAP4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FRAMECAP4_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FRAMECAP4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FRAMECAP4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FRAMECAP4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FRAMECAP4_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FRAMECAP4_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FRAMECAP4_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FRAMECAP4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FRAMECAP4_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FRAMECAP4_CTR - FrameCap Control Register */
#define IRIS_MVPL_FRAMECAP4_CTR_Cen_MASK         (0x1U)
#define IRIS_MVPL_FRAMECAP4_CTR_Cen_SHIFT        (0U)
#define IRIS_MVPL_FRAMECAP4_CTR_Cen(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_CTR_Cen_SHIFT)) & IRIS_MVPL_FRAMECAP4_CTR_Cen_MASK)

/*! @name FRAMECAP4_SPR - FrameCap Sync Polarity Register */
#define IRIS_MVPL_FRAMECAP4_SPR_PolEn_MASK       (0x1U)
#define IRIS_MVPL_FRAMECAP4_SPR_PolEn_SHIFT      (0U)
#define IRIS_MVPL_FRAMECAP4_SPR_PolEn(x)         (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_SPR_PolEn_SHIFT)) & IRIS_MVPL_FRAMECAP4_SPR_PolEn_MASK)
#define IRIS_MVPL_FRAMECAP4_SPR_PolHs_MASK       (0x2U)
#define IRIS_MVPL_FRAMECAP4_SPR_PolHs_SHIFT      (1U)
#define IRIS_MVPL_FRAMECAP4_SPR_PolHs(x)         (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_SPR_PolHs_SHIFT)) & IRIS_MVPL_FRAMECAP4_SPR_PolHs_MASK)
#define IRIS_MVPL_FRAMECAP4_SPR_PolVs_MASK       (0x4U)
#define IRIS_MVPL_FRAMECAP4_SPR_PolVs_SHIFT      (2U)
#define IRIS_MVPL_FRAMECAP4_SPR_PolVs(x)         (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_SPR_PolVs_SHIFT)) & IRIS_MVPL_FRAMECAP4_SPR_PolVs_MASK)

/*! @name FRAMECAP4_FDR - Frame dimension (progressive frame and field 0). */
#define IRIS_MVPL_FRAMECAP4_FDR_Width_MASK       (0x3FFFU)
#define IRIS_MVPL_FRAMECAP4_FDR_Width_SHIFT      (0U)
#define IRIS_MVPL_FRAMECAP4_FDR_Width(x)         (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_FDR_Width_SHIFT)) & IRIS_MVPL_FRAMECAP4_FDR_Width_MASK)
#define IRIS_MVPL_FRAMECAP4_FDR_Height_MASK      (0x3FFF0000U)
#define IRIS_MVPL_FRAMECAP4_FDR_Height_SHIFT     (16U)
#define IRIS_MVPL_FRAMECAP4_FDR_Height(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_FDR_Height_SHIFT)) & IRIS_MVPL_FRAMECAP4_FDR_Height_MASK)

/*! @name FRAMECAP4_FDR1 - Frame dimension (field 1). */
#define IRIS_MVPL_FRAMECAP4_FDR1_Height1_MASK    (0x3FFF0000U)
#define IRIS_MVPL_FRAMECAP4_FDR1_Height1_SHIFT   (16U)
#define IRIS_MVPL_FRAMECAP4_FDR1_Height1(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_FDR1_Height1_SHIFT)) & IRIS_MVPL_FRAMECAP4_FDR1_Height1_MASK)

/*! @name FRAMECAP4_KCR - FrameCap Kick Config Register */
#define IRIS_MVPL_FRAMECAP4_KCR_KickDel_MASK     (0xFFFFFFFU)
#define IRIS_MVPL_FRAMECAP4_KCR_KickDel_SHIFT    (0U)
#define IRIS_MVPL_FRAMECAP4_KCR_KickDel(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_KCR_KickDel_SHIFT)) & IRIS_MVPL_FRAMECAP4_KCR_KickDel_MASK)

/*! @name FRAMECAP4_SCR - FrameCap Sync Config Register */
#define IRIS_MVPL_FRAMECAP4_SCR_Fus_MASK         (0xFU)
#define IRIS_MVPL_FRAMECAP4_SCR_Fus_SHIFT        (0U)
#define IRIS_MVPL_FRAMECAP4_SCR_Fus(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_SCR_Fus_SHIFT)) & IRIS_MVPL_FRAMECAP4_SCR_Fus_MASK)

/*! @name FRAMECAP4_STS - FrameCap Status Register. Shows current status of the FrameCap module. */
#define IRIS_MVPL_FRAMECAP4_STS_FifoFull_MASK    (0x1U)
#define IRIS_MVPL_FRAMECAP4_STS_FifoFull_SHIFT   (0U)
#define IRIS_MVPL_FRAMECAP4_STS_FifoFull(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_STS_FifoFull_SHIFT)) & IRIS_MVPL_FRAMECAP4_STS_FifoFull_MASK)
#define IRIS_MVPL_FRAMECAP4_STS_VsLate_MASK      (0x2U)
#define IRIS_MVPL_FRAMECAP4_STS_VsLate_SHIFT     (1U)
#define IRIS_MVPL_FRAMECAP4_STS_VsLate(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_STS_VsLate_SHIFT)) & IRIS_MVPL_FRAMECAP4_STS_VsLate_MASK)
#define IRIS_MVPL_FRAMECAP4_STS_VsEarly_MASK     (0x4U)
#define IRIS_MVPL_FRAMECAP4_STS_VsEarly_SHIFT    (2U)
#define IRIS_MVPL_FRAMECAP4_STS_VsEarly(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_STS_VsEarly_SHIFT)) & IRIS_MVPL_FRAMECAP4_STS_VsEarly_MASK)
#define IRIS_MVPL_FRAMECAP4_STS_SyncStat_MASK    (0x100U)
#define IRIS_MVPL_FRAMECAP4_STS_SyncStat_SHIFT   (8U)
#define IRIS_MVPL_FRAMECAP4_STS_SyncStat(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_STS_SyncStat_SHIFT)) & IRIS_MVPL_FRAMECAP4_STS_SyncStat_MASK)

/*! @name FRAMECAP4_STSCLR - FrameCap Status Clear Register. Clears the locked status bits in Sts register. */
#define IRIS_MVPL_FRAMECAP4_STSCLR_ClrStat_MASK  (0x1U)
#define IRIS_MVPL_FRAMECAP4_STSCLR_ClrStat_SHIFT (0U)
#define IRIS_MVPL_FRAMECAP4_STSCLR_ClrStat(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_STSCLR_ClrStat_SHIFT)) & IRIS_MVPL_FRAMECAP4_STSCLR_ClrStat_MASK)

/*! @name FRAMECAP4_FRCNT - FrameCap Frame Rate Count Register. */
#define IRIS_MVPL_FRAMECAP4_FRCNT_FRCount_MASK   (0xFFFFFFFFU)
#define IRIS_MVPL_FRAMECAP4_FRCNT_FRCount_SHIFT  (0U)
#define IRIS_MVPL_FRAMECAP4_FRCNT_FRCount(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_FRCNT_FRCount_SHIFT)) & IRIS_MVPL_FRAMECAP4_FRCNT_FRCount_MASK)

/*! @name FRAMECAP4_FRLINECOUNT - FrameCap Line Counter register. */
#define IRIS_MVPL_FRAMECAP4_FRLINECOUNT_FRLineCount_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMECAP4_FRLINECOUNT_FRLineCount_SHIFT (0U)
#define IRIS_MVPL_FRAMECAP4_FRLINECOUNT_FRLineCount(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP4_FRLINECOUNT_FRLineCount_SHIFT)) & IRIS_MVPL_FRAMECAP4_FRLINECOUNT_FRLineCount_MASK)

/*! @name FRAMECAP5_LOCKUNLOCK - Register to change the protection status of this address block. */
#define IRIS_MVPL_FRAMECAP5_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_FRAMECAP5_LOCKUNLOCK_LockUnlock_SHIFT (0U)
#define IRIS_MVPL_FRAMECAP5_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FRAMECAP5_LOCKUNLOCK_LockUnlock_MASK)

/*! @name FRAMECAP5_LOCKSTATUS - Protection status of this address block. */
#define IRIS_MVPL_FRAMECAP5_LOCKSTATUS_LockStatus_MASK (0x1U)
#define IRIS_MVPL_FRAMECAP5_LOCKSTATUS_LockStatus_SHIFT (0U)
#define IRIS_MVPL_FRAMECAP5_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FRAMECAP5_LOCKSTATUS_LockStatus_MASK)
#define IRIS_MVPL_FRAMECAP5_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
#define IRIS_MVPL_FRAMECAP5_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
#define IRIS_MVPL_FRAMECAP5_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FRAMECAP5_LOCKSTATUS_PrivilegeStatus_MASK)
#define IRIS_MVPL_FRAMECAP5_LOCKSTATUS_FreezeStatus_MASK (0x100U)
#define IRIS_MVPL_FRAMECAP5_LOCKSTATUS_FreezeStatus_SHIFT (8U)
#define IRIS_MVPL_FRAMECAP5_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FRAMECAP5_LOCKSTATUS_FreezeStatus_MASK)

/*! @name FRAMECAP5_CTR - FrameCap Control Register */
#define IRIS_MVPL_FRAMECAP5_CTR_Cen_MASK         (0x1U)
#define IRIS_MVPL_FRAMECAP5_CTR_Cen_SHIFT        (0U)
#define IRIS_MVPL_FRAMECAP5_CTR_Cen(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_CTR_Cen_SHIFT)) & IRIS_MVPL_FRAMECAP5_CTR_Cen_MASK)

/*! @name FRAMECAP5_SPR - FrameCap Sync Polarity Register */
#define IRIS_MVPL_FRAMECAP5_SPR_PolEn_MASK       (0x1U)
#define IRIS_MVPL_FRAMECAP5_SPR_PolEn_SHIFT      (0U)
#define IRIS_MVPL_FRAMECAP5_SPR_PolEn(x)         (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_SPR_PolEn_SHIFT)) & IRIS_MVPL_FRAMECAP5_SPR_PolEn_MASK)
#define IRIS_MVPL_FRAMECAP5_SPR_PolHs_MASK       (0x2U)
#define IRIS_MVPL_FRAMECAP5_SPR_PolHs_SHIFT      (1U)
#define IRIS_MVPL_FRAMECAP5_SPR_PolHs(x)         (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_SPR_PolHs_SHIFT)) & IRIS_MVPL_FRAMECAP5_SPR_PolHs_MASK)
#define IRIS_MVPL_FRAMECAP5_SPR_PolVs_MASK       (0x4U)
#define IRIS_MVPL_FRAMECAP5_SPR_PolVs_SHIFT      (2U)
#define IRIS_MVPL_FRAMECAP5_SPR_PolVs(x)         (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_SPR_PolVs_SHIFT)) & IRIS_MVPL_FRAMECAP5_SPR_PolVs_MASK)

/*! @name FRAMECAP5_FDR - Frame dimension (progressive frame and field 0). */
#define IRIS_MVPL_FRAMECAP5_FDR_Width_MASK       (0x3FFFU)
#define IRIS_MVPL_FRAMECAP5_FDR_Width_SHIFT      (0U)
#define IRIS_MVPL_FRAMECAP5_FDR_Width(x)         (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_FDR_Width_SHIFT)) & IRIS_MVPL_FRAMECAP5_FDR_Width_MASK)
#define IRIS_MVPL_FRAMECAP5_FDR_Height_MASK      (0x3FFF0000U)
#define IRIS_MVPL_FRAMECAP5_FDR_Height_SHIFT     (16U)
#define IRIS_MVPL_FRAMECAP5_FDR_Height(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_FDR_Height_SHIFT)) & IRIS_MVPL_FRAMECAP5_FDR_Height_MASK)

/*! @name FRAMECAP5_FDR1 - Frame dimension (field 1). */
#define IRIS_MVPL_FRAMECAP5_FDR1_Height1_MASK    (0x3FFF0000U)
#define IRIS_MVPL_FRAMECAP5_FDR1_Height1_SHIFT   (16U)
#define IRIS_MVPL_FRAMECAP5_FDR1_Height1(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_FDR1_Height1_SHIFT)) & IRIS_MVPL_FRAMECAP5_FDR1_Height1_MASK)

/*! @name FRAMECAP5_KCR - FrameCap Kick Config Register */
#define IRIS_MVPL_FRAMECAP5_KCR_KickDel_MASK     (0xFFFFFFFU)
#define IRIS_MVPL_FRAMECAP5_KCR_KickDel_SHIFT    (0U)
#define IRIS_MVPL_FRAMECAP5_KCR_KickDel(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_KCR_KickDel_SHIFT)) & IRIS_MVPL_FRAMECAP5_KCR_KickDel_MASK)

/*! @name FRAMECAP5_SCR - FrameCap Sync Config Register */
#define IRIS_MVPL_FRAMECAP5_SCR_Fus_MASK         (0xFU)
#define IRIS_MVPL_FRAMECAP5_SCR_Fus_SHIFT        (0U)
#define IRIS_MVPL_FRAMECAP5_SCR_Fus(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_SCR_Fus_SHIFT)) & IRIS_MVPL_FRAMECAP5_SCR_Fus_MASK)

/*! @name FRAMECAP5_STS - FrameCap Status Register. Shows current status of the FrameCap module. */
#define IRIS_MVPL_FRAMECAP5_STS_FifoFull_MASK    (0x1U)
#define IRIS_MVPL_FRAMECAP5_STS_FifoFull_SHIFT   (0U)
#define IRIS_MVPL_FRAMECAP5_STS_FifoFull(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_STS_FifoFull_SHIFT)) & IRIS_MVPL_FRAMECAP5_STS_FifoFull_MASK)
#define IRIS_MVPL_FRAMECAP5_STS_VsLate_MASK      (0x2U)
#define IRIS_MVPL_FRAMECAP5_STS_VsLate_SHIFT     (1U)
#define IRIS_MVPL_FRAMECAP5_STS_VsLate(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_STS_VsLate_SHIFT)) & IRIS_MVPL_FRAMECAP5_STS_VsLate_MASK)
#define IRIS_MVPL_FRAMECAP5_STS_VsEarly_MASK     (0x4U)
#define IRIS_MVPL_FRAMECAP5_STS_VsEarly_SHIFT    (2U)
#define IRIS_MVPL_FRAMECAP5_STS_VsEarly(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_STS_VsEarly_SHIFT)) & IRIS_MVPL_FRAMECAP5_STS_VsEarly_MASK)
#define IRIS_MVPL_FRAMECAP5_STS_SyncStat_MASK    (0x100U)
#define IRIS_MVPL_FRAMECAP5_STS_SyncStat_SHIFT   (8U)
#define IRIS_MVPL_FRAMECAP5_STS_SyncStat(x)      (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_STS_SyncStat_SHIFT)) & IRIS_MVPL_FRAMECAP5_STS_SyncStat_MASK)

/*! @name FRAMECAP5_STSCLR - FrameCap Status Clear Register. Clears the locked status bits in Sts register. */
#define IRIS_MVPL_FRAMECAP5_STSCLR_ClrStat_MASK  (0x1U)
#define IRIS_MVPL_FRAMECAP5_STSCLR_ClrStat_SHIFT (0U)
#define IRIS_MVPL_FRAMECAP5_STSCLR_ClrStat(x)    (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_STSCLR_ClrStat_SHIFT)) & IRIS_MVPL_FRAMECAP5_STSCLR_ClrStat_MASK)

/*! @name FRAMECAP5_FRCNT - FrameCap Frame Rate Count Register. */
#define IRIS_MVPL_FRAMECAP5_FRCNT_FRCount_MASK   (0xFFFFFFFFU)
#define IRIS_MVPL_FRAMECAP5_FRCNT_FRCount_SHIFT  (0U)
#define IRIS_MVPL_FRAMECAP5_FRCNT_FRCount(x)     (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_FRCNT_FRCount_SHIFT)) & IRIS_MVPL_FRAMECAP5_FRCNT_FRCount_MASK)

/*! @name FRAMECAP5_FRLINECOUNT - FrameCap Line Counter register. */
#define IRIS_MVPL_FRAMECAP5_FRLINECOUNT_FRLineCount_MASK (0x3FFFU)
#define IRIS_MVPL_FRAMECAP5_FRLINECOUNT_FRLineCount_SHIFT (0U)
#define IRIS_MVPL_FRAMECAP5_FRLINECOUNT_FRLineCount(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMECAP5_FRLINECOUNT_FRLineCount_SHIFT)) & IRIS_MVPL_FRAMECAP5_FRLINECOUNT_FRLineCount_MASK)

/*! @name ANALYSER4_MON_RGB_CTRL - Configuration of the RGB sync signals and timing. */
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_timmon_en_MASK (0x1U)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_timmon_en_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_timmon_en(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_timmon_en_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_timmon_en_MASK)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_wdg_en_MASK (0x2U)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_wdg_en_SHIFT (1U)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_wdg_en(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_wdg_en_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_wdg_en_MASK)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_mode_clear_MASK (0x10000U)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_mode_clear_SHIFT (16U)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_mode_clear(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_mode_clear_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_mode_clear_MASK)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_pol_clear_MASK (0x20000U)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_pol_clear_SHIFT (17U)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_pol_clear(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_pol_clear_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_pol_clear_MASK)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_tim_clear_MASK (0x40000U)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_tim_clear_SHIFT (18U)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_tim_clear(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_tim_clear_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_tim_clear_MASK)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_pixel_clear_MASK (0x80000U)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_pixel_clear_SHIFT (19U)
#define IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_pixel_clear(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_pixel_clear_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_RGB_CTRL_pixel_clear_MASK)

/*! @name ANALYSER4_MON_THRESH_TIM - Configures threshold for stability and jitter check. */
#define IRIS_MVPL_ANALYSER4_MON_THRESH_TIM_tim_stable_thresh_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER4_MON_THRESH_TIM_tim_stable_thresh_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_THRESH_TIM_tim_stable_thresh(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_THRESH_TIM_tim_stable_thresh_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_THRESH_TIM_tim_stable_thresh_MASK)
#define IRIS_MVPL_ANALYSER4_MON_THRESH_TIM_tim_jitter_thresh_MASK (0xFFFF0000U)
#define IRIS_MVPL_ANALYSER4_MON_THRESH_TIM_tim_jitter_thresh_SHIFT (16U)
#define IRIS_MVPL_ANALYSER4_MON_THRESH_TIM_tim_jitter_thresh(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_THRESH_TIM_tim_jitter_thresh_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_THRESH_TIM_tim_jitter_thresh_MASK)

/*! @name ANALYSER4_MON_THRESH_POL - Configures the threshold for polarity detection. */
#define IRIS_MVPL_ANALYSER4_MON_THRESH_POL_pol_tout_thresh_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER4_MON_THRESH_POL_pol_tout_thresh_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_THRESH_POL_pol_tout_thresh(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_THRESH_POL_pol_tout_thresh_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_THRESH_POL_pol_tout_thresh_MASK)

/*! @name ANALYSER4_MON_THRESH_MODE - Configures the threshold for mode detection. */
#define IRIS_MVPL_ANALYSER4_MON_THRESH_MODE_mode_tout_thresh_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_ANALYSER4_MON_THRESH_MODE_mode_tout_thresh_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_THRESH_MODE_mode_tout_thresh(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_THRESH_MODE_mode_tout_thresh_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_THRESH_MODE_mode_tout_thresh_MASK)

/*! @name ANALYSER4_MON_MODE_STATUS - Shows the detected mode of the RGB sync signals. */
#define IRIS_MVPL_ANALYSER4_MON_MODE_STATUS_mode_sync_MASK (0x3U)
#define IRIS_MVPL_ANALYSER4_MON_MODE_STATUS_mode_sync_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_MODE_STATUS_mode_sync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_MODE_STATUS_mode_sync_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_MODE_STATUS_mode_sync_MASK)
#define IRIS_MVPL_ANALYSER4_MON_MODE_STATUS_mode_sync_new_MASK (0x10000U)
#define IRIS_MVPL_ANALYSER4_MON_MODE_STATUS_mode_sync_new_SHIFT (16U)
#define IRIS_MVPL_ANALYSER4_MON_MODE_STATUS_mode_sync_new(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_MODE_STATUS_mode_sync_new_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_MODE_STATUS_mode_sync_new_MASK)

/*! @name ANALYSER4_MON_POL_STATUS - Shows the detected polarity of the RGB sync signals. */
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_stat_MASK (0x3U)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_stat_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_stat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_stat_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_stat_MASK)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_de_MASK (0x100U)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_de_SHIFT (8U)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_de(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_de_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_de_MASK)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_vsync_MASK (0x200U)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_vsync_SHIFT (9U)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_vsync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_vsync_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_vsync_MASK)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_hsync_MASK (0x400U)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_hsync_SHIFT (10U)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_hsync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_hsync_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_hsync_MASK)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_hsync_shift_MASK (0x800U)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_hsync_shift_SHIFT (11U)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_hsync_shift(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_hsync_shift_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_hsync_shift_MASK)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_lost_MASK (0x10000U)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_lost_SHIFT (16U)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_lost(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_lost_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_lost_MASK)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_cnt_MASK (0xFF000000U)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_cnt_SHIFT (24U)
#define IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_cnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_cnt_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_POL_STATUS_pol_det_cnt_MASK)

/*! @name ANALYSER4_MON_STATUS - Shows the stability/jitter of horizontal/vertical total and active parameters. */
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vactive_stable_MASK (0x1U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vactive_stable_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vactive_stable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vactive_stable_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vactive_stable_MASK)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vtotal_stable_MASK (0x2U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vtotal_stable_SHIFT (1U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vtotal_stable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vtotal_stable_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vtotal_stable_MASK)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_hactive_stable_MASK (0x4U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_hactive_stable_SHIFT (2U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_hactive_stable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_STATUS_tim_hactive_stable_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_STATUS_tim_hactive_stable_MASK)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_htotal_stable_MASK (0x8U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_htotal_stable_SHIFT (3U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_htotal_stable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_STATUS_tim_htotal_stable_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_STATUS_tim_htotal_stable_MASK)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vactive_jitter_MASK (0x10000U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vactive_jitter_SHIFT (16U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vactive_jitter(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vactive_jitter_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vactive_jitter_MASK)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vtotal_jitter_MASK (0x20000U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vtotal_jitter_SHIFT (17U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vtotal_jitter(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vtotal_jitter_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_STATUS_tim_vtotal_jitter_MASK)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_hactive_jitter_MASK (0x40000U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_hactive_jitter_SHIFT (18U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_hactive_jitter(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_STATUS_tim_hactive_jitter_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_STATUS_tim_hactive_jitter_MASK)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_htotal_jitter_MASK (0x80000U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_htotal_jitter_SHIFT (19U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_htotal_jitter(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_STATUS_tim_htotal_jitter_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_STATUS_tim_htotal_jitter_MASK)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_det_MASK (0x80000000U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_det_SHIFT (31U)
#define IRIS_MVPL_ANALYSER4_MON_STATUS_tim_det(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_STATUS_tim_det_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_STATUS_tim_det_MASK)

/*! @name ANALYSER4_MON_VAL_HTOTAL - Detected timing parameter horizontal total pixel. */
#define IRIS_MVPL_ANALYSER4_MON_VAL_HTOTAL_tim_htotal_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER4_MON_VAL_HTOTAL_tim_htotal_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_VAL_HTOTAL_tim_htotal(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_VAL_HTOTAL_tim_htotal_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_VAL_HTOTAL_tim_htotal_MASK)

/*! @name ANALYSER4_MON_VAL_HACTIVE - Detected timing parameter horizontal active pixels. */
#define IRIS_MVPL_ANALYSER4_MON_VAL_HACTIVE_tim_hactive_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER4_MON_VAL_HACTIVE_tim_hactive_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_VAL_HACTIVE_tim_hactive(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_VAL_HACTIVE_tim_hactive_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_VAL_HACTIVE_tim_hactive_MASK)

/*! @name ANALYSER4_MON_VAL_HBACK - Detected timing parameter horizontal back porch. */
#define IRIS_MVPL_ANALYSER4_MON_VAL_HBACK_tim_hback_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER4_MON_VAL_HBACK_tim_hback_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_VAL_HBACK_tim_hback(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_VAL_HBACK_tim_hback_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_VAL_HBACK_tim_hback_MASK)

/*! @name ANALYSER4_TIM_VAL_HFRONT - Detected timing parameter horizontal front porch. */
#define IRIS_MVPL_ANALYSER4_TIM_VAL_HFRONT_tim_hfront_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER4_TIM_VAL_HFRONT_tim_hfront_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_TIM_VAL_HFRONT_tim_hfront(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_TIM_VAL_HFRONT_tim_hfront_SHIFT)) & IRIS_MVPL_ANALYSER4_TIM_VAL_HFRONT_tim_hfront_MASK)

/*! @name ANALYSER4_MON_VAL_VTOTAL - Detected timing parameter vertical total lines. */
#define IRIS_MVPL_ANALYSER4_MON_VAL_VTOTAL_tim_vtotal_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER4_MON_VAL_VTOTAL_tim_vtotal_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_VAL_VTOTAL_tim_vtotal(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_VAL_VTOTAL_tim_vtotal_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_VAL_VTOTAL_tim_vtotal_MASK)

/*! @name ANALYSER4_MON_VAL_VACTIVE - Detected timing parameter vertical active lines. */
#define IRIS_MVPL_ANALYSER4_MON_VAL_VACTIVE_tim_vactive_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER4_MON_VAL_VACTIVE_tim_vactive_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_VAL_VACTIVE_tim_vactive(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_VAL_VACTIVE_tim_vactive_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_VAL_VACTIVE_tim_vactive_MASK)

/*! @name ANALYSER4_MON_VAL_VBACK - Detected timing parameter vertical back porch. */
#define IRIS_MVPL_ANALYSER4_MON_VAL_VBACK_tim_vback_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER4_MON_VAL_VBACK_tim_vback_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_VAL_VBACK_tim_vback(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_VAL_VBACK_tim_vback_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_VAL_VBACK_tim_vback_MASK)

/*! @name ANALYSER4_MON_VAL_VFRONT - Detected timing parameter vertical front porch. */
#define IRIS_MVPL_ANALYSER4_MON_VAL_VFRONT_tim_vfront_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER4_MON_VAL_VFRONT_tim_vfront_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_VAL_VFRONT_tim_vfront(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_VAL_VFRONT_tim_vfront_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_VAL_VFRONT_tim_vfront_MASK)

/*! @name ANALYSER4_MON_VAL_TOTAL_CLK - Detected timing parameter total clocks. */
#define IRIS_MVPL_ANALYSER4_MON_VAL_TOTAL_CLK_tim_vtotal_clk_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_ANALYSER4_MON_VAL_TOTAL_CLK_tim_vtotal_clk_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_VAL_TOTAL_CLK_tim_vtotal_clk(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_VAL_TOTAL_CLK_tim_vtotal_clk_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_VAL_TOTAL_CLK_tim_vtotal_clk_MASK)

/*! @name ANALYSER4_MON_PIXEL_CTRL - Configure RGB pixel observation. */
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_mode_MASK (0x7U)
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_mode_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_mode_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_mode_MASK)
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_red_MASK (0xFF00U)
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_red_SHIFT (8U)
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_red(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_red_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_red_MASK)
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_green_MASK (0xFF0000U)
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_green_SHIFT (16U)
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_green(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_green_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_green_MASK)
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_blue_MASK (0xFF000000U)
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_blue_SHIFT (24U)
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_blue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_blue_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_PIXEL_CTRL_mon_pixel_blue_MASK)

/*! @name ANALYSER4_MON_PIXEL_STAT - Status RGB pixel observation. */
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_STAT_mon_pixel_error_cnt_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_STAT_mon_pixel_error_cnt_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_PIXEL_STAT_mon_pixel_error_cnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_PIXEL_STAT_mon_pixel_error_cnt_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_PIXEL_STAT_mon_pixel_error_cnt_MASK)

/*! @name ANALYSER4_MON_WATCHDOG_TOUT - Configure sync-activity timeout (watchdog). */
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_TOUT_wdg_hsync_tout_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_TOUT_wdg_hsync_tout_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_TOUT_wdg_hsync_tout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_WATCHDOG_TOUT_wdg_hsync_tout_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_WATCHDOG_TOUT_wdg_hsync_tout_MASK)
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_TOUT_wdg_vsync_tout_MASK (0xFFFF0000U)
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_TOUT_wdg_vsync_tout_SHIFT (16U)
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_TOUT_wdg_vsync_tout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_WATCHDOG_TOUT_wdg_vsync_tout_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_WATCHDOG_TOUT_wdg_vsync_tout_MASK)

/*! @name ANALYSER4_MON_WATCHDOG_STAT - Detected timing parameter total clocks. */
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_hsync_inactive_MASK (0x1U)
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_hsync_inactive_SHIFT (0U)
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_hsync_inactive(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_hsync_inactive_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_hsync_inactive_MASK)
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_vsync_inactive_MASK (0x2U)
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_vsync_inactive_SHIFT (1U)
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_vsync_inactive(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_vsync_inactive_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_vsync_inactive_MASK)
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_de_inactive_MASK (0x4U)
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_de_inactive_SHIFT (2U)
#define IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_de_inactive(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_de_inactive_SHIFT)) & IRIS_MVPL_ANALYSER4_MON_WATCHDOG_STAT_wdg_de_inactive_MASK)

/*! @name ANALYSER5_MON_RGB_CTRL - Configuration of the RGB sync signals and timing. */
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_timmon_en_MASK (0x1U)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_timmon_en_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_timmon_en(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_timmon_en_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_timmon_en_MASK)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_wdg_en_MASK (0x2U)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_wdg_en_SHIFT (1U)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_wdg_en(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_wdg_en_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_wdg_en_MASK)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_mode_clear_MASK (0x10000U)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_mode_clear_SHIFT (16U)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_mode_clear(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_mode_clear_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_mode_clear_MASK)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_pol_clear_MASK (0x20000U)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_pol_clear_SHIFT (17U)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_pol_clear(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_pol_clear_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_pol_clear_MASK)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_tim_clear_MASK (0x40000U)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_tim_clear_SHIFT (18U)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_tim_clear(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_tim_clear_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_tim_clear_MASK)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_pixel_clear_MASK (0x80000U)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_pixel_clear_SHIFT (19U)
#define IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_pixel_clear(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_pixel_clear_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_RGB_CTRL_pixel_clear_MASK)

/*! @name ANALYSER5_MON_THRESH_TIM - Configures threshold for stability and jitter check. */
#define IRIS_MVPL_ANALYSER5_MON_THRESH_TIM_tim_stable_thresh_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER5_MON_THRESH_TIM_tim_stable_thresh_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_THRESH_TIM_tim_stable_thresh(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_THRESH_TIM_tim_stable_thresh_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_THRESH_TIM_tim_stable_thresh_MASK)
#define IRIS_MVPL_ANALYSER5_MON_THRESH_TIM_tim_jitter_thresh_MASK (0xFFFF0000U)
#define IRIS_MVPL_ANALYSER5_MON_THRESH_TIM_tim_jitter_thresh_SHIFT (16U)
#define IRIS_MVPL_ANALYSER5_MON_THRESH_TIM_tim_jitter_thresh(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_THRESH_TIM_tim_jitter_thresh_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_THRESH_TIM_tim_jitter_thresh_MASK)

/*! @name ANALYSER5_MON_THRESH_POL - Configures the threshold for polarity detection. */
#define IRIS_MVPL_ANALYSER5_MON_THRESH_POL_pol_tout_thresh_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER5_MON_THRESH_POL_pol_tout_thresh_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_THRESH_POL_pol_tout_thresh(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_THRESH_POL_pol_tout_thresh_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_THRESH_POL_pol_tout_thresh_MASK)

/*! @name ANALYSER5_MON_THRESH_MODE - Configures the threshold for mode detection. */
#define IRIS_MVPL_ANALYSER5_MON_THRESH_MODE_mode_tout_thresh_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_ANALYSER5_MON_THRESH_MODE_mode_tout_thresh_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_THRESH_MODE_mode_tout_thresh(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_THRESH_MODE_mode_tout_thresh_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_THRESH_MODE_mode_tout_thresh_MASK)

/*! @name ANALYSER5_MON_MODE_STATUS - Shows the detected mode of the RGB sync signals. */
#define IRIS_MVPL_ANALYSER5_MON_MODE_STATUS_mode_sync_MASK (0x3U)
#define IRIS_MVPL_ANALYSER5_MON_MODE_STATUS_mode_sync_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_MODE_STATUS_mode_sync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_MODE_STATUS_mode_sync_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_MODE_STATUS_mode_sync_MASK)
#define IRIS_MVPL_ANALYSER5_MON_MODE_STATUS_mode_sync_new_MASK (0x10000U)
#define IRIS_MVPL_ANALYSER5_MON_MODE_STATUS_mode_sync_new_SHIFT (16U)
#define IRIS_MVPL_ANALYSER5_MON_MODE_STATUS_mode_sync_new(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_MODE_STATUS_mode_sync_new_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_MODE_STATUS_mode_sync_new_MASK)

/*! @name ANALYSER5_MON_POL_STATUS - Shows the detected polarity of the RGB sync signals. */
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_stat_MASK (0x3U)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_stat_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_stat(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_stat_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_stat_MASK)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_de_MASK (0x100U)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_de_SHIFT (8U)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_de(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_de_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_de_MASK)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_vsync_MASK (0x200U)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_vsync_SHIFT (9U)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_vsync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_vsync_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_vsync_MASK)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_hsync_MASK (0x400U)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_hsync_SHIFT (10U)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_hsync(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_hsync_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_hsync_MASK)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_hsync_shift_MASK (0x800U)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_hsync_shift_SHIFT (11U)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_hsync_shift(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_hsync_shift_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_hsync_shift_MASK)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_lost_MASK (0x10000U)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_lost_SHIFT (16U)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_lost(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_lost_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_lost_MASK)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_cnt_MASK (0xFF000000U)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_cnt_SHIFT (24U)
#define IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_cnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_cnt_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_POL_STATUS_pol_det_cnt_MASK)

/*! @name ANALYSER5_MON_STATUS - Shows the stability/jitter of horizontal/vertical total and active parameters. */
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vactive_stable_MASK (0x1U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vactive_stable_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vactive_stable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vactive_stable_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vactive_stable_MASK)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vtotal_stable_MASK (0x2U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vtotal_stable_SHIFT (1U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vtotal_stable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vtotal_stable_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vtotal_stable_MASK)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_hactive_stable_MASK (0x4U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_hactive_stable_SHIFT (2U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_hactive_stable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_STATUS_tim_hactive_stable_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_STATUS_tim_hactive_stable_MASK)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_htotal_stable_MASK (0x8U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_htotal_stable_SHIFT (3U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_htotal_stable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_STATUS_tim_htotal_stable_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_STATUS_tim_htotal_stable_MASK)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vactive_jitter_MASK (0x10000U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vactive_jitter_SHIFT (16U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vactive_jitter(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vactive_jitter_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vactive_jitter_MASK)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vtotal_jitter_MASK (0x20000U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vtotal_jitter_SHIFT (17U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vtotal_jitter(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vtotal_jitter_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_STATUS_tim_vtotal_jitter_MASK)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_hactive_jitter_MASK (0x40000U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_hactive_jitter_SHIFT (18U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_hactive_jitter(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_STATUS_tim_hactive_jitter_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_STATUS_tim_hactive_jitter_MASK)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_htotal_jitter_MASK (0x80000U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_htotal_jitter_SHIFT (19U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_htotal_jitter(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_STATUS_tim_htotal_jitter_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_STATUS_tim_htotal_jitter_MASK)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_det_MASK (0x80000000U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_det_SHIFT (31U)
#define IRIS_MVPL_ANALYSER5_MON_STATUS_tim_det(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_STATUS_tim_det_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_STATUS_tim_det_MASK)

/*! @name ANALYSER5_MON_VAL_HTOTAL - Detected timing parameter horizontal total pixel. */
#define IRIS_MVPL_ANALYSER5_MON_VAL_HTOTAL_tim_htotal_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER5_MON_VAL_HTOTAL_tim_htotal_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_VAL_HTOTAL_tim_htotal(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_VAL_HTOTAL_tim_htotal_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_VAL_HTOTAL_tim_htotal_MASK)

/*! @name ANALYSER5_MON_VAL_HACTIVE - Detected timing parameter horizontal active pixels. */
#define IRIS_MVPL_ANALYSER5_MON_VAL_HACTIVE_tim_hactive_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER5_MON_VAL_HACTIVE_tim_hactive_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_VAL_HACTIVE_tim_hactive(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_VAL_HACTIVE_tim_hactive_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_VAL_HACTIVE_tim_hactive_MASK)

/*! @name ANALYSER5_MON_VAL_HBACK - Detected timing parameter horizontal back porch. */
#define IRIS_MVPL_ANALYSER5_MON_VAL_HBACK_tim_hback_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER5_MON_VAL_HBACK_tim_hback_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_VAL_HBACK_tim_hback(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_VAL_HBACK_tim_hback_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_VAL_HBACK_tim_hback_MASK)

/*! @name ANALYSER5_TIM_VAL_HFRONT - Detected timing parameter horizontal front porch. */
#define IRIS_MVPL_ANALYSER5_TIM_VAL_HFRONT_tim_hfront_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER5_TIM_VAL_HFRONT_tim_hfront_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_TIM_VAL_HFRONT_tim_hfront(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_TIM_VAL_HFRONT_tim_hfront_SHIFT)) & IRIS_MVPL_ANALYSER5_TIM_VAL_HFRONT_tim_hfront_MASK)

/*! @name ANALYSER5_MON_VAL_VTOTAL - Detected timing parameter vertical total lines. */
#define IRIS_MVPL_ANALYSER5_MON_VAL_VTOTAL_tim_vtotal_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER5_MON_VAL_VTOTAL_tim_vtotal_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_VAL_VTOTAL_tim_vtotal(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_VAL_VTOTAL_tim_vtotal_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_VAL_VTOTAL_tim_vtotal_MASK)

/*! @name ANALYSER5_MON_VAL_VACTIVE - Detected timing parameter vertical active lines. */
#define IRIS_MVPL_ANALYSER5_MON_VAL_VACTIVE_tim_vactive_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER5_MON_VAL_VACTIVE_tim_vactive_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_VAL_VACTIVE_tim_vactive(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_VAL_VACTIVE_tim_vactive_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_VAL_VACTIVE_tim_vactive_MASK)

/*! @name ANALYSER5_MON_VAL_VBACK - Detected timing parameter vertical back porch. */
#define IRIS_MVPL_ANALYSER5_MON_VAL_VBACK_tim_vback_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER5_MON_VAL_VBACK_tim_vback_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_VAL_VBACK_tim_vback(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_VAL_VBACK_tim_vback_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_VAL_VBACK_tim_vback_MASK)

/*! @name ANALYSER5_MON_VAL_VFRONT - Detected timing parameter vertical front porch. */
#define IRIS_MVPL_ANALYSER5_MON_VAL_VFRONT_tim_vfront_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER5_MON_VAL_VFRONT_tim_vfront_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_VAL_VFRONT_tim_vfront(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_VAL_VFRONT_tim_vfront_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_VAL_VFRONT_tim_vfront_MASK)

/*! @name ANALYSER5_MON_VAL_TOTAL_CLK - Detected timing parameter total clocks. */
#define IRIS_MVPL_ANALYSER5_MON_VAL_TOTAL_CLK_tim_vtotal_clk_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_ANALYSER5_MON_VAL_TOTAL_CLK_tim_vtotal_clk_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_VAL_TOTAL_CLK_tim_vtotal_clk(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_VAL_TOTAL_CLK_tim_vtotal_clk_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_VAL_TOTAL_CLK_tim_vtotal_clk_MASK)

/*! @name ANALYSER5_MON_PIXEL_CTRL - Configure RGB pixel observation. */
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_mode_MASK (0x7U)
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_mode_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_mode_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_mode_MASK)
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_red_MASK (0xFF00U)
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_red_SHIFT (8U)
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_red(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_red_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_red_MASK)
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_green_MASK (0xFF0000U)
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_green_SHIFT (16U)
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_green(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_green_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_green_MASK)
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_blue_MASK (0xFF000000U)
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_blue_SHIFT (24U)
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_blue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_blue_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_PIXEL_CTRL_mon_pixel_blue_MASK)

/*! @name ANALYSER5_MON_PIXEL_STAT - Status RGB pixel observation. */
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_STAT_mon_pixel_error_cnt_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_STAT_mon_pixel_error_cnt_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_PIXEL_STAT_mon_pixel_error_cnt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_PIXEL_STAT_mon_pixel_error_cnt_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_PIXEL_STAT_mon_pixel_error_cnt_MASK)

/*! @name ANALYSER5_MON_WATCHDOG_TOUT - Configure sync-activity timeout (watchdog). */
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_TOUT_wdg_hsync_tout_MASK (0xFFFFU)
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_TOUT_wdg_hsync_tout_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_TOUT_wdg_hsync_tout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_WATCHDOG_TOUT_wdg_hsync_tout_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_WATCHDOG_TOUT_wdg_hsync_tout_MASK)
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_TOUT_wdg_vsync_tout_MASK (0xFFFF0000U)
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_TOUT_wdg_vsync_tout_SHIFT (16U)
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_TOUT_wdg_vsync_tout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_WATCHDOG_TOUT_wdg_vsync_tout_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_WATCHDOG_TOUT_wdg_vsync_tout_MASK)

/*! @name ANALYSER5_MON_WATCHDOG_STAT - Detected timing parameter total clocks. */
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_hsync_inactive_MASK (0x1U)
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_hsync_inactive_SHIFT (0U)
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_hsync_inactive(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_hsync_inactive_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_hsync_inactive_MASK)
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_vsync_inactive_MASK (0x2U)
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_vsync_inactive_SHIFT (1U)
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_vsync_inactive(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_vsync_inactive_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_vsync_inactive_MASK)
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_de_inactive_MASK (0x4U)
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_de_inactive_SHIFT (2U)
#define IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_de_inactive(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_de_inactive_SHIFT)) & IRIS_MVPL_ANALYSER5_MON_WATCHDOG_STAT_wdg_de_inactive_MASK)

/*! @name DPUXPC_CONTROL -  */
#define IRIS_MVPL_DPUXPC_CONTROL_Enable_MASK     (0x1U)
#define IRIS_MVPL_DPUXPC_CONTROL_Enable_SHIFT    (0U)
#define IRIS_MVPL_DPUXPC_CONTROL_Enable(x)       (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_CONTROL_Enable_SHIFT)) & IRIS_MVPL_DPUXPC_CONTROL_Enable_MASK)
#define IRIS_MVPL_DPUXPC_CONTROL_Mode_MASK       (0x6U)
#define IRIS_MVPL_DPUXPC_CONTROL_Mode_SHIFT      (1U)
#define IRIS_MVPL_DPUXPC_CONTROL_Mode(x)         (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_CONTROL_Mode_SHIFT)) & IRIS_MVPL_DPUXPC_CONTROL_Mode_MASK)
#define IRIS_MVPL_DPUXPC_CONTROL_IncrementMode_MASK (0x40000000U)
#define IRIS_MVPL_DPUXPC_CONTROL_IncrementMode_SHIFT (30U)
#define IRIS_MVPL_DPUXPC_CONTROL_IncrementMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_CONTROL_IncrementMode_SHIFT)) & IRIS_MVPL_DPUXPC_CONTROL_IncrementMode_MASK)
#define IRIS_MVPL_DPUXPC_CONTROL_OTCDisable_MASK (0x80000000U)
#define IRIS_MVPL_DPUXPC_CONTROL_OTCDisable_SHIFT (31U)
#define IRIS_MVPL_DPUXPC_CONTROL_OTCDisable(x)   (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_CONTROL_OTCDisable_SHIFT)) & IRIS_MVPL_DPUXPC_CONTROL_OTCDisable_MASK)

/*! @name DPUXPC_TIMER -  */
#define IRIS_MVPL_DPUXPC_TIMER_Load_MASK         (0xFFFFFFFU)
#define IRIS_MVPL_DPUXPC_TIMER_Load_SHIFT        (0U)
#define IRIS_MVPL_DPUXPC_TIMER_Load(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_TIMER_Load_SHIFT)) & IRIS_MVPL_DPUXPC_TIMER_Load_MASK)
#define IRIS_MVPL_DPUXPC_TIMER_Divider_MASK      (0xF0000000U)
#define IRIS_MVPL_DPUXPC_TIMER_Divider_SHIFT     (28U)
#define IRIS_MVPL_DPUXPC_TIMER_Divider(x)        (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_TIMER_Divider_SHIFT)) & IRIS_MVPL_DPUXPC_TIMER_Divider_MASK)

/*! @name DPUXPC_MEASUREMENTTIMECONTROL -  */
#define IRIS_MVPL_DPUXPC_MEASUREMENTTIMECONTROL_MTDivider_MASK (0xFFFFFU)
#define IRIS_MVPL_DPUXPC_MEASUREMENTTIMECONTROL_MTDivider_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MEASUREMENTTIMECONTROL_MTDivider(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MEASUREMENTTIMECONTROL_MTDivider_SHIFT)) & IRIS_MVPL_DPUXPC_MEASUREMENTTIMECONTROL_MTDivider_MASK)
#define IRIS_MVPL_DPUXPC_MEASUREMENTTIMECONTROL_MTEnable_MASK (0x80000000U)
#define IRIS_MVPL_DPUXPC_MEASUREMENTTIMECONTROL_MTEnable_SHIFT (31U)
#define IRIS_MVPL_DPUXPC_MEASUREMENTTIMECONTROL_MTEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MEASUREMENTTIMECONTROL_MTEnable_SHIFT)) & IRIS_MVPL_DPUXPC_MEASUREMENTTIMECONTROL_MTEnable_MASK)

/*! @name DPUXPC_SW_TAG -  */
#define IRIS_MVPL_DPUXPC_SW_TAG_Tag_MASK         (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_SW_TAG_Tag_SHIFT        (0U)
#define IRIS_MVPL_DPUXPC_SW_TAG_Tag(x)           (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_SW_TAG_Tag_SHIFT)) & IRIS_MVPL_DPUXPC_SW_TAG_Tag_MASK)

/*! @name DPUXPC_MEASUREMENTTIME -  */
#define IRIS_MVPL_DPUXPC_MEASUREMENTTIME_Time_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MEASUREMENTTIME_Time_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MEASUREMENTTIME_Time(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MEASUREMENTTIME_Time_SHIFT)) & IRIS_MVPL_DPUXPC_MEASUREMENTTIME_Time_MASK)

/*! @name DPUXPC_GLOBAL_COUNTER -  */
#define IRIS_MVPL_DPUXPC_GLOBAL_COUNTER_Global_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_GLOBAL_COUNTER_Global_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_GLOBAL_COUNTER_Global(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_GLOBAL_COUNTER_Global_SHIFT)) & IRIS_MVPL_DPUXPC_GLOBAL_COUNTER_Global_MASK)

/*! @name DPUXPC_MU00_SWITCH -  */
#define IRIS_MVPL_DPUXPC_MU00_SWITCH_MU00_Select_MASK (0x1FU)
#define IRIS_MVPL_DPUXPC_MU00_SWITCH_MU00_Select_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU00_SWITCH_MU00_Select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU00_SWITCH_MU00_Select_SHIFT)) & IRIS_MVPL_DPUXPC_MU00_SWITCH_MU00_Select_MASK)

/*! @name DPUXPC_MU00_DATA_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU00_DATA_COUNTER_MU00_Data_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU00_DATA_COUNTER_MU00_Data_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU00_DATA_COUNTER_MU00_Data(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU00_DATA_COUNTER_MU00_Data_SHIFT)) & IRIS_MVPL_DPUXPC_MU00_DATA_COUNTER_MU00_Data_MASK)

/*! @name DPUXPC_MU00_BUSY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU00_BUSY_COUNTER_MU00_Busy_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU00_BUSY_COUNTER_MU00_Busy_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU00_BUSY_COUNTER_MU00_Busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU00_BUSY_COUNTER_MU00_Busy_SHIFT)) & IRIS_MVPL_DPUXPC_MU00_BUSY_COUNTER_MU00_Busy_MASK)

/*! @name DPUXPC_MU00_TRANSFER_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU00_TRANSFER_COUNTER_MU00_Transfer_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU00_TRANSFER_COUNTER_MU00_Transfer_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU00_TRANSFER_COUNTER_MU00_Transfer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU00_TRANSFER_COUNTER_MU00_Transfer_SHIFT)) & IRIS_MVPL_DPUXPC_MU00_TRANSFER_COUNTER_MU00_Transfer_MASK)

/*! @name DPUXPC_MU00_ADDRBUSY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU00_ADDRBUSY_COUNTER_MU00_Addrbusy_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU00_ADDRBUSY_COUNTER_MU00_Addrbusy_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU00_ADDRBUSY_COUNTER_MU00_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU00_ADDRBUSY_COUNTER_MU00_Addrbusy_SHIFT)) & IRIS_MVPL_DPUXPC_MU00_ADDRBUSY_COUNTER_MU00_Addrbusy_MASK)

/*! @name DPUXPC_MU00_LATENCY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU00_LATENCY_COUNTER_MU00_Latency_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU00_LATENCY_COUNTER_MU00_Latency_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU00_LATENCY_COUNTER_MU00_Latency(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU00_LATENCY_COUNTER_MU00_Latency_SHIFT)) & IRIS_MVPL_DPUXPC_MU00_LATENCY_COUNTER_MU00_Latency_MASK)

/*! @name DPUXPC_MU01_SWITCH -  */
#define IRIS_MVPL_DPUXPC_MU01_SWITCH_MU01_Select_MASK (0x1FU)
#define IRIS_MVPL_DPUXPC_MU01_SWITCH_MU01_Select_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU01_SWITCH_MU01_Select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU01_SWITCH_MU01_Select_SHIFT)) & IRIS_MVPL_DPUXPC_MU01_SWITCH_MU01_Select_MASK)

/*! @name DPUXPC_MU01_DATA_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU01_DATA_COUNTER_MU01_Data_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU01_DATA_COUNTER_MU01_Data_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU01_DATA_COUNTER_MU01_Data(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU01_DATA_COUNTER_MU01_Data_SHIFT)) & IRIS_MVPL_DPUXPC_MU01_DATA_COUNTER_MU01_Data_MASK)

/*! @name DPUXPC_MU01_BUSY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU01_BUSY_COUNTER_MU01_Busy_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU01_BUSY_COUNTER_MU01_Busy_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU01_BUSY_COUNTER_MU01_Busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU01_BUSY_COUNTER_MU01_Busy_SHIFT)) & IRIS_MVPL_DPUXPC_MU01_BUSY_COUNTER_MU01_Busy_MASK)

/*! @name DPUXPC_MU01_TRANSFER_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU01_TRANSFER_COUNTER_MU01_Transfer_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU01_TRANSFER_COUNTER_MU01_Transfer_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU01_TRANSFER_COUNTER_MU01_Transfer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU01_TRANSFER_COUNTER_MU01_Transfer_SHIFT)) & IRIS_MVPL_DPUXPC_MU01_TRANSFER_COUNTER_MU01_Transfer_MASK)

/*! @name DPUXPC_MU01_ADDRBUSY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU01_ADDRBUSY_COUNTER_MU01_Addrbusy_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU01_ADDRBUSY_COUNTER_MU01_Addrbusy_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU01_ADDRBUSY_COUNTER_MU01_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU01_ADDRBUSY_COUNTER_MU01_Addrbusy_SHIFT)) & IRIS_MVPL_DPUXPC_MU01_ADDRBUSY_COUNTER_MU01_Addrbusy_MASK)

/*! @name DPUXPC_MU01_LATENCY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU01_LATENCY_COUNTER_MU01_Latency_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU01_LATENCY_COUNTER_MU01_Latency_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU01_LATENCY_COUNTER_MU01_Latency(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU01_LATENCY_COUNTER_MU01_Latency_SHIFT)) & IRIS_MVPL_DPUXPC_MU01_LATENCY_COUNTER_MU01_Latency_MASK)

/*! @name DPUXPC_MU02_SWITCH -  */
#define IRIS_MVPL_DPUXPC_MU02_SWITCH_MU02_Select_MASK (0x1FU)
#define IRIS_MVPL_DPUXPC_MU02_SWITCH_MU02_Select_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU02_SWITCH_MU02_Select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU02_SWITCH_MU02_Select_SHIFT)) & IRIS_MVPL_DPUXPC_MU02_SWITCH_MU02_Select_MASK)

/*! @name DPUXPC_MU02_DATA_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU02_DATA_COUNTER_MU02_Data_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU02_DATA_COUNTER_MU02_Data_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU02_DATA_COUNTER_MU02_Data(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU02_DATA_COUNTER_MU02_Data_SHIFT)) & IRIS_MVPL_DPUXPC_MU02_DATA_COUNTER_MU02_Data_MASK)

/*! @name DPUXPC_MU02_BUSY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU02_BUSY_COUNTER_MU02_Busy_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU02_BUSY_COUNTER_MU02_Busy_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU02_BUSY_COUNTER_MU02_Busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU02_BUSY_COUNTER_MU02_Busy_SHIFT)) & IRIS_MVPL_DPUXPC_MU02_BUSY_COUNTER_MU02_Busy_MASK)

/*! @name DPUXPC_MU02_TRANSFER_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU02_TRANSFER_COUNTER_MU02_Transfer_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU02_TRANSFER_COUNTER_MU02_Transfer_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU02_TRANSFER_COUNTER_MU02_Transfer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU02_TRANSFER_COUNTER_MU02_Transfer_SHIFT)) & IRIS_MVPL_DPUXPC_MU02_TRANSFER_COUNTER_MU02_Transfer_MASK)

/*! @name DPUXPC_MU02_ADDRBUSY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU02_ADDRBUSY_COUNTER_MU02_Addrbusy_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU02_ADDRBUSY_COUNTER_MU02_Addrbusy_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU02_ADDRBUSY_COUNTER_MU02_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU02_ADDRBUSY_COUNTER_MU02_Addrbusy_SHIFT)) & IRIS_MVPL_DPUXPC_MU02_ADDRBUSY_COUNTER_MU02_Addrbusy_MASK)

/*! @name DPUXPC_MU02_LATENCY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU02_LATENCY_COUNTER_MU02_Latency_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU02_LATENCY_COUNTER_MU02_Latency_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU02_LATENCY_COUNTER_MU02_Latency(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU02_LATENCY_COUNTER_MU02_Latency_SHIFT)) & IRIS_MVPL_DPUXPC_MU02_LATENCY_COUNTER_MU02_Latency_MASK)

/*! @name DPUXPC_MU03_SWITCH -  */
#define IRIS_MVPL_DPUXPC_MU03_SWITCH_MU03_Select_MASK (0x1FU)
#define IRIS_MVPL_DPUXPC_MU03_SWITCH_MU03_Select_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU03_SWITCH_MU03_Select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU03_SWITCH_MU03_Select_SHIFT)) & IRIS_MVPL_DPUXPC_MU03_SWITCH_MU03_Select_MASK)

/*! @name DPUXPC_MU03_DATA_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU03_DATA_COUNTER_MU03_Data_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU03_DATA_COUNTER_MU03_Data_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU03_DATA_COUNTER_MU03_Data(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU03_DATA_COUNTER_MU03_Data_SHIFT)) & IRIS_MVPL_DPUXPC_MU03_DATA_COUNTER_MU03_Data_MASK)

/*! @name DPUXPC_MU03_BUSY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU03_BUSY_COUNTER_MU03_Busy_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU03_BUSY_COUNTER_MU03_Busy_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU03_BUSY_COUNTER_MU03_Busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU03_BUSY_COUNTER_MU03_Busy_SHIFT)) & IRIS_MVPL_DPUXPC_MU03_BUSY_COUNTER_MU03_Busy_MASK)

/*! @name DPUXPC_MU03_TRANSFER_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU03_TRANSFER_COUNTER_MU03_Transfer_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU03_TRANSFER_COUNTER_MU03_Transfer_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU03_TRANSFER_COUNTER_MU03_Transfer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU03_TRANSFER_COUNTER_MU03_Transfer_SHIFT)) & IRIS_MVPL_DPUXPC_MU03_TRANSFER_COUNTER_MU03_Transfer_MASK)

/*! @name DPUXPC_MU03_ADDRBUSY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU03_ADDRBUSY_COUNTER_MU03_Addrbusy_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU03_ADDRBUSY_COUNTER_MU03_Addrbusy_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU03_ADDRBUSY_COUNTER_MU03_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU03_ADDRBUSY_COUNTER_MU03_Addrbusy_SHIFT)) & IRIS_MVPL_DPUXPC_MU03_ADDRBUSY_COUNTER_MU03_Addrbusy_MASK)

/*! @name DPUXPC_MU03_LATENCY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU03_LATENCY_COUNTER_MU03_Latency_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU03_LATENCY_COUNTER_MU03_Latency_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU03_LATENCY_COUNTER_MU03_Latency(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU03_LATENCY_COUNTER_MU03_Latency_SHIFT)) & IRIS_MVPL_DPUXPC_MU03_LATENCY_COUNTER_MU03_Latency_MASK)

/*! @name DPUXPC_MU04_SWITCH -  */
#define IRIS_MVPL_DPUXPC_MU04_SWITCH_MU04_Select_MASK (0x1FU)
#define IRIS_MVPL_DPUXPC_MU04_SWITCH_MU04_Select_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU04_SWITCH_MU04_Select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU04_SWITCH_MU04_Select_SHIFT)) & IRIS_MVPL_DPUXPC_MU04_SWITCH_MU04_Select_MASK)

/*! @name DPUXPC_MU04_DATA_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU04_DATA_COUNTER_MU04_Data_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU04_DATA_COUNTER_MU04_Data_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU04_DATA_COUNTER_MU04_Data(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU04_DATA_COUNTER_MU04_Data_SHIFT)) & IRIS_MVPL_DPUXPC_MU04_DATA_COUNTER_MU04_Data_MASK)

/*! @name DPUXPC_MU04_BUSY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU04_BUSY_COUNTER_MU04_Busy_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU04_BUSY_COUNTER_MU04_Busy_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU04_BUSY_COUNTER_MU04_Busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU04_BUSY_COUNTER_MU04_Busy_SHIFT)) & IRIS_MVPL_DPUXPC_MU04_BUSY_COUNTER_MU04_Busy_MASK)

/*! @name DPUXPC_MU04_TRANSFER_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU04_TRANSFER_COUNTER_MU04_Transfer_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU04_TRANSFER_COUNTER_MU04_Transfer_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU04_TRANSFER_COUNTER_MU04_Transfer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU04_TRANSFER_COUNTER_MU04_Transfer_SHIFT)) & IRIS_MVPL_DPUXPC_MU04_TRANSFER_COUNTER_MU04_Transfer_MASK)

/*! @name DPUXPC_MU04_ADDRBUSY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU04_ADDRBUSY_COUNTER_MU04_Addrbusy_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU04_ADDRBUSY_COUNTER_MU04_Addrbusy_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU04_ADDRBUSY_COUNTER_MU04_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU04_ADDRBUSY_COUNTER_MU04_Addrbusy_SHIFT)) & IRIS_MVPL_DPUXPC_MU04_ADDRBUSY_COUNTER_MU04_Addrbusy_MASK)

/*! @name DPUXPC_MU04_LATENCY_COUNTER -  */
#define IRIS_MVPL_DPUXPC_MU04_LATENCY_COUNTER_MU04_Latency_MASK (0xFFFFFFFFU)
#define IRIS_MVPL_DPUXPC_MU04_LATENCY_COUNTER_MU04_Latency_SHIFT (0U)
#define IRIS_MVPL_DPUXPC_MU04_LATENCY_COUNTER_MU04_Latency(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_DPUXPC_MU04_LATENCY_COUNTER_MU04_Latency_SHIFT)) & IRIS_MVPL_DPUXPC_MU04_LATENCY_COUNTER_MU04_Latency_MASK)


/*!
 * @}
 */ /* end of group IRIS_MVPL_Register_Masks */


/* IRIS_MVPL - Peripheral instance base addresses */
/** Peripheral DC_0__IRIS_MVPL base address */
#define DC_0__IRIS_MVPL_BASE                     (0x56180000u)
/** Peripheral DC_0__IRIS_MVPL base pointer */
#define DC_0__IRIS_MVPL                          ((IRIS_MVPL_Type *)DC_0__IRIS_MVPL_BASE)
/** Peripheral DC_1__IRIS_MVPL base address */
#define DC_1__IRIS_MVPL_BASE                     (0x57180000u)
/** Peripheral DC_1__IRIS_MVPL base pointer */
#define DC_1__IRIS_MVPL                          ((IRIS_MVPL_Type *)DC_1__IRIS_MVPL_BASE)
/** Array initializer of IRIS_MVPL peripheral base addresses */
#define IRIS_MVPL_BASE_ADDRS                     { DC_0__IRIS_MVPL_BASE, DC_1__IRIS_MVPL_BASE }
/** Array initializer of IRIS_MVPL peripheral base pointers */
#define IRIS_MVPL_BASE_PTRS                      { DC_0__IRIS_MVPL, DC_1__IRIS_MVPL }

/*!
 * @}
 */ /* end of group IRIS_MVPL_Peripheral_Access_Layer */
 
 
/* ----------------------------------------------------------------------------
   -- IRQSTEER Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IRQSTEER_Peripheral_Access_Layer IRQSTEER Peripheral Access Layer
 * @{
 */

/** IRQSTEER - Register Layout Typedef */
typedef struct {
  __IO uint32_t CHANnCTL;                          /**< Channel n Control Register, offset: 0x0 */
  __IO uint32_t CHn_MASK[16];                      /**< Channel n Interrupt Mask Register, offset: 0x4 */
  __IO uint32_t CHn_SET[16];                       /**< Channel n Interrupt Set Register, offset: 0x44 */
  __I  uint32_t CHn_STATUS[16];                    /**< Channel n Interrupt Status Register, offset: 0x84 */
  __IO uint32_t CHn_MINTDIS;                       /**< Channel n Master Interrupt Disable Register, offset: 0xC4 */
  __I  uint32_t CHn_MSTRSTAT;                      /**< Channel n Master Status Register, offset: 0xC8 */
} IRQSTEER_Type;

/* ----------------------------------------------------------------------------
   -- IRQSTEER Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IRQSTEER_Register_Masks IRQSTEER Register Masks
 * @{
 */

/*! @name CHANnCTL - Channel n Control Register */
#define IRQSTEER_CHANnCTL_CH0_MASK               (0x1U)
#define IRQSTEER_CHANnCTL_CH0_SHIFT              (0U)
#define IRQSTEER_CHANnCTL_CH0(x)                 (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH0_SHIFT)) & IRQSTEER_CHANnCTL_CH0_MASK)
#define IRQSTEER_CHANnCTL_CH1_MASK               (0x2U)
#define IRQSTEER_CHANnCTL_CH1_SHIFT              (1U)
#define IRQSTEER_CHANnCTL_CH1(x)                 (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH1_SHIFT)) & IRQSTEER_CHANnCTL_CH1_MASK)
#define IRQSTEER_CHANnCTL_CH2_MASK               (0x4U)
#define IRQSTEER_CHANnCTL_CH2_SHIFT              (2U)
#define IRQSTEER_CHANnCTL_CH2(x)                 (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH2_SHIFT)) & IRQSTEER_CHANnCTL_CH2_MASK)
#define IRQSTEER_CHANnCTL_CH3_MASK               (0x8U)
#define IRQSTEER_CHANnCTL_CH3_SHIFT              (3U)
#define IRQSTEER_CHANnCTL_CH3(x)                 (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH3_SHIFT)) & IRQSTEER_CHANnCTL_CH3_MASK)
#define IRQSTEER_CHANnCTL_CH4_MASK               (0x10U)
#define IRQSTEER_CHANnCTL_CH4_SHIFT              (4U)
#define IRQSTEER_CHANnCTL_CH4(x)                 (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHANnCTL_CH4_SHIFT)) & IRQSTEER_CHANnCTL_CH4_MASK)

/*! @name CHn_MASK - Channel n Interrupt Mask Register */
#define IRQSTEER_CHn_MASK_MASKFLD_MASK           (0xFFFFFFFFU)
#define IRQSTEER_CHn_MASK_MASKFLD_SHIFT          (0U)
#define IRQSTEER_CHn_MASK_MASKFLD(x)             (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MASK_MASKFLD_SHIFT)) & IRQSTEER_CHn_MASK_MASKFLD_MASK)

/*! @name CHn_SET - Channel n Interrupt Set Register */
#define IRQSTEER_CHn_SET_FORCEFLD_MASK           (0xFFFFFFFFU)
#define IRQSTEER_CHn_SET_FORCEFLD_SHIFT          (0U)
#define IRQSTEER_CHn_SET_FORCEFLD(x)             (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_SET_FORCEFLD_SHIFT)) & IRQSTEER_CHn_SET_FORCEFLD_MASK)

/*! @name CHn_STATUS - Channel n Interrupt Status Register */
#define IRQSTEER_CHn_STATUS_STATUS_MASK          (0xFFFFFFFFU)
#define IRQSTEER_CHn_STATUS_STATUS_SHIFT         (0U)
#define IRQSTEER_CHn_STATUS_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_STATUS_STATUS_SHIFT)) & IRQSTEER_CHn_STATUS_STATUS_MASK)

/*! @name CHn_MINTDIS - Channel n Master Interrupt Disable Register */
#define IRQSTEER_CHn_MINTDIS_DISABLE_MASK        (0xFFU)
#define IRQSTEER_CHn_MINTDIS_DISABLE_SHIFT       (0U)
#define IRQSTEER_CHn_MINTDIS_DISABLE(x)          (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MINTDIS_DISABLE_SHIFT)) & IRQSTEER_CHn_MINTDIS_DISABLE_MASK)

/*! @name CHn_MSTRSTAT - Channel n Master Status Register */
#define IRQSTEER_CHn_MSTRSTAT_STATUS_MASK        (0x1U)
#define IRQSTEER_CHn_MSTRSTAT_STATUS_SHIFT       (0U)
#define IRQSTEER_CHn_MSTRSTAT_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MSTRSTAT_STATUS_SHIFT)) & IRQSTEER_CHn_MSTRSTAT_STATUS_MASK)

/*!
 * @}
 */ /* end of group IRQSTEER_Register_Masks */

/* IRQSTEER - Peripheral instance base addresses */
/** Peripheral IRQSTEER base address */
#define IRQSTEER_BASE                              (0x51080000u)
/** Peripheral IRQSTEER base pointer */
#define IRQSTEER                                   ((IRQSTEER_Type *)IRQSTEER_BASE)
/** Array initializer of IRQSTEER peripheral base addresses */
#define IRQSTEER_BASE_ADDRS                        { IRQSTEER_BASE }
/** Array initializer of IRQSTEER peripheral base pointers */
#define IRQSTEER_BASE_PTRS                         { IRQSTEER }
/** Interrupt vectors for the INTMUX peripheral type */
#define IRQSTEER_IRQS                              { IRQSTEER_0_IRQn, IRQSTEER_1_IRQn, IRQSTEER_2_IRQn, IRQSTEER_3_IRQn, IRQSTEER_4_IRQn, IRQSTEER_5_IRQn, IRQSTEER_6_IRQn, IRQSTEER_7_IRQn }

/*!
 * @}
 */ /* end of group IRQSTEER_Peripheral_Access_Layer */

typedef enum DPU_IRQSTEER_IRQn
{
    /* DISPLAY_INT_OUT0 */
    CmdSeqError_DPU_IRQn = 0,
    SoftwareInt0_DPU_IRQn = 1,
    SoftwareInt1_DPU_IRQn = 2,
    SoftwareInt2_DPU_IRQn = 3,
    SoftwareInt3_DPU_IRQn = 4,

    /* DISPLAY_INT_OUT2 */
    ExtDst0ShadowLoad_DPU_IRQn = 128,
    ExtDst0FrameComplete_DPU_IRQn = 129,
    ExtDst0SeqComplete_DPU_IRQn = 130,
    ExtDst4ShadowLoad_DPU_IRQn = 131,
    ExtDst4FrameComplete_DPU_IRQn = 132,
    ExtDst4SeqComplete_DPU_IRQn = 133,
    Display0ShadowLoad_DPU_IRQn = 136,
    Display0FrameComplete_DPU_IRQn = 137,
    Display0SeqComplete_DPU_IRQn = 138,
    FrameGen0Int0_DPU_IRQn = 139,
    FrameGen0Int1_DPU_IRQn = 140,
    FrameGen0Int2_DPU_IRQn = 141,
    FrameGen0Int3_DPU_IRQn = 142,
    Sig0ShadowLoad_DPU_IRQn = 143,
    Sig0Valid_DPU_IRQn = 144,
    Sig0Error_DPU_IRQn = 145,
    FrameGen0PrimSyncOn_DPU_IRQn = 146,
    FrameGen0PrimSyncOff_DPU_IRQn = 147,
    FrameGen0SecSyncOn_DPU_IRQn = 148,
    FrameGen0SecSyncOff_DPU_IRQn = 149,

    /* DISPLAY_INT_OUT4 */
    ExtDst1ShadowLoad_DPU_IRQn = 256,
    ExtDst1FrameComplete_DPU_IRQn = 257,
    ExtDst1SeqComplete_DPU_IRQn = 258,
    ExtDst5ShadowLoad_DPU_IRQn = 259,
    ExtDst5FrameComplete_DPU_IRQn = 260,
    ExtDst5SeqComplete_DPU_IRQn = 261,
    Display1ShadowLoad_DPU_IRQn = 263,
    Display1FrameComplete_DPU_IRQn = 264,
    Display1SeqComplete_DPU_IRQn = 265,
    FrameGen1Int0_DPU_IRQn = 266,
    FrameGen1Int1_DPU_IRQn = 267,
    FrameGen1Int2_DPU_IRQn = 268,
    FrameGen1Int3_DPU_IRQn = 269,
    Sig1ShadowLoad_DPU_IRQn = 270,
    Sig1Valid_DPU_IRQn = 271,
    Sig1Error_DPU_IRQn = 272,
    FrameGen1PrimSyncOn_DPU_IRQn = 273,
    FrameGen1PrimSyncOff_DPU_IRQn = 274,
    FrameGen1SecSyncOn_DPU_IRQn = 275,
    FrameGen1SecSyncOff_DPU_IRQn = 276,

    /* DISPLAY_INT_OUT7 */
    Store9ShadowLoad_DPU_IRQn = 448,
    Store9FrameComplete_DPU_IRQn = 449,
    Store9SeqComplete_DPU_IRQn = 450,
} DPU_IRQSTEER_IRQn_Type;

#define DPU0_IRQSTEER_BASE                         (0x56000000u)
#define DPU0_IRQSTEER                              ((IRQSTEER_Type *)DPU0_IRQSTEER_BASE)
#define DPU1_IRQSTEER_BASE                         (0x57000000u)
#define DPU1_IRQSTEER                              ((IRQSTEER_Type *)DPU1_IRQSTEER_BASE)

/* ----------------------------------------------------------------------------
   -- ISI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ISI_Peripheral_Access_Layer ISI Peripheral Access Layer
 * @{
 */

/** ISI - Register Layout Typedef */
typedef struct {
  __IO uint32_t CHNL_CTRL;                         /**< Channel Control Register, offset: 0x0 */
  __IO uint32_t CHNL_IMG_CTRL;                     /**< Channel Image Control Register, offset: 0x4 */
  __IO uint32_t CHNL_OUT_BUF_CTRL;                 /**< Channel Output Buffer Control Register, offset: 0x8 */
  __IO uint32_t CHNL_IMG_CFG;                      /**< Channel Image Configuration, offset: 0xC */
  __IO uint32_t CHNL_IER;                          /**< Channel Interrupt Enable Register, offset: 0x10 */
  __IO uint32_t CHNL_STS;                          /**< Channel Status Register, offset: 0x14 */
  __IO uint32_t CHNL_SCALE_FACTOR;                 /**< Channel Scale Factor Register, offset: 0x18 */
  __IO uint32_t CHNL_SCALE_OFFSET;                 /**< Channel Scale Offset Register, offset: 0x1C */
  __IO uint32_t CHNL_CROP_ULC;                     /**< Channel Crop Upper Left Corner Coordinate Register, offset: 0x20 */
  __IO uint32_t CHNL_CROP_LRC;                     /**< Channel Crop Lower Right Corner Coordinate Register, offset: 0x24 */
  __IO uint32_t CHNL_CSC_COEFF0;                   /**< Channel Color Space Conversion Coefficient Register 0, offset: 0x28 */
  __IO uint32_t CHNL_CSC_COEFF1;                   /**< Channel Color Space Conversion Coefficient Register 1, offset: 0x2C */
  __IO uint32_t CHNL_CSC_COEFF2;                   /**< Channel Color Space Conversion Coefficient Register 2, offset: 0x30 */
  __IO uint32_t CHNL_CSC_COEFF3;                   /**< Channel Color Space Conversion Coefficient Register 3, offset: 0x34 */
  __IO uint32_t CHNL_CSC_COEFF4;                   /**< Channel Color Space Conversion Coefficient Register 4, offset: 0x38 */
  __IO uint32_t CHNL_CSC_COEFF5;                   /**< Channel Color Space Conversion Coefficient Register 5, offset: 0x3C */
  struct {                                         /* offset: 0x40, array step: 0xC */
    __IO uint32_t CHNL_ROI_ALPHA;                    /**< Channel Alpha Value Register for Region of Interest 0..Channel Alpha Value Register for Region of Interest 3, array offset: 0x40, array step: 0xC */
    __IO uint32_t CHNL_ROI_ULC;                      /**< Channel Upper Left Coordinate Register for Region of Interest 0..Channel Upper Left Coordinate Register for Region of Interest 3, array offset: 0x44, array step: 0xC */
    __IO uint32_t CHNL_ROI_LRC;                      /**< Channel Lower Right Coordinate Register for Region of Interest 0..Channel Lower Right Coordinate Register for Region of Interest 3, array offset: 0x48, array step: 0xC */
  } ROI[4];
  __IO uint32_t CHNL_OUT_BUF1_ADDR_Y;              /**< Channel RGB or Luma (Y) Output Buffer 1 Address, offset: 0x70 */
  __IO uint32_t CHNL_OUT_BUF1_ADDR_U;              /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address, offset: 0x74 */
  __IO uint32_t CHNL_OUT_BUF1_ADDR_V;              /**< Channel Chroma (V/Cr) Output Buffer 1 Address, offset: 0x78 */
  __IO uint32_t CHNL_OUT_BUF_PITCH;                /**< Channel Output Buffer Pitch, offset: 0x7C */
  __IO uint32_t CHNL_IN_BUF_ADDR;                  /**< Channel Input Buffer Address, offset: 0x80 */
  __IO uint32_t CHNL_IN_BUF_PITCH;                 /**< Channel Input Buffer Pitch, offset: 0x84 */
  __IO uint32_t CHNL_MEM_RD_CTRL;                  /**< Channel Memory Read Control, offset: 0x88 */
  __IO uint32_t CHNL_OUT_BUF2_ADDR_Y;              /**< Channel RGB or Luma (Y) Output Buffer 2 Address, offset: 0x8C */
  __IO uint32_t CHNL_OUT_BUF2_ADDR_U;              /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address, offset: 0x90 */
  __IO uint32_t CHNL_OUT_BUF2_ADDR_V;              /**< Channel Chroma (V/Cr) Output Buffer 2 Address, offset: 0x94 */
  __IO uint32_t CHNL_SCL_IMG_CFG;                  /**< Channel Scaled Image Configuration, offset: 0x98 */
} ISI_Type;

/* ----------------------------------------------------------------------------
   -- ISI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ISI_Register_Masks ISI Register Masks
 * @{
 */

/*! @name CHNL_CTRL - Channel Control Register */
/*! @{ */
#define ISI_CHNL_CTRL_SRC_MASK                   (0x7U)
#define ISI_CHNL_CTRL_SRC_SHIFT                  (0U)
/*! SRC - Input image source port selection
 *  0b000..Image will be sourced from input port 0 of the Pixel Link Crossbar
 *  0b001..Image will be sourced from input port 1 of the Pixel Link Crossbar
 *  0b010..Image will be sourced from input port 2 of the Pixel Link Crossbar
 *  0b011..Image will be sourced from input port 3 of the Pixel Link Crossbar
 *  0b100..Image will be sourced from input port 4 of the Pixel Link Crossbar
 *  0b101..Image will be sourced from input port 5 of the Pixel Link Crossbar (Input port 5 connected to AXI read)
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define ISI_CHNL_CTRL_SRC(x)                     (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_SHIFT)) & ISI_CHNL_CTRL_SRC_MASK)
#define ISI_CHNL_CTRL_SRC_TYPE_MASK              (0x10U)
#define ISI_CHNL_CTRL_SRC_TYPE_SHIFT             (4U)
/*! SRC_TYPE - Type of selected input image source
 *  0b0..Image input source is MIPI CSI, Display Controller or HDMI Rx
 *  0b1..Image input source is Memory
 */
#define ISI_CHNL_CTRL_SRC_TYPE(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_TYPE_SHIFT)) & ISI_CHNL_CTRL_SRC_TYPE_MASK)
#define ISI_CHNL_CTRL_MIPI_VC_ID_MASK            (0xC0U)
#define ISI_CHNL_CTRL_MIPI_VC_ID_SHIFT           (6U)
/*! MIPI_VC_ID - Virtual channel ID
 *  0b00..Virtual Channel 0 selected or no virtual channel used
 *  0b01..Virtual Channel 1 selected
 *  0b10..Virtual Channel 2 selected
 *  0b11..Virtual Channel 3 selected
 */
#define ISI_CHNL_CTRL_MIPI_VC_ID(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_MIPI_VC_ID_SHIFT)) & ISI_CHNL_CTRL_MIPI_VC_ID_MASK)
#define ISI_CHNL_CTRL_SEC_LB_SRC_MASK            (0x700U)
#define ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT           (8U)
#define ISI_CHNL_CTRL_SEC_LB_SRC(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT)) & ISI_CHNL_CTRL_SEC_LB_SRC_MASK)
#define ISI_CHNL_CTRL_BLANK_PXL_MASK             (0xFF0000U)
#define ISI_CHNL_CTRL_BLANK_PXL_SHIFT            (16U)
/*! BLANK_PXL - Blank pixel value
 *  0b11111111..Default value
 *  0b00000000..Black color
 */
#define ISI_CHNL_CTRL_BLANK_PXL(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_BLANK_PXL_SHIFT)) & ISI_CHNL_CTRL_BLANK_PXL_MASK)
#define ISI_CHNL_CTRL_SW_RST_MASK                (0x1000000U)
#define ISI_CHNL_CTRL_SW_RST_SHIFT               (24U)
/*! SW_RST - Software reset bit
 *  0b0..No Reset
 *  0b1..Channel pipeline is under software reset
 */
#define ISI_CHNL_CTRL_SW_RST(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SW_RST_SHIFT)) & ISI_CHNL_CTRL_SW_RST_MASK)
#define ISI_CHNL_CTRL_CHAIN_BUF_MASK             (0x6000000U)
#define ISI_CHNL_CTRL_CHAIN_BUF_SHIFT            (25U)
/*! CHAIN_BUF - Chain line buffer control
 *  0b00..No line buffers chained (supports 2048 or less horizontal resolution)
 *  0b01..2 line buffers chained (supports 4096 horizontal resolution). Line buffers of channels 'n' and 'n+1' are chained.
 *  0b10..4 line buffers chained (supports 8192 horizontal resolution). Line buffers of channels 'n', 'n+1', 'n+2' and 'n+3' are chained.
 *  0b11..Reserved for future use
 */
#define ISI_CHNL_CTRL_CHAIN_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHAIN_BUF_SHIFT)) & ISI_CHNL_CTRL_CHAIN_BUF_MASK)
#define ISI_CHNL_CTRL_CHNL_BYPASS_MASK           (0x20000000U)
#define ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT          (29U)
/*! CHNL_BYPASS - Channel bypass enable
 *  0b0..Channel is not bypassed
 *  0b1..Channel is bypassed
 */
#define ISI_CHNL_CTRL_CHNL_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT)) & ISI_CHNL_CTRL_CHNL_BYPASS_MASK)
#define ISI_CHNL_CTRL_CLK_EN_MASK                (0x40000000U)
#define ISI_CHNL_CTRL_CLK_EN_SHIFT               (30U)
/*! CLK_EN - Channel clock enable
 *  0b0..Channel processing clock is disabled
 *  0b1..Channel processing clock is enabled
 */
#define ISI_CHNL_CTRL_CLK_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CLK_EN_SHIFT)) & ISI_CHNL_CTRL_CLK_EN_MASK)
#define ISI_CHNL_CTRL_CHNL_EN_MASK               (0x80000000U)
#define ISI_CHNL_CTRL_CHNL_EN_SHIFT              (31U)
/*! CHNL_EN - Enable channel processing
 *  0b0..Processing channel is disabled
 *  0b1..Processing channel is enabled
 */
#define ISI_CHNL_CTRL_CHNL_EN(x)                 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_EN_SHIFT)) & ISI_CHNL_CTRL_CHNL_EN_MASK)
/*! @} */

/*! @name CHNL_IMG_CTRL - Channel Image Control Register */
/*! @{ */
#define ISI_CHNL_IMG_CTRL_CSC_BYP_MASK           (0x1U)
#define ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT          (0U)
/*! CSC_BYP - Color Space Conversion bypass control
 *  0b0..CSC is operational
 *  0b1..CSC is bypassed
 */
#define ISI_CHNL_IMG_CTRL_CSC_BYP(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_BYP_MASK)
#define ISI_CHNL_IMG_CTRL_CSC_MODE_MASK          (0x6U)
#define ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT         (1U)
/*! CSC_MODE - Color Space Conversion operating mode
 *  0b00..Convert from YUV to RGB
 *  0b01..Convert from YCbCr to RGB
 *  0b10..Convert from RGB to YUV
 *  0b11..Convert from RGB to YCbCr
 */
#define ISI_CHNL_IMG_CTRL_CSC_MODE(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_MODE_MASK)
#define ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK        (0x8U)
#define ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT       (3U)
/*! YCBCR_MODE - YCbCr Mode
 *  0b0..YCbCr mode is disabled
 *  0b1..YCbCr mode is enabled
 */
#define ISI_CHNL_IMG_CTRL_YCBCR_MODE(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK)
#define ISI_CHNL_IMG_CTRL_RSVD2_MASK             (0x10U)
#define ISI_CHNL_IMG_CTRL_RSVD2_SHIFT            (4U)
#define ISI_CHNL_IMG_CTRL_RSVD2(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_RSVD2_SHIFT)) & ISI_CHNL_IMG_CTRL_RSVD2_MASK)
#define ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK          (0x20U)
#define ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT         (5U)
/*! HFLIP_EN - Horizontal flip control
 *  0b0..Horizantal image flip disabled
 *  0b1..Horizontal image flip enabled
 */
#define ISI_CHNL_IMG_CTRL_HFLIP_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK)
#define ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK          (0x40U)
#define ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT         (6U)
/*! VFLIP_EN - Veritical flip control
 *  0b0..Vertical image flip disabled
 *  0b1..Vertical image flip enabled
 */
#define ISI_CHNL_IMG_CTRL_VFLIP_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK)
#define ISI_CHNL_IMG_CTRL_CROP_EN_MASK           (0x80U)
#define ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT          (7U)
/*! CROP_EN - Output image cropping enable
 *  0b0..Image cropping is disabled
 *  0b1..Image cropping is enabled
 */
#define ISI_CHNL_IMG_CTRL_CROP_EN(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_CROP_EN_MASK)
#define ISI_CHNL_IMG_CTRL_DEC_Y_MASK             (0x300U)
#define ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT            (8U)
/*! DEC_Y - Vertical pre-decimation control
 *  0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational.
 *  0b01..Decimate by 2
 *  0b10..Decimate by 4
 *  0b11..Decimate by 8
 */
#define ISI_CHNL_IMG_CTRL_DEC_Y(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_Y_MASK)
#define ISI_CHNL_IMG_CTRL_DEC_X_MASK             (0xC00U)
#define ISI_CHNL_IMG_CTRL_DEC_X_SHIFT            (10U)
/*! DEC_X - Horizontal pre-decimation control
 *  0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational.
 *  0b01..Decimate by 2
 *  0b10..Decimate by 4
 *  0b11..Decimate by 8
 */
#define ISI_CHNL_IMG_CTRL_DEC_X(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_X_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_X_MASK)
#define ISI_CHNL_IMG_CTRL_DEINT_MASK             (0x7000U)
#define ISI_CHNL_IMG_CTRL_DEINT_SHIFT            (12U)
/*! DEINT - De-interlace control
 *  0b000, 0b001..No de-interlacing done
 *  0b010..Weave de-interlacing (Odd, Even) method used
 *  0b011..Weave de-interlacing (Even, Odd) method used
 *  0b100..Blending or linear interpolation (Odd + Even) de-interlacing method used
 *  0b101..Blending or linear interpolation (Even + Odd) de-interlacing method used
 *  0b110, 0b111..Line doubling de-interlacing method used. Both Odd and Even fields are doubled.
 */
#define ISI_CHNL_IMG_CTRL_DEINT(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEINT_SHIFT)) & ISI_CHNL_IMG_CTRL_DEINT_MASK)
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK      (0x8000U)
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT     (15U)
/*! GBL_ALPHA_EN - Global alpha value insertion enable
 *  0b0..Global Alpha value insertion is disabled
 *  0b1..Global Alpha value insertion is enabled
 */
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK)
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK     (0xFF0000U)
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT    (16U)
/*! GBL_ALPHA_VAL - Global alpha value
 *  0b00000000-0b11111111..Alpha value to be inserted with all RGB pixels
 */
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK)
#define ISI_CHNL_IMG_CTRL_FORMAT_MASK            (0x3F000000U)
#define ISI_CHNL_IMG_CTRL_FORMAT_SHIFT           (24U)
/*! FORMAT - Output image format
 *  0b000000..RGBA8888 - RGB format with alpha in LSB; 8-bits per component. 'A' indicates alpha value.
 *  0b000001..ABGR8888 - BGR format with alpha in MSB; 8-bits per component. 'A' indicates alpha value.
 *  0b000010..ARGB8888 - RGB format with alpha in MSB; 8-bits per component. 'A' indicates alpha value.
 *  0b000011..RGBX888 - RGB format with 8-bits per color component (unpacked and MSB-alinged in 32-bit DWORD). 'X' indicates the waste bits.
 *  0b000100..XBGR888 - BGR format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD). 'X' indicates the waste bits.
 *  0b000101..XRGB888 - RGB format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD). 'X' indicates the waste bits.
 *  0b000110..RGB888P - RGB format with 8-bits per color component (packed into 24-bits). No waste bits.
 *  0b000111..BGR888P - BGR format with 8-bits per color component (packed into 24-bits). No waste bits.
 *  0b001000..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color component. 'A' indicates alpha value.
 *  0b001001..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color component. 'A' indicates alpha value.
 *  0b001010..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into 16-bits WORD). No waste bits.
 *  0b001011..RAW8 - 8-bit RAW data packed into 32-bit DWORD
 *  0b001100..RAW10 - 10-bit RAW data packed into 16-bit WORD with 6 LSBs waste bits
 *  0b001101..RAW10P - 10-bit RAW data packed into 32-bit DWORD
 *  0b001110..RAW12 - 12-bit RAW data packed into 16-bit DWORD with 4 LSBs waste bits
 *  0b001111..RAW16 - 16-bit RAW data packed into 32-bit DWORD
 *  0b010000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
 *  0b010001..YUV444_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
 *  0b010010..YUV444_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
 *  0b010011..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved unpacked bytes (8 MSBs waste bits in 32-bit DWORD)
 *  0b010100..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b010101..YUV444_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b010110..YUV444_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b010111..Reserved for future use
 *  0b011000..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b011001..YUV444_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b011010..YUV444_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b011011..Reserved for future use
 *  0b011100..YUV444_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b011101..YUV444_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b011110..YUV444_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b011111..Reserved for future use
 *  0b100000..YUV422_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
 *  0b100001..YUV422_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
 *  0b100010..YUV422_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
 *  0b100011..Reserved for future use
 *  0b100100..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b100101..YUV422_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b100110..YUV422_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b100111..Reserved for future use
 *  0b101000..YUV422_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b101001..YUV422_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b101010..YUV422_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b101011..Reserved for future use
 *  0b101100..YUV422_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b101101..YUV422_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b101110..YUV422_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b101111..Reserved for future use
 *  0b110000..Reserved for future use
 *  0b110001..YUV420_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
 *  0b110010..YUV420_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
 *  0b110011..Reserved for future use
 *  0b110100..Reserved for future use
 *  0b110101..YUV420_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b110110..YUV420_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b110111..Reserved for future use
 *  0b111000..Reserved for future use
 *  0b111001..YUV420_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b111010..YUV420_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
 *  0b111011..Reserved for future use
 *  0b111100..Reserved for future use
 *  0b111101..YUV420_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b111110..YUV420_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b111111..Reserved for future use
 */
#define ISI_CHNL_IMG_CTRL_FORMAT(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_FORMAT_SHIFT)) & ISI_CHNL_IMG_CTRL_FORMAT_MASK)
#define ISI_CHNL_IMG_CTRL_RSVD0_MASK             (0xC0000000U)
#define ISI_CHNL_IMG_CTRL_RSVD0_SHIFT            (30U)
#define ISI_CHNL_IMG_CTRL_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_RSVD0_SHIFT)) & ISI_CHNL_IMG_CTRL_RSVD0_MASK)
/*! @} */

/*! @name CHNL_OUT_BUF_CTRL - Channel Output Buffer Control Register */
/*! @{ */
#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_MASK (0x3U)
#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_SHIFT (0U)
/*! OFLW_PANIC_SET_THD_Y - Overflow panic set threshold value for Y/RGB output buffer
 *  0b00..No panic alert will be asserted
 *  0b01..Panic will assert when the buffers are 25% full (i.e. have 128 bytes)
 *  0b10..Panic will assert when the buffers are 50% full (i.e. have 256 bytes)
 *  0b11..Panic will assert when the buffers are 75% full (i.e. have 384 bytes)
 */
#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_MASK)
#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_MASK (0x18U)
#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_SHIFT (3U)
/*! OFLW_PANIC_SET_THD_U - Overflow panic set threshold value for U output buffer
 *  0b00..No panic alert will be asserted
 *  0b01..Panic will assert when the buffers are 25% full (i.e. have 128 bytes)
 *  0b10..Panic will assert when the buffers are 50% full (i.e. have 256 bytes)
 *  0b11..Panic will assert when the buffers are 75% full (i.e. have 384 bytes)
 */
#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_MASK)
#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_MASK (0xC0U)
#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_SHIFT (6U)
/*! OFLW_PANIC_SET_THD_V - Overflow panic set threshold value for V output buffer
 *  0b00..No panic alert will be asserted
 *  0b01..Panic will assert when the buffers are 25% full (i.e. have 128 bytes)
 *  0b10..Panic will assert when the buffers are 50% full (i.e. have 256 bytes)
 *  0b11..Panic will assert when the buffers are 75% full (i.e. have 384 bytes)
 */
#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_MASK)
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK (0x4000U)
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT (14U)
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK)
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK (0x8000U)
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT (15U)
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK)
/*! @} */

/*! @name CHNL_IMG_CFG - Channel Image Configuration */
/*! @{ */
#define ISI_CHNL_IMG_CFG_WIDTH_MASK              (0x1FFFU)
#define ISI_CHNL_IMG_CFG_WIDTH_SHIFT             (0U)
#define ISI_CHNL_IMG_CFG_WIDTH(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_IMG_CFG_WIDTH_MASK)
#define ISI_CHNL_IMG_CFG_RSVD0_MASK              (0xE000U)
#define ISI_CHNL_IMG_CFG_RSVD0_SHIFT             (13U)
#define ISI_CHNL_IMG_CFG_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_RSVD0_SHIFT)) & ISI_CHNL_IMG_CFG_RSVD0_MASK)
#define ISI_CHNL_IMG_CFG_HEIGHT_MASK             (0x1FFF0000U)
#define ISI_CHNL_IMG_CFG_HEIGHT_SHIFT            (16U)
#define ISI_CHNL_IMG_CFG_HEIGHT(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_IMG_CFG_HEIGHT_MASK)
#define ISI_CHNL_IMG_CFG_RSVD1_MASK              (0xE0000000U)
#define ISI_CHNL_IMG_CFG_RSVD1_SHIFT             (29U)
#define ISI_CHNL_IMG_CFG_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_RSVD1_SHIFT)) & ISI_CHNL_IMG_CFG_RSVD1_MASK)
/*! @} */

/*! @name CHNL_IER - Channel Interrupt Enable Register */
/*! @{ */
#define ISI_CHNL_IER_RSVD0_MASK                  (0x3FFFU)
#define ISI_CHNL_IER_RSVD0_SHIFT                 (0U)
#define ISI_CHNL_IER_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_RSVD0_SHIFT)) & ISI_CHNL_IER_RSVD0_MASK)
#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK      (0x4000U)
#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT     (14U)
/*! LATE_VSYNC_ERR_EN - VSYNC timing (Late) error interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK)
#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK     (0x8000U)
#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT    (15U)
/*! EARLY_VSYNC_ERR_EN - VSYNC timing (Early) error interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK)
#define ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK          (0x10000U)
#define ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT         (16U)
/*! OFLW_Y_BUF_EN - Y output buffer overflow interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_OFLW_Y_BUF_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK)
#define ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_MASK     (0x20000U)
#define ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_SHIFT    (17U)
/*! EXCS_OFLW_Y_BUF_EN - Y output buffer excess overflow interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_MASK)
#define ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_MASK    (0x40000U)
#define ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_SHIFT   (18U)
/*! OFLW_PANIC_Y_BUF_EN - Y output buffer potential overflow panic interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN(x)      (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_MASK)
#define ISI_CHNL_IER_OFLW_U_BUF_EN_MASK          (0x80000U)
#define ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT         (19U)
/*! OFLW_U_BUF_EN - U output buffer overflow interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_OFLW_U_BUF_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_U_BUF_EN_MASK)
#define ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_MASK     (0x100000U)
#define ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_SHIFT    (20U)
/*! EXCS_OFLW_U_BUF_EN - U output buffer excess overflow interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_MASK)
#define ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_MASK    (0x200000U)
#define ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_SHIFT   (21U)
/*! OFLW_PANIC_U_BUF_EN - U output buffer potential overflow panic interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN(x)      (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_MASK)
#define ISI_CHNL_IER_OFLW_V_BUF_EN_MASK          (0x400000U)
#define ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT         (22U)
/*! OFLW_V_BUF_EN - V output buffer overflow interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_OFLW_V_BUF_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_V_BUF_EN_MASK)
#define ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_MASK     (0x800000U)
#define ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_SHIFT    (23U)
/*! EXCS_OFLW_V_BUF_EN - V output buffer excess overflow interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_MASK)
#define ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_MASK    (0x1000000U)
#define ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_SHIFT   (24U)
/*! OFLW_PANIC_V_BUF_EN - V output buffer potential overflow panic interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN(x)      (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_MASK)
#define ISI_CHNL_IER_AXI_RD_ERR_EN_MASK          (0x2000000U)
#define ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT         (25U)
/*! AXI_RD_ERR_EN - AXI bus read error interrupt enable bit (Channel 0 only)
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_AXI_RD_ERR_EN(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT)) & ISI_CHNL_IER_AXI_RD_ERR_EN_MASK)
#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK        (0x4000000U)
#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT       (26U)
/*! AXI_WR_ERR_Y_EN - AXI bus read error interrupt enable bit for Y/RGB data buffer
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK)
#define ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK        (0x8000000U)
#define ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT       (27U)
/*! AXI_WR_ERR_U_EN - AXI bus read error interrupt enable bit for U data buffer
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_AXI_WR_ERR_U_EN(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK)
#define ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK        (0x10000000U)
#define ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT       (28U)
/*! AXI_WR_ERR_V_EN - AXI bus read error interrupt enable bit for V data buffer
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_AXI_WR_ERR_V_EN(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK)
#define ISI_CHNL_IER_FRM_RCVD_EN_MASK            (0x20000000U)
#define ISI_CHNL_IER_FRM_RCVD_EN_SHIFT           (29U)
/*! FRM_RCVD_EN - Frame received interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_FRM_RCVD_EN(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_FRM_RCVD_EN_SHIFT)) & ISI_CHNL_IER_FRM_RCVD_EN_MASK)
#define ISI_CHNL_IER_LINE_RCVD_EN_MASK           (0x40000000U)
#define ISI_CHNL_IER_LINE_RCVD_EN_SHIFT          (30U)
/*! LINE_RCVD_EN - Line received interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_LINE_RCVD_EN(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LINE_RCVD_EN_SHIFT)) & ISI_CHNL_IER_LINE_RCVD_EN_MASK)
#define ISI_CHNL_IER_MEM_RD_DONE_EN_MASK         (0x80000000U)
#define ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT        (31U)
/*! MEM_RD_DONE_EN - Memory read complete interrupt enable bit
 *  0b0..Interrupt is disabled
 *  0b1..Interrupt is enabled
 */
#define ISI_CHNL_IER_MEM_RD_DONE_EN(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT)) & ISI_CHNL_IER_MEM_RD_DONE_EN_MASK)
/*! @} */

/*! @name CHNL_STS - Channel Status Register */
/*! @{ */
#define ISI_CHNL_STS_OFLW_BYTES_MASK             (0xFFU)
#define ISI_CHNL_STS_OFLW_BYTES_SHIFT            (0U)
/*! OFLW_BYTES - Number of bytes lost during an overflow event
 *  0b00000000..No overflow
 *  0b00000001-0b11111111..Total bytes lost during an overflow event
 */
#define ISI_CHNL_STS_OFLW_BYTES(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_BYTES_SHIFT)) & ISI_CHNL_STS_OFLW_BYTES_MASK)
#define ISI_CHNL_STS_BUF1_ACTIVE_MASK            (0x100U)
#define ISI_CHNL_STS_BUF1_ACTIVE_SHIFT           (8U)
/*! BUF1_ACTIVE - Current frame being stored in Buffer 1 Address
 *  0b0..Buffer 1 Address inactive
 *  0b1..Buffer 1 Address in use
 */
#define ISI_CHNL_STS_BUF1_ACTIVE(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF1_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF1_ACTIVE_MASK)
#define ISI_CHNL_STS_BUF2_ACTIVE_MASK            (0x200U)
#define ISI_CHNL_STS_BUF2_ACTIVE_SHIFT           (9U)
/*! BUF2_ACTIVE - Current frame being stored in Buffer 2 Address
 *  0b0..Buffer 2 Address inactive
 *  0b1..Buffer 2 Address in use
 */
#define ISI_CHNL_STS_BUF2_ACTIVE(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF2_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF2_ACTIVE_MASK)
#define ISI_CHNL_STS_MEM_RD_OFLOW_MASK           (0x400U)
#define ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT          (10U)
/*! MEM_RD_OFLOW - Memory read FIFO overflow error status
 *  0b0..No overflow occurred during memory read
 *  0b1..FIFO overflow occurred during memory read
 */
#define ISI_CHNL_STS_MEM_RD_OFLOW(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT)) & ISI_CHNL_STS_MEM_RD_OFLOW_MASK)
#define ISI_CHNL_STS_RSVD1_MASK                  (0x3800U)
#define ISI_CHNL_STS_RSVD1_SHIFT                 (11U)
#define ISI_CHNL_STS_RSVD1(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_RSVD1_SHIFT)) & ISI_CHNL_STS_RSVD1_MASK)
#define ISI_CHNL_STS_LATE_VSYNC_ERR_MASK         (0x4000U)
#define ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT        (14U)
/*! LATE_VSYNC_ERR - VSYNC timing (Late) error interrupt flag
 *  0b0..No error
 *  0b1..VSYNC detected later than expected
 */
#define ISI_CHNL_STS_LATE_VSYNC_ERR(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_LATE_VSYNC_ERR_MASK)
#define ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK        (0x8000U)
#define ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT       (15U)
/*! EARLY_VSYNC_ERR - VSYNC timing (Early) error interrupt flag
 *  0b0..No error
 *  0b1..VSYNC detected earlier than expected
 */
#define ISI_CHNL_STS_EARLY_VSYNC_ERR(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK)
#define ISI_CHNL_STS_OFLW_Y_BUF_MASK             (0x10000U)
#define ISI_CHNL_STS_OFLW_Y_BUF_SHIFT            (16U)
/*! OFLW_Y_BUF - Overflow in Y/RGB output buffer interrupt flag
 *  0b0..No overflow
 *  0b1..Overflow has occured in the channel
 */
#define ISI_CHNL_STS_OFLW_Y_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_Y_BUF_MASK)
#define ISI_CHNL_STS_EXCS_OFLW_Y_BUF_MASK        (0x20000U)
#define ISI_CHNL_STS_EXCS_OFLW_Y_BUF_SHIFT       (17U)
/*! EXCS_OFLW_Y_BUF - Y/RGB output buffer excess overflow interrupt flag
 *  0b0..No overflow or overflow condition within recoverable limits
 *  0b1..Overflow confition beyond recoverable limits
 */
#define ISI_CHNL_STS_EXCS_OFLW_Y_BUF(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EXCS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_EXCS_OFLW_Y_BUF_MASK)
#define ISI_CHNL_STS_OFLW_PANIC_Y_BUF_MASK       (0x40000U)
#define ISI_CHNL_STS_OFLW_PANIC_Y_BUF_SHIFT      (18U)
/*! OFLW_PANIC_Y_BUF - Y/RGB output buffer potential overflow panic alert interrupt flag
 *  0b0..Buffer has not crossed the panic threshold limit
 *  0b1..Panic threshold limit crossed. Software must take action.
 */
#define ISI_CHNL_STS_OFLW_PANIC_Y_BUF(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_PANIC_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_PANIC_Y_BUF_MASK)
#define ISI_CHNL_STS_OFLW_U_BUF_MASK             (0x80000U)
#define ISI_CHNL_STS_OFLW_U_BUF_SHIFT            (19U)
/*! OFLW_U_BUF - Overflow in U output buffer interrupt flag
 *  0b0..No overflow
 *  0b1..Overflow has occured in the channel
 */
#define ISI_CHNL_STS_OFLW_U_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_U_BUF_MASK)
#define ISI_CHNL_STS_EXCS_OFLW_U_BUF_MASK        (0x100000U)
#define ISI_CHNL_STS_EXCS_OFLW_U_BUF_SHIFT       (20U)
/*! EXCS_OFLW_U_BUF - U output buffer excess overflow interrupt flag
 *  0b0..No overflow or overflow condition within recoverable limits
 *  0b1..Overflow confition beyond recoverable limits
 */
#define ISI_CHNL_STS_EXCS_OFLW_U_BUF(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EXCS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_EXCS_OFLW_U_BUF_MASK)
#define ISI_CHNL_STS_OFLW_PANIC_U_BUF_MASK       (0x200000U)
#define ISI_CHNL_STS_OFLW_PANIC_U_BUF_SHIFT      (21U)
/*! OFLW_PANIC_U_BUF - U output buffer potential overflow panic alert interrupt flag
 *  0b0..Buffer has not crossed the panic threshold limit
 *  0b1..Panic threshold limit crossed. Software must take action.
 */
#define ISI_CHNL_STS_OFLW_PANIC_U_BUF(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_PANIC_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_PANIC_U_BUF_MASK)
#define ISI_CHNL_STS_OFLW_V_BUF_MASK             (0x400000U)
#define ISI_CHNL_STS_OFLW_V_BUF_SHIFT            (22U)
/*! OFLW_V_BUF - Overflow in U output buffer interrupt flag
 *  0b0..No overflow
 *  0b1..Overflow has occured in the channel
 */
#define ISI_CHNL_STS_OFLW_V_BUF(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_V_BUF_MASK)
#define ISI_CHNL_STS_EXCS_OFLW_V_BUF_MASK        (0x800000U)
#define ISI_CHNL_STS_EXCS_OFLW_V_BUF_SHIFT       (23U)
/*! EXCS_OFLW_V_BUF - V output buffer excess overflow interrupt flag
 *  0b0..No overflow or overflow condition within recoverable limits
 *  0b1..Overflow confition beyond recoverable limits
 */
#define ISI_CHNL_STS_EXCS_OFLW_V_BUF(x)          (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EXCS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_EXCS_OFLW_V_BUF_MASK)
#define ISI_CHNL_STS_OFLW_PANIC_V_BUF_MASK       (0x1000000U)
#define ISI_CHNL_STS_OFLW_PANIC_V_BUF_SHIFT      (24U)
/*! OFLW_PANIC_V_BUF - V output buffer potential overflow panic alert interrupt flag
 *  0b0..Buffer has not crossed the panic threshold limit
 *  0b1..Panic threshold limit crossed. Software must take action.
 */
#define ISI_CHNL_STS_OFLW_PANIC_V_BUF(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_PANIC_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_PANIC_V_BUF_MASK)
#define ISI_CHNL_STS_AXI_RD_ERR_MASK             (0x2000000U)
#define ISI_CHNL_STS_AXI_RD_ERR_SHIFT            (25U)
/*! AXI_RD_ERR - AXI Bus read error interrupt flag (Channel 0 only)
 *  0b0..No error
 *  0b1..Error occured during read
 */
#define ISI_CHNL_STS_AXI_RD_ERR(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_RD_ERR_SHIFT)) & ISI_CHNL_STS_AXI_RD_ERR_MASK)
#define ISI_CHNL_STS_AXI_WR_ERR_Y_MASK           (0x4000000U)
#define ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT          (26U)
/*! AXI_WR_ERR_Y - AXI Bus write error interrupt flag for Y/RGB data buffer
 *  0b0..No error
 *  0b1..Error occured during write
 */
#define ISI_CHNL_STS_AXI_WR_ERR_Y(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_Y_MASK)
#define ISI_CHNL_STS_AXI_WR_ERR_U_MASK           (0x8000000U)
#define ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT          (27U)
/*! AXI_WR_ERR_U - AXI Bus write error interrupt flag for U data buffer
 *  0b0..No error
 *  0b1..Error occured during write
 */
#define ISI_CHNL_STS_AXI_WR_ERR_U(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_U_MASK)
#define ISI_CHNL_STS_AXI_WR_ERR_V_MASK           (0x10000000U)
#define ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT          (28U)
/*! AXI_WR_ERR_V - AXI Bus write error interrupt flag for V data buffer
 *  0b0..No error
 *  0b1..Error occured during write
 */
#define ISI_CHNL_STS_AXI_WR_ERR_V(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_V_MASK)
#define ISI_CHNL_STS_FRM_STRD_MASK               (0x20000000U)
#define ISI_CHNL_STS_FRM_STRD_SHIFT              (29U)
/*! FRM_STRD - Frame stored successfully interrupt flag
 *  0b0..No frame being received or in progress
 *  0b1..One full frame has been received and stored in memory
 */
#define ISI_CHNL_STS_FRM_STRD(x)                 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_FRM_STRD_SHIFT)) & ISI_CHNL_STS_FRM_STRD_MASK)
#define ISI_CHNL_STS_LINE_STRD_MASK              (0x40000000U)
#define ISI_CHNL_STS_LINE_STRD_SHIFT             (30U)
/*! LINE_STRD - Line received and stored interrupt flag
 *  0b0..No new line received
 *  0b1..New line received and stored into memory
 */
#define ISI_CHNL_STS_LINE_STRD(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LINE_STRD_SHIFT)) & ISI_CHNL_STS_LINE_STRD_MASK)
#define ISI_CHNL_STS_MEM_RD_DONE_MASK            (0x80000000U)
#define ISI_CHNL_STS_MEM_RD_DONE_SHIFT           (31U)
/*! MEM_RD_DONE - Memory read complete interrupt flag
 *  0b0..Image read from memory not complete or not started
 *  0b1..Image read from memory completed
 */
#define ISI_CHNL_STS_MEM_RD_DONE(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_DONE_SHIFT)) & ISI_CHNL_STS_MEM_RD_DONE_MASK)
/*! @} */

/*! @name CHNL_SCALE_FACTOR - Channel Scale Factor Register */
/*! @{ */
#define ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK       (0x3FFFU)
#define ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT      (0U)
#define ISI_CHNL_SCALE_FACTOR_X_SCALE(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK)
#define ISI_CHNL_SCALE_FACTOR_RSVD1_MASK         (0xC000U)
#define ISI_CHNL_SCALE_FACTOR_RSVD1_SHIFT        (14U)
#define ISI_CHNL_SCALE_FACTOR_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_RSVD1_SHIFT)) & ISI_CHNL_SCALE_FACTOR_RSVD1_MASK)
#define ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK       (0x3FFF0000U)
#define ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT      (16U)
#define ISI_CHNL_SCALE_FACTOR_Y_SCALE(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK)
#define ISI_CHNL_SCALE_FACTOR_RSVD0_MASK         (0xC0000000U)
#define ISI_CHNL_SCALE_FACTOR_RSVD0_SHIFT        (30U)
#define ISI_CHNL_SCALE_FACTOR_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_RSVD0_SHIFT)) & ISI_CHNL_SCALE_FACTOR_RSVD0_MASK)
/*! @} */

/*! @name CHNL_SCALE_OFFSET - Channel Scale Offset Register */
/*! @{ */
#define ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK      (0xFFFU)
#define ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT     (0U)
#define ISI_CHNL_SCALE_OFFSET_X_OFFSET(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK)
#define ISI_CHNL_SCALE_OFFSET_RSVD1_MASK         (0xF000U)
#define ISI_CHNL_SCALE_OFFSET_RSVD1_SHIFT        (12U)
#define ISI_CHNL_SCALE_OFFSET_RSVD1(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_RSVD1_SHIFT)) & ISI_CHNL_SCALE_OFFSET_RSVD1_MASK)
#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK      (0xFFF0000U)
#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT     (16U)
#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET(x)        (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK)
#define ISI_CHNL_SCALE_OFFSET_RSVD0_MASK         (0xF0000000U)
#define ISI_CHNL_SCALE_OFFSET_RSVD0_SHIFT        (28U)
#define ISI_CHNL_SCALE_OFFSET_RSVD0(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_RSVD0_SHIFT)) & ISI_CHNL_SCALE_OFFSET_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CROP_ULC - Channel Crop Upper Left Corner Coordinate Register */
/*! @{ */
#define ISI_CHNL_CROP_ULC_Y_MASK                 (0xFFFU)
#define ISI_CHNL_CROP_ULC_Y_SHIFT                (0U)
#define ISI_CHNL_CROP_ULC_Y(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_Y_SHIFT)) & ISI_CHNL_CROP_ULC_Y_MASK)
#define ISI_CHNL_CROP_ULC_RSVD1_MASK             (0xF000U)
#define ISI_CHNL_CROP_ULC_RSVD1_SHIFT            (12U)
#define ISI_CHNL_CROP_ULC_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_RSVD1_SHIFT)) & ISI_CHNL_CROP_ULC_RSVD1_MASK)
#define ISI_CHNL_CROP_ULC_X_MASK                 (0xFFF0000U)
#define ISI_CHNL_CROP_ULC_X_SHIFT                (16U)
#define ISI_CHNL_CROP_ULC_X(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_X_SHIFT)) & ISI_CHNL_CROP_ULC_X_MASK)
#define ISI_CHNL_CROP_ULC_RSVD0_MASK             (0xF0000000U)
#define ISI_CHNL_CROP_ULC_RSVD0_SHIFT            (28U)
#define ISI_CHNL_CROP_ULC_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_RSVD0_SHIFT)) & ISI_CHNL_CROP_ULC_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CROP_LRC - Channel Crop Lower Right Corner Coordinate Register */
/*! @{ */
#define ISI_CHNL_CROP_LRC_Y_MASK                 (0xFFFU)
#define ISI_CHNL_CROP_LRC_Y_SHIFT                (0U)
#define ISI_CHNL_CROP_LRC_Y(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_Y_SHIFT)) & ISI_CHNL_CROP_LRC_Y_MASK)
#define ISI_CHNL_CROP_LRC_RSVD1_MASK             (0xF000U)
#define ISI_CHNL_CROP_LRC_RSVD1_SHIFT            (12U)
#define ISI_CHNL_CROP_LRC_RSVD1(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_RSVD1_SHIFT)) & ISI_CHNL_CROP_LRC_RSVD1_MASK)
#define ISI_CHNL_CROP_LRC_X_MASK                 (0xFFF0000U)
#define ISI_CHNL_CROP_LRC_X_SHIFT                (16U)
#define ISI_CHNL_CROP_LRC_X(x)                   (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_X_SHIFT)) & ISI_CHNL_CROP_LRC_X_MASK)
#define ISI_CHNL_CROP_LRC_RSVD0_MASK             (0xF0000000U)
#define ISI_CHNL_CROP_LRC_RSVD0_SHIFT            (28U)
#define ISI_CHNL_CROP_LRC_RSVD0(x)               (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_RSVD0_SHIFT)) & ISI_CHNL_CROP_LRC_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CSC_COEFF0 - Channel Color Space Conversion Coefficient Register 0 */
/*! @{ */
#define ISI_CHNL_CSC_COEFF0_A1_MASK              (0x7FFU)
#define ISI_CHNL_CSC_COEFF0_A1_SHIFT             (0U)
#define ISI_CHNL_CSC_COEFF0_A1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A1_SHIFT)) & ISI_CHNL_CSC_COEFF0_A1_MASK)
#define ISI_CHNL_CSC_COEFF0_RSVD1_MASK           (0xF800U)
#define ISI_CHNL_CSC_COEFF0_RSVD1_SHIFT          (11U)
#define ISI_CHNL_CSC_COEFF0_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF0_RSVD1_MASK)
#define ISI_CHNL_CSC_COEFF0_A2_MASK              (0x7FF0000U)
#define ISI_CHNL_CSC_COEFF0_A2_SHIFT             (16U)
#define ISI_CHNL_CSC_COEFF0_A2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A2_SHIFT)) & ISI_CHNL_CSC_COEFF0_A2_MASK)
#define ISI_CHNL_CSC_COEFF0_RSVD0_MASK           (0xF8000000U)
#define ISI_CHNL_CSC_COEFF0_RSVD0_SHIFT          (27U)
#define ISI_CHNL_CSC_COEFF0_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF0_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CSC_COEFF1 - Channel Color Space Conversion Coefficient Register 1 */
/*! @{ */
#define ISI_CHNL_CSC_COEFF1_A3_MASK              (0x7FFU)
#define ISI_CHNL_CSC_COEFF1_A3_SHIFT             (0U)
#define ISI_CHNL_CSC_COEFF1_A3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_A3_SHIFT)) & ISI_CHNL_CSC_COEFF1_A3_MASK)
#define ISI_CHNL_CSC_COEFF1_RSVD1_MASK           (0xF800U)
#define ISI_CHNL_CSC_COEFF1_RSVD1_SHIFT          (11U)
#define ISI_CHNL_CSC_COEFF1_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF1_RSVD1_MASK)
#define ISI_CHNL_CSC_COEFF1_B1_MASK              (0x7FF0000U)
#define ISI_CHNL_CSC_COEFF1_B1_SHIFT             (16U)
#define ISI_CHNL_CSC_COEFF1_B1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_B1_SHIFT)) & ISI_CHNL_CSC_COEFF1_B1_MASK)
#define ISI_CHNL_CSC_COEFF1_RSVD0_MASK           (0xF8000000U)
#define ISI_CHNL_CSC_COEFF1_RSVD0_SHIFT          (27U)
#define ISI_CHNL_CSC_COEFF1_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF1_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CSC_COEFF2 - Channel Color Space Conversion Coefficient Register 2 */
/*! @{ */
#define ISI_CHNL_CSC_COEFF2_B2_MASK              (0x7FFU)
#define ISI_CHNL_CSC_COEFF2_B2_SHIFT             (0U)
#define ISI_CHNL_CSC_COEFF2_B2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B2_SHIFT)) & ISI_CHNL_CSC_COEFF2_B2_MASK)
#define ISI_CHNL_CSC_COEFF2_RSVD1_MASK           (0xF800U)
#define ISI_CHNL_CSC_COEFF2_RSVD1_SHIFT          (11U)
#define ISI_CHNL_CSC_COEFF2_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF2_RSVD1_MASK)
#define ISI_CHNL_CSC_COEFF2_B3_MASK              (0x7FF0000U)
#define ISI_CHNL_CSC_COEFF2_B3_SHIFT             (16U)
#define ISI_CHNL_CSC_COEFF2_B3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B3_SHIFT)) & ISI_CHNL_CSC_COEFF2_B3_MASK)
#define ISI_CHNL_CSC_COEFF2_RSVD0_MASK           (0xF8000000U)
#define ISI_CHNL_CSC_COEFF2_RSVD0_SHIFT          (27U)
#define ISI_CHNL_CSC_COEFF2_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF2_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CSC_COEFF3 - Channel Color Space Conversion Coefficient Register 3 */
/*! @{ */
#define ISI_CHNL_CSC_COEFF3_C1_MASK              (0x7FFU)
#define ISI_CHNL_CSC_COEFF3_C1_SHIFT             (0U)
#define ISI_CHNL_CSC_COEFF3_C1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C1_SHIFT)) & ISI_CHNL_CSC_COEFF3_C1_MASK)
#define ISI_CHNL_CSC_COEFF3_RSVD1_MASK           (0xF800U)
#define ISI_CHNL_CSC_COEFF3_RSVD1_SHIFT          (11U)
#define ISI_CHNL_CSC_COEFF3_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF3_RSVD1_MASK)
#define ISI_CHNL_CSC_COEFF3_C2_MASK              (0x7FF0000U)
#define ISI_CHNL_CSC_COEFF3_C2_SHIFT             (16U)
#define ISI_CHNL_CSC_COEFF3_C2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C2_SHIFT)) & ISI_CHNL_CSC_COEFF3_C2_MASK)
#define ISI_CHNL_CSC_COEFF3_RSVD0_MASK           (0xF8000000U)
#define ISI_CHNL_CSC_COEFF3_RSVD0_SHIFT          (27U)
#define ISI_CHNL_CSC_COEFF3_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF3_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CSC_COEFF4 - Channel Color Space Conversion Coefficient Register 4 */
/*! @{ */
#define ISI_CHNL_CSC_COEFF4_C3_MASK              (0x7FFU)
#define ISI_CHNL_CSC_COEFF4_C3_SHIFT             (0U)
#define ISI_CHNL_CSC_COEFF4_C3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_C3_SHIFT)) & ISI_CHNL_CSC_COEFF4_C3_MASK)
#define ISI_CHNL_CSC_COEFF4_RSVD1_MASK           (0xF800U)
#define ISI_CHNL_CSC_COEFF4_RSVD1_SHIFT          (11U)
#define ISI_CHNL_CSC_COEFF4_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF4_RSVD1_MASK)
#define ISI_CHNL_CSC_COEFF4_D1_MASK              (0x1FF0000U)
#define ISI_CHNL_CSC_COEFF4_D1_SHIFT             (16U)
#define ISI_CHNL_CSC_COEFF4_D1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_D1_SHIFT)) & ISI_CHNL_CSC_COEFF4_D1_MASK)
#define ISI_CHNL_CSC_COEFF4_RSVD0_MASK           (0xFE000000U)
#define ISI_CHNL_CSC_COEFF4_RSVD0_SHIFT          (25U)
#define ISI_CHNL_CSC_COEFF4_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF4_RSVD0_MASK)
/*! @} */

/*! @name CHNL_CSC_COEFF5 - Channel Color Space Conversion Coefficient Register 5 */
/*! @{ */
#define ISI_CHNL_CSC_COEFF5_D2_MASK              (0x1FFU)
#define ISI_CHNL_CSC_COEFF5_D2_SHIFT             (0U)
#define ISI_CHNL_CSC_COEFF5_D2(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D2_SHIFT)) & ISI_CHNL_CSC_COEFF5_D2_MASK)
#define ISI_CHNL_CSC_COEFF5_RSVD1_MASK           (0xFE00U)
#define ISI_CHNL_CSC_COEFF5_RSVD1_SHIFT          (9U)
#define ISI_CHNL_CSC_COEFF5_RSVD1(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF5_RSVD1_MASK)
#define ISI_CHNL_CSC_COEFF5_D3_MASK              (0x1FF0000U)
#define ISI_CHNL_CSC_COEFF5_D3_SHIFT             (16U)
#define ISI_CHNL_CSC_COEFF5_D3(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D3_SHIFT)) & ISI_CHNL_CSC_COEFF5_D3_MASK)
#define ISI_CHNL_CSC_COEFF5_RSVD0_MASK           (0xFE000000U)
#define ISI_CHNL_CSC_COEFF5_RSVD0_SHIFT          (25U)
#define ISI_CHNL_CSC_COEFF5_RSVD0(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF5_RSVD0_MASK)
/*! @} */

/*! @name CHNL_ROI_ALPHA - Channel Alpha Value Register for Region of Interest 0..Channel Alpha Value Register for Region of Interest 3 */
/*! @{ */
#define ISI_CHNL_ROI_ALPHA_RSVD1_MASK            (0xFFFFU)
#define ISI_CHNL_ROI_ALPHA_RSVD1_SHIFT           (0U)
#define ISI_CHNL_ROI_ALPHA_RSVD1(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_ALPHA_RSVD1_MASK)
#define ISI_CHNL_ROI_ALPHA_ALPHA_EN_MASK         (0x10000U)
#define ISI_CHNL_ROI_ALPHA_ALPHA_EN_SHIFT        (16U)
/*! ALPHA_EN - Alpha value insertion enable
 *  0b0..Alpha value insertion is disabled
 *  0b1..Alpha value insertion is enabled
 */
#define ISI_CHNL_ROI_ALPHA_ALPHA_EN(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_ALPHA_ALPHA_EN_MASK)
#define ISI_CHNL_ROI_ALPHA_RSVD0_MASK            (0xFE0000U)
#define ISI_CHNL_ROI_ALPHA_RSVD0_SHIFT           (17U)
#define ISI_CHNL_ROI_ALPHA_RSVD0(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_ALPHA_RSVD0_MASK)
#define ISI_CHNL_ROI_ALPHA_ALPHA_MASK            (0xFF000000U)
#define ISI_CHNL_ROI_ALPHA_ALPHA_SHIFT           (24U)
#define ISI_CHNL_ROI_ALPHA_ALPHA(x)              (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_ALPHA_ALPHA_MASK)
/*! @} */

/* The count of ISI_CHNL_ROI_ALPHA */
#define ISI_CHNL_ROI_ALPHA_COUNT                 (4U)

/*! @name CHNL_ROI_ULC - Channel Upper Left Coordinate Register for Region of Interest 0..Channel Upper Left Coordinate Register for Region of Interest 3 */
/*! @{ */
#define ISI_CHNL_ROI_ULC_Y_MASK                  (0xFFFU)
#define ISI_CHNL_ROI_ULC_Y_SHIFT                 (0U)
#define ISI_CHNL_ROI_ULC_Y(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_Y_SHIFT)) & ISI_CHNL_ROI_ULC_Y_MASK)
#define ISI_CHNL_ROI_ULC_RSVD1_MASK              (0xF000U)
#define ISI_CHNL_ROI_ULC_RSVD1_SHIFT             (12U)
#define ISI_CHNL_ROI_ULC_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_ULC_RSVD1_MASK)
#define ISI_CHNL_ROI_ULC_X_MASK                  (0xFFF0000U)
#define ISI_CHNL_ROI_ULC_X_SHIFT                 (16U)
#define ISI_CHNL_ROI_ULC_X(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_X_SHIFT)) & ISI_CHNL_ROI_ULC_X_MASK)
#define ISI_CHNL_ROI_ULC_RSVD0_MASK              (0xF0000000U)
#define ISI_CHNL_ROI_ULC_RSVD0_SHIFT             (28U)
#define ISI_CHNL_ROI_ULC_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_ULC_RSVD0_MASK)
/*! @} */

/* The count of ISI_CHNL_ROI_ULC */
#define ISI_CHNL_ROI_ULC_COUNT                   (4U)

/*! @name CHNL_ROI_LRC - Channel Lower Right Coordinate Register for Region of Interest 0..Channel Lower Right Coordinate Register for Region of Interest 3 */
/*! @{ */
#define ISI_CHNL_ROI_LRC_Y_MASK                  (0xFFFU)
#define ISI_CHNL_ROI_LRC_Y_SHIFT                 (0U)
#define ISI_CHNL_ROI_LRC_Y(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_Y_SHIFT)) & ISI_CHNL_ROI_LRC_Y_MASK)
#define ISI_CHNL_ROI_LRC_RSVD1_MASK              (0xF000U)
#define ISI_CHNL_ROI_LRC_RSVD1_SHIFT             (12U)
#define ISI_CHNL_ROI_LRC_RSVD1(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_LRC_RSVD1_MASK)
#define ISI_CHNL_ROI_LRC_X_MASK                  (0xFFF0000U)
#define ISI_CHNL_ROI_LRC_X_SHIFT                 (16U)
#define ISI_CHNL_ROI_LRC_X(x)                    (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_X_SHIFT)) & ISI_CHNL_ROI_LRC_X_MASK)
#define ISI_CHNL_ROI_LRC_RSVD0_MASK              (0xF0000000U)
#define ISI_CHNL_ROI_LRC_RSVD0_SHIFT             (28U)
#define ISI_CHNL_ROI_LRC_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_LRC_RSVD0_MASK)
/*! @} */

/* The count of ISI_CHNL_ROI_LRC */
#define ISI_CHNL_ROI_LRC_COUNT                   (4U)

/*! @name CHNL_OUT_BUF1_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 1 Address */
/*! @{ */
#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK       (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT      (0U)
#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK)
/*! @} */

/*! @name CHNL_OUT_BUF1_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */
/*! @{ */
#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK       (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT      (0U)
#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK)
/*! @} */

/*! @name CHNL_OUT_BUF1_ADDR_V - Channel Chroma (V/Cr) Output Buffer 1 Address */
/*! @{ */
#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK       (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT      (0U)
#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK)
/*! @} */

/*! @name CHNL_OUT_BUF_PITCH - Channel Output Buffer Pitch */
/*! @{ */
#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK   (0xFFFFU)
#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT  (0U)
#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH(x)     (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK)
/*! @} */

/*! @name CHNL_IN_BUF_ADDR - Channel Input Buffer Address */
/*! @{ */
#define ISI_CHNL_IN_BUF_ADDR_ADDR_MASK           (0xFFFFFFFFU)
#define ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT          (0U)
#define ISI_CHNL_IN_BUF_ADDR_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT)) & ISI_CHNL_IN_BUF_ADDR_ADDR_MASK)
/*! @} */

/*! @name CHNL_IN_BUF_PITCH - Channel Input Buffer Pitch */
/*! @{ */
#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK    (0xFFFFU)
#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT   (0U)
#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH(x)      (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK)
#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK     (0xFFFF0000U)
#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT    (16U)
#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH(x)       (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK)
/*! @} */

/*! @name CHNL_MEM_RD_CTRL - Channel Memory Read Control */
/*! @{ */
#define ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK       (0x1U)
#define ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT      (0U)
/*! READ_MEM - Initiate read from memory
 *  0b0..No reads from memory done
 *  0b1..Reads from memory initiated
 */
#define ISI_CHNL_MEM_RD_CTRL_READ_MEM(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK)
#define ISI_CHNL_MEM_RD_CTRL_RSVD0_MASK          (0xFFFFFFEU)
#define ISI_CHNL_MEM_RD_CTRL_RSVD0_SHIFT         (1U)
#define ISI_CHNL_MEM_RD_CTRL_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_RSVD0_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_RSVD0_MASK)
#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK       (0xF0000000U)
#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT      (28U)
/*! IMG_TYPE - Input image format
 *  0b0000..BGR8P - BGR format with 8-bits per color component (packed into 32-bit DWORD)
 *  0b0001..RGB8P - RGB format with 8-bits per color component (packed into 32-bit DWORD)
 *  0b0010..XRGB8 - RGB format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD)
 *  0b0011..RGBX8 - RGB format with 8-bits per color component (unpacked and MSBalinged in 32-bit DWORD)
 *  0b0100..XBGR8 - BGR format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD)
 *  0b0101..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into 32-bit DWORD)
 *  0b0110..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color component
 *  0b0111..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color component
 *  0b1000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
 *  0b1001..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b1010..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit WORD)
 *  0b1011..YUV444_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
 *  0b1100..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved unpacked bytes (8 MSBs waste bits in 32-bit DWORD)
 *  0b1101..YUV422_1P8P with 8-bits per color component; 1-plane YUV interleaved packed bytes
 *  0b1110..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
 *  0b1111..YUV422_1P12 with 12-bits per color component; 1-plane, YUV interleaved packed bytes (4 MSBs waste bits in 16-bit WORD)
 */
#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK)
/*! @} */

/*! @name CHNL_OUT_BUF2_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 2 Address */
/*! @{ */
#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK       (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT      (0U)
#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK)
/*! @} */

/*! @name CHNL_OUT_BUF2_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */
/*! @{ */
#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK       (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT      (0U)
#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK)
/*! @} */

/*! @name CHNL_OUT_BUF2_ADDR_V - Channel Chroma (V/Cr) Output Buffer 2 Address */
/*! @{ */
#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK       (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT      (0U)
#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK)
/*! @} */

/*! @name CHNL_SCL_IMG_CFG - Channel Scaled Image Configuration */
/*! @{ */
#define ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK          (0x1FFFU)
#define ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT         (0U)
#define ISI_CHNL_SCL_IMG_CFG_WIDTH(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK)
#define ISI_CHNL_SCL_IMG_CFG_RSVD0_MASK          (0xE000U)
#define ISI_CHNL_SCL_IMG_CFG_RSVD0_SHIFT         (13U)
#define ISI_CHNL_SCL_IMG_CFG_RSVD0(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_RSVD0_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_RSVD0_MASK)
#define ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK         (0x1FFF0000U)
#define ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT        (16U)
#define ISI_CHNL_SCL_IMG_CFG_HEIGHT(x)           (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK)
#define ISI_CHNL_SCL_IMG_CFG_RSVD1_MASK          (0xE0000000U)
#define ISI_CHNL_SCL_IMG_CFG_RSVD1_SHIFT         (29U)
#define ISI_CHNL_SCL_IMG_CFG_RSVD1(x)            (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_RSVD1_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_RSVD1_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ISI_Register_Masks */


/* ISI - Peripheral instance base addresses */
/** Peripheral IMAGING__ISI0 base address */
#define IMAGING__ISI0_BASE                       (0x58100000u)
/** Peripheral IMAGING__ISI0 base pointer */
#define IMAGING__ISI0                            ((ISI_Type *)IMAGING__ISI0_BASE)
/** Peripheral IMAGING__ISI1 base address */
#define IMAGING__ISI1_BASE                       (0x58110000u)
/** Peripheral IMAGING__ISI1 base pointer */
#define IMAGING__ISI1                            ((ISI_Type *)IMAGING__ISI1_BASE)
/** Peripheral IMAGING__ISI2 base address */
#define IMAGING__ISI2_BASE                       (0x58120000u)
/** Peripheral IMAGING__ISI2 base pointer */
#define IMAGING__ISI2                            ((ISI_Type *)IMAGING__ISI2_BASE)
/** Peripheral IMAGING__ISI3 base address */
#define IMAGING__ISI3_BASE                       (0x58130000u)
/** Peripheral IMAGING__ISI3 base pointer */
#define IMAGING__ISI3                            ((ISI_Type *)IMAGING__ISI3_BASE)
/** Peripheral IMAGING__ISI4 base address */
#define IMAGING__ISI4_BASE                       (0x58140000u)
/** Peripheral IMAGING__ISI4 base pointer */
#define IMAGING__ISI4                            ((ISI_Type *)IMAGING__ISI4_BASE)
/** Peripheral IMAGING__ISI5 base address */
#define IMAGING__ISI5_BASE                       (0x58150000u)
/** Peripheral IMAGING__ISI5 base pointer */
#define IMAGING__ISI5                            ((ISI_Type *)IMAGING__ISI5_BASE)
/** Peripheral IMAGING__ISI6 base address */
#define IMAGING__ISI6_BASE                       (0x58160000u)
/** Peripheral IMAGING__ISI6 base pointer */
#define IMAGING__ISI6                            ((ISI_Type *)IMAGING__ISI6_BASE)
/** Peripheral IMAGING__ISI7 base address */
#define IMAGING__ISI7_BASE                       (0x58170000u)
/** Peripheral IMAGING__ISI7 base pointer */
#define IMAGING__ISI7                            ((ISI_Type *)IMAGING__ISI7_BASE)
/** Array initializer of ISI peripheral base addresses */
#define ISI_BASE_ADDRS                           { IMAGING__ISI0_BASE, IMAGING__ISI1_BASE, IMAGING__ISI2_BASE, IMAGING__ISI3_BASE, IMAGING__ISI4_BASE, IMAGING__ISI5_BASE, IMAGING__ISI6_BASE, IMAGING__ISI7_BASE }
/** Array initializer of ISI peripheral base pointers */
#define ISI_BASE_PTRS                            { IMAGING__ISI0, IMAGING__ISI1, IMAGING__ISI2, IMAGING__ISI3, IMAGING__ISI4, IMAGING__ISI5, IMAGING__ISI6, IMAGING__ISI7 }
/** Interrupt vectors for the ISI peripheral type */
#define ISI_IRQS                                 { IMAGING_PDMA_STREAM0_INT_IRQn, IMAGING_PDMA_STREAM1_INT_IRQn, IMAGING_PDMA_STREAM2_INT_IRQn, IMAGING_PDMA_STREAM3_INT_IRQn, IMAGING_PDMA_STREAM4_INT_IRQn, IMAGING_PDMA_STREAM5_INT_IRQn, IMAGING_PDMA_STREAM6_INT_IRQn, IMAGING_PDMA_STREAM7_INT_IRQn }

/*!
 * @}
 */ /* end of group ISI_Peripheral_Access_Layer */
 
 
/* ----------------------------------------------------------------------------
   -- JPEGDEC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup JPEGDEC_Peripheral_Access_Layer JPEGDEC Peripheral Access Layer
 * @{
 */

/** JPEGDEC - Register Layout Typedef */
typedef struct {
  __IO uint32_t GLB_CTRL;                          /**< Global Control, offset: 0x0 */
  __I  uint32_t COM_STATUS;                        /**< Common Status, offset: 0x4 */
  __I  uint32_t RSVD_COM_IRQ_EN;                   /**< RSVD, offset: 0x8 */
  __I  uint32_t RSVD_CUR_DESCPT_PTR;               /**< RSVD, offset: 0xC */
  __I  uint32_t RSVD_NXT_DESCPT_PTR;               /**< RSVD, offset: 0x10 */
  __IO uint32_t OUT_BUF_BASE0;                     /**< Output Image Frame Buffer0 Base Address, offset: 0x14 */
  __IO uint32_t OUT_BUF_BASE1;                     /**< Output Image Frame Buffer1 Base Address, offset: 0x18 */
  __IO uint32_t OUT_PITCH;                         /**< Image Output Buffer Pitch, offset: 0x1C */
  __IO uint32_t STM_BUFBASE;                       /**< Input JPEG Stream Buffer Base Address, offset: 0x20 */
  __IO uint32_t STM_BUFSIZE;                       /**< Input JPEG Stream Buffer Size, offset: 0x24 */
  __IO uint32_t IMGSIZE;                           /**< Image Resolution, offset: 0x28 */
  __IO uint32_t STM_CTRL;                          /**< Bit Stream and Switching Control, offset: 0x2C */
       uint8_t RESERVED_0[65488];
  struct {                                         /* offset: 0x10000, array step: 0x10000 */
    __IO uint32_t SLOT_STATUS;                       /**< Bitstream Status, array offset: 0x10000, array step: 0x10000 */
    __IO uint32_t SLOT_IRQ_EN;                       /**< Bitstream Interrupt Eanble, array offset: 0x10004, array step: 0x10000 */
    __I  uint32_t SLOT_BUF_PTR;                      /**< Bitstream Buffer Pointer, array offset: 0x10008, array step: 0x10000 */
    __I  uint32_t SLOT_CUR_DESCPT_PTR;               /**< Current Descriptors, array offset: 0x1000C, array step: 0x10000 */
    __IO uint32_t SLOT_NXT_DESCPT_PTR;               /**< Next Descriptors, array offset: 0x10010, array step: 0x10000 */
         uint8_t RESERVED_0[65516];
  } BITSTRM_SLOT_REGS[4];
} JPEGDEC_Type;

/* ----------------------------------------------------------------------------
   -- JPEGDEC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup JPEGDEC_Register_Masks JPEGDEC Register Masks
 * @{
 */

/*! @name GLB_CTRL - Global Control */
#define JPEGDEC_GLB_CTRL_JPG_DEC_EN_MASK         (0x1U)
#define JPEGDEC_GLB_CTRL_JPG_DEC_EN_SHIFT        (0U)
#define JPEGDEC_GLB_CTRL_JPG_DEC_EN(x)           (((uint32_t)(((uint32_t)(x)) << JPEGDEC_GLB_CTRL_JPG_DEC_EN_SHIFT)) & JPEGDEC_GLB_CTRL_JPG_DEC_EN_MASK)
#define JPEGDEC_GLB_CTRL_SFTRST_MASK             (0x2U)
#define JPEGDEC_GLB_CTRL_SFTRST_SHIFT            (1U)
#define JPEGDEC_GLB_CTRL_SFTRST(x)               (((uint32_t)(((uint32_t)(x)) << JPEGDEC_GLB_CTRL_SFTRST_SHIFT)) & JPEGDEC_GLB_CTRL_SFTRST_MASK)
#define JPEGDEC_GLB_CTRL_DEC_GO_MASK             (0x4U)
#define JPEGDEC_GLB_CTRL_DEC_GO_SHIFT            (2U)
#define JPEGDEC_GLB_CTRL_DEC_GO(x)               (((uint32_t)(((uint32_t)(x)) << JPEGDEC_GLB_CTRL_DEC_GO_SHIFT)) & JPEGDEC_GLB_CTRL_DEC_GO_MASK)
#define JPEGDEC_GLB_CTRL_L_ENDIAN_MASK           (0x8U)
#define JPEGDEC_GLB_CTRL_L_ENDIAN_SHIFT          (3U)
#define JPEGDEC_GLB_CTRL_L_ENDIAN(x)             (((uint32_t)(((uint32_t)(x)) << JPEGDEC_GLB_CTRL_L_ENDIAN_SHIFT)) & JPEGDEC_GLB_CTRL_L_ENDIAN_MASK)
#define JPEGDEC_GLB_CTRL_SLOT_EN_MASK            (0xF0U)
#define JPEGDEC_GLB_CTRL_SLOT_EN_SHIFT           (4U)
#define JPEGDEC_GLB_CTRL_SLOT_EN(x)              (((uint32_t)(((uint32_t)(x)) << JPEGDEC_GLB_CTRL_SLOT_EN_SHIFT)) & JPEGDEC_GLB_CTRL_SLOT_EN_MASK)

/*! @name COM_STATUS - Common Status */
#define JPEGDEC_COM_STATUS_CUR_SLOT_MASK         (0x60000000U)
#define JPEGDEC_COM_STATUS_CUR_SLOT_SHIFT        (29U)
#define JPEGDEC_COM_STATUS_CUR_SLOT(x)           (((uint32_t)(((uint32_t)(x)) << JPEGDEC_COM_STATUS_CUR_SLOT_SHIFT)) & JPEGDEC_COM_STATUS_CUR_SLOT_MASK)
#define JPEGDEC_COM_STATUS_DEC_ONGOING_MASK      (0x80000000U)
#define JPEGDEC_COM_STATUS_DEC_ONGOING_SHIFT     (31U)
#define JPEGDEC_COM_STATUS_DEC_ONGOING(x)        (((uint32_t)(((uint32_t)(x)) << JPEGDEC_COM_STATUS_DEC_ONGOING_SHIFT)) & JPEGDEC_COM_STATUS_DEC_ONGOING_MASK)

/*! @name OUT_BUF_BASE0 - Output Image Frame Buffer0 Base Address */
#define JPEGDEC_OUT_BUF_BASE0_OUT_BUF_BASE0_MASK (0xFFFFFFF0U)
#define JPEGDEC_OUT_BUF_BASE0_OUT_BUF_BASE0_SHIFT (4U)
#define JPEGDEC_OUT_BUF_BASE0_OUT_BUF_BASE0(x)   (((uint32_t)(((uint32_t)(x)) << JPEGDEC_OUT_BUF_BASE0_OUT_BUF_BASE0_SHIFT)) & JPEGDEC_OUT_BUF_BASE0_OUT_BUF_BASE0_MASK)

/*! @name OUT_BUF_BASE1 - Output Image Frame Buffer1 Base Address */
#define JPEGDEC_OUT_BUF_BASE1_OUT_BUF_BASE1_MASK (0xFFFFFFF0U)
#define JPEGDEC_OUT_BUF_BASE1_OUT_BUF_BASE1_SHIFT (4U)
#define JPEGDEC_OUT_BUF_BASE1_OUT_BUF_BASE1(x)   (((uint32_t)(((uint32_t)(x)) << JPEGDEC_OUT_BUF_BASE1_OUT_BUF_BASE1_SHIFT)) & JPEGDEC_OUT_BUF_BASE1_OUT_BUF_BASE1_MASK)

/*! @name OUT_PITCH - Image Output Buffer Pitch */
#define JPEGDEC_OUT_PITCH_OUT_PITCH_MASK         (0xFFFFU)
#define JPEGDEC_OUT_PITCH_OUT_PITCH_SHIFT        (0U)
#define JPEGDEC_OUT_PITCH_OUT_PITCH(x)           (((uint32_t)(((uint32_t)(x)) << JPEGDEC_OUT_PITCH_OUT_PITCH_SHIFT)) & JPEGDEC_OUT_PITCH_OUT_PITCH_MASK)

/*! @name STM_BUFBASE - Input JPEG Stream Buffer Base Address */
#define JPEGDEC_STM_BUFBASE_STM_BUFBASE_MASK     (0xFFFFFFF0U)
#define JPEGDEC_STM_BUFBASE_STM_BUFBASE_SHIFT    (4U)
#define JPEGDEC_STM_BUFBASE_STM_BUFBASE(x)       (((uint32_t)(((uint32_t)(x)) << JPEGDEC_STM_BUFBASE_STM_BUFBASE_SHIFT)) & JPEGDEC_STM_BUFBASE_STM_BUFBASE_MASK)

/*! @name STM_BUFSIZE - Input JPEG Stream Buffer Size */
#define JPEGDEC_STM_BUFSIZE_STM_BUFSIZE_MASK     (0xFFFFFC00U)
#define JPEGDEC_STM_BUFSIZE_STM_BUFSIZE_SHIFT    (10U)
#define JPEGDEC_STM_BUFSIZE_STM_BUFSIZE(x)       (((uint32_t)(((uint32_t)(x)) << JPEGDEC_STM_BUFSIZE_STM_BUFSIZE_SHIFT)) & JPEGDEC_STM_BUFSIZE_STM_BUFSIZE_MASK)

/*! @name IMGSIZE - Image Resolution */
#define JPEGDEC_IMGSIZE_IMG_HEIGHT_MASK          (0x3FFFU)
#define JPEGDEC_IMGSIZE_IMG_HEIGHT_SHIFT         (0U)
#define JPEGDEC_IMGSIZE_IMG_HEIGHT(x)            (((uint32_t)(((uint32_t)(x)) << JPEGDEC_IMGSIZE_IMG_HEIGHT_SHIFT)) & JPEGDEC_IMGSIZE_IMG_HEIGHT_MASK)
#define JPEGDEC_IMGSIZE_IMG_WIDTH_MASK           (0x3FFF0000U)
#define JPEGDEC_IMGSIZE_IMG_WIDTH_SHIFT          (16U)
#define JPEGDEC_IMGSIZE_IMG_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << JPEGDEC_IMGSIZE_IMG_WIDTH_SHIFT)) & JPEGDEC_IMGSIZE_IMG_WIDTH_MASK)

/*! @name STM_CTRL - Bit Stream and Switching Control */
#define JPEGDEC_STM_CTRL_PIXEL_PRECISION_MASK    (0x4U)
#define JPEGDEC_STM_CTRL_PIXEL_PRECISION_SHIFT   (2U)
#define JPEGDEC_STM_CTRL_PIXEL_PRECISION(x)      (((uint32_t)(((uint32_t)(x)) << JPEGDEC_STM_CTRL_PIXEL_PRECISION_SHIFT)) & JPEGDEC_STM_CTRL_PIXEL_PRECISION_MASK)
#define JPEGDEC_STM_CTRL_IMAGE_FORMAT_MASK       (0x78U)
#define JPEGDEC_STM_CTRL_IMAGE_FORMAT_SHIFT      (3U)
#define JPEGDEC_STM_CTRL_IMAGE_FORMAT(x)         (((uint32_t)(((uint32_t)(x)) << JPEGDEC_STM_CTRL_IMAGE_FORMAT_SHIFT)) & JPEGDEC_STM_CTRL_IMAGE_FORMAT_MASK)
#define JPEGDEC_STM_CTRL_BITBUF_PTR_CLR_MASK     (0x80U)
#define JPEGDEC_STM_CTRL_BITBUF_PTR_CLR_SHIFT    (7U)
#define JPEGDEC_STM_CTRL_BITBUF_PTR_CLR(x)       (((uint32_t)(((uint32_t)(x)) << JPEGDEC_STM_CTRL_BITBUF_PTR_CLR_SHIFT)) & JPEGDEC_STM_CTRL_BITBUF_PTR_CLR_MASK)
#define JPEGDEC_STM_CTRL_AUTO_START_MASK         (0x100U)
#define JPEGDEC_STM_CTRL_AUTO_START_SHIFT        (8U)
#define JPEGDEC_STM_CTRL_AUTO_START(x)           (((uint32_t)(((uint32_t)(x)) << JPEGDEC_STM_CTRL_AUTO_START_SHIFT)) & JPEGDEC_STM_CTRL_AUTO_START_MASK)

/*! @name SLOT_STATUS - Bitstream Status */
#define JPEGDEC_SLOT_STATUS_STMBUF_HALF_MASK     (0x1U)
#define JPEGDEC_SLOT_STATUS_STMBUF_HALF_SHIFT    (0U)
#define JPEGDEC_SLOT_STATUS_STMBUF_HALF(x)       (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_STATUS_STMBUF_HALF_SHIFT)) & JPEGDEC_SLOT_STATUS_STMBUF_HALF_MASK)
#define JPEGDEC_SLOT_STATUS_STMBUF_RTND_MASK     (0x2U)
#define JPEGDEC_SLOT_STATUS_STMBUF_RTND_SHIFT    (1U)
#define JPEGDEC_SLOT_STATUS_STMBUF_RTND(x)       (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_STATUS_STMBUF_RTND_SHIFT)) & JPEGDEC_SLOT_STATUS_STMBUF_RTND_MASK)
#define JPEGDEC_SLOT_STATUS_SWITCHED_IN_MASK     (0x4U)
#define JPEGDEC_SLOT_STATUS_SWITCHED_IN_SHIFT    (2U)
#define JPEGDEC_SLOT_STATUS_SWITCHED_IN(x)       (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_STATUS_SWITCHED_IN_SHIFT)) & JPEGDEC_SLOT_STATUS_SWITCHED_IN_MASK)
#define JPEGDEC_SLOT_STATUS_FRMDONE_MASK         (0x8U)
#define JPEGDEC_SLOT_STATUS_FRMDONE_SHIFT        (3U)
#define JPEGDEC_SLOT_STATUS_FRMDONE(x)           (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_STATUS_FRMDONE_SHIFT)) & JPEGDEC_SLOT_STATUS_FRMDONE_MASK)
#define JPEGDEC_SLOT_STATUS_DECERR_MASK          (0x100U)
#define JPEGDEC_SLOT_STATUS_DECERR_SHIFT         (8U)
#define JPEGDEC_SLOT_STATUS_DECERR(x)            (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_STATUS_DECERR_SHIFT)) & JPEGDEC_SLOT_STATUS_DECERR_MASK)
#define JPEGDEC_SLOT_STATUS_DES_RD_ERR_MASK      (0x200U)
#define JPEGDEC_SLOT_STATUS_DES_RD_ERR_SHIFT     (9U)
#define JPEGDEC_SLOT_STATUS_DES_RD_ERR(x)        (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_STATUS_DES_RD_ERR_SHIFT)) & JPEGDEC_SLOT_STATUS_DES_RD_ERR_MASK)
#define JPEGDEC_SLOT_STATUS_BIT_RD_ERR_MASK      (0x400U)
#define JPEGDEC_SLOT_STATUS_BIT_RD_ERR_SHIFT     (10U)
#define JPEGDEC_SLOT_STATUS_BIT_RD_ERR(x)        (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_STATUS_BIT_RD_ERR_SHIFT)) & JPEGDEC_SLOT_STATUS_BIT_RD_ERR_MASK)
#define JPEGDEC_SLOT_STATUS_PIXEL_WT_ERR_MASK    (0x800U)
#define JPEGDEC_SLOT_STATUS_PIXEL_WT_ERR_SHIFT   (11U)
#define JPEGDEC_SLOT_STATUS_PIXEL_WT_ERR(x)      (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_STATUS_PIXEL_WT_ERR_SHIFT)) & JPEGDEC_SLOT_STATUS_PIXEL_WT_ERR_MASK)
#define JPEGDEC_SLOT_STATUS_CUR_SLOT_MASK        (0x60000000U)
#define JPEGDEC_SLOT_STATUS_CUR_SLOT_SHIFT       (29U)
#define JPEGDEC_SLOT_STATUS_CUR_SLOT(x)          (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_STATUS_CUR_SLOT_SHIFT)) & JPEGDEC_SLOT_STATUS_CUR_SLOT_MASK)
#define JPEGDEC_SLOT_STATUS_DEC_ONGOING_MASK     (0x80000000U)
#define JPEGDEC_SLOT_STATUS_DEC_ONGOING_SHIFT    (31U)
#define JPEGDEC_SLOT_STATUS_DEC_ONGOING(x)       (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_STATUS_DEC_ONGOING_SHIFT)) & JPEGDEC_SLOT_STATUS_DEC_ONGOING_MASK)

/* The count of JPEGDEC_SLOT_STATUS */
#define JPEGDEC_SLOT_STATUS_COUNT                (4U)

/*! @name SLOT_IRQ_EN - Bitstream Interrupt Eanble */
#define JPEGDEC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK (0x1U)
#define JPEGDEC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT (0U)
#define JPEGDEC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT)) & JPEGDEC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK)
#define JPEGDEC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK (0x2U)
#define JPEGDEC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT (1U)
#define JPEGDEC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT)) & JPEGDEC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK)
#define JPEGDEC_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_MASK (0x4U)
#define JPEGDEC_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_SHIFT (2U)
#define JPEGDEC_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_SHIFT)) & JPEGDEC_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_MASK)
#define JPEGDEC_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK  (0x8U)
#define JPEGDEC_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT (3U)
#define JPEGDEC_SLOT_IRQ_EN_FRMDONE_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT)) & JPEGDEC_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK)
#define JPEGDEC_SLOT_IRQ_EN_DECERR_irq_en_MASK   (0x100U)
#define JPEGDEC_SLOT_IRQ_EN_DECERR_irq_en_SHIFT  (8U)
#define JPEGDEC_SLOT_IRQ_EN_DECERR_irq_en(x)     (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_IRQ_EN_DECERR_irq_en_SHIFT)) & JPEGDEC_SLOT_IRQ_EN_DECERR_irq_en_MASK)
#define JPEGDEC_SLOT_IRQ_EN_DES_RD_ERR_irq_en_MASK (0x200U)
#define JPEGDEC_SLOT_IRQ_EN_DES_RD_ERR_irq_en_SHIFT (9U)
#define JPEGDEC_SLOT_IRQ_EN_DES_RD_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_IRQ_EN_DES_RD_ERR_irq_en_SHIFT)) & JPEGDEC_SLOT_IRQ_EN_DES_RD_ERR_irq_en_MASK)
#define JPEGDEC_SLOT_IRQ_EN_BIT_RD_ERR_irq_en_MASK (0x400U)
#define JPEGDEC_SLOT_IRQ_EN_BIT_RD_ERR_irq_en_SHIFT (10U)
#define JPEGDEC_SLOT_IRQ_EN_BIT_RD_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_IRQ_EN_BIT_RD_ERR_irq_en_SHIFT)) & JPEGDEC_SLOT_IRQ_EN_BIT_RD_ERR_irq_en_MASK)
#define JPEGDEC_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en_MASK (0x800U)
#define JPEGDEC_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en_SHIFT (11U)
#define JPEGDEC_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en(x) (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en_SHIFT)) & JPEGDEC_SLOT_IRQ_EN_PIXEL_WT_ERR_irq_en_MASK)

/* The count of JPEGDEC_SLOT_IRQ_EN */
#define JPEGDEC_SLOT_IRQ_EN_COUNT                (4U)

/*! @name SLOT_BUF_PTR - Bitstream Buffer Pointer */
#define JPEGDEC_SLOT_BUF_PTR_stmbuf_ptr_MASK     (0xFFFFFFFFU)
#define JPEGDEC_SLOT_BUF_PTR_stmbuf_ptr_SHIFT    (0U)
#define JPEGDEC_SLOT_BUF_PTR_stmbuf_ptr(x)       (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_BUF_PTR_stmbuf_ptr_SHIFT)) & JPEGDEC_SLOT_BUF_PTR_stmbuf_ptr_MASK)

/* The count of JPEGDEC_SLOT_BUF_PTR */
#define JPEGDEC_SLOT_BUF_PTR_COUNT               (4U)

/*! @name SLOT_CUR_DESCPT_PTR - Current Descriptors */
#define JPEGDEC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK (0xFFFFFFFCU)
#define JPEGDEC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT (2U)
#define JPEGDEC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT)) & JPEGDEC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK)

/* The count of JPEGDEC_SLOT_CUR_DESCPT_PTR */
#define JPEGDEC_SLOT_CUR_DESCPT_PTR_COUNT        (4U)

/*! @name SLOT_NXT_DESCPT_PTR - Next Descriptors */
#define JPEGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_MASK (0x1U)
#define JPEGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_SHIFT (0U)
#define JPEGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_SHIFT)) & JPEGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_MASK)
#define JPEGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK (0xFFFFFFFCU)
#define JPEGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT (2U)
#define JPEGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPEGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT)) & JPEGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK)

/* The count of JPEGDEC_SLOT_NXT_DESCPT_PTR */
#define JPEGDEC_SLOT_NXT_DESCPT_PTR_COUNT        (4U)


/*!
 * @}
 */ /* end of group JPEGDEC_Register_Masks */


/* JPEGDEC - Peripheral instance base addresses */
/** Peripheral IMAGING_JPGDECWRP base address */
#define IMAGING_JPGDECWRP_BASE                   (0x58400000u)
/** Peripheral IMAGING_JPGDECWRP base pointer */
#define IMAGING_JPGDECWRP                        ((JPEGDEC_Type *)IMAGING_JPGDECWRP_BASE)
/** Array initializer of JPEGDEC peripheral base addresses */
#define JPEGDEC_BASE_ADDRS                       { IMAGING_JPGDECWRP_BASE }
/** Array initializer of JPEGDEC peripheral base pointers */
#define JPEGDEC_BASE_PTRS                        { IMAGING_JPGDECWRP }

/*!
 * @}
 */ /* end of group JPEGDEC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- JPEGENC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup JPEGENC_Peripheral_Access_Layer JPEGENC Peripheral Access Layer
 * @{
 */

/** JPEGENC - Register Layout Typedef */
typedef struct {
  __IO uint32_t GLB_CTRL;                          /**< Global Control, offset: 0x0 */
  __I  uint32_t COM_STATUS;                        /**< Common Status, offset: 0x4 */
  __I  uint32_t RSVD_COM_IRQ_EN;                   /**< RSVD, offset: 0x8 */
  __I  uint32_t RSVD_CUR_DESCPT_PTR;               /**< RSVD, offset: 0xC */
  __I  uint32_t RSVD_NXT_DESCPT_PTR;               /**< RSVD, offset: 0x10 */
  __IO uint32_t IN_BUF_BASE0;                      /**< Input Image Frame Buffer0 Base Address, offset: 0x14 */
  __IO uint32_t IN_BUF_BASE1;                      /**< Input Image Frame Buffer1 Base Address, offset: 0x18 */
  __IO uint32_t IN_LINE_PITCH;                     /**< Image Input Buffer Line Pitch, offset: 0x1C */
  __IO uint32_t STM_BUFBASE;                       /**< Output JPEG Stream Buffer Base Address, offset: 0x20 */
  __IO uint32_t STM_BUFSIZE;                       /**< Output JPEG Stream Buffer Size, offset: 0x24 */
  __IO uint32_t IMGSIZE;                           /**< Image Resolution, offset: 0x28 */
  __IO uint32_t STM_CTRL;                          /**< Bit Stream Switch and Control, offset: 0x2C */
       uint8_t RESERVED_0[65488];
  struct {                                         /* offset: 0x10000, array step: 0x10000 */
    __IO uint32_t STATUS;                            /**< Bit Stream SLOT Status, array offset: 0x10000, array step: 0x10000 */
    __IO uint32_t IRQ_EN;                            /**< Bit Stream Interrupt Enable Register, array offset: 0x10004, array step: 0x10000 */
    __I  uint32_t BUF_PTR;                           /**< Bit Stream Buffer Pointer, array offset: 0x10008, array step: 0x10000 */
    __I  uint32_t CUR_DESCPT_PTR;                    /**< Current Encoding Descriptor Pointer, array offset: 0x1000C, array step: 0x10000 */
    __IO uint32_t NXT_DESCPT_PTR;                    /**< Next Encoding Descriptor Pointer, array offset: 0x10010, array step: 0x10000 */
         uint8_t RESERVED_0[65516];
  } SLOT[4];
} JPEGENC_Type;

/* ----------------------------------------------------------------------------
   -- JPEGENC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup JPEGENC_Register_Masks JPEGENC Register Masks
 * @{
 */

/*! @name GLB_CTRL - Global Control */
#define JPEGENC_GLB_CTRL_JPG_ENC_EN_MASK         (0x1U)
#define JPEGENC_GLB_CTRL_JPG_ENC_EN_SHIFT        (0U)
#define JPEGENC_GLB_CTRL_JPG_ENC_EN(x)           (((uint32_t)(((uint32_t)(x)) << JPEGENC_GLB_CTRL_JPG_ENC_EN_SHIFT)) & JPEGENC_GLB_CTRL_JPG_ENC_EN_MASK)
#define JPEGENC_GLB_CTRL_SFTRST_MASK             (0x2U)
#define JPEGENC_GLB_CTRL_SFTRST_SHIFT            (1U)
#define JPEGENC_GLB_CTRL_SFTRST(x)               (((uint32_t)(((uint32_t)(x)) << JPEGENC_GLB_CTRL_SFTRST_SHIFT)) & JPEGENC_GLB_CTRL_SFTRST_MASK)
#define JPEGENC_GLB_CTRL_ENC_GO_MASK             (0x4U)
#define JPEGENC_GLB_CTRL_ENC_GO_SHIFT            (2U)
#define JPEGENC_GLB_CTRL_ENC_GO(x)               (((uint32_t)(((uint32_t)(x)) << JPEGENC_GLB_CTRL_ENC_GO_SHIFT)) & JPEGENC_GLB_CTRL_ENC_GO_MASK)
#define JPEGENC_GLB_CTRL_L_ENDIAN_MASK           (0x8U)
#define JPEGENC_GLB_CTRL_L_ENDIAN_SHIFT          (3U)
#define JPEGENC_GLB_CTRL_L_ENDIAN(x)             (((uint32_t)(((uint32_t)(x)) << JPEGENC_GLB_CTRL_L_ENDIAN_SHIFT)) & JPEGENC_GLB_CTRL_L_ENDIAN_MASK)
#define JPEGENC_GLB_CTRL_SLOT_EN_MASK            (0xF0U)
#define JPEGENC_GLB_CTRL_SLOT_EN_SHIFT           (4U)
#define JPEGENC_GLB_CTRL_SLOT_EN(x)              (((uint32_t)(((uint32_t)(x)) << JPEGENC_GLB_CTRL_SLOT_EN_SHIFT)) & JPEGENC_GLB_CTRL_SLOT_EN_MASK)

/*! @name COM_STATUS - Common Status */
#define JPEGENC_COM_STATUS_CUR_SLOT_MASK         (0x60000000U)
#define JPEGENC_COM_STATUS_CUR_SLOT_SHIFT        (29U)
#define JPEGENC_COM_STATUS_CUR_SLOT(x)           (((uint32_t)(((uint32_t)(x)) << JPEGENC_COM_STATUS_CUR_SLOT_SHIFT)) & JPEGENC_COM_STATUS_CUR_SLOT_MASK)
#define JPEGENC_COM_STATUS_ENC_ONGOING_MASK      (0x80000000U)
#define JPEGENC_COM_STATUS_ENC_ONGOING_SHIFT     (31U)
#define JPEGENC_COM_STATUS_ENC_ONGOING(x)        (((uint32_t)(((uint32_t)(x)) << JPEGENC_COM_STATUS_ENC_ONGOING_SHIFT)) & JPEGENC_COM_STATUS_ENC_ONGOING_MASK)

/*! @name IN_BUF_BASE0 - Input Image Frame Buffer0 Base Address */
#define JPEGENC_IN_BUF_BASE0_IN_BUF_BASE0_MASK   (0xFFFFFFF0U)
#define JPEGENC_IN_BUF_BASE0_IN_BUF_BASE0_SHIFT  (4U)
#define JPEGENC_IN_BUF_BASE0_IN_BUF_BASE0(x)     (((uint32_t)(((uint32_t)(x)) << JPEGENC_IN_BUF_BASE0_IN_BUF_BASE0_SHIFT)) & JPEGENC_IN_BUF_BASE0_IN_BUF_BASE0_MASK)

/*! @name IN_BUF_BASE1 - Input Image Frame Buffer1 Base Address */
#define JPEGENC_IN_BUF_BASE1_IN_BUF_BASE1_MASK   (0xFFFFFFF0U)
#define JPEGENC_IN_BUF_BASE1_IN_BUF_BASE1_SHIFT  (4U)
#define JPEGENC_IN_BUF_BASE1_IN_BUF_BASE1(x)     (((uint32_t)(((uint32_t)(x)) << JPEGENC_IN_BUF_BASE1_IN_BUF_BASE1_SHIFT)) & JPEGENC_IN_BUF_BASE1_IN_BUF_BASE1_MASK)

/*! @name IN_LINE_PITCH - Image Input Buffer Line Pitch */
#define JPEGENC_IN_LINE_PITCH_In_line_pitch_MASK (0xFFFFU)
#define JPEGENC_IN_LINE_PITCH_In_line_pitch_SHIFT (0U)
#define JPEGENC_IN_LINE_PITCH_In_line_pitch(x)   (((uint32_t)(((uint32_t)(x)) << JPEGENC_IN_LINE_PITCH_In_line_pitch_SHIFT)) & JPEGENC_IN_LINE_PITCH_In_line_pitch_MASK)

/*! @name STM_BUFBASE - Output JPEG Stream Buffer Base Address */
#define JPEGENC_STM_BUFBASE_STM_BUFBASE_MASK     (0xFFFFFFF0U)
#define JPEGENC_STM_BUFBASE_STM_BUFBASE_SHIFT    (4U)
#define JPEGENC_STM_BUFBASE_STM_BUFBASE(x)       (((uint32_t)(((uint32_t)(x)) << JPEGENC_STM_BUFBASE_STM_BUFBASE_SHIFT)) & JPEGENC_STM_BUFBASE_STM_BUFBASE_MASK)

/*! @name STM_BUFSIZE - Output JPEG Stream Buffer Size */
#define JPEGENC_STM_BUFSIZE_STM_BUFSIZE_MASK     (0xFFFFFC00U)
#define JPEGENC_STM_BUFSIZE_STM_BUFSIZE_SHIFT    (10U)
#define JPEGENC_STM_BUFSIZE_STM_BUFSIZE(x)       (((uint32_t)(((uint32_t)(x)) << JPEGENC_STM_BUFSIZE_STM_BUFSIZE_SHIFT)) & JPEGENC_STM_BUFSIZE_STM_BUFSIZE_MASK)

/*! @name IMGSIZE - Image Resolution */
#define JPEGENC_IMGSIZE_img_height_MASK          (0x3FFFU)
#define JPEGENC_IMGSIZE_img_height_SHIFT         (0U)
#define JPEGENC_IMGSIZE_img_height(x)            (((uint32_t)(((uint32_t)(x)) << JPEGENC_IMGSIZE_img_height_SHIFT)) & JPEGENC_IMGSIZE_img_height_MASK)
#define JPEGENC_IMGSIZE_img_width_MASK           (0x3FFF0000U)
#define JPEGENC_IMGSIZE_img_width_SHIFT          (16U)
#define JPEGENC_IMGSIZE_img_width(x)             (((uint32_t)(((uint32_t)(x)) << JPEGENC_IMGSIZE_img_width_SHIFT)) & JPEGENC_IMGSIZE_img_width_MASK)

/*! @name STM_CTRL - Bit Stream Switch and Control */
#define JPEGENC_STM_CTRL_pixel_precision_MASK    (0x4U)
#define JPEGENC_STM_CTRL_pixel_precision_SHIFT   (2U)
#define JPEGENC_STM_CTRL_pixel_precision(x)      (((uint32_t)(((uint32_t)(x)) << JPEGENC_STM_CTRL_pixel_precision_SHIFT)) & JPEGENC_STM_CTRL_pixel_precision_MASK)
#define JPEGENC_STM_CTRL_image_format_MASK       (0x78U)
#define JPEGENC_STM_CTRL_image_format_SHIFT      (3U)
#define JPEGENC_STM_CTRL_image_format(x)         (((uint32_t)(((uint32_t)(x)) << JPEGENC_STM_CTRL_image_format_SHIFT)) & JPEGENC_STM_CTRL_image_format_MASK)
#define JPEGENC_STM_CTRL_bitbuf_ptr_clr_MASK     (0x80U)
#define JPEGENC_STM_CTRL_bitbuf_ptr_clr_SHIFT    (7U)
#define JPEGENC_STM_CTRL_bitbuf_ptr_clr(x)       (((uint32_t)(((uint32_t)(x)) << JPEGENC_STM_CTRL_bitbuf_ptr_clr_SHIFT)) & JPEGENC_STM_CTRL_bitbuf_ptr_clr_MASK)
#define JPEGENC_STM_CTRL_AUTO_START_MASK         (0x100U)
#define JPEGENC_STM_CTRL_AUTO_START_SHIFT        (8U)
#define JPEGENC_STM_CTRL_AUTO_START(x)           (((uint32_t)(((uint32_t)(x)) << JPEGENC_STM_CTRL_AUTO_START_SHIFT)) & JPEGENC_STM_CTRL_AUTO_START_MASK)
#define JPEGENC_STM_CTRL_Config_Mod_MASK         (0x200U)
#define JPEGENC_STM_CTRL_Config_Mod_SHIFT        (9U)
#define JPEGENC_STM_CTRL_Config_Mod(x)           (((uint32_t)(((uint32_t)(x)) << JPEGENC_STM_CTRL_Config_Mod_SHIFT)) & JPEGENC_STM_CTRL_Config_Mod_MASK)

/*! @name STATUS - Bit Stream SLOT Status */
#define JPEGENC_STATUS_STMBUF_HALF_MASK          (0x1U)
#define JPEGENC_STATUS_STMBUF_HALF_SHIFT         (0U)
#define JPEGENC_STATUS_STMBUF_HALF(x)            (((uint32_t)(((uint32_t)(x)) << JPEGENC_STATUS_STMBUF_HALF_SHIFT)) & JPEGENC_STATUS_STMBUF_HALF_MASK)
#define JPEGENC_STATUS_STMBUF_RTND_MASK          (0x2U)
#define JPEGENC_STATUS_STMBUF_RTND_SHIFT         (1U)
#define JPEGENC_STATUS_STMBUF_RTND(x)            (((uint32_t)(((uint32_t)(x)) << JPEGENC_STATUS_STMBUF_RTND_SHIFT)) & JPEGENC_STATUS_STMBUF_RTND_MASK)
#define JPEGENC_STATUS_SWITCHED_IN_MASK          (0x4U)
#define JPEGENC_STATUS_SWITCHED_IN_SHIFT         (2U)
#define JPEGENC_STATUS_SWITCHED_IN(x)            (((uint32_t)(((uint32_t)(x)) << JPEGENC_STATUS_SWITCHED_IN_SHIFT)) & JPEGENC_STATUS_SWITCHED_IN_MASK)
#define JPEGENC_STATUS_FRMDONE_MASK              (0x8U)
#define JPEGENC_STATUS_FRMDONE_SHIFT             (3U)
#define JPEGENC_STATUS_FRMDONE(x)                (((uint32_t)(((uint32_t)(x)) << JPEGENC_STATUS_FRMDONE_SHIFT)) & JPEGENC_STATUS_FRMDONE_MASK)
#define JPEGENC_STATUS_ENC_CONFG_ERR_MASK        (0x100U)
#define JPEGENC_STATUS_ENC_CONFG_ERR_SHIFT       (8U)
#define JPEGENC_STATUS_ENC_CONFG_ERR(x)          (((uint32_t)(((uint32_t)(x)) << JPEGENC_STATUS_ENC_CONFG_ERR_SHIFT)) & JPEGENC_STATUS_ENC_CONFG_ERR_MASK)
#define JPEGENC_STATUS_DES_RD_ERR_MASK           (0x200U)
#define JPEGENC_STATUS_DES_RD_ERR_SHIFT          (9U)
#define JPEGENC_STATUS_DES_RD_ERR(x)             (((uint32_t)(((uint32_t)(x)) << JPEGENC_STATUS_DES_RD_ERR_SHIFT)) & JPEGENC_STATUS_DES_RD_ERR_MASK)
#define JPEGENC_STATUS_BIT_WT_ERR_MASK           (0x400U)
#define JPEGENC_STATUS_BIT_WT_ERR_SHIFT          (10U)
#define JPEGENC_STATUS_BIT_WT_ERR(x)             (((uint32_t)(((uint32_t)(x)) << JPEGENC_STATUS_BIT_WT_ERR_SHIFT)) & JPEGENC_STATUS_BIT_WT_ERR_MASK)
#define JPEGENC_STATUS_IMG_RD_ERR_MASK           (0x800U)
#define JPEGENC_STATUS_IMG_RD_ERR_SHIFT          (11U)
#define JPEGENC_STATUS_IMG_RD_ERR(x)             (((uint32_t)(((uint32_t)(x)) << JPEGENC_STATUS_IMG_RD_ERR_SHIFT)) & JPEGENC_STATUS_IMG_RD_ERR_MASK)
#define JPEGENC_STATUS_CUR_SLOT_MASK             (0x60000000U)
#define JPEGENC_STATUS_CUR_SLOT_SHIFT            (29U)
#define JPEGENC_STATUS_CUR_SLOT(x)               (((uint32_t)(((uint32_t)(x)) << JPEGENC_STATUS_CUR_SLOT_SHIFT)) & JPEGENC_STATUS_CUR_SLOT_MASK)
#define JPEGENC_STATUS_ENC_ONGOING_MASK          (0x80000000U)
#define JPEGENC_STATUS_ENC_ONGOING_SHIFT         (31U)
#define JPEGENC_STATUS_ENC_ONGOING(x)            (((uint32_t)(((uint32_t)(x)) << JPEGENC_STATUS_ENC_ONGOING_SHIFT)) & JPEGENC_STATUS_ENC_ONGOING_MASK)

/* The count of JPEGENC_STATUS */
#define JPEGENC_STATUS_COUNT                     (4U)

/*! @name IRQ_EN - Bit Stream Interrupt Enable Register */
#define JPEGENC_IRQ_EN_STMBUF_HALF_irq_en_MASK   (0x1U)
#define JPEGENC_IRQ_EN_STMBUF_HALF_irq_en_SHIFT  (0U)
#define JPEGENC_IRQ_EN_STMBUF_HALF_irq_en(x)     (((uint32_t)(((uint32_t)(x)) << JPEGENC_IRQ_EN_STMBUF_HALF_irq_en_SHIFT)) & JPEGENC_IRQ_EN_STMBUF_HALF_irq_en_MASK)
#define JPEGENC_IRQ_EN_STMBUF_RTND_irq_en_MASK   (0x2U)
#define JPEGENC_IRQ_EN_STMBUF_RTND_irq_en_SHIFT  (1U)
#define JPEGENC_IRQ_EN_STMBUF_RTND_irq_en(x)     (((uint32_t)(((uint32_t)(x)) << JPEGENC_IRQ_EN_STMBUF_RTND_irq_en_SHIFT)) & JPEGENC_IRQ_EN_STMBUF_RTND_irq_en_MASK)
#define JPEGENC_IRQ_EN_SWITHCED_IN_irq_en_MASK   (0x4U)
#define JPEGENC_IRQ_EN_SWITHCED_IN_irq_en_SHIFT  (2U)
#define JPEGENC_IRQ_EN_SWITHCED_IN_irq_en(x)     (((uint32_t)(((uint32_t)(x)) << JPEGENC_IRQ_EN_SWITHCED_IN_irq_en_SHIFT)) & JPEGENC_IRQ_EN_SWITHCED_IN_irq_en_MASK)
#define JPEGENC_IRQ_EN_FRMDONE_irq_en_MASK       (0x8U)
#define JPEGENC_IRQ_EN_FRMDONE_irq_en_SHIFT      (3U)
#define JPEGENC_IRQ_EN_FRMDONE_irq_en(x)         (((uint32_t)(((uint32_t)(x)) << JPEGENC_IRQ_EN_FRMDONE_irq_en_SHIFT)) & JPEGENC_IRQ_EN_FRMDONE_irq_en_MASK)
#define JPEGENC_IRQ_EN_ENC_CONFG_ERR_irq_en_MASK (0x100U)
#define JPEGENC_IRQ_EN_ENC_CONFG_ERR_irq_en_SHIFT (8U)
#define JPEGENC_IRQ_EN_ENC_CONFG_ERR_irq_en(x)   (((uint32_t)(((uint32_t)(x)) << JPEGENC_IRQ_EN_ENC_CONFG_ERR_irq_en_SHIFT)) & JPEGENC_IRQ_EN_ENC_CONFG_ERR_irq_en_MASK)
#define JPEGENC_IRQ_EN_DES_RD_ERR_irq_en_MASK    (0x200U)
#define JPEGENC_IRQ_EN_DES_RD_ERR_irq_en_SHIFT   (9U)
#define JPEGENC_IRQ_EN_DES_RD_ERR_irq_en(x)      (((uint32_t)(((uint32_t)(x)) << JPEGENC_IRQ_EN_DES_RD_ERR_irq_en_SHIFT)) & JPEGENC_IRQ_EN_DES_RD_ERR_irq_en_MASK)
#define JPEGENC_IRQ_EN_BIT_WT_ERR_irq_en_MASK    (0x400U)
#define JPEGENC_IRQ_EN_BIT_WT_ERR_irq_en_SHIFT   (10U)
#define JPEGENC_IRQ_EN_BIT_WT_ERR_irq_en(x)      (((uint32_t)(((uint32_t)(x)) << JPEGENC_IRQ_EN_BIT_WT_ERR_irq_en_SHIFT)) & JPEGENC_IRQ_EN_BIT_WT_ERR_irq_en_MASK)
#define JPEGENC_IRQ_EN_IMG_RD_ERR_irq_en_MASK    (0x800U)
#define JPEGENC_IRQ_EN_IMG_RD_ERR_irq_en_SHIFT   (11U)
#define JPEGENC_IRQ_EN_IMG_RD_ERR_irq_en(x)      (((uint32_t)(((uint32_t)(x)) << JPEGENC_IRQ_EN_IMG_RD_ERR_irq_en_SHIFT)) & JPEGENC_IRQ_EN_IMG_RD_ERR_irq_en_MASK)

/* The count of JPEGENC_IRQ_EN */
#define JPEGENC_IRQ_EN_COUNT                     (4U)

/*! @name BUF_PTR - Bit Stream Buffer Pointer */
#define JPEGENC_BUF_PTR_stmbuf_ptr_MASK          (0xFFFFFFFFU)
#define JPEGENC_BUF_PTR_stmbuf_ptr_SHIFT         (0U)
#define JPEGENC_BUF_PTR_stmbuf_ptr(x)            (((uint32_t)(((uint32_t)(x)) << JPEGENC_BUF_PTR_stmbuf_ptr_SHIFT)) & JPEGENC_BUF_PTR_stmbuf_ptr_MASK)

/* The count of JPEGENC_BUF_PTR */
#define JPEGENC_BUF_PTR_COUNT                    (4U)

/*! @name CUR_DESCPT_PTR - Current Encoding Descriptor Pointer */
#define JPEGENC_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK (0xFFFFFFFCU)
#define JPEGENC_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT (2U)
#define JPEGENC_CUR_DESCPT_PTR_CUR_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPEGENC_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT)) & JPEGENC_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK)

/* The count of JPEGENC_CUR_DESCPT_PTR */
#define JPEGENC_CUR_DESCPT_PTR_COUNT             (4U)

/*! @name NXT_DESCPT_PTR - Next Encoding Descriptor Pointer */
#define JPEGENC_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_MASK (0x1U)
#define JPEGENC_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_SHIFT (0U)
#define JPEGENC_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEGENC_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_SHIFT)) & JPEGENC_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_MASK)
#define JPEGENC_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK (0xFFFFFFFCU)
#define JPEGENC_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT (2U)
#define JPEGENC_NXT_DESCPT_PTR_NXT_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPEGENC_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT)) & JPEGENC_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK)

/* The count of JPEGENC_NXT_DESCPT_PTR */
#define JPEGENC_NXT_DESCPT_PTR_COUNT             (4U)


/*!
 * @}
 */ /* end of group JPEGENC_Register_Masks */


/* JPEGENC - Peripheral instance base addresses */
/** Peripheral IMAGING_JPGENCWRP base address */
#define IMAGING_JPGENCWRP_BASE                   (0x58450000u)
/** Peripheral IMAGING_JPGENCWRP base pointer */
#define IMAGING_JPGENCWRP                        ((JPEGENC_Type *)IMAGING_JPGENCWRP_BASE)
/** Array initializer of JPEGENC peripheral base addresses */
#define JPEGENC_BASE_ADDRS                       { IMAGING_JPGENCWRP_BASE }
/** Array initializer of JPEGENC peripheral base pointers */
#define JPEGENC_BASE_PTRS                        { IMAGING_JPGENCWRP }

/*!
 * @}
 */ /* end of group JPEGENC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- KPP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer
 * @{
 */

/** KPP - Register Layout Typedef */
typedef struct {
  __IO uint16_t KPCR;                              /**< Keypad Control Register, offset: 0x0 */
  __IO uint16_t KPSR;                              /**< Keypad Status Register, offset: 0x2 */
  __IO uint16_t KDDR;                              /**< Keypad Data Direction Register, offset: 0x4 */
  __IO uint16_t KPDR;                              /**< Keypad Data Register, offset: 0x6 */
} KPP_Type;

/* ----------------------------------------------------------------------------
   -- KPP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup KPP_Register_Masks KPP Register Masks
 * @{
 */

/*! @name KPCR - Keypad Control Register */
/*! @{ */
#define KPP_KPCR_KRE_MASK                        (0xFFU)
#define KPP_KPCR_KRE_SHIFT                       (0U)
/*! KRE - KRE
 *  0b00000000..Row is not included in the keypad key press detect.
 *  0b00000001..Row is included in the keypad key press detect.
 */
#define KPP_KPCR_KRE(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
#define KPP_KPCR_KCO_MASK                        (0xFF00U)
#define KPP_KPCR_KCO_SHIFT                       (8U)
/*! KCO - KCO
 *  0b00000000..Column strobe output is totem pole drive.
 *  0b00000001..Column strobe output is open drain.
 */
#define KPP_KPCR_KCO(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
/*! @} */

/*! @name KPSR - Keypad Status Register */
/*! @{ */
#define KPP_KPSR_KPKD_MASK                       (0x1U)
#define KPP_KPSR_KPKD_SHIFT                      (0U)
/*! KPKD - KPKD
 *  0b0..No key presses detected
 *  0b1..A key has been depressed
 */
#define KPP_KPSR_KPKD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
#define KPP_KPSR_KPKR_MASK                       (0x2U)
#define KPP_KPSR_KPKR_SHIFT                      (1U)
/*! KPKR - KPKR
 *  0b0..No key release detected
 *  0b1..All keys have been released
 */
#define KPP_KPSR_KPKR(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
#define KPP_KPSR_KDSC_MASK                       (0x4U)
#define KPP_KPSR_KDSC_SHIFT                      (2U)
/*! KDSC - KDSC
 *  0b0..No effect
 *  0b1..Set bits that clear the keypad depress synchronizer chain
 */
#define KPP_KPSR_KDSC(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
#define KPP_KPSR_KRSS_MASK                       (0x8U)
#define KPP_KPSR_KRSS_SHIFT                      (3U)
/*! KRSS - KRSS
 *  0b0..No effect
 *  0b1..Set bits which sets keypad release synchronizer chain
 */
#define KPP_KPSR_KRSS(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
#define KPP_KPSR_KDIE_MASK                       (0x100U)
#define KPP_KPSR_KDIE_SHIFT                      (8U)
/*! KDIE - KDIE
 *  0b0..No interrupt request is generated when KPKD is set.
 *  0b1..An interrupt request is generated when KPKD is set.
 */
#define KPP_KPSR_KDIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
#define KPP_KPSR_KRIE_MASK                       (0x200U)
#define KPP_KPSR_KRIE_SHIFT                      (9U)
/*! KRIE - KRIE
 *  0b0..No interrupt request is generated when KPKR is set.
 *  0b1..An interrupt request is generated when KPKR is set.
 */
#define KPP_KPSR_KRIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
#define KPP_KPSR_KPP_EN_MASK                     (0x400U)
#define KPP_KPSR_KPP_EN_SHIFT                    (10U)
/*! KPP_EN - KPP_EN
 *  0b0..Disable high frequency clock to Keypad module.
 *  0b1..Enable high frequency clock to Keypad module.
 */
#define KPP_KPSR_KPP_EN(x)                       (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPP_EN_SHIFT)) & KPP_KPSR_KPP_EN_MASK)
/*! @} */

/*! @name KDDR - Keypad Data Direction Register */
/*! @{ */
#define KPP_KDDR_KRDD_MASK                       (0xFFU)
#define KPP_KDDR_KRDD_SHIFT                      (0U)
/*! KRDD - KRDD
 *  0b00000000..ROWn pin configured as an input.
 *  0b00000001..ROWn pin configured as an output.
 */
#define KPP_KDDR_KRDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
#define KPP_KDDR_KCDD_MASK                       (0xFF00U)
#define KPP_KDDR_KCDD_SHIFT                      (8U)
/*! KCDD - KCDD
 *  0b00000000..COLn pin is configured as an input.
 *  0b00000001..COLn pin is configured as an output.
 */
#define KPP_KDDR_KCDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
/*! @} */

/*! @name KPDR - Keypad Data Register */
/*! @{ */
#define KPP_KPDR_KRD_MASK                        (0xFFU)
#define KPP_KPDR_KRD_SHIFT                       (0U)
#define KPP_KPDR_KRD(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
#define KPP_KPDR_KCD_MASK                        (0xFF00U)
#define KPP_KPDR_KCD_SHIFT                       (8U)
#define KPP_KPDR_KCD(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group KPP_Register_Masks */


/* KPP - Peripheral instance base addresses */
/** Peripheral LSIO__KPP base address */
#define LSIO__KPP_BASE                           (0x5D1A0000u)
/** Peripheral LSIO__KPP base pointer */
#define LSIO__KPP                                ((KPP_Type *)LSIO__KPP_BASE)
/** Array initializer of KPP peripheral base addresses */
#define KPP_BASE_ADDRS                           { LSIO__KPP_BASE }
/** Array initializer of KPP peripheral base pointers */
#define KPP_BASE_PTRS                            { LSIO__KPP }

/*!
 * @}
 */ /* end of group KPP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LDB Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LDB_Peripheral_Access_Layer LDB Peripheral Access Layer
 * @{
 */

/** LDB - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[0x1000];
  __IO uint32_t PHY_CTRL;
       uint8_t RESERVED_1[0x0C];
  __IO uint32_t PHY_STATUS;
       uint8_t RESERVED_2[0x0C];
  __IO uint32_t PHY_SS_CTRL;
       uint8_t RESERVED_3[0xBC];
  __IO uint32_t PM_CTRL_REG;
} LDB_Type;

/* ----------------------------------------------------------------------------
   -- LDB Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LDB_Register_Masks LDB Register Masks
 * @{
 */

/*! @name PHY_CTRL - LDB Phy control */

#define LDB_PHY_CTRL_PD_MASK           (0x1U)
#define LDB_PHY_CTRL_PD_SHIFT          (0U)
#define LDB_PHY_CTRL_PD(x)             (((uint32_t)(((uint32_t)(x)) << LDB_PHY_CTRL_PD_SHIFT)) & LDB_PHY_CTRL_PD_MASK)

#define LDB_PHY_CTRL_RFB_MASK          (0x2U)
#define LDB_PHY_CTRL_RFB_SHIFT         (1U)
#define LDB_PHY_CTRL_RFB(x)            (((uint32_t)(((uint32_t)(x)) << LDB_PHY_CTRL_RFB_SHIFT)) & LDB_PHY_CTRL_RFB_MASK)

#define LDB_PHY_CTRL_NB_MASK           (0x4U)
#define LDB_PHY_CTRL_NB_SHIFT          (2U)
#define LDB_PHY_CTRL_NB(x)             (((uint32_t)(((uint32_t)(x)) << LDB_PHY_CTRL_NB_SHIFT)) & LDB_PHY_CTRL_NB_MASK)

#define LDB_PHY_CTRL_CH0_EN_MASK       (0x8U)
#define LDB_PHY_CTRL_CH0_EN_SHIFT      (3U)
#define LDB_PHY_CTRL_CH0_EN(x)         (((uint32_t)(((uint32_t)(x)) << LDB_PHY_CTRL_CH0_EN_SHIFT)) & LDB_PHY_CTRL_CH0_EN_MASK)

#define LDB_PHY_CTRL_CH1_EN_MASK       (0x10U)
#define LDB_PHY_CTRL_CH1_EN_SHIFT      (4U)
#define LDB_PHY_CTRL_CH1_EN(x)         (((uint32_t)(((uint32_t)(x)) << LDB_PHY_CTRL_CH1_EN_SHIFT)) & LDB_PHY_CTRL_CH1_EN_MASK)

#define LDB_PHY_CTRL_TST_MASK          (0x7E0U)
#define LDB_PHY_CTRL_TST_SHIFT         (5U)
#define LDB_PHY_CTRL_TST(x)            (((uint32_t)(((uint32_t)(x)) << LDB_PHY_CTRL_TST_SHIFT)) & LDB_PHY_CTRL_TST_MASK)

#define LDB_PHY_CTRL_CA_MASK           (0x3800U)
#define LDB_PHY_CTRL_CA_SHIFT          (11U)
#define LDB_PHY_CTRL_CA(x)             (((uint32_t)(((uint32_t)(x)) << LDB_PHY_CTRL_CA_SHIFT)) & LDB_PHY_CTRL_CA_MASK)

#define LDB_PHY_CTRL_CCM_MASK          (0x1C000U)
#define LDB_PHY_CTRL_CCM_SHIFT         (14U)
#define LDB_PHY_CTRL_CCM(x)            (((uint32_t)(((uint32_t)(x)) << LDB_PHY_CTRL_CCM_SHIFT)) & LDB_PHY_CTRL_CCM_MASK)

#define LDB_PHY_CTRL_M_MASK            (0x60000U)
#define LDB_PHY_CTRL_M_SHIFT           (17U)
#define LDB_PHY_CTRL_M(x)              (((uint32_t)(((uint32_t)(x)) << LDB_PHY_CTRL_M_SHIFT)) & LDB_PHY_CTRL_M_MASK)

/*! @name PHY_STATUS - LDB Phy status */
#define LDB_PHY_STATUS_LOCK_MASK           (0x1U)
#define LDB_PHY_STATUS_LOCK_SHIFT          (0U)
#define LDB_PHY_STATUS_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << LDB_PHY_STATUS_LOCK_SHIFT)) & LDB_PHY_STATUS_LOCK_MASK)

/*! @name SS_CTRL - SS control */
#define LDB_SS_CTRL_CH0_HSYNC_POL_MASK     (0x1U)
#define LDB_SS_CTRL_CH0_HSYNC_POL_SHIFT    (0U)
#define LDB_SS_CTRL_CH0_HSYNC_POL(x)       (((uint32_t)(((uint32_t)(x)) << LDB_SS_CTRL_CH0_HSYNC_POL_SHIFT)) & LDB_SS_CTRL_CH0_HSYNC_POL_MASK)

#define LDB_SS_CTRL_CH0_VSYNC_POL_MASK     (0x2U)
#define LDB_SS_CTRL_CH0_VSYNC_POL_SHIFT    (1U)
#define LDB_SS_CTRL_CH0_VSYNC_POL(x)       (((uint32_t)(((uint32_t)(x)) << LDB_SS_CTRL_CH0_VSYNC_POL_SHIFT)) & LDB_SS_CTRL_CH0_VSYNC_POL_MASK)

#define LDB_SS_CTRL_CH1_HSYNC_POL_MASK     (0x4U)
#define LDB_SS_CTRL_CH1_HSYNC_POL_SHIFT    (2U)
#define LDB_SS_CTRL_CH1_HSYNC_POL(x)       (((uint32_t)(((uint32_t)(x)) << LDB_SS_CTRL_CH1_HSYNC_POL_SHIFT)) & LDB_SS_CTRL_CH1_HSYNC_POL_MASK)

#define LDB_SS_CTRL_CH1_VSYNC_POL_MASK     (0x8U)
#define LDB_SS_CTRL_CH1_VSYNC_POL_SHIFT    (3U)
#define LDB_SS_CTRL_CH1_VSYNC_POL(x)       (((uint32_t)(((uint32_t)(x)) << LDB_SS_CTRL_CH1_VSYNC_POL_SHIFT)) & LDB_SS_CTRL_CH1_VSYNC_POL_MASK)


/*! @name PM_CTRL_REG - pixel mapper the control register */

#define LDB_PM_CTRL_REG_CH0_MODE_MASK           (0x3U)
#define LDB_PM_CTRL_REG_CH0_MODE_SHIFT          (0U)
#define LDB_PM_CTRL_REG_CH0_MODE(x)             (((uint32_t)(((uint32_t)(x)) << LDB_PM_CTRL_REG_CH0_MODE_SHIFT)) & LDB_PM_CTRL_REG_CH0_MODE_MASK)

#define LDB_PM_CTRL_REG_CH1_MODE_MASK           (0xCU)
#define LDB_PM_CTRL_REG_CH1_MODE_SHIFT          (2U)
#define LDB_PM_CTRL_REG_CH1_MODE(x)             (((uint32_t)(((uint32_t)(x)) << LDB_PM_CTRL_REG_CH1_MODE_SHIFT)) & LDB_PM_CTRL_REG_CH1_MODE_MASK)

#define LDB_PM_CTRL_REG_SPLIT_MODE_EN_MASK      (0x10U)
#define LDB_PM_CTRL_REG_SPLIT_MODE_EN_SHIFT     (4U)
#define LDB_PM_CTRL_REG_SPLIT_MODE_EN(x)        (((uint32_t)(((uint32_t)(x)) << LDB_PM_CTRL_REG_SPLIT_MODE_EN_SHIFT)) & LDB_PM_CTRL_REG_SPLIT_MODE_EN_MASK)

#define LDB_PM_CTRL_REG_CH0_DATA_WIDTH_MASK     (0x20U)
#define LDB_PM_CTRL_REG_CH0_DATA_WIDTH_SHIFT    (5U)
#define LDB_PM_CTRL_REG_CH0_DATA_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << LDB_PM_CTRL_REG_CH0_DATA_WIDTH_SHIFT)) & LDB_PM_CTRL_REG_CH0_DATA_WIDTH_MASK)

#define LDB_PM_CTRL_REG_CH0_BIT_MAPPING_MASK    (0x40U)
#define LDB_PM_CTRL_REG_CH0_BIT_MAPPING_SHIFT   (6U)
#define LDB_PM_CTRL_REG_CH0_BIT_MAPPING(x)      (((uint32_t)(((uint32_t)(x)) << LDB_PM_CTRL_REG_CH0_BIT_MAPPING_SHIFT)) & LDB_PM_CTRL_REG_CH0_BIT_MAPPING_MASK)

#define LDB_PM_CTRL_REG_CH1_DATA_WIDTH_MASK     (0x80U)
#define LDB_PM_CTRL_REG_CH1_DATA_WIDTH_SHIFT    (7U)
#define LDB_PM_CTRL_REG_CH1_DATA_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << LDB_PM_CTRL_REG_CH1_DATA_WIDTH_SHIFT)) & LDB_PM_CTRL_REG_CH1_DATA_WIDTH_MASK)

#define LDB_PM_CTRL_REG_CH1_BIT_MAPPING_MASK    (0x100U)
#define LDB_PM_CTRL_REG_CH1_BIT_MAPPING_SHIFT   (8U)
#define LDB_PM_CTRL_REG_CH1_BIT_MAPPING(x)      (((uint32_t)(((uint32_t)(x)) << LDB_PM_CTRL_REG_CH1_BIT_MAPPING_SHIFT)) & LDB_PM_CTRL_REG_CH1_BIT_MAPPING_MASK)

#define LDB_PM_CTRL_REG_DI0_VS_POLARITY_MASK    (0x200U)
#define LDB_PM_CTRL_REG_DI0_VS_POLARITY_SHIFT   (9U)
#define LDB_PM_CTRL_REG_DI0_VS_POLARITY(x)      (((uint32_t)(((uint32_t)(x)) << LDB_PM_CTRL_REG_DI0_VS_POLARITY_SHIFT)) & LDB_PM_CTRL_REG_DI0_VS_POLARITY_MASK)

#define LDB_PM_CTRL_REG_DI1_VS_POLARITY_MASK    (0x400U)
#define LDB_PM_CTRL_REG_DI1_VS_POLARITY_SHIFT   (10U)
#define LDB_PM_CTRL_REG_DI1_VS_POLARITY(x)      (((uint32_t)(((uint32_t)(x)) << LDB_PM_CTRL_REG_DI1_VS_POLARITY_SHIFT)) & LDB_PM_CTRL_REG_DI1_VS_POLARITY_MASK)

#define LDB_PM_CTRL_REG_CH0_10B_EN_MASK         (0x400000U)
#define LDB_PM_CTRL_REG_CH0_10B_EN_SHIFT        (22U)
#define LDB_PM_CTRL_REG_CH0_10B_EN(x)           (((uint32_t)(((uint32_t)(x)) << LDB_PM_CTRL_REG_CH0_10B_EN_SHIFT)) & LDB_PM_CTRL_REG_CH0_10B_EN_MASK)

#define LDB_PM_CTRL_REG_CH1_10B_EN_MASK         (0x800000U)
#define LDB_PM_CTRL_REG_CH1_10B_EN_SHIFT        (23U)
#define LDB_PM_CTRL_REG_CH1_10B_EN(x)           (((uint32_t)(((uint32_t)(x)) << LDB_PM_CTRL_REG_CH1_10B_EN_SHIFT)) & LDB_PM_CTRL_REG_CH1_10B_EN_MASK)

#define LDB_PM_CTRL_REG_DI0_DATA_WIDTH_MASK     (0x3000000U)
#define LDB_PM_CTRL_REG_DI0_DATA_WIDTH_SHIFT    (24U)
#define LDB_PM_CTRL_REG_DI0_DATA_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << LDB_PM_CTRL_REG_DI0_DATA_WIDTH_SHIFT)) & LDB_PM_CTRL_REG_DI0_DATA_WIDTH_MASK)

#define LDB_PM_CTRL_REG_DI1_DATA_WIDTH_MASK     (0xC000000U)
#define LDB_PM_CTRL_REG_DI1_DATA_WIDTH_SHIFT    (26U)
#define LDB_PM_CTRL_REG_DI1_DATA_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << LDB_PM_CTRL_REG_DI1_DATA_WIDTH_SHIFT)) & LDB_PM_CTRL_REG_DI1_DATA_WIDTH_MASK)

/*!
 * @}
 */ /* end of group LDB_Register_Masks */


/* LDB - Peripheral instance base addresses */
/** Peripheral LDB base address */
#define DI_LVDS_0__LDB_BASE                     (0x56240000u)
/** Peripheral LDB base pointer */
#define DI_LVDS_0__LDB                          ((LDB_Type *)DI_LVDS_0__LDB_BASE)
/** Peripheral LDB base address */
#define DI_LVDS_1__LDB_BASE                     (0x57240000u)
/** Peripheral LDB base pointer */
#define DI_LVDS_1__LDB                          ((LDB_Type *)DI_LVDS_1__LDB_BASE)
/** Array initializer of LDB peripheral base addresses */
#define LDB_BASE_ADDRS                          { DI_LVDS_0__LDB_BASE, DI_LVDS_1__LDB_BASE }
/** Array initializer of LDB peripheral base pointers */
#define LDB_BASE_PTRS                           { DI_LVDS_0__LDB, DI_LVDS_1__LDB }

/*!
 * @}
 */ /* end of group LDB_Peripheral_Access_Layer */
 

/* ----------------------------------------------------------------------------
   -- LMEM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
 * @{
 */

/** LMEM - Register Layout Typedef */
typedef struct {
  __IO uint32_t PCCCR;                             /**< Cache control register, offset: 0x0 */
  __IO uint32_t PCCLCR;                            /**< Cache line control register, offset: 0x4 */
  __IO uint32_t PCCSAR;                            /**< Cache search address register, offset: 0x8 */
  __IO uint32_t PCCCVR;                            /**< Cache read/write value register, offset: 0xC */
  __IO uint32_t PCCSRR;                            /**< Cache soft reset register, offset: 0x10 */
       uint8_t RESERVED_0[2028];
  __IO uint32_t PSCCR;                             /**< Cache control register, offset: 0x800 */
  __IO uint32_t PSCLCR;                            /**< Cache line control register, offset: 0x804 */
  __IO uint32_t PSCSAR;                            /**< Cache search address register, offset: 0x808 */
  __IO uint32_t PSCCVR;                            /**< Cache read/write value register, offset: 0x80C */
  __IO uint32_t PSCSRR;                            /**< Cache soft reset register, offset: 0x810 */
} LMEM_Type;

/* ----------------------------------------------------------------------------
   -- LMEM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LMEM_Register_Masks LMEM Register Masks
 * @{
 */

/*! @name PCCCR - Cache control register */
/*! @{ */
#define LMEM_PCCCR_ENCACHE_MASK                  (0x1U)
#define LMEM_PCCCR_ENCACHE_SHIFT                 (0U)
/*! ENCACHE - Cache enable
 *  0b0..Cache disabled
 *  0b1..Cache enabled
 */
#define LMEM_PCCCR_ENCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)
#define LMEM_PCCCR_ENWRBUF_MASK                  (0x2U)
#define LMEM_PCCCR_ENWRBUF_SHIFT                 (1U)
/*! ENWRBUF - Enable Write Buffer
 *  0b0..Write buffer disabled
 *  0b1..Write buffer enabled
 */
#define LMEM_PCCCR_ENWRBUF(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)
#define LMEM_PCCCR_PCCR2_MASK                    (0x4U)
#define LMEM_PCCCR_PCCR2_SHIFT                   (2U)
#define LMEM_PCCCR_PCCR2(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)
#define LMEM_PCCCR_PCCR3_MASK                    (0x8U)
#define LMEM_PCCCR_PCCR3_SHIFT                   (3U)
#define LMEM_PCCCR_PCCR3(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)
#define LMEM_PCCCR_INVW0_MASK                    (0x1000000U)
#define LMEM_PCCCR_INVW0_SHIFT                   (24U)
/*! INVW0 - Invalidate Way 0
 *  0b0..No operation
 *  0b1..When setting the GO bit, invalidate all lines in way 0.
 */
#define LMEM_PCCCR_INVW0(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)
#define LMEM_PCCCR_PUSHW0_MASK                   (0x2000000U)
#define LMEM_PCCCR_PUSHW0_SHIFT                  (25U)
/*! PUSHW0 - Push Way 0
 *  0b0..No operation
 *  0b1..When setting the GO bit, push all modified lines in way 0
 */
#define LMEM_PCCCR_PUSHW0(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)
#define LMEM_PCCCR_INVW1_MASK                    (0x4000000U)
#define LMEM_PCCCR_INVW1_SHIFT                   (26U)
/*! INVW1 - Invalidate Way 1
 *  0b0..No operation
 *  0b1..When setting the GO bit, invalidate all lines in way 1
 */
#define LMEM_PCCCR_INVW1(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)
#define LMEM_PCCCR_PUSHW1_MASK                   (0x8000000U)
#define LMEM_PCCCR_PUSHW1_SHIFT                  (27U)
/*! PUSHW1 - Push Way 1
 *  0b0..No operation
 *  0b1..When setting the GO bit, push all modified lines in way 1
 */
#define LMEM_PCCCR_PUSHW1(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)
#define LMEM_PCCCR_GO_MASK                       (0x80000000U)
#define LMEM_PCCCR_GO_SHIFT                      (31U)
/*! GO - Initiate Cache Command
 *  0b0..Write: no effect. Read: no cache command active.
 *  0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
 */
#define LMEM_PCCCR_GO(x)                         (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)
/*! @} */

/*! @name PCCLCR - Cache line control register */
/*! @{ */
#define LMEM_PCCLCR_LGO_MASK                     (0x1U)
#define LMEM_PCCLCR_LGO_SHIFT                    (0U)
/*! LGO - Initiate Cache Line Command
 *  0b0..Write: no effect. Read: no line command active.
 *  0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
 */
#define LMEM_PCCLCR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)
#define LMEM_PCCLCR_CACHEADDR_MASK               (0x3FFCU)
#define LMEM_PCCLCR_CACHEADDR_SHIFT              (2U)
#define LMEM_PCCLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)
#define LMEM_PCCLCR_WSEL_MASK                    (0x4000U)
#define LMEM_PCCLCR_WSEL_SHIFT                   (14U)
/*! WSEL - Way select
 *  0b0..Way 0
 *  0b1..Way 1
 */
#define LMEM_PCCLCR_WSEL(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)
#define LMEM_PCCLCR_TDSEL_MASK                   (0x10000U)
#define LMEM_PCCLCR_TDSEL_SHIFT                  (16U)
/*! TDSEL - Tag/Data Select
 *  0b0..Data
 *  0b1..Tag
 */
#define LMEM_PCCLCR_TDSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)
#define LMEM_PCCLCR_LCIVB_MASK                   (0x100000U)
#define LMEM_PCCLCR_LCIVB_SHIFT                  (20U)
#define LMEM_PCCLCR_LCIVB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)
#define LMEM_PCCLCR_LCIMB_MASK                   (0x200000U)
#define LMEM_PCCLCR_LCIMB_SHIFT                  (21U)
#define LMEM_PCCLCR_LCIMB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)
#define LMEM_PCCLCR_LCWAY_MASK                   (0x400000U)
#define LMEM_PCCLCR_LCWAY_SHIFT                  (22U)
#define LMEM_PCCLCR_LCWAY(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)
#define LMEM_PCCLCR_LCMD_MASK                    (0x3000000U)
#define LMEM_PCCLCR_LCMD_SHIFT                   (24U)
/*! LCMD - Line Command
 *  0b00..Search and read or write
 *  0b01..Invalidate
 *  0b10..Push
 *  0b11..Clear
 */
#define LMEM_PCCLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)
#define LMEM_PCCLCR_LADSEL_MASK                  (0x4000000U)
#define LMEM_PCCLCR_LADSEL_SHIFT                 (26U)
/*! LADSEL - Line Address Select
 *  0b0..Cache address
 *  0b1..Physical address
 */
#define LMEM_PCCLCR_LADSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)
#define LMEM_PCCLCR_LACC_MASK                    (0x8000000U)
#define LMEM_PCCLCR_LACC_SHIFT                   (27U)
/*! LACC - Line access type
 *  0b0..Read
 *  0b1..Write
 */
#define LMEM_PCCLCR_LACC(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)
/*! @} */

/*! @name PCCSAR - Cache search address register */
/*! @{ */
#define LMEM_PCCSAR_LGO_MASK                     (0x1U)
#define LMEM_PCCSAR_LGO_SHIFT                    (0U)
/*! LGO - Initiate Cache Line Command
 *  0b0..Write: no effect. Read: no line command active.
 *  0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
 */
#define LMEM_PCCSAR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)
#define LMEM_PCCSAR_PHYADDR_MASK                 (0xFFFFFFFEU)
#define LMEM_PCCSAR_PHYADDR_SHIFT                (1U)
#define LMEM_PCCSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
/*! @} */

/*! @name PCCCVR - Cache read/write value register */
/*! @{ */
#define LMEM_PCCCVR_DATA_MASK                    (0xFFFFFFFFU)
#define LMEM_PCCCVR_DATA_SHIFT                   (0U)
#define LMEM_PCCCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)
/*! @} */

/*! @name PCCSRR - Cache soft reset register */
/*! @{ */
#define LMEM_PCCSRR_RESET_MASK                   (0x3U)
#define LMEM_PCCSRR_RESET_SHIFT                  (0U)
#define LMEM_PCCSRR_RESET(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSRR_RESET_SHIFT)) & LMEM_PCCSRR_RESET_MASK)
/*! @} */

/*! @name PSCCR - Cache control register */
/*! @{ */
#define LMEM_PSCCR_ENCACHE_MASK                  (0x1U)
#define LMEM_PSCCR_ENCACHE_SHIFT                 (0U)
/*! ENCACHE - Cache enable
 *  0b0..Cache disabled
 *  0b1..Cache enabled
 */
#define LMEM_PSCCR_ENCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENCACHE_SHIFT)) & LMEM_PSCCR_ENCACHE_MASK)
#define LMEM_PSCCR_ENWRBUF_MASK                  (0x2U)
#define LMEM_PSCCR_ENWRBUF_SHIFT                 (1U)
/*! ENWRBUF - Enable Write Buffer
 *  0b0..Write buffer disabled
 *  0b1..Write buffer enabled
 */
#define LMEM_PSCCR_ENWRBUF(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENWRBUF_SHIFT)) & LMEM_PSCCR_ENWRBUF_MASK)
#define LMEM_PSCCR_INVW0_MASK                    (0x1000000U)
#define LMEM_PSCCR_INVW0_SHIFT                   (24U)
/*! INVW0 - Invalidate Way 0
 *  0b0..No operation
 *  0b1..When setting the GO bit, invalidate all lines in way 0.
 */
#define LMEM_PSCCR_INVW0(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW0_SHIFT)) & LMEM_PSCCR_INVW0_MASK)
#define LMEM_PSCCR_PUSHW0_MASK                   (0x2000000U)
#define LMEM_PSCCR_PUSHW0_SHIFT                  (25U)
/*! PUSHW0 - Push Way 0
 *  0b0..No operation
 *  0b1..When setting the GO bit, push all modified lines in way 0
 */
#define LMEM_PSCCR_PUSHW0(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW0_SHIFT)) & LMEM_PSCCR_PUSHW0_MASK)
#define LMEM_PSCCR_INVW1_MASK                    (0x4000000U)
#define LMEM_PSCCR_INVW1_SHIFT                   (26U)
/*! INVW1 - Invalidate Way 1
 *  0b0..No operation
 *  0b1..When setting the GO bit, invalidate all lines in way 1
 */
#define LMEM_PSCCR_INVW1(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW1_SHIFT)) & LMEM_PSCCR_INVW1_MASK)
#define LMEM_PSCCR_PUSHW1_MASK                   (0x8000000U)
#define LMEM_PSCCR_PUSHW1_SHIFT                  (27U)
/*! PUSHW1 - Push Way 1
 *  0b0..No operation
 *  0b1..When setting the GO bit, push all modified lines in way 1
 */
#define LMEM_PSCCR_PUSHW1(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW1_SHIFT)) & LMEM_PSCCR_PUSHW1_MASK)
#define LMEM_PSCCR_GO_MASK                       (0x80000000U)
#define LMEM_PSCCR_GO_SHIFT                      (31U)
/*! GO - Initiate Cache Command
 *  0b0..Write: no effect. Read: no cache command active.
 *  0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
 */
#define LMEM_PSCCR_GO(x)                         (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_GO_SHIFT)) & LMEM_PSCCR_GO_MASK)
/*! @} */

/*! @name PSCLCR - Cache line control register */
/*! @{ */
#define LMEM_PSCLCR_LGO_MASK                     (0x1U)
#define LMEM_PSCLCR_LGO_SHIFT                    (0U)
/*! LGO - Initiate Cache Line Command
 *  0b0..Write: no effect. Read: no line command active.
 *  0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
 */
#define LMEM_PSCLCR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LGO_SHIFT)) & LMEM_PSCLCR_LGO_MASK)
#define LMEM_PSCLCR_CACHEADDR_MASK               (0x3FFCU)
#define LMEM_PSCLCR_CACHEADDR_SHIFT              (2U)
#define LMEM_PSCLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_CACHEADDR_SHIFT)) & LMEM_PSCLCR_CACHEADDR_MASK)
#define LMEM_PSCLCR_WSEL_MASK                    (0x4000U)
#define LMEM_PSCLCR_WSEL_SHIFT                   (14U)
/*! WSEL - Way select
 *  0b0..Way 0
 *  0b1..Way 1
 */
#define LMEM_PSCLCR_WSEL(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_WSEL_SHIFT)) & LMEM_PSCLCR_WSEL_MASK)
#define LMEM_PSCLCR_TDSEL_MASK                   (0x10000U)
#define LMEM_PSCLCR_TDSEL_SHIFT                  (16U)
/*! TDSEL - Tag/Data Select
 *  0b0..Data
 *  0b1..Tag
 */
#define LMEM_PSCLCR_TDSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_TDSEL_SHIFT)) & LMEM_PSCLCR_TDSEL_MASK)
#define LMEM_PSCLCR_LCIVB_MASK                   (0x100000U)
#define LMEM_PSCLCR_LCIVB_SHIFT                  (20U)
#define LMEM_PSCLCR_LCIVB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIVB_SHIFT)) & LMEM_PSCLCR_LCIVB_MASK)
#define LMEM_PSCLCR_LCIMB_MASK                   (0x200000U)
#define LMEM_PSCLCR_LCIMB_SHIFT                  (21U)
#define LMEM_PSCLCR_LCIMB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIMB_SHIFT)) & LMEM_PSCLCR_LCIMB_MASK)
#define LMEM_PSCLCR_LCWAY_MASK                   (0x400000U)
#define LMEM_PSCLCR_LCWAY_SHIFT                  (22U)
#define LMEM_PSCLCR_LCWAY(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCWAY_SHIFT)) & LMEM_PSCLCR_LCWAY_MASK)
#define LMEM_PSCLCR_LCMD_MASK                    (0x3000000U)
#define LMEM_PSCLCR_LCMD_SHIFT                   (24U)
/*! LCMD - Line Command
 *  0b00..Search and read or write
 *  0b01..Invalidate
 *  0b10..Push
 *  0b11..Clear
 */
#define LMEM_PSCLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCMD_SHIFT)) & LMEM_PSCLCR_LCMD_MASK)
#define LMEM_PSCLCR_LADSEL_MASK                  (0x4000000U)
#define LMEM_PSCLCR_LADSEL_SHIFT                 (26U)
/*! LADSEL - Line Address Select
 *  0b0..Cache address
 *  0b1..Physical address
 */
#define LMEM_PSCLCR_LADSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LADSEL_SHIFT)) & LMEM_PSCLCR_LADSEL_MASK)
#define LMEM_PSCLCR_LACC_MASK                    (0x8000000U)
#define LMEM_PSCLCR_LACC_SHIFT                   (27U)
/*! LACC - Line access type
 *  0b0..Read
 *  0b1..Write
 */
#define LMEM_PSCLCR_LACC(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LACC_SHIFT)) & LMEM_PSCLCR_LACC_MASK)
/*! @} */

/*! @name PSCSAR - Cache search address register */
/*! @{ */
#define LMEM_PSCSAR_LGO_MASK                     (0x1U)
#define LMEM_PSCSAR_LGO_SHIFT                    (0U)
/*! LGO - Initiate Cache Line Command
 *  0b0..Write: no effect. Read: no line command active.
 *  0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
 */
#define LMEM_PSCSAR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_LGO_SHIFT)) & LMEM_PSCSAR_LGO_MASK)
#define LMEM_PSCSAR_PHYADDR_MASK                 (0xFFFFFFFEU)
#define LMEM_PSCSAR_PHYADDR_SHIFT                (1U)
#define LMEM_PSCSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_PHYADDR_SHIFT)) & LMEM_PSCSAR_PHYADDR_MASK)
/*! @} */

/*! @name PSCCVR - Cache read/write value register */
/*! @{ */
#define LMEM_PSCCVR_DATA_MASK                    (0xFFFFFFFFU)
#define LMEM_PSCCVR_DATA_SHIFT                   (0U)
#define LMEM_PSCCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCVR_DATA_SHIFT)) & LMEM_PSCCVR_DATA_MASK)
/*! @} */

/*! @name PSCSRR - Cache soft reset register */
/*! @{ */
#define LMEM_PSCSRR_RESET_MASK                   (0x3U)
#define LMEM_PSCSRR_RESET_SHIFT                  (0U)
#define LMEM_PSCSRR_RESET(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSRR_RESET_SHIFT)) & LMEM_PSCSRR_RESET_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LMEM_Register_Masks */


/* LMEM - Peripheral instance base addresses */
/** Peripheral LMEM base address */
#define LMEM_BASE                                (0xE0082000u)
/** Peripheral LMEM base pointer */
#define LMEM                                     ((LMEM_Type *)LMEM_BASE)
/** Array initializer of LMEM peripheral base addresses */
#define LMEM_BASE_ADDRS                          { LMEM_BASE }
/** Array initializer of LMEM peripheral base pointers */
#define LMEM_BASE_PTRS                           { LMEM }

/*!
 * @}
 */ /* end of group LMEM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPC_Peripheral_Access_Layer LPC Peripheral Access Layer
 * @{
 */

/** LPC - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPC_PC[7];                         /**< LPC Power Control Register N, array offset: 0x0, array step: 0x4 */
  __IO uint32_t LPC_CR;                            /**< LPC Configuration Register, offset: 0x1C */
  __IO uint32_t LPC_ED[7];                         /**< LPC Entry Delay Stage N, array offset: 0x20, array step: 0x4 */
       uint8_t RESERVED_0[4];
  __IO uint32_t LPC_XD[6];                         /**< LPC Exit Delay Stage N, array offset: 0x40, array step: 0x4 */
  __IO uint32_t LPC_XD6;                           /**< LPC Exit Delay Stage 6, offset: 0x58 */
} LPC_Type;

/* ----------------------------------------------------------------------------
   -- LPC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPC_Register_Masks LPC Register Masks
 * @{
 */

/*! @name LPC_PC - LPC Power Control Register N */
/*! @{ */
#define LPC_LPC_PC_PC_MASK                       (0xFFFFFFU)
#define LPC_LPC_PC_PC_SHIFT                      (0U)
#define LPC_LPC_PC_PC(x)                         (((uint32_t)(((uint32_t)(x)) << LPC_LPC_PC_PC_SHIFT)) & LPC_LPC_PC_PC_MASK)
/*! @} */

/* The count of LPC_LPC_PC */
#define LPC_LPC_PC_COUNT                         (7U)

/*! @name LPC_CR - LPC Configuration Register */
/*! @{ */
#define LPC_LPC_CR_ROSCDIS_MASK                  (0x1U)
#define LPC_LPC_CR_ROSCDIS_SHIFT                 (0U)
/*! ROSCDIS - ROSC Disable
 *  0b0..ROSC enabled during low power mode.
 *  0b1..ROSC disabled during low power mode.
 */
#define LPC_LPC_CR_ROSCDIS(x)                    (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_ROSCDIS_SHIFT)) & LPC_LPC_CR_ROSCDIS_MASK)
#define LPC_LPC_CR_PMICSTDBY_MASK                (0x2U)
#define LPC_LPC_CR_PMICSTDBY_SHIFT               (1U)
/*! PMICSTDBY - PMIC Standby
 *  0b0..PMIC standby request deasserted during low power mode.
 *  0b1..PMIC standby request asserted during low power mode.
 */
#define LPC_LPC_CR_PMICSTDBY(x)                  (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_PMICSTDBY_SHIFT)) & LPC_LPC_CR_PMICSTDBY_MASK)
#define LPC_LPC_CR_PCSEL_MASK                    (0x4U)
#define LPC_LPC_CR_PCSEL_SHIFT                   (2U)
/*! PCSEL - LPC/DSC Power Control Select
 *  0b0..Power controls driven by DSC.
 *  0b1..Power controls driven by LPC.
 */
#define LPC_LPC_CR_PCSEL(x)                      (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_PCSEL_SHIFT)) & LPC_LPC_CR_PCSEL_MASK)
#define LPC_LPC_CR_CLKSEL_MASK                   (0x30U)
#define LPC_LPC_CR_CLKSEL_SHIFT                  (4U)
/*! CLKSEL - LPC Clock Select
 *  0b00..25MHz clock selected
 *  0b01..1MHz clock selected
 *  0b10..32kHz clock selected
 *  0b11..Reserved
 */
#define LPC_LPC_CR_CLKSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_CLKSEL_SHIFT)) & LPC_LPC_CR_CLKSEL_MASK)
#define LPC_LPC_CR_CLKS_MASK                     (0x40U)
#define LPC_LPC_CR_CLKS_SHIFT                    (6U)
/*! CLKS - LPC Clock Status
 *  0b0..LPC Clock is not gated.
 *  0b1..LPC Clock is gated.
 */
#define LPC_LPC_CR_CLKS(x)                       (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_CLKS_SHIFT)) & LPC_LPC_CR_CLKS_MASK)
#define LPC_LPC_CR_CLKG_MASK                     (0x80U)
#define LPC_LPC_CR_CLKG_SHIFT                    (7U)
/*! CLKG - LPC Clock Gate
 *  0b0..LPC Clock gate not requested.
 *  0b1..LPC Clock gate requested.
 */
#define LPC_LPC_CR_CLKG(x)                       (((uint32_t)(((uint32_t)(x)) << LPC_LPC_CR_CLKG_SHIFT)) & LPC_LPC_CR_CLKG_MASK)
/*! @} */

/*! @name LPC_ED - LPC Entry Delay Stage N */
/*! @{ */
#define LPC_LPC_ED_ED_MASK                       (0x1FU)
#define LPC_LPC_ED_ED_SHIFT                      (0U)
#define LPC_LPC_ED_ED(x)                         (((uint32_t)(((uint32_t)(x)) << LPC_LPC_ED_ED_SHIFT)) & LPC_LPC_ED_ED_MASK)
/*! @} */

/* The count of LPC_LPC_ED */
#define LPC_LPC_ED_COUNT                         (7U)

/*! @name LPC_XD - LPC Exit Delay Stage N */
/*! @{ */
#define LPC_LPC_XD_XD_MASK                       (0x1FU)
#define LPC_LPC_XD_XD_SHIFT                      (0U)
#define LPC_LPC_XD_XD(x)                         (((uint32_t)(((uint32_t)(x)) << LPC_LPC_XD_XD_SHIFT)) & LPC_LPC_XD_XD_MASK)
/*! @} */

/* The count of LPC_LPC_XD */
#define LPC_LPC_XD_COUNT                         (6U)

/*! @name LPC_XD6 - LPC Exit Delay Stage 6 */
/*! @{ */
#define LPC_LPC_XD6_XD_MASK                      (0xFFFFU)
#define LPC_LPC_XD6_XD_SHIFT                     (0U)
#define LPC_LPC_XD6_XD(x)                        (((uint32_t)(((uint32_t)(x)) << LPC_LPC_XD6_XD_SHIFT)) & LPC_LPC_XD6_XD_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LPC_Register_Masks */


/* LPC - Peripheral instance base addresses */
/** Peripheral SCU__LPC base address */
#define SCU__LPC_BASE                            (0x32070000u)
/** Peripheral SCU__LPC base pointer */
#define SCU__LPC                                 ((LPC_Type *)SCU__LPC_BASE)
/** Array initializer of LPC peripheral base addresses */
#define LPC_BASE_ADDRS                           { SCU__LPC_BASE }
/** Array initializer of LPC peripheral base pointers */
#define LPC_BASE_PTRS                            { SCU__LPC }

/*!
 * @}
 */ /* end of group LPC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPI2C Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
 * @{
 */

/** LPI2C - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t MCR;                               /**< Master Control Register, offset: 0x10 */
  __IO uint32_t MSR;                               /**< Master Status Register, offset: 0x14 */
  __IO uint32_t MIER;                              /**< Master Interrupt Enable Register, offset: 0x18 */
  __IO uint32_t MDER;                              /**< Master DMA Enable Register, offset: 0x1C */
  __IO uint32_t MCFGR0;                            /**< Master Configuration Register 0, offset: 0x20 */
  __IO uint32_t MCFGR1;                            /**< Master Configuration Register 1, offset: 0x24 */
  __IO uint32_t MCFGR2;                            /**< Master Configuration Register 2, offset: 0x28 */
  __IO uint32_t MCFGR3;                            /**< Master Configuration Register 3, offset: 0x2C */
       uint8_t RESERVED_1[16];
  __IO uint32_t MDMR;                              /**< Master Data Match Register, offset: 0x40 */
       uint8_t RESERVED_2[4];
  __IO uint32_t MCCR0;                             /**< Master Clock Configuration Register 0, offset: 0x48 */
       uint8_t RESERVED_3[4];
  __IO uint32_t MCCR1;                             /**< Master Clock Configuration Register 1, offset: 0x50 */
       uint8_t RESERVED_4[4];
  __IO uint32_t MFCR;                              /**< Master FIFO Control Register, offset: 0x58 */
  __I  uint32_t MFSR;                              /**< Master FIFO Status Register, offset: 0x5C */
  __O  uint32_t MTDR;                              /**< Master Transmit Data Register, offset: 0x60 */
       uint8_t RESERVED_5[12];
  __I  uint32_t MRDR;                              /**< Master Receive Data Register, offset: 0x70 */
       uint8_t RESERVED_6[156];
  __IO uint32_t SCR;                               /**< Slave Control Register, offset: 0x110 */
  __IO uint32_t SSR;                               /**< Slave Status Register, offset: 0x114 */
  __IO uint32_t SIER;                              /**< Slave Interrupt Enable Register, offset: 0x118 */
  __IO uint32_t SDER;                              /**< Slave DMA Enable Register, offset: 0x11C */
       uint8_t RESERVED_7[4];
  __IO uint32_t SCFGR1;                            /**< Slave Configuration Register 1, offset: 0x124 */
  __IO uint32_t SCFGR2;                            /**< Slave Configuration Register 2, offset: 0x128 */
       uint8_t RESERVED_8[20];
  __IO uint32_t SAMR;                              /**< Slave Address Match Register, offset: 0x140 */
       uint8_t RESERVED_9[12];
  __I  uint32_t SASR;                              /**< Slave Address Status Register, offset: 0x150 */
  __IO uint32_t STAR;                              /**< Slave Transmit ACK Register, offset: 0x154 */
       uint8_t RESERVED_10[8];
  __O  uint32_t STDR;                              /**< Slave Transmit Data Register, offset: 0x160 */
       uint8_t RESERVED_11[12];
  __I  uint32_t SRDR;                              /**< Slave Receive Data Register, offset: 0x170 */
} LPI2C_Type;

/* ----------------------------------------------------------------------------
   -- LPI2C Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */
#define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
#define LPI2C_VERID_FEATURE_SHIFT                (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000010..Master only, with standard feature set
 *  0b0000000000000011..Master and slave, with standard feature set
 */
#define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
#define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
#define LPI2C_VERID_MINOR_SHIFT                  (16U)
#define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
#define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
#define LPI2C_VERID_MAJOR_SHIFT                  (24U)
#define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */
#define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
#define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
#define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
#define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
#define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
#define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
/*! @} */

/*! @name MCR - Master Control Register */
/*! @{ */
#define LPI2C_MCR_MEN_MASK                       (0x1U)
#define LPI2C_MCR_MEN_SHIFT                      (0U)
/*! MEN - Master Enable
 *  0b0..Master logic is disabled
 *  0b1..Master logic is enabled
 */
#define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
#define LPI2C_MCR_RST_MASK                       (0x2U)
#define LPI2C_MCR_RST_SHIFT                      (1U)
/*! RST - Software Reset
 *  0b0..Master logic is not reset
 *  0b1..Master logic is reset
 */
#define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
#define LPI2C_MCR_DOZEN_MASK                     (0x4U)
#define LPI2C_MCR_DOZEN_SHIFT                    (2U)
/*! DOZEN - Doze mode enable
 *  0b0..Master is enabled in Doze mode
 *  0b1..Master is disabled in Doze mode
 */
#define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
#define LPI2C_MCR_DBGEN_MASK                     (0x8U)
#define LPI2C_MCR_DBGEN_SHIFT                    (3U)
/*! DBGEN - Debug Enable
 *  0b0..Master is disabled in debug mode
 *  0b1..Master is enabled in debug mode
 */
#define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
#define LPI2C_MCR_RTF_MASK                       (0x100U)
#define LPI2C_MCR_RTF_SHIFT                      (8U)
/*! RTF - Reset Transmit FIFO
 *  0b0..No effect
 *  0b1..Transmit FIFO is reset
 */
#define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
#define LPI2C_MCR_RRF_MASK                       (0x200U)
#define LPI2C_MCR_RRF_SHIFT                      (9U)
/*! RRF - Reset Receive FIFO
 *  0b0..No effect
 *  0b1..Receive FIFO is reset
 */
#define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
/*! @} */

/*! @name MSR - Master Status Register */
/*! @{ */
#define LPI2C_MSR_TDF_MASK                       (0x1U)
#define LPI2C_MSR_TDF_SHIFT                      (0U)
/*! TDF - Transmit Data Flag
 *  0b0..Transmit data is not requested
 *  0b1..Transmit data is requested
 */
#define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
#define LPI2C_MSR_RDF_MASK                       (0x2U)
#define LPI2C_MSR_RDF_SHIFT                      (1U)
/*! RDF - Receive Data Flag
 *  0b0..Receive Data is not ready
 *  0b1..Receive data is ready
 */
#define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
#define LPI2C_MSR_EPF_MASK                       (0x100U)
#define LPI2C_MSR_EPF_SHIFT                      (8U)
/*! EPF - End Packet Flag
 *  0b0..Master has not generated a STOP or Repeated START condition
 *  0b1..Master has generated a STOP or Repeated START condition
 */
#define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
#define LPI2C_MSR_SDF_MASK                       (0x200U)
#define LPI2C_MSR_SDF_SHIFT                      (9U)
/*! SDF - STOP Detect Flag
 *  0b0..Master has not generated a STOP condition
 *  0b1..Master has generated a STOP condition
 */
#define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
#define LPI2C_MSR_NDF_MASK                       (0x400U)
#define LPI2C_MSR_NDF_SHIFT                      (10U)
/*! NDF - NACK Detect Flag
 *  0b0..Unexpected NACK was not detected
 *  0b1..Unexpected NACK was detected
 */
#define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
#define LPI2C_MSR_ALF_MASK                       (0x800U)
#define LPI2C_MSR_ALF_SHIFT                      (11U)
/*! ALF - Arbitration Lost Flag
 *  0b0..Master has not lost arbitration
 *  0b1..Master has lost arbitration
 */
#define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
#define LPI2C_MSR_FEF_MASK                       (0x1000U)
#define LPI2C_MSR_FEF_SHIFT                      (12U)
/*! FEF - FIFO Error Flag
 *  0b0..No error
 *  0b1..Master sending or receiving data without a START condition
 */
#define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
#define LPI2C_MSR_PLTF_MASK                      (0x2000U)
#define LPI2C_MSR_PLTF_SHIFT                     (13U)
/*! PLTF - Pin Low Timeout Flag
 *  0b0..Pin low timeout has not occurred or is disabled
 *  0b1..Pin low timeout has occurred
 */
#define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
#define LPI2C_MSR_DMF_MASK                       (0x4000U)
#define LPI2C_MSR_DMF_SHIFT                      (14U)
/*! DMF - Data Match Flag
 *  0b0..Have not received matching data
 *  0b1..Have received matching data
 */
#define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
#define LPI2C_MSR_MBF_MASK                       (0x1000000U)
#define LPI2C_MSR_MBF_SHIFT                      (24U)
/*! MBF - Master Busy Flag
 *  0b0..I2C Master is idle
 *  0b1..I2C Master is busy
 */
#define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
#define LPI2C_MSR_BBF_MASK                       (0x2000000U)
#define LPI2C_MSR_BBF_SHIFT                      (25U)
/*! BBF - Bus Busy Flag
 *  0b0..I2C Bus is idle
 *  0b1..I2C Bus is busy
 */
#define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
/*! @} */

/*! @name MIER - Master Interrupt Enable Register */
/*! @{ */
#define LPI2C_MIER_TDIE_MASK                     (0x1U)
#define LPI2C_MIER_TDIE_SHIFT                    (0U)
/*! TDIE - Transmit Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
#define LPI2C_MIER_RDIE_MASK                     (0x2U)
#define LPI2C_MIER_RDIE_SHIFT                    (1U)
/*! RDIE - Receive Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
#define LPI2C_MIER_EPIE_MASK                     (0x100U)
#define LPI2C_MIER_EPIE_SHIFT                    (8U)
/*! EPIE - End Packet Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
#define LPI2C_MIER_SDIE_MASK                     (0x200U)
#define LPI2C_MIER_SDIE_SHIFT                    (9U)
/*! SDIE - STOP Detect Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
#define LPI2C_MIER_NDIE_MASK                     (0x400U)
#define LPI2C_MIER_NDIE_SHIFT                    (10U)
/*! NDIE - NACK Detect Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
#define LPI2C_MIER_ALIE_MASK                     (0x800U)
#define LPI2C_MIER_ALIE_SHIFT                    (11U)
/*! ALIE - Arbitration Lost Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
#define LPI2C_MIER_FEIE_MASK                     (0x1000U)
#define LPI2C_MIER_FEIE_SHIFT                    (12U)
/*! FEIE - FIFO Error Interrupt Enable
 *  0b0..Enabled
 *  0b1..Disabled
 */
#define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
#define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
#define LPI2C_MIER_PLTIE_SHIFT                   (13U)
/*! PLTIE - Pin Low Timeout Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
#define LPI2C_MIER_DMIE_MASK                     (0x4000U)
#define LPI2C_MIER_DMIE_SHIFT                    (14U)
/*! DMIE - Data Match Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
/*! @} */

/*! @name MDER - Master DMA Enable Register */
/*! @{ */
#define LPI2C_MDER_TDDE_MASK                     (0x1U)
#define LPI2C_MDER_TDDE_SHIFT                    (0U)
/*! TDDE - Transmit Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
#define LPI2C_MDER_RDDE_MASK                     (0x2U)
#define LPI2C_MDER_RDDE_SHIFT                    (1U)
/*! RDDE - Receive Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
/*! @} */

/*! @name MCFGR0 - Master Configuration Register 0 */
/*! @{ */
#define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
#define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
/*! HREN - Host Request Enable
 *  0b0..Host request input is disabled
 *  0b1..Host request input is enabled
 */
#define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
#define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
#define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
/*! HRPOL - Host Request Polarity
 *  0b0..Active low
 *  0b1..Active high
 */
#define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
#define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
#define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
/*! HRSEL - Host Request Select
 *  0b0..Host request input is pin HREQ
 *  0b1..Host request input is input trigger
 */
#define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
#define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
#define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
/*! CIRFIFO - Circular FIFO Enable
 *  0b0..Circular FIFO is disabled
 *  0b1..Circular FIFO is enabled
 */
#define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
#define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
#define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
/*! RDMO - Receive Data Match Only
 *  0b0..Received data is stored in the receive FIFO
 *  0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set
 */
#define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
/*! @} */

/*! @name MCFGR1 - Master Configuration Register 1 */
/*! @{ */
#define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
#define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
/*! PRESCALE - Prescaler
 *  0b000..Divide by 1
 *  0b001..Divide by 2
 *  0b010..Divide by 4
 *  0b011..Divide by 8
 *  0b100..Divide by 16
 *  0b101..Divide by 32
 *  0b110..Divide by 64
 *  0b111..Divide by 128
 */
#define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
#define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
#define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
/*! AUTOSTOP - Automatic STOP Generation
 *  0b0..No effect
 *  0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
 */
#define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
#define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
#define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
/*! IGNACK - IGNACK
 *  0b0..LPI2C Master will receive ACK and NACK normally
 *  0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK
 */
#define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
#define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
#define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
/*! TIMECFG - Timeout Configuration
 *  0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout
 *  0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout
 */
#define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
#define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
#define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
/*! MATCFG - Match Configuration
 *  0b000..Match is disabled
 *  0b001..Reserved
 *  0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1)
 *  0b011..Match is enabled (any data word equals MATCH0 OR MATCH1)
 *  0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)
 *  0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1)
 *  0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)
 *  0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)
 */
#define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
#define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
#define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
/*! PINCFG - Pin Configuration
 *  0b000..2-pin open drain mode
 *  0b001..2-pin output only mode (ultra-fast mode)
 *  0b010..2-pin push-pull mode
 *  0b011..4-pin push-pull mode
 *  0b100..2-pin open drain mode with separate LPI2C slave
 *  0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave
 *  0b110..2-pin push-pull mode with separate LPI2C slave
 *  0b111..4-pin push-pull mode (inverted outputs)
 */
#define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
/*! @} */

/*! @name MCFGR2 - Master Configuration Register 2 */
/*! @{ */
#define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
#define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
#define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
#define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
#define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
#define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
#define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
#define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
#define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
/*! @} */

/*! @name MCFGR3 - Master Configuration Register 3 */
/*! @{ */
#define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
#define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
#define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
/*! @} */

/*! @name MDMR - Master Data Match Register */
/*! @{ */
#define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
#define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
#define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
#define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
#define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
#define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
/*! @} */

/*! @name MCCR0 - Master Clock Configuration Register 0 */
/*! @{ */
#define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
#define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
#define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
#define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
#define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
#define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
#define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
#define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
#define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
#define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
#define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
#define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
/*! @} */

/*! @name MCCR1 - Master Clock Configuration Register 1 */
/*! @{ */
#define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
#define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
#define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
#define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
#define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
#define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
#define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
#define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
#define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
#define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
#define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
#define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
/*! @} */

/*! @name MFCR - Master FIFO Control Register */
/*! @{ */
#define LPI2C_MFCR_TXWATER_MASK                  (0xFU)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
#define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
#define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
#define LPI2C_MFCR_RXWATER_MASK                  (0xF0000U)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
#define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
#define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)  /* Merged from fields with different position or width, of widths (2, 4), largest definition used */
/*! @} */

/*! @name MFSR - Master FIFO Status Register */
/*! @{ */
#define LPI2C_MFSR_TXCOUNT_MASK                  (0x1FU)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
#define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define LPI2C_MFSR_RXCOUNT_MASK                  (0x1F0000U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
#define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
/*! @} */

/*! @name MTDR - Master Transmit Data Register */
/*! @{ */
#define LPI2C_MTDR_DATA_MASK                     (0xFFU)
#define LPI2C_MTDR_DATA_SHIFT                    (0U)
#define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
#define LPI2C_MTDR_CMD_MASK                      (0x700U)
#define LPI2C_MTDR_CMD_SHIFT                     (8U)
/*! CMD - Command Data
 *  0b000..Transmit DATA[7:0]
 *  0b001..Receive (DATA[7:0] + 1) bytes
 *  0b010..Generate STOP condition
 *  0b011..Receive and discard (DATA[7:0] + 1) bytes
 *  0b100..Generate (repeated) START and transmit address in DATA[7:0]
 *  0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
 *  0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
 *  0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
 */
#define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
/*! @} */

/*! @name MRDR - Master Receive Data Register */
/*! @{ */
#define LPI2C_MRDR_DATA_MASK                     (0xFFU)
#define LPI2C_MRDR_DATA_SHIFT                    (0U)
#define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
#define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
#define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
/*! RXEMPTY - RX Empty
 *  0b0..Receive FIFO is not empty
 *  0b1..Receive FIFO is empty
 */
#define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
/*! @} */

/*! @name SCR - Slave Control Register */
/*! @{ */
#define LPI2C_SCR_SEN_MASK                       (0x1U)
#define LPI2C_SCR_SEN_SHIFT                      (0U)
/*! SEN - Slave Enable
 *  0b0..I2C Slave mode is disabled
 *  0b1..I2C Slave mode is enabled
 */
#define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
#define LPI2C_SCR_RST_MASK                       (0x2U)
#define LPI2C_SCR_RST_SHIFT                      (1U)
/*! RST - Software Reset
 *  0b0..Slave mode logic is not reset
 *  0b1..Slave mode logic is reset
 */
#define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
#define LPI2C_SCR_FILTEN_MASK                    (0x10U)
#define LPI2C_SCR_FILTEN_SHIFT                   (4U)
/*! FILTEN - Filter Enable
 *  0b0..Disable digital filter and output delay counter for slave mode
 *  0b1..Enable digital filter and output delay counter for slave mode
 */
#define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
#define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
#define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
/*! FILTDZ - Filter Doze Enable
 *  0b0..Filter remains enabled in Doze mode
 *  0b1..Filter is disabled in Doze mode
 */
#define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
#define LPI2C_SCR_RTF_MASK                       (0x100U)
#define LPI2C_SCR_RTF_SHIFT                      (8U)
/*! RTF - Reset Transmit FIFO
 *  0b0..No effect
 *  0b1..Transmit Data Register is now empty
 */
#define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
#define LPI2C_SCR_RRF_MASK                       (0x200U)
#define LPI2C_SCR_RRF_SHIFT                      (9U)
/*! RRF - Reset Receive FIFO
 *  0b0..No effect
 *  0b1..Receive Data Register is now empty
 */
#define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
/*! @} */

/*! @name SSR - Slave Status Register */
/*! @{ */
#define LPI2C_SSR_TDF_MASK                       (0x1U)
#define LPI2C_SSR_TDF_SHIFT                      (0U)
/*! TDF - Transmit Data Flag
 *  0b0..Transmit data not requested
 *  0b1..Transmit data is requested
 */
#define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
#define LPI2C_SSR_RDF_MASK                       (0x2U)
#define LPI2C_SSR_RDF_SHIFT                      (1U)
/*! RDF - Receive Data Flag
 *  0b0..Receive data is not ready
 *  0b1..Receive data is ready
 */
#define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
#define LPI2C_SSR_AVF_MASK                       (0x4U)
#define LPI2C_SSR_AVF_SHIFT                      (2U)
/*! AVF - Address Valid Flag
 *  0b0..Address Status Register is not valid
 *  0b1..Address Status Register is valid
 */
#define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
#define LPI2C_SSR_TAF_MASK                       (0x8U)
#define LPI2C_SSR_TAF_SHIFT                      (3U)
/*! TAF - Transmit ACK Flag
 *  0b0..Transmit ACK/NACK is not required
 *  0b1..Transmit ACK/NACK is required
 */
#define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
#define LPI2C_SSR_RSF_MASK                       (0x100U)
#define LPI2C_SSR_RSF_SHIFT                      (8U)
/*! RSF - Repeated Start Flag
 *  0b0..Slave has not detected a Repeated START condition
 *  0b1..Slave has detected a Repeated START condition
 */
#define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
#define LPI2C_SSR_SDF_MASK                       (0x200U)
#define LPI2C_SSR_SDF_SHIFT                      (9U)
/*! SDF - STOP Detect Flag
 *  0b0..Slave has not detected a STOP condition
 *  0b1..Slave has detected a STOP condition
 */
#define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
#define LPI2C_SSR_BEF_MASK                       (0x400U)
#define LPI2C_SSR_BEF_SHIFT                      (10U)
/*! BEF - Bit Error Flag
 *  0b0..Slave has not detected a bit error
 *  0b1..Slave has detected a bit error
 */
#define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
#define LPI2C_SSR_FEF_MASK                       (0x800U)
#define LPI2C_SSR_FEF_SHIFT                      (11U)
/*! FEF - FIFO Error Flag
 *  0b0..FIFO underflow or overflow was not detected
 *  0b1..FIFO underflow or overflow was detected
 */
#define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
#define LPI2C_SSR_AM0F_MASK                      (0x1000U)
#define LPI2C_SSR_AM0F_SHIFT                     (12U)
/*! AM0F - Address Match 0 Flag
 *  0b0..Have not received an ADDR0 matching address
 *  0b1..Have received an ADDR0 matching address
 */
#define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
#define LPI2C_SSR_AM1F_MASK                      (0x2000U)
#define LPI2C_SSR_AM1F_SHIFT                     (13U)
/*! AM1F - Address Match 1 Flag
 *  0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address
 *  0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address
 */
#define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
#define LPI2C_SSR_GCF_MASK                       (0x4000U)
#define LPI2C_SSR_GCF_SHIFT                      (14U)
/*! GCF - General Call Flag
 *  0b0..Slave has not detected the General Call Address or the General Call Address is disabled
 *  0b1..Slave has detected the General Call Address
 */
#define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
#define LPI2C_SSR_SARF_MASK                      (0x8000U)
#define LPI2C_SSR_SARF_SHIFT                     (15U)
/*! SARF - SMBus Alert Response Flag
 *  0b0..SMBus Alert Response is disabled or not detected
 *  0b1..SMBus Alert Response is enabled and detected
 */
#define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
#define LPI2C_SSR_SBF_MASK                       (0x1000000U)
#define LPI2C_SSR_SBF_SHIFT                      (24U)
/*! SBF - Slave Busy Flag
 *  0b0..I2C Slave is idle
 *  0b1..I2C Slave is busy
 */
#define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
#define LPI2C_SSR_BBF_MASK                       (0x2000000U)
#define LPI2C_SSR_BBF_SHIFT                      (25U)
/*! BBF - Bus Busy Flag
 *  0b0..I2C Bus is idle
 *  0b1..I2C Bus is busy
 */
#define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
/*! @} */

/*! @name SIER - Slave Interrupt Enable Register */
/*! @{ */
#define LPI2C_SIER_TDIE_MASK                     (0x1U)
#define LPI2C_SIER_TDIE_SHIFT                    (0U)
/*! TDIE - Transmit Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
#define LPI2C_SIER_RDIE_MASK                     (0x2U)
#define LPI2C_SIER_RDIE_SHIFT                    (1U)
/*! RDIE - Receive Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
#define LPI2C_SIER_AVIE_MASK                     (0x4U)
#define LPI2C_SIER_AVIE_SHIFT                    (2U)
/*! AVIE - Address Valid Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
#define LPI2C_SIER_TAIE_MASK                     (0x8U)
#define LPI2C_SIER_TAIE_SHIFT                    (3U)
/*! TAIE - Transmit ACK Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
#define LPI2C_SIER_RSIE_MASK                     (0x100U)
#define LPI2C_SIER_RSIE_SHIFT                    (8U)
/*! RSIE - Repeated Start Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
#define LPI2C_SIER_SDIE_MASK                     (0x200U)
#define LPI2C_SIER_SDIE_SHIFT                    (9U)
/*! SDIE - STOP Detect Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
#define LPI2C_SIER_BEIE_MASK                     (0x400U)
#define LPI2C_SIER_BEIE_SHIFT                    (10U)
/*! BEIE - Bit Error Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
#define LPI2C_SIER_FEIE_MASK                     (0x800U)
#define LPI2C_SIER_FEIE_SHIFT                    (11U)
/*! FEIE - FIFO Error Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
#define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
#define LPI2C_SIER_AM0IE_SHIFT                   (12U)
/*! AM0IE - Address Match 0 Interrupt Enable
 *  0b0..Enabled
 *  0b1..Disabled
 */
#define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
#define LPI2C_SIER_AM1F_MASK                     (0x2000U)
#define LPI2C_SIER_AM1F_SHIFT                    (13U)
/*! AM1F - Address Match 1 Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_AM1F(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
#define LPI2C_SIER_GCIE_MASK                     (0x4000U)
#define LPI2C_SIER_GCIE_SHIFT                    (14U)
/*! GCIE - General Call Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
#define LPI2C_SIER_SARIE_MASK                    (0x8000U)
#define LPI2C_SIER_SARIE_SHIFT                   (15U)
/*! SARIE - SMBus Alert Response Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
/*! @} */

/*! @name SDER - Slave DMA Enable Register */
/*! @{ */
#define LPI2C_SDER_TDDE_MASK                     (0x1U)
#define LPI2C_SDER_TDDE_SHIFT                    (0U)
/*! TDDE - Transmit Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
#define LPI2C_SDER_RDDE_MASK                     (0x2U)
#define LPI2C_SDER_RDDE_SHIFT                    (1U)
/*! RDDE - Receive Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
#define LPI2C_SDER_AVDE_MASK                     (0x4U)
#define LPI2C_SDER_AVDE_SHIFT                    (2U)
/*! AVDE - Address Valid DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
#define LPI2C_SDER_RSDE_MASK                     (0x100U)
#define LPI2C_SDER_RSDE_SHIFT                    (8U)
/*! RSDE - Repeated Start DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_RSDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK)
#define LPI2C_SDER_SDDE_MASK                     (0x200U)
#define LPI2C_SDER_SDDE_SHIFT                    (9U)
/*! SDDE - Stop Detect DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_SDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK)
/*! @} */

/*! @name SCFGR1 - Slave Configuration Register 1 */
/*! @{ */
#define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
#define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
/*! ADRSTALL - Address SCL Stall
 *  0b0..Clock stretching is disabled
 *  0b1..Clock stretching is enabled
 */
#define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
#define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
#define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
/*! RXSTALL - RX SCL Stall
 *  0b0..Clock stretching is disabled
 *  0b1..Clock stretching is enabled
 */
#define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
#define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
#define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
/*! TXDSTALL - TX Data SCL Stall
 *  0b0..Clock stretching is disabled
 *  0b1..Clock stretching is enabled
 */
#define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
#define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
#define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
/*! ACKSTALL - ACK SCL Stall
 *  0b0..Clock stretching is disabled
 *  0b1..Clock stretching is enabled
 */
#define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
#define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
#define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
/*! GCEN - General Call Enable
 *  0b0..General Call address is disabled
 *  0b1..General Call address is enabled
 */
#define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
#define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
#define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
/*! SAEN - SMBus Alert Enable
 *  0b0..Disables match on SMBus Alert
 *  0b1..Enables match on SMBus Alert
 */
#define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
#define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
#define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
/*! TXCFG - Transmit Flag Configuration
 *  0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty
 *  0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty
 */
#define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
#define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
#define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
/*! RXCFG - Receive Data Configuration
 *  0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]).
 *  0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]).
 */
#define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
#define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
#define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
/*! IGNACK - Ignore NACK
 *  0b0..Slave will end transfer when NACK is detected
 *  0b1..Slave will not end transfer when NACK detected
 */
#define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
#define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
#define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
/*! HSMEN - High Speed Mode Enable
 *  0b0..Disables detection of HS-mode master code
 *  0b1..Enables detection of HS-mode master code
 */
#define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
#define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
#define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
/*! ADDRCFG - Address Configuration
 *  0b000..Address match 0 (7-bit)
 *  0b001..Address match 0 (10-bit)
 *  0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
 *  0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
 *  0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
 *  0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
 *  0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
 *  0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
 */
#define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
/*! @} */

/*! @name SCFGR2 - Slave Configuration Register 2 */
/*! @{ */
#define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
#define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
#define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
#define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
#define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
#define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
#define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
#define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
#define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
#define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
#define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
#define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
/*! @} */

/*! @name SAMR - Slave Address Match Register */
/*! @{ */
#define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
#define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
#define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
#define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
#define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
#define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
/*! @} */

/*! @name SASR - Slave Address Status Register */
/*! @{ */
#define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
#define LPI2C_SASR_RADDR_SHIFT                   (0U)
#define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
#define LPI2C_SASR_ANV_MASK                      (0x4000U)
#define LPI2C_SASR_ANV_SHIFT                     (14U)
/*! ANV - Address Not Valid
 *  0b0..Received Address (RADDR) is valid
 *  0b1..Received Address (RADDR) is not valid
 */
#define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
/*! @} */

/*! @name STAR - Slave Transmit ACK Register */
/*! @{ */
#define LPI2C_STAR_TXNACK_MASK                   (0x1U)
#define LPI2C_STAR_TXNACK_SHIFT                  (0U)
/*! TXNACK - Transmit NACK
 *  0b0..Write a Transmit ACK for each received word
 *  0b1..Write a Transmit NACK for each received word
 */
#define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
/*! @} */

/*! @name STDR - Slave Transmit Data Register */
/*! @{ */
#define LPI2C_STDR_DATA_MASK                     (0xFFU)
#define LPI2C_STDR_DATA_SHIFT                    (0U)
#define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
/*! @} */

/*! @name SRDR - Slave Receive Data Register */
/*! @{ */
#define LPI2C_SRDR_DATA_MASK                     (0xFFU)
#define LPI2C_SRDR_DATA_SHIFT                    (0U)
#define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
#define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
#define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
/*! RXEMPTY - RX Empty
 *  0b0..The Receive Data Register is not empty
 *  0b1..The Receive Data Register is empty
 */
#define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
#define LPI2C_SRDR_SOF_MASK                      (0x8000U)
#define LPI2C_SRDR_SOF_SHIFT                     (15U)
/*! SOF - Start Of Frame
 *  0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
 *  0b1..Indicates this is the first data word since a (repeated) START or STOP condition
 */
#define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LPI2C_Register_Masks */


/* LPI2C - Peripheral instance base addresses */
/** Peripheral CM4_0__LPI2C base address */
#define CM4_0__LPI2C_BASE                        (0x37230000u)
/** Peripheral CM4_0__LPI2C base pointer */
#define CM4_0__LPI2C                             ((LPI2C_Type *)CM4_0__LPI2C_BASE)
/** Peripheral CM4_1__LPI2C base address */
#define CM4_1__LPI2C_BASE                        (0x41230000u)
/** Peripheral CM4_1__LPI2C base pointer */
#define CM4_1__LPI2C                             ((LPI2C_Type *)CM4_1__LPI2C_BASE)
/** Peripheral DI_HDMI__LPI2C base address */
#define DI_HDMI__LPI2C_BASE                      (0x56266000u)
/** Peripheral DI_HDMI__LPI2C base pointer */
#define DI_HDMI__LPI2C                           ((LPI2C_Type *)DI_HDMI__LPI2C_BASE)
/** Peripheral DI_LVDS_0__LPI2C0 base address */
#define DI_LVDS_0__LPI2C0_BASE                   (0x56246000u)
/** Peripheral DI_LVDS_0__LPI2C0 base pointer */
#define DI_LVDS_0__LPI2C0                        ((LPI2C_Type *)DI_LVDS_0__LPI2C0_BASE)
/** Peripheral DI_LVDS_0__LPI2C1 base address */
#define DI_LVDS_0__LPI2C1_BASE                   (0x56247000u)
/** Peripheral DI_LVDS_0__LPI2C1 base pointer */
#define DI_LVDS_0__LPI2C1                        ((LPI2C_Type *)DI_LVDS_0__LPI2C1_BASE)
/** Peripheral DI_LVDS_1__LPI2C0 base address */
#define DI_LVDS_1__LPI2C0_BASE                   (0x57246000u)
/** Peripheral DI_LVDS_1__LPI2C0 base pointer */
#define DI_LVDS_1__LPI2C0                        ((LPI2C_Type *)DI_LVDS_1__LPI2C0_BASE)
/** Peripheral DI_LVDS_1__LPI2C1 base address */
#define DI_LVDS_1__LPI2C1_BASE                   (0x57247000u)
/** Peripheral DI_LVDS_1__LPI2C1 base pointer */
#define DI_LVDS_1__LPI2C1                        ((LPI2C_Type *)DI_LVDS_1__LPI2C1_BASE)
/** Peripheral DI_MIPI_0__LPI2C0 base address */
#define DI_MIPI_0__LPI2C0_BASE                   (0x56226000u)
/** Peripheral DI_MIPI_0__LPI2C0 base pointer */
#define DI_MIPI_0__LPI2C0                        ((LPI2C_Type *)DI_MIPI_0__LPI2C0_BASE)
/** Peripheral DI_MIPI_0__LPI2C1 base address */
#define DI_MIPI_0__LPI2C1_BASE                   (0x56227000u)
/** Peripheral DI_MIPI_0__LPI2C1 base pointer */
#define DI_MIPI_0__LPI2C1                        ((LPI2C_Type *)DI_MIPI_0__LPI2C1_BASE)
/** Peripheral DI_MIPI_1__LPI2C0 base address */
#define DI_MIPI_1__LPI2C0_BASE                   (0x57226000u)
/** Peripheral DI_MIPI_1__LPI2C0 base pointer */
#define DI_MIPI_1__LPI2C0                        ((LPI2C_Type *)DI_MIPI_1__LPI2C0_BASE)
/** Peripheral DI_MIPI_1__LPI2C1 base address */
#define DI_MIPI_1__LPI2C1_BASE                   (0x57227000u)
/** Peripheral DI_MIPI_1__LPI2C1 base pointer */
#define DI_MIPI_1__LPI2C1                        ((LPI2C_Type *)DI_MIPI_1__LPI2C1_BASE)
/** Peripheral DMA__LPI2C0 base address */
#define DMA__LPI2C0_BASE                         (0x5A800000u)
/** Peripheral DMA__LPI2C0 base pointer */
#define DMA__LPI2C0                              ((LPI2C_Type *)DMA__LPI2C0_BASE)
/** Peripheral DMA__LPI2C1 base address */
#define DMA__LPI2C1_BASE                         (0x5A810000u)
/** Peripheral DMA__LPI2C1 base pointer */
#define DMA__LPI2C1                              ((LPI2C_Type *)DMA__LPI2C1_BASE)
/** Peripheral DMA__LPI2C2 base address */
#define DMA__LPI2C2_BASE                         (0x5A820000u)
/** Peripheral DMA__LPI2C2 base pointer */
#define DMA__LPI2C2                              ((LPI2C_Type *)DMA__LPI2C2_BASE)
/** Peripheral DMA__LPI2C3 base address */
#define DMA__LPI2C3_BASE                         (0x5A830000u)
/** Peripheral DMA__LPI2C3 base pointer */
#define DMA__LPI2C3                              ((LPI2C_Type *)DMA__LPI2C3_BASE)
/** Peripheral DMA__LPI2C4 base address */
#define DMA__LPI2C4_BASE                         (0x5A840000u)
/** Peripheral DMA__LPI2C4 base pointer */
#define DMA__LPI2C4                              ((LPI2C_Type *)DMA__LPI2C4_BASE)
/** Peripheral MIPI_CSI_0__LPI2C base address */
#define MIPI_CSI_0__LPI2C_BASE                   (0x58226000u)
/** Peripheral MIPI_CSI_0__LPI2C base pointer */
#define MIPI_CSI_0__LPI2C                        ((LPI2C_Type *)MIPI_CSI_0__LPI2C_BASE)
/** Peripheral MIPI_CSI_1__LPI2C base address */
#define MIPI_CSI_1__LPI2C_BASE                   (0x58246000u)
/** Peripheral MIPI_CSI_1__LPI2C base pointer */
#define MIPI_CSI_1__LPI2C                        ((LPI2C_Type *)MIPI_CSI_1__LPI2C_BASE)
/** Peripheral RX_HDMI__LPI2C base address */
#define RX_HDMI__LPI2C_BASE                      (0x58266000u)
/** Peripheral RX_HDMI__LPI2C base pointer */
#define RX_HDMI__LPI2C                           ((LPI2C_Type *)RX_HDMI__LPI2C_BASE)
/** Peripheral SCU__LPI2C base address */
#define SCU__LPI2C_BASE                          (0x33230000u)
/** Peripheral SCU__LPI2C base pointer */
#define SCU__LPI2C                               ((LPI2C_Type *)SCU__LPI2C_BASE)
/** Array initializer of LPI2C peripheral base addresses */
#define LPI2C_BASE_ADDRS                         { CM4_0__LPI2C_BASE, CM4_1__LPI2C_BASE, DI_HDMI__LPI2C_BASE, DI_LVDS_0__LPI2C0_BASE, DI_LVDS_0__LPI2C1_BASE, DI_LVDS_1__LPI2C0_BASE, DI_LVDS_1__LPI2C1_BASE, DI_MIPI_0__LPI2C0_BASE, DI_MIPI_0__LPI2C1_BASE, DI_MIPI_1__LPI2C0_BASE, DI_MIPI_1__LPI2C1_BASE, DMA__LPI2C0_BASE, DMA__LPI2C1_BASE, DMA__LPI2C2_BASE, DMA__LPI2C3_BASE, DMA__LPI2C4_BASE, MIPI_CSI_0__LPI2C_BASE, MIPI_CSI_1__LPI2C_BASE, RX_HDMI__LPI2C_BASE, SCU__LPI2C_BASE }
/** Array initializer of LPI2C peripheral base pointers */
#define LPI2C_BASE_PTRS                          { CM4_0__LPI2C, CM4_1__LPI2C, DI_HDMI__LPI2C, DI_LVDS_0__LPI2C0, DI_LVDS_0__LPI2C1, DI_LVDS_1__LPI2C0, DI_LVDS_1__LPI2C1, DI_MIPI_0__LPI2C0, DI_MIPI_0__LPI2C1, DI_MIPI_1__LPI2C0, DI_MIPI_1__LPI2C1, DMA__LPI2C0, DMA__LPI2C1, DMA__LPI2C2, DMA__LPI2C3, DMA__LPI2C4, MIPI_CSI_0__LPI2C, MIPI_CSI_1__LPI2C, RX_HDMI__LPI2C, SCU__LPI2C }
/** Interrupt vectors for the LPI2C peripheral type */
#define LPI2C_IRQS                               { NotAvail_IRQn, M4_1_LPI2C_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }

/*!
 * @}
 */ /* end of group LPI2C_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPIT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer
 * @{
 */

/** LPIT - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __IO uint32_t MCR;                               /**< Module Control Register, offset: 0x8 */
  __IO uint32_t MSR;                               /**< Module Status Register, offset: 0xC */
  __IO uint32_t MIER;                              /**< Module Interrupt Enable Register, offset: 0x10 */
  __IO uint32_t SETTEN;                            /**< Set Timer Enable Register, offset: 0x14 */
  __O  uint32_t CLRTEN;                            /**< Clear Timer Enable Register, offset: 0x18 */
       uint32_t RSVD;                              /**< Reserved Register, offset: 0x1C */
  struct {                                         /* offset: 0x20, array step: 0x10 */
    __IO uint32_t TVAL;                              /**< Timer Value Register, array offset: 0x20, array step: 0x10 */
    __I  uint32_t CVAL;                              /**< Current Timer Value, array offset: 0x24, array step: 0x10 */
    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x28, array step: 0x10 */
         uint32_t RFU;                               /**< Reserved for Future Use, array offset: 0x2C, array step: 0x10 */
  } CHANNEL[4];
} LPIT_Type;

/* ----------------------------------------------------------------------------
   -- LPIT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPIT_Register_Masks LPIT Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */
#define LPIT_VERID_FEATURE_MASK                  (0xFFFFU)
#define LPIT_VERID_FEATURE_SHIFT                 (0U)
#define LPIT_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK)
#define LPIT_VERID_MINOR_MASK                    (0xFF0000U)
#define LPIT_VERID_MINOR_SHIFT                   (16U)
#define LPIT_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK)
#define LPIT_VERID_MAJOR_MASK                    (0xFF000000U)
#define LPIT_VERID_MAJOR_SHIFT                   (24U)
#define LPIT_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */
#define LPIT_PARAM_CHANNEL_MASK                  (0xFFU)
#define LPIT_PARAM_CHANNEL_SHIFT                 (0U)
#define LPIT_PARAM_CHANNEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK)
#define LPIT_PARAM_EXT_TRIG_MASK                 (0xFF00U)
#define LPIT_PARAM_EXT_TRIG_SHIFT                (8U)
#define LPIT_PARAM_EXT_TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK)
/*! @} */

/*! @name MCR - Module Control Register */
/*! @{ */
#define LPIT_MCR_M_CEN_MASK                      (0x1U)
#define LPIT_MCR_M_CEN_SHIFT                     (0U)
/*! M_CEN - Module Clock Enable
 *  0b0..Disable peripheral clock to timers
 *  0b1..Enable peripheral clock to timers
 */
#define LPIT_MCR_M_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK)
#define LPIT_MCR_SW_RST_MASK                     (0x2U)
#define LPIT_MCR_SW_RST_SHIFT                    (1U)
/*! SW_RST - Software Reset Bit
 *  0b0..Timer channels and registers are not reset
 *  0b1..Reset timer channels and registers
 */
#define LPIT_MCR_SW_RST(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK)
#define LPIT_MCR_DOZE_EN_MASK                    (0x4U)
#define LPIT_MCR_DOZE_EN_SHIFT                   (2U)
/*! DOZE_EN - DOZE Mode Enable Bit
 *  0b0..Stop timer channels in DOZE mode
 *  0b1..Allow timer channels to continue to run in DOZE mode
 */
#define LPIT_MCR_DOZE_EN(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK)
#define LPIT_MCR_DBG_EN_MASK                     (0x8U)
#define LPIT_MCR_DBG_EN_SHIFT                    (3U)
/*! DBG_EN - Debug Enable Bit
 *  0b0..Stop timer channels in Debug mode
 *  0b1..Allow timer channels to continue to run in Debug mode
 */
#define LPIT_MCR_DBG_EN(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK)
/*! @} */

/*! @name MSR - Module Status Register */
/*! @{ */
#define LPIT_MSR_TIF0_MASK                       (0x1U)
#define LPIT_MSR_TIF0_SHIFT                      (0U)
/*! TIF0 - Channel 0 Timer Interrupt Flag
 *  0b0..Timer has not timed out
 *  0b1..Timeout has occurred (timer has timed out)
 */
#define LPIT_MSR_TIF0(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK)
#define LPIT_MSR_TIF1_MASK                       (0x2U)
#define LPIT_MSR_TIF1_SHIFT                      (1U)
/*! TIF1 - Channel 1 Timer Interrupt Flag
 *  0b0..Timer has not timed out
 *  0b1..Timeout has occurred (timer has timed out)
 */
#define LPIT_MSR_TIF1(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK)
#define LPIT_MSR_TIF2_MASK                       (0x4U)
#define LPIT_MSR_TIF2_SHIFT                      (2U)
/*! TIF2 - Channel 2 Timer Interrupt Flag
 *  0b0..Timer has not timed out
 *  0b1..Timeout has occurred (timer has timed out)
 */
#define LPIT_MSR_TIF2(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK)
#define LPIT_MSR_TIF3_MASK                       (0x8U)
#define LPIT_MSR_TIF3_SHIFT                      (3U)
/*! TIF3 - Channel 3 Timer Interrupt Flag
 *  0b0..Timer has not timed out
 *  0b1..Timeout has occurred (timer has timed out)
 */
#define LPIT_MSR_TIF3(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK)
/*! @} */

/*! @name MIER - Module Interrupt Enable Register */
/*! @{ */
#define LPIT_MIER_TIE0_MASK                      (0x1U)
#define LPIT_MIER_TIE0_SHIFT                     (0U)
/*! TIE0 - Channel 0 Timer Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPIT_MIER_TIE0(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK)
#define LPIT_MIER_TIE1_MASK                      (0x2U)
#define LPIT_MIER_TIE1_SHIFT                     (1U)
/*! TIE1 - Channel 1 Timer Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPIT_MIER_TIE1(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK)
#define LPIT_MIER_TIE2_MASK                      (0x4U)
#define LPIT_MIER_TIE2_SHIFT                     (2U)
/*! TIE2 - Channel 2 Timer Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPIT_MIER_TIE2(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK)
#define LPIT_MIER_TIE3_MASK                      (0x8U)
#define LPIT_MIER_TIE3_SHIFT                     (3U)
/*! TIE3 - Channel 3 Timer Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPIT_MIER_TIE3(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK)
/*! @} */

/*! @name SETTEN - Set Timer Enable Register */
/*! @{ */
#define LPIT_SETTEN_SET_T_EN_0_MASK              (0x1U)
#define LPIT_SETTEN_SET_T_EN_0_SHIFT             (0U)
/*! SET_T_EN_0 - Set Timer 0 Enable
 *  0b0..No effect
 *  0b1..Enables Timer Channel 0
 */
#define LPIT_SETTEN_SET_T_EN_0(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK)
#define LPIT_SETTEN_SET_T_EN_1_MASK              (0x2U)
#define LPIT_SETTEN_SET_T_EN_1_SHIFT             (1U)
/*! SET_T_EN_1 - Set Timer 1 Enable
 *  0b0..No Effect
 *  0b1..Enables Timer Channel 1
 */
#define LPIT_SETTEN_SET_T_EN_1(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK)
#define LPIT_SETTEN_SET_T_EN_2_MASK              (0x4U)
#define LPIT_SETTEN_SET_T_EN_2_SHIFT             (2U)
/*! SET_T_EN_2 - Set Timer 2 Enable
 *  0b0..No Effect
 *  0b1..Enables Timer Channel 2
 */
#define LPIT_SETTEN_SET_T_EN_2(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK)
#define LPIT_SETTEN_SET_T_EN_3_MASK              (0x8U)
#define LPIT_SETTEN_SET_T_EN_3_SHIFT             (3U)
/*! SET_T_EN_3 - Set Timer 3 Enable
 *  0b0..No effect
 *  0b1..Enables Timer Channel 3
 */
#define LPIT_SETTEN_SET_T_EN_3(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK)
/*! @} */

/*! @name CLRTEN - Clear Timer Enable Register */
/*! @{ */
#define LPIT_CLRTEN_CLR_T_EN_0_MASK              (0x1U)
#define LPIT_CLRTEN_CLR_T_EN_0_SHIFT             (0U)
/*! CLR_T_EN_0 - Clear Timer 0 Enable
 *  0b0..No action
 *  0b1..Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0
 */
#define LPIT_CLRTEN_CLR_T_EN_0(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK)
#define LPIT_CLRTEN_CLR_T_EN_1_MASK              (0x2U)
#define LPIT_CLRTEN_CLR_T_EN_1_SHIFT             (1U)
/*! CLR_T_EN_1 - Clear Timer 1 Enable
 *  0b0..No Action
 *  0b1..Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1
 */
#define LPIT_CLRTEN_CLR_T_EN_1(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK)
#define LPIT_CLRTEN_CLR_T_EN_2_MASK              (0x4U)
#define LPIT_CLRTEN_CLR_T_EN_2_SHIFT             (2U)
/*! CLR_T_EN_2 - Clear Timer 2 Enable
 *  0b0..No Action
 *  0b1..Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2
 */
#define LPIT_CLRTEN_CLR_T_EN_2(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK)
#define LPIT_CLRTEN_CLR_T_EN_3_MASK              (0x8U)
#define LPIT_CLRTEN_CLR_T_EN_3_SHIFT             (3U)
/*! CLR_T_EN_3 - Clear Timer 3 Enable
 *  0b0..No Action
 *  0b1..Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3
 */
#define LPIT_CLRTEN_CLR_T_EN_3(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK)
/*! @} */

/*! @name TVAL - Timer Value Register */
/*! @{ */
#define LPIT_TVAL_TMR_VAL_MASK                   (0xFFFFFFFFU)
#define LPIT_TVAL_TMR_VAL_SHIFT                  (0U)
/*! TMR_VAL - Timer Value
 *  0b00000000000000000000000000000000..Invalid load value in compare mode
 *  0b00000000000000000000000000000001..Invalid load value in compare mode
 *  0b00000000000000000000000000000010-0b11111111111111111111111111111111..In compare mode: the value to be loaded; in capture mode, the value of the timer
 */
#define LPIT_TVAL_TMR_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK)
/*! @} */

/* The count of LPIT_TVAL */
#define LPIT_TVAL_COUNT                          (4U)

/*! @name CVAL - Current Timer Value */
/*! @{ */
#define LPIT_CVAL_TMR_CUR_VAL_MASK               (0xFFFFFFFFU)
#define LPIT_CVAL_TMR_CUR_VAL_SHIFT              (0U)
#define LPIT_CVAL_TMR_CUR_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/*! @} */

/* The count of LPIT_CVAL */
#define LPIT_CVAL_COUNT                          (4U)

/*! @name TCTRL - Timer Control Register */
/*! @{ */
#define LPIT_TCTRL_T_EN_MASK                     (0x1U)
#define LPIT_TCTRL_T_EN_SHIFT                    (0U)
/*! T_EN - Timer Enable
 *  0b0..Timer Channel is disabled
 *  0b1..Timer Channel is enabled
 */
#define LPIT_TCTRL_T_EN(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK)
#define LPIT_TCTRL_CHAIN_MASK                    (0x2U)
#define LPIT_TCTRL_CHAIN_SHIFT                   (1U)
/*! CHAIN - Chain Channel
 *  0b0..Channel Chaining is disabled. The channel timer runs independently.
 *  0b1..Channel Chaining is enabled. The timer decrements on the previous channel's timeout.
 */
#define LPIT_TCTRL_CHAIN(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK)
#define LPIT_TCTRL_MODE_MASK                     (0xCU)
#define LPIT_TCTRL_MODE_SHIFT                    (2U)
/*! MODE - Timer Operation Mode
 *  0b00..32-bit Periodic Counter
 *  0b01..Dual 16-bit Periodic Counter
 *  0b10..32-bit Trigger Accumulator
 *  0b11..32-bit Trigger Input Capture
 */
#define LPIT_TCTRL_MODE(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK)
#define LPIT_TCTRL_TSOT_MASK                     (0x10000U)
#define LPIT_TCTRL_TSOT_SHIFT                    (16U)
/*! TSOT - Timer Start On Trigger
 *  0b0..Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI))
 *  0b1..Timer starts to decrement when a rising edge on a selected trigger is detected
 */
#define LPIT_TCTRL_TSOT(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK)
#define LPIT_TCTRL_TSOI_MASK                     (0x20000U)
#define LPIT_TCTRL_TSOI_SHIFT                    (17U)
/*! TSOI - Timer Stop On Interrupt
 *  0b0..The channel timer does not stop after timeout
 *  0b1..The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected.
 */
#define LPIT_TCTRL_TSOI(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK)
#define LPIT_TCTRL_TROT_MASK                     (0x40000U)
#define LPIT_TCTRL_TROT_SHIFT                    (18U)
/*! TROT - Timer Reload On Trigger
 *  0b0..Timer will not reload on the selected trigger
 *  0b1..Timer will reload on the selected trigger
 */
#define LPIT_TCTRL_TROT(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK)
#define LPIT_TCTRL_TRG_SRC_MASK                  (0x800000U)
#define LPIT_TCTRL_TRG_SRC_SHIFT                 (23U)
/*! TRG_SRC - Trigger Source
 *  0b0..Selects external triggers
 *  0b1..Selects internal triggers
 */
#define LPIT_TCTRL_TRG_SRC(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK)
#define LPIT_TCTRL_TRG_SEL_MASK                  (0xF000000U)
#define LPIT_TCTRL_TRG_SEL_SHIFT                 (24U)
/*! TRG_SEL - Trigger Select
 *  0b0000-0b0011..Timer channel 0 - 3 trigger source is selected
 *  0b0100-0b1111..Reserved
 */
#define LPIT_TCTRL_TRG_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK)
/*! @} */

/* The count of LPIT_TCTRL */
#define LPIT_TCTRL_COUNT                         (4U)

/* The count of LPIT_RFU */
#define LPIT_RFU_COUNT                           (4U)


/*!
 * @}
 */ /* end of group LPIT_Register_Masks */


/* LPIT - Peripheral instance base addresses */
/** Peripheral CM4_0__LPIT base address */
#define CM4_0__LPIT_BASE                         (0x37210000u)
/** Peripheral CM4_0__LPIT base pointer */
#define CM4_0__LPIT                              ((LPIT_Type *)CM4_0__LPIT_BASE)
/** Peripheral CM4_1__LPIT base address */
#define CM4_1__LPIT_BASE                         (0x41210000u)
/** Peripheral CM4_1__LPIT base pointer */
#define CM4_1__LPIT                              ((LPIT_Type *)CM4_1__LPIT_BASE)
/** Peripheral SCU__LPIT base address */
#define SCU__LPIT_BASE                           (0x33210000u)
/** Peripheral SCU__LPIT base pointer */
#define SCU__LPIT                                ((LPIT_Type *)SCU__LPIT_BASE)
/** Array initializer of LPIT peripheral base addresses */
#define LPIT_BASE_ADDRS                          { CM4_0__LPIT_BASE, CM4_1__LPIT_BASE, SCU__LPIT_BASE }
/** Array initializer of LPIT peripheral base pointers */
#define LPIT_BASE_PTRS                           { CM4_0__LPIT, CM4_1__LPIT, SCU__LPIT }
/** Interrupt vectors for the LPIT peripheral type */
#define LPIT_IRQS                                { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { M4_1_LPIT_IRQn, M4_1_LPIT_IRQn, M4_1_LPIT_IRQn, M4_1_LPIT_IRQn }, { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } }

/*!
 * @}
 */ /* end of group LPIT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPSPI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
 * @{
 */

/** LPSPI - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t CR;                                /**< Control Register, offset: 0x10 */
  __IO uint32_t SR;                                /**< Status Register, offset: 0x14 */
  __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x18 */
  __IO uint32_t DER;                               /**< DMA Enable Register, offset: 0x1C */
  __IO uint32_t CFGR0;                             /**< Configuration Register 0, offset: 0x20 */
  __IO uint32_t CFGR1;                             /**< Configuration Register 1, offset: 0x24 */
       uint8_t RESERVED_1[8];
  __IO uint32_t DMR0;                              /**< Data Match Register 0, offset: 0x30 */
  __IO uint32_t DMR1;                              /**< Data Match Register 1, offset: 0x34 */
       uint8_t RESERVED_2[8];
  __IO uint32_t CCR;                               /**< Clock Configuration Register, offset: 0x40 */
       uint8_t RESERVED_3[20];
  __IO uint32_t FCR;                               /**< FIFO Control Register, offset: 0x58 */
  __I  uint32_t FSR;                               /**< FIFO Status Register, offset: 0x5C */
  __IO uint32_t TCR;                               /**< Transmit Command Register, offset: 0x60 */
  __O  uint32_t TDR;                               /**< Transmit Data Register, offset: 0x64 */
       uint8_t RESERVED_4[8];
  __I  uint32_t RSR;                               /**< Receive Status Register, offset: 0x70 */
  __I  uint32_t RDR;                               /**< Receive Data Register, offset: 0x74 */
} LPSPI_Type;

/* ----------------------------------------------------------------------------
   -- LPSPI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */
#define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
#define LPSPI_VERID_FEATURE_SHIFT                (0U)
/*! FEATURE - Module Identification Number
 *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
 */
#define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
#define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
#define LPSPI_VERID_MINOR_SHIFT                  (16U)
#define LPSPI_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
#define LPSPI_VERID_MAJOR_MASK                   (0xFF000000U)
#define LPSPI_VERID_MAJOR_SHIFT                  (24U)
#define LPSPI_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */
#define LPSPI_PARAM_TXFIFO_MASK                  (0xFFU)
#define LPSPI_PARAM_TXFIFO_SHIFT                 (0U)
#define LPSPI_PARAM_TXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
#define LPSPI_PARAM_RXFIFO_MASK                  (0xFF00U)
#define LPSPI_PARAM_RXFIFO_SHIFT                 (8U)
#define LPSPI_PARAM_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
/*! @} */

/*! @name CR - Control Register */
/*! @{ */
#define LPSPI_CR_MEN_MASK                        (0x1U)
#define LPSPI_CR_MEN_SHIFT                       (0U)
/*! MEN - Module Enable
 *  0b0..Module is disabled
 *  0b1..Module is enabled
 */
#define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
#define LPSPI_CR_RST_MASK                        (0x2U)
#define LPSPI_CR_RST_SHIFT                       (1U)
/*! RST - Software Reset
 *  0b0..Module is not reset
 *  0b1..Module is reset
 */
#define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
#define LPSPI_CR_DOZEN_MASK                      (0x4U)
#define LPSPI_CR_DOZEN_SHIFT                     (2U)
/*! DOZEN - Doze Mode Enable
 *  0b0..LPSPI module is enabled in Doze mode
 *  0b1..LPSPI module is disabled in Doze mode
 */
#define LPSPI_CR_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
#define LPSPI_CR_DBGEN_MASK                      (0x8U)
#define LPSPI_CR_DBGEN_SHIFT                     (3U)
/*! DBGEN - Debug Enable
 *  0b0..LPSPI module is disabled in debug mode
 *  0b1..LPSPI module is enabled in debug mode
 */
#define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
#define LPSPI_CR_RTF_MASK                        (0x100U)
#define LPSPI_CR_RTF_SHIFT                       (8U)
/*! RTF - Reset Transmit FIFO
 *  0b0..No effect
 *  0b1..Transmit FIFO is reset
 */
#define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
#define LPSPI_CR_RRF_MASK                        (0x200U)
#define LPSPI_CR_RRF_SHIFT                       (9U)
/*! RRF - Reset Receive FIFO
 *  0b0..No effect
 *  0b1..Receive FIFO is reset
 */
#define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
/*! @} */

/*! @name SR - Status Register */
/*! @{ */
#define LPSPI_SR_TDF_MASK                        (0x1U)
#define LPSPI_SR_TDF_SHIFT                       (0U)
/*! TDF - Transmit Data Flag
 *  0b0..Transmit data not requested
 *  0b1..Transmit data is requested
 */
#define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
#define LPSPI_SR_RDF_MASK                        (0x2U)
#define LPSPI_SR_RDF_SHIFT                       (1U)
/*! RDF - Receive Data Flag
 *  0b0..Receive Data is not ready
 *  0b1..Receive data is ready
 */
#define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
#define LPSPI_SR_WCF_MASK                        (0x100U)
#define LPSPI_SR_WCF_SHIFT                       (8U)
/*! WCF - Word Complete Flag
 *  0b0..Transfer of a received word has not yet completed
 *  0b1..Transfer of a received word has completed
 */
#define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
#define LPSPI_SR_FCF_MASK                        (0x200U)
#define LPSPI_SR_FCF_SHIFT                       (9U)
/*! FCF - Frame Complete Flag
 *  0b0..Frame transfer has not completed
 *  0b1..Frame transfer has completed
 */
#define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
#define LPSPI_SR_TCF_MASK                        (0x400U)
#define LPSPI_SR_TCF_SHIFT                       (10U)
/*! TCF - Transfer Complete Flag
 *  0b0..All transfers have not completed
 *  0b1..All transfers have completed
 */
#define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
#define LPSPI_SR_TEF_MASK                        (0x800U)
#define LPSPI_SR_TEF_SHIFT                       (11U)
/*! TEF - Transmit Error Flag
 *  0b0..Transmit FIFO underrun has not occurred
 *  0b1..Transmit FIFO underrun has occurred
 */
#define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
#define LPSPI_SR_REF_MASK                        (0x1000U)
#define LPSPI_SR_REF_SHIFT                       (12U)
/*! REF - Receive Error Flag
 *  0b0..Receive FIFO has not overflowed
 *  0b1..Receive FIFO has overflowed
 */
#define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
#define LPSPI_SR_DMF_MASK                        (0x2000U)
#define LPSPI_SR_DMF_SHIFT                       (13U)
/*! DMF - Data Match Flag
 *  0b0..Have not received matching data
 *  0b1..Have received matching data
 */
#define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
#define LPSPI_SR_MBF_MASK                        (0x1000000U)
#define LPSPI_SR_MBF_SHIFT                       (24U)
/*! MBF - Module Busy Flag
 *  0b0..LPSPI is idle
 *  0b1..LPSPI is busy
 */
#define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
/*! @} */

/*! @name IER - Interrupt Enable Register */
/*! @{ */
#define LPSPI_IER_TDIE_MASK                      (0x1U)
#define LPSPI_IER_TDIE_SHIFT                     (0U)
/*! TDIE - Transmit Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
#define LPSPI_IER_RDIE_MASK                      (0x2U)
#define LPSPI_IER_RDIE_SHIFT                     (1U)
/*! RDIE - Receive Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
#define LPSPI_IER_WCIE_MASK                      (0x100U)
#define LPSPI_IER_WCIE_SHIFT                     (8U)
/*! WCIE - Word Complete Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
#define LPSPI_IER_FCIE_MASK                      (0x200U)
#define LPSPI_IER_FCIE_SHIFT                     (9U)
/*! FCIE - Frame Complete Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
#define LPSPI_IER_TCIE_MASK                      (0x400U)
#define LPSPI_IER_TCIE_SHIFT                     (10U)
/*! TCIE - Transfer Complete Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
#define LPSPI_IER_TEIE_MASK                      (0x800U)
#define LPSPI_IER_TEIE_SHIFT                     (11U)
/*! TEIE - Transmit Error Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
#define LPSPI_IER_REIE_MASK                      (0x1000U)
#define LPSPI_IER_REIE_SHIFT                     (12U)
/*! REIE - Receive Error Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
#define LPSPI_IER_DMIE_MASK                      (0x2000U)
#define LPSPI_IER_DMIE_SHIFT                     (13U)
/*! DMIE - Data Match Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
/*! @} */

/*! @name DER - DMA Enable Register */
/*! @{ */
#define LPSPI_DER_TDDE_MASK                      (0x1U)
#define LPSPI_DER_TDDE_SHIFT                     (0U)
/*! TDDE - Transmit Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
#define LPSPI_DER_RDDE_MASK                      (0x2U)
#define LPSPI_DER_RDDE_SHIFT                     (1U)
/*! RDDE - Receive Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
#define LPSPI_DER_FCDE_MASK                      (0x200U)
#define LPSPI_DER_FCDE_SHIFT                     (9U)
/*! FCDE - Frame Complete DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPSPI_DER_FCDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK)
/*! @} */

/*! @name CFGR0 - Configuration Register 0 */
/*! @{ */
#define LPSPI_CFGR0_HREN_MASK                    (0x1U)
#define LPSPI_CFGR0_HREN_SHIFT                   (0U)
/*! HREN - Host Request Enable
 *  0b0..Host request is disabled
 *  0b1..Host request is enabled
 */
#define LPSPI_CFGR0_HREN(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
#define LPSPI_CFGR0_HRPOL_MASK                   (0x2U)
#define LPSPI_CFGR0_HRPOL_SHIFT                  (1U)
/*! HRPOL - Host Request Polarity
 *  0b0..Active low
 *  0b1..Active high
 */
#define LPSPI_CFGR0_HRPOL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
#define LPSPI_CFGR0_HRSEL_MASK                   (0x4U)
#define LPSPI_CFGR0_HRSEL_SHIFT                  (2U)
/*! HRSEL - Host Request Select
 *  0b0..Host request input is the LPSPI_HREQ pin
 *  0b1..Host request input is the input trigger
 */
#define LPSPI_CFGR0_HRSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
#define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
#define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
/*! CIRFIFO - Circular FIFO Enable
 *  0b0..Circular FIFO is disabled
 *  0b1..Circular FIFO is enabled
 */
#define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
#define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
#define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
/*! RDMO - Receive Data Match Only
 *  0b0..Received data is stored in the receive FIFO as in normal operations
 *  0b1..Received data is discarded unless the Data Match Flag (DMF) is set
 */
#define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
/*! @} */

/*! @name CFGR1 - Configuration Register 1 */
/*! @{ */
#define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
#define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
/*! MASTER - Master Mode
 *  0b0..Slave mode
 *  0b1..Master mode
 */
#define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
#define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
#define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
/*! SAMPLE - Sample Point
 *  0b0..Input data is sampled on SCK edge
 *  0b1..Input data is sampled on delayed SCK edge
 */
#define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
#define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
#define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
/*! AUTOPCS - Automatic PCS
 *  0b0..Automatic PCS generation is disabled
 *  0b1..Automatic PCS generation is enabled
 */
#define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
#define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
#define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
/*! NOSTALL - No Stall
 *  0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full
 *  0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur
 */
#define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
#define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
#define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
/*! PCSPOL - Peripheral Chip Select Polarity
 *  0b0000..The Peripheral Chip Select pin PCSx is active low
 *  0b0001..The Peripheral Chip Select pin PCSx is active high
 */
#define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
#define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
#define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
/*! MATCFG - Match Configuration
 *  0b000..Match is disabled
 *  0b001..Reserved
 *  0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)
 *  0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)
 *  0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)]
 *  0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)]
 *  0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)]
 *  0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]
 */
#define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
#define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
#define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
/*! PINCFG - Pin Configuration
 *  0b00..SIN is used for input data and SOUT is used for output data
 *  0b01..SIN is used for both input and output data
 *  0b10..SOUT is used for both input and output data
 *  0b11..SOUT is used for input data and SIN is used for output data
 */
#define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
#define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
#define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
/*! OUTCFG - Output Configuration
 *  0b0..Output data retains last value when chip select is negated
 *  0b1..Output data is tristated when chip select is negated
 */
#define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
#define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
#define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
/*! PCSCFG - Peripheral Chip Select Configuration
 *  0b0..PCS[3:2] are enabled
 *  0b1..PCS[3:2] are disabled
 */
#define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
/*! @} */

/*! @name DMR0 - Data Match Register 0 */
/*! @{ */
#define LPSPI_DMR0_MATCH0_MASK                   (0xFFFFFFFFU)
#define LPSPI_DMR0_MATCH0_SHIFT                  (0U)
#define LPSPI_DMR0_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
/*! @} */

/*! @name DMR1 - Data Match Register 1 */
/*! @{ */
#define LPSPI_DMR1_MATCH1_MASK                   (0xFFFFFFFFU)
#define LPSPI_DMR1_MATCH1_SHIFT                  (0U)
#define LPSPI_DMR1_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
/*! @} */

/*! @name CCR - Clock Configuration Register */
/*! @{ */
#define LPSPI_CCR_SCKDIV_MASK                    (0xFFU)
#define LPSPI_CCR_SCKDIV_SHIFT                   (0U)
#define LPSPI_CCR_SCKDIV(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
#define LPSPI_CCR_DBT_MASK                       (0xFF00U)
#define LPSPI_CCR_DBT_SHIFT                      (8U)
#define LPSPI_CCR_DBT(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
#define LPSPI_CCR_PCSSCK_MASK                    (0xFF0000U)
#define LPSPI_CCR_PCSSCK_SHIFT                   (16U)
#define LPSPI_CCR_PCSSCK(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
#define LPSPI_CCR_SCKPCS_MASK                    (0xFF000000U)
#define LPSPI_CCR_SCKPCS_SHIFT                   (24U)
#define LPSPI_CCR_SCKPCS(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
/*! @} */

/*! @name FCR - FIFO Control Register */
/*! @{ */
#define LPSPI_FCR_TXWATER_MASK                   (0x3FU)
#define LPSPI_FCR_TXWATER_SHIFT                  (0U)
#define LPSPI_FCR_TXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
#define LPSPI_FCR_RXWATER_MASK                   (0x3F0000U)
#define LPSPI_FCR_RXWATER_SHIFT                  (16U)
#define LPSPI_FCR_RXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
/*! @} */

/*! @name FSR - FIFO Status Register */
/*! @{ */
#define LPSPI_FSR_TXCOUNT_MASK                   (0x7FU)
#define LPSPI_FSR_TXCOUNT_SHIFT                  (0U)
#define LPSPI_FSR_TXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
#define LPSPI_FSR_RXCOUNT_MASK                   (0x7F0000U)
#define LPSPI_FSR_RXCOUNT_SHIFT                  (16U)
#define LPSPI_FSR_RXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
/*! @} */

/*! @name TCR - Transmit Command Register */
/*! @{ */
#define LPSPI_TCR_FRAMESZ_MASK                   (0xFFFU)
#define LPSPI_TCR_FRAMESZ_SHIFT                  (0U)
#define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
#define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
#define LPSPI_TCR_WIDTH_SHIFT                    (16U)
/*! WIDTH - Transfer Width
 *  0b00..1 bit transfer
 *  0b01..2 bit transfer
 *  0b10..4 bit transfer
 *  0b11..Reserved
 */
#define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
#define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
#define LPSPI_TCR_TXMSK_SHIFT                    (18U)
/*! TXMSK - Transmit Data Mask
 *  0b0..Normal transfer
 *  0b1..Mask transmit data
 */
#define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
#define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
#define LPSPI_TCR_RXMSK_SHIFT                    (19U)
/*! RXMSK - Receive Data Mask
 *  0b0..Normal transfer
 *  0b1..Receive data is masked
 */
#define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
#define LPSPI_TCR_CONTC_MASK                     (0x100000U)
#define LPSPI_TCR_CONTC_SHIFT                    (20U)
/*! CONTC - Continuing Command
 *  0b0..Command word for start of new transfer
 *  0b1..Command word for continuing transfer
 */
#define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
#define LPSPI_TCR_CONT_MASK                      (0x200000U)
#define LPSPI_TCR_CONT_SHIFT                     (21U)
/*! CONT - Continuous Transfer
 *  0b0..Continuous transfer is disabled
 *  0b1..Continuous transfer is enabled
 */
#define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
#define LPSPI_TCR_BYSW_MASK                      (0x400000U)
#define LPSPI_TCR_BYSW_SHIFT                     (22U)
/*! BYSW - Byte Swap
 *  0b0..Byte swap is disabled
 *  0b1..Byte swap is enabled
 */
#define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
#define LPSPI_TCR_LSBF_MASK                      (0x800000U)
#define LPSPI_TCR_LSBF_SHIFT                     (23U)
/*! LSBF - LSB First
 *  0b0..Data is transferred MSB first
 *  0b1..Data is transferred LSB first
 */
#define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
#define LPSPI_TCR_PCS_MASK                       (0x3000000U)
#define LPSPI_TCR_PCS_SHIFT                      (24U)
/*! PCS - Peripheral Chip Select
 *  0b00..Transfer using LPSPI_PCS[0]
 *  0b01..Transfer using LPSPI_PCS[1]
 *  0b10..Transfer using LPSPI_PCS[2]
 *  0b11..Transfer using LPSPI_PCS[3]
 */
#define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
#define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
#define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
/*! PRESCALE - Prescaler Value
 *  0b000..Divide by 1
 *  0b001..Divide by 2
 *  0b010..Divide by 4
 *  0b011..Divide by 8
 *  0b100..Divide by 16
 *  0b101..Divide by 32
 *  0b110..Divide by 64
 *  0b111..Divide by 128
 */
#define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
#define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
#define LPSPI_TCR_CPHA_SHIFT                     (30U)
/*! CPHA - Clock Phase
 *  0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK
 *  0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK
 */
#define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
#define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
#define LPSPI_TCR_CPOL_SHIFT                     (31U)
/*! CPOL - Clock Polarity
 *  0b0..The inactive state value of SCK is low
 *  0b1..The inactive state value of SCK is high
 */
#define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
/*! @} */

/*! @name TDR - Transmit Data Register */
/*! @{ */
#define LPSPI_TDR_DATA_MASK                      (0xFFFFFFFFU)
#define LPSPI_TDR_DATA_SHIFT                     (0U)
#define LPSPI_TDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
/*! @} */

/*! @name RSR - Receive Status Register */
/*! @{ */
#define LPSPI_RSR_SOF_MASK                       (0x1U)
#define LPSPI_RSR_SOF_SHIFT                      (0U)
/*! SOF - Start Of Frame
 *  0b0..Subsequent data word received after LPSPI_PCS assertion
 *  0b1..First data word received after LPSPI_PCS assertion
 */
#define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
#define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
#define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
/*! RXEMPTY - RX FIFO Empty
 *  0b0..RX FIFO is not empty
 *  0b1..RX FIFO is empty
 */
#define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
/*! @} */

/*! @name RDR - Receive Data Register */
/*! @{ */
#define LPSPI_RDR_DATA_MASK                      (0xFFFFFFFFU)
#define LPSPI_RDR_DATA_SHIFT                     (0U)
#define LPSPI_RDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LPSPI_Register_Masks */


/* LPSPI - Peripheral instance base addresses */
/** Peripheral DMA__LPSPI0 base address */
#define DMA__LPSPI0_BASE                         (0x5A000000u)
/** Peripheral DMA__LPSPI0 base pointer */
#define DMA__LPSPI0                              ((LPSPI_Type *)DMA__LPSPI0_BASE)
/** Peripheral DMA__LPSPI1 base address */
#define DMA__LPSPI1_BASE                         (0x5A010000u)
/** Peripheral DMA__LPSPI1 base pointer */
#define DMA__LPSPI1                              ((LPSPI_Type *)DMA__LPSPI1_BASE)
/** Peripheral DMA__LPSPI2 base address */
#define DMA__LPSPI2_BASE                         (0x5A020000u)
/** Peripheral DMA__LPSPI2 base pointer */
#define DMA__LPSPI2                              ((LPSPI_Type *)DMA__LPSPI2_BASE)
/** Peripheral DMA__LPSPI3 base address */
#define DMA__LPSPI3_BASE                         (0x5A030000u)
/** Peripheral DMA__LPSPI3 base pointer */
#define DMA__LPSPI3                              ((LPSPI_Type *)DMA__LPSPI3_BASE)
/** Array initializer of LPSPI peripheral base addresses */
#define LPSPI_BASE_ADDRS                         { DMA__LPSPI0_BASE, DMA__LPSPI1_BASE, DMA__LPSPI2_BASE, DMA__LPSPI3_BASE }
/** Array initializer of LPSPI peripheral base pointers */
#define LPSPI_BASE_PTRS                          { DMA__LPSPI0, DMA__LPSPI1, DMA__LPSPI2, DMA__LPSPI3 }
/** Interrupt vectors for the LPSPI peripheral type */
#define LPSPI_IRQS                               { DMA_SPI0_INT_IRQn, DMA_SPI1_INT_IRQn, DMA_SPI2_INT_IRQn, DMA_SPI3_INT_IRQn }

/*!
 * @}
 */ /* end of group LPSPI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPUART Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
 * @{
 */

/** LPUART - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __IO uint32_t GLOBAL;                            /**< LPUART Global Register, offset: 0x8 */
  __IO uint32_t PINCFG;                            /**< LPUART Pin Configuration Register, offset: 0xC */
  __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x10 */
  __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x14 */
  __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x18 */
  __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0x1C */
  __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x20 */
  __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x24 */
  __IO uint32_t FIFO;                              /**< LPUART FIFO Register, offset: 0x28 */
  __IO uint32_t WATER;                             /**< LPUART Watermark Register, offset: 0x2C */
} LPUART_Type;

/* ----------------------------------------------------------------------------
   -- LPUART Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPUART_Register_Masks LPUART Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */
#define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
#define LPUART_VERID_FEATURE_SHIFT               (0U)
/*! FEATURE - Feature Identification Number
 *  0b0000000000000001..Standard feature set.
 *  0b0000000000000011..Standard feature set with MODEM/IrDA support.
 */
#define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
#define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
#define LPUART_VERID_MINOR_SHIFT                 (16U)
#define LPUART_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
#define LPUART_VERID_MAJOR_MASK                  (0xFF000000U)
#define LPUART_VERID_MAJOR_SHIFT                 (24U)
#define LPUART_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */
#define LPUART_PARAM_TXFIFO_MASK                 (0xFFU)
#define LPUART_PARAM_TXFIFO_SHIFT                (0U)
#define LPUART_PARAM_TXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
#define LPUART_PARAM_RXFIFO_MASK                 (0xFF00U)
#define LPUART_PARAM_RXFIFO_SHIFT                (8U)
#define LPUART_PARAM_RXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
/*! @} */

/*! @name GLOBAL - LPUART Global Register */
/*! @{ */
#define LPUART_GLOBAL_RST_MASK                   (0x2U)
#define LPUART_GLOBAL_RST_SHIFT                  (1U)
/*! RST - Software Reset
 *  0b0..Module is not reset.
 *  0b1..Module is reset.
 */
#define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
/*! @} */

/*! @name PINCFG - LPUART Pin Configuration Register */
/*! @{ */
#define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
#define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
/*! TRGSEL - Trigger Select
 *  0b00..Input trigger is disabled.
 *  0b01..Input trigger is used instead of RXD pin input.
 *  0b10..Input trigger is used instead of CTS_B pin input.
 *  0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger.
 */
#define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
/*! @} */

/*! @name BAUD - LPUART Baud Rate Register */
/*! @{ */
#define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
#define LPUART_BAUD_SBR_SHIFT                    (0U)
#define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
#define LPUART_BAUD_SBNS_MASK                    (0x2000U)
#define LPUART_BAUD_SBNS_SHIFT                   (13U)
/*! SBNS - Stop Bit Number Select
 *  0b0..One stop bit.
 *  0b1..Two stop bits.
 */
#define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
#define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
#define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
/*! RXEDGIE - RX Input Active Edge Interrupt Enable
 *  0b0..Hardware interrupts from STAT[RXEDGIF] are disabled.
 *  0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.
 */
#define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
#define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
#define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
/*! LBKDIE - LIN Break Detect Interrupt Enable
 *  0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling).
 *  0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1.
 */
#define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
#define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
#define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
/*! RESYNCDIS - Resynchronization Disable
 *  0b0..Resynchronization during received data word is supported
 *  0b1..Resynchronization during received data word is disabled
 */
#define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
#define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
#define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
/*! BOTHEDGE - Both Edge Sampling
 *  0b0..Receiver samples input data using the rising edge of the baud rate clock.
 *  0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
 */
#define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
#define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
#define LPUART_BAUD_MATCFG_SHIFT                 (18U)
/*! MATCFG - Match Configuration
 *  0b00..Address Match Wakeup
 *  0b01..Idle Match Wakeup
 *  0b10..Match On and Match Off
 */
#define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
#define LPUART_BAUD_RIDMAE_MASK                  (0x100000U)
#define LPUART_BAUD_RIDMAE_SHIFT                 (20U)
/*! RIDMAE - Receiver Idle DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define LPUART_BAUD_RIDMAE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
#define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
#define LPUART_BAUD_RDMAE_SHIFT                  (21U)
/*! RDMAE - Receiver Full DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
#define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
#define LPUART_BAUD_TDMAE_SHIFT                  (23U)
/*! TDMAE - Transmitter DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
#define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
#define LPUART_BAUD_OSR_SHIFT                    (24U)
/*! OSR - Oversampling Ratio
 *  0b00000..Writing 0 to this field will result in an oversampling ratio of 16
 *  0b00001..Reserved
 *  0b00010..Reserved
 *  0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set.
 *  0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set.
 *  0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set.
 *  0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set.
 *  0b00111..Oversampling ratio of 8.
 *  0b01000..Oversampling ratio of 9.
 *  0b01001..Oversampling ratio of 10.
 *  0b01010..Oversampling ratio of 11.
 *  0b01011..Oversampling ratio of 12.
 *  0b01100..Oversampling ratio of 13.
 *  0b01101..Oversampling ratio of 14.
 *  0b01110..Oversampling ratio of 15.
 *  0b01111..Oversampling ratio of 16.
 *  0b10000..Oversampling ratio of 17.
 *  0b10001..Oversampling ratio of 18.
 *  0b10010..Oversampling ratio of 19.
 *  0b10011..Oversampling ratio of 20.
 *  0b10100..Oversampling ratio of 21.
 *  0b10101..Oversampling ratio of 22.
 *  0b10110..Oversampling ratio of 23.
 *  0b10111..Oversampling ratio of 24.
 *  0b11000..Oversampling ratio of 25.
 *  0b11001..Oversampling ratio of 26.
 *  0b11010..Oversampling ratio of 27.
 *  0b11011..Oversampling ratio of 28.
 *  0b11100..Oversampling ratio of 29.
 *  0b11101..Oversampling ratio of 30.
 *  0b11110..Oversampling ratio of 31.
 *  0b11111..Oversampling ratio of 32.
 */
#define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
#define LPUART_BAUD_M10_MASK                     (0x20000000U)
#define LPUART_BAUD_M10_SHIFT                    (29U)
/*! M10 - 10-bit Mode select
 *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters.
 *  0b1..Receiver and transmitter use 10-bit data characters.
 */
#define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
#define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
#define LPUART_BAUD_MAEN2_SHIFT                  (30U)
/*! MAEN2 - Match Address Mode Enable 2
 *  0b0..Normal operation.
 *  0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
 */
#define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
#define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
#define LPUART_BAUD_MAEN1_SHIFT                  (31U)
/*! MAEN1 - Match Address Mode Enable 1
 *  0b0..Normal operation.
 *  0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
 */
#define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
/*! @} */

/*! @name STAT - LPUART Status Register */
/*! @{ */
#define LPUART_STAT_MA2F_MASK                    (0x4000U)
#define LPUART_STAT_MA2F_SHIFT                   (14U)
/*! MA2F - Match 2 Flag
 *  0b0..Received data is not equal to MA2
 *  0b1..Received data is equal to MA2
 */
#define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
#define LPUART_STAT_MA1F_MASK                    (0x8000U)
#define LPUART_STAT_MA1F_SHIFT                   (15U)
/*! MA1F - Match 1 Flag
 *  0b0..Received data is not equal to MA1
 *  0b1..Received data is equal to MA1
 */
#define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
#define LPUART_STAT_PF_MASK                      (0x10000U)
#define LPUART_STAT_PF_SHIFT                     (16U)
/*! PF - Parity Error Flag
 *  0b0..No parity error.
 *  0b1..Parity error.
 */
#define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
#define LPUART_STAT_FE_MASK                      (0x20000U)
#define LPUART_STAT_FE_SHIFT                     (17U)
/*! FE - Framing Error Flag
 *  0b0..No framing error detected. This does not guarantee the framing is correct.
 *  0b1..Framing error.
 */
#define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
#define LPUART_STAT_NF_MASK                      (0x40000U)
#define LPUART_STAT_NF_SHIFT                     (18U)
/*! NF - Noise Flag
 *  0b0..No noise detected.
 *  0b1..Noise detected in the received character in the DATA register.
 */
#define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
#define LPUART_STAT_OR_MASK                      (0x80000U)
#define LPUART_STAT_OR_SHIFT                     (19U)
/*! OR - Receiver Overrun Flag
 *  0b0..No overrun.
 *  0b1..Receive overrun (new LPUART data lost).
 */
#define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
#define LPUART_STAT_IDLE_MASK                    (0x100000U)
#define LPUART_STAT_IDLE_SHIFT                   (20U)
/*! IDLE - Idle Line Flag
 *  0b0..No idle line detected.
 *  0b1..Idle line was detected.
 */
#define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
#define LPUART_STAT_RDRF_MASK                    (0x200000U)
#define LPUART_STAT_RDRF_SHIFT                   (21U)
/*! RDRF - Receive Data Register Full Flag
 *  0b0..Receive data buffer empty.
 *  0b1..Receive data buffer full.
 */
#define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
#define LPUART_STAT_TC_MASK                      (0x400000U)
#define LPUART_STAT_TC_SHIFT                     (22U)
/*! TC - Transmission Complete Flag
 *  0b0..Transmitter active (sending data, a preamble, or a break).
 *  0b1..Transmitter idle (transmission activity complete).
 */
#define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
#define LPUART_STAT_TDRE_MASK                    (0x800000U)
#define LPUART_STAT_TDRE_SHIFT                   (23U)
/*! TDRE - Transmit Data Register Empty Flag
 *  0b0..Transmit data buffer full.
 *  0b1..Transmit data buffer empty.
 */
#define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
#define LPUART_STAT_RAF_MASK                     (0x1000000U)
#define LPUART_STAT_RAF_SHIFT                    (24U)
/*! RAF - Receiver Active Flag
 *  0b0..LPUART receiver idle waiting for a start bit.
 *  0b1..LPUART receiver active (RXD input not idle).
 */
#define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
#define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
#define LPUART_STAT_LBKDE_SHIFT                  (25U)
/*! LBKDE - LIN Break Detection Enable
 *  0b0..LIN break detect is disabled, normal break character can be detected.
 *  0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
 */
#define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
#define LPUART_STAT_BRK13_MASK                   (0x4000000U)
#define LPUART_STAT_BRK13_SHIFT                  (26U)
/*! BRK13 - Break Character Generation Length
 *  0b0..Break character is transmitted with length of 9 to 13 bit times.
 *  0b1..Break character is transmitted with length of 12 to 15 bit times.
 */
#define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
#define LPUART_STAT_RWUID_MASK                   (0x8000000U)
#define LPUART_STAT_RWUID_SHIFT                  (27U)
/*! RWUID - Receive Wake Up Idle Detect
 *  0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match.
 *  0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match.
 */
#define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
#define LPUART_STAT_RXINV_MASK                   (0x10000000U)
#define LPUART_STAT_RXINV_SHIFT                  (28U)
/*! RXINV - Receive Data Inversion
 *  0b0..Receive data not inverted.
 *  0b1..Receive data inverted.
 */
#define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
#define LPUART_STAT_MSBF_MASK                    (0x20000000U)
#define LPUART_STAT_MSBF_SHIFT                   (29U)
/*! MSBF - MSB First
 *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
 *  0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
 */
#define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
#define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
#define LPUART_STAT_RXEDGIF_SHIFT                (30U)
/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
 *  0b0..No active edge on the receive pin has occurred.
 *  0b1..An active edge on the receive pin has occurred.
 */
#define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
#define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
#define LPUART_STAT_LBKDIF_SHIFT                 (31U)
/*! LBKDIF - LIN Break Detect Interrupt Flag
 *  0b0..No LIN break character has been detected.
 *  0b1..LIN break character has been detected.
 */
#define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
/*! @} */

/*! @name CTRL - LPUART Control Register */
/*! @{ */
#define LPUART_CTRL_PT_MASK                      (0x1U)
#define LPUART_CTRL_PT_SHIFT                     (0U)
/*! PT - Parity Type
 *  0b0..Even parity.
 *  0b1..Odd parity.
 */
#define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
#define LPUART_CTRL_PE_MASK                      (0x2U)
#define LPUART_CTRL_PE_SHIFT                     (1U)
/*! PE - Parity Enable
 *  0b0..No hardware parity generation or checking.
 *  0b1..Parity enabled.
 */
#define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
#define LPUART_CTRL_ILT_MASK                     (0x4U)
#define LPUART_CTRL_ILT_SHIFT                    (2U)
/*! ILT - Idle Line Type Select
 *  0b0..Idle character bit count starts after start bit.
 *  0b1..Idle character bit count starts after stop bit.
 */
#define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
#define LPUART_CTRL_WAKE_MASK                    (0x8U)
#define LPUART_CTRL_WAKE_SHIFT                   (3U)
/*! WAKE - Receiver Wakeup Method Select
 *  0b0..Configures RWU for idle-line wakeup.
 *  0b1..Configures RWU with address-mark wakeup.
 */
#define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
#define LPUART_CTRL_M_MASK                       (0x10U)
#define LPUART_CTRL_M_SHIFT                      (4U)
/*! M - 9-Bit or 8-Bit Mode Select
 *  0b0..Receiver and transmitter use 8-bit data characters.
 *  0b1..Receiver and transmitter use 9-bit data characters.
 */
#define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
#define LPUART_CTRL_RSRC_MASK                    (0x20U)
#define LPUART_CTRL_RSRC_SHIFT                   (5U)
/*! RSRC - Receiver Source Select
 *  0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.
 *  0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.
 */
#define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
#define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
#define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
/*! DOZEEN - Doze Enable
 *  0b0..LPUART is enabled in Doze mode.
 *  0b1..LPUART is disabled in Doze mode.
 */
#define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
#define LPUART_CTRL_LOOPS_MASK                   (0x80U)
#define LPUART_CTRL_LOOPS_SHIFT                  (7U)
/*! LOOPS - Loop Mode Select
 *  0b0..Normal operation - RXD and TXD use separate pins.
 *  0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
 */
#define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
#define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
#define LPUART_CTRL_IDLECFG_SHIFT                (8U)
/*! IDLECFG - Idle Configuration
 *  0b000..1 idle character
 *  0b001..2 idle characters
 *  0b010..4 idle characters
 *  0b011..8 idle characters
 *  0b100..16 idle characters
 *  0b101..32 idle characters
 *  0b110..64 idle characters
 *  0b111..128 idle characters
 */
#define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
#define LPUART_CTRL_M7_MASK                      (0x800U)
#define LPUART_CTRL_M7_SHIFT                     (11U)
/*! M7 - 7-Bit Mode Select
 *  0b0..Receiver and transmitter use 8-bit to 10-bit data characters.
 *  0b1..Receiver and transmitter use 7-bit data characters.
 */
#define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
#define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
#define LPUART_CTRL_MA2IE_SHIFT                  (14U)
/*! MA2IE - Match 2 Interrupt Enable
 *  0b0..MA2F interrupt disabled
 *  0b1..MA2F interrupt enabled
 */
#define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
#define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
#define LPUART_CTRL_MA1IE_SHIFT                  (15U)
/*! MA1IE - Match 1 Interrupt Enable
 *  0b0..MA1F interrupt disabled
 *  0b1..MA1F interrupt enabled
 */
#define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
#define LPUART_CTRL_SBK_MASK                     (0x10000U)
#define LPUART_CTRL_SBK_SHIFT                    (16U)
/*! SBK - Send Break
 *  0b0..Normal transmitter operation.
 *  0b1..Queue break character(s) to be sent.
 */
#define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
#define LPUART_CTRL_RWU_MASK                     (0x20000U)
#define LPUART_CTRL_RWU_SHIFT                    (17U)
/*! RWU - Receiver Wakeup Control
 *  0b0..Normal receiver operation.
 *  0b1..LPUART receiver in standby waiting for wakeup condition.
 */
#define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
#define LPUART_CTRL_RE_MASK                      (0x40000U)
#define LPUART_CTRL_RE_SHIFT                     (18U)
/*! RE - Receiver Enable
 *  0b0..Receiver disabled.
 *  0b1..Receiver enabled.
 */
#define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
#define LPUART_CTRL_TE_MASK                      (0x80000U)
#define LPUART_CTRL_TE_SHIFT                     (19U)
/*! TE - Transmitter Enable
 *  0b0..Transmitter disabled.
 *  0b1..Transmitter enabled.
 */
#define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
#define LPUART_CTRL_ILIE_MASK                    (0x100000U)
#define LPUART_CTRL_ILIE_SHIFT                   (20U)
/*! ILIE - Idle Line Interrupt Enable
 *  0b0..Hardware interrupts from IDLE disabled; use polling.
 *  0b1..Hardware interrupt requested when IDLE flag is 1.
 */
#define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
#define LPUART_CTRL_RIE_MASK                     (0x200000U)
#define LPUART_CTRL_RIE_SHIFT                    (21U)
/*! RIE - Receiver Interrupt Enable
 *  0b0..Hardware interrupts from RDRF disabled; use polling.
 *  0b1..Hardware interrupt requested when RDRF flag is 1.
 */
#define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
#define LPUART_CTRL_TCIE_MASK                    (0x400000U)
#define LPUART_CTRL_TCIE_SHIFT                   (22U)
/*! TCIE - Transmission Complete Interrupt Enable for
 *  0b0..Hardware interrupts from TC disabled; use polling.
 *  0b1..Hardware interrupt requested when TC flag is 1.
 */
#define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
#define LPUART_CTRL_TIE_MASK                     (0x800000U)
#define LPUART_CTRL_TIE_SHIFT                    (23U)
/*! TIE - Transmit Interrupt Enable
 *  0b0..Hardware interrupts from TDRE disabled; use polling.
 *  0b1..Hardware interrupt requested when TDRE flag is 1.
 */
#define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
#define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
#define LPUART_CTRL_PEIE_SHIFT                   (24U)
/*! PEIE - Parity Error Interrupt Enable
 *  0b0..PF interrupts disabled; use polling).
 *  0b1..Hardware interrupt requested when PF is set.
 */
#define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
#define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
#define LPUART_CTRL_FEIE_SHIFT                   (25U)
/*! FEIE - Framing Error Interrupt Enable
 *  0b0..FE interrupts disabled; use polling.
 *  0b1..Hardware interrupt requested when FE is set.
 */
#define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
#define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
#define LPUART_CTRL_NEIE_SHIFT                   (26U)
/*! NEIE - Noise Error Interrupt Enable
 *  0b0..NF interrupts disabled; use polling.
 *  0b1..Hardware interrupt requested when NF is set.
 */
#define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
#define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
#define LPUART_CTRL_ORIE_SHIFT                   (27U)
/*! ORIE - Overrun Interrupt Enable
 *  0b0..OR interrupts disabled; use polling.
 *  0b1..Hardware interrupt requested when OR is set.
 */
#define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
#define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
#define LPUART_CTRL_TXINV_SHIFT                  (28U)
/*! TXINV - Transmit Data Inversion
 *  0b0..Transmit data not inverted.
 *  0b1..Transmit data inverted.
 */
#define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
#define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
#define LPUART_CTRL_TXDIR_SHIFT                  (29U)
/*! TXDIR - TXD Pin Direction in Single-Wire Mode
 *  0b0..TXD pin is an input in single-wire mode.
 *  0b1..TXD pin is an output in single-wire mode.
 */
#define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
#define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
#define LPUART_CTRL_R9T8_SHIFT                   (30U)
#define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
#define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
#define LPUART_CTRL_R8T9_SHIFT                   (31U)
#define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
/*! @} */

/*! @name DATA - LPUART Data Register */
/*! @{ */
#define LPUART_DATA_R0T0_MASK                    (0x1U)
#define LPUART_DATA_R0T0_SHIFT                   (0U)
#define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
#define LPUART_DATA_R1T1_MASK                    (0x2U)
#define LPUART_DATA_R1T1_SHIFT                   (1U)
#define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
#define LPUART_DATA_R2T2_MASK                    (0x4U)
#define LPUART_DATA_R2T2_SHIFT                   (2U)
#define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
#define LPUART_DATA_R3T3_MASK                    (0x8U)
#define LPUART_DATA_R3T3_SHIFT                   (3U)
#define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
#define LPUART_DATA_R4T4_MASK                    (0x10U)
#define LPUART_DATA_R4T4_SHIFT                   (4U)
#define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
#define LPUART_DATA_R5T5_MASK                    (0x20U)
#define LPUART_DATA_R5T5_SHIFT                   (5U)
#define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
#define LPUART_DATA_R6T6_MASK                    (0x40U)
#define LPUART_DATA_R6T6_SHIFT                   (6U)
#define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
#define LPUART_DATA_R7T7_MASK                    (0x80U)
#define LPUART_DATA_R7T7_SHIFT                   (7U)
#define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
#define LPUART_DATA_R8T8_MASK                    (0x100U)
#define LPUART_DATA_R8T8_SHIFT                   (8U)
#define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
#define LPUART_DATA_R9T9_MASK                    (0x200U)
#define LPUART_DATA_R9T9_SHIFT                   (9U)
#define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
#define LPUART_DATA_IDLINE_MASK                  (0x800U)
#define LPUART_DATA_IDLINE_SHIFT                 (11U)
/*! IDLINE - Idle Line
 *  0b0..Receiver was not idle before receiving this character.
 *  0b1..Receiver was idle before receiving this character.
 */
#define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
#define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
#define LPUART_DATA_RXEMPT_SHIFT                 (12U)
/*! RXEMPT - Receive Buffer Empty
 *  0b0..Receive buffer contains valid data.
 *  0b1..Receive buffer is empty, data returned on read is not valid.
 */
#define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
#define LPUART_DATA_FRETSC_MASK                  (0x2000U)
#define LPUART_DATA_FRETSC_SHIFT                 (13U)
/*! FRETSC - Frame Error / Transmit Special Character
 *  0b0..The dataword was received without a frame error on read, or transmit a normal character on write.
 *  0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit.
 */
#define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
#define LPUART_DATA_PARITYE_MASK                 (0x4000U)
#define LPUART_DATA_PARITYE_SHIFT                (14U)
/*! PARITYE - PARITYE
 *  0b0..The dataword was received without a parity error.
 *  0b1..The dataword was received with a parity error.
 */
#define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
#define LPUART_DATA_NOISY_MASK                   (0x8000U)
#define LPUART_DATA_NOISY_SHIFT                  (15U)
/*! NOISY - NOISY
 *  0b0..The dataword was received without noise.
 *  0b1..The data was received with noise.
 */
#define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
/*! @} */

/*! @name MATCH - LPUART Match Address Register */
/*! @{ */
#define LPUART_MATCH_MA1_MASK                    (0x3FFU)
#define LPUART_MATCH_MA1_SHIFT                   (0U)
#define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
#define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
#define LPUART_MATCH_MA2_SHIFT                   (16U)
#define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
/*! @} */

/*! @name MODIR - LPUART Modem IrDA Register */
/*! @{ */
#define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
#define LPUART_MODIR_TXCTSE_SHIFT                (0U)
/*! TXCTSE - Transmitter clear-to-send enable
 *  0b0..CTS has no effect on the transmitter.
 *  0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
 */
#define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
#define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
#define LPUART_MODIR_TXRTSE_SHIFT                (1U)
/*! TXRTSE - Transmitter request-to-send enable
 *  0b0..The transmitter has no effect on RTS.
 *  0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.
 */
#define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
#define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
#define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
/*! TXRTSPOL - Transmitter request-to-send polarity
 *  0b0..Transmitter RTS is active low.
 *  0b1..Transmitter RTS is active high.
 */
#define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
#define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
#define LPUART_MODIR_RXRTSE_SHIFT                (3U)
/*! RXRTSE - Receiver request-to-send enable
 *  0b0..The receiver has no effect on RTS.
 */
#define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
#define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
#define LPUART_MODIR_TXCTSC_SHIFT                (4U)
/*! TXCTSC - Transmit CTS Configuration
 *  0b0..CTS input is sampled at the start of each character.
 *  0b1..CTS input is sampled when the transmitter is idle.
 */
#define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
#define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
#define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
/*! TXCTSSRC - Transmit CTS Source
 *  0b0..CTS input is the CTS_B pin.
 *  0b1..CTS input is the inverted Receiver Match result.
 */
#define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
#define LPUART_MODIR_RTSWATER_MASK               (0x3F00U)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
#define LPUART_MODIR_RTSWATER_SHIFT              (8U)
#define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
#define LPUART_MODIR_TNP_MASK                    (0x30000U)
#define LPUART_MODIR_TNP_SHIFT                   (16U)
/*! TNP - Transmitter narrow pulse
 *  0b00..1/OSR.
 *  0b01..2/OSR.
 *  0b10..3/OSR.
 *  0b11..4/OSR.
 */
#define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
#define LPUART_MODIR_IREN_MASK                   (0x40000U)
#define LPUART_MODIR_IREN_SHIFT                  (18U)
/*! IREN - Infrared enable
 *  0b0..IR disabled.
 *  0b1..IR enabled.
 */
#define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
/*! @} */

/*! @name FIFO - LPUART FIFO Register */
/*! @{ */
#define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
#define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
/*! RXFIFOSIZE - Receive FIFO Buffer Depth
 *  0b000..Receive FIFO/Buffer depth = 1 dataword.
 *  0b001..Receive FIFO/Buffer depth = 4 datawords.
 *  0b010..Receive FIFO/Buffer depth = 8 datawords.
 *  0b011..Receive FIFO/Buffer depth = 16 datawords.
 *  0b100..Receive FIFO/Buffer depth = 32 datawords.
 *  0b101..Receive FIFO/Buffer depth = 64 datawords.
 *  0b110..Receive FIFO/Buffer depth = 128 datawords.
 *  0b111..Receive FIFO/Buffer depth = 256 datawords.
 */
#define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
#define LPUART_FIFO_RXFE_MASK                    (0x8U)
#define LPUART_FIFO_RXFE_SHIFT                   (3U)
/*! RXFE - Receive FIFO Enable
 *  0b0..Receive FIFO is not enabled. Buffer is depth 1.
 *  0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
 */
#define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
#define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
#define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
/*! TXFIFOSIZE - Transmit FIFO Buffer Depth
 *  0b000..Transmit FIFO/Buffer depth = 1 dataword.
 *  0b001..Transmit FIFO/Buffer depth = 4 datawords.
 *  0b010..Transmit FIFO/Buffer depth = 8 datawords.
 *  0b011..Transmit FIFO/Buffer depth = 16 datawords.
 *  0b100..Transmit FIFO/Buffer depth = 32 datawords.
 *  0b101..Transmit FIFO/Buffer depth = 64 datawords.
 *  0b110..Transmit FIFO/Buffer depth = 128 datawords.
 *  0b111..Transmit FIFO/Buffer depth = 256 datawords
 */
#define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
#define LPUART_FIFO_TXFE_MASK                    (0x80U)
#define LPUART_FIFO_TXFE_SHIFT                   (7U)
/*! TXFE - Transmit FIFO Enable
 *  0b0..Transmit FIFO is not enabled. Buffer is depth 1.
 *  0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
 */
#define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
#define LPUART_FIFO_RXUFE_MASK                   (0x100U)
#define LPUART_FIFO_RXUFE_SHIFT                  (8U)
/*! RXUFE - Receive FIFO Underflow Interrupt Enable
 *  0b0..RXUF flag does not generate an interrupt to the host.
 *  0b1..RXUF flag generates an interrupt to the host.
 */
#define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
#define LPUART_FIFO_TXOFE_MASK                   (0x200U)
#define LPUART_FIFO_TXOFE_SHIFT                  (9U)
/*! TXOFE - Transmit FIFO Overflow Interrupt Enable
 *  0b0..TXOF flag does not generate an interrupt to the host.
 *  0b1..TXOF flag generates an interrupt to the host.
 */
#define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
#define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
#define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
/*! RXIDEN - Receiver Idle Empty Enable
 *  0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
 *  0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
 *  0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
 *  0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
 *  0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
 *  0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
 *  0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
 *  0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
 */
#define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
#define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
#define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
/*! RXFLUSH - Receive FIFO/Buffer Flush
 *  0b0..No flush operation occurs.
 *  0b1..All data in the receive FIFO/buffer is cleared out.
 */
#define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
#define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
#define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
/*! TXFLUSH - Transmit FIFO/Buffer Flush
 *  0b0..No flush operation occurs.
 *  0b1..All data in the transmit FIFO/Buffer is cleared out.
 */
#define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
#define LPUART_FIFO_RXUF_MASK                    (0x10000U)
#define LPUART_FIFO_RXUF_SHIFT                   (16U)
/*! RXUF - Receiver Buffer Underflow Flag
 *  0b0..No receive buffer underflow has occurred since the last time the flag was cleared.
 *  0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared.
 */
#define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
#define LPUART_FIFO_TXOF_MASK                    (0x20000U)
#define LPUART_FIFO_TXOF_SHIFT                   (17U)
/*! TXOF - Transmitter Buffer Overflow Flag
 *  0b0..No transmit buffer overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared.
 */
#define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
#define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
#define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
/*! RXEMPT - Receive Buffer/FIFO Empty
 *  0b0..Receive buffer is not empty.
 *  0b1..Receive buffer is empty.
 */
#define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
#define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
#define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
/*! TXEMPT - Transmit Buffer/FIFO Empty
 *  0b0..Transmit buffer is not empty.
 *  0b1..Transmit buffer is empty.
 */
#define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
/*! @} */

/*! @name WATER - LPUART Watermark Register */
/*! @{ */
#define LPUART_WATER_TXWATER_MASK                (0x3FU)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
#define LPUART_WATER_TXWATER_SHIFT               (0U)
#define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
#define LPUART_WATER_TXCOUNT_MASK                (0x7F00U)  /* Merged from fields with different position or width, of widths (6, 7), largest definition used */
#define LPUART_WATER_TXCOUNT_SHIFT               (8U)
#define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)  /* Merged from fields with different position or width, of widths (6, 7), largest definition used */
#define LPUART_WATER_RXWATER_MASK                (0x3F0000U)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
#define LPUART_WATER_RXWATER_SHIFT               (16U)
#define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)  /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
#define LPUART_WATER_RXCOUNT_MASK                (0x7F000000U)  /* Merged from fields with different position or width, of widths (6, 7), largest definition used */
#define LPUART_WATER_RXCOUNT_SHIFT               (24U)
#define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)  /* Merged from fields with different position or width, of widths (6, 7), largest definition used */
/*! @} */


/*!
 * @}
 */ /* end of group LPUART_Register_Masks */


/* LPUART - Peripheral instance base addresses */
/** Peripheral CM4_0__LPUART base address */
#define CM4_0__LPUART_BASE                       (0x37220000u)
/** Peripheral CM4_0__LPUART base pointer */
#define CM4_0__LPUART                            ((LPUART_Type *)CM4_0__LPUART_BASE)
/** Peripheral CM4_1__LPUART base address */
#define CM4_1__LPUART_BASE                       (0x41220000u)
/** Peripheral CM4_1__LPUART base pointer */
#define CM4_1__LPUART                            ((LPUART_Type *)CM4_1__LPUART_BASE)
/** Peripheral DMA__LPUART0 base address */
#define DMA__LPUART0_BASE                        (0x5A060000u)
/** Peripheral DMA__LPUART0 base pointer */
#define DMA__LPUART0                             ((LPUART_Type *)DMA__LPUART0_BASE)
/** Peripheral DMA__LPUART1 base address */
#define DMA__LPUART1_BASE                        (0x5A070000u)
/** Peripheral DMA__LPUART1 base pointer */
#define DMA__LPUART1                             ((LPUART_Type *)DMA__LPUART1_BASE)
/** Peripheral DMA__LPUART2 base address */
#define DMA__LPUART2_BASE                        (0x5A080000u)
/** Peripheral DMA__LPUART2 base pointer */
#define DMA__LPUART2                             ((LPUART_Type *)DMA__LPUART2_BASE)
/** Peripheral DMA__LPUART3 base address */
#define DMA__LPUART3_BASE                        (0x5A090000u)
/** Peripheral DMA__LPUART3 base pointer */
#define DMA__LPUART3                             ((LPUART_Type *)DMA__LPUART3_BASE)
/** Peripheral DMA__LPUART4 base address */
#define DMA__LPUART4_BASE                        (0x5A0A0000u)
/** Peripheral DMA__LPUART4 base pointer */
#define DMA__LPUART4                             ((LPUART_Type *)DMA__LPUART4_BASE)
/** Peripheral SCU__LPUART base address */
#define SCU__LPUART_BASE                         (0x33220000u)
/** Peripheral SCU__LPUART base pointer */
#define SCU__LPUART                              ((LPUART_Type *)SCU__LPUART_BASE)
/** Array initializer of LPUART peripheral base addresses */
#define LPUART_BASE_ADDRS                        { CM4_0__LPUART_BASE, CM4_1__LPUART_BASE, DMA__LPUART0_BASE, DMA__LPUART1_BASE, DMA__LPUART2_BASE, DMA__LPUART3_BASE, DMA__LPUART4_BASE, SCU__LPUART_BASE }
/** Array initializer of LPUART peripheral base pointers */
#define LPUART_BASE_PTRS                         { CM4_0__LPUART, CM4_1__LPUART, DMA__LPUART0, DMA__LPUART1, DMA__LPUART2, DMA__LPUART3, DMA__LPUART4, SCU__LPUART }
/** Interrupt vectors for the LPUART peripheral type */
#define LPUART_RX_TX_IRQS                        { NotAvail_IRQn, M4_1_LPUART_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }

/*!
 * @}
 */ /* end of group LPUART_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO0_Peripheral_Access_Layer LSIO_LPCG_GPIO0 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_GPIO0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_GPIO0_0;                      /**< na, offset: 0x0 */
} LSIO_LPCG_GPIO0_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO0_Register_Masks LSIO_LPCG_GPIO0 Register Masks
 * @{
 */

/*! @name LPCG_GPIO0_0 - na */
/*! @{ */
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15_MASK (0xFFFFU)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15_SHIFT (0U)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_0_15_MASK)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_18_18_MASK)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_gpio0_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO0_LPCG_GPIO0_0_LPCG_GPIO0_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO0_Register_Masks */


/* LSIO_LPCG_GPIO0 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_GPIO0 base address */
#define LSIO__LPCG_GPIO0_BASE                    (0x5D480000u)
/** Peripheral LSIO__LPCG_GPIO0 base pointer */
#define LSIO__LPCG_GPIO0                         ((LSIO_LPCG_GPIO0_Type *)LSIO__LPCG_GPIO0_BASE)
/** Array initializer of LSIO_LPCG_GPIO0 peripheral base addresses */
#define LSIO_LPCG_GPIO0_BASE_ADDRS               { LSIO__LPCG_GPIO0_BASE }
/** Array initializer of LSIO_LPCG_GPIO0 peripheral base pointers */
#define LSIO_LPCG_GPIO0_BASE_PTRS                { LSIO__LPCG_GPIO0 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO1_Peripheral_Access_Layer LSIO_LPCG_GPIO1 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_GPIO1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_GPIO1_0;                      /**< na, offset: 0x0 */
} LSIO_LPCG_GPIO1_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO1_Register_Masks LSIO_LPCG_GPIO1 Register Masks
 * @{
 */

/*! @name LPCG_GPIO1_0 - na */
/*! @{ */
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15_MASK (0xFFFFU)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15_SHIFT (0U)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_0_15_MASK)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_18_18_MASK)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_gpio1_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO1_LPCG_GPIO1_0_LPCG_GPIO1_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO1_Register_Masks */


/* LSIO_LPCG_GPIO1 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_GPIO1 base address */
#define LSIO__LPCG_GPIO1_BASE                    (0x5D490000u)
/** Peripheral LSIO__LPCG_GPIO1 base pointer */
#define LSIO__LPCG_GPIO1                         ((LSIO_LPCG_GPIO1_Type *)LSIO__LPCG_GPIO1_BASE)
/** Array initializer of LSIO_LPCG_GPIO1 peripheral base addresses */
#define LSIO_LPCG_GPIO1_BASE_ADDRS               { LSIO__LPCG_GPIO1_BASE }
/** Array initializer of LSIO_LPCG_GPIO1 peripheral base pointers */
#define LSIO_LPCG_GPIO1_BASE_PTRS                { LSIO__LPCG_GPIO1 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO2_Peripheral_Access_Layer LSIO_LPCG_GPIO2 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_GPIO2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_GPIO2_0;                      /**< na, offset: 0x0 */
} LSIO_LPCG_GPIO2_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO2_Register_Masks LSIO_LPCG_GPIO2 Register Masks
 * @{
 */

/*! @name LPCG_GPIO2_0 - na */
/*! @{ */
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15_MASK (0xFFFFU)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15_SHIFT (0U)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_0_15_MASK)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_18_18_MASK)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_gpio2_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO2_LPCG_GPIO2_0_LPCG_GPIO2_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO2_Register_Masks */


/* LSIO_LPCG_GPIO2 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_GPIO2 base address */
#define LSIO__LPCG_GPIO2_BASE                    (0x5D4A0000u)
/** Peripheral LSIO__LPCG_GPIO2 base pointer */
#define LSIO__LPCG_GPIO2                         ((LSIO_LPCG_GPIO2_Type *)LSIO__LPCG_GPIO2_BASE)
/** Array initializer of LSIO_LPCG_GPIO2 peripheral base addresses */
#define LSIO_LPCG_GPIO2_BASE_ADDRS               { LSIO__LPCG_GPIO2_BASE }
/** Array initializer of LSIO_LPCG_GPIO2 peripheral base pointers */
#define LSIO_LPCG_GPIO2_BASE_PTRS                { LSIO__LPCG_GPIO2 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO3_Peripheral_Access_Layer LSIO_LPCG_GPIO3 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_GPIO3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_GPIO3_0;                      /**< na, offset: 0x0 */
} LSIO_LPCG_GPIO3_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO3_Register_Masks LSIO_LPCG_GPIO3 Register Masks
 * @{
 */

/*! @name LPCG_GPIO3_0 - na */
/*! @{ */
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15_MASK (0xFFFFU)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15_SHIFT (0U)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_0_15_MASK)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_18_18_MASK)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_gpio3_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO3_LPCG_GPIO3_0_LPCG_GPIO3_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO3_Register_Masks */


/* LSIO_LPCG_GPIO3 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_GPIO3 base address */
#define LSIO__LPCG_GPIO3_BASE                    (0x5D4B0000u)
/** Peripheral LSIO__LPCG_GPIO3 base pointer */
#define LSIO__LPCG_GPIO3                         ((LSIO_LPCG_GPIO3_Type *)LSIO__LPCG_GPIO3_BASE)
/** Array initializer of LSIO_LPCG_GPIO3 peripheral base addresses */
#define LSIO_LPCG_GPIO3_BASE_ADDRS               { LSIO__LPCG_GPIO3_BASE }
/** Array initializer of LSIO_LPCG_GPIO3 peripheral base pointers */
#define LSIO_LPCG_GPIO3_BASE_PTRS                { LSIO__LPCG_GPIO3 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO4 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO4_Peripheral_Access_Layer LSIO_LPCG_GPIO4 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_GPIO4 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_GPIO4_0;                      /**< na, offset: 0x0 */
} LSIO_LPCG_GPIO4_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO4 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO4_Register_Masks LSIO_LPCG_GPIO4 Register Masks
 * @{
 */

/*! @name LPCG_GPIO4_0 - na */
/*! @{ */
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15_MASK (0xFFFFU)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15_SHIFT (0U)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_0_15_MASK)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_18_18_MASK)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_gpio4_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO4_LPCG_GPIO4_0_LPCG_GPIO4_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO4_Register_Masks */


/* LSIO_LPCG_GPIO4 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_GPIO4 base address */
#define LSIO__LPCG_GPIO4_BASE                    (0x5D4C0000u)
/** Peripheral LSIO__LPCG_GPIO4 base pointer */
#define LSIO__LPCG_GPIO4                         ((LSIO_LPCG_GPIO4_Type *)LSIO__LPCG_GPIO4_BASE)
/** Array initializer of LSIO_LPCG_GPIO4 peripheral base addresses */
#define LSIO_LPCG_GPIO4_BASE_ADDRS               { LSIO__LPCG_GPIO4_BASE }
/** Array initializer of LSIO_LPCG_GPIO4 peripheral base pointers */
#define LSIO_LPCG_GPIO4_BASE_PTRS                { LSIO__LPCG_GPIO4 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO4_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO5 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO5_Peripheral_Access_Layer LSIO_LPCG_GPIO5 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_GPIO5 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_GPIO5_0;                      /**< na, offset: 0x0 */
} LSIO_LPCG_GPIO5_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO5 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO5_Register_Masks LSIO_LPCG_GPIO5 Register Masks
 * @{
 */

/*! @name LPCG_GPIO5_0 - na */
/*! @{ */
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15_MASK (0xFFFFU)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15_SHIFT (0U)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_0_15_MASK)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_18_18_MASK)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_gpio5_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO5_LPCG_GPIO5_0_LPCG_GPIO5_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO5_Register_Masks */


/* LSIO_LPCG_GPIO5 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_GPIO5 base address */
#define LSIO__LPCG_GPIO5_BASE                    (0x5D4D0000u)
/** Peripheral LSIO__LPCG_GPIO5 base pointer */
#define LSIO__LPCG_GPIO5                         ((LSIO_LPCG_GPIO5_Type *)LSIO__LPCG_GPIO5_BASE)
/** Array initializer of LSIO_LPCG_GPIO5 peripheral base addresses */
#define LSIO_LPCG_GPIO5_BASE_ADDRS               { LSIO__LPCG_GPIO5_BASE }
/** Array initializer of LSIO_LPCG_GPIO5 peripheral base pointers */
#define LSIO_LPCG_GPIO5_BASE_PTRS                { LSIO__LPCG_GPIO5 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO5_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO6 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO6_Peripheral_Access_Layer LSIO_LPCG_GPIO6 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_GPIO6 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_GPIO6_0;                      /**< na, offset: 0x0 */
} LSIO_LPCG_GPIO6_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO6 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO6_Register_Masks LSIO_LPCG_GPIO6 Register Masks
 * @{
 */

/*! @name LPCG_GPIO6_0 - na */
/*! @{ */
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15_MASK (0xFFFFU)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15_SHIFT (0U)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_0_15_MASK)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_18_18_MASK)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_gpio6_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO6_LPCG_GPIO6_0_LPCG_GPIO6_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO6_Register_Masks */


/* LSIO_LPCG_GPIO6 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_GPIO6 base address */
#define LSIO__LPCG_GPIO6_BASE                    (0x5D4E0000u)
/** Peripheral LSIO__LPCG_GPIO6 base pointer */
#define LSIO__LPCG_GPIO6                         ((LSIO_LPCG_GPIO6_Type *)LSIO__LPCG_GPIO6_BASE)
/** Array initializer of LSIO_LPCG_GPIO6 peripheral base addresses */
#define LSIO_LPCG_GPIO6_BASE_ADDRS               { LSIO__LPCG_GPIO6_BASE }
/** Array initializer of LSIO_LPCG_GPIO6 peripheral base pointers */
#define LSIO_LPCG_GPIO6_BASE_PTRS                { LSIO__LPCG_GPIO6 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO6_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO7 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO7_Peripheral_Access_Layer LSIO_LPCG_GPIO7 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_GPIO7 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_GPIO7_0;                      /**< na, offset: 0x0 */
} LSIO_LPCG_GPIO7_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPIO7 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPIO7_Register_Masks LSIO_LPCG_GPIO7 Register Masks
 * @{
 */

/*! @name LPCG_GPIO7_0 - na */
/*! @{ */
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15_MASK (0xFFFFU)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15_SHIFT (0U)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_0_15_MASK)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_18_18_MASK)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_gpio7_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31_SHIFT)) & LSIO_LPCG_GPIO7_LPCG_GPIO7_0_LPCG_GPIO7_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO7_Register_Masks */


/* LSIO_LPCG_GPIO7 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_GPIO7 base address */
#define LSIO__LPCG_GPIO7_BASE                    (0x5D4F0000u)
/** Peripheral LSIO__LPCG_GPIO7 base pointer */
#define LSIO__LPCG_GPIO7                         ((LSIO_LPCG_GPIO7_Type *)LSIO__LPCG_GPIO7_BASE)
/** Array initializer of LSIO_LPCG_GPIO7 peripheral base addresses */
#define LSIO_LPCG_GPIO7_BASE_ADDRS               { LSIO__LPCG_GPIO7_BASE }
/** Array initializer of LSIO_LPCG_GPIO7 peripheral base pointers */
#define LSIO_LPCG_GPIO7_BASE_PTRS                { LSIO__LPCG_GPIO7 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_GPIO7_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPT0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPT0_Peripheral_Access_Layer LSIO_LPCG_GPT0 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_GPT0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_IPS_SYNC_GPT0_0;              /**< na, offset: 0x0 */
} LSIO_LPCG_GPT0_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPT0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPT0_Register_Masks LSIO_LPCG_GPT0 Register Masks
 * @{
 */

/*! @name LPCG_IPS_SYNC_GPT0_0 - na */
/*! @{ */
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN_MASK (0x1U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN_SHIFT (0U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_HWEN_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN_MASK (0x2U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN_SHIFT (1U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_2_2_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP_MASK (0x8U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP_SHIFT (3U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_STOP_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4_MASK (0x10U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4_SHIFT (4U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_4_4_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN_MASK (0x20U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN_SHIFT (5U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_SWEN_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6_MASK (0x40U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6_SHIFT (6U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_6_6_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP_MASK (0x80U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP_SHIFT (7U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_highfreq_STOP_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8_MASK (0x100U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8_SHIFT (8U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_8_8_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN_MASK (0x200U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN_SHIFT (9U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_SWEN_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10_MASK (0x400U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10_SHIFT (10U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_10_10_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP_MASK (0x800U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP_SHIFT (11U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ccm_ckil_sync_wrapper0_clk_in_STOP_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15_MASK (0xF000U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15_SHIFT (12U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_12_15_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_18_18_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_gpt0_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_20_20_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_SWEN_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_22_22_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_slave_clk_STOP_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN_SHIFT (24U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_HWEN_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN_SHIFT (25U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_SWEN_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_26_26_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP_MASK (0x8000000U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP_SHIFT (27U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_ips_sync_gpt0_ipg_master_clk_STOP_MASK)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT0_LPCG_IPS_SYNC_GPT0_0_LPCG_IPS_SYNC_GPT0_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_GPT0_Register_Masks */


/* LSIO_LPCG_GPT0 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_GPT0 base address */
#define LSIO__LPCG_GPT0_BASE                     (0x5D540000u)
/** Peripheral LSIO__LPCG_GPT0 base pointer */
#define LSIO__LPCG_GPT0                          ((LSIO_LPCG_GPT0_Type *)LSIO__LPCG_GPT0_BASE)
/** Array initializer of LSIO_LPCG_GPT0 peripheral base addresses */
#define LSIO_LPCG_GPT0_BASE_ADDRS                { LSIO__LPCG_GPT0_BASE }
/** Array initializer of LSIO_LPCG_GPT0 peripheral base pointers */
#define LSIO_LPCG_GPT0_BASE_PTRS                 { LSIO__LPCG_GPT0 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_GPT0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPT1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPT1_Peripheral_Access_Layer LSIO_LPCG_GPT1 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_GPT1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_IPS_SYNC_GPT1_0;              /**< na, offset: 0x0 */
} LSIO_LPCG_GPT1_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPT1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPT1_Register_Masks LSIO_LPCG_GPT1 Register Masks
 * @{
 */

/*! @name LPCG_IPS_SYNC_GPT1_0 - na */
/*! @{ */
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN_MASK (0x1U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN_SHIFT (0U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_HWEN_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN_MASK (0x2U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN_SHIFT (1U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_2_2_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP_MASK (0x8U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP_SHIFT (3U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_STOP_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4_MASK (0x10U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4_SHIFT (4U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_4_4_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN_MASK (0x20U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN_SHIFT (5U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_SWEN_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6_MASK (0x40U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6_SHIFT (6U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_6_6_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP_MASK (0x80U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP_SHIFT (7U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_highfreq_STOP_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8_MASK (0x100U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8_SHIFT (8U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_8_8_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN_MASK (0x200U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN_SHIFT (9U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_SWEN_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10_MASK (0x400U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10_SHIFT (10U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_10_10_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP_MASK (0x800U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP_SHIFT (11U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ccm_ckil_sync_wrapper1_clk_in_STOP_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15_MASK (0xF000U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15_SHIFT (12U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_12_15_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_18_18_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_gpt1_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_20_20_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_SWEN_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_22_22_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_slave_clk_STOP_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN_SHIFT (24U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_HWEN_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN_SHIFT (25U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_SWEN_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_26_26_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP_MASK (0x8000000U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP_SHIFT (27U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_ips_sync_gpt1_ipg_master_clk_STOP_MASK)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT1_LPCG_IPS_SYNC_GPT1_0_LPCG_IPS_SYNC_GPT1_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_GPT1_Register_Masks */


/* LSIO_LPCG_GPT1 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_GPT1 base address */
#define LSIO__LPCG_GPT1_BASE                     (0x5D550000u)
/** Peripheral LSIO__LPCG_GPT1 base pointer */
#define LSIO__LPCG_GPT1                          ((LSIO_LPCG_GPT1_Type *)LSIO__LPCG_GPT1_BASE)
/** Array initializer of LSIO_LPCG_GPT1 peripheral base addresses */
#define LSIO_LPCG_GPT1_BASE_ADDRS                { LSIO__LPCG_GPT1_BASE }
/** Array initializer of LSIO_LPCG_GPT1 peripheral base pointers */
#define LSIO_LPCG_GPT1_BASE_PTRS                 { LSIO__LPCG_GPT1 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_GPT1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPT2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPT2_Peripheral_Access_Layer LSIO_LPCG_GPT2 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_GPT2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_IPS_SYNC_GPT2_0;              /**< na, offset: 0x0 */
} LSIO_LPCG_GPT2_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPT2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPT2_Register_Masks LSIO_LPCG_GPT2 Register Masks
 * @{
 */

/*! @name LPCG_IPS_SYNC_GPT2_0 - na */
/*! @{ */
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN_MASK (0x1U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN_SHIFT (0U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_HWEN_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN_MASK (0x2U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN_SHIFT (1U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_2_2_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP_MASK (0x8U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP_SHIFT (3U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_STOP_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4_MASK (0x10U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4_SHIFT (4U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_4_4_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN_MASK (0x20U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN_SHIFT (5U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_SWEN_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6_MASK (0x40U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6_SHIFT (6U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_6_6_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP_MASK (0x80U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP_SHIFT (7U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_highfreq_STOP_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8_MASK (0x100U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8_SHIFT (8U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_8_8_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN_MASK (0x200U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN_SHIFT (9U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_SWEN_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10_MASK (0x400U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10_SHIFT (10U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_10_10_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP_MASK (0x800U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP_SHIFT (11U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ccm_ckil_sync_wrapper2_clk_in_STOP_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15_MASK (0xF000U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15_SHIFT (12U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_12_15_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_18_18_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_gpt2_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_20_20_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_SWEN_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_22_22_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_slave_clk_STOP_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN_SHIFT (24U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_HWEN_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN_SHIFT (25U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_SWEN_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_26_26_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP_MASK (0x8000000U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP_SHIFT (27U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_ips_sync_gpt2_ipg_master_clk_STOP_MASK)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT2_LPCG_IPS_SYNC_GPT2_0_LPCG_IPS_SYNC_GPT2_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_GPT2_Register_Masks */


/* LSIO_LPCG_GPT2 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_GPT2 base address */
#define LSIO__LPCG_GPT2_BASE                     (0x5D560000u)
/** Peripheral LSIO__LPCG_GPT2 base pointer */
#define LSIO__LPCG_GPT2                          ((LSIO_LPCG_GPT2_Type *)LSIO__LPCG_GPT2_BASE)
/** Array initializer of LSIO_LPCG_GPT2 peripheral base addresses */
#define LSIO_LPCG_GPT2_BASE_ADDRS                { LSIO__LPCG_GPT2_BASE }
/** Array initializer of LSIO_LPCG_GPT2 peripheral base pointers */
#define LSIO_LPCG_GPT2_BASE_PTRS                 { LSIO__LPCG_GPT2 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_GPT2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPT3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPT3_Peripheral_Access_Layer LSIO_LPCG_GPT3 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_GPT3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_IPS_SYNC_GPT3_0;              /**< na, offset: 0x0 */
} LSIO_LPCG_GPT3_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPT3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPT3_Register_Masks LSIO_LPCG_GPT3 Register Masks
 * @{
 */

/*! @name LPCG_IPS_SYNC_GPT3_0 - na */
/*! @{ */
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN_MASK (0x1U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN_SHIFT (0U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_HWEN_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN_MASK (0x2U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN_SHIFT (1U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_2_2_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP_MASK (0x8U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP_SHIFT (3U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_STOP_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4_MASK (0x10U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4_SHIFT (4U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_4_4_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN_MASK (0x20U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN_SHIFT (5U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_SWEN_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6_MASK (0x40U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6_SHIFT (6U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_6_6_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP_MASK (0x80U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP_SHIFT (7U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_highfreq_STOP_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8_MASK (0x100U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8_SHIFT (8U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_8_8_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN_MASK (0x200U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN_SHIFT (9U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_SWEN_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10_MASK (0x400U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10_SHIFT (10U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_10_10_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP_MASK (0x800U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP_SHIFT (11U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ccm_ckil_sync_wrapper3_clk_in_STOP_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15_MASK (0xF000U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15_SHIFT (12U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_12_15_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_18_18_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_gpt3_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_20_20_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_SWEN_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_22_22_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_slave_clk_STOP_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN_SHIFT (24U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_HWEN_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN_SHIFT (25U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_SWEN_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_26_26_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP_MASK (0x8000000U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP_SHIFT (27U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_ips_sync_gpt3_ipg_master_clk_STOP_MASK)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT3_LPCG_IPS_SYNC_GPT3_0_LPCG_IPS_SYNC_GPT3_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_GPT3_Register_Masks */


/* LSIO_LPCG_GPT3 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_GPT3 base address */
#define LSIO__LPCG_GPT3_BASE                     (0x5D570000u)
/** Peripheral LSIO__LPCG_GPT3 base pointer */
#define LSIO__LPCG_GPT3                          ((LSIO_LPCG_GPT3_Type *)LSIO__LPCG_GPT3_BASE)
/** Array initializer of LSIO_LPCG_GPT3 peripheral base addresses */
#define LSIO_LPCG_GPT3_BASE_ADDRS                { LSIO__LPCG_GPT3_BASE }
/** Array initializer of LSIO_LPCG_GPT3 peripheral base pointers */
#define LSIO_LPCG_GPT3_BASE_PTRS                 { LSIO__LPCG_GPT3 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_GPT3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPT4 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPT4_Peripheral_Access_Layer LSIO_LPCG_GPT4 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_GPT4 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_IPS_SYNC_GPT4_0;              /**< na, offset: 0x0 */
} LSIO_LPCG_GPT4_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_GPT4 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_GPT4_Register_Masks LSIO_LPCG_GPT4 Register Masks
 * @{
 */

/*! @name LPCG_IPS_SYNC_GPT4_0 - na */
/*! @{ */
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN_MASK (0x1U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN_SHIFT (0U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_HWEN_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN_MASK (0x2U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN_SHIFT (1U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_2_2_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP_MASK (0x8U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP_SHIFT (3U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_STOP_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4_MASK (0x10U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4_SHIFT (4U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_4_4_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN_MASK (0x20U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN_SHIFT (5U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_SWEN_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6_MASK (0x40U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6_SHIFT (6U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_6_6_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP_MASK (0x80U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP_SHIFT (7U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_highfreq_STOP_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8_MASK (0x100U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8_SHIFT (8U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_8_8_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN_MASK (0x200U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN_SHIFT (9U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_SWEN_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10_MASK (0x400U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10_SHIFT (10U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_10_10_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP_MASK (0x800U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP_SHIFT (11U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ccm_ckil_sync_wrapper4_clk_in_STOP_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15_MASK (0xF000U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15_SHIFT (12U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_12_15_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_18_18_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_gpt4_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_20_20_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_SWEN_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_22_22_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_slave_clk_STOP_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN_SHIFT (24U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_HWEN_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN_SHIFT (25U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_SWEN_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_26_26_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP_MASK (0x8000000U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP_SHIFT (27U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_ips_sync_gpt4_ipg_master_clk_STOP_MASK)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31_SHIFT)) & LSIO_LPCG_GPT4_LPCG_IPS_SYNC_GPT4_0_LPCG_IPS_SYNC_GPT4_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_GPT4_Register_Masks */


/* LSIO_LPCG_GPT4 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_GPT4 base address */
#define LSIO__LPCG_GPT4_BASE                     (0x5D580000u)
/** Peripheral LSIO__LPCG_GPT4 base pointer */
#define LSIO__LPCG_GPT4                          ((LSIO_LPCG_GPT4_Type *)LSIO__LPCG_GPT4_BASE)
/** Array initializer of LSIO_LPCG_GPT4 peripheral base addresses */
#define LSIO_LPCG_GPT4_BASE_ADDRS                { LSIO__LPCG_GPT4_BASE }
/** Array initializer of LSIO_LPCG_GPT4 peripheral base pointers */
#define LSIO_LPCG_GPT4_BASE_PTRS                 { LSIO__LPCG_GPT4 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_GPT4_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_KPP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_KPP_Peripheral_Access_Layer LSIO_LPCG_KPP Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_KPP - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_KPP_0;                        /**< na, offset: 0x0 */
} LSIO_LPCG_KPP_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_KPP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_KPP_Register_Masks LSIO_LPCG_KPP Register Masks
 * @{
 */

/*! @name LPCG_KPP_0 - na */
/*! @{ */
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_0_0_MASK)
#define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN_MASK (0x2U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN_SHIFT (1U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_SWEN_MASK)
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_2_2_MASK)
#define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP_MASK (0x8U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP_SHIFT (3U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_ccm_ckil_sync_wrapper13_clk_in_STOP_MASK)
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_4_15_MASK)
#define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_18_18_MASK)
#define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_kpp_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_KPP_LPCG_KPP_0_LPCG_KPP_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_KPP_Register_Masks */


/* LSIO_LPCG_KPP - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_KPP base address */
#define LSIO__LPCG_KPP_BASE                      (0x5D5A0000u)
/** Peripheral LSIO__LPCG_KPP base pointer */
#define LSIO__LPCG_KPP                           ((LSIO_LPCG_KPP_Type *)LSIO__LPCG_KPP_BASE)
/** Array initializer of LSIO_LPCG_KPP peripheral base addresses */
#define LSIO_LPCG_KPP_BASE_ADDRS                 { LSIO__LPCG_KPP_BASE }
/** Array initializer of LSIO_LPCG_KPP peripheral base pointers */
#define LSIO_LPCG_KPP_BASE_PTRS                  { LSIO__LPCG_KPP }

/*!
 * @}
 */ /* end of group LSIO_LPCG_KPP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU10_DSP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU10_DSP_Peripheral_Access_Layer LSIO_LPCG_MU10_DSP Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU10_DSP - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU10_DSP_0;                   /**< na, offset: 0x0 */
} LSIO_LPCG_MU10_DSP_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU10_DSP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU10_DSP_Register_Masks LSIO_LPCG_MU10_DSP Register Masks
 * @{
 */

/*! @name LPCG_MU10_DSP_0 - na */
/*! @{ */
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_SWEN_MASK)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP_MASK (0x8U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP_SHIFT (3U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_dsp_STOP_MASK)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_HWEN_MASK)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_SWEN_MASK)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP_SHIFT (19U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_mu10_ipg_clk_s_dsp_STOP_MASK)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU10_DSP_LPCG_MU10_DSP_0_LPCG_MU10_DSP_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU10_DSP_Register_Masks */


/* LSIO_LPCG_MU10_DSP - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU10_DSP base address */
#define LSIO__LPCG_MU10_DSP_BASE                 (0x5D6E0000u)
/** Peripheral LSIO__LPCG_MU10_DSP base pointer */
#define LSIO__LPCG_MU10_DSP                      ((LSIO_LPCG_MU10_DSP_Type *)LSIO__LPCG_MU10_DSP_BASE)
/** Array initializer of LSIO_LPCG_MU10_DSP peripheral base addresses */
#define LSIO_LPCG_MU10_DSP_BASE_ADDRS            { LSIO__LPCG_MU10_DSP_BASE }
/** Array initializer of LSIO_LPCG_MU10_DSP peripheral base pointers */
#define LSIO_LPCG_MU10_DSP_BASE_PTRS             { LSIO__LPCG_MU10_DSP }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU10_DSP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU10_MCU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU10_MCU_Peripheral_Access_Layer LSIO_LPCG_MU10_MCU Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU10_MCU - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU10_MCU_0;                   /**< na, offset: 0x0 */
} LSIO_LPCG_MU10_MCU_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU10_MCU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU10_MCU_Register_Masks LSIO_LPCG_MU10_MCU Register Masks
 * @{
 */

/*! @name LPCG_MU10_MCU_0 - na */
/*! @{ */
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_SWEN_MASK)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP_MASK (0x8U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP_SHIFT (3U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_mcu_STOP_MASK)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_HWEN_MASK)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_SWEN_MASK)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP_SHIFT (19U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_mu10_ipg_clk_s_mcu_STOP_MASK)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU10_MCU_LPCG_MU10_MCU_0_LPCG_MU10_MCU_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU10_MCU_Register_Masks */


/* LSIO_LPCG_MU10_MCU - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU10_MCU base address */
#define LSIO__LPCG_MU10_MCU_BASE                 (0x5D650000u)
/** Peripheral LSIO__LPCG_MU10_MCU base pointer */
#define LSIO__LPCG_MU10_MCU                      ((LSIO_LPCG_MU10_MCU_Type *)LSIO__LPCG_MU10_MCU_BASE)
/** Array initializer of LSIO_LPCG_MU10_MCU peripheral base addresses */
#define LSIO_LPCG_MU10_MCU_BASE_ADDRS            { LSIO__LPCG_MU10_MCU_BASE }
/** Array initializer of LSIO_LPCG_MU10_MCU peripheral base pointers */
#define LSIO_LPCG_MU10_MCU_BASE_PTRS             { LSIO__LPCG_MU10_MCU }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU10_MCU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU11_DSP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU11_DSP_Peripheral_Access_Layer LSIO_LPCG_MU11_DSP Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU11_DSP - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU11_DSP_0;                   /**< na, offset: 0x0 */
} LSIO_LPCG_MU11_DSP_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU11_DSP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU11_DSP_Register_Masks LSIO_LPCG_MU11_DSP Register Masks
 * @{
 */

/*! @name LPCG_MU11_DSP_0 - na */
/*! @{ */
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_SWEN_MASK)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP_MASK (0x8U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP_SHIFT (3U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_dsp_STOP_MASK)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_HWEN_MASK)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_SWEN_MASK)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP_SHIFT (19U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_mu11_ipg_clk_s_dsp_STOP_MASK)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU11_DSP_LPCG_MU11_DSP_0_LPCG_MU11_DSP_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU11_DSP_Register_Masks */


/* LSIO_LPCG_MU11_DSP - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU11_DSP base address */
#define LSIO__LPCG_MU11_DSP_BASE                 (0x5D6F0000u)
/** Peripheral LSIO__LPCG_MU11_DSP base pointer */
#define LSIO__LPCG_MU11_DSP                      ((LSIO_LPCG_MU11_DSP_Type *)LSIO__LPCG_MU11_DSP_BASE)
/** Array initializer of LSIO_LPCG_MU11_DSP peripheral base addresses */
#define LSIO_LPCG_MU11_DSP_BASE_ADDRS            { LSIO__LPCG_MU11_DSP_BASE }
/** Array initializer of LSIO_LPCG_MU11_DSP peripheral base pointers */
#define LSIO_LPCG_MU11_DSP_BASE_PTRS             { LSIO__LPCG_MU11_DSP }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU11_DSP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU11_MCU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU11_MCU_Peripheral_Access_Layer LSIO_LPCG_MU11_MCU Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU11_MCU - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU11_MCU_0;                   /**< na, offset: 0x0 */
} LSIO_LPCG_MU11_MCU_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU11_MCU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU11_MCU_Register_Masks LSIO_LPCG_MU11_MCU Register Masks
 * @{
 */

/*! @name LPCG_MU11_MCU_0 - na */
/*! @{ */
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_SWEN_MASK)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP_MASK (0x8U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP_SHIFT (3U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_mcu_STOP_MASK)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_HWEN_MASK)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_SWEN_MASK)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP_SHIFT (19U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_mu11_ipg_clk_s_mcu_STOP_MASK)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU11_MCU_LPCG_MU11_MCU_0_LPCG_MU11_MCU_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU11_MCU_Register_Masks */


/* LSIO_LPCG_MU11_MCU - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU11_MCU base address */
#define LSIO__LPCG_MU11_MCU_BASE                 (0x5D660000u)
/** Peripheral LSIO__LPCG_MU11_MCU base pointer */
#define LSIO__LPCG_MU11_MCU                      ((LSIO_LPCG_MU11_MCU_Type *)LSIO__LPCG_MU11_MCU_BASE)
/** Array initializer of LSIO_LPCG_MU11_MCU peripheral base addresses */
#define LSIO_LPCG_MU11_MCU_BASE_ADDRS            { LSIO__LPCG_MU11_MCU_BASE }
/** Array initializer of LSIO_LPCG_MU11_MCU peripheral base pointers */
#define LSIO_LPCG_MU11_MCU_BASE_PTRS             { LSIO__LPCG_MU11_MCU }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU11_MCU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU12_DSP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU12_DSP_Peripheral_Access_Layer LSIO_LPCG_MU12_DSP Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU12_DSP - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU12_DSP_0;                   /**< na, offset: 0x0 */
} LSIO_LPCG_MU12_DSP_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU12_DSP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU12_DSP_Register_Masks LSIO_LPCG_MU12_DSP Register Masks
 * @{
 */

/*! @name LPCG_MU12_DSP_0 - na */
/*! @{ */
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_SWEN_MASK)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP_MASK (0x8U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP_SHIFT (3U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_dsp_STOP_MASK)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_HWEN_MASK)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_SWEN_MASK)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP_SHIFT (19U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_mu12_ipg_clk_s_dsp_STOP_MASK)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU12_DSP_LPCG_MU12_DSP_0_LPCG_MU12_DSP_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU12_DSP_Register_Masks */


/* LSIO_LPCG_MU12_DSP - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU12_DSP base address */
#define LSIO__LPCG_MU12_DSP_BASE                 (0x5D700000u)
/** Peripheral LSIO__LPCG_MU12_DSP base pointer */
#define LSIO__LPCG_MU12_DSP                      ((LSIO_LPCG_MU12_DSP_Type *)LSIO__LPCG_MU12_DSP_BASE)
/** Array initializer of LSIO_LPCG_MU12_DSP peripheral base addresses */
#define LSIO_LPCG_MU12_DSP_BASE_ADDRS            { LSIO__LPCG_MU12_DSP_BASE }
/** Array initializer of LSIO_LPCG_MU12_DSP peripheral base pointers */
#define LSIO_LPCG_MU12_DSP_BASE_PTRS             { LSIO__LPCG_MU12_DSP }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU12_DSP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU12_MCU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU12_MCU_Peripheral_Access_Layer LSIO_LPCG_MU12_MCU Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU12_MCU - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU12_MCU_0;                   /**< na, offset: 0x0 */
} LSIO_LPCG_MU12_MCU_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU12_MCU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU12_MCU_Register_Masks LSIO_LPCG_MU12_MCU Register Masks
 * @{
 */

/*! @name LPCG_MU12_MCU_0 - na */
/*! @{ */
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_SWEN_MASK)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP_MASK (0x8U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP_SHIFT (3U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_mcu_STOP_MASK)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_HWEN_MASK)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_SWEN_MASK)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP_SHIFT (19U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_mu12_ipg_clk_s_mcu_STOP_MASK)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU12_MCU_LPCG_MU12_MCU_0_LPCG_MU12_MCU_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU12_MCU_Register_Masks */


/* LSIO_LPCG_MU12_MCU - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU12_MCU base address */
#define LSIO__LPCG_MU12_MCU_BASE                 (0x5D670000u)
/** Peripheral LSIO__LPCG_MU12_MCU base pointer */
#define LSIO__LPCG_MU12_MCU                      ((LSIO_LPCG_MU12_MCU_Type *)LSIO__LPCG_MU12_MCU_BASE)
/** Array initializer of LSIO_LPCG_MU12_MCU peripheral base addresses */
#define LSIO_LPCG_MU12_MCU_BASE_ADDRS            { LSIO__LPCG_MU12_MCU_BASE }
/** Array initializer of LSIO_LPCG_MU12_MCU peripheral base pointers */
#define LSIO_LPCG_MU12_MCU_BASE_PTRS             { LSIO__LPCG_MU12_MCU }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU12_MCU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU13_DSP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU13_DSP_Peripheral_Access_Layer LSIO_LPCG_MU13_DSP Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU13_DSP - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU13_DSP_0;                   /**< na, offset: 0x0 */
} LSIO_LPCG_MU13_DSP_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU13_DSP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU13_DSP_Register_Masks LSIO_LPCG_MU13_DSP Register Masks
 * @{
 */

/*! @name LPCG_MU13_DSP_0 - na */
/*! @{ */
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_SWEN_MASK)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP_MASK (0x8U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP_SHIFT (3U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_dsp_STOP_MASK)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_HWEN_MASK)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_SWEN_MASK)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP_SHIFT (19U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_mu13_ipg_clk_s_dsp_STOP_MASK)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU13_DSP_LPCG_MU13_DSP_0_LPCG_MU13_DSP_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU13_DSP_Register_Masks */


/* LSIO_LPCG_MU13_DSP - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU13_DSP base address */
#define LSIO__LPCG_MU13_DSP_BASE                 (0x5D710000u)
/** Peripheral LSIO__LPCG_MU13_DSP base pointer */
#define LSIO__LPCG_MU13_DSP                      ((LSIO_LPCG_MU13_DSP_Type *)LSIO__LPCG_MU13_DSP_BASE)
/** Array initializer of LSIO_LPCG_MU13_DSP peripheral base addresses */
#define LSIO_LPCG_MU13_DSP_BASE_ADDRS            { LSIO__LPCG_MU13_DSP_BASE }
/** Array initializer of LSIO_LPCG_MU13_DSP peripheral base pointers */
#define LSIO_LPCG_MU13_DSP_BASE_PTRS             { LSIO__LPCG_MU13_DSP }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU13_DSP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU13_MCU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU13_MCU_Peripheral_Access_Layer LSIO_LPCG_MU13_MCU Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU13_MCU - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU13_MCU_0;                   /**< na, offset: 0x0 */
} LSIO_LPCG_MU13_MCU_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU13_MCU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU13_MCU_Register_Masks LSIO_LPCG_MU13_MCU Register Masks
 * @{
 */

/*! @name LPCG_MU13_MCU_0 - na */
/*! @{ */
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_SWEN_MASK)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP_MASK (0x8U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP_SHIFT (3U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_mcu_STOP_MASK)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_HWEN_MASK)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_SWEN_MASK)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP_SHIFT (19U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_mu13_ipg_clk_s_mcu_STOP_MASK)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU13_MCU_LPCG_MU13_MCU_0_LPCG_MU13_MCU_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU13_MCU_Register_Masks */


/* LSIO_LPCG_MU13_MCU - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU13_MCU base address */
#define LSIO__LPCG_MU13_MCU_BASE                 (0x5D680000u)
/** Peripheral LSIO__LPCG_MU13_MCU base pointer */
#define LSIO__LPCG_MU13_MCU                      ((LSIO_LPCG_MU13_MCU_Type *)LSIO__LPCG_MU13_MCU_BASE)
/** Array initializer of LSIO_LPCG_MU13_MCU peripheral base addresses */
#define LSIO_LPCG_MU13_MCU_BASE_ADDRS            { LSIO__LPCG_MU13_MCU_BASE }
/** Array initializer of LSIO_LPCG_MU13_MCU peripheral base pointers */
#define LSIO_LPCG_MU13_MCU_BASE_PTRS             { LSIO__LPCG_MU13_MCU }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU13_MCU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU5_DSP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU5_DSP_Peripheral_Access_Layer LSIO_LPCG_MU5_DSP Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU5_DSP - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU5_DSP_0;                    /**< na, offset: 0x0 */
} LSIO_LPCG_MU5_DSP_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU5_DSP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU5_DSP_Register_Masks LSIO_LPCG_MU5_DSP Register Masks
 * @{
 */

/*! @name LPCG_MU5_DSP_0 - na */
/*! @{ */
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_SWEN_MASK)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP_MASK (0x8U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP_SHIFT (3U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_dsp_STOP_MASK)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_HWEN_MASK)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_SWEN_MASK)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP_SHIFT (19U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_mu5_ipg_clk_s_dsp_STOP_MASK)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU5_DSP_LPCG_MU5_DSP_0_LPCG_MU5_DSP_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU5_DSP_Register_Masks */


/* LSIO_LPCG_MU5_DSP - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU5_DSP base address */
#define LSIO__LPCG_MU5_DSP_BASE                  (0x5D690000u)
/** Peripheral LSIO__LPCG_MU5_DSP base pointer */
#define LSIO__LPCG_MU5_DSP                       ((LSIO_LPCG_MU5_DSP_Type *)LSIO__LPCG_MU5_DSP_BASE)
/** Array initializer of LSIO_LPCG_MU5_DSP peripheral base addresses */
#define LSIO_LPCG_MU5_DSP_BASE_ADDRS             { LSIO__LPCG_MU5_DSP_BASE }
/** Array initializer of LSIO_LPCG_MU5_DSP peripheral base pointers */
#define LSIO_LPCG_MU5_DSP_BASE_PTRS              { LSIO__LPCG_MU5_DSP }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU5_DSP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU5_MCU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU5_MCU_Peripheral_Access_Layer LSIO_LPCG_MU5_MCU Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU5_MCU - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU5_MCU_0;                    /**< na, offset: 0x0 */
} LSIO_LPCG_MU5_MCU_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU5_MCU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU5_MCU_Register_Masks LSIO_LPCG_MU5_MCU Register Masks
 * @{
 */

/*! @name LPCG_MU5_MCU_0 - na */
/*! @{ */
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_SWEN_MASK)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP_MASK (0x8U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP_SHIFT (3U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_mcu_STOP_MASK)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_HWEN_MASK)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_SWEN_MASK)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP_SHIFT (19U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_mu5_ipg_clk_s_mcu_STOP_MASK)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU5_MCU_LPCG_MU5_MCU_0_LPCG_MU5_MCU_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU5_MCU_Register_Masks */


/* LSIO_LPCG_MU5_MCU - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU5_MCU base address */
#define LSIO__LPCG_MU5_MCU_BASE                  (0x5D600000u)
/** Peripheral LSIO__LPCG_MU5_MCU base pointer */
#define LSIO__LPCG_MU5_MCU                       ((LSIO_LPCG_MU5_MCU_Type *)LSIO__LPCG_MU5_MCU_BASE)
/** Array initializer of LSIO_LPCG_MU5_MCU peripheral base addresses */
#define LSIO_LPCG_MU5_MCU_BASE_ADDRS             { LSIO__LPCG_MU5_MCU_BASE }
/** Array initializer of LSIO_LPCG_MU5_MCU peripheral base pointers */
#define LSIO_LPCG_MU5_MCU_BASE_PTRS              { LSIO__LPCG_MU5_MCU }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU5_MCU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU6_DSP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU6_DSP_Peripheral_Access_Layer LSIO_LPCG_MU6_DSP Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU6_DSP - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU6_DSP_0;                    /**< na, offset: 0x0 */
} LSIO_LPCG_MU6_DSP_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU6_DSP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU6_DSP_Register_Masks LSIO_LPCG_MU6_DSP Register Masks
 * @{
 */

/*! @name LPCG_MU6_DSP_0 - na */
/*! @{ */
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_SWEN_MASK)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP_MASK (0x8U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP_SHIFT (3U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_dsp_STOP_MASK)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_HWEN_MASK)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_SWEN_MASK)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP_SHIFT (19U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_mu6_ipg_clk_s_dsp_STOP_MASK)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU6_DSP_LPCG_MU6_DSP_0_LPCG_MU6_DSP_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU6_DSP_Register_Masks */


/* LSIO_LPCG_MU6_DSP - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU6_DSP base address */
#define LSIO__LPCG_MU6_DSP_BASE                  (0x5D6A0000u)
/** Peripheral LSIO__LPCG_MU6_DSP base pointer */
#define LSIO__LPCG_MU6_DSP                       ((LSIO_LPCG_MU6_DSP_Type *)LSIO__LPCG_MU6_DSP_BASE)
/** Array initializer of LSIO_LPCG_MU6_DSP peripheral base addresses */
#define LSIO_LPCG_MU6_DSP_BASE_ADDRS             { LSIO__LPCG_MU6_DSP_BASE }
/** Array initializer of LSIO_LPCG_MU6_DSP peripheral base pointers */
#define LSIO_LPCG_MU6_DSP_BASE_PTRS              { LSIO__LPCG_MU6_DSP }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU6_DSP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU6_MCU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU6_MCU_Peripheral_Access_Layer LSIO_LPCG_MU6_MCU Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU6_MCU - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU6_MCU_0;                    /**< na, offset: 0x0 */
} LSIO_LPCG_MU6_MCU_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU6_MCU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU6_MCU_Register_Masks LSIO_LPCG_MU6_MCU Register Masks
 * @{
 */

/*! @name LPCG_MU6_MCU_0 - na */
/*! @{ */
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_SWEN_MASK)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP_MASK (0x8U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP_SHIFT (3U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_mcu_STOP_MASK)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_HWEN_MASK)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_SWEN_MASK)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP_SHIFT (19U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_mu6_ipg_clk_s_mcu_STOP_MASK)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU6_MCU_LPCG_MU6_MCU_0_LPCG_MU6_MCU_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU6_MCU_Register_Masks */


/* LSIO_LPCG_MU6_MCU - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU6_MCU base address */
#define LSIO__LPCG_MU6_MCU_BASE                  (0x5D610000u)
/** Peripheral LSIO__LPCG_MU6_MCU base pointer */
#define LSIO__LPCG_MU6_MCU                       ((LSIO_LPCG_MU6_MCU_Type *)LSIO__LPCG_MU6_MCU_BASE)
/** Array initializer of LSIO_LPCG_MU6_MCU peripheral base addresses */
#define LSIO_LPCG_MU6_MCU_BASE_ADDRS             { LSIO__LPCG_MU6_MCU_BASE }
/** Array initializer of LSIO_LPCG_MU6_MCU peripheral base pointers */
#define LSIO_LPCG_MU6_MCU_BASE_PTRS              { LSIO__LPCG_MU6_MCU }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU6_MCU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU7_DSP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU7_DSP_Peripheral_Access_Layer LSIO_LPCG_MU7_DSP Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU7_DSP - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU7_DSP_0;                    /**< na, offset: 0x0 */
} LSIO_LPCG_MU7_DSP_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU7_DSP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU7_DSP_Register_Masks LSIO_LPCG_MU7_DSP Register Masks
 * @{
 */

/*! @name LPCG_MU7_DSP_0 - na */
/*! @{ */
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_SWEN_MASK)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP_MASK (0x8U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP_SHIFT (3U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_dsp_STOP_MASK)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_HWEN_MASK)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_SWEN_MASK)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP_SHIFT (19U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_mu7_ipg_clk_s_dsp_STOP_MASK)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU7_DSP_LPCG_MU7_DSP_0_LPCG_MU7_DSP_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU7_DSP_Register_Masks */


/* LSIO_LPCG_MU7_DSP - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU7_DSP base address */
#define LSIO__LPCG_MU7_DSP_BASE                  (0x5D6B0000u)
/** Peripheral LSIO__LPCG_MU7_DSP base pointer */
#define LSIO__LPCG_MU7_DSP                       ((LSIO_LPCG_MU7_DSP_Type *)LSIO__LPCG_MU7_DSP_BASE)
/** Array initializer of LSIO_LPCG_MU7_DSP peripheral base addresses */
#define LSIO_LPCG_MU7_DSP_BASE_ADDRS             { LSIO__LPCG_MU7_DSP_BASE }
/** Array initializer of LSIO_LPCG_MU7_DSP peripheral base pointers */
#define LSIO_LPCG_MU7_DSP_BASE_PTRS              { LSIO__LPCG_MU7_DSP }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU7_DSP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU7_MCU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU7_MCU_Peripheral_Access_Layer LSIO_LPCG_MU7_MCU Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU7_MCU - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU7_MCU_0;                    /**< na, offset: 0x0 */
} LSIO_LPCG_MU7_MCU_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU7_MCU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU7_MCU_Register_Masks LSIO_LPCG_MU7_MCU Register Masks
 * @{
 */

/*! @name LPCG_MU7_MCU_0 - na */
/*! @{ */
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_SWEN_MASK)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP_MASK (0x8U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP_SHIFT (3U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_mcu_STOP_MASK)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_HWEN_MASK)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_SWEN_MASK)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP_SHIFT (19U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_mu7_ipg_clk_s_mcu_STOP_MASK)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU7_MCU_LPCG_MU7_MCU_0_LPCG_MU7_MCU_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU7_MCU_Register_Masks */


/* LSIO_LPCG_MU7_MCU - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU7_MCU base address */
#define LSIO__LPCG_MU7_MCU_BASE                  (0x5D620000u)
/** Peripheral LSIO__LPCG_MU7_MCU base pointer */
#define LSIO__LPCG_MU7_MCU                       ((LSIO_LPCG_MU7_MCU_Type *)LSIO__LPCG_MU7_MCU_BASE)
/** Array initializer of LSIO_LPCG_MU7_MCU peripheral base addresses */
#define LSIO_LPCG_MU7_MCU_BASE_ADDRS             { LSIO__LPCG_MU7_MCU_BASE }
/** Array initializer of LSIO_LPCG_MU7_MCU peripheral base pointers */
#define LSIO_LPCG_MU7_MCU_BASE_PTRS              { LSIO__LPCG_MU7_MCU }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU7_MCU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU8_DSP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU8_DSP_Peripheral_Access_Layer LSIO_LPCG_MU8_DSP Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU8_DSP - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU8_DSP_0;                    /**< na, offset: 0x0 */
} LSIO_LPCG_MU8_DSP_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU8_DSP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU8_DSP_Register_Masks LSIO_LPCG_MU8_DSP Register Masks
 * @{
 */

/*! @name LPCG_MU8_DSP_0 - na */
/*! @{ */
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_SWEN_MASK)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP_MASK (0x8U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP_SHIFT (3U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_dsp_STOP_MASK)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_HWEN_MASK)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_SWEN_MASK)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP_SHIFT (19U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_mu8_ipg_clk_s_dsp_STOP_MASK)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU8_DSP_LPCG_MU8_DSP_0_LPCG_MU8_DSP_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU8_DSP_Register_Masks */


/* LSIO_LPCG_MU8_DSP - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU8_DSP base address */
#define LSIO__LPCG_MU8_DSP_BASE                  (0x5D6C0000u)
/** Peripheral LSIO__LPCG_MU8_DSP base pointer */
#define LSIO__LPCG_MU8_DSP                       ((LSIO_LPCG_MU8_DSP_Type *)LSIO__LPCG_MU8_DSP_BASE)
/** Array initializer of LSIO_LPCG_MU8_DSP peripheral base addresses */
#define LSIO_LPCG_MU8_DSP_BASE_ADDRS             { LSIO__LPCG_MU8_DSP_BASE }
/** Array initializer of LSIO_LPCG_MU8_DSP peripheral base pointers */
#define LSIO_LPCG_MU8_DSP_BASE_PTRS              { LSIO__LPCG_MU8_DSP }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU8_DSP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU8_MCU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU8_MCU_Peripheral_Access_Layer LSIO_LPCG_MU8_MCU Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU8_MCU - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU8_MCU_0;                    /**< na, offset: 0x0 */
} LSIO_LPCG_MU8_MCU_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU8_MCU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU8_MCU_Register_Masks LSIO_LPCG_MU8_MCU Register Masks
 * @{
 */

/*! @name LPCG_MU8_MCU_0 - na */
/*! @{ */
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_SWEN_MASK)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP_MASK (0x8U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP_SHIFT (3U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_mcu_STOP_MASK)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_HWEN_MASK)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_SWEN_MASK)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP_SHIFT (19U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_mu8_ipg_clk_s_mcu_STOP_MASK)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU8_MCU_LPCG_MU8_MCU_0_LPCG_MU8_MCU_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU8_MCU_Register_Masks */


/* LSIO_LPCG_MU8_MCU - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU8_MCU base address */
#define LSIO__LPCG_MU8_MCU_BASE                  (0x5D630000u)
/** Peripheral LSIO__LPCG_MU8_MCU base pointer */
#define LSIO__LPCG_MU8_MCU                       ((LSIO_LPCG_MU8_MCU_Type *)LSIO__LPCG_MU8_MCU_BASE)
/** Array initializer of LSIO_LPCG_MU8_MCU peripheral base addresses */
#define LSIO_LPCG_MU8_MCU_BASE_ADDRS             { LSIO__LPCG_MU8_MCU_BASE }
/** Array initializer of LSIO_LPCG_MU8_MCU peripheral base pointers */
#define LSIO_LPCG_MU8_MCU_BASE_PTRS              { LSIO__LPCG_MU8_MCU }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU8_MCU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU9_DSP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU9_DSP_Peripheral_Access_Layer LSIO_LPCG_MU9_DSP Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU9_DSP - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU9_DSP_0;                    /**< na, offset: 0x0 */
} LSIO_LPCG_MU9_DSP_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU9_DSP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU9_DSP_Register_Masks LSIO_LPCG_MU9_DSP Register Masks
 * @{
 */

/*! @name LPCG_MU9_DSP_0 - na */
/*! @{ */
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_SWEN_MASK)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP_MASK (0x8U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP_SHIFT (3U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_dsp_STOP_MASK)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_HWEN_MASK)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_SWEN_MASK)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP_SHIFT (19U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_mu9_ipg_clk_s_dsp_STOP_MASK)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU9_DSP_LPCG_MU9_DSP_0_LPCG_MU9_DSP_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU9_DSP_Register_Masks */


/* LSIO_LPCG_MU9_DSP - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU9_DSP base address */
#define LSIO__LPCG_MU9_DSP_BASE                  (0x5D6D0000u)
/** Peripheral LSIO__LPCG_MU9_DSP base pointer */
#define LSIO__LPCG_MU9_DSP                       ((LSIO_LPCG_MU9_DSP_Type *)LSIO__LPCG_MU9_DSP_BASE)
/** Array initializer of LSIO_LPCG_MU9_DSP peripheral base addresses */
#define LSIO_LPCG_MU9_DSP_BASE_ADDRS             { LSIO__LPCG_MU9_DSP_BASE }
/** Array initializer of LSIO_LPCG_MU9_DSP peripheral base pointers */
#define LSIO_LPCG_MU9_DSP_BASE_PTRS              { LSIO__LPCG_MU9_DSP }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU9_DSP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU9_MCU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU9_MCU_Peripheral_Access_Layer LSIO_LPCG_MU9_MCU Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_MU9_MCU - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MU9_MCU_0;                    /**< na, offset: 0x0 */
} LSIO_LPCG_MU9_MCU_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_MU9_MCU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_MU9_MCU_Register_Masks LSIO_LPCG_MU9_MCU Register Masks
 * @{
 */

/*! @name LPCG_MU9_MCU_0 - na */
/*! @{ */
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_0_0_MASK)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN_MASK (0x2U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN_SHIFT (1U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_SWEN_MASK)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_2_2_MASK)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP_MASK (0x8U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP_SHIFT (3U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_mcu_STOP_MASK)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15_MASK (0xFFF0U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15_SHIFT (4U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_4_15_MASK)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN_MASK (0x10000U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN_SHIFT (16U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_HWEN_MASK)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN_MASK (0x20000U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN_SHIFT (17U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_SWEN_MASK)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_18_18_MASK)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP_MASK (0x80000U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP_SHIFT (19U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_mu9_ipg_clk_s_mcu_STOP_MASK)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31_MASK (0xFFF00000U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31_SHIFT (20U)
#define LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31_SHIFT)) & LSIO_LPCG_MU9_MCU_LPCG_MU9_MCU_0_LPCG_MU9_MCU_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_MU9_MCU_Register_Masks */


/* LSIO_LPCG_MU9_MCU - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_MU9_MCU base address */
#define LSIO__LPCG_MU9_MCU_BASE                  (0x5D640000u)
/** Peripheral LSIO__LPCG_MU9_MCU base pointer */
#define LSIO__LPCG_MU9_MCU                       ((LSIO_LPCG_MU9_MCU_Type *)LSIO__LPCG_MU9_MCU_BASE)
/** Array initializer of LSIO_LPCG_MU9_MCU peripheral base addresses */
#define LSIO_LPCG_MU9_MCU_BASE_ADDRS             { LSIO__LPCG_MU9_MCU_BASE }
/** Array initializer of LSIO_LPCG_MU9_MCU peripheral base pointers */
#define LSIO_LPCG_MU9_MCU_BASE_PTRS              { LSIO__LPCG_MU9_MCU }

/*!
 * @}
 */ /* end of group LSIO_LPCG_MU9_MCU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_OCRAM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_OCRAM_Peripheral_Access_Layer LSIO_LPCG_OCRAM Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_OCRAM - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_OCRAM_0;                      /**< na, offset: 0x0 */
} LSIO_LPCG_OCRAM_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_OCRAM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_OCRAM_Register_Masks LSIO_LPCG_OCRAM Register Masks
 * @{
 */

/*! @name LPCG_OCRAM_0 - na */
/*! @{ */
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_0_MASK)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_MASK (0x2U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_SHIFT (1U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_SWEN_MASK)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_2_2_MASK)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_MASK (0x8U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_SHIFT (3U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_ctrl_clk_STOP_MASK)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4_MASK (0x10U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4_SHIFT (4U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_4_4_MASK)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN_MASK (0x20U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN_SHIFT (5U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_SWEN_MASK)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6_MASK (0x40U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6_SHIFT (6U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_6_6_MASK)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP_MASK (0x80U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP_SHIFT (7U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_ocram_mem_wrapper_clk_STOP_MASK)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31_MASK (0xFFFFFF00U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31_SHIFT (8U)
#define LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31_SHIFT)) & LSIO_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_8_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_OCRAM_Register_Masks */


/* LSIO_LPCG_OCRAM - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_OCRAM base address */
#define LSIO__LPCG_OCRAM_BASE                    (0x5D590000u)
/** Peripheral LSIO__LPCG_OCRAM base pointer */
#define LSIO__LPCG_OCRAM                         ((LSIO_LPCG_OCRAM_Type *)LSIO__LPCG_OCRAM_BASE)
/** Array initializer of LSIO_LPCG_OCRAM peripheral base addresses */
#define LSIO_LPCG_OCRAM_BASE_ADDRS               { LSIO__LPCG_OCRAM_BASE }
/** Array initializer of LSIO_LPCG_OCRAM peripheral base pointers */
#define LSIO_LPCG_OCRAM_BASE_PTRS                { LSIO__LPCG_OCRAM }

/*!
 * @}
 */ /* end of group LSIO_LPCG_OCRAM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM0_Peripheral_Access_Layer LSIO_LPCG_PWM0 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_PWM0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_IPS_SYNC_PWM0_0;              /**< na, offset: 0x0 */
} LSIO_LPCG_PWM0_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM0_Register_Masks LSIO_LPCG_PWM0 Register Masks
 * @{
 */

/*! @name LPCG_IPS_SYNC_PWM0_0 - na */
/*! @{ */
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN_MASK (0x1U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN_SHIFT (0U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_HWEN_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN_MASK (0x2U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN_SHIFT (1U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_2_2_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP_MASK (0x8U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP_SHIFT (3U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_STOP_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4_MASK (0x10U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4_SHIFT (4U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_4_4_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN_MASK (0x20U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN_SHIFT (5U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_SWEN_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6_MASK (0x40U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6_SHIFT (6U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_6_6_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP_MASK (0x80U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP_SHIFT (7U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_highfreq_STOP_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8_MASK (0x100U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8_SHIFT (8U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_8_8_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN_MASK (0x200U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN_SHIFT (9U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_SWEN_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10_MASK (0x400U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10_SHIFT (10U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_10_10_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP_MASK (0x800U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP_SHIFT (11U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ccm_ckil_sync_wrapper5_clk_in_STOP_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15_MASK (0xF000U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15_SHIFT (12U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_12_15_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_18_18_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_pwm0_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_20_20_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_SWEN_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_22_22_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_slave_clk_STOP_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN_SHIFT (24U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_HWEN_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN_SHIFT (25U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_SWEN_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_26_26_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP_MASK (0x8000000U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP_SHIFT (27U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_ips_sync_pwm0_ipg_master_clk_STOP_MASK)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM0_LPCG_IPS_SYNC_PWM0_0_LPCG_IPS_SYNC_PWM0_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM0_Register_Masks */


/* LSIO_LPCG_PWM0 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_PWM0 base address */
#define LSIO__LPCG_PWM0_BASE                     (0x5D400000u)
/** Peripheral LSIO__LPCG_PWM0 base pointer */
#define LSIO__LPCG_PWM0                          ((LSIO_LPCG_PWM0_Type *)LSIO__LPCG_PWM0_BASE)
/** Array initializer of LSIO_LPCG_PWM0 peripheral base addresses */
#define LSIO_LPCG_PWM0_BASE_ADDRS                { LSIO__LPCG_PWM0_BASE }
/** Array initializer of LSIO_LPCG_PWM0 peripheral base pointers */
#define LSIO_LPCG_PWM0_BASE_PTRS                 { LSIO__LPCG_PWM0 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM1_Peripheral_Access_Layer LSIO_LPCG_PWM1 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_PWM1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_IPS_SYNC_PWM1_0;              /**< na, offset: 0x0 */
} LSIO_LPCG_PWM1_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM1_Register_Masks LSIO_LPCG_PWM1 Register Masks
 * @{
 */

/*! @name LPCG_IPS_SYNC_PWM1_0 - na */
/*! @{ */
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN_MASK (0x1U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN_SHIFT (0U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_HWEN_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN_MASK (0x2U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN_SHIFT (1U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_2_2_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP_MASK (0x8U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP_SHIFT (3U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_STOP_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4_MASK (0x10U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4_SHIFT (4U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_4_4_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN_MASK (0x20U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN_SHIFT (5U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_SWEN_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6_MASK (0x40U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6_SHIFT (6U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_6_6_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP_MASK (0x80U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP_SHIFT (7U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_highfreq_STOP_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8_MASK (0x100U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8_SHIFT (8U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_8_8_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN_MASK (0x200U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN_SHIFT (9U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_SWEN_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10_MASK (0x400U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10_SHIFT (10U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_10_10_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP_MASK (0x800U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP_SHIFT (11U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ccm_ckil_sync_wrapper6_clk_in_STOP_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15_MASK (0xF000U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15_SHIFT (12U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_12_15_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_18_18_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_pwm1_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_20_20_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_SWEN_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_22_22_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_slave_clk_STOP_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN_SHIFT (24U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_HWEN_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN_SHIFT (25U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_SWEN_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_26_26_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP_MASK (0x8000000U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP_SHIFT (27U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_ips_sync_pwm1_ipg_master_clk_STOP_MASK)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM1_LPCG_IPS_SYNC_PWM1_0_LPCG_IPS_SYNC_PWM1_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM1_Register_Masks */


/* LSIO_LPCG_PWM1 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_PWM1 base address */
#define LSIO__LPCG_PWM1_BASE                     (0x5D410000u)
/** Peripheral LSIO__LPCG_PWM1 base pointer */
#define LSIO__LPCG_PWM1                          ((LSIO_LPCG_PWM1_Type *)LSIO__LPCG_PWM1_BASE)
/** Array initializer of LSIO_LPCG_PWM1 peripheral base addresses */
#define LSIO_LPCG_PWM1_BASE_ADDRS                { LSIO__LPCG_PWM1_BASE }
/** Array initializer of LSIO_LPCG_PWM1 peripheral base pointers */
#define LSIO_LPCG_PWM1_BASE_PTRS                 { LSIO__LPCG_PWM1 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM2_Peripheral_Access_Layer LSIO_LPCG_PWM2 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_PWM2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_IPS_SYNC_PWM2_0;              /**< na, offset: 0x0 */
} LSIO_LPCG_PWM2_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM2_Register_Masks LSIO_LPCG_PWM2 Register Masks
 * @{
 */

/*! @name LPCG_IPS_SYNC_PWM2_0 - na */
/*! @{ */
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN_MASK (0x1U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN_SHIFT (0U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_HWEN_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN_MASK (0x2U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN_SHIFT (1U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_2_2_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP_MASK (0x8U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP_SHIFT (3U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_STOP_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4_MASK (0x10U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4_SHIFT (4U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_4_4_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN_MASK (0x20U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN_SHIFT (5U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_SWEN_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6_MASK (0x40U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6_SHIFT (6U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_6_6_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP_MASK (0x80U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP_SHIFT (7U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_highfreq_STOP_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8_MASK (0x100U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8_SHIFT (8U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_8_8_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN_MASK (0x200U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN_SHIFT (9U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_SWEN_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10_MASK (0x400U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10_SHIFT (10U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_10_10_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP_MASK (0x800U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP_SHIFT (11U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ccm_ckil_sync_wrapper7_clk_in_STOP_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15_MASK (0xF000U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15_SHIFT (12U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_12_15_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_18_18_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_pwm2_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_20_20_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_SWEN_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_22_22_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_slave_clk_STOP_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN_SHIFT (24U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_HWEN_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN_SHIFT (25U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_SWEN_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_26_26_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP_MASK (0x8000000U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP_SHIFT (27U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_ips_sync_pwm2_ipg_master_clk_STOP_MASK)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM2_LPCG_IPS_SYNC_PWM2_0_LPCG_IPS_SYNC_PWM2_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM2_Register_Masks */


/* LSIO_LPCG_PWM2 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_PWM2 base address */
#define LSIO__LPCG_PWM2_BASE                     (0x5D420000u)
/** Peripheral LSIO__LPCG_PWM2 base pointer */
#define LSIO__LPCG_PWM2                          ((LSIO_LPCG_PWM2_Type *)LSIO__LPCG_PWM2_BASE)
/** Array initializer of LSIO_LPCG_PWM2 peripheral base addresses */
#define LSIO_LPCG_PWM2_BASE_ADDRS                { LSIO__LPCG_PWM2_BASE }
/** Array initializer of LSIO_LPCG_PWM2 peripheral base pointers */
#define LSIO_LPCG_PWM2_BASE_PTRS                 { LSIO__LPCG_PWM2 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM3_Peripheral_Access_Layer LSIO_LPCG_PWM3 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_PWM3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_IPS_SYNC_PWM3_0;              /**< na, offset: 0x0 */
} LSIO_LPCG_PWM3_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM3_Register_Masks LSIO_LPCG_PWM3 Register Masks
 * @{
 */

/*! @name LPCG_IPS_SYNC_PWM3_0 - na */
/*! @{ */
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN_MASK (0x1U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN_SHIFT (0U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_HWEN_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN_MASK (0x2U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN_SHIFT (1U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_2_2_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP_MASK (0x8U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP_SHIFT (3U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_STOP_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4_MASK (0x10U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4_SHIFT (4U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_4_4_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN_MASK (0x20U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN_SHIFT (5U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_SWEN_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6_MASK (0x40U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6_SHIFT (6U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_6_6_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP_MASK (0x80U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP_SHIFT (7U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_highfreq_STOP_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8_MASK (0x100U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8_SHIFT (8U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_8_8_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN_MASK (0x200U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN_SHIFT (9U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_SWEN_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10_MASK (0x400U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10_SHIFT (10U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_10_10_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP_MASK (0x800U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP_SHIFT (11U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ccm_ckil_sync_wrapper8_clk_in_STOP_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15_MASK (0xF000U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15_SHIFT (12U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_12_15_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_18_18_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_pwm3_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_20_20_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_SWEN_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_22_22_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_slave_clk_STOP_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN_SHIFT (24U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_HWEN_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN_SHIFT (25U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_SWEN_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_26_26_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP_MASK (0x8000000U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP_SHIFT (27U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_ips_sync_pwm3_ipg_master_clk_STOP_MASK)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM3_LPCG_IPS_SYNC_PWM3_0_LPCG_IPS_SYNC_PWM3_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM3_Register_Masks */


/* LSIO_LPCG_PWM3 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_PWM3 base address */
#define LSIO__LPCG_PWM3_BASE                     (0x5D430000u)
/** Peripheral LSIO__LPCG_PWM3 base pointer */
#define LSIO__LPCG_PWM3                          ((LSIO_LPCG_PWM3_Type *)LSIO__LPCG_PWM3_BASE)
/** Array initializer of LSIO_LPCG_PWM3 peripheral base addresses */
#define LSIO_LPCG_PWM3_BASE_ADDRS                { LSIO__LPCG_PWM3_BASE }
/** Array initializer of LSIO_LPCG_PWM3 peripheral base pointers */
#define LSIO_LPCG_PWM3_BASE_PTRS                 { LSIO__LPCG_PWM3 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM4 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM4_Peripheral_Access_Layer LSIO_LPCG_PWM4 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_PWM4 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_IPS_SYNC_PWM4_0;              /**< na, offset: 0x0 */
} LSIO_LPCG_PWM4_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM4 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM4_Register_Masks LSIO_LPCG_PWM4 Register Masks
 * @{
 */

/*! @name LPCG_IPS_SYNC_PWM4_0 - na */
/*! @{ */
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN_MASK (0x1U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN_SHIFT (0U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_HWEN_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN_MASK (0x2U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN_SHIFT (1U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_2_2_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP_MASK (0x8U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP_SHIFT (3U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_STOP_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4_MASK (0x10U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4_SHIFT (4U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_4_4_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN_MASK (0x20U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN_SHIFT (5U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_SWEN_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6_MASK (0x40U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6_SHIFT (6U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_6_6_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP_MASK (0x80U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP_SHIFT (7U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_highfreq_STOP_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8_MASK (0x100U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8_SHIFT (8U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_8_8_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN_MASK (0x200U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN_SHIFT (9U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_SWEN_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10_MASK (0x400U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10_SHIFT (10U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_10_10_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP_MASK (0x800U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP_SHIFT (11U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ccm_ckil_sync_wrapper9_clk_in_STOP_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15_MASK (0xF000U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15_SHIFT (12U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_12_15_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_18_18_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_pwm4_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_20_20_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_SWEN_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_22_22_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_slave_clk_STOP_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN_SHIFT (24U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_HWEN_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN_SHIFT (25U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_SWEN_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_26_26_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP_MASK (0x8000000U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP_SHIFT (27U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_ips_sync_pwm4_ipg_master_clk_STOP_MASK)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM4_LPCG_IPS_SYNC_PWM4_0_LPCG_IPS_SYNC_PWM4_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM4_Register_Masks */


/* LSIO_LPCG_PWM4 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_PWM4 base address */
#define LSIO__LPCG_PWM4_BASE                     (0x5D440000u)
/** Peripheral LSIO__LPCG_PWM4 base pointer */
#define LSIO__LPCG_PWM4                          ((LSIO_LPCG_PWM4_Type *)LSIO__LPCG_PWM4_BASE)
/** Array initializer of LSIO_LPCG_PWM4 peripheral base addresses */
#define LSIO_LPCG_PWM4_BASE_ADDRS                { LSIO__LPCG_PWM4_BASE }
/** Array initializer of LSIO_LPCG_PWM4 peripheral base pointers */
#define LSIO_LPCG_PWM4_BASE_PTRS                 { LSIO__LPCG_PWM4 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM4_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM5 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM5_Peripheral_Access_Layer LSIO_LPCG_PWM5 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_PWM5 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_IPS_SYNC_PWM5_0;              /**< na, offset: 0x0 */
} LSIO_LPCG_PWM5_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM5 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM5_Register_Masks LSIO_LPCG_PWM5 Register Masks
 * @{
 */

/*! @name LPCG_IPS_SYNC_PWM5_0 - na */
/*! @{ */
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN_MASK (0x1U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN_SHIFT (0U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_HWEN_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN_MASK (0x2U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN_SHIFT (1U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_2_2_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP_MASK (0x8U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP_SHIFT (3U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_STOP_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4_MASK (0x10U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4_SHIFT (4U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_4_4_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN_MASK (0x20U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN_SHIFT (5U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_SWEN_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6_MASK (0x40U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6_SHIFT (6U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_6_6_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP_MASK (0x80U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP_SHIFT (7U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_highfreq_STOP_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8_MASK (0x100U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8_SHIFT (8U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_8_8_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN_MASK (0x200U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN_SHIFT (9U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_SWEN_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10_MASK (0x400U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10_SHIFT (10U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_10_10_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP_MASK (0x800U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP_SHIFT (11U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ccm_ckil_sync_wrapper10_clk_in_STOP_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15_MASK (0xF000U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15_SHIFT (12U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_12_15_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_18_18_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_pwm5_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_20_20_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_SWEN_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_22_22_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_slave_clk_STOP_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN_SHIFT (24U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_HWEN_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN_SHIFT (25U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_SWEN_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_26_26_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP_MASK (0x8000000U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP_SHIFT (27U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_ips_sync_pwm5_ipg_master_clk_STOP_MASK)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM5_LPCG_IPS_SYNC_PWM5_0_LPCG_IPS_SYNC_PWM5_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM5_Register_Masks */


/* LSIO_LPCG_PWM5 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_PWM5 base address */
#define LSIO__LPCG_PWM5_BASE                     (0x5D450000u)
/** Peripheral LSIO__LPCG_PWM5 base pointer */
#define LSIO__LPCG_PWM5                          ((LSIO_LPCG_PWM5_Type *)LSIO__LPCG_PWM5_BASE)
/** Array initializer of LSIO_LPCG_PWM5 peripheral base addresses */
#define LSIO_LPCG_PWM5_BASE_ADDRS                { LSIO__LPCG_PWM5_BASE }
/** Array initializer of LSIO_LPCG_PWM5 peripheral base pointers */
#define LSIO_LPCG_PWM5_BASE_PTRS                 { LSIO__LPCG_PWM5 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM5_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM6 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM6_Peripheral_Access_Layer LSIO_LPCG_PWM6 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_PWM6 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_IPS_SYNC_PWM6_0;              /**< na, offset: 0x0 */
} LSIO_LPCG_PWM6_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM6 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM6_Register_Masks LSIO_LPCG_PWM6 Register Masks
 * @{
 */

/*! @name LPCG_IPS_SYNC_PWM6_0 - na */
/*! @{ */
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN_MASK (0x1U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN_SHIFT (0U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_HWEN_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN_MASK (0x2U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN_SHIFT (1U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_2_2_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP_MASK (0x8U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP_SHIFT (3U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_STOP_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4_MASK (0x10U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4_SHIFT (4U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_4_4_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN_MASK (0x20U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN_SHIFT (5U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_SWEN_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6_MASK (0x40U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6_SHIFT (6U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_6_6_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP_MASK (0x80U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP_SHIFT (7U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_highfreq_STOP_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8_MASK (0x100U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8_SHIFT (8U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_8_8_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN_MASK (0x200U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN_SHIFT (9U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_SWEN_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10_MASK (0x400U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10_SHIFT (10U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_10_10_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP_MASK (0x800U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP_SHIFT (11U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ccm_ckil_sync_wrapper11_clk_in_STOP_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15_MASK (0xF000U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15_SHIFT (12U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_12_15_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_18_18_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_pwm6_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_20_20_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_SWEN_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_22_22_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_slave_clk_STOP_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN_SHIFT (24U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_HWEN_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN_SHIFT (25U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_SWEN_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_26_26_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP_MASK (0x8000000U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP_SHIFT (27U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_ips_sync_pwm6_ipg_master_clk_STOP_MASK)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM6_LPCG_IPS_SYNC_PWM6_0_LPCG_IPS_SYNC_PWM6_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM6_Register_Masks */


/* LSIO_LPCG_PWM6 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_PWM6 base address */
#define LSIO__LPCG_PWM6_BASE                     (0x5D460000u)
/** Peripheral LSIO__LPCG_PWM6 base pointer */
#define LSIO__LPCG_PWM6                          ((LSIO_LPCG_PWM6_Type *)LSIO__LPCG_PWM6_BASE)
/** Array initializer of LSIO_LPCG_PWM6 peripheral base addresses */
#define LSIO_LPCG_PWM6_BASE_ADDRS                { LSIO__LPCG_PWM6_BASE }
/** Array initializer of LSIO_LPCG_PWM6 peripheral base pointers */
#define LSIO_LPCG_PWM6_BASE_PTRS                 { LSIO__LPCG_PWM6 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM6_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM7 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM7_Peripheral_Access_Layer LSIO_LPCG_PWM7 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_PWM7 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_IPS_SYNC_PWM7_0;              /**< na, offset: 0x0 */
} LSIO_LPCG_PWM7_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_PWM7 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_PWM7_Register_Masks LSIO_LPCG_PWM7 Register Masks
 * @{
 */

/*! @name LPCG_IPS_SYNC_PWM7_0 - na */
/*! @{ */
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN_MASK (0x1U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN_SHIFT (0U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_HWEN_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN_MASK (0x2U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN_SHIFT (1U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_2_2_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP_MASK (0x8U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP_SHIFT (3U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_STOP_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4_MASK (0x10U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4_SHIFT (4U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_4_4_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN_MASK (0x20U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN_SHIFT (5U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_SWEN_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6_MASK (0x40U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6_SHIFT (6U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_6_6_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP_MASK (0x80U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP_SHIFT (7U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_highfreq_STOP_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8_MASK (0x100U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8_SHIFT (8U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_8_8_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN_MASK (0x200U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN_SHIFT (9U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_SWEN_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10_MASK (0x400U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10_SHIFT (10U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_10_10_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP_MASK (0x800U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP_SHIFT (11U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ccm_ckil_sync_wrapper12_clk_in_STOP_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15_MASK (0xF000U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15_SHIFT (12U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_12_15_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN_MASK (0x10000U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN_SHIFT (16U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN_MASK (0x20000U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN_SHIFT (17U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_18_18_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP_MASK (0x80000U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP_SHIFT (19U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_pwm7_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_20_20_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_SWEN_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_22_22_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_slave_clk_STOP_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN_SHIFT (24U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_HWEN_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN_SHIFT (25U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_SWEN_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_26_26_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP_MASK (0x8000000U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP_SHIFT (27U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_ips_sync_pwm7_ipg_master_clk_STOP_MASK)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31_SHIFT)) & LSIO_LPCG_PWM7_LPCG_IPS_SYNC_PWM7_0_LPCG_IPS_SYNC_PWM7_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM7_Register_Masks */


/* LSIO_LPCG_PWM7 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_PWM7 base address */
#define LSIO__LPCG_PWM7_BASE                     (0x5D470000u)
/** Peripheral LSIO__LPCG_PWM7 base pointer */
#define LSIO__LPCG_PWM7                          ((LSIO_LPCG_PWM7_Type *)LSIO__LPCG_PWM7_BASE)
/** Array initializer of LSIO_LPCG_PWM7 peripheral base addresses */
#define LSIO_LPCG_PWM7_BASE_ADDRS                { LSIO__LPCG_PWM7_BASE }
/** Array initializer of LSIO_LPCG_PWM7 peripheral base pointers */
#define LSIO_LPCG_PWM7_BASE_PTRS                 { LSIO__LPCG_PWM7 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_PWM7_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_QSPI0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_QSPI0_Peripheral_Access_Layer LSIO_LPCG_QSPI0 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_QSPI0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_QSPI0_0;                      /**< na, offset: 0x0 */
} LSIO_LPCG_QSPI0_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_QSPI0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_QSPI0_Register_Masks LSIO_LPCG_QSPI0 Register Masks
 * @{
 */

/*! @name LPCG_QSPI0_0 - na */
/*! @{ */
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_0_0_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN_MASK (0x2U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN_SHIFT (1U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_SWEN_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_2_2_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP_MASK (0x8U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP_SHIFT (3U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_sfck_STOP_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16_MASK (0x1FFF0U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16_SHIFT (4U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_4_16_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN_MASK (0x20000U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN_SHIFT (17U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_SWEN_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_18_18_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP_MASK (0x80000U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP_SHIFT (19U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_hclk_STOP_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_20_20_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_22_22_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_STOP_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN_SHIFT (24U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN_SHIFT (25U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_26_26_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP_MASK (0x8000000U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP_SHIFT (27U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_qspi0_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31_SHIFT)) & LSIO_LPCG_QSPI0_LPCG_QSPI0_0_LPCG_QSPI0_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_QSPI0_Register_Masks */


/* LSIO_LPCG_QSPI0 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_QSPI0 base address */
#define LSIO__LPCG_QSPI0_BASE                    (0x5D520000u)
/** Peripheral LSIO__LPCG_QSPI0 base pointer */
#define LSIO__LPCG_QSPI0                         ((LSIO_LPCG_QSPI0_Type *)LSIO__LPCG_QSPI0_BASE)
/** Array initializer of LSIO_LPCG_QSPI0 peripheral base addresses */
#define LSIO_LPCG_QSPI0_BASE_ADDRS               { LSIO__LPCG_QSPI0_BASE }
/** Array initializer of LSIO_LPCG_QSPI0 peripheral base pointers */
#define LSIO_LPCG_QSPI0_BASE_PTRS                { LSIO__LPCG_QSPI0 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_QSPI0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_QSPI1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_QSPI1_Peripheral_Access_Layer LSIO_LPCG_QSPI1 Peripheral Access Layer
 * @{
 */

/** LSIO_LPCG_QSPI1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_QSPI1_0;                      /**< na, offset: 0x0 */
} LSIO_LPCG_QSPI1_Type;

/* ----------------------------------------------------------------------------
   -- LSIO_LPCG_QSPI1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LSIO_LPCG_QSPI1_Register_Masks LSIO_LPCG_QSPI1 Register Masks
 * @{
 */

/*! @name LPCG_QSPI1_0 - na */
/*! @{ */
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0_MASK (0x1U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0_SHIFT (0U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_0_0_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN_MASK (0x2U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN_SHIFT (1U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_SWEN_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2_MASK (0x4U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2_SHIFT (2U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_2_2_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP_MASK (0x8U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP_SHIFT (3U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_sfck_STOP_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16_MASK (0x1FFF0U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16_SHIFT (4U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_4_16_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN_MASK (0x20000U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN_SHIFT (17U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_SWEN_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18_MASK (0x40000U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18_SHIFT (18U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_18_18_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP_MASK (0x80000U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP_SHIFT (19U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_hclk_STOP_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20_MASK (0x100000U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20_SHIFT (20U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_20_20_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN_MASK (0x200000U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN_SHIFT (21U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_SWEN_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22_MASK (0x400000U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22_SHIFT (22U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_22_22_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP_MASK (0x800000U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP_SHIFT (23U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_STOP_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN_MASK (0x1000000U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN_SHIFT (24U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_HWEN_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN_MASK (0x2000000U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN_SHIFT (25U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_SWEN_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26_MASK (0x4000000U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26_SHIFT (26U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_26_26_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP_MASK (0x8000000U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP_SHIFT (27U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_qspi1_ipg_clk_s_STOP_MASK)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31_MASK (0xF0000000U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31_SHIFT (28U)
#define LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31_SHIFT)) & LSIO_LPCG_QSPI1_LPCG_QSPI1_0_LPCG_QSPI1_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LSIO_LPCG_QSPI1_Register_Masks */


/* LSIO_LPCG_QSPI1 - Peripheral instance base addresses */
/** Peripheral LSIO__LPCG_QSPI1 base address */
#define LSIO__LPCG_QSPI1_BASE                    (0x5D530000u)
/** Peripheral LSIO__LPCG_QSPI1 base pointer */
#define LSIO__LPCG_QSPI1                         ((LSIO_LPCG_QSPI1_Type *)LSIO__LPCG_QSPI1_BASE)
/** Array initializer of LSIO_LPCG_QSPI1 peripheral base addresses */
#define LSIO_LPCG_QSPI1_BASE_ADDRS               { LSIO__LPCG_QSPI1_BASE }
/** Array initializer of LSIO_LPCG_QSPI1 peripheral base pointers */
#define LSIO_LPCG_QSPI1_BASE_PTRS                { LSIO__LPCG_QSPI1 }

/*!
 * @}
 */ /* end of group LSIO_LPCG_QSPI1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MIPI_CSI2RX Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_CSI2RX_Peripheral_Access_Layer MIPI_CSI2RX Peripheral Access Layer
 * @{
 */

/** MIPI_CSI2RX - Register Layout Typedef */
typedef struct {
  __IO uint32_t CSI2RX_CFG_NUM_LANES;              /**< , offset: 0x0 */
  __IO uint32_t CSI2RX_CFG_DISABLE_DATA_LANES;     /**< , offset: 0x4 */
  __I  uint32_t CSI2RX_BIT_ERR;                    /**< , offset: 0x8 */
  __I  uint32_t CSI2RX_IRQ_STATUS;                 /**< , offset: 0xC */
  __IO uint32_t CSI2RX_IRQ_MASK;                   /**< , offset: 0x10 */
  __I  uint32_t CSI2RX_ULPS_STATUS;                /**< , offset: 0x14 */
  __I  uint32_t CSI2RX_PPI_ERRSOT_HS;              /**< , offset: 0x18 */
  __I  uint32_t CSI2RX_PPI_ERRSOTSYNC_HS;          /**< , offset: 0x1C */
  __I  uint32_t CSI2RX_PPI_ERRESC;                 /**< , offset: 0x20 */
  __I  uint32_t CSI2RX_PPI_ERRSYNCESC;             /**< , offset: 0x24 */
  __I  uint32_t CSI2RX_PPI_ERRCONTROL;             /**< , offset: 0x28 */
  __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_0;      /**< , offset: 0x2C */
  __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_1;      /**< , offset: 0x30 */
} MIPI_CSI2RX_Type;

/* ----------------------------------------------------------------------------
   -- MIPI_CSI2RX Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_CSI2RX_Register_Masks MIPI_CSI2RX Register Masks
 * @{
 */

/*! @name CSI2RX_CFG_NUM_LANES -  */
/*! @{ */
#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK (0x3U)
#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_SHIFT (0U)
#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK)
#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_reserved_MASK (0xFFFFFFFCU)
#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_reserved_SHIFT (2U)
#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_reserved_MASK)
/*! @} */

/*! @name CSI2RX_CFG_DISABLE_DATA_LANES -  */
/*! @{ */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_MASK (0xFU)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_SHIFT (0U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_MASK)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_reserved_MASK (0xFFFFFFF0U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_reserved_SHIFT (4U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_reserved_MASK)
/*! @} */

/*! @name CSI2RX_BIT_ERR -  */
/*! @{ */
#define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_MASK (0x3FFU)
#define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_SHIFT (0U)
#define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_SHIFT)) & MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_MASK)
#define MIPI_CSI2RX_CSI2RX_BIT_ERR_reserved_MASK (0xFFFFFC00U)
#define MIPI_CSI2RX_CSI2RX_BIT_ERR_reserved_SHIFT (10U)
#define MIPI_CSI2RX_CSI2RX_BIT_ERR_reserved(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_BIT_ERR_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_BIT_ERR_reserved_MASK)
/*! @} */

/*! @name CSI2RX_IRQ_STATUS -  */
/*! @{ */
#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_MASK (0x1FFU)
#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_SHIFT (0U)
#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_MASK)
#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_reserved_MASK (0xFFFFFE00U)
#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_reserved_SHIFT (9U)
#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_STATUS_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_STATUS_reserved_MASK)
/*! @} */

/*! @name CSI2RX_IRQ_MASK -  */
/*! @{ */
#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK (0x1FFU)
#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_SHIFT (0U)
#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK)
#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_reserved_MASK (0xFFFFFE00U)
#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_reserved_SHIFT (9U)
#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_reserved(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_MASK_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_MASK_reserved_MASK)
/*! @} */

/*! @name CSI2RX_ULPS_STATUS -  */
/*! @{ */
#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_MASK (0x3FFU)
#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_SHIFT (0U)
#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_SHIFT)) & MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_MASK)
#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_reserved_MASK (0xFFFFFC00U)
#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_reserved_SHIFT (10U)
#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_ULPS_STATUS_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_ULPS_STATUS_reserved_MASK)
/*! @} */

/*! @name CSI2RX_PPI_ERRSOT_HS -  */
/*! @{ */
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_MASK (0xFU)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_SHIFT (0U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_MASK)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_reserved_MASK (0xFFFFFFF0U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_reserved_SHIFT (4U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_reserved_MASK)
/*! @} */

/*! @name CSI2RX_PPI_ERRSOTSYNC_HS -  */
/*! @{ */
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_MASK (0xFU)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_SHIFT (0U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_MASK)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_reserved_MASK (0xFFFFFFF0U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_reserved_SHIFT (4U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_reserved_MASK)
/*! @} */

/*! @name CSI2RX_PPI_ERRESC -  */
/*! @{ */
#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_MASK (0xFU)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_SHIFT (0U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_MASK)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_reserved_MASK (0xFFFFFFF0U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_reserved_SHIFT (4U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRESC_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRESC_reserved_MASK)
/*! @} */

/*! @name CSI2RX_PPI_ERRSYNCESC -  */
/*! @{ */
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_MASK (0xFU)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_SHIFT (0U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_MASK)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_reserved_MASK (0xFFFFFFF0U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_reserved_SHIFT (4U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_reserved_MASK)
/*! @} */

/*! @name CSI2RX_PPI_ERRCONTROL -  */
/*! @{ */
#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_MASK (0xFU)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_SHIFT (0U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_MASK)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_reserved_MASK (0xFFFFFFF0U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_reserved_SHIFT (4U)
#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_reserved_MASK)
/*! @} */

/*! @name CSI2RX_CFG_DISABLE_PAYLOAD_0 -  */
/*! @{ */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_0_MASK (0xFFFFFFFFU)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_0_SHIFT (0U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_0_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_0_MASK)
/*! @} */

/*! @name CSI2RX_CFG_DISABLE_PAYLOAD_1 -  */
/*! @{ */
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_1_MASK (0x1FFFFU)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_1_SHIFT (0U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_1_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_1_MASK)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_reserved_MASK (0xFFFE0000U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_reserved_SHIFT (17U)
#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_reserved_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MIPI_CSI2RX_Register_Masks */


/* MIPI_CSI2RX - Peripheral instance base addresses */
/** Peripheral MIPI_CSI_0__MIPI_CSI2RX base address */
#define MIPI_CSI_0__MIPI_CSI2RX_BASE             (0x58227100u)
/** Peripheral MIPI_CSI_0__MIPI_CSI2RX base pointer */
#define MIPI_CSI_0__MIPI_CSI2RX                  ((MIPI_CSI2RX_Type *)MIPI_CSI_0__MIPI_CSI2RX_BASE)
/** Peripheral MIPI_CSI_1__MIPI_CSI2RX base address */
#define MIPI_CSI_1__MIPI_CSI2RX_BASE             (0x58247100u)
/** Peripheral MIPI_CSI_1__MIPI_CSI2RX base pointer */
#define MIPI_CSI_1__MIPI_CSI2RX                  ((MIPI_CSI2RX_Type *)MIPI_CSI_1__MIPI_CSI2RX_BASE)
/** Array initializer of MIPI_CSI2RX peripheral base addresses */
#define MIPI_CSI2RX_BASE_ADDRS                   { MIPI_CSI_0__MIPI_CSI2RX_BASE, MIPI_CSI_1__MIPI_CSI2RX_BASE }
/** Array initializer of MIPI_CSI2RX peripheral base pointers */
#define MIPI_CSI2RX_BASE_PTRS                    { MIPI_CSI_0__MIPI_CSI2RX, MIPI_CSI_1__MIPI_CSI2RX }

/*!
 * @}
 */ /* end of group MIPI_CSI2RX_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MIPI_CSI_LPCG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_CSI_LPCG_Peripheral_Access_Layer MIPI_CSI_LPCG Peripheral Access Layer
 * @{
 */

/** MIPI_CSI_LPCG - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MIPI_CSI_LPCG_0;              /**< na, offset: 0x0 */
  __IO uint32_t LPCG_MIPI_CSI_LPCG_4;              /**< na, offset: 0x4 */
  __IO uint32_t LPCG_MIPI_CSI_LPCG_8;              /**< na, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t LPCG_MIPI_CSI_LPCG_16;             /**< na, offset: 0x10 */
  __IO uint32_t LPCG_MIPI_CSI_LPCG_20;             /**< na, offset: 0x14 */
  __IO uint32_t LPCG_MIPI_CSI_LPCG_24;             /**< na, offset: 0x18 */
  __IO uint32_t LPCG_MIPI_CSI_LPCG_28;             /**< na, offset: 0x1C */
} MIPI_CSI_LPCG_Type;

/* ----------------------------------------------------------------------------
   -- MIPI_CSI_LPCG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_CSI_LPCG_Register_Masks MIPI_CSI_LPCG Register Masks
 * @{
 */

/*! @name LPCG_MIPI_CSI_LPCG_0 - na */
/*! @{ */
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16_MASK (0x1FFFFU)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16_SHIFT (0U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_0_16_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN_MASK (0x20000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN_SHIFT (17U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_SWEN_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18_MASK (0x40000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18_SHIFT (18U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_18_18_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP_MASK (0x80000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP_SHIFT (19U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_lis_ipg_clk_STOP_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31_MASK (0xFFF00000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31_SHIFT (20U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_0_LPCG_mipi_csi_lpcg_0_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_MIPI_CSI_LPCG_4 - na */
/*! @{ */
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16_MASK (0x1FFFFU)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16_SHIFT (0U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_0_16_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN_MASK (0x20000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN_SHIFT (17U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_SWEN_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18_MASK (0x40000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18_SHIFT (18U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_18_18_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP_MASK (0x80000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP_SHIFT (19U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_mipi_csi_regs_apb_clk_STOP_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31_MASK (0xFFF00000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31_SHIFT (20U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_4_LPCG_mipi_csi_lpcg_4_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_MIPI_CSI_LPCG_8 - na */
/*! @{ */
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15_MASK (0xFFFFU)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15_SHIFT (0U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_0_15_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN_MASK (0x10000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT (16U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_HWEN_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN_MASK (0x20000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT (17U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_SWEN_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18_MASK (0x40000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18_SHIFT (18U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_18_18_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP_MASK (0x80000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT (19U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_gpio_ipg_clk_s_STOP_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31_MASK (0xFFF00000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31_SHIFT (20U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_8_LPCG_mipi_csi_lpcg_8_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_MIPI_CSI_LPCG_16 - na */
/*! @{ */
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0_MASK (0x1U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0_SHIFT (0U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_0_0_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_MASK (0x2U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_SHIFT (1U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_SWEN_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2_MASK (0x4U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2_SHIFT (2U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_2_2_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP_MASK (0x8U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP_SHIFT (3U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_highfreq_STOP_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15_MASK (0xFFF0U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15_SHIFT (4U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_4_15_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK (0x10000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT (16U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK (0x20000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT (17U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18_MASK (0x40000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18_SHIFT (18U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_18_18_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK (0x80000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT (19U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31_MASK (0xFFF00000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31_SHIFT (20U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_16_LPCG_mipi_csi_lpcg_16_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_MIPI_CSI_LPCG_20 - na */
/*! @{ */
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_MASK (0x1U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_SHIFT (0U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN_MASK (0x2U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN_SHIFT (1U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_SWEN_AND_lpi2c_lpi2c_div_clk_SWEN_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2_MASK (0x4U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2_SHIFT (2U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_2_2_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP_MASK (0x8U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP_SHIFT (3U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_lpi2c_clk_STOP_AND_lpi2c_lpi2c_div_clk_STOP_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15_MASK (0xFFF0U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15_SHIFT (4U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_4_15_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN_MASK (0x10000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN_SHIFT (16U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_s_HWEN_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN_MASK (0x20000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN_SHIFT (17U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_SWEN_AND_lpi2c_ipg_clk_s_SWEN_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18_MASK (0x40000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18_SHIFT (18U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_18_18_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP_MASK (0x80000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP_SHIFT (19U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_lpi2c_ipg_clk_STOP_AND_lpi2c_ipg_clk_s_STOP_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31_MASK (0xFFF00000U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31_SHIFT (20U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_20_LPCG_mipi_csi_lpcg_20_reserved_20_31_MASK)
/*! @} */

/*! @name LPCG_MIPI_CSI_LPCG_24 - na */
/*! @{ */
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0_MASK (0x1U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0_SHIFT (0U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_0_0_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN_MASK (0x2U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN_SHIFT (1U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_SWEN_AND_csi2_rx_top_clk_ui_SWEN_AND_csi2_rx_top_scan_clk_in_SWEN_AND_pixel_link_mst_clk_SWEN_AND_pixel_reformatting_clk_ui_SWEN_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2_MASK (0x4U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2_SHIFT (2U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_2_2_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP_MASK (0x8U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP_SHIFT (3U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_csi2_rx_top_clk_STOP_AND_csi2_rx_top_clk_ui_STOP_AND_csi2_rx_top_scan_clk_in_STOP_AND_pixel_link_mst_clk_STOP_AND_pixel_reformatting_clk_ui_STOP_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31_MASK (0xFFFFFFF0U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31_SHIFT (4U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_24_LPCG_mipi_csi_lpcg_24_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_MIPI_CSI_LPCG_28 - na */
/*! @{ */
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0_MASK (0x1U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0_SHIFT (0U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_0_0_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN_MASK (0x2U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN_SHIFT (1U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_SWEN_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2_MASK (0x4U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2_SHIFT (2U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_2_2_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP_MASK (0x8U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP_SHIFT (3U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_csi2_rx_top_clk_esc_STOP_MASK)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31_MASK (0xFFFFFFF0U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31_SHIFT (4U)
#define MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31_SHIFT)) & MIPI_CSI_LPCG_LPCG_MIPI_CSI_LPCG_28_LPCG_mipi_csi_lpcg_28_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MIPI_CSI_LPCG_Register_Masks */


/* MIPI_CSI_LPCG - Peripheral instance base addresses */
/** Peripheral MIPI_CSI_0__LPCG_CLK base address */
#define MIPI_CSI_0__LPCG_CLK_BASE                (0x58223000u)
/** Peripheral MIPI_CSI_0__LPCG_CLK base pointer */
#define MIPI_CSI_0__LPCG_CLK                     ((MIPI_CSI_LPCG_Type *)MIPI_CSI_0__LPCG_CLK_BASE)
/** Peripheral MIPI_CSI_1__LPCG_CLK base address */
#define MIPI_CSI_1__LPCG_CLK_BASE                (0x58243000u)
/** Peripheral MIPI_CSI_1__LPCG_CLK base pointer */
#define MIPI_CSI_1__LPCG_CLK                     ((MIPI_CSI_LPCG_Type *)MIPI_CSI_1__LPCG_CLK_BASE)
/** Array initializer of MIPI_CSI_LPCG peripheral base addresses */
#define MIPI_CSI_LPCG_BASE_ADDRS                 { MIPI_CSI_0__LPCG_CLK_BASE, MIPI_CSI_1__LPCG_CLK_BASE }
/** Array initializer of MIPI_CSI_LPCG peripheral base pointers */
#define MIPI_CSI_LPCG_BASE_PTRS                  { MIPI_CSI_0__LPCG_CLK, MIPI_CSI_1__LPCG_CLK }

/*!
 * @}
 */ /* end of group MIPI_CSI_LPCG_Peripheral_Access_Layer */
 

/** MIPI_CSI_CSR - Register Layout Typedef */
typedef struct {
    __IO uint32_t PLM_CTRL;
    __IO uint32_t PHY_CTRL;
    __IO uint32_t PHY_STATUS;
       uint8_t RESERVED_0[36];
    __IO uint32_t VC_INTERLACED;
       uint8_t RESERVED_1[4];
    __IO uint32_t DATA_TYPE_DIS;
       uint8_t RESERVED_2[4];
    __IO uint32_t YUV420_FIRST_LINE_DATA_TYPE;
    __IO uint32_t CONTROLLER_CLOCK_RESET_CONTROL;
    __IO uint32_t STREAM_FENCING_CTRL;
} MIPI_CSI_CSR_Type;

#define MIPI_CSI_CSR_PLM_CTRL_ENABLE_MASK (0x01UL)
#define MIPI_CSI_CSR_PLM_CTRL_ADDR_MASK (0x03UL << 1U)
#define MIPI_CSI_CSR_PLM_CTRL_OVERRIDE_MASK (1UL << 8U)
#define MIPI_CSI_CSR_PLM_CTRL_VSYNC_OVERRIDE_MASK (1UL << 9U)
#define MIPI_CSI_CSR_PLM_CTRL_HSYNC_OVERRIDE_MASK (1UL << 10U)
#define MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE_MASK (1UL << 11U)
#define MIPI_CSI_CSR_PLM_CTRL_POLARITY_MASK (1UL << 12U)
#define MIPI_CSI_CSR_PLM_CTRL_PL_CLOCK_RUNNING_MASK (1UL << 31U)

#define MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_MASK (1UL << 0U)
#define MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN_MASK (1UL << 1U)
#define MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN_MASK (1UL << 2U)
#define MIPI_CSI_CSR_PHY_CTRL_CONTI_CLK_MODE_MASK (1UL << 3U)
#define MIPI_CSI_CSR_PHY_CTRL_PRG_RXHS_SETTLE_MASK (0x3FUL << 4U)
#define MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL_MASK (1UL << 21U)
#define MIPI_CSI_CSR_PHY_CTRL_PD_MASK (1UL << 22U)
#define MIPI_CSI_CSR_PHY_CTRL_PRG_RXHS_SETTLE(x) ((((uint32_t)(x)) & 0x3FUL)<< 4U)

#define MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CTL_CLK_OFF_MASK (1UL << 1U)
#define MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_SW_RESET_MASK (1UL << 0U)

#define MIPI_CSI_CSR0_BASE                       (0x58221000u)
#define MIPI_CSI_CSR0                            ((MIPI_CSI_CSR_Type*)MIPI_CSI_CSR0_BASE)
#define MIPI_CSI_CSR1_BASE                       (0x58241000u)
#define MIPI_CSI_CSR1                            ((MIPI_CSI_CSR_Type*)MIPI_CSI_CSR1_BASE)
#define MIPI_CSI_CSR_BASE_ADDRS                  { MIPI_CSI_CSR0_BASE, MIPI_CSI_CSR1_BASE }
#define MIPI_CSI_CSR_BASE_PTRS                   { MIPI_CSI_CSR0, MIPI_CSI_CSR1 }


/* ----------------------------------------------------------------------------
   -- MMCAU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MMCAU_Peripheral_Access_Layer MMCAU Peripheral Access Layer
 * @{
 */

/** MMCAU - Register Layout Typedef */
typedef struct {
  __IO uint32_t CASR;                              /**< Status Register, offset: 0x0 */
  __IO uint32_t CAA;                               /**< Accumulator, offset: 0x4 */
  __IO uint32_t CA[9];                             /**< General Purpose Register, array offset: 0x8, array step: 0x4 */
} MMCAU_Type;

/* ----------------------------------------------------------------------------
   -- MMCAU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MMCAU_Register_Masks MMCAU Register Masks
 * @{
 */

/*! @name CASR - Status Register */
/*! @{ */
#define MMCAU_CASR_IC_MASK                       (0x1U)
#define MMCAU_CASR_IC_SHIFT                      (0U)
/*! IC - Illegal Command
 *  0b0..No illegal commands issued.
 *  0b1..Illegal command issued.
 */
#define MMCAU_CASR_IC(x)                         (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_IC_SHIFT)) & MMCAU_CASR_IC_MASK)
#define MMCAU_CASR_DPE_MASK                      (0x2U)
#define MMCAU_CASR_DPE_SHIFT                     (1U)
/*! DPE - DES Parity Error
 *  0b0..No error detected.
 *  0b1..DES key parity error detected.
 */
#define MMCAU_CASR_DPE(x)                        (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_DPE_SHIFT)) & MMCAU_CASR_DPE_MASK)
#define MMCAU_CASR_VER_MASK                      (0xF0000000U)
#define MMCAU_CASR_VER_SHIFT                     (28U)
/*! VER - CAU Version
 *  0b0001..Initial CAU version.
 */
#define MMCAU_CASR_VER(x)                        (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_VER_SHIFT)) & MMCAU_CASR_VER_MASK)
/*! @} */

/*! @name CAA - Accumulator */
/*! @{ */
#define MMCAU_CAA_ACC_MASK                       (0xFFFFFFFFU)
#define MMCAU_CAA_ACC_SHIFT                      (0U)
#define MMCAU_CAA_ACC(x)                         (((uint32_t)(((uint32_t)(x)) << MMCAU_CAA_ACC_SHIFT)) & MMCAU_CAA_ACC_MASK)
/*! @} */

/*! @name CA - General Purpose Register */
/*! @{ */
#define MMCAU_CA_CAn_MASK                        (0xFFFFFFFFU)
#define MMCAU_CA_CAn_SHIFT                       (0U)
#define MMCAU_CA_CAn(x)                          (((uint32_t)(((uint32_t)(x)) << MMCAU_CA_CAn_SHIFT)) & MMCAU_CA_CAn_MASK)
/*! @} */

/* The count of MMCAU_CA */
#define MMCAU_CA_COUNT                           (9U)


/*!
 * @}
 */ /* end of group MMCAU_Register_Masks */


/* MMCAU - Peripheral instance base addresses */
/** Peripheral MMCAU base address */
#define MMCAU_BASE                               (0xE0081000u)
/** Peripheral MMCAU base pointer */
#define MMCAU                                    ((MMCAU_Type *)MMCAU_BASE)
/** Array initializer of MMCAU peripheral base addresses */
#define MMCAU_BASE_ADDRS                         { MMCAU_BASE }
/** Array initializer of MMCAU peripheral base pointers */
#define MMCAU_BASE_PTRS                          { MMCAU }

/*!
 * @}
 */ /* end of group MMCAU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MQS_REGS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MQS_REGS_Peripheral_Access_Layer MQS_REGS Peripheral Access Layer
 * @{
 */

/** MQS_REGS - Register Layout Typedef */
typedef struct {
  __IO uint32_t MQS_CTL;                           /**< Pixel Mux configuration, offset: 0x0 */
} MQS_REGS_Type;

/* ----------------------------------------------------------------------------
   -- MQS_REGS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MQS_REGS_Register_Masks MQS_REGS Register Masks
 * @{
 */

/*! @name MQS_CTL - Pixel Mux configuration */
/*! @{ */
#define MQS_REGS_MQS_CTL_DIV_MASK                (0xFFU)
#define MQS_REGS_MQS_CTL_DIV_SHIFT               (0U)
#define MQS_REGS_MQS_CTL_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << MQS_REGS_MQS_CTL_DIV_SHIFT)) & MQS_REGS_MQS_CTL_DIV_MASK)
#define MQS_REGS_MQS_CTL_OVR_MASK                (0x100000U)
#define MQS_REGS_MQS_CTL_OVR_SHIFT               (20U)
#define MQS_REGS_MQS_CTL_OVR(x)                  (((uint32_t)(((uint32_t)(x)) << MQS_REGS_MQS_CTL_OVR_SHIFT)) & MQS_REGS_MQS_CTL_OVR_MASK)
#define MQS_REGS_MQS_CTL_RST_MASK                (0x1000000U)
#define MQS_REGS_MQS_CTL_RST_SHIFT               (24U)
#define MQS_REGS_MQS_CTL_RST(x)                  (((uint32_t)(((uint32_t)(x)) << MQS_REGS_MQS_CTL_RST_SHIFT)) & MQS_REGS_MQS_CTL_RST_MASK)
#define MQS_REGS_MQS_CTL_ENB_MASK                (0x10000000U)
#define MQS_REGS_MQS_CTL_ENB_SHIFT               (28U)
#define MQS_REGS_MQS_CTL_ENB(x)                  (((uint32_t)(((uint32_t)(x)) << MQS_REGS_MQS_CTL_ENB_SHIFT)) & MQS_REGS_MQS_CTL_ENB_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MQS_REGS_Register_Masks */


/* MQS_REGS - Peripheral instance base addresses */
/** Peripheral AUDIO__MQS_REGS base address */
#define AUDIO__MQS_REGS_BASE                     (0x59850000u)
/** Peripheral AUDIO__MQS_REGS base pointer */
#define AUDIO__MQS_REGS                          ((MQS_REGS_Type *)AUDIO__MQS_REGS_BASE)
/** Array initializer of MQS_REGS peripheral base addresses */
#define MQS_REGS_BASE_ADDRS                      { AUDIO__MQS_REGS_BASE }
/** Array initializer of MQS_REGS peripheral base pointers */
#define MQS_REGS_BASE_PTRS                       { AUDIO__MQS_REGS }

/*!
 * @}
 */ /* end of group MQS_REGS_Peripheral_Access_Layer */
 

/* ----------------------------------------------------------------------------
   -- MIPI_DSI_HOST Peripheral Access Layer
   ---------------------------------------------------------------------------- */
 
 
/*!
 * @addtogroup MIPI_DSI_HOST_Peripheral_Access_Layer MIPI_DSI_HOST Peripheral Access Layer
 * @{
 */

/** MIPI_DSI_HOST - Register Layout Typedef */
typedef struct {
  __IO uint32_t DSI_HOST_CFG_NUM_LANES;            /**< DSI_HOST_CFG_NUM_LANES, offset: 0x0 */
  __IO uint32_t DSI_HOST_CFG_NONCONTINUOUS_CLK;    /**< DSI_HOST_CFG_NONCONTINUOUS_CLK, offset: 0x4 */
  __IO uint32_t DSI_HOST_CFG_T_PRE;                /**< DSI_HOST_CFG_T_PRE, offset: 0x8 */
  __IO uint32_t DSI_HOST_CFG_T_POST;               /**< DSI_HOST_CFG_T_POST, offset: 0xC */
  __IO uint32_t DSI_HOST_CFG_TX_GAP;               /**< DSI_HOST_CFG_TX_GAP, offset: 0x10 */
  __IO uint32_t DSI_HOST_CFG_AUTOINSERT_EOTP;      /**< DSI_HOST_CFG_AUTOINSERT_EOTP, offset: 0x14 */
  __IO uint32_t DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP; /**< DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP, offset: 0x18 */
  __IO uint32_t DSI_HOST_CFG_HTX_TO_COUNT;         /**< DSI_HOST_CFG_HTX_TO_COUNT, offset: 0x1C */
  __IO uint32_t DSI_HOST_CFG_LRX_H_TO_COUNT;       /**< DSI_HOST_CFG_LRX_H_TO_COUNT, offset: 0x20 */
  __IO uint32_t DSI_HOST_CFG_BTA_H_TO_COUNT;       /**< DSI_HOST_CFG_BTA_H_TO_COUNT, offset: 0x24 */
  __IO uint32_t DSI_HOST_CFG_TWAKEUP;              /**< DSI_HOST_CFG_TWAKEUP, offset: 0x28 */
  __I  uint32_t DSI_HOST_CFG_STATUS_OUT;           /**< DSI_HOST_CFG_STATUS_OUT, offset: 0x2C */
  __IO uint32_t DSI_HOST_RX_ERROR_STATUS;          /**< DSI_HOST_RX_ERROR_STATUS, offset: 0x30 */
       uint8_t RESERVED_0[460];
  __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE; /**< DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE, offset: 0x200 */
  __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL; /**< DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL, offset: 0x204 */
  __IO uint32_t DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING; /**< DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING, offset: 0x208 */
  __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FORMAT;     /**< DSI_HOST_CFG_DPI_PIXEL_FORMAT, offset: 0x20C */
  __IO uint32_t DSI_HOST_CFG_DPI_VSYNC_POLARITY;   /**< DSI_HOST_CFG_DPI_VSYNC_POLARITY, offset: 0x210 */
  __IO uint32_t DSI_HOST_CFG_DPI_HSYNC_POLARITY;   /**< DSI_HOST_CFG_DPI_HSYNC_POLARITY, offset: 0x214 */
  __IO uint32_t DSI_HOST_CFG_DPI_VIDEO_MODE;       /**< DSI_HOST_CFG_DPI_VIDEO_MODE, offset: 0x218 */
  __IO uint32_t DSI_HOST_CFG_DPI_HFP;              /**< DSI_HOST_CFG_DPI_HFP, offset: 0x21C */
  __IO uint32_t DSI_HOST_CFG_DPI_HBP;              /**< DSI_HOST_CFG_DPI_HBP, offset: 0x220 */
  __IO uint32_t DSI_HOST_CFG_DPI_HSA;              /**< DSI_HOST_CFG_DPI_HSA, offset: 0x224 */
  __IO uint32_t DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS; /**< DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS, offset: 0x228 */
  __IO uint32_t DSI_HOST_CFG_DPI_VBP;              /**< DSI_HOST_CFG_DPI_VBP, offset: 0x22C */
  __IO uint32_t DSI_HOST_CFG_DPI_VFP;              /**< DSI_HOST_CFG_DPI_VFP, offset: 0x230 */
  __IO uint32_t DSI_HOST_CFG_DPI_BLLP_MODE;        /**< DSI_HOST_CFG_DPI_BLLP_MODE, offset: 0x234 */
  __IO uint32_t DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP; /**< DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP, offset: 0x238 */
  __IO uint32_t DSI_HOST_CFG_DPI_VACTIVE;          /**< DSI_HOST_CFG_DPI_VACTIVE, offset: 0x23C */
  __IO uint32_t DSI_HOST_CFG_DPI_VC;               /**< DSI_HOST_CFG_DPI_VC, offset: 0x240 */
       uint8_t RESERVED_1[60];
  __IO uint32_t DSI_HOST_TX_PAYLOAD;               /**< DSI_HOST_TX_PAYLOAD, offset: 0x280 */
  __IO uint32_t DSI_HOST_PKT_CONTROL;              /**< DSI_HOST_PKT_CONTROL, offset: 0x284 */
  __IO uint32_t DSI_HOST_SEND_PACKET;              /**< DSI_HOST_SEND_PACKET, offset: 0x288 */
  __IO uint32_t DSI_HOST_PKT_STATUS;               /**< DSI_HOST_PKT_STATUS, offset: 0x28C */
  __IO uint32_t DSI_HOST_PKT_FIFO_WR_LEVEL;        /**< DSI_HOST_PKT_FIFO_WR_LEVEL, offset: 0x290 */
  __IO uint32_t DSI_HOST_PKT_FIFO_RD_LEVEL;        /**< DSI_HOST_PKT_FIFO_RD_LEVEL, offset: 0x294 */
  __I  uint32_t DSI_HOST_PKT_RX_PAYLOAD;           /**< DSI_HOST_PKT_RX_PAYLOAD, offset: 0x298 */
  __IO uint32_t DSI_HOST_PKT_RX_PKT_HEADER;        /**< DSI_HOST_PKT_RX_PKT_HEADER, offset: 0x29C */
  __I  uint32_t DSI_HOST_IRQ_STATUS;               /**< DSI_HOST_IRQ_STATUS, offset: 0x2A0 */
  __IO uint32_t DSI_HOST_IRQ_STATUS2;              /**< DSI_HOST_IRQ_STATUS2, offset: 0x2A4 */
  __IO uint32_t DSI_HOST_IRQ_MASK;                 /**< DSI_HOST_IRQ_MASK, offset: 0x2A8 */
  __IO uint32_t DSI_HOST_IRQ_MASK2;                /**< DSI_HOST_IRQ_MASK2, offset: 0x2AC */
       uint8_t RESERVED_2[80];
  __IO uint32_t DPHY_PD_TX;                        /**< DPHY_PD_TX, offset: 0x300 */
  __IO uint32_t DPHY_M_PRG_HS_PREPARE;             /**< DPHY_M_PRG_HS_PREPARE, offset: 0x304 */
  __IO uint32_t DPHY_MC_PRG_HS_PREPARE;            /**< DPHY_MC_PRG_HS_PREPARE, offset: 0x308 */
  __IO uint32_t DPHY_M_PRG_HS_ZERO;                /**< DPHY_M_PRG_HS_ZERO, offset: 0x30C */
  __IO uint32_t DPHY_MC_PRG_HS_ZERO;               /**< DPHY_MC_PRG_HS_ZERO, offset: 0x310 */
  __IO uint32_t DPHY_M_PRG_HS_TRAIL;               /**< DPHY_M_PRG_HS_TRAIL, offset: 0x314 */
  __IO uint32_t DPHY_MC_PRG_HS_TRAIL;              /**< DPHY_MC_PRG_HS_TRAIL, offset: 0x318 */
  __IO uint32_t DPHY_PD_PLL;                       /**< DPHY_PD_PLL, offset: 0x31C */
  __IO uint32_t DPHY_TST;                          /**< DPHY_TST, offset: 0x320 */
  __IO uint32_t DPHY_CN;                           /**< DPHY_CN, offset: 0x324 */
  __IO uint32_t DPHY_CM;                           /**< DPHY_CM, offset: 0x328 */
  __IO uint32_t DPHY_CO;                           /**< DPHY_CO, offset: 0x32C */
  __IO uint32_t DPHY_LOCK;                         /**< DPHY_LOCK, offset: 0x330 */
  __IO uint32_t DPHY_LOCK_BYP;                     /**< DPHY_LOCK_BYP, offset: 0x334 */
  __IO uint32_t DPHY_TX_RCAL;                      /**< DPHY_TX_RCAL, offset: 0x338 */
  __IO uint32_t DPHY_AUTO_PD_EN;                   /**< DPHY_AUTO_PD_EN, offset: 0x33C */
  __IO uint32_t DPHY_RXLPRP;                       /**< DPHY_RXLPRP, offset: 0x340 */
  __IO uint32_t DPHY_RXCDRP;                       /**< DPHY_RXCDRP, offset: 0x344 */
} MIPI_DSI_HOST_Type;

/* ----------------------------------------------------------------------------
   -- MIPI_DSI_HOST Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_DSI_HOST_Register_Masks MIPI_DSI_HOST Register Masks
 * @{
 */

/*! @name DSI_HOST_CFG_NUM_LANES - DSI_HOST_CFG_NUM_LANES */
#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK (0x3U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK)

/*! @name DSI_HOST_CFG_NONCONTINUOUS_CLK - DSI_HOST_CFG_NONCONTINUOUS_CLK */
#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK)

/*! @name DSI_HOST_CFG_T_PRE - DSI_HOST_CFG_T_PRE */
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK (0xFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK)

/*! @name DSI_HOST_CFG_T_POST - DSI_HOST_CFG_T_POST */
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK (0xFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK)

/*! @name DSI_HOST_CFG_TX_GAP - DSI_HOST_CFG_TX_GAP */
#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_ap_MASK (0xFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_ap_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_ap(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_ap_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_ap_MASK)

/*! @name DSI_HOST_CFG_AUTOINSERT_EOTP - DSI_HOST_CFG_AUTOINSERT_EOTP */
#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK)

/*! @name DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP - DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP */
#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK (0xFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK)

/*! @name DSI_HOST_CFG_HTX_TO_COUNT - DSI_HOST_CFG_HTX_TO_COUNT */
#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK)

/*! @name DSI_HOST_CFG_LRX_H_TO_COUNT - DSI_HOST_CFG_LRX_H_TO_COUNT */
#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK)

/*! @name DSI_HOST_CFG_BTA_H_TO_COUNT - DSI_HOST_CFG_BTA_H_TO_COUNT */
#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK)

/*! @name DSI_HOST_CFG_TWAKEUP - DSI_HOST_CFG_TWAKEUP */
#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK (0x7FFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK)

/*! @name DSI_HOST_CFG_STATUS_OUT - DSI_HOST_CFG_STATUS_OUT */
#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_MASK)

/*! @name DSI_HOST_RX_ERROR_STATUS - DSI_HOST_RX_ERROR_STATUS */
#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK (0x7FFU)
#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK)

/*! @name DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE - DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK)

/*! @name DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL - DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK)

/*! @name DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING - DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK (0x7U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK)

/*! @name DSI_HOST_CFG_DPI_PIXEL_FORMAT - DSI_HOST_CFG_DPI_PIXEL_FORMAT */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK (0x3U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK)

/*! @name DSI_HOST_CFG_DPI_VSYNC_POLARITY - DSI_HOST_CFG_DPI_VSYNC_POLARITY */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK)

/*! @name DSI_HOST_CFG_DPI_HSYNC_POLARITY - DSI_HOST_CFG_DPI_HSYNC_POLARITY */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK)

/*! @name DSI_HOST_CFG_DPI_VIDEO_MODE - DSI_HOST_CFG_DPI_VIDEO_MODE */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK (0x3U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK)

/*! @name DSI_HOST_CFG_DPI_HFP - DSI_HOST_CFG_DPI_HFP */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK)

/*! @name DSI_HOST_CFG_DPI_HBP - DSI_HOST_CFG_DPI_HBP */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK)

/*! @name DSI_HOST_CFG_DPI_HSA - DSI_HOST_CFG_DPI_HSA */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK)

/*! @name DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS - DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK)

/*! @name DSI_HOST_CFG_DPI_VBP - DSI_HOST_CFG_DPI_VBP */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK (0xFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK)

/*! @name DSI_HOST_CFG_DPI_VFP - DSI_HOST_CFG_DPI_VFP */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK (0xFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK)

/*! @name DSI_HOST_CFG_DPI_BLLP_MODE - DSI_HOST_CFG_DPI_BLLP_MODE */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK)

/*! @name DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP - DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK)

/*! @name DSI_HOST_CFG_DPI_VACTIVE - DSI_HOST_CFG_DPI_VACTIVE */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK (0x3FFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK)

/*! @name DSI_HOST_CFG_DPI_VC - DSI_HOST_CFG_DPI_VC */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK (0x3U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK)

/*! @name DSI_HOST_TX_PAYLOAD - DSI_HOST_TX_PAYLOAD */
#define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK)

/*! @name DSI_HOST_PKT_CONTROL - DSI_HOST_PKT_CONTROL */
#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK (0x7FFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK)

/*! @name DSI_HOST_SEND_PACKET - DSI_HOST_SEND_PACKET */
#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK)

/*! @name DSI_HOST_PKT_STATUS - DSI_HOST_PKT_STATUS */
#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK (0x1FFU)
#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK)

/*! @name DSI_HOST_PKT_FIFO_WR_LEVEL - DSI_HOST_PKT_FIFO_WR_LEVEL */
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK)

/*! @name DSI_HOST_PKT_FIFO_RD_LEVEL - DSI_HOST_PKT_FIFO_RD_LEVEL */
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK)

/*! @name DSI_HOST_PKT_RX_PAYLOAD - DSI_HOST_PKT_RX_PAYLOAD */
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK)

/*! @name DSI_HOST_PKT_RX_PKT_HEADER - DSI_HOST_PKT_RX_PKT_HEADER */
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK)

/*! @name DSI_HOST_IRQ_STATUS - DSI_HOST_IRQ_STATUS */
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK)

/*! @name DSI_HOST_IRQ_STATUS2 - DSI_HOST_IRQ_STATUS2 */
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK (0x7U)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK)

/*! @name DSI_HOST_IRQ_MASK - DSI_HOST_IRQ_MASK */
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK)

/*! @name DSI_HOST_IRQ_MASK2 - DSI_HOST_IRQ_MASK2 */
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK (0x7U)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT (0U)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK)

/*! @name DPHY_PD_TX - DPHY_PD_TX */
#define MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_MASK (0x1U)
#define MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_SHIFT (0U)
#define MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_MASK)

/*! @name DPHY_M_PRG_HS_PREPARE - DPHY_M_PRG_HS_PREPARE */
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK (0x3U)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT (0U)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK)

/*! @name DPHY_MC_PRG_HS_PREPARE - DPHY_MC_PRG_HS_PREPARE */
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK (0x1U)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT (0U)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK)

/*! @name DPHY_M_PRG_HS_ZERO - DPHY_M_PRG_HS_ZERO */
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK (0x1FU)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT (0U)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK)

/*! @name DPHY_MC_PRG_HS_ZERO - DPHY_MC_PRG_HS_ZERO */
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK (0x3FU)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT (0U)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK)

/*! @name DPHY_M_PRG_HS_TRAIL - DPHY_M_PRG_HS_TRAIL */
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK (0xFU)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT (0U)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK)

/*! @name DPHY_MC_PRG_HS_TRAIL - DPHY_MC_PRG_HS_TRAIL */
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK (0xFU)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT (0U)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK)

/*! @name DPHY_PD_PLL - DPHY_PD_PLL */
#define MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_MASK (0x1U)
#define MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_SHIFT (0U)
#define MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_MASK)

/*! @name DPHY_TST - DPHY_TST */
#define MIPI_DSI_HOST_DPHY_TST_dphy_tst_MASK     (0x3FU)
#define MIPI_DSI_HOST_DPHY_TST_dphy_tst_SHIFT    (0U)
#define MIPI_DSI_HOST_DPHY_TST_dphy_tst(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TST_dphy_tst_SHIFT)) & MIPI_DSI_HOST_DPHY_TST_dphy_tst_MASK)

/*! @name DPHY_CN - DPHY_CN */
#define MIPI_DSI_HOST_DPHY_CN_dphy_cn_MASK       (0x1FU)
#define MIPI_DSI_HOST_DPHY_CN_dphy_cn_SHIFT      (0U)
#define MIPI_DSI_HOST_DPHY_CN_dphy_cn(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CN_dphy_cn_SHIFT)) & MIPI_DSI_HOST_DPHY_CN_dphy_cn_MASK)

/*! @name DPHY_CM - DPHY_CM */
#define MIPI_DSI_HOST_DPHY_CM_dphy_cm_MASK       (0xFFU)
#define MIPI_DSI_HOST_DPHY_CM_dphy_cm_SHIFT      (0U)
#define MIPI_DSI_HOST_DPHY_CM_dphy_cm(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CM_dphy_cm_SHIFT)) & MIPI_DSI_HOST_DPHY_CM_dphy_cm_MASK)

/*! @name DPHY_CO - DPHY_CO */
#define MIPI_DSI_HOST_DPHY_CO_dphy_co_MASK       (0x3U)
#define MIPI_DSI_HOST_DPHY_CO_dphy_co_SHIFT      (0U)
#define MIPI_DSI_HOST_DPHY_CO_dphy_co(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CO_dphy_co_SHIFT)) & MIPI_DSI_HOST_DPHY_CO_dphy_co_MASK)

/*! @name DPHY_LOCK - DPHY_LOCK */
#define MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_MASK   (0x1U)
#define MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_SHIFT  (0U)
#define MIPI_DSI_HOST_DPHY_LOCK_dphy_lock(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_SHIFT)) & MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_MASK)

/*! @name DPHY_LOCK_BYP - DPHY_LOCK_BYP */
#define MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_MASK (0x1U)
#define MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT (0U)
#define MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT)) & MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_MASK)

/*! @name DPHY_TX_RCAL - DPHY_TX_RCAL */
#define MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_MASK (0x3U)
#define MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_SHIFT (0U)
#define MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_SHIFT)) & MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_MASK)

/*! @name DPHY_AUTO_PD_EN - DPHY_AUTO_PD_EN */
#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK (0x1U)
#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT (0U)
#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT)) & MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK)

/*! @name DPHY_RXLPRP - DPHY_RXLPRP */
#define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_MASK (0x3U)
#define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_SHIFT (0U)
#define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_SHIFT)) & MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_MASK)

/*! @name DPHY_RXCDRP - DPHY_RXCDRP */
#define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_MASK (0x3U)
#define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_SHIFT (0U)
#define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_SHIFT)) & MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_MASK)


/*!
 * @}
 */ /* end of group MIPI_DSI_HOST_Register_Masks */


/* MIPI_DSI_HOST - Peripheral instance base addresses */
/** Peripheral MIPI_DSI_HOST0 base address */
#define MIPI_DSI_HOST0_BASE                      (0x56228000u)
/** Peripheral MIPI_DSI_HOST0 base pointer */
#define MIPI_DSI_HOST0                           ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST0_BASE)
/** Peripheral MIPI_DSI_HOST1 base address */
#define MIPI_DSI_HOST1_BASE                      (0x57228000u)
/** Peripheral MIPI_DSI_HOST1 base pointer */
#define MIPI_DSI_HOST1                           ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST1_BASE)
/** Array initializer of MIPI_DSI_HOST peripheral base addresses */
#define MIPI_DSI_HOST_BASE_ADDRS                 { MIPI_DSI_HOST0_BASE, MIPI_DSI_HOST1_BASE }
/** Array initializer of MIPI_DSI_HOST peripheral base pointers */
#define MIPI_DSI_HOST_BASE_PTRS                  { MIPI_DSI_HOST0, MIPI_DSI_HOST1 }

/** MIPI_DSI_CSR - Register Layout Typedef */
typedef struct {
  __IO uint32_t TX_ULPS_ENABLE;            /**< TX_ULPS_ENABLE, offset: 0x0 */
  __IO uint32_t PXL2DPI_CONFIG;            /**< PXL2DPI_CONFIG, offset: 0x0 */
} MIPI_DSI_CSR_Type;

#define MIPI_DSI_TX_ULPS_ENABLE_TX_ULPS_ENABLE_MASK  (0x1FU)
#define MIPI_DSI_TX_ULPS_ENABLE_TX_ULPS_ENABLE_SHIFT (0x0U)
#define MIPI_DSI_TX_ULPS_ENABLE_TX_ULPS_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_TX_ULPS_ENABLE_TX_ULPS_ENABLE_SHIFT)) & MIPI_DSI_TX_ULPS_ENABLE_TX_ULPS_ENABLE_MASK)
#define MIPI_DSI_PXL2DPI_CONFIG_PXL2DPI_CONFIG_MASK  (0x07U)
#define MIPI_DSI_PXL2DPI_CONFIG_PXL2DPI_CONFIG_SHIFT (0x0U)
#define MIPI_DSI_PXL2DPI_CONFIG_PXL2DPI_CONFIG(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PXL2DPI_CONFIG_PXL2DPI_CONFIG_SHIFT)) & MIPI_DSI_PXL2DPI_CONFIG_PXL2DPI_CONFIG_MASK)

#define MIPI_DSI_CSR0_BASE                       (0x56221000u)
#define MIPI_DSI_CSR0                            ((MIPI_DSI_CSR_Type*)MIPI_DSI_CSR0_BASE)
#define MIPI_DSI_CSR1_BASE                       (0x57221000u)
#define MIPI_DSI_CSR1                            ((MIPI_DSI_CSR_Type*)MIPI_DSI_CSR1_BASE)
#define MIPI_DSI_CSR_BASE_ADDRS                  { MIPI_DSI_CSR0_BASE, MIPI_DSI_CSR1_BASE }
#define MIPI_DSI_CSR_BASE_PTRS                   { MIPI_DSI_CSR0, MIPI_DSI_CSR1 }

/*!
 * @}
 */ /* end of group MIPI_DSI_HOST_Peripheral_Access_Layer */
 
 
/* ----------------------------------------------------------------------------
   -- MU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
 * @{
 */

/*!
 * @brief Core B boot mode.
 */
typedef enum _mu_core_boot_mode
{
    kMU_CoreBootFromAddr0 = 0x00U, /*!< Boot from 0x00.      */
    kMU_CoreBootFromDmem = 0x01U,  /*!< Boot from DMEM base. */
    kMU_CoreBootFromImem = 0x02U   /*!< Boot from IMEM base. */
} mu_core_boot_mode_t;

/*!
 * @brief Power mode definition.
 */
typedef enum _mu_power_mode
{
    kMU_PowerModeRun = 0x00U,  /*!< Run mode.           */
    kMU_PowerModeWait = 0x01U, /*!< WAIT mode.          */
    kMU_PowerModeStop = 0x02U, /*!< STOP/VLPS mode.     */
    kMU_PowerModeDsm = 0x03U   /*!< DSM: LLS/VLLS mode. */
} mu_power_mode_t;

/*!
 * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
 * @{
 */

/** MU - Register Layout Typedef */
typedef struct {
  __IO uint32_t TR[4];                             /**< Transmit Register, array offset: 0x00, array step: 0x4 */
  __I  uint32_t RR[4];                             /**< Receive Register, array offset: 0x10, array step: 0x4 */
  __IO uint32_t SR;                                /**< Status Register, offset: 0x20 */
  __IO uint32_t CR;                                /**< Control Register, offset: 0x24 */
} MU_Type;

/* ----------------------------------------------------------------------------
   -- MU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MU_Register_Masks MU Register Masks
 * @{
 */

/*! @name TR - Transmit Register */
#define MU_TR_DATA_MASK                          (0xFFFFFFFFU)
#define MU_TR_DATA_SHIFT                         (0U)
#define MU_TR_DATA(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK)

/* The count of MU_TR */
#define MU_TR_COUNT                              (4U)

/*! @name RR - Receive Register */
#define MU_RR_DATA_MASK                          (0xFFFFFFFFU)
#define MU_RR_DATA_SHIFT                         (0U)
#define MU_RR_DATA(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)

/* The count of MU_RR */
#define MU_RR_COUNT                              (4U)

/*! @name SR - Status Register */
#define MU_SR_Fn_MASK                            (0x7U)
#define MU_SR_Fn_SHIFT                           (0U)
#define MU_SR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
#define MU_SR_NMIC_MASK                          (0x8U)
#define MU_SR_NMIC_SHIFT                         (3U)
#define MU_SR_NMIC(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_NMIC_SHIFT)) & MU_SR_NMIC_MASK)
#define MU_SR_EP_MASK                            (0x10U)
#define MU_SR_EP_SHIFT                           (4U)
#define MU_SR_EP(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
#define MU_SR_PM_MASK                            (0x60U)
#define MU_SR_PM_SHIFT                           (5U)
#define MU_SR_PM(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_PM_SHIFT)) & MU_SR_PM_MASK)
#define MU_SR_FUP_MASK                           (0x100U)
#define MU_SR_FUP_SHIFT                          (8U)
#define MU_SR_FUP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
#define MU_SR_TEn_MASK                           (0xF00000U)
#define MU_SR_TEn_SHIFT                          (20U)
#define MU_SR_TEn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
#define MU_SR_RFn_MASK                           (0xF000000U)
#define MU_SR_RFn_SHIFT                          (24U)
#define MU_SR_RFn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
#define MU_SR_GIPn_MASK                          (0xF0000000U)
#define MU_SR_GIPn_SHIFT                         (28U)
#define MU_SR_GIPn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)

/*! @name CR - Control Register */
#define MU_CR_Fn_MASK                            (0x7U)
#define MU_CR_Fn_SHIFT                           (0U)
#define MU_CR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)
#define MU_CR_NMI_MASK                           (0x8U)
#define MU_CR_NMI_SHIFT                          (3U)
#define MU_CR_NMI(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_NMI_SHIFT)) & MU_CR_NMI_MASK)
#define MU_CR_HR_MASK                            (0x10U)
#define MU_CR_HR_SHIFT                           (4U)
#define MU_CR_HR(x)                              (((uint32_t)(((uint32_t)(x)) << MU_CR_BHR_SHIFT)) & MU_CR_BHR_MASK)
#define MU_CR_MUR_MASK                           (0x20U)
#define MU_CR_MUR_SHIFT                          (5U)
#define MU_CR_MUR(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
#define MU_CR_BRSTH_MASK                         (0x80U)
#define MU_CR_BRSTH_SHIFT                        (7U)
#define MU_CR_BRSTH(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CR_BRSTH_SHIFT)) & MU_CR_BRSTH_MASK)
#define MU_CR_CLKE_MASK                          (0x100U)
#define MU_CR_CLKE_SHIFT                         (8U)
#define MU_CR_CLKE(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_CLKE_SHIFT)) & MU_CR_CLKE_MASK)
#define MU_CR_BBOOT_MASK                         (0x600U)
#define MU_CR_BBOOT_SHIFT                        (9U)
#define MU_CR_BBOOT(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CR_BBOOT_SHIFT)) & MU_CR_BBOOT_MASK)
#define MU_CR_GIRn_MASK                          (0xF0000U)
#define MU_CR_GIRn_SHIFT                         (16U)
#define MU_CR_GIRn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
#define MU_CR_TIEn_MASK                          (0xF00000U)
#define MU_CR_TIEn_SHIFT                         (20U)
#define MU_CR_TIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
#define MU_CR_RIEn_MASK                          (0xF000000U)
#define MU_CR_RIEn_SHIFT                         (24U)
#define MU_CR_RIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
#define MU_CR_GIEn_MASK                          (0xF0000000U)
#define MU_CR_GIEn_SHIFT                         (28U)
#define MU_CR_GIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)

/* Backward compatibility */
#define MU_CR_BOOT_MASK  MU_CR_BBOOT_MASK
#define MU_CR_BOOT(x)  MU_CR_BBOOT(x)
#define MU_CR_RSTH_MASK MU_CR_BRSTH_MASK
#define MU_CR_RSTH(x) MU_CR_BRSTH(x) 
/*!
 * @}
 */ /* end of group MU_Register_Masks */


/* MU - Peripheral instance base addresses */
/** Peripheral CM4_0__MU0_B0 base address */
#define CM4_0__MU0_B0_BASE                          (0x37430000u)
/** Peripheral CM4_0__MU0_B0 base pointer */
#define CM4_0__MU0_B0                               ((MU_Type *)CM4_0__MU0_B0_BASE)
/** Peripheral CM4_0__MU0_B1 base address */
#define CM4_0__MU0_B1_BASE                          (0x37430080u)
/** Peripheral CM4_0__MU0_B1 base pointer */
#define CM4_0__MU0_B1                               ((MU_Type *)CM4_0__MU0_B1_BASE)
/** Peripheral CM4_0__MU0_B2 base address */
#define CM4_0__MU0_B2_BASE                          (0x37430100u)
/** Peripheral CM4_0__MU0_B2 base pointer */
#define CM4_0__MU0_B2                               ((MU_Type *)CM4_0__MU0_B2_BASE)
/** Peripheral CM4_0__MU0_B3 base address */
#define CM4_0__MU0_B3_BASE                          (0x37430180u)
/** Peripheral CM4_0__MU0_B3 base pointer */
#define CM4_0__MU0_B3                               ((MU_Type *)CM4_0__MU0_B3_BASE)
/** Peripheral CM4_0__MU0_A0 base address */
#define CM4_0__MU0_A0_BASE                         (0x37440000u)
/** Peripheral CM4_0__MU0_A0 base pointer */
#define CM4_0__MU0_A0                              ((MU_Type *)CM4_0__MU0_A0_BASE)
/** Peripheral CM4_0__MU0_A1 base address */
#define CM4_0__MU0_A1_BASE                         (0x37450000u)
/** Peripheral CM4_0__MU0_A1 base pointer */
#define CM4_0__MU0_A1                              ((MU_Type *)CM4_0__MU0_A1_BASE)
/** Peripheral CM4_0__MU0_A2 base address */
#define CM4_0__MU0_A2_BASE                         (0x37460000u)
/** Peripheral CM4_0__MU0_A2 base pointer */
#define CM4_0__MU0_A2                              ((MU_Type *)CM4_0__MU0_A2_BASE)
/** Peripheral CM4_0__MU0_A3 base address */
#define CM4_0__MU0_A3_BASE                         (0x37470000u)
/** Peripheral CM4_0__MU0_A3 base pointer */
#define CM4_0__MU0_A3                              ((MU_Type *)CM4_0__MU0_A3_BASE)
/** Peripheral CM4_0__MU1_A base address */
#define CM4_0__MU1_A_BASE                          (0x37480000u)
/** Peripheral CM4_0__MU1_A base pointer */
#define CM4_0__MU1_A                               ((MU_Type *)CM4_0__MU1_A_BASE)
/** Peripheral CM4_1__MU0_B0 base address */
#define CM4_1__MU0_B0_BASE                          (0x41430000u)
/** Peripheral CM4_1__MU0_B0 base pointer */
#define CM4_1__MU0_B0                               ((MU_Type *)CM4_1__MU0_B0_BASE)
/** Peripheral CM4_1__MU0_B1 base address */
#define CM4_1__MU0_B1_BASE                          (0x41430080u)
/** Peripheral CM4_1__MU0_B1 base pointer */
#define CM4_1__MU0_B1                               ((MU_Type *)CM4_1__MU0_B1_BASE)
/** Peripheral CM4_1__MU0_B2 base address */
#define CM4_1__MU0_B2_BASE                          (0x41430100u)
/** Peripheral CM4_1__MU0_B2 base pointer */
#define CM4_1__MU0_B2                               ((MU_Type *)CM4_1__MU0_B2_BASE)
/** Peripheral CM4_1__MU0_B3 base address */
#define CM4_1__MU0_B3_BASE                          (0x41430180u)
/** Peripheral CM4_1__MU0_B3 base pointer */
#define CM4_1__MU0_B3                               ((MU_Type *)CM4_1__MU0_B3_BASE)
/** Peripheral CM4_1__MU0_A0 base address */
#define CM4_1__MU0_A0_BASE                         (0x41440000u)
/** Peripheral CM4_1__MU0_A0 base pointer */
#define CM4_1__MU0_A0                              ((MU_Type *)CM4_1__MU0_A0_BASE)
/** Peripheral CM4_1__MU0_A1 base address */
#define CM4_1__MU0_A1_BASE                         (0x41450000u)
/** Peripheral CM4_1__MU0_A1 base pointer */
#define CM4_1__MU0_A1                              ((MU_Type *)CM4_1__MU0_A1_BASE)
/** Peripheral CM4_1__MU0_A2 base address */
#define CM4_1__MU0_A2_BASE                         (0x41460000u)
/** Peripheral CM4_1__MU0_A2 base pointer */
#define CM4_1__MU0_A2                              ((MU_Type *)CM4_1__MU0_A2_BASE)
/** Peripheral CM4_1__MU0_A3 base address */
#define CM4_1__MU0_A3_BASE                         (0x41470000u)
/** Peripheral CM4_1__MU0_A3 base pointer */
#define CM4_1__MU0_A3                              ((MU_Type *)CM4_1__MU0_A3_BASE)
/** Peripheral CM4_1__MU1_A base address */
#define CM4_1__MU1_A_BASE                          (0x41480000u)
/** Peripheral CM4_1__MU1_A base pointer */
#define CM4_1__MU1_A                               ((MU_Type *)CM4_1__MU1_A_BASE)
/** Peripheral LSIO__MU0_A base address */
#define LSIO__MU0_A_BASE                          (0x5D1B0000u)
/** Peripheral LSIO__MU0_A base pointer */
#define LSIO__MU0_A                               ((MU_Type *)LSIO__MU0_A_BASE)
/** Peripheral LSIO__MU1_A base address */
#define LSIO__MU1_A_BASE                          (0x5D1C0000u)
/** Peripheral LSIO__MU1_A base pointer */
#define LSIO__MU1_A                               ((MU_Type *)LSIO__MU1_A_BASE)
/** Peripheral LSIO__MU2_A base address */
#define LSIO__MU2_A_BASE                          (0x5D1D0000u)
/** Peripheral LSIO__MU2_A base pointer */
#define LSIO__MU2_A                               ((MU_Type *)LSIO__MU2_A_BASE)
/** Peripheral LSIO__MU3_A base address */
#define LSIO__MU3_A_BASE                          (0x5D1E0000u)
/** Peripheral LSIO__MU3_A base pointer */
#define LSIO__MU3_A                               ((MU_Type *)LSIO__MU3_A_BASE)
/** Peripheral LSIO__MU4_A base address */
#define LSIO__MU4_A_BASE                          (0x5D1F0000u)
/** Peripheral LSIO__MU4_A base pointer */
#define LSIO__MU4_A                               ((MU_Type *)LSIO__MU4_A_BASE)
/** Peripheral LSIO__MU5_A base address */
#define LSIO__MU5_A_BASE                          (0x5D200000u)
/** Peripheral LSIO__MU5_A base pointer */
#define LSIO__MU5_A                               ((MU_Type *)LSIO__MU5_A_BASE)
/** Peripheral LSIO__MU6_A base address */
#define LSIO__MU6_A_BASE                          (0x5D210000u)
/** Peripheral LSIO__MU6_A base pointer */
#define LSIO__MU6_A                               ((MU_Type *)LSIO__MU6_A_BASE)
/** Peripheral LSIO__MU7_A base address */
#define LSIO__MU7_A_BASE                          (0x5D220000u)
/** Peripheral LSIO__MU7_A base pointer */
#define LSIO__MU7_A                               ((MU_Type *)LSIO__MU7_A_BASE)
/** Peripheral LSIO__MU8_A base address */
#define LSIO__MU8_A_BASE                          (0x5D230000u)
/** Peripheral LSIO__MU8_A base pointer */
#define LSIO__MU8_A                               ((MU_Type *)LSIO__MU8_A_BASE)
/** Peripheral LSIO__MU9_A base address */
#define LSIO__MU9_A_BASE                          (0x5D240000u)
/** Peripheral LSIO__MU9_A base pointer */
#define LSIO__MU9_A                               ((MU_Type *)LSIO__MU9_A_BASE)
/** Peripheral LSIO__MU10_A base address */
#define LSIO__MU10_A_BASE                          (0x5D250000u)
/** Peripheral LSIO__MU10_A base pointer */
#define LSIO__MU10_A                               ((MU_Type *)LSIO__MU10_A_BASE)
/** Peripheral LSIO__MU11_A base address */
#define LSIO__MU11_A_BASE                          (0x5D260000u)
/** Peripheral LSIO__MU11_A base pointer */
#define LSIO__MU11_A                               ((MU_Type *)LSIO__MU11_A_BASE)
/** Peripheral LSIO__MU12_A base address */
#define LSIO__MU12_A_BASE                          (0x5D270000u)
/** Peripheral LSIO__MU12_A base pointer */
#define LSIO__MU12_A                               ((MU_Type *)LSIO__MU12_A_BASE)
/** Peripheral LSIO__MU13_A base address */
#define LSIO__MU13_A_BASE                          (0x5D280000u)
/** Peripheral LSIO__MU13_A base pointer */
#define LSIO__MU13_A                               ((MU_Type *)LSIO__MU13_A_BASE)
/** Peripheral LSIO__MU5_B base address */
#define LSIO__MU5_B_BASE                          (0x5D290000u)
/** Peripheral LSIO__MU5_B base pointer */
#define LSIO__MU5_B                               ((MU_Type *)LSIO__MU5_B_BASE)
/** Peripheral LSIO__MU6_B base address */
#define LSIO__MU6_B_BASE                          (0x5D2A0000u)
/** Peripheral LSIO__MU6_B base pointer */
#define LSIO__MU6_B                               ((MU_Type *)LSIO__MU6_B_BASE)
/** Peripheral LSIO__MU7_B base address */
#define LSIO__MU7_B_BASE                          (0x5D2B0000u)
/** Peripheral LSIO__MU7_B base pointer */
#define LSIO__MU7_B                               ((MU_Type *)LSIO__MU7_B_BASE)
/** Peripheral LSIO__MU8_B base address */
#define LSIO__MU8_B_BASE                          (0x5D2C0000u)
/** Peripheral LSIO__MU8_B base pointer */
#define LSIO__MU8_B                               ((MU_Type *)LSIO__MU8_B_BASE)
/** Peripheral LSIO__MU9_B base address */
#define LSIO__MU9_B_BASE                          (0x5D2D0000u)
/** Peripheral LSIO__MU9_B base pointer */
#define LSIO__MU9_B                               ((MU_Type *)LSIO__MU9_B_BASE)
/** Peripheral LSIO__MU10_B base address */
#define LSIO__MU10_B_BASE                          (0x5D2E0000u)
/** Peripheral LSIO__MU10_B base pointer */
#define LSIO__MU10_B                               ((MU_Type *)LSIO__MU10_B_BASE)
/** Peripheral LSIO__MU11_B base address */
#define LSIO__MU11_B_BASE                          (0x5D2F0000u)
/** Peripheral LSIO__MU11_B base pointer */
#define LSIO__MU11_B                               ((MU_Type *)LSIO__MU11_B_BASE)
/** Peripheral LSIO__MU12_B base address */
#define LSIO__MU12_B_BASE                          (0x5D300000u)
/** Peripheral LSIO__MU12_B base pointer */
#define LSIO__MU12_B                               ((MU_Type *)LSIO__MU12_B_BASE)
/** Peripheral LSIO__MU13_B base address */
#define LSIO__MU13_B_BASE                          (0x5D310000u)
/** Peripheral LSIO__MU13_B base pointer */
#define LSIO__MU13_B                               ((MU_Type *)LSIO__MU13_B_BASE)

/** Array initializer of MU peripheral base addresses */
#define MU_BASE_ADDRS                            { CM4_0__MU0_B0_BASE, CM4_0__MU0_B1_BASE, CM4_0__MU0_B2_BASE, CM4_0__MU0_B3_BASE, CM4_0__MU0_A0_BASE, CM4_0__MU0_A1_BASE, CM4_0__MU0_A2_BASE, CM4_0__MU0_A3_BASE, CM4_0__MU1_A_BASE, CM4_1__MU0_B0_BASE, CM4_1__MU0_B1_BASE, CM4_1__MU0_B2_BASE, CM4_1__MU0_B3_BASE, CM4_1__MU0_A0_BASE, CM4_1__MU0_A1_BASE, CM4_1__MU0_A2_BASE, CM4_1__MU0_A3_BASE, CM4_1__MU1_A_BASE, LSIO__MU0_A_BASE, LSIO__MU1_A_BASE, LSIO__MU2_A_BASE, LSIO__MU3_A_BASE, LSIO__MU4_A_BASE, LSIO__MU5_A_BASE, LSIO__MU6_A_BASE, LSIO__MU7_A_BASE, LSIO__MU8_A_BASE, LSIO__MU9_A_BASE, LSIO__MU10_A_BASE, LSIO__MU11_A_BASE, LSIO__MU12_A_BASE, LSIO__MU13_A_BASE, LSIO__MU5_B_BASE, LSIO__MU6_B_BASE, LSIO__MU7_B_BASE, LSIO__MU8_B_BASE, LSIO__MU9_B_BASE, LSIO__MU10_B_BASE, LSIO__MU11_B_BASE, LSIO__MU12_B_BASE, LSIO__MU13_B_BASE}
/** Array initializer of MU peripheral base pointers */
#define MU_BASE_PTRS                             { CM4_0__MU0_B0, CM4_0__MU0_B1, CM4_0__MU0_B2, CM4_0__MU0_B3, CM4_0__MU0_A0, CM4_0__MU0_A1, CM4_0__MU0_A2, CM4_0__MU0_A3, CM4_0__MU1_A, CM4_1__MU0_B0, CM4_1__MU0_B1, CM4_1__MU0_B2, CM4_1__MU0_B3, CM4_1__MU0_A0, CM4_1__MU0_A1, CM4_1__MU0_A2, CM4_1__MU0_A3, CM4_1__MU1_A, LSIO__MU0_A, LSIO__MU1_A, LSIO__MU2_A, LSIO__MU3_A, LSIO__MU4_A, LSIO__MU5_A, LSIO__MU6_A, LSIO__MU7_A, LSIO__MU8_A, LSIO__MU9_A, LSIO__MU10_A, LSIO__MU11_A, LSIO__MU12_A, LSIO__MU13_A, LSIO__MU5_B, LSIO__MU6_B, LSIO__MU7_B, LSIO__MU8_B, LSIO__MU9_B, LSIO__MU10_B, LSIO__MU11_B, LSIO__MU12_B, LSIO__MU13_B}


/* ----------------------------------------------------------------------------
   -- PRG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PRG_Peripheral_Access_Layer PRG Peripheral Access Layer
 * @{
 */

/** PRG - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0 */
    __IO uint32_t RW;                                /**< PRG Control Register, offset: 0x0 */
    __IO uint32_t SET;                               /**< PRG Control Register, offset: 0x4 */
    __IO uint32_t CLR;                               /**< PRG Control Register, offset: 0x8 */
    __IO uint32_t TOG;                               /**< PRG Control Register, offset: 0xC */
  } PRG_CTRL;
  struct {                                         /* offset: 0x10 */
    __I  uint32_t RW;                                /**< PRG Status Register, offset: 0x10 */
    __I  uint32_t SET;                               /**< PRG Status Register, offset: 0x14 */
    __I  uint32_t CLR;                               /**< PRG Status Register, offset: 0x18 */
    __I  uint32_t TOG;                               /**< PRG Status Register, offset: 0x1C */
  } PRG_STATUS;
  struct {                                         /* offset: 0x20 */
    __IO uint32_t RW;                                /**< PRG REG update Register, offset: 0x20 */
    __IO uint32_t SET;                               /**< PRG REG update Register, offset: 0x24 */
    __IO uint32_t CLR;                               /**< PRG REG update Register, offset: 0x28 */
    __IO uint32_t TOG;                               /**< PRG REG update Register, offset: 0x2C */
  } PRG_REG_UPDATE;
  struct {                                         /* offset: 0x30 */
    __IO uint32_t RW;                                /**< PRG Stride Register, offset: 0x30 */
    __IO uint32_t SET;                               /**< PRG Stride Register, offset: 0x34 */
    __IO uint32_t CLR;                               /**< PRG Stride Register, offset: 0x38 */
    __IO uint32_t TOG;                               /**< PRG Stride Register, offset: 0x3C */
  } PRG_STRIDE;
  struct {                                         /* offset: 0x40 */
    __IO uint32_t RW;                                /**< PRG Height Register, offset: 0x40 */
    __IO uint32_t SET;                               /**< PRG Height Register, offset: 0x44 */
    __IO uint32_t CLR;                               /**< PRG Height Register, offset: 0x48 */
    __IO uint32_t TOG;                               /**< PRG Height Register, offset: 0x4C */
  } PRG_HEIGHT;
  struct {                                         /* offset: 0x50 */
    __IO uint32_t RW;                                /**< PRG Base Address Register, offset: 0x50 */
    __IO uint32_t SET;                               /**< PRG Base Address Register, offset: 0x54 */
    __IO uint32_t CLR;                               /**< PRG Base Address Register, offset: 0x58 */
    __IO uint32_t TOG;                               /**< PRG Base Address Register, offset: 0x5C */
  } PRG_BADDR;
  struct {                                         /* offset: 0x60 */
    __IO uint32_t RW;                                /**< PRG Offset Address Register, offset: 0x60 */
    __IO uint32_t SET;                               /**< PRG Offset Address Register, offset: 0x64 */
    __IO uint32_t CLR;                               /**< PRG Offset Address Register, offset: 0x68 */
    __IO uint32_t TOG;                               /**< PRG Offset Address Register, offset: 0x6C */
  } PRG_OFFSET;
  struct {                                         /* offset: 0x70 */
    __IO uint32_t RW;                                /**< PRG Width Register, offset: 0x70 */
    __IO uint32_t SET;                               /**< PRG Width Register, offset: 0x74 */
    __IO uint32_t CLR;                               /**< PRG Width Register, offset: 0x78 */
    __IO uint32_t TOG;                               /**< PRG Width Register, offset: 0x7C */
  } PRG_WIDTH;
} PRG_Type;

/* ----------------------------------------------------------------------------
   -- PRG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PRG_Register_Masks PRG Register Masks
 * @{
 */

/*! @name PRG_CTRL - PRG Control Register */
/*! @{ */
#define PRG_PRG_CTRL_BYPASS_MASK                 (0x1U)
#define PRG_PRG_CTRL_BYPASS_SHIFT                (0U)
#define PRG_PRG_CTRL_BYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_BYPASS_SHIFT)) & PRG_PRG_CTRL_BYPASS_MASK)
#define PRG_PRG_CTRL_RESERVED_MASK               (0x2U)
#define PRG_PRG_CTRL_RESERVED_SHIFT              (1U)
#define PRG_PRG_CTRL_RESERVED(x)                 (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_RESERVED_SHIFT)) & PRG_PRG_CTRL_RESERVED_MASK)
#define PRG_PRG_CTRL_SC_DATA_TYPE_MASK           (0x4U)
#define PRG_PRG_CTRL_SC_DATA_TYPE_SHIFT          (2U)
#define PRG_PRG_CTRL_SC_DATA_TYPE(x)             (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_SC_DATA_TYPE_SHIFT)) & PRG_PRG_CTRL_SC_DATA_TYPE_MASK)
#define PRG_PRG_CTRL_UV_EN_MASK                  (0x8U)
#define PRG_PRG_CTRL_UV_EN_SHIFT                 (3U)
#define PRG_PRG_CTRL_UV_EN(x)                    (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_UV_EN_SHIFT)) & PRG_PRG_CTRL_UV_EN_MASK)
#define PRG_PRG_CTRL_HANDSHAKE_MODE_MASK         (0x10U)
#define PRG_PRG_CTRL_HANDSHAKE_MODE_SHIFT        (4U)
#define PRG_PRG_CTRL_HANDSHAKE_MODE(x)           (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_HANDSHAKE_MODE_SHIFT)) & PRG_PRG_CTRL_HANDSHAKE_MODE_MASK)
#define PRG_PRG_CTRL_SHADOW_LOAD_MODE_MASK       (0x20U)
#define PRG_PRG_CTRL_SHADOW_LOAD_MODE_SHIFT      (5U)
#define PRG_PRG_CTRL_SHADOW_LOAD_MODE(x)         (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_SHADOW_LOAD_MODE_SHIFT)) & PRG_PRG_CTRL_SHADOW_LOAD_MODE_MASK)
#define PRG_PRG_CTRL_DES_DATA_TYPE_MASK          (0x30000U)
#define PRG_PRG_CTRL_DES_DATA_TYPE_SHIFT         (16U)
#define PRG_PRG_CTRL_DES_DATA_TYPE(x)            (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_DES_DATA_TYPE_SHIFT)) & PRG_PRG_CTRL_DES_DATA_TYPE_MASK)
#define PRG_PRG_CTRL_SOFTRST_MASK                (0x40000000U)
#define PRG_PRG_CTRL_SOFTRST_SHIFT               (30U)
#define PRG_PRG_CTRL_SOFTRST(x)                  (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_SOFTRST_SHIFT)) & PRG_PRG_CTRL_SOFTRST_MASK)
#define PRG_PRG_CTRL_SHADOW_EN_MASK              (0x80000000U)
#define PRG_PRG_CTRL_SHADOW_EN_SHIFT             (31U)
#define PRG_PRG_CTRL_SHADOW_EN(x)                (((uint32_t)(((uint32_t)(x)) << PRG_PRG_CTRL_SHADOW_EN_SHIFT)) & PRG_PRG_CTRL_SHADOW_EN_MASK)
/*! @} */

/*! @name PRG_STATUS - PRG Status Register */
/*! @{ */
#define PRG_PRG_STATUS_BUFFER_VALID_A_MASK       (0x1U)
#define PRG_PRG_STATUS_BUFFER_VALID_A_SHIFT      (0U)
#define PRG_PRG_STATUS_BUFFER_VALID_A(x)         (((uint32_t)(((uint32_t)(x)) << PRG_PRG_STATUS_BUFFER_VALID_A_SHIFT)) & PRG_PRG_STATUS_BUFFER_VALID_A_MASK)
#define PRG_PRG_STATUS_BUFFER_VALID_B_MASK       (0x2U)
#define PRG_PRG_STATUS_BUFFER_VALID_B_SHIFT      (1U)
#define PRG_PRG_STATUS_BUFFER_VALID_B(x)         (((uint32_t)(((uint32_t)(x)) << PRG_PRG_STATUS_BUFFER_VALID_B_SHIFT)) & PRG_PRG_STATUS_BUFFER_VALID_B_MASK)
/*! @} */

/*! @name PRG_REG_UPDATE - PRG REG update Register */
/*! @{ */
#define PRG_PRG_REG_UPDATE_REG_UPDATE_MASK       (0x1U)
#define PRG_PRG_REG_UPDATE_REG_UPDATE_SHIFT      (0U)
#define PRG_PRG_REG_UPDATE_REG_UPDATE(x)         (((uint32_t)(((uint32_t)(x)) << PRG_PRG_REG_UPDATE_REG_UPDATE_SHIFT)) & PRG_PRG_REG_UPDATE_REG_UPDATE_MASK)
/*! @} */

/*! @name PRG_STRIDE - PRG Stride Register */
/*! @{ */
#define PRG_PRG_STRIDE_STRIDE_MASK               (0xFFFFU)
#define PRG_PRG_STRIDE_STRIDE_SHIFT              (0U)
#define PRG_PRG_STRIDE_STRIDE(x)                 (((uint32_t)(((uint32_t)(x)) << PRG_PRG_STRIDE_STRIDE_SHIFT)) & PRG_PRG_STRIDE_STRIDE_MASK)
/*! @} */

/*! @name PRG_HEIGHT - PRG Height Register */
/*! @{ */
#define PRG_PRG_HEIGHT_HEIGHT_MASK               (0xFFFFU)
#define PRG_PRG_HEIGHT_HEIGHT_SHIFT              (0U)
#define PRG_PRG_HEIGHT_HEIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << PRG_PRG_HEIGHT_HEIGHT_SHIFT)) & PRG_PRG_HEIGHT_HEIGHT_MASK)
/*! @} */

/*! @name PRG_BADDR - PRG Base Address Register */
/*! @{ */
#define PRG_PRG_BADDR_BADDR_MASK                 (0xFFFFFFFFU)
#define PRG_PRG_BADDR_BADDR_SHIFT                (0U)
#define PRG_PRG_BADDR_BADDR(x)                   (((uint32_t)(((uint32_t)(x)) << PRG_PRG_BADDR_BADDR_SHIFT)) & PRG_PRG_BADDR_BADDR_MASK)
/*! @} */

/*! @name PRG_OFFSET - PRG Offset Address Register */
/*! @{ */
#define PRG_PRG_OFFSET_X_MASK                    (0xFFFFU)
#define PRG_PRG_OFFSET_X_SHIFT                   (0U)
#define PRG_PRG_OFFSET_X(x)                      (((uint32_t)(((uint32_t)(x)) << PRG_PRG_OFFSET_X_SHIFT)) & PRG_PRG_OFFSET_X_MASK)
#define PRG_PRG_OFFSET_Y_MASK                    (0x70000U)
#define PRG_PRG_OFFSET_Y_SHIFT                   (16U)
#define PRG_PRG_OFFSET_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PRG_PRG_OFFSET_Y_SHIFT)) & PRG_PRG_OFFSET_Y_MASK)
/*! @} */

/*! @name PRG_WIDTH - PRG Width Register */
/*! @{ */
#define PRG_PRG_WIDTH_WIDTH_MASK                 (0xFFFFU)
#define PRG_PRG_WIDTH_WIDTH_SHIFT                (0U)
#define PRG_PRG_WIDTH_WIDTH(x)                   (((uint32_t)(((uint32_t)(x)) << PRG_PRG_WIDTH_WIDTH_SHIFT)) & PRG_PRG_WIDTH_WIDTH_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PRG_Register_Masks */


/* PRG - Peripheral instance base addresses */
/** Peripheral DC_0__PRG0 base address */
#define DC_0__PRG0_BASE                            (0x56040000u)
/** Peripheral DC_0__PRG0 base pointer */
#define DC_0__PRG0                                 ((PRG_Type *)DC_0__PRG0_BASE)
/** Peripheral DC_0__PRG1 base address */
#define DC_0__PRG1_BASE                            (0x56050000u)
/** Peripheral DC_0__PRG1 base pointer */
#define DC_0__PRG1                                 ((PRG_Type *)DC_0__PRG1_BASE)
/** Peripheral DC_0__PRG2 base address */
#define DC_0__PRG2_BASE                            (0x56060000u)
/** Peripheral DC_0__PRG2 base pointer */
#define DC_0__PRG2                                 ((PRG_Type *)DC_0__PRG2_BASE)
/** Peripheral DC_0__PRG3 base address */
#define DC_0__PRG3_BASE                            (0x56070000u)
/** Peripheral DC_0__PRG3 base pointer */
#define DC_0__PRG3                                 ((PRG_Type *)DC_0__PRG3_BASE)
/** Peripheral DC_0__PRG4 base address */
#define DC_0__PRG4_BASE                            (0x56080000u)
/** Peripheral DC_0__PRG4 base pointer */
#define DC_0__PRG4                                 ((PRG_Type *)DC_0__PRG4_BASE)
/** Peripheral DC_0__PRG5 base address */
#define DC_0__PRG5_BASE                            (0x56090000u)
/** Peripheral DC_0__PRG5 base pointer */
#define DC_0__PRG5                                 ((PRG_Type *)DC_0__PRG5_BASE)
/** Peripheral DC_0__PRG6 base address */
#define DC_0__PRG6_BASE                            (0x560A0000u)
/** Peripheral DC_0__PRG6 base pointer */
#define DC_0__PRG6                                 ((PRG_Type *)DC_0__PRG6_BASE)
/** Peripheral DC_0__PRG7 base address */
#define DC_0__PRG7_BASE                            (0x560B0000u)
/** Peripheral DC_0__PRG7 base pointer */
#define DC_0__PRG7                                 ((PRG_Type *)DC_0__PRG7_BASE)
/** Peripheral DC_0__PRG8 base address */
#define DC_0__PRG8_BASE                            (0x560C0000u)
/** Peripheral DC_0__PRG8 base pointer */
#define DC_0__PRG8                                 ((PRG_Type *)DC_0__PRG8_BASE)
/** Peripheral DC_1__PRG0 base address */
#define DC_1__PRG0_BASE                            (0x57040000u)
/** Peripheral DC_1__PRG0 base pointer */
#define DC_1__PRG0                                 ((PRG_Type *)DC_1__PRG0_BASE)
/** Peripheral DC_1__PRG1 base address */
#define DC_1__PRG1_BASE                            (0x57050000u)
/** Peripheral DC_1__PRG1 base pointer */
#define DC_1__PRG1                                 ((PRG_Type *)DC_1__PRG1_BASE)
/** Peripheral DC_1__PRG2 base address */
#define DC_1__PRG2_BASE                            (0x57060000u)
/** Peripheral DC_1__PRG2 base pointer */
#define DC_1__PRG2                                 ((PRG_Type *)DC_1__PRG2_BASE)
/** Peripheral DC_1__PRG3 base address */
#define DC_1__PRG3_BASE                            (0x57070000u)
/** Peripheral DC_1__PRG3 base pointer */
#define DC_1__PRG3                                 ((PRG_Type *)DC_1__PRG3_BASE)
/** Peripheral DC_1__PRG4 base address */
#define DC_1__PRG4_BASE                            (0x57080000u)
/** Peripheral DC_1__PRG4 base pointer */
#define DC_1__PRG4                                 ((PRG_Type *)DC_1__PRG4_BASE)
/** Peripheral DC_1__PRG5 base address */
#define DC_1__PRG5_BASE                            (0x57090000u)
/** Peripheral DC_1__PRG5 base pointer */
#define DC_1__PRG5                                 ((PRG_Type *)DC_1__PRG5_BASE)
/** Peripheral DC_1__PRG6 base address */
#define DC_1__PRG6_BASE                            (0x570A0000u)
/** Peripheral DC_1__PRG6 base pointer */
#define DC_1__PRG6                                 ((PRG_Type *)DC_1__PRG6_BASE)
/** Peripheral DC_1__PRG7 base address */
#define DC_1__PRG7_BASE                            (0x570B0000u)
/** Peripheral DC_1__PRG7 base pointer */
#define DC_1__PRG7                                 ((PRG_Type *)DC_1__PRG7_BASE)
/** Peripheral DC_1__PRG8 base address */
#define DC_1__PRG8_BASE                            (0x570C0000u)
/** Peripheral DC_1__PRG8 base pointer */
#define DC_1__PRG8                                 ((PRG_Type *)DC_1__PRG8_BASE)

/** Array initializer of PRG peripheral base addresses */
#define PRG_BASE_ADDRS                           { DC_0__PRG0_BASE, DC_0__PRG1_BASE, DC_0__PRG2_BASE, DC_0__PRG3_BASE, DC_0__PRG4_BASE, DC_0__PRG5_BASE, DC_0__PRG6_BASE, DC_0__PRG7_BASE, DC_0__PRG8_BASE, \
                                                   DC_1__PRG0_BASE, DC_1__PRG1_BASE, DC_1__PRG2_BASE, DC_1__PRG3_BASE, DC_1__PRG4_BASE, DC_1__PRG5_BASE, DC_1__PRG6_BASE, DC_1__PRG7_BASE, DC_1__PRG8_BASE }
/** Array initializer of PRG peripheral base pointers */
#define PRG_BASE_PTRS                            { DC_0__PRG0, DC_0__PRG1, DC_0__PRG2, DC_0__PRG3, DC_0__PRG4, DC_0__PRG5, DC_0__PRG6, DC_0__PRG7, DC_0__PRG8, \
                                                   DC_1__PRG0, DC_1__PRG1, DC_1__PRG2, DC_1__PRG3, DC_1__PRG4, DC_1__PRG5, DC_1__PRG6, DC_1__PRG7, DC_1__PRG8 }

/*!
 * @}
 */ /* end of group PRG_Peripheral_Access_Layer */
 

/* ----------------------------------------------------------------------------
   -- PWM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
 * @{
 */

/** PWM - Register Layout Typedef */
typedef struct {
  __IO uint32_t PWMCR;                             /**< PWM Control Register, offset: 0x0 */
  __IO uint32_t PWMSR;                             /**< PWM Status Register, offset: 0x4 */
  __IO uint32_t PWMIR;                             /**< PWM Interrupt Register, offset: 0x8 */
  __IO uint32_t PWMSAR;                            /**< PWM Sample Register, offset: 0xC */
  __IO uint32_t PWMPR;                             /**< PWM Period Register, offset: 0x10 */
  __I  uint32_t PWMCNR;                            /**< PWM Counter Register, offset: 0x14 */
} PWM_Type;

/* ----------------------------------------------------------------------------
   -- PWM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PWM_Register_Masks PWM Register Masks
 * @{
 */

/*! @name PWMCR - PWM Control Register */
/*! @{ */
#define PWM_PWMCR_EN_MASK                        (0x1U)
#define PWM_PWMCR_EN_SHIFT                       (0U)
/*! EN - EN
 *  0b0..PWM disabled
 *  0b1..PWM enabled
 */
#define PWM_PWMCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_EN_SHIFT)) & PWM_PWMCR_EN_MASK)
#define PWM_PWMCR_REPEAT_MASK                    (0x6U)
#define PWM_PWMCR_REPEAT_SHIFT                   (1U)
/*! REPEAT - REPEAT
 *  0b00..Use each sample once
 *  0b01..Use each sample twice
 *  0b10..Use each sample four times
 *  0b11..Use each sample eight times
 */
#define PWM_PWMCR_REPEAT(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_REPEAT_SHIFT)) & PWM_PWMCR_REPEAT_MASK)
#define PWM_PWMCR_SWR_MASK                       (0x8U)
#define PWM_PWMCR_SWR_SHIFT                      (3U)
/*! SWR - SWR
 *  0b0..PWM is out of reset
 *  0b1..PWM is undergoing reset
 */
#define PWM_PWMCR_SWR(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_SWR_SHIFT)) & PWM_PWMCR_SWR_MASK)
#define PWM_PWMCR_PRESCALER_MASK                 (0xFFF0U)
#define PWM_PWMCR_PRESCALER_SHIFT                (4U)
/*! PRESCALER - PRESCALER
 *  0b000000000000..Divide by 1
 *  0b000000000001..Divide by 2
 *  0b111111111111..Divide by 4096
 */
#define PWM_PWMCR_PRESCALER(x)                   (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_PRESCALER_SHIFT)) & PWM_PWMCR_PRESCALER_MASK)
#define PWM_PWMCR_CLKSRC_MASK                    (0x30000U)
#define PWM_PWMCR_CLKSRC_SHIFT                   (16U)
/*! CLKSRC - CLKSRC
 *  0b00..Clock is off
 *  0b01..ipg_clk
 */
#define PWM_PWMCR_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_CLKSRC_SHIFT)) & PWM_PWMCR_CLKSRC_MASK)
#define PWM_PWMCR_POUTC_MASK                     (0xC0000U)
#define PWM_PWMCR_POUTC_SHIFT                    (18U)
/*! POUTC - POUTC
 *  0b00..Output pin is set at rollover and cleared at comparison
 *  0b01..Output pin is cleared at rollover and set at comparison
 *  0b10..PWM output is disconnected
 *  0b11..PWM output is disconnected
 */
#define PWM_PWMCR_POUTC(x)                       (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_POUTC_SHIFT)) & PWM_PWMCR_POUTC_MASK)
#define PWM_PWMCR_HCTR_MASK                      (0x100000U)
#define PWM_PWMCR_HCTR_SHIFT                     (20U)
/*! HCTR - HCTR
 *  0b0..Half word swapping does not take place
 *  0b1..Half words from write data bus are swapped
 */
#define PWM_PWMCR_HCTR(x)                        (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_HCTR_SHIFT)) & PWM_PWMCR_HCTR_MASK)
#define PWM_PWMCR_BCTR_MASK                      (0x200000U)
#define PWM_PWMCR_BCTR_SHIFT                     (21U)
/*! BCTR - BCTR
 *  0b0..byte ordering remains the same
 *  0b1..byte ordering is reversed
 */
#define PWM_PWMCR_BCTR(x)                        (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_BCTR_SHIFT)) & PWM_PWMCR_BCTR_MASK)
#define PWM_PWMCR_WAITEN_MASK                    (0x800000U)
#define PWM_PWMCR_WAITEN_SHIFT                   (23U)
/*! WAITEN - WAITEN
 *  0b0..Inactive in wait mode
 *  0b1..Active in wait mode
 */
#define PWM_PWMCR_WAITEN(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_WAITEN_SHIFT)) & PWM_PWMCR_WAITEN_MASK)
#define PWM_PWMCR_DOZEN_MASK                     (0x1000000U)
#define PWM_PWMCR_DOZEN_SHIFT                    (24U)
/*! DOZEN - DOZEN
 *  0b0..Inactive in doze mode
 *  0b1..Active in doze mode
 */
#define PWM_PWMCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DOZEN_SHIFT)) & PWM_PWMCR_DOZEN_MASK)
#define PWM_PWMCR_STOPEN_MASK                    (0x2000000U)
#define PWM_PWMCR_STOPEN_SHIFT                   (25U)
/*! STOPEN - STOPEN
 *  0b0..Inactive in stop mode
 *  0b1..Active in stop mode
 */
#define PWM_PWMCR_STOPEN(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_STOPEN_SHIFT)) & PWM_PWMCR_STOPEN_MASK)
#define PWM_PWMCR_FWM_MASK                       (0xC000000U)
#define PWM_PWMCR_FWM_SHIFT                      (26U)
/*! FWM - FWM
 *  0b00..FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO
 *  0b01..FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO
 *  0b10..FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO
 *  0b11..FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO
 */
#define PWM_PWMCR_FWM(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_FWM_SHIFT)) & PWM_PWMCR_FWM_MASK)
/*! @} */

/*! @name PWMSR - PWM Status Register */
/*! @{ */
#define PWM_PWMSR_FIFOAV_MASK                    (0x7U)
#define PWM_PWMSR_FIFOAV_SHIFT                   (0U)
/*! FIFOAV - FIFOAV
 *  0b000..No data available
 *  0b001..1 word of data in FIFO
 *  0b010..2 words of data in FIFO
 *  0b011..3 words of data in FIFO
 *  0b100..4 words of data in FIFO
 *  0b101..unused
 *  0b110..unused
 *  0b111..unused
 */
#define PWM_PWMSR_FIFOAV(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FIFOAV_SHIFT)) & PWM_PWMSR_FIFOAV_MASK)
#define PWM_PWMSR_FE_MASK                        (0x8U)
#define PWM_PWMSR_FE_SHIFT                       (3U)
/*! FE - FE
 *  0b0..Data level is above water mark
 *  0b1..When the data level falls below the mark set by FWM field
 */
#define PWM_PWMSR_FE(x)                          (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FE_SHIFT)) & PWM_PWMSR_FE_MASK)
#define PWM_PWMSR_ROV_MASK                       (0x10U)
#define PWM_PWMSR_ROV_SHIFT                      (4U)
/*! ROV - ROV
 *  0b0..Roll-over event not occurred
 *  0b1..Roll-over event occurred
 */
#define PWM_PWMSR_ROV(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_ROV_SHIFT)) & PWM_PWMSR_ROV_MASK)
#define PWM_PWMSR_CMP_MASK                       (0x20U)
#define PWM_PWMSR_CMP_SHIFT                      (5U)
/*! CMP - CMP
 *  0b0..Compare event not occurred
 *  0b1..Compare event occurred
 */
#define PWM_PWMSR_CMP(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_CMP_SHIFT)) & PWM_PWMSR_CMP_MASK)
#define PWM_PWMSR_FWE_MASK                       (0x40U)
#define PWM_PWMSR_FWE_SHIFT                      (6U)
/*! FWE - FWE
 *  0b0..FIFO write error not occurred
 *  0b1..FIFO write error occurred
 */
#define PWM_PWMSR_FWE(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FWE_SHIFT)) & PWM_PWMSR_FWE_MASK)
/*! @} */

/*! @name PWMIR - PWM Interrupt Register */
/*! @{ */
#define PWM_PWMIR_FIE_MASK                       (0x1U)
#define PWM_PWMIR_FIE_SHIFT                      (0U)
/*! FIE - FIE
 *  0b0..FIFO Empty interrupt disabled
 *  0b1..FIFO Empty interrupt enabled
 */
#define PWM_PWMIR_FIE(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_FIE_SHIFT)) & PWM_PWMIR_FIE_MASK)
#define PWM_PWMIR_RIE_MASK                       (0x2U)
#define PWM_PWMIR_RIE_SHIFT                      (1U)
/*! RIE - RIE
 *  0b0..Roll-over interrupt not enabled
 *  0b1..Roll-over Interrupt enabled
 */
#define PWM_PWMIR_RIE(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_RIE_SHIFT)) & PWM_PWMIR_RIE_MASK)
#define PWM_PWMIR_CIE_MASK                       (0x4U)
#define PWM_PWMIR_CIE_SHIFT                      (2U)
/*! CIE - CIE
 *  0b0..Compare Interrupt not enabled
 *  0b1..Compare Interrupt enabled
 */
#define PWM_PWMIR_CIE(x)                         (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_CIE_SHIFT)) & PWM_PWMIR_CIE_MASK)
/*! @} */

/*! @name PWMSAR - PWM Sample Register */
/*! @{ */
#define PWM_PWMSAR_SAMPLE_MASK                   (0xFFFFU)
#define PWM_PWMSAR_SAMPLE_SHIFT                  (0U)
#define PWM_PWMSAR_SAMPLE(x)                     (((uint32_t)(((uint32_t)(x)) << PWM_PWMSAR_SAMPLE_SHIFT)) & PWM_PWMSAR_SAMPLE_MASK)
/*! @} */

/*! @name PWMPR - PWM Period Register */
/*! @{ */
#define PWM_PWMPR_PERIOD_MASK                    (0xFFFFU)
#define PWM_PWMPR_PERIOD_SHIFT                   (0U)
#define PWM_PWMPR_PERIOD(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMPR_PERIOD_SHIFT)) & PWM_PWMPR_PERIOD_MASK)
/*! @} */

/*! @name PWMCNR - PWM Counter Register */
/*! @{ */
#define PWM_PWMCNR_COUNT_MASK                    (0xFFFFU)
#define PWM_PWMCNR_COUNT_SHIFT                   (0U)
#define PWM_PWMCNR_COUNT(x)                      (((uint32_t)(((uint32_t)(x)) << PWM_PWMCNR_COUNT_SHIFT)) & PWM_PWMCNR_COUNT_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PWM_Register_Masks */


/* PWM - Peripheral instance base addresses */
/** Peripheral DI_HDMI__PWM base address */
#define DI_HDMI__PWM_BASE                        (0x56264000u)
/** Peripheral DI_HDMI__PWM base pointer */
#define DI_HDMI__PWM                             ((PWM_Type *)DI_HDMI__PWM_BASE)
/** Peripheral DI_LVDS_0__PWM base address */
#define DI_LVDS_0__PWM_BASE                      (0x56244000u)
/** Peripheral DI_LVDS_0__PWM base pointer */
#define DI_LVDS_0__PWM                           ((PWM_Type *)DI_LVDS_0__PWM_BASE)
/** Peripheral DI_LVDS_1__PWM base address */
#define DI_LVDS_1__PWM_BASE                      (0x57244000u)
/** Peripheral DI_LVDS_1__PWM base pointer */
#define DI_LVDS_1__PWM                           ((PWM_Type *)DI_LVDS_1__PWM_BASE)
/** Peripheral DI_MIPI_0__PWM base address */
#define DI_MIPI_0__PWM_BASE                      (0x56224000u)
/** Peripheral DI_MIPI_0__PWM base pointer */
#define DI_MIPI_0__PWM                           ((PWM_Type *)DI_MIPI_0__PWM_BASE)
/** Peripheral DI_MIPI_1__PWM base address */
#define DI_MIPI_1__PWM_BASE                      (0x57224000u)
/** Peripheral DI_MIPI_1__PWM base pointer */
#define DI_MIPI_1__PWM                           ((PWM_Type *)DI_MIPI_1__PWM_BASE)
/** Peripheral LSIO__PWM0 base address */
#define LSIO__PWM0_BASE                          (0x5D000000u)
/** Peripheral LSIO__PWM0 base pointer */
#define LSIO__PWM0                               ((PWM_Type *)LSIO__PWM0_BASE)
/** Peripheral LSIO__PWM1 base address */
#define LSIO__PWM1_BASE                          (0x5D010000u)
/** Peripheral LSIO__PWM1 base pointer */
#define LSIO__PWM1                               ((PWM_Type *)LSIO__PWM1_BASE)
/** Peripheral LSIO__PWM2 base address */
#define LSIO__PWM2_BASE                          (0x5D020000u)
/** Peripheral LSIO__PWM2 base pointer */
#define LSIO__PWM2                               ((PWM_Type *)LSIO__PWM2_BASE)
/** Peripheral LSIO__PWM3 base address */
#define LSIO__PWM3_BASE                          (0x5D030000u)
/** Peripheral LSIO__PWM3 base pointer */
#define LSIO__PWM3                               ((PWM_Type *)LSIO__PWM3_BASE)
/** Peripheral LSIO__PWM4 base address */
#define LSIO__PWM4_BASE                          (0x5D040000u)
/** Peripheral LSIO__PWM4 base pointer */
#define LSIO__PWM4                               ((PWM_Type *)LSIO__PWM4_BASE)
/** Peripheral LSIO__PWM5 base address */
#define LSIO__PWM5_BASE                          (0x5D050000u)
/** Peripheral LSIO__PWM5 base pointer */
#define LSIO__PWM5                               ((PWM_Type *)LSIO__PWM5_BASE)
/** Peripheral LSIO__PWM6 base address */
#define LSIO__PWM6_BASE                          (0x5D060000u)
/** Peripheral LSIO__PWM6 base pointer */
#define LSIO__PWM6                               ((PWM_Type *)LSIO__PWM6_BASE)
/** Peripheral LSIO__PWM7 base address */
#define LSIO__PWM7_BASE                          (0x5D070000u)
/** Peripheral LSIO__PWM7 base pointer */
#define LSIO__PWM7                               ((PWM_Type *)LSIO__PWM7_BASE)
/** Peripheral MIPI_CSI_0__PWM base address */
#define MIPI_CSI_0__PWM_BASE                     (0x58224000u)
/** Peripheral MIPI_CSI_0__PWM base pointer */
#define MIPI_CSI_0__PWM                          ((PWM_Type *)MIPI_CSI_0__PWM_BASE)
/** Peripheral MIPI_CSI_1__PWM base address */
#define MIPI_CSI_1__PWM_BASE                     (0x58244000u)
/** Peripheral MIPI_CSI_1__PWM base pointer */
#define MIPI_CSI_1__PWM                          ((PWM_Type *)MIPI_CSI_1__PWM_BASE)
/** Peripheral RX_HDMI__PWM base address */
#define RX_HDMI__PWM_BASE                        (0x58264000u)
/** Peripheral RX_HDMI__PWM base pointer */
#define RX_HDMI__PWM                             ((PWM_Type *)RX_HDMI__PWM_BASE)
/** Array initializer of PWM peripheral base addresses */
#define PWM_BASE_ADDRS                           { DI_HDMI__PWM_BASE, DI_LVDS_0__PWM_BASE, DI_LVDS_1__PWM_BASE, DI_MIPI_0__PWM_BASE, DI_MIPI_1__PWM_BASE, LSIO__PWM0_BASE, LSIO__PWM1_BASE, LSIO__PWM2_BASE, LSIO__PWM3_BASE, LSIO__PWM4_BASE, LSIO__PWM5_BASE, LSIO__PWM6_BASE, LSIO__PWM7_BASE, MIPI_CSI_0__PWM_BASE, MIPI_CSI_1__PWM_BASE, RX_HDMI__PWM_BASE }
/** Array initializer of PWM peripheral base pointers */
#define PWM_BASE_PTRS                            { DI_HDMI__PWM, DI_LVDS_0__PWM, DI_LVDS_1__PWM, DI_MIPI_0__PWM, DI_MIPI_1__PWM, LSIO__PWM0, LSIO__PWM1, LSIO__PWM2, LSIO__PWM3, LSIO__PWM4, LSIO__PWM5, LSIO__PWM6, LSIO__PWM7, MIPI_CSI_0__PWM, MIPI_CSI_1__PWM, RX_HDMI__PWM }
/** Interrupt vectors for the PWM peripheral type */
#define PWM_IRQS                                 { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, LSIO_PWM0_INT_IRQn, LSIO_PWM1_INT_IRQn, LSIO_PWM2_INT_IRQn, LSIO_PWM3_INT_IRQn, LSIO_PWM4_INT_IRQn, LSIO_PWM5_INT_IRQn, LSIO_PWM6_INT_IRQn, LSIO_PWM7_INT_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }

/*!
 * @}
 */ /* end of group PWM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RGPIO Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RGPIO_Peripheral_Access_Layer RGPIO Peripheral Access Layer
 * @{
 */

/** RGPIO - Register Layout Typedef */
typedef struct {
  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
} RGPIO_Type;

/* ----------------------------------------------------------------------------
   -- RGPIO Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RGPIO_Register_Masks RGPIO Register Masks
 * @{
 */

/*! @name PDOR - Port Data Output Register */
/*! @{ */
#define RGPIO_PDOR_PDO_MASK                      (0xFFFFFFFFU)
#define RGPIO_PDOR_PDO_SHIFT                     (0U)
#define RGPIO_PDOR_PDO(x)                        (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO_SHIFT)) & RGPIO_PDOR_PDO_MASK)
/*! @} */

/*! @name PSOR - Port Set Output Register */
/*! @{ */
#define RGPIO_PSOR_PTSO_MASK                     (0xFFFFFFFFU)
#define RGPIO_PSOR_PTSO_SHIFT                    (0U)
#define RGPIO_PSOR_PTSO(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO_SHIFT)) & RGPIO_PSOR_PTSO_MASK)
/*! @} */

/*! @name PCOR - Port Clear Output Register */
/*! @{ */
#define RGPIO_PCOR_PTCO_MASK                     (0xFFFFFFFFU)
#define RGPIO_PCOR_PTCO_SHIFT                    (0U)
#define RGPIO_PCOR_PTCO(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO_SHIFT)) & RGPIO_PCOR_PTCO_MASK)
/*! @} */

/*! @name PTOR - Port Toggle Output Register */
/*! @{ */
#define RGPIO_PTOR_PTTO_MASK                     (0xFFFFFFFFU)
#define RGPIO_PTOR_PTTO_SHIFT                    (0U)
#define RGPIO_PTOR_PTTO(x)                       (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO_SHIFT)) & RGPIO_PTOR_PTTO_MASK)
/*! @} */

/*! @name PDIR - Port Data Input Register */
/*! @{ */
#define RGPIO_PDIR_PDI_MASK                      (0xFFFFFFFFU)
#define RGPIO_PDIR_PDI_SHIFT                     (0U)
#define RGPIO_PDIR_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI_SHIFT)) & RGPIO_PDIR_PDI_MASK)
/*! @} */

/*! @name PDDR - Port Data Direction Register */
/*! @{ */
#define RGPIO_PDDR_PDD_MASK                      (0xFFFFFFFFU)
#define RGPIO_PDDR_PDD_SHIFT                     (0U)
#define RGPIO_PDDR_PDD(x)                        (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD_SHIFT)) & RGPIO_PDDR_PDD_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RGPIO_Register_Masks */


/* RGPIO - Peripheral instance base addresses */
/** Peripheral CM4_0__RGPIO base address */
#define CM4_0__RGPIO_BASE                        (0x370F0000u)
/** Peripheral CM4_0__RGPIO base pointer */
#define CM4_0__RGPIO                             ((RGPIO_Type *)CM4_0__RGPIO_BASE)
/** Peripheral CM4_1__RGPIO base address */
#define CM4_1__RGPIO_BASE                        (0x410F0000u)
/** Peripheral CM4_1__RGPIO base pointer */
#define CM4_1__RGPIO                             ((RGPIO_Type *)CM4_1__RGPIO_BASE)
/** Peripheral SCU__RGPIO base address */
#define SCU__RGPIO_BASE                          (0x330F0000u)
/** Peripheral SCU__RGPIO base pointer */
#define SCU__RGPIO                               ((RGPIO_Type *)SCU__RGPIO_BASE)
/** Array initializer of RGPIO peripheral base addresses */
#define RGPIO_BASE_ADDRS                         { CM4_0__RGPIO_BASE, CM4_1__RGPIO_BASE, SCU__RGPIO_BASE }
/** Array initializer of RGPIO peripheral base pointers */
#define RGPIO_BASE_PTRS                          { CM4_0__RGPIO, CM4_1__RGPIO, SCU__RGPIO }

/*!
 * @}
 */ /* end of group RGPIO_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ROMCP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ROMCP_Peripheral_Access_Layer ROMCP Peripheral Access Layer
 * @{
 */

/** ROMCP - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[212];
  __IO uint32_t ROMPATCHD[8];                      /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */
  __IO uint32_t ROMPATCHCNTL;                      /**< ROMC Control Register, offset: 0xF4 */
       uint32_t ROMPATCHENH;                       /**< ROMC Enable Register High, offset: 0xF8 */
  __IO uint32_t ROMPATCHENL;                       /**< ROMC Enable Register Low, offset: 0xFC */
  __IO uint32_t ROMPATCHA[16];                     /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_1[200];
  __IO uint32_t ROMPATCHSR;                        /**< ROMC Status Register, offset: 0x208 */
} ROMCP_Type;

/* ----------------------------------------------------------------------------
   -- ROMCP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ROMCP_Register_Masks ROMCP Register Masks
 * @{
 */

/*! @name ROMPATCHD - ROMC Data Registers */
/*! @{ */
#define ROMCP_ROMPATCHD_DATAX_MASK               (0xFFFFFFFFU)
#define ROMCP_ROMPATCHD_DATAX_SHIFT              (0U)
#define ROMCP_ROMPATCHD_DATAX(x)                 (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHD_DATAX_SHIFT)) & ROMCP_ROMPATCHD_DATAX_MASK)
/*! @} */

/* The count of ROMCP_ROMPATCHD */
#define ROMCP_ROMPATCHD_COUNT                    (8U)

/*! @name ROMPATCHCNTL - ROMC Control Register */
/*! @{ */
#define ROMCP_ROMPATCHCNTL_DATAFIX_MASK          (0xFFU)
#define ROMCP_ROMPATCHCNTL_DATAFIX_SHIFT         (0U)
/*! DATAFIX - DATAFIX
 *  0b00000000..Address comparator triggers a opcode patch
 *  0b00000001..Address comparator triggers a data fix
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX(x)            (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX_MASK)
#define ROMCP_ROMPATCHCNTL_DIS_MASK              (0x20000000U)
#define ROMCP_ROMPATCHCNTL_DIS_SHIFT             (29U)
/*! DIS - DIS
 *  0b0..Does not affect any ROMC functions (default)
 *  0b1..Disable all ROMC functions: data fixing, and opcode patching
 */
#define ROMCP_ROMPATCHCNTL_DIS(x)                (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DIS_SHIFT)) & ROMCP_ROMPATCHCNTL_DIS_MASK)
/*! @} */

/*! @name ROMPATCHENL - ROMC Enable Register Low */
/*! @{ */
#define ROMCP_ROMPATCHENL_ENABLE_MASK            (0xFFFFU)
#define ROMCP_ROMPATCHENL_ENABLE_SHIFT           (0U)
/*! ENABLE - ENABLE
 *  0b0000000000000000..Address comparator disabled
 *  0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address
 */
#define ROMCP_ROMPATCHENL_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE_MASK)
/*! @} */

/*! @name ROMPATCHA - ROMC Address Registers */
/*! @{ */
#define ROMCP_ROMPATCHA_THUMBX_MASK              (0x1U)
#define ROMCP_ROMPATCHA_THUMBX_SHIFT             (0U)
/*! THUMBX - THUMBX
 *  0b0..ARM patch
 *  0b1..THUMB patch (ignore if data fix)
 */
#define ROMCP_ROMPATCHA_THUMBX(x)                (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHA_THUMBX_SHIFT)) & ROMCP_ROMPATCHA_THUMBX_MASK)
#define ROMCP_ROMPATCHA_ADDRX_MASK               (0x7FFFFEU)
#define ROMCP_ROMPATCHA_ADDRX_SHIFT              (1U)
#define ROMCP_ROMPATCHA_ADDRX(x)                 (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHA_ADDRX_SHIFT)) & ROMCP_ROMPATCHA_ADDRX_MASK)
/*! @} */

/* The count of ROMCP_ROMPATCHA */
#define ROMCP_ROMPATCHA_COUNT                    (16U)

/*! @name ROMPATCHSR - ROMC Status Register */
/*! @{ */
#define ROMCP_ROMPATCHSR_SOURCE_MASK             (0x3FU)
#define ROMCP_ROMPATCHSR_SOURCE_SHIFT            (0U)
/*! SOURCE - SOURCE
 *  0b000000..Address Comparator 0 matched
 *  0b000001..Address Comparator 1 matched
 *  0b001111..Address Comparator 15 matched
 */
#define ROMCP_ROMPATCHSR_SOURCE(x)               (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHSR_SOURCE_SHIFT)) & ROMCP_ROMPATCHSR_SOURCE_MASK)
#define ROMCP_ROMPATCHSR_SW_MASK                 (0x20000U)
#define ROMCP_ROMPATCHSR_SW_SHIFT                (17U)
/*! SW - SW
 *  0b0..no event or comparator collisions
 *  0b1..a collision has occurred
 */
#define ROMCP_ROMPATCHSR_SW(x)                   (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHSR_SW_SHIFT)) & ROMCP_ROMPATCHSR_SW_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ROMCP_Register_Masks */


/* ROMCP - Peripheral instance base addresses */
/** Peripheral LSIO__ROMCP base address */
#define LSIO__ROMCP_BASE                         (0x5D100000u)
/** Peripheral LSIO__ROMCP base pointer */
#define LSIO__ROMCP                              ((ROMCP_Type *)LSIO__ROMCP_BASE)
/** Peripheral SCU__ROMCP base address */
#define SCU__ROMCP_BASE                          (0x32060000u)
/** Peripheral SCU__ROMCP base pointer */
#define SCU__ROMCP                               ((ROMCP_Type *)SCU__ROMCP_BASE)
/** Array initializer of ROMCP peripheral base addresses */
#define ROMCP_BASE_ADDRS                         { LSIO__ROMCP_BASE, SCU__ROMCP_BASE }
/** Array initializer of ROMCP peripheral base pointers */
#define ROMCP_BASE_PTRS                          { LSIO__ROMCP, SCU__ROMCP }

/*!
 * @}
 */ /* end of group ROMCP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RX_HDMI_LPCG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RX_HDMI_LPCG_Peripheral_Access_Layer RX_HDMI_LPCG Peripheral Access Layer
 * @{
 */

/** RX_HDMI_LPCG - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_RX_HDMI_LPCG_0;               /**< na, offset: 0x0 */
  __IO uint32_t LPCG_RX_HDMI_LPCG_4;               /**< na, offset: 0x4 */
  __IO uint32_t LPCG_RX_HDMI_LPCG_8;               /**< na, offset: 0x8 */
  __IO uint32_t LPCG_RX_HDMI_LPCG_12;              /**< na, offset: 0xC */
  __IO uint32_t LPCG_RX_HDMI_LPCG_16;              /**< na, offset: 0x10 */
  __IO uint32_t LPCG_RX_HDMI_LPCG_20;              /**< na, offset: 0x14 */
  __IO uint32_t LPCG_RX_HDMI_LPCG_24;              /**< na, offset: 0x18 */
  __IO uint32_t LPCG_RX_HDMI_LPCG_28;              /**< na, offset: 0x1C */
  __IO uint32_t LPCG_RX_HDMI_LPCG_32;              /**< na, offset: 0x20 */
  __IO uint32_t LPCG_RX_HDMI_LPCG_36;              /**< na, offset: 0x24 */
} RX_HDMI_LPCG_Type;

/* ----------------------------------------------------------------------------
   -- RX_HDMI_LPCG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RX_HDMI_LPCG_Register_Masks RX_HDMI_LPCG Register Masks
 * @{
 */

/*! @name LPCG_RX_HDMI_LPCG_0 - na */
/*! @{ */
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_HWEN_MASK (0x1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_HWEN_SHIFT (0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_HWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_HWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_SWEN_MASK (0x2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_SWEN_SHIFT (1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_SWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_SWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_LPCG_rx_hdmi_lpcg_0_reserved_2_2_MASK (0x4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_LPCG_rx_hdmi_lpcg_0_reserved_2_2_SHIFT (2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_LPCG_rx_hdmi_lpcg_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_LPCG_rx_hdmi_lpcg_0_reserved_2_2_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_LPCG_rx_hdmi_lpcg_0_reserved_2_2_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_STOP_MASK (0x8U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_STOP_SHIFT (3U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_STOP_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_gpio_ipg_clk_s_STOP_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_LPCG_rx_hdmi_lpcg_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_LPCG_rx_hdmi_lpcg_0_reserved_4_31_SHIFT (4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_LPCG_rx_hdmi_lpcg_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_LPCG_rx_hdmi_lpcg_0_reserved_4_31_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_0_LPCG_rx_hdmi_lpcg_0_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_RX_HDMI_LPCG_4 - na */
/*! @{ */
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_HWEN_MASK (0x1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_HWEN_SHIFT (0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_HWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_HWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_SWEN_MASK (0x2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_SWEN_SHIFT (1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_SWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_SWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_LPCG_rx_hdmi_lpcg_4_reserved_2_2_MASK (0x4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_LPCG_rx_hdmi_lpcg_4_reserved_2_2_SHIFT (2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_LPCG_rx_hdmi_lpcg_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_LPCG_rx_hdmi_lpcg_4_reserved_2_2_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_LPCG_rx_hdmi_lpcg_4_reserved_2_2_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_STOP_MASK (0x8U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_STOP_SHIFT (3U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_STOP_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_pwm_ipg_clk_STOP_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_LPCG_rx_hdmi_lpcg_4_reserved_4_31_MASK (0xFFFFFFF0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_LPCG_rx_hdmi_lpcg_4_reserved_4_31_SHIFT (4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_LPCG_rx_hdmi_lpcg_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_LPCG_rx_hdmi_lpcg_4_reserved_4_31_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_4_LPCG_rx_hdmi_lpcg_4_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_RX_HDMI_LPCG_8 - na */
/*! @{ */
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_HWEN_MASK (0x1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_HWEN_SHIFT (0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_HWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_HWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_SWEN_MASK (0x2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_SWEN_SHIFT (1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_SWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_SWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_LPCG_rx_hdmi_lpcg_8_reserved_2_2_MASK (0x4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_LPCG_rx_hdmi_lpcg_8_reserved_2_2_SHIFT (2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_LPCG_rx_hdmi_lpcg_8_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_LPCG_rx_hdmi_lpcg_8_reserved_2_2_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_LPCG_rx_hdmi_lpcg_8_reserved_2_2_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_STOP_MASK (0x8U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_STOP_SHIFT (3U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_STOP_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_pwm_ipg_clk_s_STOP_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_LPCG_rx_hdmi_lpcg_8_reserved_4_31_MASK (0xFFFFFFF0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_LPCG_rx_hdmi_lpcg_8_reserved_4_31_SHIFT (4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_LPCG_rx_hdmi_lpcg_8_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_LPCG_rx_hdmi_lpcg_8_reserved_4_31_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_8_LPCG_rx_hdmi_lpcg_8_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_RX_HDMI_LPCG_12 - na */
/*! @{ */
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_0_0_MASK (0x1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_0_0_SHIFT (0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_0_0_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_0_0_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_pwm_ipg_clk_highfreq_SWEN_MASK (0x2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_pwm_ipg_clk_highfreq_SWEN_SHIFT (1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_pwm_ipg_clk_highfreq_SWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_pwm_ipg_clk_highfreq_SWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_pwm_ipg_clk_highfreq_SWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_2_2_MASK (0x4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_2_2_SHIFT (2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_2_2_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_2_2_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_pwm_ipg_clk_highfreq_STOP_MASK (0x8U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_pwm_ipg_clk_highfreq_STOP_SHIFT (3U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_pwm_ipg_clk_highfreq_STOP(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_pwm_ipg_clk_highfreq_STOP_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_pwm_ipg_clk_highfreq_STOP_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_4_31_MASK (0xFFFFFFF0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_4_31_SHIFT (4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_4_31_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_12_LPCG_rx_hdmi_lpcg_12_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_RX_HDMI_LPCG_16 - na */
/*! @{ */
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_0_0_MASK (0x1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_0_0_SHIFT (0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_0_0_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_0_0_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_lpi2c_lpi2c_clk_SWEN_MASK (0x2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_lpi2c_lpi2c_clk_SWEN_SHIFT (1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_lpi2c_lpi2c_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_lpi2c_lpi2c_clk_SWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_lpi2c_lpi2c_clk_SWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_2_2_MASK (0x4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_2_2_SHIFT (2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_2_2_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_2_2_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_lpi2c_lpi2c_clk_STOP_MASK (0x8U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_lpi2c_lpi2c_clk_STOP_SHIFT (3U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_lpi2c_lpi2c_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_lpi2c_lpi2c_clk_STOP_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_lpi2c_lpi2c_clk_STOP_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_4_31_MASK (0xFFFFFFF0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_4_31_SHIFT (4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_4_31_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_16_LPCG_rx_hdmi_lpcg_16_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_RX_HDMI_LPCG_20 - na */
/*! @{ */
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_MASK (0x1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_SHIFT (0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_HWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_SWEN_MASK (0x2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_SWEN_SHIFT (1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_SWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_SWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_LPCG_rx_hdmi_lpcg_20_reserved_2_2_MASK (0x4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_LPCG_rx_hdmi_lpcg_20_reserved_2_2_SHIFT (2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_LPCG_rx_hdmi_lpcg_20_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_LPCG_rx_hdmi_lpcg_20_reserved_2_2_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_LPCG_rx_hdmi_lpcg_20_reserved_2_2_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_STOP_MASK (0x8U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_STOP_SHIFT (3U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_STOP_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_lpi2c_lpi2c_div_clk_STOP_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_LPCG_rx_hdmi_lpcg_20_reserved_4_31_MASK (0xFFFFFFF0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_LPCG_rx_hdmi_lpcg_20_reserved_4_31_SHIFT (4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_LPCG_rx_hdmi_lpcg_20_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_LPCG_rx_hdmi_lpcg_20_reserved_4_31_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_20_LPCG_rx_hdmi_lpcg_20_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_RX_HDMI_LPCG_24 - na */
/*! @{ */
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_0_0_MASK (0x1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_0_0_SHIFT (0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_0_0_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_0_0_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_lpi2c_ipg_clk_SWEN_MASK (0x2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_lpi2c_ipg_clk_SWEN_SHIFT (1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_lpi2c_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_lpi2c_ipg_clk_SWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_lpi2c_ipg_clk_SWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_2_2_MASK (0x4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_2_2_SHIFT (2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_2_2_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_2_2_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_lpi2c_ipg_clk_STOP_MASK (0x8U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_lpi2c_ipg_clk_STOP_SHIFT (3U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_lpi2c_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_lpi2c_ipg_clk_STOP_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_lpi2c_ipg_clk_STOP_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_4_31_MASK (0xFFFFFFF0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_4_31_SHIFT (4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_4_31_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_24_LPCG_rx_hdmi_lpcg_24_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_RX_HDMI_LPCG_28 - na */
/*! @{ */
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_HWEN_MASK (0x1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_HWEN_SHIFT (0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_HWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_HWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_SWEN_MASK (0x2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_SWEN_SHIFT (1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_SWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_SWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_LPCG_rx_hdmi_lpcg_28_reserved_2_2_MASK (0x4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_LPCG_rx_hdmi_lpcg_28_reserved_2_2_SHIFT (2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_LPCG_rx_hdmi_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_LPCG_rx_hdmi_lpcg_28_reserved_2_2_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_LPCG_rx_hdmi_lpcg_28_reserved_2_2_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_STOP_MASK (0x8U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_STOP_SHIFT (3U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_STOP_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_lpi2c_ipg_clk_s_STOP_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_LPCG_rx_hdmi_lpcg_28_reserved_4_31_MASK (0xFFFFFFF0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_LPCG_rx_hdmi_lpcg_28_reserved_4_31_SHIFT (4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_LPCG_rx_hdmi_lpcg_28_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_LPCG_rx_hdmi_lpcg_28_reserved_4_31_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_28_LPCG_rx_hdmi_lpcg_28_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_RX_HDMI_LPCG_32 - na */
/*! @{ */
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_0_0_MASK (0x1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_0_0_SHIFT (0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_0_0_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_0_0_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_pixel_link_mst_clk_SWEN_MASK (0x2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_pixel_link_mst_clk_SWEN_SHIFT (1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_pixel_link_mst_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_pixel_link_mst_clk_SWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_pixel_link_mst_clk_SWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_2_2_MASK (0x4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_2_2_SHIFT (2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_2_2_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_2_2_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_pixel_link_mst_clk_STOP_MASK (0x8U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_pixel_link_mst_clk_STOP_SHIFT (3U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_pixel_link_mst_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_pixel_link_mst_clk_STOP_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_pixel_link_mst_clk_STOP_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_4_31_MASK (0xFFFFFFF0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_4_31_SHIFT (4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_4_31_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_32_LPCG_rx_hdmi_lpcg_32_reserved_4_31_MASK)
/*! @} */

/*! @name LPCG_RX_HDMI_LPCG_36 - na */
/*! @{ */
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_0_0_MASK (0x1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_0_0_SHIFT (0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_0_0_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_0_0_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_ss_rx_hdmi_pxl_enc_clk_SWEN_MASK (0x2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_ss_rx_hdmi_pxl_enc_clk_SWEN_SHIFT (1U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_ss_rx_hdmi_pxl_enc_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_ss_rx_hdmi_pxl_enc_clk_SWEN_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_ss_rx_hdmi_pxl_enc_clk_SWEN_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_2_2_MASK (0x4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_2_2_SHIFT (2U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_2_2_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_2_2_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_ss_rx_hdmi_pxl_enc_clk_STOP_MASK (0x8U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_ss_rx_hdmi_pxl_enc_clk_STOP_SHIFT (3U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_ss_rx_hdmi_pxl_enc_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_ss_rx_hdmi_pxl_enc_clk_STOP_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_ss_rx_hdmi_pxl_enc_clk_STOP_MASK)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_4_31_MASK (0xFFFFFFF0U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_4_31_SHIFT (4U)
#define RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_4_31_SHIFT)) & RX_HDMI_LPCG_LPCG_RX_HDMI_LPCG_36_LPCG_rx_hdmi_lpcg_36_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RX_HDMI_LPCG_Register_Masks */


/* RX_HDMI_LPCG - Peripheral instance base addresses */
/** Peripheral RX_HDMI__LPCG_GPIO_IPG_CLK_S base address */
#define RX_HDMI__LPCG_GPIO_IPG_CLK_S_BASE        (0x58263000u)
/** Peripheral RX_HDMI__LPCG_GPIO_IPG_CLK_S base pointer */
#define RX_HDMI__LPCG_GPIO_IPG_CLK_S             ((RX_HDMI_LPCG_Type *)RX_HDMI__LPCG_GPIO_IPG_CLK_S_BASE)
/** Array initializer of RX_HDMI_LPCG peripheral base addresses */
#define RX_HDMI_LPCG_BASE_ADDRS                  { RX_HDMI__LPCG_GPIO_IPG_CLK_S_BASE }
/** Array initializer of RX_HDMI_LPCG peripheral base pointers */
#define RX_HDMI_LPCG_BASE_PTRS                   { RX_HDMI__LPCG_GPIO_IPG_CLK_S }

/*!
 * @}
 */ /* end of group RX_HDMI_LPCG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SATA Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SATA_Peripheral_Access_Layer SATA Peripheral Access Layer
 * @{
 */

/** SATA - Register Layout Typedef */
typedef struct {
  __IO uint32_t PCTRL;                             /**< SERDES Control, offset: 0x0 */
  __IO uint32_t PCFG;                              /**< Port Config, offset: 0x4 */
  __IO uint32_t PPCFG;                             /**< Port Phy1Cfg, offset: 0x8 */
  __IO uint32_t PP2C;                              /**< Port Phy2Cfg, offset: 0xC */
  __IO uint32_t PP3C;                              /**< Port Phy3CfgRegister, offset: 0x10 */
  __IO uint32_t PP4C;                              /**< Port Phy4Cfg, offset: 0x14 */
  __IO uint32_t PP5C;                              /**< Port Phy5Cfg, offset: 0x18 */
  __IO uint32_t AXICC;                             /**< AXI CACHE Control, offset: 0x1C */
  __IO uint32_t PAXIC;                             /**< Port AXICfg, offset: 0x20 */
  __IO uint32_t AXIPC;                             /**< AXI PROT Control, offset: 0x24 */
  __IO uint32_t PTC;                               /**< Port TransCfg, offset: 0x28 */
  __I  uint32_t PTS;                               /**< Port TransStatus, offset: 0x2C */
  __IO uint32_t PLC;                               /**< Port LinkCfg, offset: 0x30 */
  __IO uint32_t PLC1;                              /**< Port LinkCfg1, offset: 0x34 */
  __IO uint32_t PLC2;                              /**< Port LinkCfg2, offset: 0x38 */
  __I  uint32_t PLS;                               /**< Port LinkStatus, offset: 0x3C */
  __IO uint32_t PLS1;                              /**< Port LinkStatus1, offset: 0x40 */
  __IO uint32_t PCMDC;                             /**< Port CmdConfig, offset: 0x44 */
  __IO uint32_t PPCS;                              /**< Port PhyControlStatus, offset: 0x48 */
  __I  uint32_t AMS;                               /**< AXI Master Status, offset: 0x4C */
  __IO uint32_t TCR;                               /**< Timer Control, offset: 0x50 */
} SATA_Type;

/* ----------------------------------------------------------------------------
   -- SATA Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SATA_Register_Masks SATA Register Masks
 * @{
 */

/*! @name PCTRL - SERDES Control */
/*! @{ */
#define SATA_PCTRL_SAV_MASK                      (0xFFFFU)
#define SATA_PCTRL_SAV_SHIFT                     (0U)
#define SATA_PCTRL_SAV(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PCTRL_SAV_SHIFT)) & SATA_PCTRL_SAV_MASK)
#define SATA_PCTRL_SRWD_MASK                     (0xFF0000U)
#define SATA_PCTRL_SRWD_SHIFT                    (16U)
#define SATA_PCTRL_SRWD(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PCTRL_SRWD_SHIFT)) & SATA_PCTRL_SRWD_MASK)
#define SATA_PCTRL_SRI_MASK                      (0x1000000U)
#define SATA_PCTRL_SRI_SHIFT                     (24U)
/*! SRI - SRI: Read/Write indicator to SERDES bus controller. 1= Write, 0 = Read
 *  0b0..Read
 *  0b1..Write
 */
#define SATA_PCTRL_SRI(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PCTRL_SRI_SHIFT)) & SATA_PCTRL_SRI_MASK)
#define SATA_PCTRL_BSY_MASK                      (0x80000000U)
#define SATA_PCTRL_BSY_SHIFT                     (31U)
#define SATA_PCTRL_BSY(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PCTRL_BSY_SHIFT)) & SATA_PCTRL_BSY_MASK)
/*! @} */

/*! @name PCFG - Port Config */
/*! @{ */
#define SATA_PCFG_PAD_MASK                       (0x3FU)
#define SATA_PCFG_PAD_SHIFT                      (0U)
/*! PAD - PAD: Port Address
 *  0b000010..Address port 0 configuration / status register set
 *  0b000011..Address port 1 configuration / status register set
 */
#define SATA_PCFG_PAD(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PCFG_PAD_SHIFT)) & SATA_PCFG_PAD_MASK)
#define SATA_PCFG_CISE_MASK                      (0x100U)
#define SATA_PCFG_CISE_SHIFT                     (8U)
#define SATA_PCFG_CISE(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PCFG_CISE_SHIFT)) & SATA_PCFG_CISE_MASK)
#define SATA_PCFG_TPRS_MASK                      (0x7000U)
#define SATA_PCFG_TPRS_SHIFT                     (12U)
#define SATA_PCFG_TPRS(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PCFG_TPRS_SHIFT)) & SATA_PCFG_TPRS_MASK)
#define SATA_PCFG_TPSS_MASK                      (0x7F0000U)
#define SATA_PCFG_TPSS_SHIFT                     (16U)
#define SATA_PCFG_TPSS(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PCFG_TPSS_SHIFT)) & SATA_PCFG_TPSS_MASK)
/*! @} */

/*! @name PPCFG - Port Phy1Cfg */
/*! @{ */
#define SATA_PPCFG_TTA_MASK                      (0x1FFFFU)
#define SATA_PPCFG_TTA_SHIFT                     (0U)
#define SATA_PPCFG_TTA(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PPCFG_TTA_SHIFT)) & SATA_PPCFG_TTA_MASK)
#define SATA_PPCFG_SNM_MASK                      (0x20000U)
#define SATA_PPCFG_SNM_SHIFT                     (17U)
#define SATA_PPCFG_SNM(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PPCFG_SNM_SHIFT)) & SATA_PPCFG_SNM_MASK)
#define SATA_PPCFG_SNR_MASK                      (0x40000U)
#define SATA_PPCFG_SNR_SHIFT                     (18U)
#define SATA_PPCFG_SNR(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PPCFG_SNR_SHIFT)) & SATA_PPCFG_SNR_MASK)
#define SATA_PPCFG_FPR_MASK                      (0x100000U)
#define SATA_PPCFG_FPR_SHIFT                     (20U)
/*! FPR - FPR: Force PHY Ready. This signal determines how PhyReady is driven
 *  0b0..normal operation mode
 *  0b1..frcPhyRdy: In this mode the OOB and speed negotiation states of the Phy Init State machine are bypassed. The Phy Init state machine directly enters PhyReady after reset. Tx buffer IDLE control is forced off
 */
#define SATA_PPCFG_FPR(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PPCFG_FPR_SHIFT)) & SATA_PPCFG_FPR_MASK)
#define SATA_PPCFG_PBPS_MASK                     (0xE00000U)
#define SATA_PPCFG_PBPS_SHIFT                    (21U)
/*! PBPS - PBPS: PhyControl BIST Pattern Select
 *  0b000..LBP (Generator Only)
 *  0b001..LFTP
 *  0b010..MFTP
 *  0b011..HFTP
 *  0b100..PRBS Pattern
 *  0b101..BIST Pattern (Default Pattern)
 */
#define SATA_PPCFG_PBPS(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PPCFG_PBPS_SHIFT)) & SATA_PPCFG_PBPS_MASK)
#define SATA_PPCFG_PBPE_MASK                     (0x1000000U)
#define SATA_PPCFG_PBPE_SHIFT                    (24U)
#define SATA_PPCFG_PBPE(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PPCFG_PBPE_SHIFT)) & SATA_PPCFG_PBPE_MASK)
#define SATA_PPCFG_PBCE_MASK                     (0x2000000U)
#define SATA_PPCFG_PBCE_SHIFT                    (25U)
#define SATA_PPCFG_PBCE(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PPCFG_PBCE_SHIFT)) & SATA_PPCFG_PBCE_MASK)
#define SATA_PPCFG_PBPNA_MASK                    (0x4000000U)
#define SATA_PPCFG_PBPNA_SHIFT                   (26U)
#define SATA_PPCFG_PBPNA(x)                      (((uint32_t)(((uint32_t)(x)) << SATA_PPCFG_PBPNA_SHIFT)) & SATA_PPCFG_PBPNA_MASK)
#define SATA_PPCFG_STB_MASK                      (0x8000000U)
#define SATA_PPCFG_STB_SHIFT                     (27U)
#define SATA_PPCFG_STB(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PPCFG_STB_SHIFT)) & SATA_PPCFG_STB_MASK)
#define SATA_PPCFG_PSSO_MASK                     (0x10000000U)
#define SATA_PPCFG_PSSO_SHIFT                    (28U)
/*! PSSO - PSSO: PhyControl select SERDES OOB or internally decoded OOB signaling as inputs
 *  0b0..Select internal decoded OOB signaling
 *  0b1..Select SERDES decoded OOB signaling
 */
#define SATA_PPCFG_PSSO(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PPCFG_PSSO_SHIFT)) & SATA_PPCFG_PSSO_MASK)
#define SATA_PPCFG_PSS_MASK                      (0x20000000U)
#define SATA_PPCFG_PSS_SHIFT                     (29U)
#define SATA_PPCFG_PSS(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PPCFG_PSS_SHIFT)) & SATA_PPCFG_PSS_MASK)
#define SATA_PPCFG_ERSN_MASK                     (0x40000000U)
#define SATA_PPCFG_ERSN_SHIFT                    (30U)
#define SATA_PPCFG_ERSN(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PPCFG_ERSN_SHIFT)) & SATA_PPCFG_ERSN_MASK)
#define SATA_PPCFG_ESDF_MASK                     (0x80000000U)
#define SATA_PPCFG_ESDF_SHIFT                    (31U)
#define SATA_PPCFG_ESDF(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PPCFG_ESDF_SHIFT)) & SATA_PPCFG_ESDF_MASK)
/*! @} */

/*! @name PP2C - Port Phy2Cfg */
/*! @{ */
#define SATA_PP2C_CIBGMN_MASK                    (0xFFU)
#define SATA_PP2C_CIBGMN_SHIFT                   (0U)
#define SATA_PP2C_CIBGMN(x)                      (((uint32_t)(((uint32_t)(x)) << SATA_PP2C_CIBGMN_SHIFT)) & SATA_PP2C_CIBGMN_MASK)
#define SATA_PP2C_CIBGMX_MASK                    (0xFF00U)
#define SATA_PP2C_CIBGMX_SHIFT                   (8U)
#define SATA_PP2C_CIBGMX(x)                      (((uint32_t)(((uint32_t)(x)) << SATA_PP2C_CIBGMX_SHIFT)) & SATA_PP2C_CIBGMX_MASK)
#define SATA_PP2C_CIBGN_MASK                     (0xFF0000U)
#define SATA_PP2C_CIBGN_SHIFT                    (16U)
#define SATA_PP2C_CIBGN(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PP2C_CIBGN_SHIFT)) & SATA_PP2C_CIBGN_MASK)
#define SATA_PP2C_CINMP_MASK                     (0xFF000000U)
#define SATA_PP2C_CINMP_SHIFT                    (24U)
#define SATA_PP2C_CINMP(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PP2C_CINMP_SHIFT)) & SATA_PP2C_CINMP_MASK)
/*! @} */

/*! @name PP3C - Port Phy3CfgRegister */
/*! @{ */
#define SATA_PP3C_CWBGMN_MASK                    (0xFFU)
#define SATA_PP3C_CWBGMN_SHIFT                   (0U)
#define SATA_PP3C_CWBGMN(x)                      (((uint32_t)(((uint32_t)(x)) << SATA_PP3C_CWBGMN_SHIFT)) & SATA_PP3C_CWBGMN_MASK)
#define SATA_PP3C_CWBGMX_MASK                    (0xFF00U)
#define SATA_PP3C_CWBGMX_SHIFT                   (8U)
#define SATA_PP3C_CWBGMX(x)                      (((uint32_t)(((uint32_t)(x)) << SATA_PP3C_CWBGMX_SHIFT)) & SATA_PP3C_CWBGMX_MASK)
#define SATA_PP3C_CWBGN_MASK                     (0xFF0000U)
#define SATA_PP3C_CWBGN_SHIFT                    (16U)
#define SATA_PP3C_CWBGN(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PP3C_CWBGN_SHIFT)) & SATA_PP3C_CWBGN_MASK)
#define SATA_PP3C_CWNMP_MASK                     (0xFF000000U)
#define SATA_PP3C_CWNMP_SHIFT                    (24U)
#define SATA_PP3C_CWNMP(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PP3C_CWNMP_SHIFT)) & SATA_PP3C_CWNMP_MASK)
/*! @} */

/*! @name PP4C - Port Phy4Cfg */
/*! @{ */
#define SATA_PP4C_BMX_MASK                       (0xFFU)
#define SATA_PP4C_BMX_SHIFT                      (0U)
#define SATA_PP4C_BMX(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PP4C_BMX_SHIFT)) & SATA_PP4C_BMX_MASK)
#define SATA_PP4C_BNM_MASK                       (0xFF00U)
#define SATA_PP4C_BNM_SHIFT                      (8U)
#define SATA_PP4C_BNM(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PP4C_BNM_SHIFT)) & SATA_PP4C_BNM_MASK)
#define SATA_PP4C_SFD_MASK                       (0xFF0000U)
#define SATA_PP4C_SFD_SHIFT                      (16U)
#define SATA_PP4C_SFD(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PP4C_SFD_SHIFT)) & SATA_PP4C_SFD_MASK)
#define SATA_PP4C_PTST_MASK                      (0xFF000000U)
#define SATA_PP4C_PTST_SHIFT                     (24U)
#define SATA_PP4C_PTST(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PP4C_PTST_SHIFT)) & SATA_PP4C_PTST_MASK)
/*! @} */

/*! @name PP5C - Port Phy5Cfg */
/*! @{ */
#define SATA_PP5C_RIT_MASK                       (0xFFFFFU)
#define SATA_PP5C_RIT_SHIFT                      (0U)
#define SATA_PP5C_RIT(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PP5C_RIT_SHIFT)) & SATA_PP5C_RIT_MASK)
#define SATA_PP5C_RCT_MASK                       (0xFFF00000U)
#define SATA_PP5C_RCT_SHIFT                      (20U)
#define SATA_PP5C_RCT(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PP5C_RCT_SHIFT)) & SATA_PP5C_RCT_MASK)
/*! @} */

/*! @name AXICC - AXI CACHE Control */
/*! @{ */
#define SATA_AXICC_ARCA_MASK                     (0xFU)
#define SATA_AXICC_ARCA_SHIFT                    (0U)
#define SATA_AXICC_ARCA(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXICC_ARCA_SHIFT)) & SATA_AXICC_ARCA_MASK)
#define SATA_AXICC_ARCF_MASK                     (0xF0U)
#define SATA_AXICC_ARCF_SHIFT                    (4U)
#define SATA_AXICC_ARCF(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXICC_ARCF_SHIFT)) & SATA_AXICC_ARCF_MASK)
#define SATA_AXICC_ARCH_MASK                     (0xF00U)
#define SATA_AXICC_ARCH_SHIFT                    (8U)
#define SATA_AXICC_ARCH(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXICC_ARCH_SHIFT)) & SATA_AXICC_ARCH_MASK)
#define SATA_AXICC_ARCP_MASK                     (0xF000U)
#define SATA_AXICC_ARCP_SHIFT                    (12U)
#define SATA_AXICC_ARCP(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXICC_ARCP_SHIFT)) & SATA_AXICC_ARCP_MASK)
#define SATA_AXICC_AWCFD_MASK                    (0xF0000U)
#define SATA_AXICC_AWCFD_SHIFT                   (16U)
#define SATA_AXICC_AWCFD(x)                      (((uint32_t)(((uint32_t)(x)) << SATA_AXICC_AWCFD_SHIFT)) & SATA_AXICC_AWCFD_MASK)
#define SATA_AXICC_AWCD_MASK                     (0xF00000U)
#define SATA_AXICC_AWCD_SHIFT                    (20U)
#define SATA_AXICC_AWCD(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXICC_AWCD_SHIFT)) & SATA_AXICC_AWCD_MASK)
#define SATA_AXICC_AWCF_MASK                     (0xF000000U)
#define SATA_AXICC_AWCF_SHIFT                    (24U)
#define SATA_AXICC_AWCF(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXICC_AWCF_SHIFT)) & SATA_AXICC_AWCF_MASK)
#define SATA_AXICC_EARC_MASK                     (0x20000000U)
#define SATA_AXICC_EARC_SHIFT                    (29U)
#define SATA_AXICC_EARC(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXICC_EARC_SHIFT)) & SATA_AXICC_EARC_MASK)
/*! @} */

/*! @name PAXIC - Port AXICfg */
/*! @{ */
#define SATA_PAXIC_ADBW_MASK                     (0x3U)
#define SATA_PAXIC_ADBW_SHIFT                    (0U)
/*! ADBW - AXI Data Bus Width (ADBW)
 *  0b00..Data Bus Width 32 bits
 *  0b01..Data Bus width 64 bits
 *  0b10..Data Bus Width 128 bits
 */
#define SATA_PAXIC_ADBW(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PAXIC_ADBW_SHIFT)) & SATA_PAXIC_ADBW_MASK)
#define SATA_PAXIC_MAWID_MASK                    (0xF0U)
#define SATA_PAXIC_MAWID_SHIFT                   (4U)
#define SATA_PAXIC_MAWID(x)                      (((uint32_t)(((uint32_t)(x)) << SATA_PAXIC_MAWID_SHIFT)) & SATA_PAXIC_MAWID_MASK)
#define SATA_PAXIC_MAWIDD_MASK                   (0xF00U)
#define SATA_PAXIC_MAWIDD_SHIFT                  (8U)
#define SATA_PAXIC_MAWIDD(x)                     (((uint32_t)(((uint32_t)(x)) << SATA_PAXIC_MAWIDD_SHIFT)) & SATA_PAXIC_MAWIDD_MASK)
#define SATA_PAXIC_MARID_MASK                    (0xF000U)
#define SATA_PAXIC_MARID_SHIFT                   (12U)
#define SATA_PAXIC_MARID(x)                      (((uint32_t)(((uint32_t)(x)) << SATA_PAXIC_MARID_SHIFT)) & SATA_PAXIC_MARID_MASK)
#define SATA_PAXIC_MARIDD_MASK                   (0xF0000U)
#define SATA_PAXIC_MARIDD_SHIFT                  (16U)
#define SATA_PAXIC_MARIDD(x)                     (((uint32_t)(((uint32_t)(x)) << SATA_PAXIC_MARIDD_SHIFT)) & SATA_PAXIC_MARIDD_MASK)
#define SATA_PAXIC_OTL_MASK                      (0xF00000U)
#define SATA_PAXIC_OTL_SHIFT                     (20U)
#define SATA_PAXIC_OTL(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PAXIC_OTL_SHIFT)) & SATA_PAXIC_OTL_MASK)
#define SATA_PAXIC_ECM_MASK                      (0x1000000U)
#define SATA_PAXIC_ECM_SHIFT                     (24U)
#define SATA_PAXIC_ECM(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PAXIC_ECM_SHIFT)) & SATA_PAXIC_ECM_MASK)
#define SATA_PAXIC_AAO_MASK                      (0x2000000U)
#define SATA_PAXIC_AAO_SHIFT                     (25U)
#define SATA_PAXIC_AAO(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PAXIC_AAO_SHIFT)) & SATA_PAXIC_AAO_MASK)
#define SATA_PAXIC_AXIPE_MASK                    (0x4000000U)
#define SATA_PAXIC_AXIPE_SHIFT                   (26U)
#define SATA_PAXIC_AXIPE(x)                      (((uint32_t)(((uint32_t)(x)) << SATA_PAXIC_AXIPE_SHIFT)) & SATA_PAXIC_AXIPE_MASK)
#define SATA_PAXIC_AXIPT_MASK                    (0x8000000U)
#define SATA_PAXIC_AXIPT_SHIFT                   (27U)
/*! AXIPT - AXI Parity Type (AXIPT): 1 = Odd Parity, 0 = Even Parity
 *  0b0..Even Parity
 *  0b1..Odd Parity
 */
#define SATA_PAXIC_AXIPT(x)                      (((uint32_t)(((uint32_t)(x)) << SATA_PAXIC_AXIPT_SHIFT)) & SATA_PAXIC_AXIPT_MASK)
#define SATA_PAXIC_ENZP_MASK                     (0x10000000U)
#define SATA_PAXIC_ENZP_SHIFT                    (28U)
#define SATA_PAXIC_ENZP(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PAXIC_ENZP_SHIFT)) & SATA_PAXIC_ENZP_MASK)
#define SATA_PAXIC_EDAS_MASK                     (0x20000000U)
#define SATA_PAXIC_EDAS_SHIFT                    (29U)
#define SATA_PAXIC_EDAS(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PAXIC_EDAS_SHIFT)) & SATA_PAXIC_EDAS_MASK)
/*! @} */

/*! @name AXIPC - AXI PROT Control */
/*! @{ */
#define SATA_AXIPC_ARPD_MASK                     (0x7U)
#define SATA_AXIPC_ARPD_SHIFT                    (0U)
#define SATA_AXIPC_ARPD(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXIPC_ARPD_SHIFT)) & SATA_AXIPC_ARPD_MASK)
#define SATA_AXIPC_ARPF_MASK                     (0x70U)
#define SATA_AXIPC_ARPF_SHIFT                    (4U)
#define SATA_AXIPC_ARPF(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXIPC_ARPF_SHIFT)) & SATA_AXIPC_ARPF_MASK)
#define SATA_AXIPC_ARPH_MASK                     (0x700U)
#define SATA_AXIPC_ARPH_SHIFT                    (8U)
#define SATA_AXIPC_ARPH(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXIPC_ARPH_SHIFT)) & SATA_AXIPC_ARPH_MASK)
#define SATA_AXIPC_ARPP_MASK                     (0x7000U)
#define SATA_AXIPC_ARPP_SHIFT                    (12U)
#define SATA_AXIPC_ARPP(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXIPC_ARPP_SHIFT)) & SATA_AXIPC_ARPP_MASK)
#define SATA_AXIPC_AWPFD_MASK                    (0x70000U)
#define SATA_AXIPC_AWPFD_SHIFT                   (16U)
#define SATA_AXIPC_AWPFD(x)                      (((uint32_t)(((uint32_t)(x)) << SATA_AXIPC_AWPFD_SHIFT)) & SATA_AXIPC_AWPFD_MASK)
#define SATA_AXIPC_AWPD_MASK                     (0x700000U)
#define SATA_AXIPC_AWPD_SHIFT                    (20U)
#define SATA_AXIPC_AWPD(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXIPC_AWPD_SHIFT)) & SATA_AXIPC_AWPD_MASK)
#define SATA_AXIPC_AWPF_MASK                     (0x7000000U)
#define SATA_AXIPC_AWPF_SHIFT                    (24U)
#define SATA_AXIPC_AWPF(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXIPC_AWPF_SHIFT)) & SATA_AXIPC_AWPF_MASK)
#define SATA_AXIPC_EAWP_MASK                     (0x10000000U)
#define SATA_AXIPC_EAWP_SHIFT                    (28U)
#define SATA_AXIPC_EAWP(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXIPC_EAWP_SHIFT)) & SATA_AXIPC_EAWP_MASK)
#define SATA_AXIPC_EARP_MASK                     (0x20000000U)
#define SATA_AXIPC_EARP_SHIFT                    (29U)
#define SATA_AXIPC_EARP(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_AXIPC_EARP_SHIFT)) & SATA_AXIPC_EARP_MASK)
/*! @} */

/*! @name PTC - Port TransCfg */
/*! @{ */
#define SATA_PTC_RXWM_MASK                       (0x7FU)
#define SATA_PTC_RXWM_SHIFT                      (0U)
#define SATA_PTC_RXWM(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PTC_RXWM_SHIFT)) & SATA_PTC_RXWM_MASK)
#define SATA_PTC_ENBD_MASK                       (0x100U)
#define SATA_PTC_ENBD_SHIFT                      (8U)
#define SATA_PTC_ENBD(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PTC_ENBD_SHIFT)) & SATA_PTC_ENBD_MASK)
#define SATA_PTC_ITM_MASK                        (0x200U)
#define SATA_PTC_ITM_SHIFT                       (9U)
#define SATA_PTC_ITM(x)                          (((uint32_t)(((uint32_t)(x)) << SATA_PTC_ITM_SHIFT)) & SATA_PTC_ITM_MASK)
/*! @} */

/*! @name PTS - Port TransStatus */
/*! @{ */
#define SATA_PTS_RXSM_MASK                       (0xFU)
#define SATA_PTS_RXSM_SHIFT                      (0U)
/*! RXSM - Rx State Machine (RXSM)
 *  0b0000..p_rx_idle
 *  0b0001..p_rx_enable
 *  0b0010..p_rx_datafis
 *  0b0011..p_rx_datafis_rxd
 *  0b0100..p_rx_nondatafis
 *  0b0101..p_rx_unknownfis
 *  0b0110..p_rx_unknownfis_rxd
 *  0b0111..p_rx_badcrc
 *  0b1000..p_rx_good
 *  0b1001..p_rx_bad
 *  0b1010..p_rx_reset
 *  0b1011..p_rx_cmdreset
 *  0b1100..p_rx_cmdreset_comp
 *  0b1101..p_rx_reset_oflow
 *  0b1110..p_rx_forcebad
 */
#define SATA_PTS_RXSM(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PTS_RXSM_SHIFT)) & SATA_PTS_RXSM_MASK)
#define SATA_PTS_TXSM_MASK                       (0x1F0U)
#define SATA_PTS_TXSM_SHIFT                      (4U)
/*! TXSM - Tx State Machine (TXSM)
 *  0b00000..TxTrnIdle
 *  0b00001..TxTrnReset
 *  0b00010..TxTrnWaitResetComplete
 *  0b00011..TxTrnNonDataInitial
 *  0b00100..TxTrnNonDataAbort
 *  0b00101..TxTrnNonDataSend
 *  0b00110..TxTrnNonDataComp
 *  0b00111..TxTrnNonDataOk
 *  0b01000..TxTrnNonDataNotOk
 *  0b01001..TxTrnDataHeader
 *  0b01010..TxTrnDataHeaderOut
 *  0b01011..TxTrnDataSend
 *  0b01100..TxTrnDataComp
 *  0b01101..TxTrnDataNotOk
 *  0b01110..TxTrnDataOk
 *  0b01111..TxTrnCmdReset
 *  0b10000..TxTrnCmdResetComp
 *  0b10001..TxTrnCmdResetOverFlow
 *  0b10010..TxTrnNonDataBackDown
 */
#define SATA_PTS_TXSM(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PTS_TXSM_SHIFT)) & SATA_PTS_TXSM_MASK)
/*! @} */

/*! @name PLC - Port LinkCfg */
/*! @{ */
#define SATA_PLC_TXBC_MASK                       (0x1U)
#define SATA_PLC_TXBC_SHIFT                      (0U)
#define SATA_PLC_TXBC(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PLC_TXBC_SHIFT)) & SATA_PLC_TXBC_MASK)
#define SATA_PLC_RXBC_MASK                       (0x2U)
#define SATA_PLC_RXBC_SHIFT                      (1U)
#define SATA_PLC_RXBC(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PLC_RXBC_SHIFT)) & SATA_PLC_RXBC_MASK)
#define SATA_PLC_TXC_MASK                        (0x4U)
#define SATA_PLC_TXC_SHIFT                       (2U)
#define SATA_PLC_TXC(x)                          (((uint32_t)(((uint32_t)(x)) << SATA_PLC_TXC_SHIFT)) & SATA_PLC_TXC_MASK)
#define SATA_PLC_TXPJ_MASK                       (0x8U)
#define SATA_PLC_TXPJ_SHIFT                      (3U)
#define SATA_PLC_TXPJ(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PLC_TXPJ_SHIFT)) & SATA_PLC_TXPJ_MASK)
#define SATA_PLC_TXSE_MASK                       (0x10U)
#define SATA_PLC_TXSE_SHIFT                      (4U)
#define SATA_PLC_TXSE(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PLC_TXSE_SHIFT)) & SATA_PLC_TXSE_MASK)
#define SATA_PLC_RXSE_MASK                       (0x20U)
#define SATA_PLC_RXSE_SHIFT                      (5U)
#define SATA_PLC_RXSE(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PLC_RXSE_SHIFT)) & SATA_PLC_RXSE_MASK)
#define SATA_PLC_S4A_MASK                        (0x40U)
#define SATA_PLC_S4A_SHIFT                       (6U)
#define SATA_PLC_S4A(x)                          (((uint32_t)(((uint32_t)(x)) << SATA_PLC_S4A_SHIFT)) & SATA_PLC_S4A_MASK)
#define SATA_PLC_EPNRT_MASK                      (0x80U)
#define SATA_PLC_EPNRT_SHIFT                     (7U)
#define SATA_PLC_EPNRT(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PLC_EPNRT_SHIFT)) & SATA_PLC_EPNRT_MASK)
#define SATA_PLC_AIR_MASK                        (0xFF00U)
#define SATA_PLC_AIR_SHIFT                       (8U)
#define SATA_PLC_AIR(x)                          (((uint32_t)(((uint32_t)(x)) << SATA_PLC_AIR_SHIFT)) & SATA_PLC_AIR_MASK)
#define SATA_PLC_PRT_MASK                        (0x3FF0000U)
#define SATA_PLC_PRT_SHIFT                       (16U)
#define SATA_PLC_PRT(x)                          (((uint32_t)(((uint32_t)(x)) << SATA_PLC_PRT_SHIFT)) & SATA_PLC_PRT_MASK)
#define SATA_PLC_POE_MASK                        (0x4000000U)
#define SATA_PLC_POE_SHIFT                       (26U)
#define SATA_PLC_POE(x)                          (((uint32_t)(((uint32_t)(x)) << SATA_PLC_POE_SHIFT)) & SATA_PLC_POE_MASK)
#define SATA_PLC_PMPRA_MASK                      (0xF8000000U)
#define SATA_PLC_PMPRA_SHIFT                     (27U)
#define SATA_PLC_PMPRA(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PLC_PMPRA_SHIFT)) & SATA_PLC_PMPRA_MASK)
/*! @} */

/*! @name PLC1 - Port LinkCfg1 */
/*! @{ */
#define SATA_PLC1_POS_MASK                       (0x3FU)
#define SATA_PLC1_POS_SHIFT                      (0U)
#define SATA_PLC1_POS(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PLC1_POS_SHIFT)) & SATA_PLC1_POS_MASK)
#define SATA_PLC1_CD_MASK                        (0x40U)
#define SATA_PLC1_CD_SHIFT                       (6U)
#define SATA_PLC1_CD(x)                          (((uint32_t)(((uint32_t)(x)) << SATA_PLC1_CD_SHIFT)) & SATA_PLC1_CD_MASK)
/*! @} */

/*! @name PLC2 - Port LinkCfg2 */
/*! @{ */
#define SATA_PLC2_OP_MASK                        (0xFFFFFFFFU)
#define SATA_PLC2_OP_SHIFT                       (0U)
#define SATA_PLC2_OP(x)                          (((uint32_t)(((uint32_t)(x)) << SATA_PLC2_OP_SHIFT)) & SATA_PLC2_OP_MASK)
/*! @} */

/*! @name PLS - Port LinkStatus */
/*! @{ */
#define SATA_PLS_LLS_MASK                        (0x3FU)
#define SATA_PLS_LLS_SHIFT                       (0U)
/*! LLS - LAT_LINK_STATE (LLS): These six bits specify the current value of the Link Layer State Machine at the time the Status0 register is read
 *  0b000000..L_Reset
 *  0b000001..L_Idle
 *  0b000010..HL_SendChkRdy
 *  0b000011..DL_SendChkRdy
 *  0b000100..L_TPMPartial
 *  0b000101..L_TPMSlumber
 *  0b000110..L_RcvWaitFifo
 *  0b000111..L_PMOff
 *  0b001000..L_PMDeny
 *  0b001001..L_NoCommErr
 *  0b001010..L_NoComm
 *  0b001011..L_SendAlign
 *  0b001100..L_SendSOF
 *  0b001101..L_SendData
 *  0b001110..WAIT_FOR_SYNC
 *  0b001111..L_SendCRC
 *  0b010000..L_SendHold
 *  0b010001..L_RcvHold
 *  0b010010..L_SendEOF
 *  0b010011..L_Wait
 *  0b010100..L_ChkPhyRdy
 *  0b010101..L_NoCommPower
 *  0b010110..L_WakeUp1
 *  0b010111..L_WakeUp2
 *  0b011000..L_RcvChkRdy
 *  0b011001..L_RcvData
 *  0b011010..L_BadEnd
 *  0b011011..L_RcvEOF
 *  0b011100..L_SendHoldA
 *  0b011101..L_Hold
 *  0b011110..L_GoodCRC
 *  0b011111..L_GoodEnd
 *  0b100000..BISTALIGN
 *  0b100001..BISTSOF
 *  0b100010..BIST0
 *  0b100011..BIST1
 *  0b100100..L_GoodEndLock
 *  0b100101..OneFSendOneSyncLock
 *  0b100110..SFSendOneSyncLock
 *  0b100111..HL_SendChkRdyLock
 *  0b101000..waitForSyncLock
 *  0b101001..L_NoPmnak
 */
#define SATA_PLS_LLS(x)                          (((uint32_t)(((uint32_t)(x)) << SATA_PLS_LLS_SHIFT)) & SATA_PLS_LLS_MASK)
#define SATA_PLS_SRRN_MASK                       (0xFF000U)
#define SATA_PLS_SRRN_SHIFT                      (12U)
#define SATA_PLS_SRRN(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PLS_SRRN_SHIFT)) & SATA_PLS_SRRN_MASK)
#define SATA_PLS_DMBW_MASK                       (0xF00000U)
#define SATA_PLS_DMBW_SHIFT                      (20U)
/*! DMBW - DMA Master bus width (DMBW): 0 = 32 bit, 1 = 64 bit, 2 = 128 bit
 *  0b0000..32 Bit
 *  0b0001..64 Bit
 *  0b0010..128 Bit
 */
#define SATA_PLS_DMBW(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PLS_DMBW_SHIFT)) & SATA_PLS_DMBW_MASK)
#define SATA_PLS_DMB_MASK                        (0xF000000U)
#define SATA_PLS_DMB_SHIFT                       (24U)
/*! DMB - DMA Master bus type (DMB): 0 = AHB, 1 = AXI
 *  0b0000..AHB
 *  0b0001..AXI
 */
#define SATA_PLS_DMB(x)                          (((uint32_t)(((uint32_t)(x)) << SATA_PLS_DMB_SHIFT)) & SATA_PLS_DMB_MASK)
#define SATA_PLS_SVN_MASK                        (0xF0000000U)
#define SATA_PLS_SVN_SHIFT                       (28U)
/*! SVN - SATA Version (SVN): indicates the version of the SATA protocol supported by the controller. 1 = GEN1, 2 = GEN2, 3 = GEN3
 *  0b0001..Gen1
 *  0b0010..Gen2
 *  0b0011..Gen3
 */
#define SATA_PLS_SVN(x)                          (((uint32_t)(((uint32_t)(x)) << SATA_PLS_SVN_SHIFT)) & SATA_PLS_SVN_MASK)
/*! @} */

/*! @name PLS1 - Port LinkStatus1 */
/*! @{ */
#define SATA_PLS1_DEC_MASK                       (0xFFU)
#define SATA_PLS1_DEC_SHIFT                      (0U)
#define SATA_PLS1_DEC(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PLS1_DEC_SHIFT)) & SATA_PLS1_DEC_MASK)
#define SATA_PLS1_CEC_MASK                       (0xFF00U)
#define SATA_PLS1_CEC_SHIFT                      (8U)
#define SATA_PLS1_CEC(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PLS1_CEC_SHIFT)) & SATA_PLS1_CEC_MASK)
#define SATA_PLS1_PIEC_MASK                      (0xFF0000U)
#define SATA_PLS1_PIEC_SHIFT                     (16U)
#define SATA_PLS1_PIEC(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PLS1_PIEC_SHIFT)) & SATA_PLS1_PIEC_MASK)
#define SATA_PLS1_KCEC_MASK                      (0xFF000000U)
#define SATA_PLS1_KCEC_SHIFT                     (24U)
#define SATA_PLS1_KCEC(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PLS1_KCEC_SHIFT)) & SATA_PLS1_KCEC_MASK)
/*! @} */

/*! @name PCMDC - Port CmdConfig */
/*! @{ */
#define SATA_PCMDC_ETLLB_MASK                    (0x1U)
#define SATA_PCMDC_ETLLB_SHIFT                   (0U)
#define SATA_PCMDC_ETLLB(x)                      (((uint32_t)(((uint32_t)(x)) << SATA_PCMDC_ETLLB_SHIFT)) & SATA_PCMDC_ETLLB_MASK)
#define SATA_PCMDC_ETLL_MASK                     (0x2U)
#define SATA_PCMDC_ETLL_SHIFT                    (1U)
#define SATA_PCMDC_ETLL(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PCMDC_ETLL_SHIFT)) & SATA_PCMDC_ETLL_MASK)
#define SATA_PCMDC_TSVT_MASK                     (0xFFFF000U)
#define SATA_PCMDC_TSVT_SHIFT                    (12U)
#define SATA_PCMDC_TSVT(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PCMDC_TSVT_SHIFT)) & SATA_PCMDC_TSVT_MASK)
#define SATA_PCMDC_TSVI_MASK                     (0x10000000U)
#define SATA_PCMDC_TSVI_SHIFT                    (28U)
#define SATA_PCMDC_TSVI(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PCMDC_TSVI_SHIFT)) & SATA_PCMDC_TSVI_MASK)
#define SATA_PCMDC_TSVIE_MASK                    (0x20000000U)
#define SATA_PCMDC_TSVIE_SHIFT                   (29U)
#define SATA_PCMDC_TSVIE(x)                      (((uint32_t)(((uint32_t)(x)) << SATA_PCMDC_TSVIE_SHIFT)) & SATA_PCMDC_TSVIE_MASK)
/*! @} */

/*! @name PPCS - Port PhyControlStatus */
/*! @{ */
#define SATA_PPCS_PCTRLS_MASK                    (0x1FU)
#define SATA_PPCS_PCTRLS_SHIFT                   (0U)
/*! PCTRLS - Phy Control State (PCTRLS)
 *  0b00000..HP0_HR_Start
 *  0b00001..HP1_HR_Reset
 *  0b00010..HP2_HR_AwaitCOMINIT
 *  0b01100..HP2B_HR_AwaitNoCOMINIT
 *  0b00011..HP3_HR_Calibrate
 *  0b00100..HP4_HR_COMWAKE
 *  0b00101..HP5_HR_AwaitCOMWAKE
 *  0b01101..HP5B_HR_AwaitNoCOMWAKE
 *  0b00110..HP6_HR_AwaitAlign
 *  0b00111..HP7_HR_SendAlign
 *  0b01000..HP8_HR_Ready
 *  0b01001..HP9_HR_Partial
 *  0b01010..HP10_HR_Slumber
 *  0b01011..HP11_HR_AdjustSpeed
 */
#define SATA_PPCS_PCTRLS(x)                      (((uint32_t)(((uint32_t)(x)) << SATA_PPCS_PCTRLS_SHIFT)) & SATA_PPCS_PCTRLS_MASK)
#define SATA_PPCS_CCA_MASK                       (0x3E0U)
#define SATA_PPCS_CCA_SHIFT                      (5U)
#define SATA_PPCS_CCA(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_PPCS_CCA_SHIFT)) & SATA_PPCS_CCA_MASK)
#define SATA_PPCS_CCAC_MASK                      (0x400U)
#define SATA_PPCS_CCAC_SHIFT                     (10U)
#define SATA_PPCS_CCAC(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PPCS_CCAC_SHIFT)) & SATA_PPCS_CCAC_MASK)
#define SATA_PPCS_PHYD_MASK                      (0x7FFF800U)
#define SATA_PPCS_PHYD_SHIFT                     (11U)
#define SATA_PPCS_PHYD(x)                        (((uint32_t)(((uint32_t)(x)) << SATA_PPCS_PHYD_SHIFT)) & SATA_PPCS_PHYD_MASK)
#define SATA_PPCS_PHYKC_MASK                     (0x8000000U)
#define SATA_PPCS_PHYKC_SHIFT                    (27U)
#define SATA_PPCS_PHYKC(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PPCS_PHYKC_SHIFT)) & SATA_PPCS_PHYKC_MASK)
#define SATA_PPCS_PHYDE_MASK                     (0x30000000U)
#define SATA_PPCS_PHYDE_SHIFT                    (28U)
#define SATA_PPCS_PHYDE(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PPCS_PHYDE_SHIFT)) & SATA_PPCS_PHYDE_MASK)
#define SATA_PPCS_PHYCE_MASK                     (0xC0000000U)
#define SATA_PPCS_PHYCE_SHIFT                    (30U)
#define SATA_PPCS_PHYCE(x)                       (((uint32_t)(((uint32_t)(x)) << SATA_PPCS_PHYCE_SHIFT)) & SATA_PPCS_PHYCE_MASK)
/*! @} */

/*! @name AMS - AXI Master Status */
/*! @{ */
#define SATA_AMS_RAS_MASK                        (0x1U)
#define SATA_AMS_RAS_SHIFT                       (0U)
/*! RAS - Read Arbiter State (RAS)
 *  0b0..AXIRDataWS
 *  0b1..AXIRDataWReady
 */
#define SATA_AMS_RAS(x)                          (((uint32_t)(((uint32_t)(x)) << SATA_AMS_RAS_SHIFT)) & SATA_AMS_RAS_MASK)
#define SATA_AMS_WAS_MASK                        (0x2U)
#define SATA_AMS_WAS_SHIFT                       (1U)
/*! WAS - Write Arbiter State (WAS)
 *  0b0..AXIAddrWS
 *  0b1..AXIAddrWReady
 */
#define SATA_AMS_WAS(x)                          (((uint32_t)(((uint32_t)(x)) << SATA_AMS_WAS_SHIFT)) & SATA_AMS_WAS_MASK)
#define SATA_AMS_AMS0_MASK                       (0x7CU)
#define SATA_AMS_AMS0_SHIFT                      (2U)
/*! AMS0 - AXI Master State 0 (AMS0)
 *  0b00000..MRWSIdle
 *  0b00001..MRWWA
 *  0b00010..MRWWGCH
 *  0b00011..MRWWT
 *  0b00100..MRWCC
 *  0b00101..MRWSC
 *  0b00110..MRWWSF
 *  0b00111..MRWATAPI
 *  0b01000..MRWDRL
 *  0b01001..MRWWDR
 *  0b01010..MRWWDRC
 *  0b01011..MRWWDRF
 *  0b01100..MRWDWL
 *  0b01101..MRWWDW
 */
#define SATA_AMS_AMS0(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_AMS_AMS0_SHIFT)) & SATA_AMS_AMS0_MASK)
#define SATA_AMS_AMS1_MASK                       (0xF80U)
#define SATA_AMS_AMS1_SHIFT                      (7U)
/*! AMS1 - AXI Master State 1 (AMS1)
 *  0b00000..MRWSIdle
 *  0b00001..MRWWA
 *  0b00010..MRWWGCH
 *  0b00011..MRWWT
 *  0b00100..MRWCC
 *  0b00101..MRWSC
 *  0b00110..MRWWSF
 *  0b00111..MRWATAPI
 *  0b01000..MRWDRL
 *  0b01001..MRWWDR
 *  0b01010..MRWWDRC
 *  0b01011..MRWWDRF
 *  0b01100..MRWDWL
 *  0b01101..MRWWDW
 */
#define SATA_AMS_AMS1(x)                         (((uint32_t)(((uint32_t)(x)) << SATA_AMS_AMS1_SHIFT)) & SATA_AMS_AMS1_MASK)
/*! @} */

/*! @name TCR - Timer Control */
/*! @{ */
#define SATA_TCR_TPS_MASK                        (0x1FFFU)
#define SATA_TCR_TPS_SHIFT                       (0U)
#define SATA_TCR_TPS(x)                          (((uint32_t)(((uint32_t)(x)) << SATA_TCR_TPS_SHIFT)) & SATA_TCR_TPS_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SATA_Register_Masks */


/* SATA - Peripheral instance base addresses */
/** Peripheral HSIO__SATA base address */
#define HSIO__SATA_BASE                          (0x5F150000u)
/** Peripheral HSIO__SATA base pointer */
#define HSIO__SATA                               ((SATA_Type *)HSIO__SATA_BASE)
/** Array initializer of SATA peripheral base addresses */
#define SATA_BASE_ADDRS                          { HSIO__SATA_BASE }
/** Array initializer of SATA peripheral base pointers */
#define SATA_BASE_PTRS                           { HSIO__SATA }

/*!
 * @}
 */ /* end of group SATA_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SCU_LPCG_LPI2C Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCU_LPCG_LPI2C_Peripheral_Access_Layer SCU_LPCG_LPI2C Peripheral Access Layer
 * @{
 */

/** SCU_LPCG_LPI2C - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPI2C_0;                      /**< na, offset: 0x0 */
} SCU_LPCG_LPI2C_Type;

/* ----------------------------------------------------------------------------
   -- SCU_LPCG_LPI2C Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCU_LPCG_LPI2C_Register_Masks SCU_LPCG_LPI2C Register Masks
 * @{
 */

/*! @name LPCG_LPI2C_0 - na */
/*! @{ */
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK (0x4U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT (2U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT)) & SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK (0x10U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT (4U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT)) & SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK (0x20U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT (5U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT)) & SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK (0x40U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT (6U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT)) & SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK (0x80U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT (7U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT)) & SCU_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK (0xFFFFFF00U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT (8U)
#define SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT)) & SCU_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SCU_LPCG_LPI2C_Register_Masks */


/* SCU_LPCG_LPI2C - Peripheral instance base addresses */
/** Peripheral SCU__LPCG_LPI2C base address */
#define SCU__LPCG_LPI2C_BASE                     (0x33630000u)
/** Peripheral SCU__LPCG_LPI2C base pointer */
#define SCU__LPCG_LPI2C                          ((SCU_LPCG_LPI2C_Type *)SCU__LPCG_LPI2C_BASE)
/** Array initializer of SCU_LPCG_LPI2C peripheral base addresses */
#define SCU_LPCG_LPI2C_BASE_ADDRS                { SCU__LPCG_LPI2C_BASE }
/** Array initializer of SCU_LPCG_LPI2C peripheral base pointers */
#define SCU_LPCG_LPI2C_BASE_PTRS                 { SCU__LPCG_LPI2C }

/*!
 * @}
 */ /* end of group SCU_LPCG_LPI2C_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SCU_LPCG_LPIT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCU_LPCG_LPIT_Peripheral_Access_Layer SCU_LPCG_LPIT Peripheral Access Layer
 * @{
 */

/** SCU_LPCG_LPIT - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPIT_0;                       /**< na, offset: 0x0 */
} SCU_LPCG_LPIT_Type;

/* ----------------------------------------------------------------------------
   -- SCU_LPCG_LPIT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCU_LPCG_LPIT_Register_Masks SCU_LPCG_LPIT Register Masks
 * @{
 */

/*! @name LPCG_LPIT_0 - na */
/*! @{ */
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK (0x1U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT (0U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT)) & SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK (0x2U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT (1U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT)) & SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK (0x4U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT (2U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT)) & SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK (0x8U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT (3U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT)) & SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK (0x10U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT (4U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT)) & SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK (0x20U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT (5U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT)) & SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK (0x40U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT (6U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT)) & SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK (0x80U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT (7U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT)) & SCU_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK (0xFFFFFF00U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT (8U)
#define SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT)) & SCU_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SCU_LPCG_LPIT_Register_Masks */


/* SCU_LPCG_LPIT - Peripheral instance base addresses */
/** Peripheral SCU__LPCG_LPIT base address */
#define SCU__LPCG_LPIT_BASE                      (0x33610000u)
/** Peripheral SCU__LPCG_LPIT base pointer */
#define SCU__LPCG_LPIT                           ((SCU_LPCG_LPIT_Type *)SCU__LPCG_LPIT_BASE)
/** Array initializer of SCU_LPCG_LPIT peripheral base addresses */
#define SCU_LPCG_LPIT_BASE_ADDRS                 { SCU__LPCG_LPIT_BASE }
/** Array initializer of SCU_LPCG_LPIT peripheral base pointers */
#define SCU_LPCG_LPIT_BASE_PTRS                  { SCU__LPCG_LPIT }

/*!
 * @}
 */ /* end of group SCU_LPCG_LPIT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SCU_LPCG_LPUART Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCU_LPCG_LPUART_Peripheral_Access_Layer SCU_LPCG_LPUART Peripheral Access Layer
 * @{
 */

/** SCU_LPCG_LPUART - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_LPUART_0;                     /**< na, offset: 0x0 */
} SCU_LPCG_LPUART_Type;

/* ----------------------------------------------------------------------------
   -- SCU_LPCG_LPUART Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCU_LPCG_LPUART_Register_Masks SCU_LPCG_LPUART Register Masks
 * @{
 */

/*! @name LPCG_LPUART_0 - na */
/*! @{ */
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK (0x4U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT (2U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT)) & SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK (0x8U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT (3U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT)) & SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK (0x10U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT (4U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT)) & SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK (0x20U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT (5U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT)) & SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK (0x40U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT (6U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT)) & SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK (0x80U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT (7U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT)) & SCU_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK (0xFFFFFF00U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT (8U)
#define SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT)) & SCU_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SCU_LPCG_LPUART_Register_Masks */


/* SCU_LPCG_LPUART - Peripheral instance base addresses */
/** Peripheral SCU__LPCG_LPUART base address */
#define SCU__LPCG_LPUART_BASE                    (0x33620000u)
/** Peripheral SCU__LPCG_LPUART base pointer */
#define SCU__LPCG_LPUART                         ((SCU_LPCG_LPUART_Type *)SCU__LPCG_LPUART_BASE)
/** Array initializer of SCU_LPCG_LPUART peripheral base addresses */
#define SCU_LPCG_LPUART_BASE_ADDRS               { SCU__LPCG_LPUART_BASE }
/** Array initializer of SCU_LPCG_LPUART peripheral base pointers */
#define SCU_LPCG_LPUART_BASE_PTRS                { SCU__LPCG_LPUART }

/*!
 * @}
 */ /* end of group SCU_LPCG_LPUART_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SCU_LPCG_MMCAU_HCLK Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCU_LPCG_MMCAU_HCLK_Peripheral_Access_Layer SCU_LPCG_MMCAU_HCLK Peripheral Access Layer
 * @{
 */

/** SCU_LPCG_MMCAU_HCLK - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MMCAU_HCLK_0;                 /**< na, offset: 0x0 */
} SCU_LPCG_MMCAU_HCLK_Type;

/* ----------------------------------------------------------------------------
   -- SCU_LPCG_MMCAU_HCLK Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCU_LPCG_MMCAU_HCLK_Register_Masks SCU_LPCG_MMCAU_HCLK Register Masks
 * @{
 */

/*! @name LPCG_MMCAU_HCLK_0 - na */
/*! @{ */
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK (0x1U)
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT (0U)
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT)) & SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK)
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK (0x2U)
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT (1U)
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT)) & SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK)
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK (0x4U)
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT (2U)
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT)) & SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK)
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK (0x8U)
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT (3U)
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT)) & SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK)
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT (4U)
#define SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT)) & SCU_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SCU_LPCG_MMCAU_HCLK_Register_Masks */


/* SCU_LPCG_MMCAU_HCLK - Peripheral instance base addresses */
/** Peripheral SCU__LPCG_MMCAU_HCLK base address */
#define SCU__LPCG_MMCAU_HCLK_BASE                (0x335F0000u)
/** Peripheral SCU__LPCG_MMCAU_HCLK base pointer */
#define SCU__LPCG_MMCAU_HCLK                     ((SCU_LPCG_MMCAU_HCLK_Type *)SCU__LPCG_MMCAU_HCLK_BASE)
/** Array initializer of SCU_LPCG_MMCAU_HCLK peripheral base addresses */
#define SCU_LPCG_MMCAU_HCLK_BASE_ADDRS           { SCU__LPCG_MMCAU_HCLK_BASE }
/** Array initializer of SCU_LPCG_MMCAU_HCLK peripheral base pointers */
#define SCU_LPCG_MMCAU_HCLK_BASE_PTRS            { SCU__LPCG_MMCAU_HCLK }

/*!
 * @}
 */ /* end of group SCU_LPCG_MMCAU_HCLK_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SCU_LPCG_TCMC_HCLK Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCU_LPCG_TCMC_HCLK_Peripheral_Access_Layer SCU_LPCG_TCMC_HCLK Peripheral Access Layer
 * @{
 */

/** SCU_LPCG_TCMC_HCLK - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_TCMC_HCLK_0;                  /**< na, offset: 0x0 */
} SCU_LPCG_TCMC_HCLK_Type;

/* ----------------------------------------------------------------------------
   -- SCU_LPCG_TCMC_HCLK Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCU_LPCG_TCMC_HCLK_Register_Masks SCU_LPCG_TCMC_HCLK Register Masks
 * @{
 */

/*! @name LPCG_TCMC_HCLK_0 - na */
/*! @{ */
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK (0x1U)
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT (0U)
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT)) & SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK)
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK (0x2U)
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT (1U)
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT)) & SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK)
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK (0x4U)
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT (2U)
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT)) & SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK)
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK (0x8U)
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT (3U)
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT)) & SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK)
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT (4U)
#define SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT)) & SCU_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SCU_LPCG_TCMC_HCLK_Register_Masks */


/* SCU_LPCG_TCMC_HCLK - Peripheral instance base addresses */
/** Peripheral SCU__LPCG_TCMC_HCLK base address */
#define SCU__LPCG_TCMC_HCLK_BASE                 (0x335E0000u)
/** Peripheral SCU__LPCG_TCMC_HCLK base pointer */
#define SCU__LPCG_TCMC_HCLK                      ((SCU_LPCG_TCMC_HCLK_Type *)SCU__LPCG_TCMC_HCLK_BASE)
/** Array initializer of SCU_LPCG_TCMC_HCLK peripheral base addresses */
#define SCU_LPCG_TCMC_HCLK_BASE_ADDRS            { SCU__LPCG_TCMC_HCLK_BASE }
/** Array initializer of SCU_LPCG_TCMC_HCLK peripheral base pointers */
#define SCU_LPCG_TCMC_HCLK_BASE_PTRS             { SCU__LPCG_TCMC_HCLK }

/*!
 * @}
 */ /* end of group SCU_LPCG_TCMC_HCLK_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SCU_LPCG_TPM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCU_LPCG_TPM_Peripheral_Access_Layer SCU_LPCG_TPM Peripheral Access Layer
 * @{
 */

/** SCU_LPCG_TPM - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_TPM_0;                        /**< na, offset: 0x0 */
} SCU_LPCG_TPM_Type;

/* ----------------------------------------------------------------------------
   -- SCU_LPCG_TPM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCU_LPCG_TPM_Register_Masks SCU_LPCG_TPM Register Masks
 * @{
 */

/*! @name LPCG_TPM_0 - na */
/*! @{ */
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK (0x1U)
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT (0U)
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT)) & SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK)
#define SCU_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK (0x2U)
#define SCU_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT (1U)
#define SCU_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT)) & SCU_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK)
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK (0x4U)
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT (2U)
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT)) & SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK)
#define SCU_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK (0x8U)
#define SCU_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT (3U)
#define SCU_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT)) & SCU_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK)
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK (0x10U)
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT (4U)
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT)) & SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK)
#define SCU_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK (0x20U)
#define SCU_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT (5U)
#define SCU_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT)) & SCU_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK)
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK (0x40U)
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT (6U)
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT)) & SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK)
#define SCU_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK (0x80U)
#define SCU_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT (7U)
#define SCU_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT)) & SCU_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK)
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK (0xFFFFFF00U)
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT (8U)
#define SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT)) & SCU_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SCU_LPCG_TPM_Register_Masks */


/* SCU_LPCG_TPM - Peripheral instance base addresses */
/** Peripheral SCU__LPCG_TPM base address */
#define SCU__LPCG_TPM_BASE                       (0x33600000u)
/** Peripheral SCU__LPCG_TPM base pointer */
#define SCU__LPCG_TPM                            ((SCU_LPCG_TPM_Type *)SCU__LPCG_TPM_BASE)
/** Array initializer of SCU_LPCG_TPM peripheral base addresses */
#define SCU_LPCG_TPM_BASE_ADDRS                  { SCU__LPCG_TPM_BASE }
/** Array initializer of SCU_LPCG_TPM peripheral base pointers */
#define SCU_LPCG_TPM_BASE_PTRS                   { SCU__LPCG_TPM }

/*!
 * @}
 */ /* end of group SCU_LPCG_TPM_Peripheral_Access_Layer */
 

/* ----------------------------------------------------------------------------
   -- SEMA42 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer
 * @{
 */

/** SEMA42 - Register Layout Typedef */
typedef struct {
  __IO uint8_t GATE3;                              /**< Gate Register, offset: 0x0 */
  __IO uint8_t GATE2;                              /**< Gate Register, offset: 0x1 */
  __IO uint8_t GATE1;                              /**< Gate Register, offset: 0x2 */
  __IO uint8_t GATE0;                              /**< Gate Register, offset: 0x3 */
  __IO uint8_t GATE7;                              /**< Gate Register, offset: 0x4 */
  __IO uint8_t GATE6;                              /**< Gate Register, offset: 0x5 */
  __IO uint8_t GATE5;                              /**< Gate Register, offset: 0x6 */
  __IO uint8_t GATE4;                              /**< Gate Register, offset: 0x7 */
  __IO uint8_t GATE11;                             /**< Gate Register, offset: 0x8 */
  __IO uint8_t GATE10;                             /**< Gate Register, offset: 0x9 */
  __IO uint8_t GATE9;                              /**< Gate Register, offset: 0xA */
  __IO uint8_t GATE8;                              /**< Gate Register, offset: 0xB */
  __IO uint8_t GATE15;                             /**< Gate Register, offset: 0xC */
  __IO uint8_t GATE14;                             /**< Gate Register, offset: 0xD */
  __IO uint8_t GATE13;                             /**< Gate Register, offset: 0xE */
  __IO uint8_t GATE12;                             /**< Gate Register, offset: 0xF */
       uint8_t RESERVED_0[50];
  union {                                          /* offset: 0x42 */
    __I  uint16_t RSTGT_R;                           /**< Reset Gate Read, offset: 0x42 */
    __O  uint16_t RSTGT_W;                           /**< Reset Gate Write, offset: 0x42 */
  };
} SEMA42_Type;

/* ----------------------------------------------------------------------------
   -- SEMA42 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks
 * @{
 */

/*! @name GATE3 - Gate Register */
/*! @{ */
#define SEMA42_GATE3_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE3_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE3_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK)
/*! @} */

/*! @name GATE2 - Gate Register */
/*! @{ */
#define SEMA42_GATE2_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE2_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE2_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK)
/*! @} */

/*! @name GATE1 - Gate Register */
/*! @{ */
#define SEMA42_GATE1_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE1_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE1_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK)
/*! @} */

/*! @name GATE0 - Gate Register */
/*! @{ */
#define SEMA42_GATE0_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE0_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE0_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK)
/*! @} */

/*! @name GATE7 - Gate Register */
/*! @{ */
#define SEMA42_GATE7_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE7_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE7_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK)
/*! @} */

/*! @name GATE6 - Gate Register */
/*! @{ */
#define SEMA42_GATE6_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE6_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE6_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK)
/*! @} */

/*! @name GATE5 - Gate Register */
/*! @{ */
#define SEMA42_GATE5_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE5_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE5_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK)
/*! @} */

/*! @name GATE4 - Gate Register */
/*! @{ */
#define SEMA42_GATE4_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE4_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE4_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK)
/*! @} */

/*! @name GATE11 - Gate Register */
/*! @{ */
#define SEMA42_GATE11_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE11_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE11_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK)
/*! @} */

/*! @name GATE10 - Gate Register */
/*! @{ */
#define SEMA42_GATE10_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE10_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE10_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK)
/*! @} */

/*! @name GATE9 - Gate Register */
/*! @{ */
#define SEMA42_GATE9_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE9_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE9_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK)
/*! @} */

/*! @name GATE8 - Gate Register */
/*! @{ */
#define SEMA42_GATE8_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE8_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE8_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK)
/*! @} */

/*! @name GATE15 - Gate Register */
/*! @{ */
#define SEMA42_GATE15_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE15_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE15_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK)
/*! @} */

/*! @name GATE14 - Gate Register */
/*! @{ */
#define SEMA42_GATE14_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE14_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE14_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK)
/*! @} */

/*! @name GATE13 - Gate Register */
/*! @{ */
#define SEMA42_GATE13_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE13_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE13_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK)
/*! @} */

/*! @name GATE12 - Gate Register */
/*! @{ */
#define SEMA42_GATE12_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE12_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE12_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK)
/*! @} */

/*! @name RSTGT_R - Reset Gate Read */
/*! @{ */
#define SEMA42_RSTGT_R_RSTGTN_MASK               (0xFFU)
#define SEMA42_RSTGT_R_RSTGTN_SHIFT              (0U)
#define SEMA42_RSTGT_R_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK)
#define SEMA42_RSTGT_R_RSTGMS_MASK               (0xF00U)
#define SEMA42_RSTGT_R_RSTGMS_SHIFT              (8U)
#define SEMA42_RSTGT_R_RSTGMS(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK)
#define SEMA42_RSTGT_R_RSTGSM_MASK               (0x3000U)
#define SEMA42_RSTGT_R_RSTGSM_SHIFT              (12U)
/*! RSTGSM - Reset Gate Finite State Machine
 *  0b00..Idle, waiting for the first data pattern write.
 *  0b01..Waiting for the second data pattern write
 *  0b10..After the reset is performed, this machine returns to the idle (waiting for the first data pattern write) state. The "01" state persists for only a single clock cycle. Software cannot observe this state.
 *  0b11..This state encoding is never used and is therefore reserved.
 */
#define SEMA42_RSTGT_R_RSTGSM(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK)
#define SEMA42_RSTGT_R_ROZ_MASK                  (0xC000U)
#define SEMA42_RSTGT_R_ROZ_SHIFT                 (14U)
#define SEMA42_RSTGT_R_ROZ(x)                    (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_ROZ_SHIFT)) & SEMA42_RSTGT_R_ROZ_MASK)
/*! @} */

/*! @name RSTGT_W - Reset Gate Write */
/*! @{ */
#define SEMA42_RSTGT_W_RSTGTN_MASK               (0xFFU)
#define SEMA42_RSTGT_W_RSTGTN_SHIFT              (0U)
#define SEMA42_RSTGT_W_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK)
#define SEMA42_RSTGT_W_RSTGDP_MASK               (0xFF00U)
#define SEMA42_RSTGT_W_RSTGDP_SHIFT              (8U)
#define SEMA42_RSTGT_W_RSTGDP(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SEMA42_Register_Masks */


/* SEMA42 - Peripheral instance base addresses */
/** Peripheral CM4_0__SEMA42 base address */
#define CM4_0__SEMA42_BASE                       (0x371B0000u)
/** Peripheral CM4_0__SEMA42 base pointer */
#define CM4_0__SEMA42                            ((SEMA42_Type *)CM4_0__SEMA42_BASE)
/** Peripheral CM4_1__SEMA42 base address */
#define CM4_1__SEMA42_BASE                       (0x411B0000u)
/** Peripheral CM4_1__SEMA42 base pointer */
#define CM4_1__SEMA42                            ((SEMA42_Type *)CM4_1__SEMA42_BASE)
/** Peripheral SCU__SEMA42 base address */
#define SCU__SEMA42_BASE                         (0x331B0000u)
/** Peripheral SCU__SEMA42 base pointer */
#define SCU__SEMA42                              ((SEMA42_Type *)SCU__SEMA42_BASE)
/** Array initializer of SEMA42 peripheral base addresses */
#define SEMA42_BASE_ADDRS                        { CM4_0__SEMA42_BASE, CM4_1__SEMA42_BASE, SCU__SEMA42_BASE }
/** Array initializer of SEMA42 peripheral base pointers */
#define SEMA42_BASE_PTRS                         { CM4_0__SEMA42, CM4_1__SEMA42, SCU__SEMA42 }

/*!
 * @}
 */ /* end of group SEMA42_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SPDIF Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
 * @{
 */

/** SPDIF - Register Layout Typedef */
typedef struct {
  __IO uint32_t SCR;                               /**< SPDIF Configuration Register, offset: 0x0 */
  __IO uint32_t SRCD;                              /**< CDText Control Register, offset: 0x4 */
  __IO uint32_t SRPC;                              /**< PhaseConfig Register, offset: 0x8 */
  __IO uint32_t SIE;                               /**< InterruptEn Register, offset: 0xC */
  union {                                          /* offset: 0x10 */
    __O  uint32_t SIC;                               /**< InterruptClear Register, offset: 0x10 */
    __I  uint32_t SIS;                               /**< InterruptStat Register, offset: 0x10 */
  };
  __I  uint32_t SRL;                               /**< SPDIFRxLeft Register, offset: 0x14 */
  __I  uint32_t SRR;                               /**< SPDIFRxRight Register, offset: 0x18 */
  __I  uint32_t SRCSH;                             /**< SPDIFRxCChannel_h Register, offset: 0x1C */
  __I  uint32_t SRCSL;                             /**< SPDIFRxCChannel_l Register, offset: 0x20 */
  __I  uint32_t SRU;                               /**< UchannelRx Register, offset: 0x24 */
  __I  uint32_t SRQ;                               /**< QchannelRx Register, offset: 0x28 */
  __O  uint32_t STL;                               /**< SPDIFTxLeft Register, offset: 0x2C */
  __O  uint32_t STR;                               /**< SPDIFTxRight Register, offset: 0x30 */
  __IO uint32_t STCSCH;                            /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */
  __IO uint32_t STCSCL;                            /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */
       uint8_t RESERVED_0[8];
  __I  uint32_t SRFM;                              /**< FreqMeas Register, offset: 0x44 */
       uint8_t RESERVED_1[8];
  __IO uint32_t STC;                               /**< SPDIFTxClk Register, offset: 0x50 */
} SPDIF_Type;

/* ----------------------------------------------------------------------------
   -- SPDIF Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SPDIF_Register_Masks SPDIF Register Masks
 * @{
 */

/*! @name SCR - SPDIF Configuration Register */
/*! @{ */
#define SPDIF_SCR_USRC_SEL_MASK                  (0x3U)
#define SPDIF_SCR_USRC_SEL_SHIFT                 (0U)
/*! USrc_Sel - USrc_Sel
 *  0b00..No embedded U channel
 *  0b01..U channel from SPDIF receive block (CD mode)
 *  0b10..Reserved
 *  0b11..U channel from on chip transmitter
 */
#define SPDIF_SCR_USRC_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
#define SPDIF_SCR_TXSEL_MASK                     (0x1CU)
#define SPDIF_SCR_TXSEL_SHIFT                    (2U)
/*! TxSel - TxSel
 *  0b000..Off and output 0
 *  0b001..Feed-through SPDIFIN
 *  0b101..Tx Normal operation
 */
#define SPDIF_SCR_TXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
#define SPDIF_SCR_VALCTRL_MASK                   (0x20U)
#define SPDIF_SCR_VALCTRL_SHIFT                  (5U)
/*! ValCtrl - ValCtrl
 *  0b0..Outgoing Validity always set
 *  0b1..Outgoing Validity always clear
 */
#define SPDIF_SCR_VALCTRL(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
#define SPDIF_SCR_DMA_TX_EN_MASK                 (0x100U)
#define SPDIF_SCR_DMA_TX_EN_SHIFT                (8U)
#define SPDIF_SCR_DMA_TX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
#define SPDIF_SCR_DMA_RX_EN_MASK                 (0x200U)
#define SPDIF_SCR_DMA_RX_EN_SHIFT                (9U)
#define SPDIF_SCR_DMA_RX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
#define SPDIF_SCR_TXFIFO_CTRL_MASK               (0xC00U)
#define SPDIF_SCR_TXFIFO_CTRL_SHIFT              (10U)
/*! TxFIFO_Ctrl - TxFIFO_Ctrl
 *  0b00..Send out digital zero on SPDIF Tx
 *  0b01..Tx Normal operation
 *  0b10..Reset to 1 sample remaining
 *  0b11..Reserved
 */
#define SPDIF_SCR_TXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
#define SPDIF_SCR_SOFT_RESET_MASK                (0x1000U)
#define SPDIF_SCR_SOFT_RESET_SHIFT               (12U)
#define SPDIF_SCR_SOFT_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
#define SPDIF_SCR_LOW_POWER_MASK                 (0x2000U)
#define SPDIF_SCR_LOW_POWER_SHIFT                (13U)
#define SPDIF_SCR_LOW_POWER(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK           (0x18000U)
#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT          (15U)
/*! TxFIFOEmpty_Sel - TxFIFOEmpty_Sel
 *  0b00..Empty interrupt if 0 sample in Tx left and right FIFOs
 *  0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs
 *  0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs
 *  0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs
 */
#define SPDIF_SCR_TXFIFOEMPTY_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
#define SPDIF_SCR_TXAUTOSYNC_MASK                (0x20000U)
#define SPDIF_SCR_TXAUTOSYNC_SHIFT               (17U)
/*! TxAutoSync - TxAutoSync
 *  0b0..Tx FIFO auto sync off
 *  0b1..Tx FIFO auto sync on
 */
#define SPDIF_SCR_TXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
#define SPDIF_SCR_RXAUTOSYNC_MASK                (0x40000U)
#define SPDIF_SCR_RXAUTOSYNC_SHIFT               (18U)
/*! RxAutoSync - RxAutoSync
 *  0b0..Rx FIFO auto sync off
 *  0b1..RxFIFO auto sync on
 */
#define SPDIF_SCR_RXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
#define SPDIF_SCR_RXFIFOFULL_SEL_MASK            (0x180000U)
#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT           (19U)
/*! RxFIFOFull_Sel - RxFIFOFull_Sel
 *  0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs
 *  0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs
 *  0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs
 *  0b11..Full interrupt if at least 16 sample in Rx left and right FIFO
 */
#define SPDIF_SCR_RXFIFOFULL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
#define SPDIF_SCR_RXFIFO_RST_MASK                (0x200000U)
#define SPDIF_SCR_RXFIFO_RST_SHIFT               (21U)
/*! RxFIFO_Rst - RxFIFO_Rst
 *  0b0..Normal operation
 *  0b1..Reset register to 1 sample remaining
 */
#define SPDIF_SCR_RXFIFO_RST(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
#define SPDIF_SCR_RXFIFO_OFF_ON_MASK             (0x400000U)
#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT            (22U)
/*! RxFIFO_Off_On - RxFIFO_Off_On
 *  0b0..SPDIF Rx FIFO is on
 *  0b1..SPDIF Rx FIFO is off. Does not accept data from interface
 */
#define SPDIF_SCR_RXFIFO_OFF_ON(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
#define SPDIF_SCR_RXFIFO_CTRL_MASK               (0x800000U)
#define SPDIF_SCR_RXFIFO_CTRL_SHIFT              (23U)
/*! RxFIFO_Ctrl - RxFIFO_Ctrl
 *  0b0..Normal operation
 *  0b1..Always read zero from Rx data register
 */
#define SPDIF_SCR_RXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
/*! @} */

/*! @name SRCD - CDText Control Register */
/*! @{ */
#define SPDIF_SRCD_USYNCMODE_MASK                (0x2U)
#define SPDIF_SRCD_USYNCMODE_SHIFT               (1U)
/*! USyncMode - USyncMode
 *  0b0..Non-CD data
 *  0b1..CD user channel subcode
 */
#define SPDIF_SRCD_USYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
/*! @} */

/*! @name SRPC - PhaseConfig Register */
/*! @{ */
#define SPDIF_SRPC_GAINSEL_MASK                  (0x38U)
#define SPDIF_SRPC_GAINSEL_SHIFT                 (3U)
/*! GainSel - GainSel
 *  0b000..24*(2**10)
 *  0b001..16*(2**10)
 *  0b010..12*(2**10)
 *  0b011..8*(2**10)
 *  0b100..6*(2**10)
 *  0b101..4*(2**10)
 *  0b110..3*(2**10)
 */
#define SPDIF_SRPC_GAINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
#define SPDIF_SRPC_LOCK_MASK                     (0x40U)
#define SPDIF_SRPC_LOCK_SHIFT                    (6U)
#define SPDIF_SRPC_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
#define SPDIF_SRPC_CLKSRC_SEL_MASK               (0x780U)
#define SPDIF_SRPC_CLKSRC_SEL_SHIFT              (7U)
/*! ClkSrc_Sel - ClkSrc_Sel
 *  0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)
 *  0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)
 *  0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK
 *  0b0101..REF_CLK_32K (XTALOSC)
 *  0b0110..tx_clk (SPDIF0_CLK_ROOT)
 *  0b1000..SPDIF_EXT_CLK
 */
#define SPDIF_SRPC_CLKSRC_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
/*! @} */

/*! @name SIE - InterruptEn Register */
/*! @{ */
#define SPDIF_SIE_RXFIFOFUL_MASK                 (0x1U)
#define SPDIF_SIE_RXFIFOFUL_SHIFT                (0U)
#define SPDIF_SIE_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
#define SPDIF_SIE_TXEM_MASK                      (0x2U)
#define SPDIF_SIE_TXEM_SHIFT                     (1U)
#define SPDIF_SIE_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
#define SPDIF_SIE_LOCKLOSS_MASK                  (0x4U)
#define SPDIF_SIE_LOCKLOSS_SHIFT                 (2U)
#define SPDIF_SIE_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
#define SPDIF_SIE_RXFIFORESYN_MASK               (0x8U)
#define SPDIF_SIE_RXFIFORESYN_SHIFT              (3U)
#define SPDIF_SIE_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
#define SPDIF_SIE_RXFIFOUNOV_MASK                (0x10U)
#define SPDIF_SIE_RXFIFOUNOV_SHIFT               (4U)
#define SPDIF_SIE_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
#define SPDIF_SIE_UQERR_MASK                     (0x20U)
#define SPDIF_SIE_UQERR_SHIFT                    (5U)
#define SPDIF_SIE_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
#define SPDIF_SIE_UQSYNC_MASK                    (0x40U)
#define SPDIF_SIE_UQSYNC_SHIFT                   (6U)
#define SPDIF_SIE_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
#define SPDIF_SIE_QRXOV_MASK                     (0x80U)
#define SPDIF_SIE_QRXOV_SHIFT                    (7U)
#define SPDIF_SIE_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
#define SPDIF_SIE_QRXFUL_MASK                    (0x100U)
#define SPDIF_SIE_QRXFUL_SHIFT                   (8U)
#define SPDIF_SIE_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
#define SPDIF_SIE_URXOV_MASK                     (0x200U)
#define SPDIF_SIE_URXOV_SHIFT                    (9U)
#define SPDIF_SIE_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
#define SPDIF_SIE_URXFUL_MASK                    (0x400U)
#define SPDIF_SIE_URXFUL_SHIFT                   (10U)
#define SPDIF_SIE_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
#define SPDIF_SIE_BITERR_MASK                    (0x4000U)
#define SPDIF_SIE_BITERR_SHIFT                   (14U)
#define SPDIF_SIE_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
#define SPDIF_SIE_SYMERR_MASK                    (0x8000U)
#define SPDIF_SIE_SYMERR_SHIFT                   (15U)
#define SPDIF_SIE_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
#define SPDIF_SIE_VALNOGOOD_MASK                 (0x10000U)
#define SPDIF_SIE_VALNOGOOD_SHIFT                (16U)
#define SPDIF_SIE_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
#define SPDIF_SIE_CNEW_MASK                      (0x20000U)
#define SPDIF_SIE_CNEW_SHIFT                     (17U)
#define SPDIF_SIE_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
#define SPDIF_SIE_TXRESYN_MASK                   (0x40000U)
#define SPDIF_SIE_TXRESYN_SHIFT                  (18U)
#define SPDIF_SIE_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
#define SPDIF_SIE_TXUNOV_MASK                    (0x80000U)
#define SPDIF_SIE_TXUNOV_SHIFT                   (19U)
#define SPDIF_SIE_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
#define SPDIF_SIE_LOCK_MASK                      (0x100000U)
#define SPDIF_SIE_LOCK_SHIFT                     (20U)
#define SPDIF_SIE_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
/*! @} */

/*! @name SIC - InterruptClear Register */
/*! @{ */
#define SPDIF_SIC_LOCKLOSS_MASK                  (0x4U)
#define SPDIF_SIC_LOCKLOSS_SHIFT                 (2U)
#define SPDIF_SIC_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
#define SPDIF_SIC_RXFIFORESYN_MASK               (0x8U)
#define SPDIF_SIC_RXFIFORESYN_SHIFT              (3U)
#define SPDIF_SIC_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
#define SPDIF_SIC_RXFIFOUNOV_MASK                (0x10U)
#define SPDIF_SIC_RXFIFOUNOV_SHIFT               (4U)
#define SPDIF_SIC_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
#define SPDIF_SIC_UQERR_MASK                     (0x20U)
#define SPDIF_SIC_UQERR_SHIFT                    (5U)
#define SPDIF_SIC_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
#define SPDIF_SIC_UQSYNC_MASK                    (0x40U)
#define SPDIF_SIC_UQSYNC_SHIFT                   (6U)
#define SPDIF_SIC_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
#define SPDIF_SIC_QRXOV_MASK                     (0x80U)
#define SPDIF_SIC_QRXOV_SHIFT                    (7U)
#define SPDIF_SIC_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
#define SPDIF_SIC_URXOV_MASK                     (0x200U)
#define SPDIF_SIC_URXOV_SHIFT                    (9U)
#define SPDIF_SIC_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
#define SPDIF_SIC_BITERR_MASK                    (0x4000U)
#define SPDIF_SIC_BITERR_SHIFT                   (14U)
#define SPDIF_SIC_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
#define SPDIF_SIC_SYMERR_MASK                    (0x8000U)
#define SPDIF_SIC_SYMERR_SHIFT                   (15U)
#define SPDIF_SIC_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
#define SPDIF_SIC_VALNOGOOD_MASK                 (0x10000U)
#define SPDIF_SIC_VALNOGOOD_SHIFT                (16U)
#define SPDIF_SIC_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
#define SPDIF_SIC_CNEW_MASK                      (0x20000U)
#define SPDIF_SIC_CNEW_SHIFT                     (17U)
#define SPDIF_SIC_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
#define SPDIF_SIC_TXRESYN_MASK                   (0x40000U)
#define SPDIF_SIC_TXRESYN_SHIFT                  (18U)
#define SPDIF_SIC_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
#define SPDIF_SIC_TXUNOV_MASK                    (0x80000U)
#define SPDIF_SIC_TXUNOV_SHIFT                   (19U)
#define SPDIF_SIC_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
#define SPDIF_SIC_LOCK_MASK                      (0x100000U)
#define SPDIF_SIC_LOCK_SHIFT                     (20U)
#define SPDIF_SIC_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
/*! @} */

/*! @name SIS - InterruptStat Register */
/*! @{ */
#define SPDIF_SIS_RXFIFOFUL_MASK                 (0x1U)
#define SPDIF_SIS_RXFIFOFUL_SHIFT                (0U)
#define SPDIF_SIS_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
#define SPDIF_SIS_TXEM_MASK                      (0x2U)
#define SPDIF_SIS_TXEM_SHIFT                     (1U)
#define SPDIF_SIS_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
#define SPDIF_SIS_LOCKLOSS_MASK                  (0x4U)
#define SPDIF_SIS_LOCKLOSS_SHIFT                 (2U)
#define SPDIF_SIS_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
#define SPDIF_SIS_RXFIFORESYN_MASK               (0x8U)
#define SPDIF_SIS_RXFIFORESYN_SHIFT              (3U)
#define SPDIF_SIS_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
#define SPDIF_SIS_RXFIFOUNOV_MASK                (0x10U)
#define SPDIF_SIS_RXFIFOUNOV_SHIFT               (4U)
#define SPDIF_SIS_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
#define SPDIF_SIS_UQERR_MASK                     (0x20U)
#define SPDIF_SIS_UQERR_SHIFT                    (5U)
#define SPDIF_SIS_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
#define SPDIF_SIS_UQSYNC_MASK                    (0x40U)
#define SPDIF_SIS_UQSYNC_SHIFT                   (6U)
#define SPDIF_SIS_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
#define SPDIF_SIS_QRXOV_MASK                     (0x80U)
#define SPDIF_SIS_QRXOV_SHIFT                    (7U)
#define SPDIF_SIS_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
#define SPDIF_SIS_QRXFUL_MASK                    (0x100U)
#define SPDIF_SIS_QRXFUL_SHIFT                   (8U)
#define SPDIF_SIS_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
#define SPDIF_SIS_URXOV_MASK                     (0x200U)
#define SPDIF_SIS_URXOV_SHIFT                    (9U)
#define SPDIF_SIS_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
#define SPDIF_SIS_URXFUL_MASK                    (0x400U)
#define SPDIF_SIS_URXFUL_SHIFT                   (10U)
#define SPDIF_SIS_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
#define SPDIF_SIS_BITERR_MASK                    (0x4000U)
#define SPDIF_SIS_BITERR_SHIFT                   (14U)
#define SPDIF_SIS_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
#define SPDIF_SIS_SYMERR_MASK                    (0x8000U)
#define SPDIF_SIS_SYMERR_SHIFT                   (15U)
#define SPDIF_SIS_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
#define SPDIF_SIS_VALNOGOOD_MASK                 (0x10000U)
#define SPDIF_SIS_VALNOGOOD_SHIFT                (16U)
#define SPDIF_SIS_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
#define SPDIF_SIS_CNEW_MASK                      (0x20000U)
#define SPDIF_SIS_CNEW_SHIFT                     (17U)
#define SPDIF_SIS_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
#define SPDIF_SIS_TXRESYN_MASK                   (0x40000U)
#define SPDIF_SIS_TXRESYN_SHIFT                  (18U)
#define SPDIF_SIS_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
#define SPDIF_SIS_TXUNOV_MASK                    (0x80000U)
#define SPDIF_SIS_TXUNOV_SHIFT                   (19U)
#define SPDIF_SIS_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
#define SPDIF_SIS_LOCK_MASK                      (0x100000U)
#define SPDIF_SIS_LOCK_SHIFT                     (20U)
#define SPDIF_SIS_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
/*! @} */

/*! @name SRL - SPDIFRxLeft Register */
/*! @{ */
#define SPDIF_SRL_RXDATALEFT_MASK                (0xFFFFFFU)
#define SPDIF_SRL_RXDATALEFT_SHIFT               (0U)
#define SPDIF_SRL_RXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
/*! @} */

/*! @name SRR - SPDIFRxRight Register */
/*! @{ */
#define SPDIF_SRR_RXDATARIGHT_MASK               (0xFFFFFFU)
#define SPDIF_SRR_RXDATARIGHT_SHIFT              (0U)
#define SPDIF_SRR_RXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
/*! @} */

/*! @name SRCSH - SPDIFRxCChannel_h Register */
/*! @{ */
#define SPDIF_SRCSH_RXCCHANNEL_H_MASK            (0xFFFFFFU)
#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT           (0U)
#define SPDIF_SRCSH_RXCCHANNEL_H(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
/*! @} */

/*! @name SRCSL - SPDIFRxCChannel_l Register */
/*! @{ */
#define SPDIF_SRCSL_RXCCHANNEL_L_MASK            (0xFFFFFFU)
#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT           (0U)
#define SPDIF_SRCSL_RXCCHANNEL_L(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
/*! @} */

/*! @name SRU - UchannelRx Register */
/*! @{ */
#define SPDIF_SRU_RXUCHANNEL_MASK                (0xFFFFFFU)
#define SPDIF_SRU_RXUCHANNEL_SHIFT               (0U)
#define SPDIF_SRU_RXUCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
/*! @} */

/*! @name SRQ - QchannelRx Register */
/*! @{ */
#define SPDIF_SRQ_RXQCHANNEL_MASK                (0xFFFFFFU)
#define SPDIF_SRQ_RXQCHANNEL_SHIFT               (0U)
#define SPDIF_SRQ_RXQCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
/*! @} */

/*! @name STL - SPDIFTxLeft Register */
/*! @{ */
#define SPDIF_STL_TXDATALEFT_MASK                (0xFFFFFFU)
#define SPDIF_STL_TXDATALEFT_SHIFT               (0U)
#define SPDIF_STL_TXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
/*! @} */

/*! @name STR - SPDIFTxRight Register */
/*! @{ */
#define SPDIF_STR_TXDATARIGHT_MASK               (0xFFFFFFU)
#define SPDIF_STR_TXDATARIGHT_SHIFT              (0U)
#define SPDIF_STR_TXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
/*! @} */

/*! @name STCSCH - SPDIFTxCChannelCons_h Register */
/*! @{ */
#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK       (0xFFFFFFU)
#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT      (0U)
#define SPDIF_STCSCH_TXCCHANNELCONS_H(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
/*! @} */

/*! @name STCSCL - SPDIFTxCChannelCons_l Register */
/*! @{ */
#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK       (0xFFFFFFU)
#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT      (0U)
#define SPDIF_STCSCL_TXCCHANNELCONS_L(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
/*! @} */

/*! @name SRFM - FreqMeas Register */
/*! @{ */
#define SPDIF_SRFM_FREQMEAS_MASK                 (0xFFFFFFU)
#define SPDIF_SRFM_FREQMEAS_SHIFT                (0U)
#define SPDIF_SRFM_FREQMEAS(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
/*! @} */

/*! @name STC - SPDIFTxClk Register */
/*! @{ */
#define SPDIF_STC_TXCLK_DF_MASK                  (0x7FU)
#define SPDIF_STC_TXCLK_DF_SHIFT                 (0U)
/*! TxClk_DF - TxClk_DF
 *  0b0000000..divider factor is 1
 *  0b0000001..divider factor is 2
 *  0b1111111..divider factor is 128
 */
#define SPDIF_STC_TXCLK_DF(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
#define SPDIF_STC_TX_ALL_CLK_EN_MASK             (0x80U)
#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT            (7U)
/*! tx_all_clk_en - tx_all_clk_en
 *  0b0..disable transfer clock.
 *  0b1..enable transfer clock.
 */
#define SPDIF_STC_TX_ALL_CLK_EN(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
#define SPDIF_STC_TXCLK_SOURCE_MASK              (0x700U)
#define SPDIF_STC_TXCLK_SOURCE_SHIFT             (8U)
/*! TxClk_Source - TxClk_Source
 *  0b000..REF_CLK_32K input (XTALOSC 32 kHz clock)
 *  0b001..tx_clk input (from SPDIF0_CLK_ROOT. See clock control block for more information.)
 *  0b011..SPDIF_EXT_CLK, from pads
 *  0b101..ipg_clk input (frequency divided)
 */
#define SPDIF_STC_TXCLK_SOURCE(x)                (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
#define SPDIF_STC_SYSCLK_DF_MASK                 (0xFF800U)
#define SPDIF_STC_SYSCLK_DF_SHIFT                (11U)
/*! SYSCLK_DF - SYSCLK_DF
 *  0b000000000..no clock signal
 *  0b000000001..divider factor is 2
 *  0b111111111..divider factor is 512
 */
#define SPDIF_STC_SYSCLK_DF(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SPDIF_Register_Masks */


/* SPDIF - Peripheral instance base addresses */
/** Peripheral AUDIO__SPDIF0 base address */
#define AUDIO__SPDIF0_BASE                       (0x59020000u)
/** Peripheral AUDIO__SPDIF0 base pointer */
#define AUDIO__SPDIF0                            ((SPDIF_Type *)AUDIO__SPDIF0_BASE)
/** Peripheral AUDIO__SPDIF1 base address */
#define AUDIO__SPDIF1_BASE                       (0x59030000u)
/** Peripheral AUDIO__SPDIF1 base pointer */
#define AUDIO__SPDIF1                            ((SPDIF_Type *)AUDIO__SPDIF1_BASE)
/** Array initializer of SPDIF peripheral base addresses */
#define SPDIF_BASE_ADDRS                         { AUDIO__SPDIF0_BASE, AUDIO__SPDIF1_BASE }
/** Array initializer of SPDIF peripheral base pointers */
#define SPDIF_BASE_PTRS                          { AUDIO__SPDIF0, AUDIO__SPDIF1 }

/*!
 * @}
 */ /* end of group SPDIF_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- TPM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
 * @{
 */

/** TPM - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __IO uint32_t GLOBAL;                            /**< TPM Global Register, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t SC;                                /**< Status and Control, offset: 0x10 */
  __IO uint32_t CNT;                               /**< Counter, offset: 0x14 */
  __IO uint32_t MOD;                               /**< Modulo, offset: 0x18 */
  __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x1C */
  struct {                                         /* offset: 0x20, array step: 0x8 */
    __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8 */
    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x24, array step: 0x8 */
  } CONTROLS[6];
       uint8_t RESERVED_1[20];
  __IO uint32_t COMBINE;                           /**< Combine Channel Register, offset: 0x64 */
       uint8_t RESERVED_2[4];
  __IO uint32_t TRIG;                              /**< Channel Trigger, offset: 0x6C */
  __IO uint32_t POL;                               /**< Channel Polarity, offset: 0x70 */
       uint8_t RESERVED_3[4];
  __IO uint32_t FILTER;                            /**< Filter Control, offset: 0x78 */
       uint8_t RESERVED_4[4];
  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control and Status, offset: 0x80 */
  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
} TPM_Type;

/* ----------------------------------------------------------------------------
   -- TPM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TPM_Register_Masks TPM Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */
#define TPM_VERID_FEATURE_MASK                   (0xFFFFU)
#define TPM_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Identification Number
 *  0b0000000000000001..Standard feature set.
 *  0b0000000000000011..Standard feature set with Filter and Combine registers implemented.
 *  0b0000000000000111..Standard feature set with Filter, Combine and Quadrature registers implemented.
 */
#define TPM_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK)
#define TPM_VERID_MINOR_MASK                     (0xFF0000U)
#define TPM_VERID_MINOR_SHIFT                    (16U)
#define TPM_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK)
#define TPM_VERID_MAJOR_MASK                     (0xFF000000U)
#define TPM_VERID_MAJOR_SHIFT                    (24U)
#define TPM_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */
#define TPM_PARAM_CHAN_MASK                      (0xFFU)
#define TPM_PARAM_CHAN_SHIFT                     (0U)
#define TPM_PARAM_CHAN(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK)
#define TPM_PARAM_TRIG_MASK                      (0xFF00U)
#define TPM_PARAM_TRIG_SHIFT                     (8U)
#define TPM_PARAM_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK)
#define TPM_PARAM_WIDTH_MASK                     (0xFF0000U)
#define TPM_PARAM_WIDTH_SHIFT                    (16U)
#define TPM_PARAM_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK)
/*! @} */

/*! @name GLOBAL - TPM Global Register */
/*! @{ */
#define TPM_GLOBAL_RST_MASK                      (0x2U)
#define TPM_GLOBAL_RST_SHIFT                     (1U)
/*! RST - Software Reset
 *  0b0..Module is not reset.
 *  0b1..Module is reset.
 */
#define TPM_GLOBAL_RST(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK)
/*! @} */

/*! @name SC - Status and Control */
/*! @{ */
#define TPM_SC_PS_MASK                           (0x7U)
#define TPM_SC_PS_SHIFT                          (0U)
/*! PS - Prescale Factor Selection
 *  0b000..Divide by 1
 *  0b001..Divide by 2
 *  0b010..Divide by 4
 *  0b011..Divide by 8
 *  0b100..Divide by 16
 *  0b101..Divide by 32
 *  0b110..Divide by 64
 *  0b111..Divide by 128
 */
#define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
#define TPM_SC_CMOD_MASK                         (0x18U)
#define TPM_SC_CMOD_SHIFT                        (3U)
/*! CMOD - Clock Mode Selection
 *  0b00..TPM counter is disabled
 *  0b01..TPM counter increments on every TPM counter clock
 *  0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock
 */
#define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
#define TPM_SC_CPWMS_MASK                        (0x20U)
#define TPM_SC_CPWMS_SHIFT                       (5U)
#define TPM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
#define TPM_SC_TOIE_MASK                         (0x40U)
#define TPM_SC_TOIE_SHIFT                        (6U)
/*! TOIE - Timer Overflow Interrupt Enable
 *  0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
 */
#define TPM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
#define TPM_SC_TOF_MASK                          (0x80U)
#define TPM_SC_TOF_SHIFT                         (7U)
#define TPM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
#define TPM_SC_DMA_MASK                          (0x100U)
#define TPM_SC_DMA_SHIFT                         (8U)
/*! DMA - DMA Enable
 *  0b0..Disables DMA transfers.
 *  0b1..Enables DMA transfers.
 */
#define TPM_SC_DMA(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
/*! @} */

/*! @name CNT - Counter */
/*! @{ */
#define TPM_CNT_COUNT_MASK                       (0xFFFFFFFFU)
#define TPM_CNT_COUNT_SHIFT                      (0U)
#define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
/*! @} */

/*! @name MOD - Modulo */
/*! @{ */
#define TPM_MOD_MOD_MASK                         (0xFFFFFFFFU)
#define TPM_MOD_MOD_SHIFT                        (0U)
#define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
/*! @} */

/*! @name STATUS - Capture and Compare Status */
/*! @{ */
#define TPM_STATUS_CH0F_MASK                     (0x1U)
#define TPM_STATUS_CH0F_SHIFT                    (0U)
/*! CH0F - Channel 0 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
#define TPM_STATUS_CH1F_MASK                     (0x2U)
#define TPM_STATUS_CH1F_SHIFT                    (1U)
/*! CH1F - Channel 1 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
#define TPM_STATUS_CH2F_MASK                     (0x4U)
#define TPM_STATUS_CH2F_SHIFT                    (2U)
/*! CH2F - Channel 2 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
#define TPM_STATUS_CH3F_MASK                     (0x8U)
#define TPM_STATUS_CH3F_SHIFT                    (3U)
/*! CH3F - Channel 3 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
#define TPM_STATUS_CH4F_MASK                     (0x10U)
#define TPM_STATUS_CH4F_SHIFT                    (4U)
/*! CH4F - Channel 4 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
#define TPM_STATUS_CH5F_MASK                     (0x20U)
#define TPM_STATUS_CH5F_SHIFT                    (5U)
/*! CH5F - Channel 5 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
#define TPM_STATUS_TOF_MASK                      (0x100U)
#define TPM_STATUS_TOF_SHIFT                     (8U)
#define TPM_STATUS_TOF(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
/*! @} */

/*! @name CnSC - Channel (n) Status and Control */
/*! @{ */
#define TPM_CnSC_DMA_MASK                        (0x1U)
#define TPM_CnSC_DMA_SHIFT                       (0U)
/*! DMA - DMA Enable
 *  0b0..Disable DMA transfers.
 *  0b1..Enable DMA transfers.
 */
#define TPM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
#define TPM_CnSC_ELSA_MASK                       (0x4U)
#define TPM_CnSC_ELSA_SHIFT                      (2U)
#define TPM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
#define TPM_CnSC_ELSB_MASK                       (0x8U)
#define TPM_CnSC_ELSB_SHIFT                      (3U)
#define TPM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
#define TPM_CnSC_MSA_MASK                        (0x10U)
#define TPM_CnSC_MSA_SHIFT                       (4U)
#define TPM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
#define TPM_CnSC_MSB_MASK                        (0x20U)
#define TPM_CnSC_MSB_SHIFT                       (5U)
#define TPM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
#define TPM_CnSC_CHIE_MASK                       (0x40U)
#define TPM_CnSC_CHIE_SHIFT                      (6U)
/*! CHIE - Channel Interrupt Enable
 *  0b0..Disable channel interrupts.
 *  0b1..Enable channel interrupts.
 */
#define TPM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
#define TPM_CnSC_CHF_MASK                        (0x80U)
#define TPM_CnSC_CHF_SHIFT                       (7U)
/*! CHF - Channel Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
/*! @} */

/* The count of TPM_CnSC */
#define TPM_CnSC_COUNT                           (6U)

/*! @name CnV - Channel (n) Value */
/*! @{ */
#define TPM_CnV_VAL_MASK                         (0xFFFFFFFFU)
#define TPM_CnV_VAL_SHIFT                        (0U)
#define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
/*! @} */

/* The count of TPM_CnV */
#define TPM_CnV_COUNT                            (6U)

/*! @name COMBINE - Combine Channel Register */
/*! @{ */
#define TPM_COMBINE_COMBINE0_MASK                (0x1U)
#define TPM_COMBINE_COMBINE0_SHIFT               (0U)
/*! COMBINE0 - Combine Channels 0 and 1
 *  0b0..Channels 0 and 1 are independent.
 *  0b1..Channels 0 and 1 are combined.
 */
#define TPM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
#define TPM_COMBINE_COMSWAP0_MASK                (0x2U)
#define TPM_COMBINE_COMSWAP0_SHIFT               (1U)
/*! COMSWAP0 - Combine Channel 0 and 1 Swap
 *  0b0..Even channel is used for input capture and 1st compare.
 *  0b1..Odd channel is used for input capture and 1st compare.
 */
#define TPM_COMBINE_COMSWAP0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
#define TPM_COMBINE_COMBINE1_MASK                (0x100U)
#define TPM_COMBINE_COMBINE1_SHIFT               (8U)
/*! COMBINE1 - Combine Channels 2 and 3
 *  0b0..Channels 2 and 3 are independent.
 *  0b1..Channels 2 and 3 are combined.
 */
#define TPM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK)
#define TPM_COMBINE_COMSWAP1_MASK                (0x200U)
#define TPM_COMBINE_COMSWAP1_SHIFT               (9U)
/*! COMSWAP1 - Combine Channels 2 and 3 Swap
 *  0b0..Even channel is used for input capture and 1st compare.
 *  0b1..Odd channel is used for input capture and 1st compare.
 */
#define TPM_COMBINE_COMSWAP1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK)
#define TPM_COMBINE_COMBINE2_MASK                (0x10000U)
#define TPM_COMBINE_COMBINE2_SHIFT               (16U)
/*! COMBINE2 - Combine Channels 4 and 5
 *  0b0..Channels 4 and 5 are independent.
 *  0b1..Channels 4 and 5 are combined.
 */
#define TPM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE2_SHIFT)) & TPM_COMBINE_COMBINE2_MASK)
#define TPM_COMBINE_COMSWAP2_MASK                (0x20000U)
#define TPM_COMBINE_COMSWAP2_SHIFT               (17U)
/*! COMSWAP2 - Combine Channels 4 and 5 Swap
 *  0b0..Even channel is used for input capture and 1st compare.
 *  0b1..Odd channel is used for input capture and 1st compare.
 */
#define TPM_COMBINE_COMSWAP2(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP2_SHIFT)) & TPM_COMBINE_COMSWAP2_MASK)
/*! @} */

/*! @name TRIG - Channel Trigger */
/*! @{ */
#define TPM_TRIG_TRIG0_MASK                      (0x1U)
#define TPM_TRIG_TRIG0_SHIFT                     (0U)
/*! TRIG0 - Channel 0 Trigger
 *  0b0..No effect.
 *  0b1..The input trigger is used for input capture and modulates output (for output compare and PWM).
 */
#define TPM_TRIG_TRIG0(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK)
#define TPM_TRIG_TRIG1_MASK                      (0x2U)
#define TPM_TRIG_TRIG1_SHIFT                     (1U)
/*! TRIG1 - Channel 1 Trigger
 *  0b0..No effect.
 *  0b1..The input trigger is used for input capture and modulates output (for output compare and PWM).
 */
#define TPM_TRIG_TRIG1(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK)
#define TPM_TRIG_TRIG2_MASK                      (0x4U)
#define TPM_TRIG_TRIG2_SHIFT                     (2U)
/*! TRIG2 - Channel 2 Trigger
 *  0b0..No effect.
 *  0b1..The input trigger is used for input capture and modulates output (for output compare and PWM).
 */
#define TPM_TRIG_TRIG2(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK)
#define TPM_TRIG_TRIG3_MASK                      (0x8U)
#define TPM_TRIG_TRIG3_SHIFT                     (3U)
/*! TRIG3 - Channel 3 Trigger
 *  0b0..No effect.
 *  0b1..The input trigger is used for input capture and modulates output (for output compare and PWM).
 */
#define TPM_TRIG_TRIG3(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK)
#define TPM_TRIG_TRIG4_MASK                      (0x10U)
#define TPM_TRIG_TRIG4_SHIFT                     (4U)
/*! TRIG4 - Channel 4 Trigger
 *  0b0..No effect.
 *  0b1..The input trigger is used for input capture and modulates output (for output compare and PWM).
 */
#define TPM_TRIG_TRIG4(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG4_SHIFT)) & TPM_TRIG_TRIG4_MASK)
#define TPM_TRIG_TRIG5_MASK                      (0x20U)
#define TPM_TRIG_TRIG5_SHIFT                     (5U)
/*! TRIG5 - Channel 5 Trigger
 *  0b0..No effect.
 *  0b1..The input trigger is used for input capture and modulates output (for output compare and PWM).
 */
#define TPM_TRIG_TRIG5(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG5_SHIFT)) & TPM_TRIG_TRIG5_MASK)
/*! @} */

/*! @name POL - Channel Polarity */
/*! @{ */
#define TPM_POL_POL0_MASK                        (0x1U)
#define TPM_POL_POL0_SHIFT                       (0U)
/*! POL0 - Channel 0 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
#define TPM_POL_POL1_MASK                        (0x2U)
#define TPM_POL_POL1_SHIFT                       (1U)
/*! POL1 - Channel 1 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
#define TPM_POL_POL2_MASK                        (0x4U)
#define TPM_POL_POL2_SHIFT                       (2U)
/*! POL2 - Channel 2 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)
#define TPM_POL_POL3_MASK                        (0x8U)
#define TPM_POL_POL3_SHIFT                       (3U)
/*! POL3 - Channel 3 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)
#define TPM_POL_POL4_MASK                        (0x10U)
#define TPM_POL_POL4_SHIFT                       (4U)
/*! POL4 - Channel 4 Polarity
 *  0b0..The channel polarity is active high
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK)
#define TPM_POL_POL5_MASK                        (0x20U)
#define TPM_POL_POL5_SHIFT                       (5U)
/*! POL5 - Channel 5 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK)
/*! @} */

/*! @name FILTER - Filter Control */
/*! @{ */
#define TPM_FILTER_CH0FVAL_MASK                  (0xFU)
#define TPM_FILTER_CH0FVAL_SHIFT                 (0U)
#define TPM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
#define TPM_FILTER_CH1FVAL_MASK                  (0xF0U)
#define TPM_FILTER_CH1FVAL_SHIFT                 (4U)
#define TPM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
#define TPM_FILTER_CH2FVAL_MASK                  (0xF00U)
#define TPM_FILTER_CH2FVAL_SHIFT                 (8U)
#define TPM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK)
#define TPM_FILTER_CH3FVAL_MASK                  (0xF000U)
#define TPM_FILTER_CH3FVAL_SHIFT                 (12U)
#define TPM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK)
#define TPM_FILTER_CH4FVAL_MASK                  (0xF0000U)
#define TPM_FILTER_CH4FVAL_SHIFT                 (16U)
#define TPM_FILTER_CH4FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH4FVAL_SHIFT)) & TPM_FILTER_CH4FVAL_MASK)
#define TPM_FILTER_CH5FVAL_MASK                  (0xF00000U)
#define TPM_FILTER_CH5FVAL_SHIFT                 (20U)
#define TPM_FILTER_CH5FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH5FVAL_SHIFT)) & TPM_FILTER_CH5FVAL_MASK)
/*! @} */

/*! @name QDCTRL - Quadrature Decoder Control and Status */
/*! @{ */
#define TPM_QDCTRL_QUADEN_MASK                   (0x1U)
#define TPM_QDCTRL_QUADEN_SHIFT                  (0U)
/*! QUADEN - QUADEN
 *  0b0..Quadrature decoder mode is disabled.
 *  0b1..Quadrature decoder mode is enabled.
 */
#define TPM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
#define TPM_QDCTRL_TOFDIR_MASK                   (0x2U)
#define TPM_QDCTRL_TOFDIR_SHIFT                  (1U)
/*! TOFDIR - TOFDIR
 *  0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register).
 *  0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero).
 */
#define TPM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
#define TPM_QDCTRL_QUADIR_MASK                   (0x4U)
#define TPM_QDCTRL_QUADIR_SHIFT                  (2U)
/*! QUADIR - Counter Direction in Quadrature Decode Mode
 *  0b0..Counter direction is decreasing (counter decrement).
 *  0b1..Counter direction is increasing (counter increment).
 */
#define TPM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
#define TPM_QDCTRL_QUADMODE_MASK                 (0x8U)
#define TPM_QDCTRL_QUADMODE_SHIFT                (3U)
/*! QUADMODE - Quadrature Decoder Mode
 *  0b0..Phase encoding mode.
 *  0b1..Count and direction encoding mode.
 */
#define TPM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
/*! @} */

/*! @name CONF - Configuration */
/*! @{ */
#define TPM_CONF_DOZEEN_MASK                     (0x20U)
#define TPM_CONF_DOZEEN_SHIFT                    (5U)
#define TPM_CONF_DOZEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
#define TPM_CONF_DBGMODE_MASK                    (0xC0U)
#define TPM_CONF_DBGMODE_SHIFT                   (6U)
#define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
#define TPM_CONF_GTBSYNC_MASK                    (0x100U)
#define TPM_CONF_GTBSYNC_SHIFT                   (8U)
/*! GTBSYNC - Global Time Base Synchronization
 *  0b0..Global timebase synchronization disabled.
 *  0b1..Global timebase synchronization enabled.
 */
#define TPM_CONF_GTBSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
#define TPM_CONF_GTBEEN_MASK                     (0x200U)
#define TPM_CONF_GTBEEN_SHIFT                    (9U)
/*! GTBEEN - Global time base enable
 *  0b1..All channels use an externally generated global timebase as their timebase
 */
#define TPM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
#define TPM_CONF_CSOT_MASK                       (0x10000U)
#define TPM_CONF_CSOT_SHIFT                      (16U)
#define TPM_CONF_CSOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
#define TPM_CONF_CSOO_MASK                       (0x20000U)
#define TPM_CONF_CSOO_SHIFT                      (17U)
#define TPM_CONF_CSOO(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
#define TPM_CONF_CROT_MASK                       (0x40000U)
#define TPM_CONF_CROT_SHIFT                      (18U)
/*! CROT - Counter Reload On Trigger
 *  0b0..Counter is not reloaded due to a rising edge on the selected input trigger
 *  0b1..Counter is reloaded when a rising edge is detected on the selected input trigger
 */
#define TPM_CONF_CROT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
#define TPM_CONF_CPOT_MASK                       (0x80000U)
#define TPM_CONF_CPOT_SHIFT                      (19U)
#define TPM_CONF_CPOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
#define TPM_CONF_TRGPOL_MASK                     (0x400000U)
#define TPM_CONF_TRGPOL_SHIFT                    (22U)
/*! TRGPOL - Trigger Polarity
 *  0b0..Trigger is active high.
 *  0b1..Trigger is active low.
 */
#define TPM_CONF_TRGPOL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
#define TPM_CONF_TRGSRC_MASK                     (0x800000U)
#define TPM_CONF_TRGSRC_SHIFT                    (23U)
/*! TRGSRC - Trigger Source
 *  0b0..Trigger source selected by TRGSEL is external.
 *  0b1..Trigger source selected by TRGSEL is internal (channel pin input capture).
 */
#define TPM_CONF_TRGSRC(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
#define TPM_CONF_TRGSEL_MASK                     (0xF000000U)
#define TPM_CONF_TRGSEL_SHIFT                    (24U)
/*! TRGSEL - Trigger Select
 *  0b0001..Channel 0 pin input capture
 *  0b0010..Channel 1 pin input capture
 *  0b0011..Channel 0 or Channel 1 pin input capture
 *  0b0100..Channel 2 pin input capture
 *  0b0101..Channel 0 or Channel 2 pin input capture
 *  0b0110..Channel 1 or Channel 2 pin input capture
 *  0b0111..Channel 0 or Channel 1 or Channel 2 pin input capture
 *  0b1000..Channel 3 pin input capture
 *  0b1001..Channel 0 or Channel 3 pin input capture
 *  0b1010..Channel 1 or Channel 3 pin input capture
 *  0b1011..Channel 0 or Channel 1 or Channel 3 pin input capture
 *  0b1100..Channel 2 or Channel 3 pin input capture
 *  0b1101..Channel 0 or Channel 2 or Channel 3 pin input capture
 *  0b1110..Channel 1 or Channel 2 or Channel 3 pin input capture
 *  0b1111..Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture
 */
#define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group TPM_Register_Masks */


/* TPM - Peripheral instance base addresses */
/** Peripheral CM4_0__TPM base address */
#define CM4_0__TPM_BASE                          (0x37200000u)
/** Peripheral CM4_0__TPM base pointer */
#define CM4_0__TPM                               ((TPM_Type *)CM4_0__TPM_BASE)
/** Peripheral CM4_1__TPM base address */
#define CM4_1__TPM_BASE                          (0x41200000u)
/** Peripheral CM4_1__TPM base pointer */
#define CM4_1__TPM                               ((TPM_Type *)CM4_1__TPM_BASE)
/** Peripheral SCU__TPM base address */
#define SCU__TPM_BASE                            (0x33200000u)
/** Peripheral SCU__TPM base pointer */
#define SCU__TPM                                 ((TPM_Type *)SCU__TPM_BASE)
/** Array initializer of TPM peripheral base addresses */
#define TPM_BASE_ADDRS                           { CM4_0__TPM_BASE, CM4_1__TPM_BASE, SCU__TPM_BASE }
/** Array initializer of TPM peripheral base pointers */
#define TPM_BASE_PTRS                            { CM4_0__TPM, CM4_1__TPM, SCU__TPM }
/** Interrupt vectors for the TPM peripheral type */
#define TPM_IRQS                                 { NotAvail_IRQn, M4_1_TPM_IRQn, NotAvail_IRQn }

/*!
 * @}
 */ /* end of group TPM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- TSTMR Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer
 * @{
 */

/** TSTMR - Register Layout Typedef */
typedef struct {
  __I  uint32_t L;                                 /**< Time Stamp Timer Register Low, offset: 0x0 */
  __I  uint32_t H;                                 /**< Time Stamp Timer Register High, offset: 0x4 */
} TSTMR_Type;

/* ----------------------------------------------------------------------------
   -- TSTMR Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TSTMR_Register_Masks TSTMR Register Masks
 * @{
 */

/*! @name L - Time Stamp Timer Register Low */
#define TSTMR_L_VALUE_MASK                       (0xFFFFFFFFU)
#define TSTMR_L_VALUE_SHIFT                      (0U)
#define TSTMR_L_VALUE(x)                         (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK)

/*! @name H - Time Stamp Timer Register High */
#define TSTMR_H_VALUE_MASK                       (0xFFFFFFU)
#define TSTMR_H_VALUE_SHIFT                      (0U)
#define TSTMR_H_VALUE(x)                         (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK)


/*!
 * @}
 */ /* end of group TSTMR_Register_Masks */


/* TSTMR - Peripheral instance base addresses */
/** Peripheral CM4_0__TSTMR base address */
#define CM4_0__TSTMR_BASE                          (0x374100F0u)
/** Peripheral CM4_0__TSTMR base pointer */
#define CM4_0__TSTMR                               ((TSTMR_Type *)CM4_0__TSTMR_BASE)
/** Peripheral CM4_1__TSTMR base address */
#define CM4_1__TSTMR_BASE                          (0x414100F0u)
/** Peripheral CM4_1__TSTMR base pointer */
#define CM4_1__TSTMR                               ((TSTMR_Type *)CM4_1__TSTMR_BASE)
/** Array initializer of TSTMR peripheral base addresses */
#define TSTMR_BASE_ADDRS                         { CM4_0__TSTMR_BASE, CM4_1__TSTMR_BASE }
/** Array initializer of TSTMR peripheral base pointers */
#define TSTMR_BASE_PTRS                          { CM4_0__TSTMR, CM4_1__TSTMR }

/*!
 * @}
 */ /* end of group TSTMR_Peripheral_Access_Layer */
 

/* ----------------------------------------------------------------------------
   -- USB3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USB3_Peripheral_Access_Layer USB3 Peripheral Access Layer
 * @{
 */

/** USB3 - Register Layout Typedef */
typedef struct {
  __O  uint32_t OTGCMD;                            /**< OTG Command, offset: 0x0 */
  __I  uint32_t OTGSTS;                            /**< OTG Status, offset: 0x4 */
  __I  uint32_t OTGSTATE;                          /**< OTG State, offset: 0x8 */
  __IO uint32_t OTGREFCLK;                         /**< OTG Reference Clock, offset: 0xC */
  __IO uint32_t OTGIEN;                            /**< OTG Interrupt Enable, offset: 0x10 */
  __IO uint32_t OTGIVECT;                          /**< OTG Interrupt Vector, offset: 0x14 */
       uint8_t RESERVED_0[8];
  __IO uint32_t CLK_FREQ;                          /**< Clock Frequency, offset: 0x20 */
  __O  uint32_t OTGTMR;                            /**< OTG Timer, offset: 0x24 */
       uint8_t RESERVED_1[8];
  __I  uint32_t OTGVERSION;                        /**< OTG Version, offset: 0x30 */
  __I  uint32_t OTGCAPABILITY;                     /**< OTG Capability, offset: 0x34 */
       uint8_t RESERVED_2[8];
  __IO uint32_t OTGSIMULATE;                       /**< OTG Simulate, offset: 0x40 */
       uint8_t RESERVED_3[12];
  __I  uint32_t OTGANASTS;                         /**< OTG Attach Detection Protocol BC Status, offset: 0x50 */
  __I  uint32_t ADP_RAMP_TIME;                     /**< Attach Detection Protocol Ramp Time, offset: 0x54 */
  __IO uint32_t OTGCTRL1;                          /**< OTG Control, offset: 0x58 */
  __IO uint32_t OTGCTRL2;                          /**< OTG Control, offset: 0x5C */
       uint8_t RESERVED_4[65440];
  __I  uint32_t HCIVERSION_CAPLENGTH;              /**< HCI Version and CAPLENGTH, offset: 0x10000 */
  __I  uint32_t HCSPARAMS1;                        /**< Structural Parameters 1, offset: 0x10004 */
  __I  uint32_t HCSPARAMS2;                        /**< Structural Parameters 2, offset: 0x10008 */
  __I  uint32_t HCSPARAMS3;                        /**< Structural Parameters 3, offset: 0x1000C */
  __I  uint32_t HCCPARAMS;                         /**< Capability Parameters, offset: 0x10010 */
  __I  uint32_t DBOFF;                             /**< DoorBell Array Offset, offset: 0x10014 */
  __I  uint32_t RTSOFF;                            /**< xHCI Runtime Registers Offset, offset: 0x10018 */
       uint8_t RESERVED_5[100];
  __IO uint32_t USBCMD;                            /**< USB Command, offset: 0x10080 */
  __IO uint32_t USBSTS;                            /**< USB Status, offset: 0x10084 */
  __I  uint32_t PAGESIZE;                          /**< Page Size, offset: 0x10088 */
       uint8_t RESERVED_6[8];
  __IO uint32_t DNCTRL;                            /**< Device Notification Control, offset: 0x10094 */
  __IO uint32_t CRCR_LO;                           /**< Command Ring Control Register Low, offset: 0x10098 */
  __IO uint32_t CRCR_HI;                           /**< Command Ring Control Register High, offset: 0x1009C */
       uint8_t RESERVED_7[16];
  __IO uint32_t DCBAAP_LO;                         /**< Device Context Base Address Array Pointer(LOW), offset: 0x100B0 */
  __IO uint32_t DCBAAP_HI;                         /**< Device Context Base Address Array Pointer (HIGH), offset: 0x100B4 */
  __IO uint32_t CONFIG;                            /**< Configure, offset: 0x100B8 */
       uint8_t RESERVED_8[964];
  __IO uint32_t PORTSC1USB2;                       /**< USB2 Port Status and Control, offset: 0x10480 */
  __IO uint32_t PORTPMSC1USB2;                     /**< USB2 Port Power Management Status and Control, offset: 0x10484 */
       uint8_t RESERVED_9[4];
  __IO uint32_t PORT1HLPMC;                        /**< USB2 Port Hardware LPM Control register, offset: 0x1048C */
  __IO uint32_t PORTSC1USB3;                       /**< USB3 Port Status and Control, offset: 0x10490 */
  __IO uint32_t PORTPMSC1USB3;                     /**< USB3 Port Power Management Status and Control, offset: 0x10494 */
  __I  uint32_t PORTLI1;                           /**< USB3 Port Link Info, offset: 0x10498 */
       uint8_t RESERVED_10[7012];
  __I  uint32_t MFINDEX;                           /**< MicroFrame Index, offset: 0x12000 */
       uint8_t RESERVED_11[28];
  __IO uint32_t IMAN0;                             /**< Interrupter Management, offset: 0x12020 */
  __IO uint32_t IMOD0;                             /**< Interrupter Moderation, offset: 0x12024 */
  __IO uint32_t ERSTSZ0;                           /**< Event Ring Segment Table Size, offset: 0x12028 */
       uint32_t RSVD0;                             /**< Reserved, offset: 0x1202C */
  __IO uint32_t ERSTBA0_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x12030 */
  __IO uint32_t ERSTBA00_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x12034 */
  __IO uint32_t ERDP0_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x12038 */
  __IO uint32_t ERDP0_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x1203C */
  __IO uint32_t IMAN1;                             /**< Interrupter Management, offset: 0x12040 */
  __IO uint32_t IMOD1;                             /**< Interrupter Moderation, offset: 0x12044 */
  __IO uint32_t ERSTSZ1;                           /**< Event Ring Segment Table Size, offset: 0x12048 */
       uint32_t RSVD1;                             /**< Reserved, offset: 0x1204C */
  __IO uint32_t ERSTBA1_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x12050 */
  __IO uint32_t ERSTBA01_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x12054 */
  __IO uint32_t ERDP1_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x12058 */
  __IO uint32_t ERDP1_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x1205C */
  __IO uint32_t IMAN2;                             /**< Interrupter Management, offset: 0x12060 */
  __IO uint32_t IMOD2;                             /**< Interrupter Moderation, offset: 0x12064 */
  __IO uint32_t ERSTSZ2;                           /**< Event Ring Segment Table Size, offset: 0x12068 */
       uint32_t RSVD2;                             /**< Reserved, offset: 0x1206C */
  __IO uint32_t ERSTBA2_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x12070 */
  __IO uint32_t ERSTBA02_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x12074 */
  __IO uint32_t ERDP2_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x12078 */
  __IO uint32_t ERDP2_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x1207C */
  __IO uint32_t IMAN3;                             /**< Interrupter Management, offset: 0x12080 */
  __IO uint32_t IMOD3;                             /**< Interrupter Moderation, offset: 0x12084 */
  __IO uint32_t ERSTSZ3;                           /**< Event Ring Segment Table Size, offset: 0x12088 */
       uint32_t RSVD3;                             /**< Reserved, offset: 0x1208C */
  __IO uint32_t ERSTBA3_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x12090 */
  __IO uint32_t ERSTBA03_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x12094 */
  __IO uint32_t ERDP3_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x12098 */
  __IO uint32_t ERDP3_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x1209C */
  __IO uint32_t IMAN4;                             /**< Interrupter Management, offset: 0x120A0 */
  __IO uint32_t IMOD4;                             /**< Interrupter Moderation, offset: 0x120A4 */
  __IO uint32_t ERSTSZ4;                           /**< Event Ring Segment Table Size, offset: 0x120A8 */
       uint32_t RSVD4;                             /**< Reserved, offset: 0x120AC */
  __IO uint32_t ERSTBA4_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x120B0 */
  __IO uint32_t ERSTBA04_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x120B4 */
  __IO uint32_t ERDP4_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x120B8 */
  __IO uint32_t ERDP4_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x120BC */
  __IO uint32_t IMAN5;                             /**< Interrupter Management, offset: 0x120C0 */
  __IO uint32_t IMOD5;                             /**< Interrupter Moderation, offset: 0x120C4 */
  __IO uint32_t ERSTSZ5;                           /**< Event Ring Segment Table Size, offset: 0x120C8 */
       uint32_t RSVD5;                             /**< Reserved, offset: 0x120CC */
  __IO uint32_t ERSTBA5_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x120D0 */
  __IO uint32_t ERSTBA05_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x120D4 */
  __IO uint32_t ERDP5_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x120D8 */
  __IO uint32_t ERDP5_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x120DC */
  __IO uint32_t IMAN6;                             /**< Interrupter Management, offset: 0x120E0 */
  __IO uint32_t IMOD6;                             /**< Interrupter Moderation, offset: 0x120E4 */
  __IO uint32_t ERSTSZ6;                           /**< Event Ring Segment Table Size, offset: 0x120E8 */
       uint32_t RSVD6;                             /**< Reserved, offset: 0x120EC */
  __IO uint32_t ERSTBA6_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x120F0 */
  __IO uint32_t ERSTBA06_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x120F4 */
  __IO uint32_t ERDP6_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x120F8 */
  __IO uint32_t ERDP6_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x120FC */
  __IO uint32_t IMAN7;                             /**< Interrupter Management, offset: 0x12100 */
  __IO uint32_t IMOD7;                             /**< Interrupter Moderation, offset: 0x12104 */
  __IO uint32_t ERSTSZ7;                           /**< Event Ring Segment Table Size, offset: 0x12108 */
       uint32_t RSVD7;                             /**< Reserved, offset: 0x1210C */
  __IO uint32_t ERSTBA7_LO;                        /**< Event Ring Segment Table Base Address (LOW), offset: 0x12110 */
  __IO uint32_t ERSTBA07_HI;                       /**< Event Ring Segment Table Base Address (HIGH), offset: 0x12114 */
  __IO uint32_t ERDP7_LO;                          /**< Event Ring Dequeue Pointer (LOW), offset: 0x12118 */
  __IO uint32_t ERDP7_HI;                          /**< Event Ring Dequeue Pointer (HIGH), offset: 0x1211C */
       uint8_t RESERVED_12[3808];
  __IO uint32_t DB0;                               /**< Host Controller Doorbell, offset: 0x13000 */
  __IO uint32_t DB1;                               /**< Doorbell Array, offset: 0x13004 */
  __IO uint32_t DB2;                               /**< Doorbell Array, offset: 0x13008 */
  __IO uint32_t DB3;                               /**< Doorbell Array, offset: 0x1300C */
  __IO uint32_t DB4;                               /**< Doorbell Array, offset: 0x13010 */
  __IO uint32_t DB5;                               /**< Doorbell Array, offset: 0x13014 */
  __IO uint32_t DB6;                               /**< Doorbell Array, offset: 0x13018 */
  __IO uint32_t DB7;                               /**< Doorbell Array, offset: 0x1301C */
  __IO uint32_t DB8;                               /**< Doorbell Array, offset: 0x13020 */
  __IO uint32_t DB9;                               /**< Doorbell Array, offset: 0x13024 */
  __IO uint32_t DB10;                              /**< Doorbell Array, offset: 0x13028 */
  __IO uint32_t DB11;                              /**< Doorbell Array, offset: 0x1302C */
  __IO uint32_t DB12;                              /**< Doorbell Array, offset: 0x13030 */
  __IO uint32_t DB13;                              /**< Doorbell Array, offset: 0x13034 */
  __IO uint32_t DB14;                              /**< Doorbell Array, offset: 0x13038 */
  __IO uint32_t DB15;                              /**< Doorbell Array, offset: 0x1303C */
  __IO uint32_t DB16;                              /**< Doorbell Array, offset: 0x13040 */
  __IO uint32_t DB17;                              /**< Doorbell Array, offset: 0x13044 */
  __IO uint32_t DB18;                              /**< Doorbell Array, offset: 0x13048 */
  __IO uint32_t DB19;                              /**< Doorbell Array, offset: 0x1304C */
  __IO uint32_t DB20;                              /**< Doorbell Array, offset: 0x13050 */
  __IO uint32_t DB21;                              /**< Doorbell Array, offset: 0x13054 */
  __IO uint32_t DB22;                              /**< Doorbell Array, offset: 0x13058 */
  __IO uint32_t DB23;                              /**< Doorbell Array, offset: 0x1305C */
  __IO uint32_t DB24;                              /**< Doorbell Array, offset: 0x13060 */
  __IO uint32_t DB25;                              /**< Doorbell Array, offset: 0x13064 */
  __IO uint32_t DB26;                              /**< Doorbell Array, offset: 0x13068 */
  __IO uint32_t DB27;                              /**< Doorbell Array, offset: 0x1306C */
  __IO uint32_t DB28;                              /**< Doorbell Array, offset: 0x13070 */
  __IO uint32_t DB29;                              /**< Doorbell Array, offset: 0x13074 */
  __IO uint32_t DB30;                              /**< Doorbell Array, offset: 0x13078 */
  __IO uint32_t DB31;                              /**< Doorbell Array, offset: 0x1307C */
  __IO uint32_t DB32;                              /**< Doorbell Array, offset: 0x13080 */
       uint8_t RESERVED_13[20348];
  __IO uint32_t XECP_PORT_CAP_REG;                 /**< USB3 Extended capability, offset: 0x18000 */
  __IO uint32_t XECP_PORT_1_REG;                   /**< USB3 Extended capability, offset: 0x18004 */
  __IO uint32_t XECP_CDNS_DEBUG_BUS_CAP;           /**< xHCI Debug Bus Capability, offset: 0x18008 */
  __IO uint32_t XECP_CDNS_DEBUG_BUS_CTRL;          /**< xHCI Debug Bus Control, offset: 0x1800C */
  __I  uint32_t XECP_CDNS_DEBUG_BUS_STATUS;        /**< xHCI Debug Bus Status, offset: 0x18010 */
  __IO uint32_t XECP_PM_CAP;                       /**< Extended Power Management capability, offset: 0x18014 */
  __IO uint32_t XECP_PM_PMCSR;                     /**< Extended Power Management Control/Status, offset: 0x18018 */
  __IO uint32_t XECP_MSI_CAP;                      /**< MSI configuration, offset: 0x1801C */
  __IO uint32_t XECP_MSI_ADDR_L;                   /**< Message Lower Address, offset: 0x18020 */
  __IO uint32_t XECP_MSI_ADDR_H;                   /**< Message Upper Address, offset: 0x18024 */
  __IO uint32_t XECP_MSI_DATA;                     /**< Message data, offset: 0x18028 */
  __IO uint32_t XECP_AXI_CAP;                      /**< AXI Master Wrapper Extended Capability, offset: 0x1802C */
  __I  uint32_t XECP_AXI_CFG0;                     /**< AXI Master Wrapper Extended Capability Configuration, offset: 0x18030 */
  __IO uint32_t XECP_AXI_CTRL0;                    /**< AXI Master Wrapper Extended Capability Control, offset: 0x18034 */
  __IO uint32_t XECP_AXI_CTRL1;                    /**< AXI Master Wrapper Extended Capability Control, offset: 0x18038 */
  __IO uint32_t XECP_AXI_CTRL2;                    /**< AXI Master Wrapper Extended Capability Control, offset: 0x1803C */
  __I  uint32_t XECP_SUPP_USB2_CAP0;               /**< xHCI Supported Protocol Capability, offset: 0x18040 */
  __I  uint32_t XECP_SUPP_USB2_CAP1;               /**< xHCI Supported Protocol Capability, offset: 0x18044 */
  __I  uint32_t XECP_SUPP_USB2_CAP2;               /**< xHCI Supported Protocol Capability, offset: 0x18048 */
  __I  uint32_t XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE; /**< Protocol Slot Type, offset: 0x1804C */
  __I  uint32_t XECP_PSI_FULL_SPEED;               /**< Protocol Speed ID, offset: 0x18050 */
  __I  uint32_t XECP_PSI_LOW_SPEED;                /**< Protocol Speed ID, offset: 0x18054 */
  __I  uint32_t XECP_PSI_HIGH_SPEED;               /**< Protocol Speed ID, offset: 0x18058 */
       uint8_t RESERVED_14[4];
  __I  uint32_t XECP_SUPP_USB3_CAP0;               /**< xHCI Supported Protocol Capability, offset: 0x18060 */
  __I  uint32_t XECP_SUPP_USB3_CAP1;               /**< xHCI Supported Protocol Capability, offset: 0x18064 */
  __I  uint32_t XECP_SUPP_USB3_CAP2;               /**< xHCI Supported Protocol Capability; USB 3, offset: 0x18068 */
  __I  uint32_t XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE; /**< Protocol Slot Type, offset: 0x1806C */
  __I  uint32_t PSI_SUPER_SPEED;                   /**< Protocol Speed ID, offset: 0x18070 */
       uint8_t RESERVED_15[12];
  __I  uint32_t XECP_CMDM_STS0;                    /**< Command Ring related status, offset: 0x18080 */
       uint32_t RSVD01;                            /**< Reserved, offset: 0x18084 */
       uint32_t RSVD02;                            /**< Reserved, offset: 0x18088 */
       uint32_t RSVD03;                            /**< Reserved, offset: 0x1808C */
       uint32_t RSVD04;                            /**< Reserved, offset: 0x18090 */
       uint32_t RSVD05;                            /**< Reserved, offset: 0x18094 */
  __IO uint32_t XECP_CMDM_CTRL_REG1;               /**< Command Manager Control, offset: 0x18098 */
  __IO uint32_t XECP_CMDM_CTRL_REG2;               /**< Command Manager Control, offset: 0x1809C */
  __IO uint32_t XECP_CMDM_CTRL_REG3;               /**< Command Manager Control, offset: 0x180A0 */
       uint8_t RESERVED_16[12];
  __I  uint32_t XECP_HOST_CTRL_CAP;                /**< Host Control Capability, offset: 0x180B0 */
       uint32_t XECP_HOST_CTRL_RSVD;               /**< Reserved, offset: 0x180B4 */
  __O  uint32_t XECP_HOST_CLR_MASK_REG;            /**< Override Endpoint Flow Control, offset: 0x180B8 */
  __O  uint32_t XECP_HOST_CLR_IN_EP_VALID_REG;     /**< Clear Active IN EP ID Control, offset: 0x180BC */
  __O  uint32_t XECP_HOST_CLR_PMASK_REG;           /**< Clear Poll Mask Control, offset: 0x180C0 */
  __IO uint32_t XECP_HOST_CTRL_OCRD_REG;           /**< Port Credit Control, offset: 0x180C4 */
  __I  uint32_t XECP_HOST_CTRL_TEST_BUS_LO;        /**< Test Bus Low, offset: 0x180C8 */
  __I  uint32_t XECP_HOST_CTRL_TEST_BUS_HI;        /**< Test Bus High, offset: 0x180CC */
  __IO uint32_t XECP_HOST_CTRL_TRM_REG1;           /**< Host Control Transfer Manager, offset: 0x180D0 */
  __IO uint32_t XECP_HOST_CTRL_SCH_REG1;           /**< Host Control Scheduler, offset: 0x180D4 */
  __IO uint32_t XECP_HOST_CTRL_ODMA_REG;           /**< Host Control ODMA, offset: 0x180D8 */
  __IO uint32_t XECP_HOST_CTRL_IDMA_REG;           /**< Host Control IDMA, offset: 0x180DC */
  __IO uint32_t XECP_HOST_CTRL_PORT_CTRL;          /**< Global Port Control, offset: 0x180E0 */
       uint8_t RESERVED_17[28];
  __IO uint32_t XECP_AUX_CTRL_REG;                 /**< AUX Reset Control, offset: 0x18100 */
  __IO uint32_t XECP_HOST_BW_OV_SS_REG;            /**< Super Speed Bandwidth Overload, offset: 0x18104 */
  __IO uint32_t XECP_HOST_BW_OV_HS_REG;            /**< High Speed TT Bandwidth Overload, offset: 0x18108 */
  __IO uint32_t XECP_HOST_BW_OV_FS_LS_REG;         /**< Bandwidth Overload Full and Low Speed, offset: 0x1810C */
  __IO uint32_t XECP_HOST_BW_OV_SYS_REG;           /**< System Bandwidth Overload, offset: 0x18110 */
  __IO uint32_t XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG; /**< Scheduler Async Delay, offset: 0x18114 */
  __O  uint32_t XECP_UPORTS_PON_RST_REG;           /**< AUX Power PHY Reset, offset: 0x18118 */
  __IO uint32_t XECP_HOST_CTRL_TRM_REG3;           /**< Host Control Transfer Manager (TRM), offset: 0x1811C */
  __IO uint32_t XECP_AUX_CTRL_REG1;                /**< AUX Power Management Control 1, offset: 0x18120 */
       uint8_t RESERVED_18[4];
  __IO uint32_t XECP_HOST_CTRL_WATERMARK_REG;      /**< Port Watermark, offset: 0x18128 */
  __IO uint32_t XECP_HOST_CTRL_PORT_LINK_REG;      /**< SuperSpeed Port Link Control, offset: 0x1812C */
  __IO uint32_t XECP_USB2_LINK_MGR_CTRL_REG1;      /**< USB2 Port Link Control, offset: 0x18130 */
  __IO uint32_t XECP_USB2_LINK_MGR_CTRL_REG2;      /**< USB2 Port Link Control, offset: 0x18134 */
  __IO uint32_t XECP_USB2_LINK_MGR_CTRL_REG3;      /**< USB2 Port Link Control, offset: 0x18138 */
  __IO uint32_t XECP_USB2_LINK_MGR_CTRL_REG4;      /**< USB2 Port Link Control, offset: 0x1813C */
  __IO uint32_t XECP_HOST_CTRL_BW_MAX_REG;         /**< USB2 Max Bandwidth Control, offset: 0x18140 */
  __I  uint32_t XECP_FPGA_REVISION_REG;            /**< FPGA_REVISION_REG, offset: 0x18144 */
  __IO uint32_t XECP_HOST_INTF_CTRL_REG;           /**< Host interface control, offset: 0x18148 */
  __IO uint32_t XECP_BW_OV_SS_BURST_REG;           /**< BW_OV_SS_BURST_REG, offset: 0x1814C */
  __IO uint32_t XECP_HOST_CTRL_TRM_REG2;           /**< Host Control Transfer Manager (TRM), offset: 0x18150 */
       uint8_t RESERVED_19[20];
  __IO uint32_t XECP_HOST_CTRL_BW_MAX1_REG;        /**< HOST_CTRL_BW_MAX1_REG, offset: 0x18168 */
  __IO uint32_t XECP_HOST_CTRL_BW_MAX2_REG;        /**< HOST_CTRL_BW_MAX2_REG, offset: 0x1816C */
  __I  uint32_t XECP_USB2_LINESTATE_REG;           /**< USB2_LINESTATE_REG, offset: 0x18170 */
  __IO uint32_t XECP_HOST_PROTO_GAP_TIMER1_REG;    /**< HOST_PROTO_GAP_TIMER1_REG, offset: 0x18174 */
  __IO uint32_t XECP_HOST_PROTO_GAP_TIMER2_REG;    /**< HOST_PROTO_GAP_TIMER2_REG, offset: 0x18178 */
  __IO uint32_t XECP_HOST_PROTO_BTO_TIMER_REG;     /**< HOST_PROTO_BTO_TIMER_REG, offset: 0x1817C */
  __IO uint32_t XECP_HOST_CTRL_PSCH_REG;           /**< HOST_CTRL_PSCH_REG, offset: 0x18180 */
  __IO uint32_t XECP_HOST_CTRL_PSCH1_REG;          /**< HOST_CTRL_PSCH1_REG, offset: 0x18184 */
       uint8_t RESERVED_20[8];
  __I  uint32_t XECP_HOST_CTRL_LTM_REG;            /**< HOST_CTRL_LTM_REG, offset: 0x18190 */
  __IO uint32_t XECP_AUX_CTRL_REG2;                /**< AUX Power Management Control 1, offset: 0x18194 */
  __IO uint32_t XECP_AUX_CTRL_REG3;                /**< Configuration bits for USB2 PHY, offset: 0x18198 */
  __IO uint32_t XECP_DEBUG_CTRL_REG;               /**< DEBUG_CTRL_REG, offset: 0x1819C */
  __IO uint32_t XECP_HOST_CTRL_SCH_REG2;           /**< Host Control Scheduler, offset: 0x181A0 */
  __I  uint32_t XECP_AUX_DEBUG_READ_ONLY;          /**< AUX_DEBUG_READ_ONLY, offset: 0x181A4 */
  __I  uint32_t XECP_AUX_CTRL_PORTNUM_REG;         /**< AUX_CTRL_PORTNUM_REG, offset: 0x181A8 */
  __I  uint32_t XECP_AUX_CTRL_DEV_REMOVE_REG;      /**< Feature #3002 (Device Removable in PORTSC), offset: 0x181AC */
  __IO uint32_t XECP_HOST_CTRL_DEBUG_PORT_DESC;    /**< dbgp_desc_ctrl_reg, offset: 0x181B0 */
  __IO uint32_t XECP_HOST_CTRL_DEBUG_PORT_TRM;     /**< dbgp_trm_ctrl_reg, offset: 0x181B4 */
  __IO uint32_t XECP_HOST_CTRL_DEBUG_PORT_IDMA;    /**< dbgp_idma_ctrl_reg, offset: 0x181B8 */
  __IO uint32_t XECP_HOST_CTRL_DEBUG_PORT_ODMA;    /**< dbgp_odma_ctrl_reg, offset: 0x181BC */
  __IO uint32_t XECP_HOST_CTRL_DEBUG_PORT_MISC;    /**< dbgp_misc_ctrl_reg, offset: 0x181C0 */
       uint8_t RESERVED_21[28];
  __IO uint32_t XECP_HOST_CTRL_TTE_REG1;           /**< Specific control register for SCH, offset: 0x181E0 */
  __IO uint32_t XECP_HOST_CTRL_LTM_REG1;           /**< HOST_CTRL_LTM_REG1, offset: 0x181E4 */
  __IO uint32_t XECP_HOST_CTRL_LTM_REG2;           /**< HOST_CTRL_LTM_REG2, offset: 0x181E8 */
       uint8_t RESERVED_22[20];
       uint32_t XECP_AUX_SCRATCHPAD_0;             /**< For internal use, offset: 0x18200 */
       uint32_t XECP_AUX_SCRATCHPAD_1;             /**< For internal use, offset: 0x18204 */
       uint8_t RESERVED_23[8];
  __IO uint32_t XECP_BATTERY_CHARGE_REG;           /**< Battery charge mode and enable, offset: 0x18210 */
  __IO uint32_t XECP_BATTERY_CHARGE_REG1;          /**< Battery charge control register 1, offset: 0x18214 */
  __IO uint32_t XECP_BATTERY_CHARGE_REG2;          /**< Battery charge control register 2, offset: 0x18218 */
  __I  uint32_t XECP_BATTERY_CHARGE_REG3;          /**< Battery charge debug, offset: 0x1821C */
  __IO uint32_t XECP_HOST_CTRL_PORT_LINK_REG1;     /**< Feature #581, offset: 0x18220 */
       uint8_t RESERVED_24[332];
  __IO uint32_t XECP_USBLEGSUP;                    /**< USB Legacy Support Capability, offset: 0x18370 */
  __IO uint32_t XECP_USBLEGCTLSTS;                 /**< USB Legacy Support Control Status, offset: 0x18374 */
       uint8_t RESERVED_25[8];
  __I  uint32_t XECP_DCID;                         /**< Debug Capability ID, offset: 0x18380 */
  __IO uint32_t XECP_DCDB;                         /**< Debug Capability Doorbell, offset: 0x18384 */
  __IO uint32_t XECP_DCERSTSZ;                     /**< Debug Capability Event Ring Segment Table Size, offset: 0x18388 */
       uint32_t XECP_RSVD_0C;                      /**< Reserved, offset: 0x1838C */
  __IO uint32_t XECP_DCERSTBA_LOW;                 /**< Debug Capability Event Ring Segment Table Base Address, offset: 0x18390 */
  __IO uint32_t XECP_DCERSTBA_HIGH;                /**< Debug Capability Event Ring Segment Table Base Address, offset: 0x18394 */
  __IO uint32_t XECP_DCERDP_LOW;                   /**< Debug Capability Event Ring Dequeue Pointer, offset: 0x18398 */
  __IO uint32_t XECP_DCERDP_HIGH;                  /**< Debug Capability Event Ring Dequeue Pointer, offset: 0x1839C */
  __IO uint32_t XECP_DCCTRL;                       /**< Debug Capability Control, offset: 0x183A0 */
  __I  uint32_t XECP_DCST;                         /**< Debug Capability Status, offset: 0x183A4 */
  __IO uint32_t XECP_DCPORTSC;                     /**< Debug Capability Port Status and Control, offset: 0x183A8 */
       uint32_t XECP_RSVD_2C;                      /**< Reserved, offset: 0x183AC */
  __IO uint32_t XECP_DCCP_LOW;                     /**< Debug Capability Context Pointer, offset: 0x183B0 */
  __IO uint32_t XECP_DCCP_HIGH;                    /**< Debug Capability Context Pointer, offset: 0x183B4 */
  __IO uint32_t XECP_DCDDI1;                       /**< Debug Capability Device Descriptor Info, offset: 0x183B8 */
  __IO uint32_t XECP_DCDDI2;                       /**< The Debug Capability Device Descriptor, offset: 0x183BC */
       uint8_t RESERVED_26[1088];
  __IO uint32_t XECP_USB3_TEST_PORT0_REG;          /**< USB3_TEST_PORT_REG, offset: 0x18800 */
       uint8_t RESERVED_27[30716];
  __IO uint32_t USB_CONF;                          /**< Global Configuration, offset: 0x20000 */
  __I  uint32_t USB_STS;                           /**< Global Status, offset: 0x20004 */
  __IO uint32_t USB_CMD;                           /**< Global Command, offset: 0x20008 */
  __I  uint32_t USB_IPTN;                          /**< ITP Number, offset: 0x2000C */
  __I  uint32_t USB_LPM;                           /**< Link Power Management, offset: 0x20010 */
  __IO uint32_t USB_IEN;                           /**< Interrupt Enable, offset: 0x20014 */
  __IO uint32_t USB_ISTS;                          /**< Interrupt Status, offset: 0x20018 */
  __IO uint32_t EP_SEL;                            /**< Endpoint Select, offset: 0x2001C */
  __IO uint32_t EP_TRADDR;                         /**< Endpoint Transfer Ring Address, offset: 0x20020 */
  __IO uint32_t EP_CFG;                            /**< Endpoint Configuration, offset: 0x20024 */
  __IO uint32_t EP_CMD;                            /**< Endpoint Command, offset: 0x20028 */
  __IO uint32_t EP_STS;                            /**< Endpoint Status, offset: 0x2002C */
  __I  uint32_t EP_STS_SID;                        /**< Endpoint Status, offset: 0x20030 */
  __IO uint32_t EP_STS_EN;                         /**< Endpoint Status Register Enable, offset: 0x20034 */
  __IO uint32_t DRBL;                              /**< Doorbell Register, offset: 0x20038 */
  __IO uint32_t EP_IEN;                            /**< Endpoints Interrupt Enable), offset: 0x2003C */
  __I  uint32_t EP_ISTS;                           /**< Endpoints Interrupt Status, offset: 0x20040 */
  __IO uint32_t USB_PWR;                           /**< Global power configuration, offset: 0x20044 */
  __IO uint32_t USB_CONF2;                         /**< USB configuration, offset: 0x20048 */
  __I  uint32_t USB_CAP1;                          /**< USB Capability, offset: 0x2004C */
  __I  uint32_t USB_CAP2;                          /**< USB Capability, offset: 0x20050 */
  __I  uint32_t USB_CAP3;                          /**< USB Capability, offset: 0x20054 */
  __I  uint32_t USB_CAP4;                          /**< ISO HW support, offset: 0x20058 */
  __I  uint32_t USB_CAP5;                          /**< Bulk Stream HW, offset: 0x2005C */
  __I  uint32_t USB_CAP6;                          /**< Device controller version, offset: 0x20060 */
  __IO uint32_t USB_CPKT1;                         /**< Custom Packet value, offset: 0x20064 */
  __IO uint32_t USB_CPKT2;                         /**< Custom Packet value, offset: 0x20068 */
  __IO uint32_t USB_CPKT3;                         /**< Custom Packet value, offset: 0x2006C */
       uint8_t RESERVED_28[144];
  __IO uint32_t CFG_REG1;                          /**< VBUS debouncer Configuration, offset: 0x20100 */
  __IO uint32_t DBG_LINK1;                         /**< Link, offset: 0x20104 */
  __IO uint32_t DBG_LINK2;                         /**< Link, offset: 0x20108 */
  __IO uint32_t CFG_REG4;                          /**< USB3 Configuration, offset: 0x2010C */
  __IO uint32_t CFG_REG5;                          /**< USB3 Configuration, offset: 0x20110 */
  __IO uint32_t CFG_REG6;                          /**< Configuration Register 6, offset: 0x20114 */
  __IO uint32_t CFG_REG7;                          /**< USB3 Configuration, offset: 0x20118 */
  __IO uint32_t CFG_REG8;                          /**< USB3 Configuration, offset: 0x2011C */
  __IO uint32_t CFG_REG9;                          /**< USB3 Configuration, offset: 0x20120 */
  __IO uint32_t CFG_REG10;                         /**< USB3 Configuration, offset: 0x20124 */
  __IO uint32_t CFG_REG11;                         /**< USB3 Configuration, offset: 0x20128 */
  __IO uint32_t CFG_REG12;                         /**< USB3 Configuration, offset: 0x2012C */
  __IO uint32_t CFG_REG13;                         /**< USB3 Configuration, offset: 0x20130 */
  __IO uint32_t CFG_REG14;                         /**< USB3 Configuration, offset: 0x20134 */
  __IO uint32_t CFG_REG15;                         /**< USB3 Configuration, offset: 0x20138 */
  __IO uint32_t CFG_REG16;                         /**< USB3 Configuration, offset: 0x2013C */
  __IO uint32_t CFG_REG17;                         /**< USB3 Configuration, offset: 0x20140 */
  __IO uint32_t CFG_REG18;                         /**< USB3 Configuration, offset: 0x20144 */
  __IO uint32_t CFG_REG19;                         /**< USB3 Configuration, offset: 0x20148 */
  __IO uint32_t CFG_REG20;                         /**< USB3 Configuration, offset: 0x2014C */
  __IO uint32_t CFG_REG21;                         /**< USB3 Configuration, offset: 0x20150 */
  __IO uint32_t CFG_REG22;                         /**< USB3 Configuration, offset: 0x20154 */
  __IO uint32_t CFG_REG23;                         /**< USB3 Configuration, offset: 0x20158 */
  __IO uint32_t CFG_REG24;                         /**< USB3 Configuration, offset: 0x2015C */
  __IO uint32_t CFG_REG25;                         /**< USB3 Configuration, offset: 0x20160 */
  __IO uint32_t CFG_REG26;                         /**< USB3 Configuration, offset: 0x20164 */
  __IO uint32_t CFG_REG27;                         /**< USB3 Configuration, offset: 0x20168 */
  __IO uint32_t CFG_REG28;                         /**< USB3 Configuration, offset: 0x2016C */
  __IO uint32_t CFG_REG29;                         /**< USB3 Configuration, offset: 0x20170 */
  __IO uint32_t CFG_REG30;                         /**< USB3 Configuration, offset: 0x20174 */
  __IO uint32_t CFG_REG31;                         /**< USB3 Configuration, offset: 0x20178 */
  __IO uint32_t CFG_REG32;                         /**< USB3 Configuration, offset: 0x2017C */
  __IO uint32_t CFG_REG33;                         /**< USB3 Configuration, offset: 0x20180 */
  __IO uint32_t CFG_REG34;                         /**< USB3 Configuration, offset: 0x20184 */
  __IO uint32_t CFG_REG35;                         /**< USB3 Configuration, offset: 0x20188 */
       uint8_t RESERVED_29[32];
  __IO uint32_t CFG_REG36;                         /**< USB3 Configuration, offset: 0x201AC */
  __IO uint32_t CFG_REG37;                         /**< USB3 Configuration, offset: 0x201B0 */
  __IO uint32_t CFG_REG38;                         /**< USB3 Configuration, offset: 0x201B4 */
  __IO uint32_t CFG_REG39;                         /**< USB3 Configuration, offset: 0x201B8 */
  __IO uint32_t CFG_REG40;                         /**< USB3 Configuration, offset: 0x201BC */
  __IO uint32_t CFG_REG41;                         /**< USB3 Configuration, offset: 0x201C0 */
  __IO uint32_t CFG_REG42;                         /**< USB3 Configuration, offset: 0x201C4 */
  __IO uint32_t CFG_REG43;                         /**< USB3 Configuration, offset: 0x201C8 */
  __IO uint32_t CFG_REG44;                         /**< USB3 Configuration, offset: 0x201CC */
  __IO uint32_t CFG_REG45;                         /**< USB3 Configuration, offset: 0x201D0 */
  __IO uint32_t CFG_REG46;                         /**< USB3 Configuration, offset: 0x201D4 */
  __IO uint32_t CFG_REG47;                         /**< USB3 Configuration, offset: 0x201D8 */
  __IO uint32_t CFG_REG48;                         /**< USB2 Configuration, offset: 0x201DC */
  __IO uint32_t CFG_REG49;                         /**< USB2 Configuration, offset: 0x201E0 */
  __IO uint32_t CFG_REG50;                         /**< USB2 Configuration, offset: 0x201E4 */
  __IO uint32_t CFG_REG51;                         /**< USB2 Configuration, offset: 0x201E8 */
  __IO uint32_t CFG_REG52;                         /**< USB2 Configuration, offset: 0x201EC */
  __IO uint32_t CFG_REG53;                         /**< USB2 Configuration, offset: 0x201F0 */
  __IO uint32_t CFG_REG54;                         /**< USB2 Configuration, offset: 0x201F4 */
  __IO uint32_t CFG_REG55;                         /**< USB2 Configuration, offset: 0x201F8 */
  __IO uint32_t CFG_REG56;                         /**< USB2 Configuration, offset: 0x201FC */
  __IO uint32_t CFG_REG57;                         /**< USB3 Configuration, offset: 0x20200 */
  __IO uint32_t CFG_REG58;                         /**< USB3 Configuration, offset: 0x20204 */
  __IO uint32_t CFG_REG59;                         /**< USB3 Configuration, offset: 0x20208 */
  __IO uint32_t CFG_REG60;                         /**< USB3 Configuration, offset: 0x2020C */
  __IO uint32_t CFG_REG61;                         /**< USB3 Configuration, offset: 0x20210 */
  __IO uint32_t CFG_REG62;                         /**< USB3 Configuration, offset: 0x20214 */
  __IO uint32_t CFG_REG63;                         /**< USB3 Configuration, offset: 0x20218 */
       uint8_t RESERVED_30[4];
  __IO uint32_t CFG_REG64;                         /**< USB2 Configuration, offset: 0x20220 */
  __IO uint32_t CFG_REG65;                         /**< USB2 Configuration, offset: 0x20224 */
  __IO uint32_t CFG_REG66;                         /**< USB2 Configuration, offset: 0x20228 */
       uint8_t RESERVED_31[212];
  __IO uint32_t DMA_AXI_CTRL;                      /**< DMA AXI Master Control, offset: 0x20300 */
  __IO uint32_t DMA_AXI_ID;                        /**< DMA AXI Master ID, offset: 0x20304 */
  __IO uint32_t DMA_AXI_CAP;                       /**< DMA AXI Master Extended Capability, offset: 0x20308 */
  __IO uint32_t DMA_AXI_CTRL0;                     /**< DMA AXI Master Control, offset: 0x2030C */
  __IO uint32_t DMA_AXI_CTRL1;                     /**< DMA AXI Master Control, offset: 0x20310 */
} USB3_Type;

/* ----------------------------------------------------------------------------
   -- USB3 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USB3_Register_Masks USB3 Register Masks
 * @{
 */

/*! @name OTGCMD - OTG Command */
/*! @{ */
#define USB3_OTGCMD_DEV_BUS_REQ_MASK             (0x1U)
#define USB3_OTGCMD_DEV_BUS_REQ_SHIFT            (0U)
#define USB3_OTGCMD_DEV_BUS_REQ(x)               (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_BUS_REQ_SHIFT)) & USB3_OTGCMD_DEV_BUS_REQ_MASK)
#define USB3_OTGCMD_HOST_BUS_REQ_MASK            (0x2U)
#define USB3_OTGCMD_HOST_BUS_REQ_SHIFT           (1U)
#define USB3_OTGCMD_HOST_BUS_REQ(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_HOST_BUS_REQ_SHIFT)) & USB3_OTGCMD_HOST_BUS_REQ_MASK)
#define USB3_OTGCMD_OTG_EN_MASK                  (0x4U)
#define USB3_OTGCMD_OTG_EN_SHIFT                 (2U)
#define USB3_OTGCMD_OTG_EN(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_OTG_EN_SHIFT)) & USB3_OTGCMD_OTG_EN_MASK)
#define USB3_OTGCMD_OTG_DIS_MASK                 (0x8U)
#define USB3_OTGCMD_OTG_DIS_SHIFT                (3U)
#define USB3_OTGCMD_OTG_DIS(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_OTG_DIS_SHIFT)) & USB3_OTGCMD_OTG_DIS_MASK)
#define USB3_OTGCMD_A_DEV_EN_MASK                (0x10U)
#define USB3_OTGCMD_A_DEV_EN_SHIFT               (4U)
#define USB3_OTGCMD_A_DEV_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_A_DEV_EN_SHIFT)) & USB3_OTGCMD_A_DEV_EN_MASK)
#define USB3_OTGCMD_A_DEV_DIS_MASK               (0x20U)
#define USB3_OTGCMD_A_DEV_DIS_SHIFT              (5U)
#define USB3_OTGCMD_A_DEV_DIS(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_A_DEV_DIS_SHIFT)) & USB3_OTGCMD_A_DEV_DIS_MASK)
#define USB3_OTGCMD_DEV_SESS_VLD_USE_SET_MASK    (0x40U)
#define USB3_OTGCMD_DEV_SESS_VLD_USE_SET_SHIFT   (6U)
#define USB3_OTGCMD_DEV_SESS_VLD_USE_SET(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_SESS_VLD_USE_SET_SHIFT)) & USB3_OTGCMD_DEV_SESS_VLD_USE_SET_MASK)
#define USB3_OTGCMD_DEV_SESS_VLD_USE_CLR_MASK    (0x80U)
#define USB3_OTGCMD_DEV_SESS_VLD_USE_CLR_SHIFT   (7U)
#define USB3_OTGCMD_DEV_SESS_VLD_USE_CLR(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_SESS_VLD_USE_CLR_SHIFT)) & USB3_OTGCMD_DEV_SESS_VLD_USE_CLR_MASK)
#define USB3_OTGCMD_DEV_BUS_DROP_MASK            (0x100U)
#define USB3_OTGCMD_DEV_BUS_DROP_SHIFT           (8U)
#define USB3_OTGCMD_DEV_BUS_DROP(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_BUS_DROP_SHIFT)) & USB3_OTGCMD_DEV_BUS_DROP_MASK)
#define USB3_OTGCMD_HOST_BUS_DROP_MASK           (0x200U)
#define USB3_OTGCMD_HOST_BUS_DROP_SHIFT          (9U)
#define USB3_OTGCMD_HOST_BUS_DROP(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_HOST_BUS_DROP_SHIFT)) & USB3_OTGCMD_HOST_BUS_DROP_MASK)
#define USB3_OTGCMD_DIS_VBUS_DROP_MASK           (0x400U)
#define USB3_OTGCMD_DIS_VBUS_DROP_SHIFT          (10U)
#define USB3_OTGCMD_DIS_VBUS_DROP(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DIS_VBUS_DROP_SHIFT)) & USB3_OTGCMD_DIS_VBUS_DROP_MASK)
#define USB3_OTGCMD_DEV_POWER_OFF_MASK           (0x800U)
#define USB3_OTGCMD_DEV_POWER_OFF_SHIFT          (11U)
#define USB3_OTGCMD_DEV_POWER_OFF(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_POWER_OFF_SHIFT)) & USB3_OTGCMD_DEV_POWER_OFF_MASK)
#define USB3_OTGCMD_HOST_POWER_OFF_MASK          (0x1000U)
#define USB3_OTGCMD_HOST_POWER_OFF_SHIFT         (12U)
#define USB3_OTGCMD_HOST_POWER_OFF(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_HOST_POWER_OFF_SHIFT)) & USB3_OTGCMD_HOST_POWER_OFF_MASK)
#define USB3_OTGCMD_DEV_DEVEN_FORCE_SET_MASK     (0x2000U)
#define USB3_OTGCMD_DEV_DEVEN_FORCE_SET_SHIFT    (13U)
#define USB3_OTGCMD_DEV_DEVEN_FORCE_SET(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_DEVEN_FORCE_SET_SHIFT)) & USB3_OTGCMD_DEV_DEVEN_FORCE_SET_MASK)
#define USB3_OTGCMD_DEV_DEVEN_FORCE_CLR_MASK     (0x4000U)
#define USB3_OTGCMD_DEV_DEVEN_FORCE_CLR_SHIFT    (14U)
#define USB3_OTGCMD_DEV_DEVEN_FORCE_CLR(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_DEVEN_FORCE_CLR_SHIFT)) & USB3_OTGCMD_DEV_DEVEN_FORCE_CLR_MASK)
#define USB3_OTGCMD_H_WRST_FOR_SWAP_SET_MASK     (0x8000U)
#define USB3_OTGCMD_H_WRST_FOR_SWAP_SET_SHIFT    (15U)
#define USB3_OTGCMD_H_WRST_FOR_SWAP_SET(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_H_WRST_FOR_SWAP_SET_SHIFT)) & USB3_OTGCMD_H_WRST_FOR_SWAP_SET_MASK)
#define USB3_OTGCMD_H_WRST_FOR_SWAP_CLR_MASK     (0x10000U)
#define USB3_OTGCMD_H_WRST_FOR_SWAP_CLR_SHIFT    (16U)
#define USB3_OTGCMD_H_WRST_FOR_SWAP_CLR(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_H_WRST_FOR_SWAP_CLR_SHIFT)) & USB3_OTGCMD_H_WRST_FOR_SWAP_CLR_MASK)
#define USB3_OTGCMD_D_WRST_FOR_SWAP_SET_MASK     (0x20000U)
#define USB3_OTGCMD_D_WRST_FOR_SWAP_SET_SHIFT    (17U)
#define USB3_OTGCMD_D_WRST_FOR_SWAP_SET(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_D_WRST_FOR_SWAP_SET_SHIFT)) & USB3_OTGCMD_D_WRST_FOR_SWAP_SET_MASK)
#define USB3_OTGCMD_D_WRST_FOR_SWAP_CLR_MASK     (0x40000U)
#define USB3_OTGCMD_D_WRST_FOR_SWAP_CLR_SHIFT    (18U)
#define USB3_OTGCMD_D_WRST_FOR_SWAP_CLR(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_D_WRST_FOR_SWAP_CLR_SHIFT)) & USB3_OTGCMD_D_WRST_FOR_SWAP_CLR_MASK)
#define USB3_OTGCMD_SS_HOST_DISABLED_SET_MASK    (0x80000U)
#define USB3_OTGCMD_SS_HOST_DISABLED_SET_SHIFT   (19U)
#define USB3_OTGCMD_SS_HOST_DISABLED_SET(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_SS_HOST_DISABLED_SET_SHIFT)) & USB3_OTGCMD_SS_HOST_DISABLED_SET_MASK)
#define USB3_OTGCMD_SS_HOST_DISABLED_CLR_MASK    (0x100000U)
#define USB3_OTGCMD_SS_HOST_DISABLED_CLR_SHIFT   (20U)
#define USB3_OTGCMD_SS_HOST_DISABLED_CLR(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_SS_HOST_DISABLED_CLR_SHIFT)) & USB3_OTGCMD_SS_HOST_DISABLED_CLR_MASK)
#define USB3_OTGCMD_SS_PERIPH_DISABLED_SET_MASK  (0x200000U)
#define USB3_OTGCMD_SS_PERIPH_DISABLED_SET_SHIFT (21U)
#define USB3_OTGCMD_SS_PERIPH_DISABLED_SET(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_SS_PERIPH_DISABLED_SET_SHIFT)) & USB3_OTGCMD_SS_PERIPH_DISABLED_SET_MASK)
#define USB3_OTGCMD_SS_PERIPH_DISABLED_CLR_MASK  (0x400000U)
#define USB3_OTGCMD_SS_PERIPH_DISABLED_CLR_SHIFT (22U)
#define USB3_OTGCMD_SS_PERIPH_DISABLED_CLR(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_SS_PERIPH_DISABLED_CLR_SHIFT)) & USB3_OTGCMD_SS_PERIPH_DISABLED_CLR_MASK)
#define USB3_OTGCMD_A_SET_B_HNP_EN_SET_MASK      (0x800000U)
#define USB3_OTGCMD_A_SET_B_HNP_EN_SET_SHIFT     (23U)
#define USB3_OTGCMD_A_SET_B_HNP_EN_SET(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_A_SET_B_HNP_EN_SET_SHIFT)) & USB3_OTGCMD_A_SET_B_HNP_EN_SET_MASK)
#define USB3_OTGCMD_A_SET_B_HNP_EN_CLR_MASK      (0x1000000U)
#define USB3_OTGCMD_A_SET_B_HNP_EN_CLR_SHIFT     (24U)
#define USB3_OTGCMD_A_SET_B_HNP_EN_CLR(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_A_SET_B_HNP_EN_CLR_SHIFT)) & USB3_OTGCMD_A_SET_B_HNP_EN_CLR_MASK)
#define USB3_OTGCMD_B_HNP_EN_SET_MASK            (0x2000000U)
#define USB3_OTGCMD_B_HNP_EN_SET_SHIFT           (25U)
#define USB3_OTGCMD_B_HNP_EN_SET(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_B_HNP_EN_SET_SHIFT)) & USB3_OTGCMD_B_HNP_EN_SET_MASK)
#define USB3_OTGCMD_B_HNP_EN_CLR_MASK            (0x4000000U)
#define USB3_OTGCMD_B_HNP_EN_CLR_SHIFT           (26U)
#define USB3_OTGCMD_B_HNP_EN_CLR(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_B_HNP_EN_CLR_SHIFT)) & USB3_OTGCMD_B_HNP_EN_CLR_MASK)
#define USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH_MASK   (0x8000000U)
#define USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH_SHIFT  (27U)
#define USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH_SHIFT)) & USB3_OTGCMD_OTG2_SWITCH_TO_PERIPH_MASK)
#define USB3_OTGCMD_INIT_SRP_MASK                (0x10000000U)
#define USB3_OTGCMD_INIT_SRP_SHIFT               (28U)
#define USB3_OTGCMD_INIT_SRP(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_INIT_SRP_SHIFT)) & USB3_OTGCMD_INIT_SRP_MASK)
#define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET_MASK  (0x20000000U)
#define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET_SHIFT (29U)
#define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET_SHIFT)) & USB3_OTGCMD_DEV_VBUS_DEB_SHORT_SET_MASK)
#define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR_MASK  (0x40000000U)
#define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR_SHIFT (30U)
#define USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR_SHIFT)) & USB3_OTGCMD_DEV_VBUS_DEB_SHORT_CLR_MASK)
/*! @} */

/*! @name OTGSTS - OTG Status */
/*! @{ */
#define USB3_OTGSTS_ID_VALUE_MASK                (0x1U)
#define USB3_OTGSTS_ID_VALUE_SHIFT               (0U)
#define USB3_OTGSTS_ID_VALUE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_ID_VALUE_SHIFT)) & USB3_OTGSTS_ID_VALUE_MASK)
#define USB3_OTGSTS_VBUS_VALID_MASK              (0x2U)
#define USB3_OTGSTS_VBUS_VALID_SHIFT             (1U)
#define USB3_OTGSTS_VBUS_VALID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_VBUS_VALID_SHIFT)) & USB3_OTGSTS_VBUS_VALID_MASK)
#define USB3_OTGSTS_SESSION_VALID_MASK           (0x4U)
#define USB3_OTGSTS_SESSION_VALID_SHIFT          (2U)
#define USB3_OTGSTS_SESSION_VALID(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SESSION_VALID_SHIFT)) & USB3_OTGSTS_SESSION_VALID_MASK)
#define USB3_OTGSTS_DEV_ACTIVE_MASK              (0x8U)
#define USB3_OTGSTS_DEV_ACTIVE_SHIFT             (3U)
#define USB3_OTGSTS_DEV_ACTIVE(x)                (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_ACTIVE_SHIFT)) & USB3_OTGSTS_DEV_ACTIVE_MASK)
#define USB3_OTGSTS_HOST_ACTIVE_MASK             (0x10U)
#define USB3_OTGSTS_HOST_ACTIVE_SHIFT            (4U)
#define USB3_OTGSTS_HOST_ACTIVE(x)               (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_HOST_ACTIVE_SHIFT)) & USB3_OTGSTS_HOST_ACTIVE_MASK)
#define USB3_OTGSTS_OTG_IS_ENABLED_MASK          (0x20U)
#define USB3_OTGSTS_OTG_IS_ENABLED_SHIFT         (5U)
#define USB3_OTGSTS_OTG_IS_ENABLED(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_OTG_IS_ENABLED_SHIFT)) & USB3_OTGSTS_OTG_IS_ENABLED_MASK)
#define USB3_OTGSTS_OTG_MODE_MASK                (0x40U)
#define USB3_OTGSTS_OTG_MODE_SHIFT               (6U)
#define USB3_OTGSTS_OTG_MODE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_OTG_MODE_SHIFT)) & USB3_OTGSTS_OTG_MODE_MASK)
#define USB3_OTGSTS_SS_HOST_DISABLED_MASK        (0x80U)
#define USB3_OTGSTS_SS_HOST_DISABLED_SHIFT       (7U)
#define USB3_OTGSTS_SS_HOST_DISABLED(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SS_HOST_DISABLED_SHIFT)) & USB3_OTGSTS_SS_HOST_DISABLED_MASK)
#define USB3_OTGSTS_SS_PERIPH_DISABLED_MASK      (0x100U)
#define USB3_OTGSTS_SS_PERIPH_DISABLED_SHIFT     (8U)
#define USB3_OTGSTS_SS_PERIPH_DISABLED(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SS_PERIPH_DISABLED_SHIFT)) & USB3_OTGSTS_SS_PERIPH_DISABLED_MASK)
#define USB3_OTGSTS_DEV_VBUS_DEB_SHORT_MASK      (0x200U)
#define USB3_OTGSTS_DEV_VBUS_DEB_SHORT_SHIFT     (9U)
#define USB3_OTGSTS_DEV_VBUS_DEB_SHORT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_VBUS_DEB_SHORT_SHIFT)) & USB3_OTGSTS_DEV_VBUS_DEB_SHORT_MASK)
#define USB3_OTGSTS_DEV_SESS_VLD_USE_MASK        (0x400U)
#define USB3_OTGSTS_DEV_SESS_VLD_USE_SHIFT       (10U)
#define USB3_OTGSTS_DEV_SESS_VLD_USE(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_SESS_VLD_USE_SHIFT)) & USB3_OTGSTS_DEV_SESS_VLD_USE_MASK)
#define USB3_OTGSTS_OTG_NRDY_MASK                (0x800U)
#define USB3_OTGSTS_OTG_NRDY_SHIFT               (11U)
#define USB3_OTGSTS_OTG_NRDY(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_OTG_NRDY_SHIFT)) & USB3_OTGSTS_OTG_NRDY_MASK)
#define USB3_OTGSTS_STRAP_MASK                   (0x7000U)
#define USB3_OTGSTS_STRAP_SHIFT                  (12U)
#define USB3_OTGSTS_STRAP(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_STRAP_SHIFT)) & USB3_OTGSTS_STRAP_MASK)
#define USB3_OTGSTS_H_WRST_FOR_SWAP_MASK         (0x8000U)
#define USB3_OTGSTS_H_WRST_FOR_SWAP_SHIFT        (15U)
#define USB3_OTGSTS_H_WRST_FOR_SWAP(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_H_WRST_FOR_SWAP_SHIFT)) & USB3_OTGSTS_H_WRST_FOR_SWAP_MASK)
#define USB3_OTGSTS_DEV_DEVEN_FORCE_MASK         (0x10000U)
#define USB3_OTGSTS_DEV_DEVEN_FORCE_SHIFT        (16U)
#define USB3_OTGSTS_DEV_DEVEN_FORCE(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_DEVEN_FORCE_SHIFT)) & USB3_OTGSTS_DEV_DEVEN_FORCE_MASK)
#define USB3_OTGSTS_D_WRST_FOR_SWAP_MASK         (0x20000U)
#define USB3_OTGSTS_D_WRST_FOR_SWAP_SHIFT        (17U)
#define USB3_OTGSTS_D_WRST_FOR_SWAP(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_D_WRST_FOR_SWAP_SHIFT)) & USB3_OTGSTS_D_WRST_FOR_SWAP_MASK)
#define USB3_OTGSTS_SRP_INITIAL_CONDITION_MET_MASK (0x40000U)
#define USB3_OTGSTS_SRP_INITIAL_CONDITION_MET_SHIFT (18U)
#define USB3_OTGSTS_SRP_INITIAL_CONDITION_MET(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SRP_INITIAL_CONDITION_MET_SHIFT)) & USB3_OTGSTS_SRP_INITIAL_CONDITION_MET_MASK)
#define USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV_MASK (0x80000U)
#define USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV_SHIFT (19U)
#define USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV_SHIFT)) & USB3_OTGSTS_SRP_DET_NOT_COMPLIANT_DEV_MASK)
#define USB3_OTGSTS_A_SET_B_HNP_EN_MASK          (0x800000U)
#define USB3_OTGSTS_A_SET_B_HNP_EN_SHIFT         (23U)
#define USB3_OTGSTS_A_SET_B_HNP_EN(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_A_SET_B_HNP_EN_SHIFT)) & USB3_OTGSTS_A_SET_B_HNP_EN_MASK)
#define USB3_OTGSTS_B_HNP_EN_MASK                (0x2000000U)
#define USB3_OTGSTS_B_HNP_EN_SHIFT               (25U)
#define USB3_OTGSTS_B_HNP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_B_HNP_EN_SHIFT)) & USB3_OTGSTS_B_HNP_EN_MASK)
#define USB3_OTGSTS_XHC_READY_MASK               (0x4000000U)
#define USB3_OTGSTS_XHC_READY_SHIFT              (26U)
#define USB3_OTGSTS_XHC_READY(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_XHC_READY_SHIFT)) & USB3_OTGSTS_XHC_READY_MASK)
#define USB3_OTGSTS_DEV_READY_MASK               (0x8000000U)
#define USB3_OTGSTS_DEV_READY_SHIFT              (27U)
#define USB3_OTGSTS_DEV_READY(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTS_DEV_READY_SHIFT)) & USB3_OTGSTS_DEV_READY_MASK)
/*! @} */

/*! @name OTGSTATE - OTG State */
/*! @{ */
#define USB3_OTGSTATE_DEV_OTG_STATE_MASK         (0x7U)
#define USB3_OTGSTATE_DEV_OTG_STATE_SHIFT        (0U)
/*! DEV_OTG_STATE - Current state of the OTG Device FSM
 *  0b000..DEV_IDLE
 *  0b001..DEV_MODE
 *  0b010..DEV_SRP
 *  0b011..DEV_WAIT_VBUS_FALL
 *  0b100..DEV_SWITCH_TO_HOST
 *  0b101..DEV_WAIT_FOR_CONN
 */
#define USB3_OTGSTATE_DEV_OTG_STATE(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_DEV_OTG_STATE_SHIFT)) & USB3_OTGSTATE_DEV_OTG_STATE_MASK)
#define USB3_OTGSTATE_HOST_OTG_STATE_MASK        (0x38U)
#define USB3_OTGSTATE_HOST_OTG_STATE_SHIFT       (3U)
/*! HOST_OTG_STATE - Current state of the OTG Host FSM
 *  0b000..H_IDLE
 *  0b001..H_VBUS_ON
 *  0b010..H_VBUS_FAILED
 *  0b011..H_OTG_HOST_MODE
 *  0b100..H_HOST_MODE
 *  0b101..H_SWITCH_TO_DEVICE
 *  0b110..H_A_SUSPEND
 *  0b111..H_WAIT_VBUS_FALL
 */
#define USB3_OTGSTATE_HOST_OTG_STATE(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_HOST_OTG_STATE_SHIFT)) & USB3_OTGSTATE_HOST_OTG_STATE_MASK)
#define USB3_OTGSTATE_APB_AXI_CTRL_MASK          (0x300U)
#define USB3_OTGSTATE_APB_AXI_CTRL_SHIFT         (8U)
/*! APB_AXI_CTRL - Current state of the ABP/AXI mux selector
 *  0b00..Both modes off
 *  0b01..Host Active
 *  0b10..Device Active
 *  0b11..Illegal(Both modes off)
 */
#define USB3_OTGSTATE_APB_AXI_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_APB_AXI_CTRL_SHIFT)) & USB3_OTGSTATE_APB_AXI_CTRL_MASK)
#define USB3_OTGSTATE_PIPE_CTRL_MASK             (0xC00U)
#define USB3_OTGSTATE_PIPE_CTRL_SHIFT            (10U)
/*! PIPE_CTRL - Current state of the USB3 PIPE mux selector
 *  0b00..Both modes off
 *  0b01..Host Active
 *  0b10..Device Active
 *  0b11..Illegal(both modes off)
 */
#define USB3_OTGSTATE_PIPE_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_PIPE_CTRL_SHIFT)) & USB3_OTGSTATE_PIPE_CTRL_MASK)
#define USB3_OTGSTATE_UTMI_CTRL_MASK             (0x3000U)
#define USB3_OTGSTATE_UTMI_CTRL_SHIFT            (12U)
/*! UTMI_CTRL - Current state of the USB2 UTMI mux selector
 *  0b00..Both modes off, and OTG takes control over UTMI (SRP,BC)
 *  0b01..Host Active
 *  0b10..Device Active
 *  0b11..Illegal(both modes off)
 */
#define USB3_OTGSTATE_UTMI_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_UTMI_CTRL_SHIFT)) & USB3_OTGSTATE_UTMI_CTRL_MASK)
#define USB3_OTGSTATE_DEV_POWER_STATE_MASK       (0x70000U)
#define USB3_OTGSTATE_DEV_POWER_STATE_SHIFT      (16U)
/*! DEV_POWER_STATE - Current state of the Device power controlling FSM
 *  0b000..POWER_IDLE
 *  0b001..POWER_OFF_ACK
 *  0b010..POWER_OFF_MAIN_ACK
 *  0b011..POWER_OFF
 *  0b100..POWER_ON_REQ
 *  0b101..POWER_ISO_DIS
 *  0b110..POWER_ON
 *  0b111..POWER_ON_READY
 */
#define USB3_OTGSTATE_DEV_POWER_STATE(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_DEV_POWER_STATE_SHIFT)) & USB3_OTGSTATE_DEV_POWER_STATE_MASK)
#define USB3_OTGSTATE_HOST_POWER_STATE_MASK      (0x380000U)
#define USB3_OTGSTATE_HOST_POWER_STATE_SHIFT     (19U)
/*! HOST_POWER_STATE - Current state of the Host power controlling FSM
 *  0b000..POWER_IDLE
 *  0b001..POWER_OFF_ACK
 *  0b010..POWER_OFF_MAIN_ACK
 *  0b011..POWER_OFF
 *  0b100..POWER_ON_REQ
 *  0b101..POWER_ISO_DIS
 *  0b110..POWER_ON
 *  0b111..POWER_ON_READY
 */
#define USB3_OTGSTATE_HOST_POWER_STATE(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_HOST_POWER_STATE_SHIFT)) & USB3_OTGSTATE_HOST_POWER_STATE_MASK)
#define USB3_OTGSTATE_PHY_REFCLK_REQ_MASK        (0x1000000U)
#define USB3_OTGSTATE_PHY_REFCLK_REQ_SHIFT       (24U)
#define USB3_OTGSTATE_PHY_REFCLK_REQ(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_PHY_REFCLK_REQ_SHIFT)) & USB3_OTGSTATE_PHY_REFCLK_REQ_MASK)
#define USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID_MASK (0x2000000U)
#define USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID_SHIFT (25U)
#define USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID_SHIFT)) & USB3_OTGSTATE_PHY_REFCLK_1PCT_VALID_MASK)
#define USB3_OTGSTATE_PHY_REFCLK_VALID_MASK      (0x4000000U)
#define USB3_OTGSTATE_PHY_REFCLK_VALID_SHIFT     (26U)
#define USB3_OTGSTATE_PHY_REFCLK_VALID(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_PHY_REFCLK_VALID_SHIFT)) & USB3_OTGSTATE_PHY_REFCLK_VALID_MASK)
#define USB3_OTGSTATE_REFCLK_FSM_MASK            (0x38000000U)
#define USB3_OTGSTATE_REFCLK_FSM_SHIFT           (27U)
/*! REFCLK_FSM - Reference Clock control FSM state
 *  0b000..IDLE
 *  0b001..SWITCH32_GATE_ON
 *  0b010..REFCLK_OFF
 *  0b011..REFCLK_REQ
 *  0b100..GATE_OFF
 *  0b101..REFCLK_ON_SWITCH32
 *  0b110..REFCLK_ON_PHY3_AT_SLOW
 *  0b111..REFCLK_ON_SWITCH24
 */
#define USB3_OTGSTATE_REFCLK_FSM(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGSTATE_REFCLK_FSM_SHIFT)) & USB3_OTGSTATE_REFCLK_FSM_MASK)
/*! @} */

/*! @name OTGREFCLK - OTG Reference Clock */
/*! @{ */
#define USB3_OTGREFCLK_P3_TO_REFCLK_REQ_MASK     (0x3FFFU)
#define USB3_OTGREFCLK_P3_TO_REFCLK_REQ_SHIFT    (0U)
#define USB3_OTGREFCLK_P3_TO_REFCLK_REQ(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGREFCLK_P3_TO_REFCLK_REQ_SHIFT)) & USB3_OTGREFCLK_P3_TO_REFCLK_REQ_MASK)
#define USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ_MASK (0x3FFF0000U)
#define USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ_SHIFT (16U)
#define USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ_SHIFT)) & USB3_OTGREFCLK_SUSPEND_TO_REFCLK_REQ_MASK)
#define USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN_MASK (0x80000000U)
#define USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN_SHIFT (31U)
#define USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN_SHIFT)) & USB3_OTGREFCLK_OTG_STB_CLK_SWITCH_EN_MASK)
/*! @} */

/*! @name OTGIEN - OTG Interrupt Enable */
/*! @{ */
#define USB3_OTGIEN_ID_CHANGE_INT_EN_MASK        (0x1U)
#define USB3_OTGIEN_ID_CHANGE_INT_EN_SHIFT       (0U)
#define USB3_OTGIEN_ID_CHANGE_INT_EN(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_ID_CHANGE_INT_EN_SHIFT)) & USB3_OTGIEN_ID_CHANGE_INT_EN_MASK)
#define USB3_OTGIEN_VBUS_ON_FAILED_INT_EN_MASK   (0x2U)
#define USB3_OTGIEN_VBUS_ON_FAILED_INT_EN_SHIFT  (1U)
#define USB3_OTGIEN_VBUS_ON_FAILED_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_VBUS_ON_FAILED_INT_EN_SHIFT)) & USB3_OTGIEN_VBUS_ON_FAILED_INT_EN_MASK)
#define USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN_MASK (0x4U)
#define USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN_SHIFT (2U)
#define USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_OTGSESSVALID_RISE_INT_EN_MASK)
#define USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN_MASK (0x8U)
#define USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN_SHIFT (3U)
#define USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN_SHIFT)) & USB3_OTGIEN_OTGSESSVALID_FALL_INT_EN_MASK)
#define USB3_OTGIEN_VBUSVALID_RISE_INT_EN_MASK   (0x10U)
#define USB3_OTGIEN_VBUSVALID_RISE_INT_EN_SHIFT  (4U)
#define USB3_OTGIEN_VBUSVALID_RISE_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_VBUSVALID_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_VBUSVALID_RISE_INT_EN_MASK)
#define USB3_OTGIEN_VBUSVALID_FALL_INT_EN_MASK   (0x20U)
#define USB3_OTGIEN_VBUSVALID_FALL_INT_EN_SHIFT  (5U)
#define USB3_OTGIEN_VBUSVALID_FALL_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_VBUSVALID_FALL_INT_EN_SHIFT)) & USB3_OTGIEN_VBUSVALID_FALL_INT_EN_MASK)
#define USB3_OTGIEN_SENSE_RISE_INT_EN_MASK       (0x40U)
#define USB3_OTGIEN_SENSE_RISE_INT_EN_SHIFT      (6U)
#define USB3_OTGIEN_SENSE_RISE_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SENSE_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_SENSE_RISE_INT_EN_MASK)
#define USB3_OTGIEN_PROBE_RISE_INT_EN_MASK       (0x80U)
#define USB3_OTGIEN_PROBE_RISE_INT_EN_SHIFT      (7U)
#define USB3_OTGIEN_PROBE_RISE_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_PROBE_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_PROBE_RISE_INT_EN_MASK)
#define USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN_MASK (0x100U)
#define USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN_SHIFT (8U)
#define USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN_SHIFT)) & USB3_OTGIEN_ADP_PROBE_COMPLETED_INT_EN_MASK)
#define USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN_MASK (0x200U)
#define USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN_SHIFT (9U)
#define USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TA_AIDL_BDIS_TMOUT_INT_EN_MASK)
#define USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN_MASK (0x400U)
#define USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN_SHIFT (10U)
#define USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TA_BIDL_ADIS_TMOUT_INT_EN_MASK)
#define USB3_OTGIEN_SRP_DET_INT_EN_MASK          (0x800U)
#define USB3_OTGIEN_SRP_DET_INT_EN_SHIFT         (11U)
#define USB3_OTGIEN_SRP_DET_INT_EN(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SRP_DET_INT_EN_SHIFT)) & USB3_OTGIEN_SRP_DET_INT_EN_MASK)
#define USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN_MASK (0x1000U)
#define USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN_SHIFT (12U)
#define USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN_SHIFT)) & USB3_OTGIEN_SRP_NOT_COMP_DEV_REMOVED_INT_EN_MASK)
#define USB3_OTGIEN_OVERCURRENT_INT_EN_MASK      (0x2000U)
#define USB3_OTGIEN_OVERCURRENT_INT_EN_SHIFT     (13U)
#define USB3_OTGIEN_OVERCURRENT_INT_EN(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_OVERCURRENT_INT_EN_SHIFT)) & USB3_OTGIEN_OVERCURRENT_INT_EN_MASK)
#define USB3_OTGIEN_SRP_FAIL_INT_EN_MASK         (0x4000U)
#define USB3_OTGIEN_SRP_FAIL_INT_EN_SHIFT        (14U)
#define USB3_OTGIEN_SRP_FAIL_INT_EN(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SRP_FAIL_INT_EN_SHIFT)) & USB3_OTGIEN_SRP_FAIL_INT_EN_MASK)
#define USB3_OTGIEN_SRP_CMPL_INT_EN_MASK         (0x8000U)
#define USB3_OTGIEN_SRP_CMPL_INT_EN_SHIFT        (15U)
#define USB3_OTGIEN_SRP_CMPL_INT_EN(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_SRP_CMPL_INT_EN_SHIFT)) & USB3_OTGIEN_SRP_CMPL_INT_EN_MASK)
#define USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN_MASK (0x10000U)
#define USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN_SHIFT (16U)
#define USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TB_ASE0_BRST_TMOUT_INT_EN_MASK)
#define USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN_MASK (0x20000U)
#define USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN_SHIFT (17U)
#define USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TB_AIDL_BDIS_MIN_TMOUT_INT_EN_MASK)
#define USB3_OTGIEN_TIMER_TMOUT_INT_EN_MASK      (0x40000U)
#define USB3_OTGIEN_TIMER_TMOUT_INT_EN_SHIFT     (18U)
#define USB3_OTGIEN_TIMER_TMOUT_INT_EN(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_TIMER_TMOUT_INT_EN_SHIFT)) & USB3_OTGIEN_TIMER_TMOUT_INT_EN_MASK)
#define USB3_OTGIEN_H_POLL_ENTRY_INT_EN_MASK     (0x80000U)
#define USB3_OTGIEN_H_POLL_ENTRY_INT_EN_SHIFT    (19U)
#define USB3_OTGIEN_H_POLL_ENTRY_INT_EN(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_H_POLL_ENTRY_INT_EN_SHIFT)) & USB3_OTGIEN_H_POLL_ENTRY_INT_EN_MASK)
#define USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN_MASK  (0x100000U)
#define USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN_SHIFT (20U)
#define USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN_SHIFT)) & USB3_OTGIEN_H_WRST_GEN_CMPL_INT_EN_MASK)
#define USB3_OTGIEN_RID_FLOAT_FALL_INT_EN_MASK   (0x200000U)
#define USB3_OTGIEN_RID_FLOAT_FALL_INT_EN_SHIFT  (21U)
#define USB3_OTGIEN_RID_FLOAT_FALL_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_FLOAT_FALL_INT_EN_SHIFT)) & USB3_OTGIEN_RID_FLOAT_FALL_INT_EN_MASK)
#define USB3_OTGIEN_RID_FLOAT_RISE_INT_EN_MASK   (0x400000U)
#define USB3_OTGIEN_RID_FLOAT_RISE_INT_EN_SHIFT  (22U)
#define USB3_OTGIEN_RID_FLOAT_RISE_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_FLOAT_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_FLOAT_RISE_INT_EN_MASK)
#define USB3_OTGIEN_RID_GND_RISE_INT_EN_MASK     (0x800000U)
#define USB3_OTGIEN_RID_GND_RISE_INT_EN_SHIFT    (23U)
#define USB3_OTGIEN_RID_GND_RISE_INT_EN(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_GND_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_GND_RISE_INT_EN_MASK)
#define USB3_OTGIEN_RID_C_RISE_INT_EN_MASK       (0x1000000U)
#define USB3_OTGIEN_RID_C_RISE_INT_EN_SHIFT      (24U)
#define USB3_OTGIEN_RID_C_RISE_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_C_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_C_RISE_INT_EN_MASK)
#define USB3_OTGIEN_RID_B_RISE_INT_EN_MASK       (0x2000000U)
#define USB3_OTGIEN_RID_B_RISE_INT_EN_SHIFT      (25U)
#define USB3_OTGIEN_RID_B_RISE_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_B_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_B_RISE_INT_EN_MASK)
#define USB3_OTGIEN_RID_A_RISE_INT_EN_MASK       (0x4000000U)
#define USB3_OTGIEN_RID_A_RISE_INT_EN_SHIFT      (26U)
#define USB3_OTGIEN_RID_A_RISE_INT_EN(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_RID_A_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_RID_A_RISE_INT_EN_MASK)
#define USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN_MASK (0x8000000U)
#define USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN_SHIFT (27U)
#define USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_DM_VDAT_REF_RISE_INT_EN_MASK)
#define USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN_MASK (0x10000000U)
#define USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN_SHIFT (28U)
#define USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_DP_VDAT_REF_RISE_INT_EN_MASK)
#define USB3_OTGIEN_DCD_COMP_RISE_INT_EN_MASK    (0x20000000U)
#define USB3_OTGIEN_DCD_COMP_RISE_INT_EN_SHIFT   (29U)
#define USB3_OTGIEN_DCD_COMP_RISE_INT_EN(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DCD_COMP_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_DCD_COMP_RISE_INT_EN_MASK)
#define USB3_OTGIEN_DCD_COMP_FALL_INT_EN_MASK    (0x40000000U)
#define USB3_OTGIEN_DCD_COMP_FALL_INT_EN_SHIFT   (30U)
#define USB3_OTGIEN_DCD_COMP_FALL_INT_EN(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DCD_COMP_FALL_INT_EN_SHIFT)) & USB3_OTGIEN_DCD_COMP_FALL_INT_EN_MASK)
#define USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN_MASK (0x80000000U)
#define USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN_SHIFT (31U)
#define USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN_SHIFT)) & USB3_OTGIEN_DM_VLGC_COMP_RISE_INT_EN_MASK)
/*! @} */

/*! @name OTGIVECT - OTG Interrupt Vector */
/*! @{ */
#define USB3_OTGIVECT_ID_CHANGE_INT_MASK         (0x1U)
#define USB3_OTGIVECT_ID_CHANGE_INT_SHIFT        (0U)
#define USB3_OTGIVECT_ID_CHANGE_INT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_ID_CHANGE_INT_SHIFT)) & USB3_OTGIVECT_ID_CHANGE_INT_MASK)
#define USB3_OTGIVECT_VBUS_ON_FAILED_INT_MASK    (0x2U)
#define USB3_OTGIVECT_VBUS_ON_FAILED_INT_SHIFT   (1U)
#define USB3_OTGIVECT_VBUS_ON_FAILED_INT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_VBUS_ON_FAILED_INT_SHIFT)) & USB3_OTGIVECT_VBUS_ON_FAILED_INT_MASK)
#define USB3_OTGIVECT_OTGSESSVALID_RISE_INT_MASK (0x4U)
#define USB3_OTGIVECT_OTGSESSVALID_RISE_INT_SHIFT (2U)
#define USB3_OTGIVECT_OTGSESSVALID_RISE_INT(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_OTGSESSVALID_RISE_INT_SHIFT)) & USB3_OTGIVECT_OTGSESSVALID_RISE_INT_MASK)
#define USB3_OTGIVECT_OTGSESSVALID_FALL_INT_MASK (0x8U)
#define USB3_OTGIVECT_OTGSESSVALID_FALL_INT_SHIFT (3U)
#define USB3_OTGIVECT_OTGSESSVALID_FALL_INT(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_OTGSESSVALID_FALL_INT_SHIFT)) & USB3_OTGIVECT_OTGSESSVALID_FALL_INT_MASK)
#define USB3_OTGIVECT_VBUSVALID_RISE_INT_MASK    (0x10U)
#define USB3_OTGIVECT_VBUSVALID_RISE_INT_SHIFT   (4U)
#define USB3_OTGIVECT_VBUSVALID_RISE_INT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_VBUSVALID_RISE_INT_SHIFT)) & USB3_OTGIVECT_VBUSVALID_RISE_INT_MASK)
#define USB3_OTGIVECT_VBUSVALID_FALL_INT_MASK    (0x20U)
#define USB3_OTGIVECT_VBUSVALID_FALL_INT_SHIFT   (5U)
#define USB3_OTGIVECT_VBUSVALID_FALL_INT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_VBUSVALID_FALL_INT_SHIFT)) & USB3_OTGIVECT_VBUSVALID_FALL_INT_MASK)
#define USB3_OTGIVECT_SENSE_RISE_INT_MASK        (0x40U)
#define USB3_OTGIVECT_SENSE_RISE_INT_SHIFT       (6U)
#define USB3_OTGIVECT_SENSE_RISE_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SENSE_RISE_INT_SHIFT)) & USB3_OTGIVECT_SENSE_RISE_INT_MASK)
#define USB3_OTGIVECT_PROBE_RISE_INT_MASK        (0x80U)
#define USB3_OTGIVECT_PROBE_RISE_INT_SHIFT       (7U)
#define USB3_OTGIVECT_PROBE_RISE_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_PROBE_RISE_INT_SHIFT)) & USB3_OTGIVECT_PROBE_RISE_INT_MASK)
#define USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT_MASK (0x100U)
#define USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT_SHIFT (8U)
#define USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT_SHIFT)) & USB3_OTGIVECT_ADP_PROBE_COMPLETED_INT_MASK)
#define USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT_MASK (0x200U)
#define USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT_SHIFT (9U)
#define USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TA_AIDL_BDIS_TMOUT_INT_MASK)
#define USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT_MASK (0x400U)
#define USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT_SHIFT (10U)
#define USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TA_BIDL_ADIS_TMOUT_INT_MASK)
#define USB3_OTGIVECT_SRP_DET_INT_MASK           (0x800U)
#define USB3_OTGIVECT_SRP_DET_INT_SHIFT          (11U)
#define USB3_OTGIVECT_SRP_DET_INT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SRP_DET_INT_SHIFT)) & USB3_OTGIVECT_SRP_DET_INT_MASK)
#define USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT_MASK (0x1000U)
#define USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT_SHIFT (12U)
#define USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT_SHIFT)) & USB3_OTGIVECT_SRP_NOT_COMP_DEV_REMOVED_INT_MASK)
#define USB3_OTGIVECT_OVERCURRENT_INT_MASK       (0x2000U)
#define USB3_OTGIVECT_OVERCURRENT_INT_SHIFT      (13U)
#define USB3_OTGIVECT_OVERCURRENT_INT(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_OVERCURRENT_INT_SHIFT)) & USB3_OTGIVECT_OVERCURRENT_INT_MASK)
#define USB3_OTGIVECT_SRP_FAIL_INT_MASK          (0x4000U)
#define USB3_OTGIVECT_SRP_FAIL_INT_SHIFT         (14U)
#define USB3_OTGIVECT_SRP_FAIL_INT(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SRP_FAIL_INT_SHIFT)) & USB3_OTGIVECT_SRP_FAIL_INT_MASK)
#define USB3_OTGIVECT_SRP_CMPL_INT_MASK          (0x8000U)
#define USB3_OTGIVECT_SRP_CMPL_INT_SHIFT         (15U)
#define USB3_OTGIVECT_SRP_CMPL_INT(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_SRP_CMPL_INT_SHIFT)) & USB3_OTGIVECT_SRP_CMPL_INT_MASK)
#define USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT_MASK (0x10000U)
#define USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT_SHIFT (16U)
#define USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TB_ASE0_BRST_TMOUT_INT_MASK)
#define USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT_MASK (0x20000U)
#define USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT_SHIFT (17U)
#define USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT(x) (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TB_AIDL_BDIS_MIN_TMOUT_INT_MASK)
#define USB3_OTGIVECT_TIMER_TMOUT_INT_MASK       (0x40000U)
#define USB3_OTGIVECT_TIMER_TMOUT_INT_SHIFT      (18U)
#define USB3_OTGIVECT_TIMER_TMOUT_INT(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_TIMER_TMOUT_INT_SHIFT)) & USB3_OTGIVECT_TIMER_TMOUT_INT_MASK)
#define USB3_OTGIVECT_H_POLLTRY_INT_MASK         (0x80000U)
#define USB3_OTGIVECT_H_POLLTRY_INT_SHIFT        (19U)
#define USB3_OTGIVECT_H_POLLTRY_INT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_H_POLLTRY_INT_SHIFT)) & USB3_OTGIVECT_H_POLLTRY_INT_MASK)
#define USB3_OTGIVECT_H_WRST_GEN_CMPL_INT_MASK   (0x100000U)
#define USB3_OTGIVECT_H_WRST_GEN_CMPL_INT_SHIFT  (20U)
#define USB3_OTGIVECT_H_WRST_GEN_CMPL_INT(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_H_WRST_GEN_CMPL_INT_SHIFT)) & USB3_OTGIVECT_H_WRST_GEN_CMPL_INT_MASK)
#define USB3_OTGIVECT_RID_FLOAT_FALL_INT_MASK    (0x200000U)
#define USB3_OTGIVECT_RID_FLOAT_FALL_INT_SHIFT   (21U)
#define USB3_OTGIVECT_RID_FLOAT_FALL_INT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_FLOAT_FALL_INT_SHIFT)) & USB3_OTGIVECT_RID_FLOAT_FALL_INT_MASK)
#define USB3_OTGIVECT_RID_FLOAT_RISE_INT_MASK    (0x400000U)
#define USB3_OTGIVECT_RID_FLOAT_RISE_INT_SHIFT   (22U)
#define USB3_OTGIVECT_RID_FLOAT_RISE_INT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_FLOAT_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_FLOAT_RISE_INT_MASK)
#define USB3_OTGIVECT_RID_GND_RISE_INT_MASK      (0x800000U)
#define USB3_OTGIVECT_RID_GND_RISE_INT_SHIFT     (23U)
#define USB3_OTGIVECT_RID_GND_RISE_INT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_GND_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_GND_RISE_INT_MASK)
#define USB3_OTGIVECT_RID_C_RISE_INT_MASK        (0x1000000U)
#define USB3_OTGIVECT_RID_C_RISE_INT_SHIFT       (24U)
#define USB3_OTGIVECT_RID_C_RISE_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_C_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_C_RISE_INT_MASK)
#define USB3_OTGIVECT_RID_B_RISE_INT_MASK        (0x2000000U)
#define USB3_OTGIVECT_RID_B_RISE_INT_SHIFT       (25U)
#define USB3_OTGIVECT_RID_B_RISE_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_B_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_B_RISE_INT_MASK)
#define USB3_OTGIVECT_RID_A_RISE_INT_MASK        (0x4000000U)
#define USB3_OTGIVECT_RID_A_RISE_INT_SHIFT       (26U)
#define USB3_OTGIVECT_RID_A_RISE_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_RID_A_RISE_INT_SHIFT)) & USB3_OTGIVECT_RID_A_RISE_INT_MASK)
#define USB3_OTGIVECT_DM_VDAT_REF_RISE_INT_MASK  (0x8000000U)
#define USB3_OTGIVECT_DM_VDAT_REF_RISE_INT_SHIFT (27U)
#define USB3_OTGIVECT_DM_VDAT_REF_RISE_INT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DM_VDAT_REF_RISE_INT_SHIFT)) & USB3_OTGIVECT_DM_VDAT_REF_RISE_INT_MASK)
#define USB3_OTGIVECT_DP_VDAT_REF_RISE_INT_MASK  (0x10000000U)
#define USB3_OTGIVECT_DP_VDAT_REF_RISE_INT_SHIFT (28U)
#define USB3_OTGIVECT_DP_VDAT_REF_RISE_INT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DP_VDAT_REF_RISE_INT_SHIFT)) & USB3_OTGIVECT_DP_VDAT_REF_RISE_INT_MASK)
#define USB3_OTGIVECT_DCD_COMP_RISE_INT_MASK     (0x20000000U)
#define USB3_OTGIVECT_DCD_COMP_RISE_INT_SHIFT    (29U)
#define USB3_OTGIVECT_DCD_COMP_RISE_INT(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DCD_COMP_RISE_INT_SHIFT)) & USB3_OTGIVECT_DCD_COMP_RISE_INT_MASK)
#define USB3_OTGIVECT_DCD_COMP_FALL_INT_MASK     (0x40000000U)
#define USB3_OTGIVECT_DCD_COMP_FALL_INT_SHIFT    (30U)
#define USB3_OTGIVECT_DCD_COMP_FALL_INT(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DCD_COMP_FALL_INT_SHIFT)) & USB3_OTGIVECT_DCD_COMP_FALL_INT_MASK)
#define USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT_MASK (0x80000000U)
#define USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT_SHIFT (31U)
#define USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT_SHIFT)) & USB3_OTGIVECT_DM_VLGC_COMP_RISE_INT_MASK)
/*! @} */

/*! @name CLK_FREQ - Clock Frequency */
/*! @{ */
#define USB3_CLK_FREQ_CLK_FREQ_MHZ_MASK          (0xFFFFU)
#define USB3_CLK_FREQ_CLK_FREQ_MHZ_SHIFT         (0U)
#define USB3_CLK_FREQ_CLK_FREQ_MHZ(x)            (((uint32_t)(((uint32_t)(x)) << USB3_CLK_FREQ_CLK_FREQ_MHZ_SHIFT)) & USB3_CLK_FREQ_CLK_FREQ_MHZ_MASK)
#define USB3_CLK_FREQ_CLK_FREQ_KHZ_MASK          (0xFFFF0000U)
#define USB3_CLK_FREQ_CLK_FREQ_KHZ_SHIFT         (16U)
#define USB3_CLK_FREQ_CLK_FREQ_KHZ(x)            (((uint32_t)(((uint32_t)(x)) << USB3_CLK_FREQ_CLK_FREQ_KHZ_SHIFT)) & USB3_CLK_FREQ_CLK_FREQ_KHZ_MASK)
/*! @} */

/*! @name OTGTMR - OTG Timer */
/*! @{ */
#define USB3_OTGTMR_TIMEOUT_VALUE_MASK           (0xFFFFU)
#define USB3_OTGTMR_TIMEOUT_VALUE_SHIFT          (0U)
#define USB3_OTGTMR_TIMEOUT_VALUE(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMEOUT_VALUE_SHIFT)) & USB3_OTGTMR_TIMEOUT_VALUE_MASK)
#define USB3_OTGTMR_TIMEOUT_UNITS_MASK           (0x30000U)
#define USB3_OTGTMR_TIMEOUT_UNITS_SHIFT          (16U)
/*! TIMEOUT_UNITS - Time units
 *  0b00..hundreds of microseconds (valid only if otg controller clock is in MHz range)
 *  0b01..milliseconds
 *  0b10..tens of milliseconds
 *  0b11..hundreds of milliseconds, Valid only if TIMER_WRITE is 1
 */
#define USB3_OTGTMR_TIMEOUT_UNITS(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMEOUT_UNITS_SHIFT)) & USB3_OTGTMR_TIMEOUT_UNITS_MASK)
#define USB3_OTGTMR_TIMER_WRITE_MASK             (0x40000U)
#define USB3_OTGTMR_TIMER_WRITE_SHIFT            (18U)
#define USB3_OTGTMR_TIMER_WRITE(x)               (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMER_WRITE_SHIFT)) & USB3_OTGTMR_TIMER_WRITE_MASK)
#define USB3_OTGTMR_TIMER_START_MASK             (0x80000U)
#define USB3_OTGTMR_TIMER_START_SHIFT            (19U)
#define USB3_OTGTMR_TIMER_START(x)               (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMER_START_SHIFT)) & USB3_OTGTMR_TIMER_START_MASK)
#define USB3_OTGTMR_TIMER_STOP_MASK              (0x100000U)
#define USB3_OTGTMR_TIMER_STOP_SHIFT             (20U)
#define USB3_OTGTMR_TIMER_STOP(x)                (((uint32_t)(((uint32_t)(x)) << USB3_OTGTMR_TIMER_STOP_SHIFT)) & USB3_OTGTMR_TIMER_STOP_MASK)
/*! @} */

/*! @name OTGVERSION - OTG Version */
/*! @{ */
#define USB3_OTGVERSION_OTGVERSION_MASK          (0xFFFFU)
#define USB3_OTGVERSION_OTGVERSION_SHIFT         (0U)
#define USB3_OTGVERSION_OTGVERSION(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGVERSION_OTGVERSION_SHIFT)) & USB3_OTGVERSION_OTGVERSION_MASK)
/*! @} */

/*! @name OTGCAPABILITY - OTG Capability */
/*! @{ */
#define USB3_OTGCAPABILITY_SRP_SUPPORT_MASK      (0x1U)
#define USB3_OTGCAPABILITY_SRP_SUPPORT_SHIFT     (0U)
#define USB3_OTGCAPABILITY_SRP_SUPPORT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_SRP_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_SRP_SUPPORT_MASK)
#define USB3_OTGCAPABILITY_HNP_SUPPORT_MASK      (0x2U)
#define USB3_OTGCAPABILITY_HNP_SUPPORT_SHIFT     (1U)
#define USB3_OTGCAPABILITY_HNP_SUPPORT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_HNP_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_HNP_SUPPORT_MASK)
#define USB3_OTGCAPABILITY_ADP_SUPPORT_MASK      (0x4U)
#define USB3_OTGCAPABILITY_ADP_SUPPORT_SHIFT     (2U)
#define USB3_OTGCAPABILITY_ADP_SUPPORT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_ADP_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_ADP_SUPPORT_MASK)
#define USB3_OTGCAPABILITY_BC_SUPPORT_MASK       (0x8U)
#define USB3_OTGCAPABILITY_BC_SUPPORT_SHIFT      (3U)
#define USB3_OTGCAPABILITY_BC_SUPPORT(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_BC_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_BC_SUPPORT_MASK)
#define USB3_OTGCAPABILITY_RSP_SUPPORT_MASK      (0x10U)
#define USB3_OTGCAPABILITY_RSP_SUPPORT_SHIFT     (4U)
#define USB3_OTGCAPABILITY_RSP_SUPPORT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_RSP_SUPPORT_SHIFT)) & USB3_OTGCAPABILITY_RSP_SUPPORT_MASK)
#define USB3_OTGCAPABILITY_OTG2REVISION_MASK     (0xFFF00U)
#define USB3_OTGCAPABILITY_OTG2REVISION_SHIFT    (8U)
#define USB3_OTGCAPABILITY_OTG2REVISION(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_OTG2REVISION_SHIFT)) & USB3_OTGCAPABILITY_OTG2REVISION_MASK)
#define USB3_OTGCAPABILITY_OTG3REVISION_MASK     (0xFFF00000U)
#define USB3_OTGCAPABILITY_OTG3REVISION_SHIFT    (20U)
#define USB3_OTGCAPABILITY_OTG3REVISION(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCAPABILITY_OTG3REVISION_SHIFT)) & USB3_OTGCAPABILITY_OTG3REVISION_MASK)
/*! @} */

/*! @name OTGSIMULATE - OTG Simulate */
/*! @{ */
#define USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS_MASK  (0x1U)
#define USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS_SHIFT (0U)
#define USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS_SHIFT)) & USB3_OTGSIMULATE_OTG_CFG_FAST_SIMS_MASK)
/*! @} */

/*! @name OTGANASTS - OTG Attach Detection Protocol BC Status */
/*! @{ */
#define USB3_OTGANASTS_dp_vdat_ref_comp_sts_MASK (0x1U)
#define USB3_OTGANASTS_dp_vdat_ref_comp_sts_SHIFT (0U)
#define USB3_OTGANASTS_dp_vdat_ref_comp_sts(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_dp_vdat_ref_comp_sts_SHIFT)) & USB3_OTGANASTS_dp_vdat_ref_comp_sts_MASK)
#define USB3_OTGANASTS_dm_vdat_ref_comp_sts_MASK (0x2U)
#define USB3_OTGANASTS_dm_vdat_ref_comp_sts_SHIFT (1U)
#define USB3_OTGANASTS_dm_vdat_ref_comp_sts(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_dm_vdat_ref_comp_sts_SHIFT)) & USB3_OTGANASTS_dm_vdat_ref_comp_sts_MASK)
#define USB3_OTGANASTS_dm_vlgc_comp_sts_MASK     (0x4U)
#define USB3_OTGANASTS_dm_vlgc_comp_sts_SHIFT    (2U)
#define USB3_OTGANASTS_dm_vlgc_comp_sts(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_dm_vlgc_comp_sts_SHIFT)) & USB3_OTGANASTS_dm_vlgc_comp_sts_MASK)
#define USB3_OTGANASTS_dcd_comp_sts_MASK         (0x8U)
#define USB3_OTGANASTS_dcd_comp_sts_SHIFT        (3U)
#define USB3_OTGANASTS_dcd_comp_sts(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_dcd_comp_sts_SHIFT)) & USB3_OTGANASTS_dcd_comp_sts_MASK)
#define USB3_OTGANASTS_otgsessvalid_MASK         (0x10U)
#define USB3_OTGANASTS_otgsessvalid_SHIFT        (4U)
#define USB3_OTGANASTS_otgsessvalid(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_otgsessvalid_SHIFT)) & USB3_OTGANASTS_otgsessvalid_MASK)
#define USB3_OTGANASTS_adp_probe_ana_MASK        (0x20U)
#define USB3_OTGANASTS_adp_probe_ana_SHIFT       (5U)
#define USB3_OTGANASTS_adp_probe_ana(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_adp_probe_ana_SHIFT)) & USB3_OTGANASTS_adp_probe_ana_MASK)
#define USB3_OTGANASTS_adp_sense_ana_MASK        (0x40U)
#define USB3_OTGANASTS_adp_sense_ana_SHIFT       (6U)
#define USB3_OTGANASTS_adp_sense_ana(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_adp_sense_ana_SHIFT)) & USB3_OTGANASTS_adp_sense_ana_MASK)
#define USB3_OTGANASTS_sessend_MASK              (0x80U)
#define USB3_OTGANASTS_sessend_SHIFT             (7U)
#define USB3_OTGANASTS_sessend(x)                (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_sessend_SHIFT)) & USB3_OTGANASTS_sessend_MASK)
#define USB3_OTGANASTS_rid_float_comp_sts_MASK   (0x100U)
#define USB3_OTGANASTS_rid_float_comp_sts_SHIFT  (8U)
#define USB3_OTGANASTS_rid_float_comp_sts(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_float_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_float_comp_sts_MASK)
#define USB3_OTGANASTS_rid_gnd_comp_sts_MASK     (0x200U)
#define USB3_OTGANASTS_rid_gnd_comp_sts_SHIFT    (9U)
#define USB3_OTGANASTS_rid_gnd_comp_sts(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_gnd_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_gnd_comp_sts_MASK)
#define USB3_OTGANASTS_rid_c_comp_sts_MASK       (0x400U)
#define USB3_OTGANASTS_rid_c_comp_sts_SHIFT      (10U)
#define USB3_OTGANASTS_rid_c_comp_sts(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_c_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_c_comp_sts_MASK)
#define USB3_OTGANASTS_rid_b_comp_sts_MASK       (0x800U)
#define USB3_OTGANASTS_rid_b_comp_sts_SHIFT      (11U)
#define USB3_OTGANASTS_rid_b_comp_sts(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_b_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_b_comp_sts_MASK)
#define USB3_OTGANASTS_rid_a_comp_sts_MASK       (0x1000U)
#define USB3_OTGANASTS_rid_a_comp_sts_SHIFT      (12U)
#define USB3_OTGANASTS_rid_a_comp_sts(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_a_comp_sts_SHIFT)) & USB3_OTGANASTS_rid_a_comp_sts_MASK)
#define USB3_OTGANASTS_iddig_MASK                (0x2000U)
#define USB3_OTGANASTS_iddig_SHIFT               (13U)
#define USB3_OTGANASTS_iddig(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_iddig_SHIFT)) & USB3_OTGANASTS_iddig_MASK)
#define USB3_OTGANASTS_linestate_MASK            (0xC000U)
#define USB3_OTGANASTS_linestate_SHIFT           (14U)
#define USB3_OTGANASTS_linestate(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_linestate_SHIFT)) & USB3_OTGANASTS_linestate_MASK)
#define USB3_OTGANASTS_rid_float_MASK            (0x10000U)
#define USB3_OTGANASTS_rid_float_SHIFT           (16U)
#define USB3_OTGANASTS_rid_float(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_float_SHIFT)) & USB3_OTGANASTS_rid_float_MASK)
#define USB3_OTGANASTS_rid_gnd_MASK              (0x20000U)
#define USB3_OTGANASTS_rid_gnd_SHIFT             (17U)
#define USB3_OTGANASTS_rid_gnd(x)                (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_gnd_SHIFT)) & USB3_OTGANASTS_rid_gnd_MASK)
#define USB3_OTGANASTS_rid_c_MASK                (0x40000U)
#define USB3_OTGANASTS_rid_c_SHIFT               (18U)
#define USB3_OTGANASTS_rid_c(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_c_SHIFT)) & USB3_OTGANASTS_rid_c_MASK)
#define USB3_OTGANASTS_rid_b_MASK                (0x80000U)
#define USB3_OTGANASTS_rid_b_SHIFT               (19U)
#define USB3_OTGANASTS_rid_b(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_b_SHIFT)) & USB3_OTGANASTS_rid_b_MASK)
#define USB3_OTGANASTS_rid_a_MASK                (0x100000U)
#define USB3_OTGANASTS_rid_a_SHIFT               (20U)
#define USB3_OTGANASTS_rid_a(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_rid_a_SHIFT)) & USB3_OTGANASTS_rid_a_MASK)
#define USB3_OTGANASTS_adp_chrg_tmout_det_MASK   (0x1000000U)
#define USB3_OTGANASTS_adp_chrg_tmout_det_SHIFT  (24U)
#define USB3_OTGANASTS_adp_chrg_tmout_det(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGANASTS_adp_chrg_tmout_det_SHIFT)) & USB3_OTGANASTS_adp_chrg_tmout_det_MASK)
/*! @} */

/*! @name ADP_RAMP_TIME - Attach Detection Protocol Ramp Time */
/*! @{ */
#define USB3_ADP_RAMP_TIME_ADP_RAMP_TIME_MASK    (0xFFFFFFFFU)
#define USB3_ADP_RAMP_TIME_ADP_RAMP_TIME_SHIFT   (0U)
#define USB3_ADP_RAMP_TIME_ADP_RAMP_TIME(x)      (((uint32_t)(((uint32_t)(x)) << USB3_ADP_RAMP_TIME_ADP_RAMP_TIME_SHIFT)) & USB3_ADP_RAMP_TIME_ADP_RAMP_TIME_MASK)
/*! @} */

/*! @name OTGCTRL1 - OTG Control */
/*! @{ */
#define USB3_OTGCTRL1_adp_en_MASK                (0x1U)
#define USB3_OTGCTRL1_adp_en_SHIFT               (0U)
#define USB3_OTGCTRL1_adp_en(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_en_SHIFT)) & USB3_OTGCTRL1_adp_en_MASK)
#define USB3_OTGCTRL1_adp_probe_en_MASK          (0x2U)
#define USB3_OTGCTRL1_adp_probe_en_SHIFT         (1U)
#define USB3_OTGCTRL1_adp_probe_en(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_probe_en_SHIFT)) & USB3_OTGCTRL1_adp_probe_en_MASK)
#define USB3_OTGCTRL1_adp_sense_en_MASK          (0x4U)
#define USB3_OTGCTRL1_adp_sense_en_SHIFT         (2U)
#define USB3_OTGCTRL1_adp_sense_en(x)            (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_sense_en_SHIFT)) & USB3_OTGCTRL1_adp_sense_en_MASK)
#define USB3_OTGCTRL1_adp_sink_current_en_MASK   (0x8U)
#define USB3_OTGCTRL1_adp_sink_current_en_SHIFT  (3U)
#define USB3_OTGCTRL1_adp_sink_current_en(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_sink_current_en_SHIFT)) & USB3_OTGCTRL1_adp_sink_current_en_MASK)
#define USB3_OTGCTRL1_adp_source_current_en_MASK (0x10U)
#define USB3_OTGCTRL1_adp_source_current_en_SHIFT (4U)
#define USB3_OTGCTRL1_adp_source_current_en(x)   (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_source_current_en_SHIFT)) & USB3_OTGCTRL1_adp_source_current_en_MASK)
#define USB3_OTGCTRL1_do_adp_prb_MASK            (0x20U)
#define USB3_OTGCTRL1_do_adp_prb_SHIFT           (5U)
#define USB3_OTGCTRL1_do_adp_prb(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_do_adp_prb_SHIFT)) & USB3_OTGCTRL1_do_adp_prb_MASK)
#define USB3_OTGCTRL1_do_adp_sns_MASK            (0x40U)
#define USB3_OTGCTRL1_do_adp_sns_SHIFT           (6U)
#define USB3_OTGCTRL1_do_adp_sns(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_do_adp_sns_SHIFT)) & USB3_OTGCTRL1_do_adp_sns_MASK)
#define USB3_OTGCTRL1_adp_auto_MASK              (0x80U)
#define USB3_OTGCTRL1_adp_auto_SHIFT             (7U)
#define USB3_OTGCTRL1_adp_auto(x)                (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_adp_auto_SHIFT)) & USB3_OTGCTRL1_adp_auto_MASK)
#define USB3_OTGCTRL1_bc_en_MASK                 (0x100U)
#define USB3_OTGCTRL1_bc_en_SHIFT                (8U)
#define USB3_OTGCTRL1_bc_en(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_bc_en_SHIFT)) & USB3_OTGCTRL1_bc_en_MASK)
#define USB3_OTGCTRL1_idm_sink_en_MASK           (0x200U)
#define USB3_OTGCTRL1_idm_sink_en_SHIFT          (9U)
#define USB3_OTGCTRL1_idm_sink_en(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_idm_sink_en_SHIFT)) & USB3_OTGCTRL1_idm_sink_en_MASK)
#define USB3_OTGCTRL1_idp_sink_en_MASK           (0x400U)
#define USB3_OTGCTRL1_idp_sink_en_SHIFT          (10U)
#define USB3_OTGCTRL1_idp_sink_en(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_idp_sink_en_SHIFT)) & USB3_OTGCTRL1_idp_sink_en_MASK)
#define USB3_OTGCTRL1_idp_src_en_MASK            (0x800U)
#define USB3_OTGCTRL1_idp_src_en_SHIFT           (11U)
#define USB3_OTGCTRL1_idp_src_en(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_idp_src_en_SHIFT)) & USB3_OTGCTRL1_idp_src_en_MASK)
#define USB3_OTGCTRL1_vdm_src_en_MASK            (0x1000U)
#define USB3_OTGCTRL1_vdm_src_en_SHIFT           (12U)
#define USB3_OTGCTRL1_vdm_src_en(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_vdm_src_en_SHIFT)) & USB3_OTGCTRL1_vdm_src_en_MASK)
#define USB3_OTGCTRL1_vdp_src_en_MASK            (0x2000U)
#define USB3_OTGCTRL1_vdp_src_en_SHIFT           (13U)
#define USB3_OTGCTRL1_vdp_src_en(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_vdp_src_en_SHIFT)) & USB3_OTGCTRL1_vdp_src_en_MASK)
#define USB3_OTGCTRL1_dm_vdat_ref_comp_en_MASK   (0x10000U)
#define USB3_OTGCTRL1_dm_vdat_ref_comp_en_SHIFT  (16U)
#define USB3_OTGCTRL1_dm_vdat_ref_comp_en(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_dm_vdat_ref_comp_en_SHIFT)) & USB3_OTGCTRL1_dm_vdat_ref_comp_en_MASK)
#define USB3_OTGCTRL1_dm_vlgc_comp_en_MASK       (0x20000U)
#define USB3_OTGCTRL1_dm_vlgc_comp_en_SHIFT      (17U)
#define USB3_OTGCTRL1_dm_vlgc_comp_en(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_dm_vlgc_comp_en_SHIFT)) & USB3_OTGCTRL1_dm_vlgc_comp_en_MASK)
#define USB3_OTGCTRL1_dp_vdat_ref_comp_en_MASK   (0x40000U)
#define USB3_OTGCTRL1_dp_vdat_ref_comp_en_SHIFT  (18U)
#define USB3_OTGCTRL1_dp_vdat_ref_comp_en(x)     (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_dp_vdat_ref_comp_en_SHIFT)) & USB3_OTGCTRL1_dp_vdat_ref_comp_en_MASK)
#define USB3_OTGCTRL1_rid_float_comp_en_MASK     (0x80000U)
#define USB3_OTGCTRL1_rid_float_comp_en_SHIFT    (19U)
#define USB3_OTGCTRL1_rid_float_comp_en(x)       (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_rid_float_comp_en_SHIFT)) & USB3_OTGCTRL1_rid_float_comp_en_MASK)
#define USB3_OTGCTRL1_rid_nonfloat_comp_en_MASK  (0x100000U)
#define USB3_OTGCTRL1_rid_nonfloat_comp_en_SHIFT (20U)
#define USB3_OTGCTRL1_rid_nonfloat_comp_en(x)    (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_rid_nonfloat_comp_en_SHIFT)) & USB3_OTGCTRL1_rid_nonfloat_comp_en_MASK)
#define USB3_OTGCTRL1_bc_dmpulldown_MASK         (0x200000U)
#define USB3_OTGCTRL1_bc_dmpulldown_SHIFT        (21U)
#define USB3_OTGCTRL1_bc_dmpulldown(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_bc_dmpulldown_SHIFT)) & USB3_OTGCTRL1_bc_dmpulldown_MASK)
#define USB3_OTGCTRL1_bc_dppulldown_MASK         (0x400000U)
#define USB3_OTGCTRL1_bc_dppulldown_SHIFT        (22U)
#define USB3_OTGCTRL1_bc_dppulldown(x)           (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_bc_dppulldown_SHIFT)) & USB3_OTGCTRL1_bc_dppulldown_MASK)
#define USB3_OTGCTRL1_bc_pulldownctrl_MASK       (0x800000U)
#define USB3_OTGCTRL1_bc_pulldownctrl_SHIFT      (23U)
#define USB3_OTGCTRL1_bc_pulldownctrl(x)         (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_bc_pulldownctrl_SHIFT)) & USB3_OTGCTRL1_bc_pulldownctrl_MASK)
#define USB3_OTGCTRL1_idpullup_MASK              (0x1000000U)
#define USB3_OTGCTRL1_idpullup_SHIFT             (24U)
#define USB3_OTGCTRL1_idpullup(x)                (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_idpullup_SHIFT)) & USB3_OTGCTRL1_idpullup_MASK)
#define USB3_OTGCTRL1_drive_vbus_sel_MASK        (0x2000000U)
#define USB3_OTGCTRL1_drive_vbus_sel_SHIFT       (25U)
#define USB3_OTGCTRL1_drive_vbus_sel(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_drive_vbus_sel_SHIFT)) & USB3_OTGCTRL1_drive_vbus_sel_MASK)
#define USB3_OTGCTRL1_drive_vbus_sfr_MASK        (0x4000000U)
#define USB3_OTGCTRL1_drive_vbus_sfr_SHIFT       (26U)
#define USB3_OTGCTRL1_drive_vbus_sfr(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_drive_vbus_sfr_SHIFT)) & USB3_OTGCTRL1_drive_vbus_sfr_MASK)
#define USB3_OTGCTRL1_force_opmode01_MASK        (0x8000000U)
#define USB3_OTGCTRL1_force_opmode01_SHIFT       (27U)
#define USB3_OTGCTRL1_force_opmode01(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL1_force_opmode01_SHIFT)) & USB3_OTGCTRL1_force_opmode01_MASK)
/*! @} */

/*! @name OTGCTRL2 - OTG Control */
/*! @{ */
#define USB3_OTGCTRL2_TA_ADP_PRB_MASK            (0xFFU)
#define USB3_OTGCTRL2_TA_ADP_PRB_SHIFT           (0U)
#define USB3_OTGCTRL2_TA_ADP_PRB(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL2_TA_ADP_PRB_SHIFT)) & USB3_OTGCTRL2_TA_ADP_PRB_MASK)
#define USB3_OTGCTRL2_TB_ADP_PRB_MASK            (0xFF00U)
#define USB3_OTGCTRL2_TB_ADP_PRB_SHIFT           (8U)
#define USB3_OTGCTRL2_TB_ADP_PRB(x)              (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL2_TB_ADP_PRB_SHIFT)) & USB3_OTGCTRL2_TB_ADP_PRB_MASK)
#define USB3_OTGCTRL2_ADP_CHRG_TMOUT_MASK        (0xFF0000U)
#define USB3_OTGCTRL2_ADP_CHRG_TMOUT_SHIFT       (16U)
#define USB3_OTGCTRL2_ADP_CHRG_TMOUT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL2_ADP_CHRG_TMOUT_SHIFT)) & USB3_OTGCTRL2_ADP_CHRG_TMOUT_MASK)
#define USB3_OTGCTRL2_T_ADP_DSCHG_MASK           (0xFF000000U)
#define USB3_OTGCTRL2_T_ADP_DSCHG_SHIFT          (24U)
#define USB3_OTGCTRL2_T_ADP_DSCHG(x)             (((uint32_t)(((uint32_t)(x)) << USB3_OTGCTRL2_T_ADP_DSCHG_SHIFT)) & USB3_OTGCTRL2_T_ADP_DSCHG_MASK)
/*! @} */

/*! @name HCIVERSION_CAPLENGTH - HCI Version and CAPLENGTH */
/*! @{ */
#define USB3_HCIVERSION_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
#define USB3_HCIVERSION_CAPLENGTH_CAPLENGTH_SHIFT (0U)
#define USB3_HCIVERSION_CAPLENGTH_CAPLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USB3_HCIVERSION_CAPLENGTH_CAPLENGTH_SHIFT)) & USB3_HCIVERSION_CAPLENGTH_CAPLENGTH_MASK)
#define USB3_HCIVERSION_CAPLENGTH_HCIVERSION_MASK (0xFFFF0000U)
#define USB3_HCIVERSION_CAPLENGTH_HCIVERSION_SHIFT (16U)
#define USB3_HCIVERSION_CAPLENGTH_HCIVERSION(x)  (((uint32_t)(((uint32_t)(x)) << USB3_HCIVERSION_CAPLENGTH_HCIVERSION_SHIFT)) & USB3_HCIVERSION_CAPLENGTH_HCIVERSION_MASK)
/*! @} */

/*! @name HCSPARAMS1 - Structural Parameters 1 */
/*! @{ */
#define USB3_HCSPARAMS1_MaxSlots_MASK            (0xFFU)
#define USB3_HCSPARAMS1_MaxSlots_SHIFT           (0U)
#define USB3_HCSPARAMS1_MaxSlots(x)              (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS1_MaxSlots_SHIFT)) & USB3_HCSPARAMS1_MaxSlots_MASK)
#define USB3_HCSPARAMS1_MaxIntrs_MASK            (0x7FF00U)
#define USB3_HCSPARAMS1_MaxIntrs_SHIFT           (8U)
#define USB3_HCSPARAMS1_MaxIntrs(x)              (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS1_MaxIntrs_SHIFT)) & USB3_HCSPARAMS1_MaxIntrs_MASK)
#define USB3_HCSPARAMS1_MaxPorts_MASK            (0xFF000000U)
#define USB3_HCSPARAMS1_MaxPorts_SHIFT           (24U)
#define USB3_HCSPARAMS1_MaxPorts(x)              (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS1_MaxPorts_SHIFT)) & USB3_HCSPARAMS1_MaxPorts_MASK)
/*! @} */

/*! @name HCSPARAMS2 - Structural Parameters 2 */
/*! @{ */
#define USB3_HCSPARAMS2_IST_MASK                 (0xFU)
#define USB3_HCSPARAMS2_IST_SHIFT                (0U)
#define USB3_HCSPARAMS2_IST(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_IST_SHIFT)) & USB3_HCSPARAMS2_IST_MASK)
#define USB3_HCSPARAMS2_ERSTMax_MASK             (0xF0U)
#define USB3_HCSPARAMS2_ERSTMax_SHIFT            (4U)
#define USB3_HCSPARAMS2_ERSTMax(x)               (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_ERSTMax_SHIFT)) & USB3_HCSPARAMS2_ERSTMax_MASK)
#define USB3_HCSPARAMS2_MaxSPBufHi_MASK          (0x3E00000U)
#define USB3_HCSPARAMS2_MaxSPBufHi_SHIFT         (21U)
#define USB3_HCSPARAMS2_MaxSPBufHi(x)            (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_MaxSPBufHi_SHIFT)) & USB3_HCSPARAMS2_MaxSPBufHi_MASK)
#define USB3_HCSPARAMS2_SPR_MASK                 (0x4000000U)
#define USB3_HCSPARAMS2_SPR_SHIFT                (26U)
#define USB3_HCSPARAMS2_SPR(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_SPR_SHIFT)) & USB3_HCSPARAMS2_SPR_MASK)
#define USB3_HCSPARAMS2_MaxSPBufLo_MASK          (0xF8000000U)
#define USB3_HCSPARAMS2_MaxSPBufLo_SHIFT         (27U)
#define USB3_HCSPARAMS2_MaxSPBufLo(x)            (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS2_MaxSPBufLo_SHIFT)) & USB3_HCSPARAMS2_MaxSPBufLo_MASK)
/*! @} */

/*! @name HCSPARAMS3 - Structural Parameters 3 */
/*! @{ */
#define USB3_HCSPARAMS3_U1DevExitLat_MASK        (0xFFU)
#define USB3_HCSPARAMS3_U1DevExitLat_SHIFT       (0U)
#define USB3_HCSPARAMS3_U1DevExitLat(x)          (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS3_U1DevExitLat_SHIFT)) & USB3_HCSPARAMS3_U1DevExitLat_MASK)
#define USB3_HCSPARAMS3_U2DevExitLat_MASK        (0xFFFF0000U)
#define USB3_HCSPARAMS3_U2DevExitLat_SHIFT       (16U)
#define USB3_HCSPARAMS3_U2DevExitLat(x)          (((uint32_t)(((uint32_t)(x)) << USB3_HCSPARAMS3_U2DevExitLat_SHIFT)) & USB3_HCSPARAMS3_U2DevExitLat_MASK)
/*! @} */

/*! @name HCCPARAMS - Capability Parameters */
/*! @{ */
#define USB3_HCCPARAMS_AC64_MASK                 (0x1U)
#define USB3_HCCPARAMS_AC64_SHIFT                (0U)
#define USB3_HCCPARAMS_AC64(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_AC64_SHIFT)) & USB3_HCCPARAMS_AC64_MASK)
#define USB3_HCCPARAMS_BNC_MASK                  (0x2U)
#define USB3_HCCPARAMS_BNC_SHIFT                 (1U)
#define USB3_HCCPARAMS_BNC(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_BNC_SHIFT)) & USB3_HCCPARAMS_BNC_MASK)
#define USB3_HCCPARAMS_CSZ_MASK                  (0x4U)
#define USB3_HCCPARAMS_CSZ_SHIFT                 (2U)
#define USB3_HCCPARAMS_CSZ(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_CSZ_SHIFT)) & USB3_HCCPARAMS_CSZ_MASK)
#define USB3_HCCPARAMS_PPC_MASK                  (0x8U)
#define USB3_HCCPARAMS_PPC_SHIFT                 (3U)
#define USB3_HCCPARAMS_PPC(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_PPC_SHIFT)) & USB3_HCCPARAMS_PPC_MASK)
#define USB3_HCCPARAMS_PIND_MASK                 (0x10U)
#define USB3_HCCPARAMS_PIND_SHIFT                (4U)
#define USB3_HCCPARAMS_PIND(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_PIND_SHIFT)) & USB3_HCCPARAMS_PIND_MASK)
#define USB3_HCCPARAMS_LHRC_MASK                 (0x20U)
#define USB3_HCCPARAMS_LHRC_SHIFT                (5U)
#define USB3_HCCPARAMS_LHRC(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_LHRC_SHIFT)) & USB3_HCCPARAMS_LHRC_MASK)
#define USB3_HCCPARAMS_LTC_MASK                  (0x40U)
#define USB3_HCCPARAMS_LTC_SHIFT                 (6U)
#define USB3_HCCPARAMS_LTC(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_LTC_SHIFT)) & USB3_HCCPARAMS_LTC_MASK)
#define USB3_HCCPARAMS_NSS_MASK                  (0x80U)
#define USB3_HCCPARAMS_NSS_SHIFT                 (7U)
#define USB3_HCCPARAMS_NSS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_NSS_SHIFT)) & USB3_HCCPARAMS_NSS_MASK)
#define USB3_HCCPARAMS_PAE_MASK                  (0x100U)
#define USB3_HCCPARAMS_PAE_SHIFT                 (8U)
#define USB3_HCCPARAMS_PAE(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_PAE_SHIFT)) & USB3_HCCPARAMS_PAE_MASK)
#define USB3_HCCPARAMS_SPC_MASK                  (0x200U)
#define USB3_HCCPARAMS_SPC_SHIFT                 (9U)
#define USB3_HCCPARAMS_SPC(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_SPC_SHIFT)) & USB3_HCCPARAMS_SPC_MASK)
#define USB3_HCCPARAMS_MaxPSASize_MASK           (0xF000U)
#define USB3_HCCPARAMS_MaxPSASize_SHIFT          (12U)
#define USB3_HCCPARAMS_MaxPSASize(x)             (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_MaxPSASize_SHIFT)) & USB3_HCCPARAMS_MaxPSASize_MASK)
#define USB3_HCCPARAMS_xECP_MASK                 (0xFFFF0000U)
#define USB3_HCCPARAMS_xECP_SHIFT                (16U)
#define USB3_HCCPARAMS_xECP(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_HCCPARAMS_xECP_SHIFT)) & USB3_HCCPARAMS_xECP_MASK)
/*! @} */

/*! @name DBOFF - DoorBell Array Offset */
/*! @{ */
#define USB3_DBOFF_DAO_MASK                      (0xFFFFFFFCU)
#define USB3_DBOFF_DAO_SHIFT                     (2U)
#define USB3_DBOFF_DAO(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DBOFF_DAO_SHIFT)) & USB3_DBOFF_DAO_MASK)
/*! @} */

/*! @name RTSOFF - xHCI Runtime Registers Offset */
/*! @{ */
#define USB3_RTSOFF_RRSO_MASK                    (0xFFFFFFE0U)
#define USB3_RTSOFF_RRSO_SHIFT                   (5U)
#define USB3_RTSOFF_RRSO(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_RTSOFF_RRSO_SHIFT)) & USB3_RTSOFF_RRSO_MASK)
/*! @} */

/*! @name USBCMD - USB Command */
/*! @{ */
#define USB3_USBCMD_R_S_MASK                     (0x1U)
#define USB3_USBCMD_R_S_SHIFT                    (0U)
#define USB3_USBCMD_R_S(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_R_S_SHIFT)) & USB3_USBCMD_R_S_MASK)
#define USB3_USBCMD_HCRST_MASK                   (0x2U)
#define USB3_USBCMD_HCRST_SHIFT                  (1U)
#define USB3_USBCMD_HCRST(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_HCRST_SHIFT)) & USB3_USBCMD_HCRST_MASK)
#define USB3_USBCMD_INTE_MASK                    (0x4U)
#define USB3_USBCMD_INTE_SHIFT                   (2U)
#define USB3_USBCMD_INTE(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_INTE_SHIFT)) & USB3_USBCMD_INTE_MASK)
#define USB3_USBCMD_HSEE_MASK                    (0x8U)
#define USB3_USBCMD_HSEE_SHIFT                   (3U)
#define USB3_USBCMD_HSEE(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_HSEE_SHIFT)) & USB3_USBCMD_HSEE_MASK)
#define USB3_USBCMD_LHCRST_MASK                  (0x80U)
#define USB3_USBCMD_LHCRST_SHIFT                 (7U)
#define USB3_USBCMD_LHCRST(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_LHCRST_SHIFT)) & USB3_USBCMD_LHCRST_MASK)
#define USB3_USBCMD_CSS_MASK                     (0x100U)
#define USB3_USBCMD_CSS_SHIFT                    (8U)
#define USB3_USBCMD_CSS(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_CSS_SHIFT)) & USB3_USBCMD_CSS_MASK)
#define USB3_USBCMD_CRS_MASK                     (0x200U)
#define USB3_USBCMD_CRS_SHIFT                    (9U)
#define USB3_USBCMD_CRS(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_CRS_SHIFT)) & USB3_USBCMD_CRS_MASK)
#define USB3_USBCMD_EWE_MASK                     (0x400U)
#define USB3_USBCMD_EWE_SHIFT                    (10U)
#define USB3_USBCMD_EWE(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_EWE_SHIFT)) & USB3_USBCMD_EWE_MASK)
#define USB3_USBCMD_EU3S_MASK                    (0x800U)
#define USB3_USBCMD_EU3S_SHIFT                   (11U)
#define USB3_USBCMD_EU3S(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_USBCMD_EU3S_SHIFT)) & USB3_USBCMD_EU3S_MASK)
/*! @} */

/*! @name USBSTS - USB Status */
/*! @{ */
#define USB3_USBSTS_HCH_MASK                     (0x1U)
#define USB3_USBSTS_HCH_SHIFT                    (0U)
#define USB3_USBSTS_HCH(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_HCH_SHIFT)) & USB3_USBSTS_HCH_MASK)
#define USB3_USBSTS_HSE_MASK                     (0x4U)
#define USB3_USBSTS_HSE_SHIFT                    (2U)
#define USB3_USBSTS_HSE(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_HSE_SHIFT)) & USB3_USBSTS_HSE_MASK)
#define USB3_USBSTS_EINT_MASK                    (0x8U)
#define USB3_USBSTS_EINT_SHIFT                   (3U)
#define USB3_USBSTS_EINT(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_EINT_SHIFT)) & USB3_USBSTS_EINT_MASK)
#define USB3_USBSTS_PCD_MASK                     (0x10U)
#define USB3_USBSTS_PCD_SHIFT                    (4U)
#define USB3_USBSTS_PCD(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_PCD_SHIFT)) & USB3_USBSTS_PCD_MASK)
#define USB3_USBSTS_SSS_MASK                     (0x100U)
#define USB3_USBSTS_SSS_SHIFT                    (8U)
#define USB3_USBSTS_SSS(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_SSS_SHIFT)) & USB3_USBSTS_SSS_MASK)
#define USB3_USBSTS_RSS_MASK                     (0x200U)
#define USB3_USBSTS_RSS_SHIFT                    (9U)
#define USB3_USBSTS_RSS(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_RSS_SHIFT)) & USB3_USBSTS_RSS_MASK)
#define USB3_USBSTS_SRE_MASK                     (0x400U)
#define USB3_USBSTS_SRE_SHIFT                    (10U)
#define USB3_USBSTS_SRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_SRE_SHIFT)) & USB3_USBSTS_SRE_MASK)
#define USB3_USBSTS_CNR_MASK                     (0x800U)
#define USB3_USBSTS_CNR_SHIFT                    (11U)
#define USB3_USBSTS_CNR(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_CNR_SHIFT)) & USB3_USBSTS_CNR_MASK)
#define USB3_USBSTS_HCE_MASK                     (0x1000U)
#define USB3_USBSTS_HCE_SHIFT                    (12U)
#define USB3_USBSTS_HCE(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_USBSTS_HCE_SHIFT)) & USB3_USBSTS_HCE_MASK)
/*! @} */

/*! @name PAGESIZE - Page Size */
/*! @{ */
#define USB3_PAGESIZE_PAGESIZE_MASK              (0xFFFFU)
#define USB3_PAGESIZE_PAGESIZE_SHIFT             (0U)
#define USB3_PAGESIZE_PAGESIZE(x)                (((uint32_t)(((uint32_t)(x)) << USB3_PAGESIZE_PAGESIZE_SHIFT)) & USB3_PAGESIZE_PAGESIZE_MASK)
/*! @} */

/*! @name DNCTRL - Device Notification Control */
/*! @{ */
#define USB3_DNCTRL_N0_MASK                      (0x1U)
#define USB3_DNCTRL_N0_SHIFT                     (0U)
#define USB3_DNCTRL_N0(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N0_SHIFT)) & USB3_DNCTRL_N0_MASK)
#define USB3_DNCTRL_N1_MASK                      (0x2U)
#define USB3_DNCTRL_N1_SHIFT                     (1U)
#define USB3_DNCTRL_N1(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N1_SHIFT)) & USB3_DNCTRL_N1_MASK)
#define USB3_DNCTRL_N2_MASK                      (0x4U)
#define USB3_DNCTRL_N2_SHIFT                     (2U)
#define USB3_DNCTRL_N2(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N2_SHIFT)) & USB3_DNCTRL_N2_MASK)
#define USB3_DNCTRL_N3_MASK                      (0x8U)
#define USB3_DNCTRL_N3_SHIFT                     (3U)
#define USB3_DNCTRL_N3(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N3_SHIFT)) & USB3_DNCTRL_N3_MASK)
#define USB3_DNCTRL_N4_MASK                      (0x10U)
#define USB3_DNCTRL_N4_SHIFT                     (4U)
#define USB3_DNCTRL_N4(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N4_SHIFT)) & USB3_DNCTRL_N4_MASK)
#define USB3_DNCTRL_N5_MASK                      (0x20U)
#define USB3_DNCTRL_N5_SHIFT                     (5U)
#define USB3_DNCTRL_N5(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N5_SHIFT)) & USB3_DNCTRL_N5_MASK)
#define USB3_DNCTRL_N6_MASK                      (0x40U)
#define USB3_DNCTRL_N6_SHIFT                     (6U)
#define USB3_DNCTRL_N6(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N6_SHIFT)) & USB3_DNCTRL_N6_MASK)
#define USB3_DNCTRL_N7_MASK                      (0x80U)
#define USB3_DNCTRL_N7_SHIFT                     (7U)
#define USB3_DNCTRL_N7(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N7_SHIFT)) & USB3_DNCTRL_N7_MASK)
#define USB3_DNCTRL_N8_MASK                      (0x100U)
#define USB3_DNCTRL_N8_SHIFT                     (8U)
#define USB3_DNCTRL_N8(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N8_SHIFT)) & USB3_DNCTRL_N8_MASK)
#define USB3_DNCTRL_N9_MASK                      (0x200U)
#define USB3_DNCTRL_N9_SHIFT                     (9U)
#define USB3_DNCTRL_N9(x)                        (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N9_SHIFT)) & USB3_DNCTRL_N9_MASK)
#define USB3_DNCTRL_N10_MASK                     (0x400U)
#define USB3_DNCTRL_N10_SHIFT                    (10U)
#define USB3_DNCTRL_N10(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N10_SHIFT)) & USB3_DNCTRL_N10_MASK)
#define USB3_DNCTRL_N11_MASK                     (0x800U)
#define USB3_DNCTRL_N11_SHIFT                    (11U)
#define USB3_DNCTRL_N11(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N11_SHIFT)) & USB3_DNCTRL_N11_MASK)
#define USB3_DNCTRL_N12_MASK                     (0x1000U)
#define USB3_DNCTRL_N12_SHIFT                    (12U)
#define USB3_DNCTRL_N12(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N12_SHIFT)) & USB3_DNCTRL_N12_MASK)
#define USB3_DNCTRL_N13_MASK                     (0x2000U)
#define USB3_DNCTRL_N13_SHIFT                    (13U)
#define USB3_DNCTRL_N13(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N13_SHIFT)) & USB3_DNCTRL_N13_MASK)
#define USB3_DNCTRL_N14_MASK                     (0x4000U)
#define USB3_DNCTRL_N14_SHIFT                    (14U)
#define USB3_DNCTRL_N14(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N14_SHIFT)) & USB3_DNCTRL_N14_MASK)
#define USB3_DNCTRL_N15_MASK                     (0x8000U)
#define USB3_DNCTRL_N15_SHIFT                    (15U)
#define USB3_DNCTRL_N15(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_DNCTRL_N15_SHIFT)) & USB3_DNCTRL_N15_MASK)
/*! @} */

/*! @name CRCR_LO - Command Ring Control Register Low */
/*! @{ */
#define USB3_CRCR_LO_RCS_MASK                    (0x1U)
#define USB3_CRCR_LO_RCS_SHIFT                   (0U)
#define USB3_CRCR_LO_RCS(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_RCS_SHIFT)) & USB3_CRCR_LO_RCS_MASK)
#define USB3_CRCR_LO_CS_MASK                     (0x2U)
#define USB3_CRCR_LO_CS_SHIFT                    (1U)
#define USB3_CRCR_LO_CS(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_CS_SHIFT)) & USB3_CRCR_LO_CS_MASK)
#define USB3_CRCR_LO_CA_MASK                     (0x4U)
#define USB3_CRCR_LO_CA_SHIFT                    (2U)
#define USB3_CRCR_LO_CA(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_CA_SHIFT)) & USB3_CRCR_LO_CA_MASK)
#define USB3_CRCR_LO_CRR_MASK                    (0x8U)
#define USB3_CRCR_LO_CRR_SHIFT                   (3U)
#define USB3_CRCR_LO_CRR(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_CRR_SHIFT)) & USB3_CRCR_LO_CRR_MASK)
#define USB3_CRCR_LO_CRPtr_L_MASK                (0xFFFFFFC0U)
#define USB3_CRCR_LO_CRPtr_L_SHIFT               (6U)
#define USB3_CRCR_LO_CRPtr_L(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_LO_CRPtr_L_SHIFT)) & USB3_CRCR_LO_CRPtr_L_MASK)
/*! @} */

/*! @name CRCR_HI - Command Ring Control Register High */
/*! @{ */
#define USB3_CRCR_HI_CRPtr_H_MASK                (0xFFFFFFFFU)
#define USB3_CRCR_HI_CRPtr_H_SHIFT               (0U)
#define USB3_CRCR_HI_CRPtr_H(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_CRCR_HI_CRPtr_H_SHIFT)) & USB3_CRCR_HI_CRPtr_H_MASK)
/*! @} */

/*! @name DCBAAP_LO - Device Context Base Address Array Pointer(LOW) */
/*! @{ */
#define USB3_DCBAAP_LO_DCBAAPtr_L_MASK           (0xFFFFFFC0U)
#define USB3_DCBAAP_LO_DCBAAPtr_L_SHIFT          (6U)
#define USB3_DCBAAP_LO_DCBAAPtr_L(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DCBAAP_LO_DCBAAPtr_L_SHIFT)) & USB3_DCBAAP_LO_DCBAAPtr_L_MASK)
/*! @} */

/*! @name DCBAAP_HI - Device Context Base Address Array Pointer (HIGH) */
/*! @{ */
#define USB3_DCBAAP_HI_DCBAAPtr_H_MASK           (0xFFFFFFFFU)
#define USB3_DCBAAP_HI_DCBAAPtr_H_SHIFT          (0U)
#define USB3_DCBAAP_HI_DCBAAPtr_H(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DCBAAP_HI_DCBAAPtr_H_SHIFT)) & USB3_DCBAAP_HI_DCBAAPtr_H_MASK)
/*! @} */

/*! @name CONFIG - Configure */
/*! @{ */
#define USB3_CONFIG_MaxSlotsEn_MASK              (0xFFU)
#define USB3_CONFIG_MaxSlotsEn_SHIFT             (0U)
#define USB3_CONFIG_MaxSlotsEn(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CONFIG_MaxSlotsEn_SHIFT)) & USB3_CONFIG_MaxSlotsEn_MASK)
/*! @} */

/*! @name PORTSC1USB2 - USB2 Port Status and Control */
/*! @{ */
#define USB3_PORTSC1USB2_CCS_MASK                (0x1U)
#define USB3_PORTSC1USB2_CCS_SHIFT               (0U)
#define USB3_PORTSC1USB2_CCS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_CCS_SHIFT)) & USB3_PORTSC1USB2_CCS_MASK)
#define USB3_PORTSC1USB2_PED_MASK                (0x2U)
#define USB3_PORTSC1USB2_PED_SHIFT               (1U)
#define USB3_PORTSC1USB2_PED(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PED_SHIFT)) & USB3_PORTSC1USB2_PED_MASK)
#define USB3_PORTSC1USB2_OCA_MASK                (0x8U)
#define USB3_PORTSC1USB2_OCA_SHIFT               (3U)
#define USB3_PORTSC1USB2_OCA(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_OCA_SHIFT)) & USB3_PORTSC1USB2_OCA_MASK)
#define USB3_PORTSC1USB2_PR_MASK                 (0x10U)
#define USB3_PORTSC1USB2_PR_SHIFT                (4U)
#define USB3_PORTSC1USB2_PR(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PR_SHIFT)) & USB3_PORTSC1USB2_PR_MASK)
#define USB3_PORTSC1USB2_PLS_MASK                (0x1E0U)
#define USB3_PORTSC1USB2_PLS_SHIFT               (5U)
#define USB3_PORTSC1USB2_PLS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PLS_SHIFT)) & USB3_PORTSC1USB2_PLS_MASK)
#define USB3_PORTSC1USB2_PP_MASK                 (0x200U)
#define USB3_PORTSC1USB2_PP_SHIFT                (9U)
#define USB3_PORTSC1USB2_PP(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PP_SHIFT)) & USB3_PORTSC1USB2_PP_MASK)
#define USB3_PORTSC1USB2_PortSpeed_MASK          (0x3C00U)
#define USB3_PORTSC1USB2_PortSpeed_SHIFT         (10U)
#define USB3_PORTSC1USB2_PortSpeed(x)            (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PortSpeed_SHIFT)) & USB3_PORTSC1USB2_PortSpeed_MASK)
#define USB3_PORTSC1USB2_PIC_MASK                (0xC000U)
#define USB3_PORTSC1USB2_PIC_SHIFT               (14U)
#define USB3_PORTSC1USB2_PIC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PIC_SHIFT)) & USB3_PORTSC1USB2_PIC_MASK)
#define USB3_PORTSC1USB2_LWS_MASK                (0x10000U)
#define USB3_PORTSC1USB2_LWS_SHIFT               (16U)
#define USB3_PORTSC1USB2_LWS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_LWS_SHIFT)) & USB3_PORTSC1USB2_LWS_MASK)
#define USB3_PORTSC1USB2_CSC_MASK                (0x20000U)
#define USB3_PORTSC1USB2_CSC_SHIFT               (17U)
#define USB3_PORTSC1USB2_CSC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_CSC_SHIFT)) & USB3_PORTSC1USB2_CSC_MASK)
#define USB3_PORTSC1USB2_PEC_MASK                (0x40000U)
#define USB3_PORTSC1USB2_PEC_SHIFT               (18U)
#define USB3_PORTSC1USB2_PEC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PEC_SHIFT)) & USB3_PORTSC1USB2_PEC_MASK)
#define USB3_PORTSC1USB2_WRC_MASK                (0x80000U)
#define USB3_PORTSC1USB2_WRC_SHIFT               (19U)
#define USB3_PORTSC1USB2_WRC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_WRC_SHIFT)) & USB3_PORTSC1USB2_WRC_MASK)
#define USB3_PORTSC1USB2_OCC_MASK                (0x100000U)
#define USB3_PORTSC1USB2_OCC_SHIFT               (20U)
#define USB3_PORTSC1USB2_OCC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_OCC_SHIFT)) & USB3_PORTSC1USB2_OCC_MASK)
#define USB3_PORTSC1USB2_PRC_MASK                (0x200000U)
#define USB3_PORTSC1USB2_PRC_SHIFT               (21U)
#define USB3_PORTSC1USB2_PRC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PRC_SHIFT)) & USB3_PORTSC1USB2_PRC_MASK)
#define USB3_PORTSC1USB2_PLC_MASK                (0x400000U)
#define USB3_PORTSC1USB2_PLC_SHIFT               (22U)
#define USB3_PORTSC1USB2_PLC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_PLC_SHIFT)) & USB3_PORTSC1USB2_PLC_MASK)
#define USB3_PORTSC1USB2_CAS_MASK                (0x1000000U)
#define USB3_PORTSC1USB2_CAS_SHIFT               (24U)
#define USB3_PORTSC1USB2_CAS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_CAS_SHIFT)) & USB3_PORTSC1USB2_CAS_MASK)
#define USB3_PORTSC1USB2_WCE_MASK                (0x2000000U)
#define USB3_PORTSC1USB2_WCE_SHIFT               (25U)
#define USB3_PORTSC1USB2_WCE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_WCE_SHIFT)) & USB3_PORTSC1USB2_WCE_MASK)
#define USB3_PORTSC1USB2_WDE_MASK                (0x4000000U)
#define USB3_PORTSC1USB2_WDE_SHIFT               (26U)
#define USB3_PORTSC1USB2_WDE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_WDE_SHIFT)) & USB3_PORTSC1USB2_WDE_MASK)
#define USB3_PORTSC1USB2_WOE_MASK                (0x8000000U)
#define USB3_PORTSC1USB2_WOE_SHIFT               (27U)
#define USB3_PORTSC1USB2_WOE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_WOE_SHIFT)) & USB3_PORTSC1USB2_WOE_MASK)
#define USB3_PORTSC1USB2_DR_MASK                 (0x40000000U)
#define USB3_PORTSC1USB2_DR_SHIFT                (30U)
#define USB3_PORTSC1USB2_DR(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB2_DR_SHIFT)) & USB3_PORTSC1USB2_DR_MASK)
/*! @} */

/*! @name PORTPMSC1USB2 - USB2 Port Power Management Status and Control */
/*! @{ */
#define USB3_PORTPMSC1USB2_L1S_MASK              (0x7U)
#define USB3_PORTPMSC1USB2_L1S_SHIFT             (0U)
#define USB3_PORTPMSC1USB2_L1S(x)                (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_L1S_SHIFT)) & USB3_PORTPMSC1USB2_L1S_MASK)
#define USB3_PORTPMSC1USB2_RWE_MASK              (0x8U)
#define USB3_PORTPMSC1USB2_RWE_SHIFT             (3U)
#define USB3_PORTPMSC1USB2_RWE(x)                (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_RWE_SHIFT)) & USB3_PORTPMSC1USB2_RWE_MASK)
#define USB3_PORTPMSC1USB2_BESL_MASK             (0xF0U)
#define USB3_PORTPMSC1USB2_BESL_SHIFT            (4U)
#define USB3_PORTPMSC1USB2_BESL(x)               (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_BESL_SHIFT)) & USB3_PORTPMSC1USB2_BESL_MASK)
#define USB3_PORTPMSC1USB2_L1DS_MASK             (0xFF00U)
#define USB3_PORTPMSC1USB2_L1DS_SHIFT            (8U)
#define USB3_PORTPMSC1USB2_L1DS(x)               (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_L1DS_SHIFT)) & USB3_PORTPMSC1USB2_L1DS_MASK)
#define USB3_PORTPMSC1USB2_HLE_MASK              (0x10000U)
#define USB3_PORTPMSC1USB2_HLE_SHIFT             (16U)
#define USB3_PORTPMSC1USB2_HLE(x)                (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_HLE_SHIFT)) & USB3_PORTPMSC1USB2_HLE_MASK)
#define USB3_PORTPMSC1USB2_PTC_MASK              (0xF0000000U)
#define USB3_PORTPMSC1USB2_PTC_SHIFT             (28U)
#define USB3_PORTPMSC1USB2_PTC(x)                (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB2_PTC_SHIFT)) & USB3_PORTPMSC1USB2_PTC_MASK)
/*! @} */

/*! @name PORT1HLPMC - USB2 Port Hardware LPM Control register */
/*! @{ */
#define USB3_PORT1HLPMC_HIRDM_MASK               (0x3U)
#define USB3_PORT1HLPMC_HIRDM_SHIFT              (0U)
#define USB3_PORT1HLPMC_HIRDM(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_PORT1HLPMC_HIRDM_SHIFT)) & USB3_PORT1HLPMC_HIRDM_MASK)
#define USB3_PORT1HLPMC_L1_timeout_MASK          (0x3FCU)
#define USB3_PORT1HLPMC_L1_timeout_SHIFT         (2U)
#define USB3_PORT1HLPMC_L1_timeout(x)            (((uint32_t)(((uint32_t)(x)) << USB3_PORT1HLPMC_L1_timeout_SHIFT)) & USB3_PORT1HLPMC_L1_timeout_MASK)
#define USB3_PORT1HLPMC_BESLD_MASK               (0x3C00U)
#define USB3_PORT1HLPMC_BESLD_SHIFT              (10U)
#define USB3_PORT1HLPMC_BESLD(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_PORT1HLPMC_BESLD_SHIFT)) & USB3_PORT1HLPMC_BESLD_MASK)
/*! @} */

/*! @name PORTSC1USB3 - USB3 Port Status and Control */
/*! @{ */
#define USB3_PORTSC1USB3_CCS_MASK                (0x1U)
#define USB3_PORTSC1USB3_CCS_SHIFT               (0U)
#define USB3_PORTSC1USB3_CCS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_CCS_SHIFT)) & USB3_PORTSC1USB3_CCS_MASK)
#define USB3_PORTSC1USB3_PED_MASK                (0x2U)
#define USB3_PORTSC1USB3_PED_SHIFT               (1U)
#define USB3_PORTSC1USB3_PED(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PED_SHIFT)) & USB3_PORTSC1USB3_PED_MASK)
#define USB3_PORTSC1USB3_OCA_MASK                (0x8U)
#define USB3_PORTSC1USB3_OCA_SHIFT               (3U)
#define USB3_PORTSC1USB3_OCA(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_OCA_SHIFT)) & USB3_PORTSC1USB3_OCA_MASK)
#define USB3_PORTSC1USB3_PR_MASK                 (0x10U)
#define USB3_PORTSC1USB3_PR_SHIFT                (4U)
#define USB3_PORTSC1USB3_PR(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PR_SHIFT)) & USB3_PORTSC1USB3_PR_MASK)
#define USB3_PORTSC1USB3_PLS_MASK                (0x1E0U)
#define USB3_PORTSC1USB3_PLS_SHIFT               (5U)
#define USB3_PORTSC1USB3_PLS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PLS_SHIFT)) & USB3_PORTSC1USB3_PLS_MASK)
#define USB3_PORTSC1USB3_PP_MASK                 (0x200U)
#define USB3_PORTSC1USB3_PP_SHIFT                (9U)
#define USB3_PORTSC1USB3_PP(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PP_SHIFT)) & USB3_PORTSC1USB3_PP_MASK)
#define USB3_PORTSC1USB3_PortSpeed_MASK          (0x3C00U)
#define USB3_PORTSC1USB3_PortSpeed_SHIFT         (10U)
#define USB3_PORTSC1USB3_PortSpeed(x)            (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PortSpeed_SHIFT)) & USB3_PORTSC1USB3_PortSpeed_MASK)
#define USB3_PORTSC1USB3_PIC_MASK                (0xC000U)
#define USB3_PORTSC1USB3_PIC_SHIFT               (14U)
#define USB3_PORTSC1USB3_PIC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PIC_SHIFT)) & USB3_PORTSC1USB3_PIC_MASK)
#define USB3_PORTSC1USB3_LWS_MASK                (0x10000U)
#define USB3_PORTSC1USB3_LWS_SHIFT               (16U)
#define USB3_PORTSC1USB3_LWS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_LWS_SHIFT)) & USB3_PORTSC1USB3_LWS_MASK)
#define USB3_PORTSC1USB3_CSC_MASK                (0x20000U)
#define USB3_PORTSC1USB3_CSC_SHIFT               (17U)
#define USB3_PORTSC1USB3_CSC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_CSC_SHIFT)) & USB3_PORTSC1USB3_CSC_MASK)
#define USB3_PORTSC1USB3_PEC_MASK                (0x40000U)
#define USB3_PORTSC1USB3_PEC_SHIFT               (18U)
#define USB3_PORTSC1USB3_PEC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PEC_SHIFT)) & USB3_PORTSC1USB3_PEC_MASK)
#define USB3_PORTSC1USB3_WRC_MASK                (0x80000U)
#define USB3_PORTSC1USB3_WRC_SHIFT               (19U)
#define USB3_PORTSC1USB3_WRC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WRC_SHIFT)) & USB3_PORTSC1USB3_WRC_MASK)
#define USB3_PORTSC1USB3_OCC_MASK                (0x100000U)
#define USB3_PORTSC1USB3_OCC_SHIFT               (20U)
#define USB3_PORTSC1USB3_OCC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_OCC_SHIFT)) & USB3_PORTSC1USB3_OCC_MASK)
#define USB3_PORTSC1USB3_PRC_MASK                (0x200000U)
#define USB3_PORTSC1USB3_PRC_SHIFT               (21U)
#define USB3_PORTSC1USB3_PRC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PRC_SHIFT)) & USB3_PORTSC1USB3_PRC_MASK)
#define USB3_PORTSC1USB3_PLC_MASK                (0x400000U)
#define USB3_PORTSC1USB3_PLC_SHIFT               (22U)
#define USB3_PORTSC1USB3_PLC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_PLC_SHIFT)) & USB3_PORTSC1USB3_PLC_MASK)
#define USB3_PORTSC1USB3_CEC_MASK                (0x800000U)
#define USB3_PORTSC1USB3_CEC_SHIFT               (23U)
#define USB3_PORTSC1USB3_CEC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_CEC_SHIFT)) & USB3_PORTSC1USB3_CEC_MASK)
#define USB3_PORTSC1USB3_CAS_MASK                (0x1000000U)
#define USB3_PORTSC1USB3_CAS_SHIFT               (24U)
#define USB3_PORTSC1USB3_CAS(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_CAS_SHIFT)) & USB3_PORTSC1USB3_CAS_MASK)
#define USB3_PORTSC1USB3_WCE_MASK                (0x2000000U)
#define USB3_PORTSC1USB3_WCE_SHIFT               (25U)
#define USB3_PORTSC1USB3_WCE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WCE_SHIFT)) & USB3_PORTSC1USB3_WCE_MASK)
#define USB3_PORTSC1USB3_WDE_MASK                (0x4000000U)
#define USB3_PORTSC1USB3_WDE_SHIFT               (26U)
#define USB3_PORTSC1USB3_WDE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WDE_SHIFT)) & USB3_PORTSC1USB3_WDE_MASK)
#define USB3_PORTSC1USB3_WOE_MASK                (0x8000000U)
#define USB3_PORTSC1USB3_WOE_SHIFT               (27U)
#define USB3_PORTSC1USB3_WOE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WOE_SHIFT)) & USB3_PORTSC1USB3_WOE_MASK)
#define USB3_PORTSC1USB3_DR_MASK                 (0x40000000U)
#define USB3_PORTSC1USB3_DR_SHIFT                (30U)
#define USB3_PORTSC1USB3_DR(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_DR_SHIFT)) & USB3_PORTSC1USB3_DR_MASK)
#define USB3_PORTSC1USB3_WPR_MASK                (0x80000000U)
#define USB3_PORTSC1USB3_WPR_SHIFT               (31U)
#define USB3_PORTSC1USB3_WPR(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_PORTSC1USB3_WPR_SHIFT)) & USB3_PORTSC1USB3_WPR_MASK)
/*! @} */

/*! @name PORTPMSC1USB3 - USB3 Port Power Management Status and Control */
/*! @{ */
#define USB3_PORTPMSC1USB3_U1_timeout_MASK       (0xFFU)
#define USB3_PORTPMSC1USB3_U1_timeout_SHIFT      (0U)
#define USB3_PORTPMSC1USB3_U1_timeout(x)         (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB3_U1_timeout_SHIFT)) & USB3_PORTPMSC1USB3_U1_timeout_MASK)
#define USB3_PORTPMSC1USB3_U2_timeout_MASK       (0xFF00U)
#define USB3_PORTPMSC1USB3_U2_timeout_SHIFT      (8U)
#define USB3_PORTPMSC1USB3_U2_timeout(x)         (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB3_U2_timeout_SHIFT)) & USB3_PORTPMSC1USB3_U2_timeout_MASK)
#define USB3_PORTPMSC1USB3_FLA_MASK              (0x10000U)
#define USB3_PORTPMSC1USB3_FLA_SHIFT             (16U)
#define USB3_PORTPMSC1USB3_FLA(x)                (((uint32_t)(((uint32_t)(x)) << USB3_PORTPMSC1USB3_FLA_SHIFT)) & USB3_PORTPMSC1USB3_FLA_MASK)
/*! @} */

/*! @name PORTLI1 - USB3 Port Link Info */
/*! @{ */
#define USB3_PORTLI1_LEC_MASK                    (0xFFFFU)
#define USB3_PORTLI1_LEC_SHIFT                   (0U)
#define USB3_PORTLI1_LEC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_PORTLI1_LEC_SHIFT)) & USB3_PORTLI1_LEC_MASK)
/*! @} */

/*! @name MFINDEX - MicroFrame Index */
/*! @{ */
#define USB3_MFINDEX_MFIndex_MASK                (0x3FFFU)
#define USB3_MFINDEX_MFIndex_SHIFT               (0U)
#define USB3_MFINDEX_MFIndex(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_MFINDEX_MFIndex_SHIFT)) & USB3_MFINDEX_MFIndex_MASK)
/*! @} */

/*! @name IMAN0 - Interrupter Management */
/*! @{ */
#define USB3_IMAN0_IP_MASK                       (0x1U)
#define USB3_IMAN0_IP_SHIFT                      (0U)
#define USB3_IMAN0_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN0_IP_SHIFT)) & USB3_IMAN0_IP_MASK)
#define USB3_IMAN0_IE_MASK                       (0x2U)
#define USB3_IMAN0_IE_SHIFT                      (1U)
#define USB3_IMAN0_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN0_IE_SHIFT)) & USB3_IMAN0_IE_MASK)
/*! @} */

/*! @name IMOD0 - Interrupter Moderation */
/*! @{ */
#define USB3_IMOD0_IMODI_MASK                    (0xFFFFU)
#define USB3_IMOD0_IMODI_SHIFT                   (0U)
#define USB3_IMOD0_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD0_IMODI_SHIFT)) & USB3_IMOD0_IMODI_MASK)
#define USB3_IMOD0_IMODC_MASK                    (0xFFFF0000U)
#define USB3_IMOD0_IMODC_SHIFT                   (16U)
#define USB3_IMOD0_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD0_IMODC_SHIFT)) & USB3_IMOD0_IMODC_MASK)
/*! @} */

/*! @name ERSTSZ0 - Event Ring Segment Table Size */
/*! @{ */
#define USB3_ERSTSZ0_ERSTS_MASK                  (0xFFFFU)
#define USB3_ERSTSZ0_ERSTS_SHIFT                 (0U)
#define USB3_ERSTSZ0_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ0_ERSTS_SHIFT)) & USB3_ERSTSZ0_ERSTS_MASK)
/*! @} */

/*! @name ERSTBA0_LO - Event Ring Segment Table Base Address (LOW) */
/*! @{ */
#define USB3_ERSTBA0_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
#define USB3_ERSTBA0_LO_ERSTBAddr_LO_SHIFT       (6U)
#define USB3_ERSTBA0_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA0_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA0_LO_ERSTBAddr_LO_MASK)
/*! @} */

/*! @name ERSTBA00_HI - Event Ring Segment Table Base Address (HIGH) */
/*! @{ */
#define USB3_ERSTBA00_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
#define USB3_ERSTBA00_HI_ERSTBAddr_HI_SHIFT      (0U)
#define USB3_ERSTBA00_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA00_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA00_HI_ERSTBAddr_HI_MASK)
/*! @} */

/*! @name ERDP0_LO - Event Ring Dequeue Pointer (LOW) */
/*! @{ */
#define USB3_ERDP0_LO_DESI_MASK                  (0x7U)
#define USB3_ERDP0_LO_DESI_SHIFT                 (0U)
#define USB3_ERDP0_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP0_LO_DESI_SHIFT)) & USB3_ERDP0_LO_DESI_MASK)
#define USB3_ERDP0_LO_EHB_MASK                   (0x8U)
#define USB3_ERDP0_LO_EHB_SHIFT                  (3U)
#define USB3_ERDP0_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP0_LO_EHB_SHIFT)) & USB3_ERDP0_LO_EHB_MASK)
#define USB3_ERDP0_LO_ERDPtr_MASK                (0xFFFFFFF0U)
#define USB3_ERDP0_LO_ERDPtr_SHIFT               (4U)
#define USB3_ERDP0_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP0_LO_ERDPtr_SHIFT)) & USB3_ERDP0_LO_ERDPtr_MASK)
/*! @} */

/*! @name ERDP0_HI - Event Ring Dequeue Pointer (HIGH) */
/*! @{ */
#define USB3_ERDP0_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
#define USB3_ERDP0_HI_ERDPtr_HI_SHIFT            (0U)
#define USB3_ERDP0_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP0_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP0_HI_ERDPtr_HI_MASK)
/*! @} */

/*! @name IMAN1 - Interrupter Management */
/*! @{ */
#define USB3_IMAN1_IP_MASK                       (0x1U)
#define USB3_IMAN1_IP_SHIFT                      (0U)
#define USB3_IMAN1_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN1_IP_SHIFT)) & USB3_IMAN1_IP_MASK)
#define USB3_IMAN1_IE_MASK                       (0x2U)
#define USB3_IMAN1_IE_SHIFT                      (1U)
#define USB3_IMAN1_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN1_IE_SHIFT)) & USB3_IMAN1_IE_MASK)
/*! @} */

/*! @name IMOD1 - Interrupter Moderation */
/*! @{ */
#define USB3_IMOD1_IMODI_MASK                    (0xFFFFU)
#define USB3_IMOD1_IMODI_SHIFT                   (0U)
#define USB3_IMOD1_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD1_IMODI_SHIFT)) & USB3_IMOD1_IMODI_MASK)
#define USB3_IMOD1_IMODC_MASK                    (0xFFFF0000U)
#define USB3_IMOD1_IMODC_SHIFT                   (16U)
#define USB3_IMOD1_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD1_IMODC_SHIFT)) & USB3_IMOD1_IMODC_MASK)
/*! @} */

/*! @name ERSTSZ1 - Event Ring Segment Table Size */
/*! @{ */
#define USB3_ERSTSZ1_ERSTS_MASK                  (0xFFFFU)
#define USB3_ERSTSZ1_ERSTS_SHIFT                 (0U)
#define USB3_ERSTSZ1_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ1_ERSTS_SHIFT)) & USB3_ERSTSZ1_ERSTS_MASK)
/*! @} */

/*! @name ERSTBA1_LO - Event Ring Segment Table Base Address (LOW) */
/*! @{ */
#define USB3_ERSTBA1_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
#define USB3_ERSTBA1_LO_ERSTBAddr_LO_SHIFT       (6U)
#define USB3_ERSTBA1_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA1_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA1_LO_ERSTBAddr_LO_MASK)
/*! @} */

/*! @name ERSTBA01_HI - Event Ring Segment Table Base Address (HIGH) */
/*! @{ */
#define USB3_ERSTBA01_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
#define USB3_ERSTBA01_HI_ERSTBAddr_HI_SHIFT      (0U)
#define USB3_ERSTBA01_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA01_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA01_HI_ERSTBAddr_HI_MASK)
/*! @} */

/*! @name ERDP1_LO - Event Ring Dequeue Pointer (LOW) */
/*! @{ */
#define USB3_ERDP1_LO_DESI_MASK                  (0x7U)
#define USB3_ERDP1_LO_DESI_SHIFT                 (0U)
#define USB3_ERDP1_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP1_LO_DESI_SHIFT)) & USB3_ERDP1_LO_DESI_MASK)
#define USB3_ERDP1_LO_EHB_MASK                   (0x8U)
#define USB3_ERDP1_LO_EHB_SHIFT                  (3U)
#define USB3_ERDP1_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP1_LO_EHB_SHIFT)) & USB3_ERDP1_LO_EHB_MASK)
#define USB3_ERDP1_LO_ERDPtr_MASK                (0xFFFFFFF0U)
#define USB3_ERDP1_LO_ERDPtr_SHIFT               (4U)
#define USB3_ERDP1_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP1_LO_ERDPtr_SHIFT)) & USB3_ERDP1_LO_ERDPtr_MASK)
/*! @} */

/*! @name ERDP1_HI - Event Ring Dequeue Pointer (HIGH) */
/*! @{ */
#define USB3_ERDP1_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
#define USB3_ERDP1_HI_ERDPtr_HI_SHIFT            (0U)
#define USB3_ERDP1_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP1_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP1_HI_ERDPtr_HI_MASK)
/*! @} */

/*! @name IMAN2 - Interrupter Management */
/*! @{ */
#define USB3_IMAN2_IP_MASK                       (0x1U)
#define USB3_IMAN2_IP_SHIFT                      (0U)
#define USB3_IMAN2_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN2_IP_SHIFT)) & USB3_IMAN2_IP_MASK)
#define USB3_IMAN2_IE_MASK                       (0x2U)
#define USB3_IMAN2_IE_SHIFT                      (1U)
#define USB3_IMAN2_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN2_IE_SHIFT)) & USB3_IMAN2_IE_MASK)
/*! @} */

/*! @name IMOD2 - Interrupter Moderation */
/*! @{ */
#define USB3_IMOD2_IMODI_MASK                    (0xFFFFU)
#define USB3_IMOD2_IMODI_SHIFT                   (0U)
#define USB3_IMOD2_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD2_IMODI_SHIFT)) & USB3_IMOD2_IMODI_MASK)
#define USB3_IMOD2_IMODC_MASK                    (0xFFFF0000U)
#define USB3_IMOD2_IMODC_SHIFT                   (16U)
#define USB3_IMOD2_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD2_IMODC_SHIFT)) & USB3_IMOD2_IMODC_MASK)
/*! @} */

/*! @name ERSTSZ2 - Event Ring Segment Table Size */
/*! @{ */
#define USB3_ERSTSZ2_ERSTS_MASK                  (0xFFFFU)
#define USB3_ERSTSZ2_ERSTS_SHIFT                 (0U)
#define USB3_ERSTSZ2_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ2_ERSTS_SHIFT)) & USB3_ERSTSZ2_ERSTS_MASK)
/*! @} */

/*! @name ERSTBA2_LO - Event Ring Segment Table Base Address (LOW) */
/*! @{ */
#define USB3_ERSTBA2_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
#define USB3_ERSTBA2_LO_ERSTBAddr_LO_SHIFT       (6U)
#define USB3_ERSTBA2_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA2_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA2_LO_ERSTBAddr_LO_MASK)
/*! @} */

/*! @name ERSTBA02_HI - Event Ring Segment Table Base Address (HIGH) */
/*! @{ */
#define USB3_ERSTBA02_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
#define USB3_ERSTBA02_HI_ERSTBAddr_HI_SHIFT      (0U)
#define USB3_ERSTBA02_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA02_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA02_HI_ERSTBAddr_HI_MASK)
/*! @} */

/*! @name ERDP2_LO - Event Ring Dequeue Pointer (LOW) */
/*! @{ */
#define USB3_ERDP2_LO_DESI_MASK                  (0x7U)
#define USB3_ERDP2_LO_DESI_SHIFT                 (0U)
#define USB3_ERDP2_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP2_LO_DESI_SHIFT)) & USB3_ERDP2_LO_DESI_MASK)
#define USB3_ERDP2_LO_EHB_MASK                   (0x8U)
#define USB3_ERDP2_LO_EHB_SHIFT                  (3U)
#define USB3_ERDP2_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP2_LO_EHB_SHIFT)) & USB3_ERDP2_LO_EHB_MASK)
#define USB3_ERDP2_LO_ERDPtr_MASK                (0xFFFFFFF0U)
#define USB3_ERDP2_LO_ERDPtr_SHIFT               (4U)
#define USB3_ERDP2_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP2_LO_ERDPtr_SHIFT)) & USB3_ERDP2_LO_ERDPtr_MASK)
/*! @} */

/*! @name ERDP2_HI - Event Ring Dequeue Pointer (HIGH) */
/*! @{ */
#define USB3_ERDP2_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
#define USB3_ERDP2_HI_ERDPtr_HI_SHIFT            (0U)
#define USB3_ERDP2_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP2_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP2_HI_ERDPtr_HI_MASK)
/*! @} */

/*! @name IMAN3 - Interrupter Management */
/*! @{ */
#define USB3_IMAN3_IP_MASK                       (0x1U)
#define USB3_IMAN3_IP_SHIFT                      (0U)
#define USB3_IMAN3_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN3_IP_SHIFT)) & USB3_IMAN3_IP_MASK)
#define USB3_IMAN3_IE_MASK                       (0x2U)
#define USB3_IMAN3_IE_SHIFT                      (1U)
#define USB3_IMAN3_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN3_IE_SHIFT)) & USB3_IMAN3_IE_MASK)
/*! @} */

/*! @name IMOD3 - Interrupter Moderation */
/*! @{ */
#define USB3_IMOD3_IMODI_MASK                    (0xFFFFU)
#define USB3_IMOD3_IMODI_SHIFT                   (0U)
#define USB3_IMOD3_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD3_IMODI_SHIFT)) & USB3_IMOD3_IMODI_MASK)
#define USB3_IMOD3_IMODC_MASK                    (0xFFFF0000U)
#define USB3_IMOD3_IMODC_SHIFT                   (16U)
#define USB3_IMOD3_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD3_IMODC_SHIFT)) & USB3_IMOD3_IMODC_MASK)
/*! @} */

/*! @name ERSTSZ3 - Event Ring Segment Table Size */
/*! @{ */
#define USB3_ERSTSZ3_ERSTS_MASK                  (0xFFFFU)
#define USB3_ERSTSZ3_ERSTS_SHIFT                 (0U)
#define USB3_ERSTSZ3_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ3_ERSTS_SHIFT)) & USB3_ERSTSZ3_ERSTS_MASK)
/*! @} */

/*! @name ERSTBA3_LO - Event Ring Segment Table Base Address (LOW) */
/*! @{ */
#define USB3_ERSTBA3_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
#define USB3_ERSTBA3_LO_ERSTBAddr_LO_SHIFT       (6U)
#define USB3_ERSTBA3_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA3_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA3_LO_ERSTBAddr_LO_MASK)
/*! @} */

/*! @name ERSTBA03_HI - Event Ring Segment Table Base Address (HIGH) */
/*! @{ */
#define USB3_ERSTBA03_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
#define USB3_ERSTBA03_HI_ERSTBAddr_HI_SHIFT      (0U)
#define USB3_ERSTBA03_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA03_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA03_HI_ERSTBAddr_HI_MASK)
/*! @} */

/*! @name ERDP3_LO - Event Ring Dequeue Pointer (LOW) */
/*! @{ */
#define USB3_ERDP3_LO_DESI_MASK                  (0x7U)
#define USB3_ERDP3_LO_DESI_SHIFT                 (0U)
#define USB3_ERDP3_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP3_LO_DESI_SHIFT)) & USB3_ERDP3_LO_DESI_MASK)
#define USB3_ERDP3_LO_EHB_MASK                   (0x8U)
#define USB3_ERDP3_LO_EHB_SHIFT                  (3U)
#define USB3_ERDP3_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP3_LO_EHB_SHIFT)) & USB3_ERDP3_LO_EHB_MASK)
#define USB3_ERDP3_LO_ERDPtr_MASK                (0xFFFFFFF0U)
#define USB3_ERDP3_LO_ERDPtr_SHIFT               (4U)
#define USB3_ERDP3_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP3_LO_ERDPtr_SHIFT)) & USB3_ERDP3_LO_ERDPtr_MASK)
/*! @} */

/*! @name ERDP3_HI - Event Ring Dequeue Pointer (HIGH) */
/*! @{ */
#define USB3_ERDP3_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
#define USB3_ERDP3_HI_ERDPtr_HI_SHIFT            (0U)
#define USB3_ERDP3_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP3_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP3_HI_ERDPtr_HI_MASK)
/*! @} */

/*! @name IMAN4 - Interrupter Management */
/*! @{ */
#define USB3_IMAN4_IP_MASK                       (0x1U)
#define USB3_IMAN4_IP_SHIFT                      (0U)
#define USB3_IMAN4_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN4_IP_SHIFT)) & USB3_IMAN4_IP_MASK)
#define USB3_IMAN4_IE_MASK                       (0x2U)
#define USB3_IMAN4_IE_SHIFT                      (1U)
#define USB3_IMAN4_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN4_IE_SHIFT)) & USB3_IMAN4_IE_MASK)
/*! @} */

/*! @name IMOD4 - Interrupter Moderation */
/*! @{ */
#define USB3_IMOD4_IMODI_MASK                    (0xFFFFU)
#define USB3_IMOD4_IMODI_SHIFT                   (0U)
#define USB3_IMOD4_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD4_IMODI_SHIFT)) & USB3_IMOD4_IMODI_MASK)
#define USB3_IMOD4_IMODC_MASK                    (0xFFFF0000U)
#define USB3_IMOD4_IMODC_SHIFT                   (16U)
#define USB3_IMOD4_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD4_IMODC_SHIFT)) & USB3_IMOD4_IMODC_MASK)
/*! @} */

/*! @name ERSTSZ4 - Event Ring Segment Table Size */
/*! @{ */
#define USB3_ERSTSZ4_ERSTS_MASK                  (0xFFFFU)
#define USB3_ERSTSZ4_ERSTS_SHIFT                 (0U)
#define USB3_ERSTSZ4_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ4_ERSTS_SHIFT)) & USB3_ERSTSZ4_ERSTS_MASK)
/*! @} */

/*! @name ERSTBA4_LO - Event Ring Segment Table Base Address (LOW) */
/*! @{ */
#define USB3_ERSTBA4_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
#define USB3_ERSTBA4_LO_ERSTBAddr_LO_SHIFT       (6U)
#define USB3_ERSTBA4_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA4_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA4_LO_ERSTBAddr_LO_MASK)
/*! @} */

/*! @name ERSTBA04_HI - Event Ring Segment Table Base Address (HIGH) */
/*! @{ */
#define USB3_ERSTBA04_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
#define USB3_ERSTBA04_HI_ERSTBAddr_HI_SHIFT      (0U)
#define USB3_ERSTBA04_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA04_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA04_HI_ERSTBAddr_HI_MASK)
/*! @} */

/*! @name ERDP4_LO - Event Ring Dequeue Pointer (LOW) */
/*! @{ */
#define USB3_ERDP4_LO_DESI_MASK                  (0x7U)
#define USB3_ERDP4_LO_DESI_SHIFT                 (0U)
#define USB3_ERDP4_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP4_LO_DESI_SHIFT)) & USB3_ERDP4_LO_DESI_MASK)
#define USB3_ERDP4_LO_EHB_MASK                   (0x8U)
#define USB3_ERDP4_LO_EHB_SHIFT                  (3U)
#define USB3_ERDP4_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP4_LO_EHB_SHIFT)) & USB3_ERDP4_LO_EHB_MASK)
#define USB3_ERDP4_LO_ERDPtr_MASK                (0xFFFFFFF0U)
#define USB3_ERDP4_LO_ERDPtr_SHIFT               (4U)
#define USB3_ERDP4_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP4_LO_ERDPtr_SHIFT)) & USB3_ERDP4_LO_ERDPtr_MASK)
/*! @} */

/*! @name ERDP4_HI - Event Ring Dequeue Pointer (HIGH) */
/*! @{ */
#define USB3_ERDP4_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
#define USB3_ERDP4_HI_ERDPtr_HI_SHIFT            (0U)
#define USB3_ERDP4_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP4_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP4_HI_ERDPtr_HI_MASK)
/*! @} */

/*! @name IMAN5 - Interrupter Management */
/*! @{ */
#define USB3_IMAN5_IP_MASK                       (0x1U)
#define USB3_IMAN5_IP_SHIFT                      (0U)
#define USB3_IMAN5_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN5_IP_SHIFT)) & USB3_IMAN5_IP_MASK)
#define USB3_IMAN5_IE_MASK                       (0x2U)
#define USB3_IMAN5_IE_SHIFT                      (1U)
#define USB3_IMAN5_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN5_IE_SHIFT)) & USB3_IMAN5_IE_MASK)
/*! @} */

/*! @name IMOD5 - Interrupter Moderation */
/*! @{ */
#define USB3_IMOD5_IMODI_MASK                    (0xFFFFU)
#define USB3_IMOD5_IMODI_SHIFT                   (0U)
#define USB3_IMOD5_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD5_IMODI_SHIFT)) & USB3_IMOD5_IMODI_MASK)
#define USB3_IMOD5_IMODC_MASK                    (0xFFFF0000U)
#define USB3_IMOD5_IMODC_SHIFT                   (16U)
#define USB3_IMOD5_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD5_IMODC_SHIFT)) & USB3_IMOD5_IMODC_MASK)
/*! @} */

/*! @name ERSTSZ5 - Event Ring Segment Table Size */
/*! @{ */
#define USB3_ERSTSZ5_ERSTS_MASK                  (0xFFFFU)
#define USB3_ERSTSZ5_ERSTS_SHIFT                 (0U)
#define USB3_ERSTSZ5_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ5_ERSTS_SHIFT)) & USB3_ERSTSZ5_ERSTS_MASK)
/*! @} */

/*! @name ERSTBA5_LO - Event Ring Segment Table Base Address (LOW) */
/*! @{ */
#define USB3_ERSTBA5_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
#define USB3_ERSTBA5_LO_ERSTBAddr_LO_SHIFT       (6U)
#define USB3_ERSTBA5_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA5_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA5_LO_ERSTBAddr_LO_MASK)
/*! @} */

/*! @name ERSTBA05_HI - Event Ring Segment Table Base Address (HIGH) */
/*! @{ */
#define USB3_ERSTBA05_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
#define USB3_ERSTBA05_HI_ERSTBAddr_HI_SHIFT      (0U)
#define USB3_ERSTBA05_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA05_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA05_HI_ERSTBAddr_HI_MASK)
/*! @} */

/*! @name ERDP5_LO - Event Ring Dequeue Pointer (LOW) */
/*! @{ */
#define USB3_ERDP5_LO_DESI_MASK                  (0x7U)
#define USB3_ERDP5_LO_DESI_SHIFT                 (0U)
#define USB3_ERDP5_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP5_LO_DESI_SHIFT)) & USB3_ERDP5_LO_DESI_MASK)
#define USB3_ERDP5_LO_EHB_MASK                   (0x8U)
#define USB3_ERDP5_LO_EHB_SHIFT                  (3U)
#define USB3_ERDP5_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP5_LO_EHB_SHIFT)) & USB3_ERDP5_LO_EHB_MASK)
#define USB3_ERDP5_LO_ERDPtr_MASK                (0xFFFFFFF0U)
#define USB3_ERDP5_LO_ERDPtr_SHIFT               (4U)
#define USB3_ERDP5_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP5_LO_ERDPtr_SHIFT)) & USB3_ERDP5_LO_ERDPtr_MASK)
/*! @} */

/*! @name ERDP5_HI - Event Ring Dequeue Pointer (HIGH) */
/*! @{ */
#define USB3_ERDP5_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
#define USB3_ERDP5_HI_ERDPtr_HI_SHIFT            (0U)
#define USB3_ERDP5_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP5_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP5_HI_ERDPtr_HI_MASK)
/*! @} */

/*! @name IMAN6 - Interrupter Management */
/*! @{ */
#define USB3_IMAN6_IP_MASK                       (0x1U)
#define USB3_IMAN6_IP_SHIFT                      (0U)
#define USB3_IMAN6_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN6_IP_SHIFT)) & USB3_IMAN6_IP_MASK)
#define USB3_IMAN6_IE_MASK                       (0x2U)
#define USB3_IMAN6_IE_SHIFT                      (1U)
#define USB3_IMAN6_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN6_IE_SHIFT)) & USB3_IMAN6_IE_MASK)
/*! @} */

/*! @name IMOD6 - Interrupter Moderation */
/*! @{ */
#define USB3_IMOD6_IMODI_MASK                    (0xFFFFU)
#define USB3_IMOD6_IMODI_SHIFT                   (0U)
#define USB3_IMOD6_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD6_IMODI_SHIFT)) & USB3_IMOD6_IMODI_MASK)
#define USB3_IMOD6_IMODC_MASK                    (0xFFFF0000U)
#define USB3_IMOD6_IMODC_SHIFT                   (16U)
#define USB3_IMOD6_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD6_IMODC_SHIFT)) & USB3_IMOD6_IMODC_MASK)
/*! @} */

/*! @name ERSTSZ6 - Event Ring Segment Table Size */
/*! @{ */
#define USB3_ERSTSZ6_ERSTS_MASK                  (0xFFFFU)
#define USB3_ERSTSZ6_ERSTS_SHIFT                 (0U)
#define USB3_ERSTSZ6_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ6_ERSTS_SHIFT)) & USB3_ERSTSZ6_ERSTS_MASK)
/*! @} */

/*! @name ERSTBA6_LO - Event Ring Segment Table Base Address (LOW) */
/*! @{ */
#define USB3_ERSTBA6_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
#define USB3_ERSTBA6_LO_ERSTBAddr_LO_SHIFT       (6U)
#define USB3_ERSTBA6_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA6_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA6_LO_ERSTBAddr_LO_MASK)
/*! @} */

/*! @name ERSTBA06_HI - Event Ring Segment Table Base Address (HIGH) */
/*! @{ */
#define USB3_ERSTBA06_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
#define USB3_ERSTBA06_HI_ERSTBAddr_HI_SHIFT      (0U)
#define USB3_ERSTBA06_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA06_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA06_HI_ERSTBAddr_HI_MASK)
/*! @} */

/*! @name ERDP6_LO - Event Ring Dequeue Pointer (LOW) */
/*! @{ */
#define USB3_ERDP6_LO_DESI_MASK                  (0x7U)
#define USB3_ERDP6_LO_DESI_SHIFT                 (0U)
#define USB3_ERDP6_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP6_LO_DESI_SHIFT)) & USB3_ERDP6_LO_DESI_MASK)
#define USB3_ERDP6_LO_EHB_MASK                   (0x8U)
#define USB3_ERDP6_LO_EHB_SHIFT                  (3U)
#define USB3_ERDP6_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP6_LO_EHB_SHIFT)) & USB3_ERDP6_LO_EHB_MASK)
#define USB3_ERDP6_LO_ERDPtr_MASK                (0xFFFFFFF0U)
#define USB3_ERDP6_LO_ERDPtr_SHIFT               (4U)
#define USB3_ERDP6_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP6_LO_ERDPtr_SHIFT)) & USB3_ERDP6_LO_ERDPtr_MASK)
/*! @} */

/*! @name ERDP6_HI - Event Ring Dequeue Pointer (HIGH) */
/*! @{ */
#define USB3_ERDP6_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
#define USB3_ERDP6_HI_ERDPtr_HI_SHIFT            (0U)
#define USB3_ERDP6_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP6_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP6_HI_ERDPtr_HI_MASK)
/*! @} */

/*! @name IMAN7 - Interrupter Management */
/*! @{ */
#define USB3_IMAN7_IP_MASK                       (0x1U)
#define USB3_IMAN7_IP_SHIFT                      (0U)
#define USB3_IMAN7_IP(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN7_IP_SHIFT)) & USB3_IMAN7_IP_MASK)
#define USB3_IMAN7_IE_MASK                       (0x2U)
#define USB3_IMAN7_IE_SHIFT                      (1U)
#define USB3_IMAN7_IE(x)                         (((uint32_t)(((uint32_t)(x)) << USB3_IMAN7_IE_SHIFT)) & USB3_IMAN7_IE_MASK)
/*! @} */

/*! @name IMOD7 - Interrupter Moderation */
/*! @{ */
#define USB3_IMOD7_IMODI_MASK                    (0xFFFFU)
#define USB3_IMOD7_IMODI_SHIFT                   (0U)
#define USB3_IMOD7_IMODI(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD7_IMODI_SHIFT)) & USB3_IMOD7_IMODI_MASK)
#define USB3_IMOD7_IMODC_MASK                    (0xFFFF0000U)
#define USB3_IMOD7_IMODC_SHIFT                   (16U)
#define USB3_IMOD7_IMODC(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_IMOD7_IMODC_SHIFT)) & USB3_IMOD7_IMODC_MASK)
/*! @} */

/*! @name ERSTSZ7 - Event Ring Segment Table Size */
/*! @{ */
#define USB3_ERSTSZ7_ERSTS_MASK                  (0xFFFFU)
#define USB3_ERSTSZ7_ERSTS_SHIFT                 (0U)
#define USB3_ERSTSZ7_ERSTS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERSTSZ7_ERSTS_SHIFT)) & USB3_ERSTSZ7_ERSTS_MASK)
/*! @} */

/*! @name ERSTBA7_LO - Event Ring Segment Table Base Address (LOW) */
/*! @{ */
#define USB3_ERSTBA7_LO_ERSTBAddr_LO_MASK        (0xFFFFFFC0U)
#define USB3_ERSTBA7_LO_ERSTBAddr_LO_SHIFT       (6U)
#define USB3_ERSTBA7_LO_ERSTBAddr_LO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA7_LO_ERSTBAddr_LO_SHIFT)) & USB3_ERSTBA7_LO_ERSTBAddr_LO_MASK)
/*! @} */

/*! @name ERSTBA07_HI - Event Ring Segment Table Base Address (HIGH) */
/*! @{ */
#define USB3_ERSTBA07_HI_ERSTBAddr_HI_MASK       (0xFFFFFFFFU)
#define USB3_ERSTBA07_HI_ERSTBAddr_HI_SHIFT      (0U)
#define USB3_ERSTBA07_HI_ERSTBAddr_HI(x)         (((uint32_t)(((uint32_t)(x)) << USB3_ERSTBA07_HI_ERSTBAddr_HI_SHIFT)) & USB3_ERSTBA07_HI_ERSTBAddr_HI_MASK)
/*! @} */

/*! @name ERDP7_LO - Event Ring Dequeue Pointer (LOW) */
/*! @{ */
#define USB3_ERDP7_LO_DESI_MASK                  (0x7U)
#define USB3_ERDP7_LO_DESI_SHIFT                 (0U)
#define USB3_ERDP7_LO_DESI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_ERDP7_LO_DESI_SHIFT)) & USB3_ERDP7_LO_DESI_MASK)
#define USB3_ERDP7_LO_EHB_MASK                   (0x8U)
#define USB3_ERDP7_LO_EHB_SHIFT                  (3U)
#define USB3_ERDP7_LO_EHB(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_ERDP7_LO_EHB_SHIFT)) & USB3_ERDP7_LO_EHB_MASK)
#define USB3_ERDP7_LO_ERDPtr_MASK                (0xFFFFFFF0U)
#define USB3_ERDP7_LO_ERDPtr_SHIFT               (4U)
#define USB3_ERDP7_LO_ERDPtr(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_ERDP7_LO_ERDPtr_SHIFT)) & USB3_ERDP7_LO_ERDPtr_MASK)
/*! @} */

/*! @name ERDP7_HI - Event Ring Dequeue Pointer (HIGH) */
/*! @{ */
#define USB3_ERDP7_HI_ERDPtr_HI_MASK             (0xFFFFFFFFU)
#define USB3_ERDP7_HI_ERDPtr_HI_SHIFT            (0U)
#define USB3_ERDP7_HI_ERDPtr_HI(x)               (((uint32_t)(((uint32_t)(x)) << USB3_ERDP7_HI_ERDPtr_HI_SHIFT)) & USB3_ERDP7_HI_ERDPtr_HI_MASK)
/*! @} */

/*! @name DB0 - Host Controller Doorbell */
/*! @{ */
#define USB3_DB0_DB_target_MASK                  (0xFFU)
#define USB3_DB0_DB_target_SHIFT                 (0U)
#define USB3_DB0_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB0_DB_target_SHIFT)) & USB3_DB0_DB_target_MASK)
#define USB3_DB0_DB_stream_ID_MASK               (0xFFFF0000U)
#define USB3_DB0_DB_stream_ID_SHIFT              (16U)
#define USB3_DB0_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB0_DB_stream_ID_SHIFT)) & USB3_DB0_DB_stream_ID_MASK)
/*! @} */

/*! @name DB1 - Doorbell Array */
/*! @{ */
#define USB3_DB1_DB_target_MASK                  (0xFFU)
#define USB3_DB1_DB_target_SHIFT                 (0U)
#define USB3_DB1_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB1_DB_target_SHIFT)) & USB3_DB1_DB_target_MASK)
#define USB3_DB1_DB_stream_ID_MASK               (0xFFFF0000U)
#define USB3_DB1_DB_stream_ID_SHIFT              (16U)
#define USB3_DB1_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB1_DB_stream_ID_SHIFT)) & USB3_DB1_DB_stream_ID_MASK)
/*! @} */

/*! @name DB2 - Doorbell Array */
/*! @{ */
#define USB3_DB2_DB_target_MASK                  (0xFFU)
#define USB3_DB2_DB_target_SHIFT                 (0U)
#define USB3_DB2_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB2_DB_target_SHIFT)) & USB3_DB2_DB_target_MASK)
#define USB3_DB2_DB_stream_ID_MASK               (0xFFFF0000U)
#define USB3_DB2_DB_stream_ID_SHIFT              (16U)
#define USB3_DB2_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB2_DB_stream_ID_SHIFT)) & USB3_DB2_DB_stream_ID_MASK)
/*! @} */

/*! @name DB3 - Doorbell Array */
/*! @{ */
#define USB3_DB3_DB_target_MASK                  (0xFFU)
#define USB3_DB3_DB_target_SHIFT                 (0U)
#define USB3_DB3_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB3_DB_target_SHIFT)) & USB3_DB3_DB_target_MASK)
#define USB3_DB3_DB_stream_ID_MASK               (0xFFFF0000U)
#define USB3_DB3_DB_stream_ID_SHIFT              (16U)
#define USB3_DB3_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB3_DB_stream_ID_SHIFT)) & USB3_DB3_DB_stream_ID_MASK)
/*! @} */

/*! @name DB4 - Doorbell Array */
/*! @{ */
#define USB3_DB4_DB_target_MASK                  (0xFFU)
#define USB3_DB4_DB_target_SHIFT                 (0U)
#define USB3_DB4_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB4_DB_target_SHIFT)) & USB3_DB4_DB_target_MASK)
#define USB3_DB4_DB_stream_ID_MASK               (0xFFFF0000U)
#define USB3_DB4_DB_stream_ID_SHIFT              (16U)
#define USB3_DB4_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB4_DB_stream_ID_SHIFT)) & USB3_DB4_DB_stream_ID_MASK)
/*! @} */

/*! @name DB5 - Doorbell Array */
/*! @{ */
#define USB3_DB5_DB_target_MASK                  (0xFFU)
#define USB3_DB5_DB_target_SHIFT                 (0U)
#define USB3_DB5_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB5_DB_target_SHIFT)) & USB3_DB5_DB_target_MASK)
#define USB3_DB5_DB_stream_ID_MASK               (0xFFFF0000U)
#define USB3_DB5_DB_stream_ID_SHIFT              (16U)
#define USB3_DB5_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB5_DB_stream_ID_SHIFT)) & USB3_DB5_DB_stream_ID_MASK)
/*! @} */

/*! @name DB6 - Doorbell Array */
/*! @{ */
#define USB3_DB6_DB_target_MASK                  (0xFFU)
#define USB3_DB6_DB_target_SHIFT                 (0U)
#define USB3_DB6_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB6_DB_target_SHIFT)) & USB3_DB6_DB_target_MASK)
#define USB3_DB6_DB_stream_ID_MASK               (0xFFFF0000U)
#define USB3_DB6_DB_stream_ID_SHIFT              (16U)
#define USB3_DB6_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB6_DB_stream_ID_SHIFT)) & USB3_DB6_DB_stream_ID_MASK)
/*! @} */

/*! @name DB7 - Doorbell Array */
/*! @{ */
#define USB3_DB7_DB_target_MASK                  (0xFFU)
#define USB3_DB7_DB_target_SHIFT                 (0U)
#define USB3_DB7_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB7_DB_target_SHIFT)) & USB3_DB7_DB_target_MASK)
#define USB3_DB7_DB_stream_ID_MASK               (0xFFFF0000U)
#define USB3_DB7_DB_stream_ID_SHIFT              (16U)
#define USB3_DB7_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB7_DB_stream_ID_SHIFT)) & USB3_DB7_DB_stream_ID_MASK)
/*! @} */

/*! @name DB8 - Doorbell Array */
/*! @{ */
#define USB3_DB8_DB_target_MASK                  (0xFFU)
#define USB3_DB8_DB_target_SHIFT                 (0U)
#define USB3_DB8_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB8_DB_target_SHIFT)) & USB3_DB8_DB_target_MASK)
#define USB3_DB8_DB_stream_ID_MASK               (0xFFFF0000U)
#define USB3_DB8_DB_stream_ID_SHIFT              (16U)
#define USB3_DB8_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB8_DB_stream_ID_SHIFT)) & USB3_DB8_DB_stream_ID_MASK)
/*! @} */

/*! @name DB9 - Doorbell Array */
/*! @{ */
#define USB3_DB9_DB_target_MASK                  (0xFFU)
#define USB3_DB9_DB_target_SHIFT                 (0U)
#define USB3_DB9_DB_target(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_DB9_DB_target_SHIFT)) & USB3_DB9_DB_target_MASK)
#define USB3_DB9_DB_stream_ID_MASK               (0xFFFF0000U)
#define USB3_DB9_DB_stream_ID_SHIFT              (16U)
#define USB3_DB9_DB_stream_ID(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_DB9_DB_stream_ID_SHIFT)) & USB3_DB9_DB_stream_ID_MASK)
/*! @} */

/*! @name DB10 - Doorbell Array */
/*! @{ */
#define USB3_DB10_DB_target_MASK                 (0xFFU)
#define USB3_DB10_DB_target_SHIFT                (0U)
#define USB3_DB10_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB10_DB_target_SHIFT)) & USB3_DB10_DB_target_MASK)
#define USB3_DB10_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB10_DB_stream_ID_SHIFT             (16U)
#define USB3_DB10_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB10_DB_stream_ID_SHIFT)) & USB3_DB10_DB_stream_ID_MASK)
/*! @} */

/*! @name DB11 - Doorbell Array */
/*! @{ */
#define USB3_DB11_DB_target_MASK                 (0xFFU)
#define USB3_DB11_DB_target_SHIFT                (0U)
#define USB3_DB11_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB11_DB_target_SHIFT)) & USB3_DB11_DB_target_MASK)
#define USB3_DB11_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB11_DB_stream_ID_SHIFT             (16U)
#define USB3_DB11_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB11_DB_stream_ID_SHIFT)) & USB3_DB11_DB_stream_ID_MASK)
/*! @} */

/*! @name DB12 - Doorbell Array */
/*! @{ */
#define USB3_DB12_DB_target_MASK                 (0xFFU)
#define USB3_DB12_DB_target_SHIFT                (0U)
#define USB3_DB12_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB12_DB_target_SHIFT)) & USB3_DB12_DB_target_MASK)
#define USB3_DB12_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB12_DB_stream_ID_SHIFT             (16U)
#define USB3_DB12_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB12_DB_stream_ID_SHIFT)) & USB3_DB12_DB_stream_ID_MASK)
/*! @} */

/*! @name DB13 - Doorbell Array */
/*! @{ */
#define USB3_DB13_DB_target_MASK                 (0xFFU)
#define USB3_DB13_DB_target_SHIFT                (0U)
#define USB3_DB13_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB13_DB_target_SHIFT)) & USB3_DB13_DB_target_MASK)
#define USB3_DB13_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB13_DB_stream_ID_SHIFT             (16U)
#define USB3_DB13_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB13_DB_stream_ID_SHIFT)) & USB3_DB13_DB_stream_ID_MASK)
/*! @} */

/*! @name DB14 - Doorbell Array */
/*! @{ */
#define USB3_DB14_DB_target_MASK                 (0xFFU)
#define USB3_DB14_DB_target_SHIFT                (0U)
#define USB3_DB14_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB14_DB_target_SHIFT)) & USB3_DB14_DB_target_MASK)
#define USB3_DB14_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB14_DB_stream_ID_SHIFT             (16U)
#define USB3_DB14_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB14_DB_stream_ID_SHIFT)) & USB3_DB14_DB_stream_ID_MASK)
/*! @} */

/*! @name DB15 - Doorbell Array */
/*! @{ */
#define USB3_DB15_DB_target_MASK                 (0xFFU)
#define USB3_DB15_DB_target_SHIFT                (0U)
#define USB3_DB15_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB15_DB_target_SHIFT)) & USB3_DB15_DB_target_MASK)
#define USB3_DB15_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB15_DB_stream_ID_SHIFT             (16U)
#define USB3_DB15_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB15_DB_stream_ID_SHIFT)) & USB3_DB15_DB_stream_ID_MASK)
/*! @} */

/*! @name DB16 - Doorbell Array */
/*! @{ */
#define USB3_DB16_DB_target_MASK                 (0xFFU)
#define USB3_DB16_DB_target_SHIFT                (0U)
#define USB3_DB16_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB16_DB_target_SHIFT)) & USB3_DB16_DB_target_MASK)
#define USB3_DB16_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB16_DB_stream_ID_SHIFT             (16U)
#define USB3_DB16_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB16_DB_stream_ID_SHIFT)) & USB3_DB16_DB_stream_ID_MASK)
/*! @} */

/*! @name DB17 - Doorbell Array */
/*! @{ */
#define USB3_DB17_DB_target_MASK                 (0xFFU)
#define USB3_DB17_DB_target_SHIFT                (0U)
#define USB3_DB17_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB17_DB_target_SHIFT)) & USB3_DB17_DB_target_MASK)
#define USB3_DB17_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB17_DB_stream_ID_SHIFT             (16U)
#define USB3_DB17_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB17_DB_stream_ID_SHIFT)) & USB3_DB17_DB_stream_ID_MASK)
/*! @} */

/*! @name DB18 - Doorbell Array */
/*! @{ */
#define USB3_DB18_DB_target_MASK                 (0xFFU)
#define USB3_DB18_DB_target_SHIFT                (0U)
#define USB3_DB18_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB18_DB_target_SHIFT)) & USB3_DB18_DB_target_MASK)
#define USB3_DB18_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB18_DB_stream_ID_SHIFT             (16U)
#define USB3_DB18_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB18_DB_stream_ID_SHIFT)) & USB3_DB18_DB_stream_ID_MASK)
/*! @} */

/*! @name DB19 - Doorbell Array */
/*! @{ */
#define USB3_DB19_DB_target_MASK                 (0xFFU)
#define USB3_DB19_DB_target_SHIFT                (0U)
#define USB3_DB19_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB19_DB_target_SHIFT)) & USB3_DB19_DB_target_MASK)
#define USB3_DB19_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB19_DB_stream_ID_SHIFT             (16U)
#define USB3_DB19_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB19_DB_stream_ID_SHIFT)) & USB3_DB19_DB_stream_ID_MASK)
/*! @} */

/*! @name DB20 - Doorbell Array */
/*! @{ */
#define USB3_DB20_DB_target_MASK                 (0xFFU)
#define USB3_DB20_DB_target_SHIFT                (0U)
#define USB3_DB20_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB20_DB_target_SHIFT)) & USB3_DB20_DB_target_MASK)
#define USB3_DB20_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB20_DB_stream_ID_SHIFT             (16U)
#define USB3_DB20_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB20_DB_stream_ID_SHIFT)) & USB3_DB20_DB_stream_ID_MASK)
/*! @} */

/*! @name DB21 - Doorbell Array */
/*! @{ */
#define USB3_DB21_DB_target_MASK                 (0xFFU)
#define USB3_DB21_DB_target_SHIFT                (0U)
#define USB3_DB21_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB21_DB_target_SHIFT)) & USB3_DB21_DB_target_MASK)
#define USB3_DB21_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB21_DB_stream_ID_SHIFT             (16U)
#define USB3_DB21_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB21_DB_stream_ID_SHIFT)) & USB3_DB21_DB_stream_ID_MASK)
/*! @} */

/*! @name DB22 - Doorbell Array */
/*! @{ */
#define USB3_DB22_DB_target_MASK                 (0xFFU)
#define USB3_DB22_DB_target_SHIFT                (0U)
#define USB3_DB22_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB22_DB_target_SHIFT)) & USB3_DB22_DB_target_MASK)
#define USB3_DB22_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB22_DB_stream_ID_SHIFT             (16U)
#define USB3_DB22_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB22_DB_stream_ID_SHIFT)) & USB3_DB22_DB_stream_ID_MASK)
/*! @} */

/*! @name DB23 - Doorbell Array */
/*! @{ */
#define USB3_DB23_DB_target_MASK                 (0xFFU)
#define USB3_DB23_DB_target_SHIFT                (0U)
#define USB3_DB23_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB23_DB_target_SHIFT)) & USB3_DB23_DB_target_MASK)
#define USB3_DB23_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB23_DB_stream_ID_SHIFT             (16U)
#define USB3_DB23_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB23_DB_stream_ID_SHIFT)) & USB3_DB23_DB_stream_ID_MASK)
/*! @} */

/*! @name DB24 - Doorbell Array */
/*! @{ */
#define USB3_DB24_DB_target_MASK                 (0xFFU)
#define USB3_DB24_DB_target_SHIFT                (0U)
#define USB3_DB24_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB24_DB_target_SHIFT)) & USB3_DB24_DB_target_MASK)
#define USB3_DB24_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB24_DB_stream_ID_SHIFT             (16U)
#define USB3_DB24_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB24_DB_stream_ID_SHIFT)) & USB3_DB24_DB_stream_ID_MASK)
/*! @} */

/*! @name DB25 - Doorbell Array */
/*! @{ */
#define USB3_DB25_DB_target_MASK                 (0xFFU)
#define USB3_DB25_DB_target_SHIFT                (0U)
#define USB3_DB25_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB25_DB_target_SHIFT)) & USB3_DB25_DB_target_MASK)
#define USB3_DB25_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB25_DB_stream_ID_SHIFT             (16U)
#define USB3_DB25_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB25_DB_stream_ID_SHIFT)) & USB3_DB25_DB_stream_ID_MASK)
/*! @} */

/*! @name DB26 - Doorbell Array */
/*! @{ */
#define USB3_DB26_DB_target_MASK                 (0xFFU)
#define USB3_DB26_DB_target_SHIFT                (0U)
#define USB3_DB26_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB26_DB_target_SHIFT)) & USB3_DB26_DB_target_MASK)
#define USB3_DB26_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB26_DB_stream_ID_SHIFT             (16U)
#define USB3_DB26_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB26_DB_stream_ID_SHIFT)) & USB3_DB26_DB_stream_ID_MASK)
/*! @} */

/*! @name DB27 - Doorbell Array */
/*! @{ */
#define USB3_DB27_DB_target_MASK                 (0xFFU)
#define USB3_DB27_DB_target_SHIFT                (0U)
#define USB3_DB27_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB27_DB_target_SHIFT)) & USB3_DB27_DB_target_MASK)
#define USB3_DB27_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB27_DB_stream_ID_SHIFT             (16U)
#define USB3_DB27_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB27_DB_stream_ID_SHIFT)) & USB3_DB27_DB_stream_ID_MASK)
/*! @} */

/*! @name DB28 - Doorbell Array */
/*! @{ */
#define USB3_DB28_DB_target_MASK                 (0xFFU)
#define USB3_DB28_DB_target_SHIFT                (0U)
#define USB3_DB28_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB28_DB_target_SHIFT)) & USB3_DB28_DB_target_MASK)
#define USB3_DB28_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB28_DB_stream_ID_SHIFT             (16U)
#define USB3_DB28_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB28_DB_stream_ID_SHIFT)) & USB3_DB28_DB_stream_ID_MASK)
/*! @} */

/*! @name DB29 - Doorbell Array */
/*! @{ */
#define USB3_DB29_DB_target_MASK                 (0xFFU)
#define USB3_DB29_DB_target_SHIFT                (0U)
#define USB3_DB29_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB29_DB_target_SHIFT)) & USB3_DB29_DB_target_MASK)
#define USB3_DB29_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB29_DB_stream_ID_SHIFT             (16U)
#define USB3_DB29_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB29_DB_stream_ID_SHIFT)) & USB3_DB29_DB_stream_ID_MASK)
/*! @} */

/*! @name DB30 - Doorbell Array */
/*! @{ */
#define USB3_DB30_DB_target_MASK                 (0xFFU)
#define USB3_DB30_DB_target_SHIFT                (0U)
#define USB3_DB30_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB30_DB_target_SHIFT)) & USB3_DB30_DB_target_MASK)
#define USB3_DB30_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB30_DB_stream_ID_SHIFT             (16U)
#define USB3_DB30_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB30_DB_stream_ID_SHIFT)) & USB3_DB30_DB_stream_ID_MASK)
/*! @} */

/*! @name DB31 - Doorbell Array */
/*! @{ */
#define USB3_DB31_DB_target_MASK                 (0xFFU)
#define USB3_DB31_DB_target_SHIFT                (0U)
#define USB3_DB31_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB31_DB_target_SHIFT)) & USB3_DB31_DB_target_MASK)
#define USB3_DB31_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB31_DB_stream_ID_SHIFT             (16U)
#define USB3_DB31_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB31_DB_stream_ID_SHIFT)) & USB3_DB31_DB_stream_ID_MASK)
/*! @} */

/*! @name DB32 - Doorbell Array */
/*! @{ */
#define USB3_DB32_DB_target_MASK                 (0xFFU)
#define USB3_DB32_DB_target_SHIFT                (0U)
#define USB3_DB32_DB_target(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DB32_DB_target_SHIFT)) & USB3_DB32_DB_target_MASK)
#define USB3_DB32_DB_stream_ID_MASK              (0xFFFF0000U)
#define USB3_DB32_DB_stream_ID_SHIFT             (16U)
#define USB3_DB32_DB_stream_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DB32_DB_stream_ID_SHIFT)) & USB3_DB32_DB_stream_ID_MASK)
/*! @} */

/*! @name XECP_PORT_CAP_REG - USB3 Extended capability */
/*! @{ */
#define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID_MASK (0xFFU)
#define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID_SHIFT (0U)
#define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID_SHIFT)) & USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_ID_MASK)
#define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW_MASK (0xFF00U)
#define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW_SHIFT (8U)
#define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW_SHIFT)) & USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAPABILITY_DW_MASK)
#define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV_MASK (0xFF0000U)
#define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV_SHIFT (16U)
#define USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV_SHIFT)) & USB3_XECP_PORT_CAP_REG_XHCI_PORT_CAP_REV_MASK)
#define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE_MASK (0x1000000U)
#define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE_SHIFT (24U)
#define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE_SHIFT)) & USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_CAPABLE_MASK)
#define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN_MASK (0x2000000U)
#define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN_SHIFT (25U)
#define USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN_SHIFT)) & USB3_XECP_PORT_CAP_REG_LPM_2_STB_SWITCH_EN_MASK)
/*! @} */

/*! @name XECP_PORT_1_REG - USB3 Extended capability */
/*! @{ */
#define USB3_XECP_PORT_1_REG_TRAINING_FAIL_MASK  (0x1U)
#define USB3_XECP_PORT_1_REG_TRAINING_FAIL_SHIFT (0U)
#define USB3_XECP_PORT_1_REG_TRAINING_FAIL(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_TRAINING_FAIL_SHIFT)) & USB3_XECP_PORT_1_REG_TRAINING_FAIL_MASK)
#define USB3_XECP_PORT_1_REG_TERM_DEB_MAX_MASK   (0x6U)
#define USB3_XECP_PORT_1_REG_TERM_DEB_MAX_SHIFT  (1U)
#define USB3_XECP_PORT_1_REG_TERM_DEB_MAX(x)     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_TERM_DEB_MAX_SHIFT)) & USB3_XECP_PORT_1_REG_TERM_DEB_MAX_MASK)
#define USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX_MASK (0x8U)
#define USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX_SHIFT (3U)
#define USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX_SHIFT)) & USB3_XECP_PORT_1_REG_U3_SPUR_LFPS_FIX_MASK)
#define USB3_XECP_PORT_1_REG_SKP_OS_FIX_MASK     (0x10U)
#define USB3_XECP_PORT_1_REG_SKP_OS_FIX_SHIFT    (4U)
#define USB3_XECP_PORT_1_REG_SKP_OS_FIX(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_SKP_OS_FIX_SHIFT)) & USB3_XECP_PORT_1_REG_SKP_OS_FIX_MASK)
#define USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN_MASK (0x20U)
#define USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN_SHIFT (5U)
#define USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN_SHIFT)) & USB3_XECP_PORT_1_REG_TTIME_FOR_RESET_EN_MASK)
#define USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME_MASK (0x7F00U)
#define USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME_SHIFT (8U)
#define USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME_SHIFT)) & USB3_XECP_PORT_1_REG_U1_LFPS_MINGEN_TIME_MASK)
#define USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE_MASK (0x8000U)
#define USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE_SHIFT (15U)
#define USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE_SHIFT)) & USB3_XECP_PORT_1_REG_U1_LFPS_TIME_WR_STROBE_MASK)
/*! @} */

/*! @name XECP_CDNS_DEBUG_BUS_CAP - xHCI Debug Bus Capability */
/*! @{ */
#define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID_MASK (0xFFU)
#define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID_SHIFT (0U)
#define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_CAP_ID_MASK)
#define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW_MASK (0xFF00U)
#define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW_SHIFT (8U)
#define USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_CAP_XHCI_DEBUG_BUS_DW_MASK)
#define USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en_MASK (0x80000000U)
#define USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en_SHIFT (31U)
#define USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_CAP_cpu_debug_en_MASK)
/*! @} */

/*! @name XECP_CDNS_DEBUG_BUS_CTRL - xHCI Debug Bus Control */
/*! @{ */
#define USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel_MASK (0x1FU)
#define USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel_SHIFT (0U)
#define USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_CTRL_cpu_debug_bus_sel_MASK)
/*! @} */

/*! @name XECP_CDNS_DEBUG_BUS_STATUS - xHCI Debug Bus Status */
/*! @{ */
#define USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus_MASK (0xFFFFFFFFU)
#define USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus_SHIFT (0U)
#define USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus_SHIFT)) & USB3_XECP_CDNS_DEBUG_BUS_STATUS_xhci_debug_bus_MASK)
/*! @} */

/*! @name XECP_PM_CAP - Extended Power Management capability */
/*! @{ */
#define USB3_XECP_PM_CAP_XHCI_PM_CAP_ID_MASK     (0xFFU)
#define USB3_XECP_PM_CAP_XHCI_PM_CAP_ID_SHIFT    (0U)
#define USB3_XECP_PM_CAP_XHCI_PM_CAP_ID(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_XHCI_PM_CAP_ID_SHIFT)) & USB3_XECP_PM_CAP_XHCI_PM_CAP_ID_MASK)
#define USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW_MASK (0xFF00U)
#define USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW_SHIFT (8U)
#define USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW_SHIFT)) & USB3_XECP_PM_CAP_XHCI_PM_CAPABILITY_DW_MASK)
#define USB3_XECP_PM_CAP_Version_MASK            (0x70000U)
#define USB3_XECP_PM_CAP_Version_SHIFT           (16U)
#define USB3_XECP_PM_CAP_Version(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_Version_SHIFT)) & USB3_XECP_PM_CAP_Version_MASK)
#define USB3_XECP_PM_CAP_PME_clock_MASK          (0x80000U)
#define USB3_XECP_PM_CAP_PME_clock_SHIFT         (19U)
#define USB3_XECP_PM_CAP_PME_clock(x)            (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_PME_clock_SHIFT)) & USB3_XECP_PM_CAP_PME_clock_MASK)
#define USB3_XECP_PM_CAP_reserved_MASK           (0x100000U)
#define USB3_XECP_PM_CAP_reserved_SHIFT          (20U)
#define USB3_XECP_PM_CAP_reserved(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_reserved_SHIFT)) & USB3_XECP_PM_CAP_reserved_MASK)
#define USB3_XECP_PM_CAP_DSI_MASK                (0x200000U)
#define USB3_XECP_PM_CAP_DSI_SHIFT               (21U)
#define USB3_XECP_PM_CAP_DSI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_DSI_SHIFT)) & USB3_XECP_PM_CAP_DSI_MASK)
#define USB3_XECP_PM_CAP_AUX_CURRENT_MASK        (0x1C00000U)
#define USB3_XECP_PM_CAP_AUX_CURRENT_SHIFT       (22U)
#define USB3_XECP_PM_CAP_AUX_CURRENT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_AUX_CURRENT_SHIFT)) & USB3_XECP_PM_CAP_AUX_CURRENT_MASK)
#define USB3_XECP_PM_CAP_D1_Support_MASK         (0x2000000U)
#define USB3_XECP_PM_CAP_D1_Support_SHIFT        (25U)
#define USB3_XECP_PM_CAP_D1_Support(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_D1_Support_SHIFT)) & USB3_XECP_PM_CAP_D1_Support_MASK)
#define USB3_XECP_PM_CAP_D2_Support_MASK         (0x4000000U)
#define USB3_XECP_PM_CAP_D2_Support_SHIFT        (26U)
#define USB3_XECP_PM_CAP_D2_Support(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_D2_Support_SHIFT)) & USB3_XECP_PM_CAP_D2_Support_MASK)
#define USB3_XECP_PM_CAP_PME_Support_MASK        (0xF8000000U)
#define USB3_XECP_PM_CAP_PME_Support_SHIFT       (27U)
#define USB3_XECP_PM_CAP_PME_Support(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_CAP_PME_Support_SHIFT)) & USB3_XECP_PM_CAP_PME_Support_MASK)
/*! @} */

/*! @name XECP_PM_PMCSR - Extended Power Management Control/Status */
/*! @{ */
#define USB3_XECP_PM_PMCSR_PowerState_MASK       (0x3U)
#define USB3_XECP_PM_PMCSR_PowerState_SHIFT      (0U)
#define USB3_XECP_PM_PMCSR_PowerState(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_PowerState_SHIFT)) & USB3_XECP_PM_PMCSR_PowerState_MASK)
#define USB3_XECP_PM_PMCSR_reserved1_MASK        (0x4U)
#define USB3_XECP_PM_PMCSR_reserved1_SHIFT       (2U)
#define USB3_XECP_PM_PMCSR_reserved1(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_reserved1_SHIFT)) & USB3_XECP_PM_PMCSR_reserved1_MASK)
#define USB3_XECP_PM_PMCSR_No_Soft_Reset_MASK    (0x8U)
#define USB3_XECP_PM_PMCSR_No_Soft_Reset_SHIFT   (3U)
#define USB3_XECP_PM_PMCSR_No_Soft_Reset(x)      (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_No_Soft_Reset_SHIFT)) & USB3_XECP_PM_PMCSR_No_Soft_Reset_MASK)
#define USB3_XECP_PM_PMCSR_reserved2_MASK        (0xF0U)
#define USB3_XECP_PM_PMCSR_reserved2_SHIFT       (4U)
#define USB3_XECP_PM_PMCSR_reserved2(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_reserved2_SHIFT)) & USB3_XECP_PM_PMCSR_reserved2_MASK)
#define USB3_XECP_PM_PMCSR_PME_En_MASK           (0x100U)
#define USB3_XECP_PM_PMCSR_PME_En_SHIFT          (8U)
#define USB3_XECP_PM_PMCSR_PME_En(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_PME_En_SHIFT)) & USB3_XECP_PM_PMCSR_PME_En_MASK)
#define USB3_XECP_PM_PMCSR_data_select_MASK      (0x1E00U)
#define USB3_XECP_PM_PMCSR_data_select_SHIFT     (9U)
#define USB3_XECP_PM_PMCSR_data_select(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_data_select_SHIFT)) & USB3_XECP_PM_PMCSR_data_select_MASK)
#define USB3_XECP_PM_PMCSR_data_scale_MASK       (0x6000U)
#define USB3_XECP_PM_PMCSR_data_scale_SHIFT      (13U)
#define USB3_XECP_PM_PMCSR_data_scale(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_data_scale_SHIFT)) & USB3_XECP_PM_PMCSR_data_scale_MASK)
#define USB3_XECP_PM_PMCSR_pme_status_MASK       (0x8000U)
#define USB3_XECP_PM_PMCSR_pme_status_SHIFT      (15U)
#define USB3_XECP_PM_PMCSR_pme_status(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_pme_status_SHIFT)) & USB3_XECP_PM_PMCSR_pme_status_MASK)
#define USB3_XECP_PM_PMCSR_reserved3_MASK        (0x3F0000U)
#define USB3_XECP_PM_PMCSR_reserved3_SHIFT       (16U)
#define USB3_XECP_PM_PMCSR_reserved3(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_reserved3_SHIFT)) & USB3_XECP_PM_PMCSR_reserved3_MASK)
#define USB3_XECP_PM_PMCSR_B2_B3_MASK            (0x400000U)
#define USB3_XECP_PM_PMCSR_B2_B3_SHIFT           (22U)
#define USB3_XECP_PM_PMCSR_B2_B3(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_B2_B3_SHIFT)) & USB3_XECP_PM_PMCSR_B2_B3_MASK)
#define USB3_XECP_PM_PMCSR_BPCC_EN_MASK          (0x800000U)
#define USB3_XECP_PM_PMCSR_BPCC_EN_SHIFT         (23U)
#define USB3_XECP_PM_PMCSR_BPCC_EN(x)            (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_BPCC_EN_SHIFT)) & USB3_XECP_PM_PMCSR_BPCC_EN_MASK)
#define USB3_XECP_PM_PMCSR_data_register_MASK    (0xFF000000U)
#define USB3_XECP_PM_PMCSR_data_register_SHIFT   (24U)
#define USB3_XECP_PM_PMCSR_data_register(x)      (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PM_PMCSR_data_register_SHIFT)) & USB3_XECP_PM_PMCSR_data_register_MASK)
/*! @} */

/*! @name XECP_MSI_CAP - MSI configuration */
/*! @{ */
#define USB3_XECP_MSI_CAP_MSI_ID_MASK            (0xFFU)
#define USB3_XECP_MSI_CAP_MSI_ID_SHIFT           (0U)
#define USB3_XECP_MSI_CAP_MSI_ID(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_MSI_ID_SHIFT)) & USB3_XECP_MSI_CAP_MSI_ID_MASK)
#define USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET_MASK (0xFF00U)
#define USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET_SHIFT (8U)
#define USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET_SHIFT)) & USB3_XECP_MSI_CAP_XECP_MSI_CAP_OFFSET_MASK)
#define USB3_XECP_MSI_CAP_MSI_en_MASK            (0x10000U)
#define USB3_XECP_MSI_CAP_MSI_en_SHIFT           (16U)
#define USB3_XECP_MSI_CAP_MSI_en(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_MSI_en_SHIFT)) & USB3_XECP_MSI_CAP_MSI_en_MASK)
#define USB3_XECP_MSI_CAP_MSI_MMC_MASK           (0xE0000U)
#define USB3_XECP_MSI_CAP_MSI_MMC_SHIFT          (17U)
#define USB3_XECP_MSI_CAP_MSI_MMC(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_MSI_MMC_SHIFT)) & USB3_XECP_MSI_CAP_MSI_MMC_MASK)
#define USB3_XECP_MSI_CAP_MSI_MME_MASK           (0x700000U)
#define USB3_XECP_MSI_CAP_MSI_MME_SHIFT          (20U)
#define USB3_XECP_MSI_CAP_MSI_MME(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_MSI_MME_SHIFT)) & USB3_XECP_MSI_CAP_MSI_MME_MASK)
#define USB3_XECP_MSI_CAP_AC64_MASK              (0x800000U)
#define USB3_XECP_MSI_CAP_AC64_SHIFT             (23U)
#define USB3_XECP_MSI_CAP_AC64(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_AC64_SHIFT)) & USB3_XECP_MSI_CAP_AC64_MASK)
#define USB3_XECP_MSI_CAP_per_vector_masking_MASK (0x1000000U)
#define USB3_XECP_MSI_CAP_per_vector_masking_SHIFT (24U)
#define USB3_XECP_MSI_CAP_per_vector_masking(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_CAP_per_vector_masking_SHIFT)) & USB3_XECP_MSI_CAP_per_vector_masking_MASK)
/*! @} */

/*! @name XECP_MSI_ADDR_L - Message Lower Address */
/*! @{ */
#define USB3_XECP_MSI_ADDR_L_reserved_MASK       (0x3U)
#define USB3_XECP_MSI_ADDR_L_reserved_SHIFT      (0U)
#define USB3_XECP_MSI_ADDR_L_reserved(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_ADDR_L_reserved_SHIFT)) & USB3_XECP_MSI_ADDR_L_reserved_MASK)
#define USB3_XECP_MSI_ADDR_L_MSI_addr_low_MASK   (0xFFFFFFFCU)
#define USB3_XECP_MSI_ADDR_L_MSI_addr_low_SHIFT  (2U)
#define USB3_XECP_MSI_ADDR_L_MSI_addr_low(x)     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_ADDR_L_MSI_addr_low_SHIFT)) & USB3_XECP_MSI_ADDR_L_MSI_addr_low_MASK)
/*! @} */

/*! @name XECP_MSI_ADDR_H - Message Upper Address */
/*! @{ */
#define USB3_XECP_MSI_ADDR_H_MSI_addr_hi_MASK    (0xFFFFFFFFU)
#define USB3_XECP_MSI_ADDR_H_MSI_addr_hi_SHIFT   (0U)
#define USB3_XECP_MSI_ADDR_H_MSI_addr_hi(x)      (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_ADDR_H_MSI_addr_hi_SHIFT)) & USB3_XECP_MSI_ADDR_H_MSI_addr_hi_MASK)
/*! @} */

/*! @name XECP_MSI_DATA - Message data */
/*! @{ */
#define USB3_XECP_MSI_DATA_MSI_data_MASK         (0xFFFFU)
#define USB3_XECP_MSI_DATA_MSI_data_SHIFT        (0U)
#define USB3_XECP_MSI_DATA_MSI_data(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_MSI_DATA_MSI_data_SHIFT)) & USB3_XECP_MSI_DATA_MSI_data_MASK)
/*! @} */

/*! @name XECP_AXI_CAP - AXI Master Wrapper Extended Capability */
/*! @{ */
#define USB3_XECP_AXI_CAP_AXI_CAP_ID_MASK        (0xFFU)
#define USB3_XECP_AXI_CAP_AXI_CAP_ID_SHIFT       (0U)
#define USB3_XECP_AXI_CAP_AXI_CAP_ID(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_CAP_ID_SHIFT)) & USB3_XECP_AXI_CAP_AXI_CAP_ID_MASK)
#define USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET_MASK (0xFF00U)
#define USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET_SHIFT (8U)
#define USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET_SHIFT)) & USB3_XECP_AXI_CAP_XECP_AXI_CAP_OFFSET_MASK)
#define USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64_MASK (0x10000U)
#define USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64_SHIFT (16U)
#define USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64_SHIFT)) & USB3_XECP_AXI_CAP_AXI_ADDRESS_WIDTH_64_MASK)
#define USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS_MASK (0x400000U)
#define USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS_SHIFT (22U)
#define USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS_SHIFT)) & USB3_XECP_AXI_CAP_AXI_MASTER_WRAPPER_SPLIT_BYTE_BURSTS_MASK)
#define USB3_XECP_AXI_CAP_AXI_DISABLE_OOO_MASK   (0x800000U)
#define USB3_XECP_AXI_CAP_AXI_DISABLE_OOO_SHIFT  (23U)
#define USB3_XECP_AXI_CAP_AXI_DISABLE_OOO(x)     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_DISABLE_OOO_SHIFT)) & USB3_XECP_AXI_CAP_AXI_DISABLE_OOO_MASK)
#define USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE_MASK (0x7000000U)
#define USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE_SHIFT (24U)
#define USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE_SHIFT)) & USB3_XECP_AXI_CAP_AXI_DATA_BUS_SIZE_MASK)
#define USB3_XECP_AXI_CAP_AXI_ERROR_MASK         (0x20000000U)
#define USB3_XECP_AXI_CAP_AXI_ERROR_SHIFT        (29U)
#define USB3_XECP_AXI_CAP_AXI_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_ERROR_SHIFT)) & USB3_XECP_AXI_CAP_AXI_ERROR_MASK)
#define USB3_XECP_AXI_CAP_AXI_IDLE_MASK          (0x40000000U)
#define USB3_XECP_AXI_CAP_AXI_IDLE_SHIFT         (30U)
#define USB3_XECP_AXI_CAP_AXI_IDLE(x)            (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_IDLE_SHIFT)) & USB3_XECP_AXI_CAP_AXI_IDLE_MASK)
#define USB3_XECP_AXI_CAP_AXI_HALT_MASK          (0x80000000U)
#define USB3_XECP_AXI_CAP_AXI_HALT_SHIFT         (31U)
#define USB3_XECP_AXI_CAP_AXI_HALT(x)            (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CAP_AXI_HALT_SHIFT)) & USB3_XECP_AXI_CAP_AXI_HALT_MASK)
/*! @} */

/*! @name XECP_AXI_CFG0 - AXI Master Wrapper Extended Capability Configuration */
/*! @{ */
#define USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT_MASK    (0x3FU)
#define USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT_SHIFT   (0U)
#define USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT_SHIFT)) & USB3_XECP_AXI_CFG0_AXI_MAX_WR_OT_MASK)
#define USB3_XECP_AXI_CFG0_AXI_WR_DEPTH_MASK     (0xFF00U)
#define USB3_XECP_AXI_CFG0_AXI_WR_DEPTH_SHIFT    (8U)
#define USB3_XECP_AXI_CFG0_AXI_WR_DEPTH(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CFG0_AXI_WR_DEPTH_SHIFT)) & USB3_XECP_AXI_CFG0_AXI_WR_DEPTH_MASK)
#define USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT_MASK    (0x3F0000U)
#define USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT_SHIFT   (16U)
#define USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT_SHIFT)) & USB3_XECP_AXI_CFG0_AXI_MAX_RD_OT_MASK)
#define USB3_XECP_AXI_CFG0_AXI_RD_DEPTH_MASK     (0xFF000000U)
#define USB3_XECP_AXI_CFG0_AXI_RD_DEPTH_SHIFT    (24U)
#define USB3_XECP_AXI_CFG0_AXI_RD_DEPTH(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CFG0_AXI_RD_DEPTH_SHIFT)) & USB3_XECP_AXI_CFG0_AXI_RD_DEPTH_MASK)
/*! @} */

/*! @name XECP_AXI_CTRL0 - AXI Master Wrapper Extended Capability Control */
/*! @{ */
#define USB3_XECP_AXI_CTRL0_AXI_BMAX_MASK        (0xFU)
#define USB3_XECP_AXI_CTRL0_AXI_BMAX_SHIFT       (0U)
#define USB3_XECP_AXI_CTRL0_AXI_BMAX(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CTRL0_AXI_BMAX_SHIFT)) & USB3_XECP_AXI_CTRL0_AXI_BMAX_MASK)
/*! @} */

/*! @name XECP_AXI_CTRL1 - AXI Master Wrapper Extended Capability Control */
/*! @{ */
#define USB3_XECP_AXI_CTRL1_AXI_WOT_MASK         (0x3FU)
#define USB3_XECP_AXI_CTRL1_AXI_WOT_SHIFT        (0U)
#define USB3_XECP_AXI_CTRL1_AXI_WOT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CTRL1_AXI_WOT_SHIFT)) & USB3_XECP_AXI_CTRL1_AXI_WOT_MASK)
#define USB3_XECP_AXI_CTRL1_AXI_ROT_MASK         (0x3F0000U)
#define USB3_XECP_AXI_CTRL1_AXI_ROT_SHIFT        (16U)
#define USB3_XECP_AXI_CTRL1_AXI_ROT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CTRL1_AXI_ROT_SHIFT)) & USB3_XECP_AXI_CTRL1_AXI_ROT_MASK)
/*! @} */

/*! @name XECP_AXI_CTRL2 - AXI Master Wrapper Extended Capability Control */
/*! @{ */
#define USB3_XECP_AXI_CTRL2_AXI_WTHRES_MASK      (0x1FU)
#define USB3_XECP_AXI_CTRL2_AXI_WTHRES_SHIFT     (0U)
#define USB3_XECP_AXI_CTRL2_AXI_WTHRES(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AXI_CTRL2_AXI_WTHRES_SHIFT)) & USB3_XECP_AXI_CTRL2_AXI_WTHRES_MASK)
/*! @} */

/*! @name XECP_SUPP_USB2_CAP0 - xHCI Supported Protocol Capability */
/*! @{ */
#define USB3_XECP_SUPP_USB2_CAP0_PID_MASK        (0xFFU)
#define USB3_XECP_SUPP_USB2_CAP0_PID_SHIFT       (0U)
#define USB3_XECP_SUPP_USB2_CAP0_PID(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP0_PID_SHIFT)) & USB3_XECP_SUPP_USB2_CAP0_PID_MASK)
#define USB3_XECP_SUPP_USB2_CAP0_NextCapID_MASK  (0xFF00U)
#define USB3_XECP_SUPP_USB2_CAP0_NextCapID_SHIFT (8U)
#define USB3_XECP_SUPP_USB2_CAP0_NextCapID(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP0_NextCapID_SHIFT)) & USB3_XECP_SUPP_USB2_CAP0_NextCapID_MASK)
#define USB3_XECP_SUPP_USB2_CAP0_Minor_Rev_MASK  (0xFF0000U)
#define USB3_XECP_SUPP_USB2_CAP0_Minor_Rev_SHIFT (16U)
#define USB3_XECP_SUPP_USB2_CAP0_Minor_Rev(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP0_Minor_Rev_SHIFT)) & USB3_XECP_SUPP_USB2_CAP0_Minor_Rev_MASK)
#define USB3_XECP_SUPP_USB2_CAP0_Major_Rev_MASK  (0xFF000000U)
#define USB3_XECP_SUPP_USB2_CAP0_Major_Rev_SHIFT (24U)
#define USB3_XECP_SUPP_USB2_CAP0_Major_Rev(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP0_Major_Rev_SHIFT)) & USB3_XECP_SUPP_USB2_CAP0_Major_Rev_MASK)
/*! @} */

/*! @name XECP_SUPP_USB2_CAP1 - xHCI Supported Protocol Capability */
/*! @{ */
#define USB3_XECP_SUPP_USB2_CAP1_USB_STRING_MASK (0xFFFFFFFFU)
#define USB3_XECP_SUPP_USB2_CAP1_USB_STRING_SHIFT (0U)
#define USB3_XECP_SUPP_USB2_CAP1_USB_STRING(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP1_USB_STRING_SHIFT)) & USB3_XECP_SUPP_USB2_CAP1_USB_STRING_MASK)
/*! @} */

/*! @name XECP_SUPP_USB2_CAP2 - xHCI Supported Protocol Capability */
/*! @{ */
#define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset_MASK (0xFFU)
#define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset_SHIFT (0U)
#define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Offset_MASK)
#define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count_MASK (0xFF00U)
#define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count_SHIFT (8U)
#define USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_Compatible_Port_Count_MASK)
#define USB3_XECP_SUPP_USB2_CAP2_L1C_MASK        (0x10000U)
#define USB3_XECP_SUPP_USB2_CAP2_L1C_SHIFT       (16U)
#define USB3_XECP_SUPP_USB2_CAP2_L1C(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_L1C_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_L1C_MASK)
#define USB3_XECP_SUPP_USB2_CAP2_HSO_MASK        (0x20000U)
#define USB3_XECP_SUPP_USB2_CAP2_HSO_SHIFT       (17U)
#define USB3_XECP_SUPP_USB2_CAP2_HSO(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_HSO_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_HSO_MASK)
#define USB3_XECP_SUPP_USB2_CAP2_IHI_MASK        (0x40000U)
#define USB3_XECP_SUPP_USB2_CAP2_IHI_SHIFT       (18U)
#define USB3_XECP_SUPP_USB2_CAP2_IHI(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_IHI_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_IHI_MASK)
#define USB3_XECP_SUPP_USB2_CAP2_HLC_MASK        (0x80000U)
#define USB3_XECP_SUPP_USB2_CAP2_HLC_SHIFT       (19U)
#define USB3_XECP_SUPP_USB2_CAP2_HLC(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_HLC_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_HLC_MASK)
#define USB3_XECP_SUPP_USB2_CAP2_HLC_BESL_MASK   (0x100000U)
#define USB3_XECP_SUPP_USB2_CAP2_HLC_BESL_SHIFT  (20U)
#define USB3_XECP_SUPP_USB2_CAP2_HLC_BESL(x)     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_HLC_BESL_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_HLC_BESL_MASK)
#define USB3_XECP_SUPP_USB2_CAP2_PSIC_MASK       (0xF0000000U)
#define USB3_XECP_SUPP_USB2_CAP2_PSIC_SHIFT      (28U)
#define USB3_XECP_SUPP_USB2_CAP2_PSIC(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_CAP2_PSIC_SHIFT)) & USB3_XECP_SUPP_USB2_CAP2_PSIC_MASK)
/*! @} */

/*! @name XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE - Protocol Slot Type */
/*! @{ */
#define USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST_MASK (0x1FU)
#define USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST_SHIFT (0U)
#define USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST_SHIFT)) & USB3_XECP_SUPP_USB2_PROTOCOL_SLOT_TYPE_PST_MASK)
/*! @} */

/*! @name XECP_PSI_FULL_SPEED - Protocol Speed ID */
/*! @{ */
#define USB3_XECP_PSI_FULL_SPEED_PSIV_MASK       (0xFU)
#define USB3_XECP_PSI_FULL_SPEED_PSIV_SHIFT      (0U)
#define USB3_XECP_PSI_FULL_SPEED_PSIV(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PSIV_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PSIV_MASK)
#define USB3_XECP_PSI_FULL_SPEED_PSIE_MASK       (0x30U)
#define USB3_XECP_PSI_FULL_SPEED_PSIE_SHIFT      (4U)
#define USB3_XECP_PSI_FULL_SPEED_PSIE(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PSIE_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PSIE_MASK)
#define USB3_XECP_PSI_FULL_SPEED_PLT_MASK        (0xC0U)
#define USB3_XECP_PSI_FULL_SPEED_PLT_SHIFT       (6U)
#define USB3_XECP_PSI_FULL_SPEED_PLT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PLT_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PLT_MASK)
#define USB3_XECP_PSI_FULL_SPEED_PFD_MASK        (0x100U)
#define USB3_XECP_PSI_FULL_SPEED_PFD_SHIFT       (8U)
#define USB3_XECP_PSI_FULL_SPEED_PFD(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PFD_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PFD_MASK)
#define USB3_XECP_PSI_FULL_SPEED_PSIM_MASK       (0xFFFF0000U)
#define USB3_XECP_PSI_FULL_SPEED_PSIM_SHIFT      (16U)
#define USB3_XECP_PSI_FULL_SPEED_PSIM(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_FULL_SPEED_PSIM_SHIFT)) & USB3_XECP_PSI_FULL_SPEED_PSIM_MASK)
/*! @} */

/*! @name XECP_PSI_LOW_SPEED - Protocol Speed ID */
/*! @{ */
#define USB3_XECP_PSI_LOW_SPEED_PSIV_MASK        (0xFU)
#define USB3_XECP_PSI_LOW_SPEED_PSIV_SHIFT       (0U)
#define USB3_XECP_PSI_LOW_SPEED_PSIV(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PSIV_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PSIV_MASK)
#define USB3_XECP_PSI_LOW_SPEED_PSIE_MASK        (0x30U)
#define USB3_XECP_PSI_LOW_SPEED_PSIE_SHIFT       (4U)
#define USB3_XECP_PSI_LOW_SPEED_PSIE(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PSIE_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PSIE_MASK)
#define USB3_XECP_PSI_LOW_SPEED_PLT_MASK         (0xC0U)
#define USB3_XECP_PSI_LOW_SPEED_PLT_SHIFT        (6U)
#define USB3_XECP_PSI_LOW_SPEED_PLT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PLT_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PLT_MASK)
#define USB3_XECP_PSI_LOW_SPEED_PFD_MASK         (0x100U)
#define USB3_XECP_PSI_LOW_SPEED_PFD_SHIFT        (8U)
#define USB3_XECP_PSI_LOW_SPEED_PFD(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PFD_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PFD_MASK)
#define USB3_XECP_PSI_LOW_SPEED_PSIM_MASK        (0xFFFF0000U)
#define USB3_XECP_PSI_LOW_SPEED_PSIM_SHIFT       (16U)
#define USB3_XECP_PSI_LOW_SPEED_PSIM(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_LOW_SPEED_PSIM_SHIFT)) & USB3_XECP_PSI_LOW_SPEED_PSIM_MASK)
/*! @} */

/*! @name XECP_PSI_HIGH_SPEED - Protocol Speed ID */
/*! @{ */
#define USB3_XECP_PSI_HIGH_SPEED_PSIV_MASK       (0xFU)
#define USB3_XECP_PSI_HIGH_SPEED_PSIV_SHIFT      (0U)
#define USB3_XECP_PSI_HIGH_SPEED_PSIV(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PSIV_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PSIV_MASK)
#define USB3_XECP_PSI_HIGH_SPEED_PSIE_MASK       (0x30U)
#define USB3_XECP_PSI_HIGH_SPEED_PSIE_SHIFT      (4U)
#define USB3_XECP_PSI_HIGH_SPEED_PSIE(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PSIE_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PSIE_MASK)
#define USB3_XECP_PSI_HIGH_SPEED_PLT_MASK        (0xC0U)
#define USB3_XECP_PSI_HIGH_SPEED_PLT_SHIFT       (6U)
#define USB3_XECP_PSI_HIGH_SPEED_PLT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PLT_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PLT_MASK)
#define USB3_XECP_PSI_HIGH_SPEED_PFD_MASK        (0x100U)
#define USB3_XECP_PSI_HIGH_SPEED_PFD_SHIFT       (8U)
#define USB3_XECP_PSI_HIGH_SPEED_PFD(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PFD_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PFD_MASK)
#define USB3_XECP_PSI_HIGH_SPEED_PSIM_MASK       (0xFFFF0000U)
#define USB3_XECP_PSI_HIGH_SPEED_PSIM_SHIFT      (16U)
#define USB3_XECP_PSI_HIGH_SPEED_PSIM(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_PSI_HIGH_SPEED_PSIM_SHIFT)) & USB3_XECP_PSI_HIGH_SPEED_PSIM_MASK)
/*! @} */

/*! @name XECP_SUPP_USB3_CAP0 - xHCI Supported Protocol Capability */
/*! @{ */
#define USB3_XECP_SUPP_USB3_CAP0_PID_MASK        (0xFFU)
#define USB3_XECP_SUPP_USB3_CAP0_PID_SHIFT       (0U)
#define USB3_XECP_SUPP_USB3_CAP0_PID(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP0_PID_SHIFT)) & USB3_XECP_SUPP_USB3_CAP0_PID_MASK)
#define USB3_XECP_SUPP_USB3_CAP0_NextCapID_MASK  (0xFF00U)
#define USB3_XECP_SUPP_USB3_CAP0_NextCapID_SHIFT (8U)
#define USB3_XECP_SUPP_USB3_CAP0_NextCapID(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP0_NextCapID_SHIFT)) & USB3_XECP_SUPP_USB3_CAP0_NextCapID_MASK)
#define USB3_XECP_SUPP_USB3_CAP0_Minor_Rev_MASK  (0xFF0000U)
#define USB3_XECP_SUPP_USB3_CAP0_Minor_Rev_SHIFT (16U)
#define USB3_XECP_SUPP_USB3_CAP0_Minor_Rev(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP0_Minor_Rev_SHIFT)) & USB3_XECP_SUPP_USB3_CAP0_Minor_Rev_MASK)
#define USB3_XECP_SUPP_USB3_CAP0_Major_Rev_MASK  (0xFF000000U)
#define USB3_XECP_SUPP_USB3_CAP0_Major_Rev_SHIFT (24U)
#define USB3_XECP_SUPP_USB3_CAP0_Major_Rev(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP0_Major_Rev_SHIFT)) & USB3_XECP_SUPP_USB3_CAP0_Major_Rev_MASK)
/*! @} */

/*! @name XECP_SUPP_USB3_CAP1 - xHCI Supported Protocol Capability */
/*! @{ */
#define USB3_XECP_SUPP_USB3_CAP1_USB_STRING_MASK (0xFFFFFFFFU)
#define USB3_XECP_SUPP_USB3_CAP1_USB_STRING_SHIFT (0U)
#define USB3_XECP_SUPP_USB3_CAP1_USB_STRING(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP1_USB_STRING_SHIFT)) & USB3_XECP_SUPP_USB3_CAP1_USB_STRING_MASK)
/*! @} */

/*! @name XECP_SUPP_USB3_CAP2 - xHCI Supported Protocol Capability; USB 3 */
/*! @{ */
#define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset_MASK (0xFFU)
#define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset_SHIFT (0U)
#define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset_SHIFT)) & USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Offset_MASK)
#define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count_MASK (0xFF00U)
#define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count_SHIFT (8U)
#define USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count_SHIFT)) & USB3_XECP_SUPP_USB3_CAP2_Compatible_Port_Count_MASK)
#define USB3_XECP_SUPP_USB3_CAP2_PSIC_MASK       (0xF0000000U)
#define USB3_XECP_SUPP_USB3_CAP2_PSIC_SHIFT      (28U)
#define USB3_XECP_SUPP_USB3_CAP2_PSIC(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_CAP2_PSIC_SHIFT)) & USB3_XECP_SUPP_USB3_CAP2_PSIC_MASK)
/*! @} */

/*! @name XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE - Protocol Slot Type */
/*! @{ */
#define USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST_MASK (0x1FU)
#define USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST_SHIFT (0U)
#define USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST_SHIFT)) & USB3_XECP_SUPP_USB3_PROTOCOL_SLOT_TYPE_PST_MASK)
/*! @} */

/*! @name PSI_SUPER_SPEED - Protocol Speed ID */
/*! @{ */
#define USB3_PSI_SUPER_SPEED_PSIV_MASK           (0xFU)
#define USB3_PSI_SUPER_SPEED_PSIV_SHIFT          (0U)
#define USB3_PSI_SUPER_SPEED_PSIV(x)             (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PSIV_SHIFT)) & USB3_PSI_SUPER_SPEED_PSIV_MASK)
#define USB3_PSI_SUPER_SPEED_PSIE_MASK           (0x30U)
#define USB3_PSI_SUPER_SPEED_PSIE_SHIFT          (4U)
#define USB3_PSI_SUPER_SPEED_PSIE(x)             (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PSIE_SHIFT)) & USB3_PSI_SUPER_SPEED_PSIE_MASK)
#define USB3_PSI_SUPER_SPEED_PLT_MASK            (0xC0U)
#define USB3_PSI_SUPER_SPEED_PLT_SHIFT           (6U)
#define USB3_PSI_SUPER_SPEED_PLT(x)              (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PLT_SHIFT)) & USB3_PSI_SUPER_SPEED_PLT_MASK)
#define USB3_PSI_SUPER_SPEED_PFD_MASK            (0x100U)
#define USB3_PSI_SUPER_SPEED_PFD_SHIFT           (8U)
#define USB3_PSI_SUPER_SPEED_PFD(x)              (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PFD_SHIFT)) & USB3_PSI_SUPER_SPEED_PFD_MASK)
#define USB3_PSI_SUPER_SPEED_PSIM_MASK           (0xFFFF0000U)
#define USB3_PSI_SUPER_SPEED_PSIM_SHIFT          (16U)
#define USB3_PSI_SUPER_SPEED_PSIM(x)             (((uint32_t)(((uint32_t)(x)) << USB3_PSI_SUPER_SPEED_PSIM_SHIFT)) & USB3_PSI_SUPER_SPEED_PSIM_MASK)
/*! @} */

/*! @name XECP_CMDM_STS0 - Command Ring related status */
/*! @{ */
#define USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193_MASK (0xFFU)
#define USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193_SHIFT (0U)
#define USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193_SHIFT)) & USB3_XECP_CMDM_STS0_VEND_DEF_CMDM_CAP_ID_193_MASK)
#define USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET_MASK (0xFF00U)
#define USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET_SHIFT (8U)
#define USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET_SHIFT)) & USB3_XECP_CMDM_STS0_XECP_CMDM_NEXT_CAP_OFFSET_MASK)
#define USB3_XECP_CMDM_STS0_cmd_running_MASK     (0x10000U)
#define USB3_XECP_CMDM_STS0_cmd_running_SHIFT    (16U)
#define USB3_XECP_CMDM_STS0_cmd_running(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_cmd_running_SHIFT)) & USB3_XECP_CMDM_STS0_cmd_running_MASK)
#define USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky_MASK (0x20000U)
#define USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky_SHIFT (17U)
#define USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky_SHIFT)) & USB3_XECP_CMDM_STS0_host_cmd_db_rang_sticky_MASK)
#define USB3_XECP_CMDM_STS0_stopping_cmd_ring_MASK (0x40000U)
#define USB3_XECP_CMDM_STS0_stopping_cmd_ring_SHIFT (18U)
#define USB3_XECP_CMDM_STS0_stopping_cmd_ring(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_stopping_cmd_ring_SHIFT)) & USB3_XECP_CMDM_STS0_stopping_cmd_ring_MASK)
#define USB3_XECP_CMDM_STS0_trm_stall_req_MASK   (0x100000U)
#define USB3_XECP_CMDM_STS0_trm_stall_req_SHIFT  (20U)
#define USB3_XECP_CMDM_STS0_trm_stall_req(x)     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_trm_stall_req_SHIFT)) & USB3_XECP_CMDM_STS0_trm_stall_req_MASK)
#define USB3_XECP_CMDM_STS0_trm_eperr_upd_req_MASK (0x200000U)
#define USB3_XECP_CMDM_STS0_trm_eperr_upd_req_SHIFT (21U)
#define USB3_XECP_CMDM_STS0_trm_eperr_upd_req(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_trm_eperr_upd_req_SHIFT)) & USB3_XECP_CMDM_STS0_trm_eperr_upd_req_MASK)
#define USB3_XECP_CMDM_STS0_dbm_ep_upd_req_MASK  (0x400000U)
#define USB3_XECP_CMDM_STS0_dbm_ep_upd_req_SHIFT (22U)
#define USB3_XECP_CMDM_STS0_dbm_ep_upd_req(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_dbm_ep_upd_req_SHIFT)) & USB3_XECP_CMDM_STS0_dbm_ep_upd_req_MASK)
#define USB3_XECP_CMDM_STS0_update_endpt_active_MASK (0x800000U)
#define USB3_XECP_CMDM_STS0_update_endpt_active_SHIFT (23U)
#define USB3_XECP_CMDM_STS0_update_endpt_active(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_update_endpt_active_SHIFT)) & USB3_XECP_CMDM_STS0_update_endpt_active_MASK)
#define USB3_XECP_CMDM_STS0_odma_address_dev_pending_MASK (0x1000000U)
#define USB3_XECP_CMDM_STS0_odma_address_dev_pending_SHIFT (24U)
#define USB3_XECP_CMDM_STS0_odma_address_dev_pending(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_odma_address_dev_pending_SHIFT)) & USB3_XECP_CMDM_STS0_odma_address_dev_pending_MASK)
#define USB3_XECP_CMDM_STS0_odma_address_dev_done_MASK (0x2000000U)
#define USB3_XECP_CMDM_STS0_odma_address_dev_done_SHIFT (25U)
#define USB3_XECP_CMDM_STS0_odma_address_dev_done(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_odma_address_dev_done_SHIFT)) & USB3_XECP_CMDM_STS0_odma_address_dev_done_MASK)
#define USB3_XECP_CMDM_STS0_cmdm_clr_db_req_MASK (0x4000000U)
#define USB3_XECP_CMDM_STS0_cmdm_clr_db_req_SHIFT (26U)
#define USB3_XECP_CMDM_STS0_cmdm_clr_db_req(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_cmdm_clr_db_req_SHIFT)) & USB3_XECP_CMDM_STS0_cmdm_clr_db_req_MASK)
#define USB3_XECP_CMDM_STS0_cmdm_stop_req_MASK   (0x8000000U)
#define USB3_XECP_CMDM_STS0_cmdm_stop_req_SHIFT  (27U)
#define USB3_XECP_CMDM_STS0_cmdm_stop_req(x)     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_cmdm_stop_req_SHIFT)) & USB3_XECP_CMDM_STS0_cmdm_stop_req_MASK)
#define USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req_MASK (0x10000000U)
#define USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req_SHIFT (28U)
#define USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req_SHIFT)) & USB3_XECP_CMDM_STS0_cmdm_cntx_lock_req_MASK)
#define USB3_XECP_CMDM_STS0_trm_cntx_in_use_MASK (0x20000000U)
#define USB3_XECP_CMDM_STS0_trm_cntx_in_use_SHIFT (29U)
#define USB3_XECP_CMDM_STS0_trm_cntx_in_use(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_trm_cntx_in_use_SHIFT)) & USB3_XECP_CMDM_STS0_trm_cntx_in_use_MASK)
#define USB3_XECP_CMDM_STS0_odma_cntx_in_use_MASK (0x40000000U)
#define USB3_XECP_CMDM_STS0_odma_cntx_in_use_SHIFT (30U)
#define USB3_XECP_CMDM_STS0_odma_cntx_in_use(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_odma_cntx_in_use_SHIFT)) & USB3_XECP_CMDM_STS0_odma_cntx_in_use_MASK)
#define USB3_XECP_CMDM_STS0_idma_cntx_in_use_MASK (0x80000000U)
#define USB3_XECP_CMDM_STS0_idma_cntx_in_use_SHIFT (31U)
#define USB3_XECP_CMDM_STS0_idma_cntx_in_use(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_STS0_idma_cntx_in_use_SHIFT)) & USB3_XECP_CMDM_STS0_idma_cntx_in_use_MASK)
/*! @} */

/*! @name XECP_CMDM_CTRL_REG1 - Command Manager Control */
/*! @{ */
#define USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable_MASK (0x1U)
#define USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable_SHIFT (0U)
#define USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_update_endpt_event_enable_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail_MASK (0x2U)
#define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail_SHIFT (1U)
#define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_fail_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr_MASK (0x4U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr_SHIFT (2U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4setdqptr_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en_MASK (0x8U)
#define USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en_SHIFT (3U)
#define USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_addr_dev_slst_bsr_check_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev_MASK (0x10U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev_SHIFT (4U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4rstdev_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg_MASK (0x20U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg_SHIFT (5U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enslot_reg_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr_MASK (0x40U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr_SHIFT (6U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4enaddr_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt_MASK (0x80U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt_SHIFT (7U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_cntx_4encfgendpt_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot_MASK (0x100U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot_SHIFT (8U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4en_slot_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt_MASK (0x200U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt_SHIFT (9U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_endpt_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device_MASK (0x400U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device_SHIFT (10U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4rst_device_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt_MASK (0x800U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt_SHIFT (11U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4cfg_endpt_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en_MASK (0x1000U)
#define USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en_SHIFT (12U)
#define USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_glob_tsp_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_init_retry_MASK (0x2000U)
#define USB3_XECP_CMDM_CTRL_REG1_init_retry_SHIFT (13U)
#define USB3_XECP_CMDM_CTRL_REG1_init_retry(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_init_retry_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_init_retry_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en_MASK (0x4000U)
#define USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en_SHIFT (14U)
#define USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_eval_epst_check_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot_MASK (0x8000U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot_SHIFT (15U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_ep_cntx_4dis_slot_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset_MASK (0x10000U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset_SHIFT (16U)
#define USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_clr_split_state_with_tspset_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass_MASK (0x20000U)
#define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass_SHIFT (17U)
#define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_pass_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass_MASK (0x40000U)
#define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass_SHIFT (18U)
#define USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_force_bandwidth_sys_pass_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan_MASK (0x80000U)
#define USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan_SHIFT (19U)
#define USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_report_bandwidth_skip_scan_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache_MASK (0x100000U)
#define USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache_SHIFT (20U)
#define USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_enable_max_ep_cache_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis_MASK (0x200000U)
#define USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis_SHIFT (21U)
#define USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_cfg_endpt_cntx_lock_dis_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_feature_retry_en_MASK (0x400000U)
#define USB3_XECP_CMDM_CTRL_REG1_feature_retry_en_SHIFT (22U)
#define USB3_XECP_CMDM_CTRL_REG1_feature_retry_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_feature_retry_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_feature_retry_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en_MASK (0x800000U)
#define USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en_SHIFT (23U)
#define USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_eval_cntx_bw_scan_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth_MASK (0xF000000U)
#define USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth_SHIFT (24U)
#define USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_default_isoch_ep_bandwidth_MASK)
#define USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth_MASK (0xF0000000U)
#define USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth_SHIFT (28U)
#define USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth_SHIFT)) & USB3_XECP_CMDM_CTRL_REG1_default_intr_ep_bandwidth_MASK)
/*! @} */

/*! @name XECP_CMDM_CTRL_REG2 - Command Manager Control */
/*! @{ */
#define USB3_XECP_CMDM_CTRL_REG2_clr_st_MASK     (0x3FFFU)
#define USB3_XECP_CMDM_CTRL_REG2_clr_st_SHIFT    (0U)
#define USB3_XECP_CMDM_CTRL_REG2_clr_st(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_clr_st_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_clr_st_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en_MASK (0x4000U)
#define USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en_SHIFT (14U)
#define USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_burst_size_default_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep_MASK (0x8000U)
#define USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep_SHIFT (15U)
#define USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_disable_stall_clr_ep_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en_MASK (0x10000U)
#define USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en_SHIFT (16U)
#define USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_increase_update_ep_priority_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en_MASK (0x20000U)
#define USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en_SHIFT (17U)
#define USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_trm_break_loop_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg_MASK (0x40000U)
#define USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg_SHIFT (18U)
#define USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_tsp_4set_dqptr_reg_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg_MASK (0x80000U)
#define USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg_SHIFT (19U)
#define USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_force_reset_endpt_reg_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys_MASK (0x100000U)
#define USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys_SHIFT (20U)
#define USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_set_dqptr_clr_ep_arys_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg_MASK (0x200000U)
#define USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg_SHIFT (21U)
#define USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_cmd_st_dis_reg_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal_MASK (0x400000U)
#define USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal_SHIFT (22U)
#define USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_enable_bw_cal_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg_MASK (0x800000U)
#define USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg_SHIFT (23U)
#define USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_clr_cntx_4rst_endpt_reg_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en_MASK (0x1000000U)
#define USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en_SHIFT (24U)
#define USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_move_xfer_dqptr_2cpl_dqptr_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd_MASK (0x2000000U)
#define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd_SHIFT (25U)
#define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stall_upd_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt_MASK (0x4000000U)
#define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt_SHIFT (26U)
#define USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_clr_ep_cntx_4stop_endpt_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis_MASK (0x8000000U)
#define USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis_SHIFT (27U)
#define USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_all_clk_gate_dis_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_SRE_MASK        (0x10000000U)
#define USB3_XECP_CMDM_CTRL_REG2_SRE_SHIFT       (28U)
#define USB3_XECP_CMDM_CTRL_REG2_SRE(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_SRE_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_SRE_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en_MASK (0x20000000U)
#define USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en_SHIFT (29U)
#define USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_slot_id_overide_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en_MASK (0x40000000U)
#define USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en_SHIFT (30U)
#define USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_stop_endpt_2ms_timeout_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en_MASK (0x80000000U)
#define USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en_SHIFT (31U)
#define USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG2_doing_2dw_ocntx_wr_en_MASK)
/*! @} */

/*! @name XECP_CMDM_CTRL_REG3 - Command Manager Control */
/*! @{ */
#define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL_MASK (0xFFU)
#define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL_SHIFT (0U)
#define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_DEFAULT_PORT_BANDWD_AVAIL_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL_MASK (0xFF00U)
#define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL_SHIFT (8U)
#define USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_DEFAULT_HS_BANDWD_AVAIL_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select_MASK (0x30000U)
#define USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select_SHIFT (16U)
#define USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_disable_slot_timer_select_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en_MASK (0x40000U)
#define USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en_SHIFT (18U)
#define USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_clr_trm_dma_cntx_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en_MASK (0x80000U)
#define USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en_SHIFT (19U)
#define USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_stop_2timeout_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en_MASK (0x100000U)
#define USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en_SHIFT (20U)
#define USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_break_cntx_lock_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en_MASK (0x200000U)
#define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en_SHIFT (21U)
#define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_stream_st_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop_MASK (0x400000U)
#define USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop_SHIFT (22U)
#define USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_allow_clr_4stop_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx_MASK (0x800000U)
#define USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx_SHIFT (23U)
#define USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_stream_always_update_cntx_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis_MASK (0x1000000U)
#define USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis_SHIFT (24U)
#define USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_set_burst_size_4prdc_dis_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en_MASK (0x2000000U)
#define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en_SHIFT (25U)
#define USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_stop_ep_clr_lcstream_id_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped_MASK (0x4000000U)
#define USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped_SHIFT (26U)
#define USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_update_cntx_when_stopped_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st_MASK (0x8000000U)
#define USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st_SHIFT (27U)
#define USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_disable_setdqptr_clr_stream_st_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr_MASK (0x10000000U)
#define USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr_SHIFT (28U)
#define USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_disable_non0ep_cntx_clr_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en_MASK (0x20000000U)
#define USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en_SHIFT (29U)
#define USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_extra_db_rm_4stop_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en_MASK (0x40000000U)
#define USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en_SHIFT (30U)
#define USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_ignore_hi_atomic_en_MASK)
#define USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en_MASK (0x80000000U)
#define USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en_SHIFT (31U)
#define USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en_SHIFT)) & USB3_XECP_CMDM_CTRL_REG3_frindex_wr_en_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_CAP - Host Control Capability */
/*! @{ */
#define USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192_MASK (0xFFU)
#define USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192_SHIFT)) & USB3_XECP_HOST_CTRL_CAP_VEND_DEF_HOST_CAP_ID_192_MASK)
#define USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET_MASK (0xFF00U)
#define USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET_SHIFT (8U)
#define USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET_SHIFT)) & USB3_XECP_HOST_CTRL_CAP_XECP_HOST_NEXT_CAP_OFFSET_MASK)
/*! @} */

/*! @name XECP_HOST_CLR_MASK_REG - Override Endpoint Flow Control */
/*! @{ */
#define USB3_XECP_HOST_CLR_MASK_REG_EP_dir_MASK  (0x1U)
#define USB3_XECP_HOST_CLR_MASK_REG_EP_dir_SHIFT (0U)
#define USB3_XECP_HOST_CLR_MASK_REG_EP_dir(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_MASK_REG_EP_dir_SHIFT)) & USB3_XECP_HOST_CLR_MASK_REG_EP_dir_MASK)
#define USB3_XECP_HOST_CLR_MASK_REG_EP_num_MASK  (0x1EU)
#define USB3_XECP_HOST_CLR_MASK_REG_EP_num_SHIFT (1U)
#define USB3_XECP_HOST_CLR_MASK_REG_EP_num(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_MASK_REG_EP_num_SHIFT)) & USB3_XECP_HOST_CLR_MASK_REG_EP_num_MASK)
#define USB3_XECP_HOST_CLR_MASK_REG_Slot_num_MASK (0x3E0U)
#define USB3_XECP_HOST_CLR_MASK_REG_Slot_num_SHIFT (5U)
#define USB3_XECP_HOST_CLR_MASK_REG_Slot_num(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_MASK_REG_Slot_num_SHIFT)) & USB3_XECP_HOST_CLR_MASK_REG_Slot_num_MASK)
/*! @} */

/*! @name XECP_HOST_CLR_IN_EP_VALID_REG - Clear Active IN EP ID Control */
/*! @{ */
#define USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num_MASK (0xFFFFFFFFU)
#define USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num_SHIFT (0U)
#define USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num_SHIFT)) & USB3_XECP_HOST_CLR_IN_EP_VALID_REG_port_num_MASK)
/*! @} */

/*! @name XECP_HOST_CLR_PMASK_REG - Clear Poll Mask Control */
/*! @{ */
#define USB3_XECP_HOST_CLR_PMASK_REG_EP_dir_MASK (0x1U)
#define USB3_XECP_HOST_CLR_PMASK_REG_EP_dir_SHIFT (0U)
#define USB3_XECP_HOST_CLR_PMASK_REG_EP_dir(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_PMASK_REG_EP_dir_SHIFT)) & USB3_XECP_HOST_CLR_PMASK_REG_EP_dir_MASK)
#define USB3_XECP_HOST_CLR_PMASK_REG_EP_num_MASK (0x1EU)
#define USB3_XECP_HOST_CLR_PMASK_REG_EP_num_SHIFT (1U)
#define USB3_XECP_HOST_CLR_PMASK_REG_EP_num(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_PMASK_REG_EP_num_SHIFT)) & USB3_XECP_HOST_CLR_PMASK_REG_EP_num_MASK)
#define USB3_XECP_HOST_CLR_PMASK_REG_Slot_num_MASK (0x3E0U)
#define USB3_XECP_HOST_CLR_PMASK_REG_Slot_num_SHIFT (5U)
#define USB3_XECP_HOST_CLR_PMASK_REG_Slot_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CLR_PMASK_REG_Slot_num_SHIFT)) & USB3_XECP_HOST_CLR_PMASK_REG_Slot_num_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_OCRD_REG - Port Credit Control */
/*! @{ */
#define USB3_XECP_HOST_CTRL_OCRD_REG_port_num_MASK (0xFFU)
#define USB3_XECP_HOST_CTRL_OCRD_REG_port_num_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_OCRD_REG_port_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_port_num_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_port_num_MASK)
#define USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg_MASK (0x4000000U)
#define USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg_SHIFT (26U)
#define USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_st_upd_reg_MASK)
#define USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo_MASK (0x8000000U)
#define USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo_SHIFT (27U)
#define USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_minus_4rfifo_MASK)
#define USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd_MASK (0x10000000U)
#define USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd_SHIFT (28U)
#define USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_minus_ocrd_MASK)
#define USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd_MASK (0x20000000U)
#define USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd_SHIFT (29U)
#define USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_plus_ocrd_MASK)
#define USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st_MASK (0x40000000U)
#define USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st_SHIFT (30U)
#define USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_clr_cpl_st_MASK)
#define USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st_MASK (0x80000000U)
#define USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st_SHIFT (31U)
#define USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st_SHIFT)) & USB3_XECP_HOST_CTRL_OCRD_REG_clr_xfer_st_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_TEST_BUS_LO - Test Bus Low */
/*! @{ */
#define USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO_MASK (0xFFFFFFFFU)
#define USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO_SHIFT)) & USB3_XECP_HOST_CTRL_TEST_BUS_LO_TEST_BUS_LO_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_TEST_BUS_HI - Test Bus High */
/*! @{ */
#define USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI_MASK (0xFFFFFFFFU)
#define USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI_SHIFT)) & USB3_XECP_HOST_CTRL_TEST_BUS_HI_TEST_BUS_HI_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_TRM_REG1 - Host Control Transfer Manager */
/*! @{ */
#define USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable_MASK (0x1U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_in_td_pace_enable_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy_MASK (0x2U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy_SHIFT (1U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_fc_4inrdy_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en_MASK (0x4U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en_SHIFT (2U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_link_nop_sucess_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall_MASK (0x8U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall_SHIFT (3U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_stall_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable_MASK (0x10U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable_SHIFT (4U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_xport_crd_disable_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en_MASK (0x20U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en_SHIFT (5U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_cpl_pkt_clr_mask_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable_MASK (0x40U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable_SHIFT (6U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_en_bb_port_disable_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable_MASK (0x80U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable_SHIFT (7U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_npkt0_fc_disable_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en_MASK (0x100U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en_SHIFT (8U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_trb_cache_invalide_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable_MASK (0x200U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable_SHIFT (9U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_in_npkt_pace_disable_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en_MASK (0x400U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en_SHIFT (10U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_flush_2clr_valid_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry_MASK (0x800U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry_SHIFT (11U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_ctrl_reg_clr_bndry_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en_MASK (0x1000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en_SHIFT (12U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_ENT_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en_MASK (0x2000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en_SHIFT (13U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_single_burst_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en_MASK (0x4000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en_SHIFT (14U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_xfer_block_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en_MASK (0x8000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en_SHIFT (15U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_iso_0len_lpf_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en_MASK (0x10000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en_SHIFT (16U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_set_addr_err_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en_MASK (0x20000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en_SHIFT (17U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_phase1_imd_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td_MASK (0x40000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td_SHIFT (18U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_no_op_as_td_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en_MASK (0x80000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en_SHIFT (19U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_short_err_4msi_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en_MASK (0x100000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en_SHIFT (20U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_deadlock_detect_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop_MASK (0x200000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop_SHIFT (21U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_erdy_drop_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en_MASK (0x400000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en_SHIFT (22U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_cpl_db_rang_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo_MASK (0x800000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo_SHIFT (23U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_write_erdp_lo_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma_MASK (0x1000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma_SHIFT (24U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_imd_4nodma_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en_MASK (0x2000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en_SHIFT (25U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_trb_err_rm_db_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en_MASK (0x4000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en_SHIFT (26U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_ep_halt_2retry_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd_MASK (0x8000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd_SHIFT (27U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_enable_noop_upd_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err_MASK (0x10000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err_SHIFT (28U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_ppipe_err_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err_MASK (0x20000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err_SHIFT (29U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_disable_cpl_sst_mdata_err_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en_MASK (0x40000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en_SHIFT (30U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_usb2_nak_auto_detect_reg_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en_MASK (0x80000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en_SHIFT (31U)
#define USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG1_trb_pace_en_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_SCH_REG1 - Host Control Scheduler */
/*! @{ */
#define USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis_MASK (0x1U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_poll_delay_dis_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid_MASK (0x2U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid_SHIFT (1U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_trm_active_in_ep_valid_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_2_MASK  (0x4U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_2_SHIFT (2U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_2(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_2_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_2_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop_MASK (0x8U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop_SHIFT (3U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_tte_enable_introut_overlap_stop_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern_MASK (0x30U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern_SHIFT (4U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_sort_pattern_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf_MASK (0x40U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf_SHIFT (6U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_out_max_perf_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf_MASK (0x80U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf_SHIFT (7U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_perf_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en_MASK (0x100U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en_SHIFT (8U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_scratch_pad_en_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_maxEP_MASK  (0x600U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_maxEP_SHIFT (9U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_maxEP(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_maxEP_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_maxEP_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl_MASK (0x1800U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl_SHIFT (11U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_cache_size_ctrl_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0_MASK  (0x2000U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0_SHIFT (13U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_0_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1_MASK  (0x4000U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1_SHIFT (14U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_1_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2_MASK  (0x8000U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2_SHIFT (15U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_2_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3_MASK  (0x30000U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3_SHIFT (16U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_3_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix_MASK (0x40000U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix_SHIFT (18U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_iso_fix_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix_MASK (0x80000U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix_SHIFT (19U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_disable_gl_hub_int_fix_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4_MASK  (0x100000U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4_SHIFT (20U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_TTE_4_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc_MASK (0x200000U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc_SHIFT (21U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_stop_serve_nc_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check_MASK (0xC00000U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check_SHIFT (22U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_cclk_prdc_done_check_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis_MASK (0x1000000U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis_SHIFT (24U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_prdc_cc_dis_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins_MASK (0x2000000U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins_SHIFT (25U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_tt_overlap_all_ins_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref_MASK (0x4000000U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref_SHIFT (26U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_async_1pkt_split_pref_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en_MASK (0x8000000U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en_SHIFT (27U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_block_pending_en_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc_MASK (0xF0000000U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc_SHIFT (28U)
#define USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG1_sch_limit_prdc_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_ODMA_REG - Host Control ODMA */
/*! @{ */
#define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en_MASK (0x1U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_en_MASK)
#define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len_MASK (0x6U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len_SHIFT (1U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_EP_trans_timeout_len_MASK)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle_MASK (0x8U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle_SHIFT (3U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_rd_to_idle_MASK)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle_MASK (0x10U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle_SHIFT (4U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_resp_to_idle_MASK)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle_MASK (0x20U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle_SHIFT (5U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_completion_to_idle_MASK)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle_MASK (0x40U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle_SHIFT (6U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_set_addr_to_idle_MASK)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_7_MASK (0x80U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_7_SHIFT (7U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_7(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_7_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_7_MASK)
#define USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks_MASK (0x100U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks_SHIFT (8U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_clear_cntx_locks_MASK)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_9_MASK (0x200U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_9_SHIFT (9U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_9(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_9_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_9_MASK)
#define USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick_MASK (0x400U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick_SHIFT (10U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_ep_timer_tick_MASK)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_11_MASK (0x800U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_11_SHIFT (11U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_odma_11(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_odma_11_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_odma_11_MASK)
#define USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer_MASK (0x1000U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer_SHIFT (12U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_EP_base_timer_MASK)
#define USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en_MASK (0x2000U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en_SHIFT (13U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_ACK_crd_check_en_MASK)
#define USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout_MASK (0x4000U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout_SHIFT (14U)
#define USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout_SHIFT)) & USB3_XECP_HOST_CTRL_ODMA_REG_speed_up_timeout_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_IDMA_REG - Host Control IDMA */
/*! @{ */
#define USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en_MASK (0x1U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_EP_trans_timeout_en_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick_MASK (0x6U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick_SHIFT (1U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_EP_timer_tick_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse_MASK (0x8U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse_SHIFT (3U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_restore_pulse_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse_MASK (0x10U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse_SHIFT (4U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_restore_rdp_credits_pulse_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse_MASK (0x20U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse_SHIFT (5U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_ack_pst_clr_pulse_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse_MASK (0x40U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse_SHIFT (6U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_dm_pst_clr_pulse_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks_MASK (0x80U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks_SHIFT (7U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_clear_cntx_locks_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable_MASK (0x100U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable_SHIFT (8U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_compliance_iso_enable_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_9_MASK (0x200U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_9_SHIFT (9U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_9(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_9_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_9_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0_MASK (0x400U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0_SHIFT (10U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick0_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy_MASK (0x800U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy_SHIFT (11U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_seq_num_adj_on_nrdy_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout_MASK (0x1000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout_SHIFT (12U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_speed_up_timeout_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_13_MASK (0x2000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_13_SHIFT (13U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_13(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_13_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_13_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_14_MASK (0x4000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_14_SHIFT (14U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_14(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_14_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_14_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_15_MASK (0x8000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_15_SHIFT (15U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_15(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_15_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_15_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set_MASK (0x10000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set_SHIFT (16U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_ptr_buf_room_set_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_17_MASK (0x20000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_17_SHIFT (17U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_17(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_17_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_17_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit_MASK (0x40000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit_SHIFT (18U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_addr_fifo_flush_bit_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19_MASK (0xF80000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19_SHIFT (19U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_23_19_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_24_MASK (0x1000000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_24_SHIFT (24U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_24(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_24_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_24_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_25_MASK (0x2000000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_25_SHIFT (25U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_25(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_25_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_25_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1_MASK (0x4000000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1_SHIFT (26U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_timer_tick1_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_27_MASK (0x8000000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_27_SHIFT (27U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_27(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_27_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_27_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_28_MASK (0x10000000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_28_SHIFT (28U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_idma_28(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_idma_28_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_idma_28_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en_MASK (0x20000000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en_SHIFT (29U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_db_event_gen_en_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_event_priority_MASK (0x40000000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_event_priority_SHIFT (30U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_event_priority(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_event_priority_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_event_priority_MASK)
#define USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis_MASK (0x80000000U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis_SHIFT (31U)
#define USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis_SHIFT)) & USB3_XECP_HOST_CTRL_IDMA_REG_event_fifo_dis_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_PORT_CTRL - Global Port Control */
/*! @{ */
#define USB3_XECP_HOST_CTRL_PORT_CTRL_res1_MASK  (0xFU)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_res1_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_res1(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_res1_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_res1_MASK)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits_MASK (0x1F0U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits_SHIFT (4U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_test_bus_sel_ctrl_bits_MASK)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket_MASK (0x800U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket_SHIFT (11U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_PCIe_gasket_MASK)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt_MASK (0x1000U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt_SHIFT (12U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_enable_itp_xmt_MASK)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk_MASK (0x1E000U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk_SHIFT (13U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_hbuf_water_mark_reg_cclk_MASK)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en_MASK (0x20000U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en_SHIFT (17U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_overflow_sys_err_en_MASK)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en_MASK (0x40000U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en_SHIFT (18U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_rd_wr_addr_conflict_en_MASK)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en_MASK (0x80000U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en_SHIFT (19U)
#define USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_CTRL_lock_header_data_en_MASK)
/*! @} */

/*! @name XECP_AUX_CTRL_REG - AUX Reset Control */
/*! @{ */
#define USB3_XECP_AUX_CTRL_REG_force_fd_rst_MASK (0x3U)
#define USB3_XECP_AUX_CTRL_REG_force_fd_rst_SHIFT (0U)
#define USB3_XECP_AUX_CTRL_REG_force_fd_rst(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_force_fd_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_force_fd_rst_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst_MASK (0x4U)
#define USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst_SHIFT (2U)
#define USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_perst_4fd_rst_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup_MASK (0x8U)
#define USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup_SHIFT (3U)
#define USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_perst_4main_pwrup_MASK)
#define USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en_MASK (0x10U)
#define USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en_SHIFT (4U)
#define USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_pm_ctrl_main_rst_en_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst_MASK (0x20U)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst_SHIFT (5U)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_rst_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy_MASK (0x40U)
#define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy_SHIFT (6U)
#define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_2usb_phy_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy_MASK (0x80U)
#define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy_SHIFT (7U)
#define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_2usb_phy_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy_MASK (0x100U)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy_SHIFT (8U)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcie_phy_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore_MASK (0x200U)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore_SHIFT (9U)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2pcore_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port_MASK (0x400U)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port_SHIFT (10U)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u2port_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port_MASK (0x800U)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port_SHIFT (11U)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_4u3port_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port_MASK (0x1000U)
#define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port_SHIFT (12U)
#define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4u3port_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port_MASK (0x2000U)
#define USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port_SHIFT (13U)
#define USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hot_rst_4u3port_MASK)
#define USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en_MASK (0x4000U)
#define USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en_SHIFT (14U)
#define USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_pcie_linkdown_rst_en_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon_MASK (0x8000U)
#define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon_SHIFT (15U)
#define USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_warm_rst_4uphy_pon_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst_MASK (0x10000U)
#define USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst_SHIFT (16U)
#define USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_mac_phy_pipe_rst_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy_MASK (0x20000U)
#define USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy_SHIFT (17U)
#define USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hc_rst_2pcie_phy_MASK)
#define USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main_MASK (0x40000U)
#define USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main_SHIFT (18U)
#define USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main_SHIFT)) & USB3_XECP_AUX_CTRL_REG_eeprom_load_on_main_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore_MASK (0x80000U)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore_SHIFT (19U)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_hc_2pcore_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon_MASK (0x100000U)
#define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon_SHIFT (20U)
#define USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hc_warm_rst_4uphy_pon_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2_MASK (0x200000U)
#define USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2_SHIFT (21U)
#define USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_hcreset_4usb2_MASK)
#define USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse_MASK (0x400000U)
#define USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse_SHIFT (22U)
#define USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse_SHIFT)) & USB3_XECP_AUX_CTRL_REG_cold_rst_n_pulse_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy_MASK (0x800000U)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy_SHIFT (23U)
#define USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_main_pwrup_2usb_phy_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport_MASK (0x1000000U)
#define USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport_SHIFT (24U)
#define USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_linkdown_rst_4uport_MASK)
#define USB3_XECP_AUX_CTRL_REG_fast_sim_rst_MASK (0x2000000U)
#define USB3_XECP_AUX_CTRL_REG_fast_sim_rst_SHIFT (25U)
#define USB3_XECP_AUX_CTRL_REG_fast_sim_rst(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_fast_sim_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG_fast_sim_rst_MASK)
#define USB3_XECP_AUX_CTRL_REG_ignore_perst_en_MASK (0x4000000U)
#define USB3_XECP_AUX_CTRL_REG_ignore_perst_en_SHIFT (26U)
#define USB3_XECP_AUX_CTRL_REG_ignore_perst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_ignore_perst_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_ignore_perst_en_MASK)
#define USB3_XECP_AUX_CTRL_REG_perst_4main_en_MASK (0x8000000U)
#define USB3_XECP_AUX_CTRL_REG_perst_4main_en_SHIFT (27U)
#define USB3_XECP_AUX_CTRL_REG_perst_4main_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_perst_4main_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_perst_4main_en_MASK)
#define USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en_MASK (0x10000000U)
#define USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en_SHIFT (28U)
#define USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG_perst_2pwdown_en_MASK)
#define USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel_MASK (0x20000000U)
#define USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel_SHIFT (29U)
#define USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel_SHIFT)) & USB3_XECP_AUX_CTRL_REG_pcie_phy_rst_sel_MASK)
#define USB3_XECP_AUX_CTRL_REG_perst_filter_dis_MASK (0x40000000U)
#define USB3_XECP_AUX_CTRL_REG_perst_filter_dis_SHIFT (30U)
#define USB3_XECP_AUX_CTRL_REG_perst_filter_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG_perst_filter_dis_SHIFT)) & USB3_XECP_AUX_CTRL_REG_perst_filter_dis_MASK)
/*! @} */

/*! @name XECP_HOST_BW_OV_SS_REG - Super Speed Bandwidth Overload */
/*! @{ */
#define USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc_MASK (0xFFFU)
#define USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc_SHIFT (0U)
#define USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc_SHIFT)) & USB3_XECP_HOST_BW_OV_SS_REG_ss_bw_calc_MASK)
#define USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw_MASK (0xFFF000U)
#define USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw_SHIFT (12U)
#define USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw_SHIFT)) & USB3_XECP_HOST_BW_OV_SS_REG_max_tt_bw_MASK)
/*! @} */

/*! @name XECP_HOST_BW_OV_HS_REG - High Speed TT Bandwidth Overload */
/*! @{ */
#define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt_MASK (0xFFFU)
#define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt_SHIFT (0U)
#define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt_SHIFT)) & USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_tt_MASK)
#define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_MASK (0xFFF000U)
#define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_SHIFT (12U)
#define USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_SHIFT)) & USB3_XECP_HOST_BW_OV_HS_REG_bw_ov_hs_MASK)
/*! @} */

/*! @name XECP_HOST_BW_OV_FS_LS_REG - Bandwidth Overload Full and Low Speed */
/*! @{ */
#define USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc_MASK (0xFFFU)
#define USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc_SHIFT (0U)
#define USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc_SHIFT)) & USB3_XECP_HOST_BW_OV_FS_LS_REG_ls_bw_calc_MASK)
#define USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc_MASK (0xFFF000U)
#define USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc_SHIFT (12U)
#define USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc_SHIFT)) & USB3_XECP_HOST_BW_OV_FS_LS_REG_fs_bw_calc_MASK)
/*! @} */

/*! @name XECP_HOST_BW_OV_SYS_REG - System Bandwidth Overload */
/*! @{ */
#define USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc_MASK (0xFFFU)
#define USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc_SHIFT (0U)
#define USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc_SHIFT)) & USB3_XECP_HOST_BW_OV_SYS_REG_sys_bw_calc_MASK)
#define USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt_MASK (0xFFF000U)
#define USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt_SHIFT (12U)
#define USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt_SHIFT)) & USB3_XECP_HOST_BW_OV_SYS_REG_bw_ov_sys_tt_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG - Scheduler Async Delay */
/*! @{ */
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def_MASK (0x7U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_def_MASK)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en_MASK (0x8U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en_SHIFT (3U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_ls_ctrl_delay_en_MASK)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def_MASK (0x70U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def_SHIFT (4U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_def_MASK)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en_MASK (0x80U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en_SHIFT (7U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_ctrl_delay_en_MASK)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def_MASK (0x700U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def_SHIFT (8U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_def_MASK)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en_MASK (0x800U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en_SHIFT (11U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_ctrl_delay_en_MASK)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def_MASK (0x7000U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def_SHIFT (12U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_def_MASK)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en_MASK (0x8000U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en_SHIFT (15U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_fs_bulk_delay_en_MASK)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def_MASK (0x70000U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def_SHIFT (16U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_def_MASK)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en_MASK (0x80000U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en_SHIFT (19U)
#define USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_ASYNC_DELAY_REG_hs_bulk_delay_en_MASK)
/*! @} */

/*! @name XECP_UPORTS_PON_RST_REG - AUX Power PHY Reset */
/*! @{ */
#define USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num_MASK (0xFU)
#define USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num_SHIFT (0U)
#define USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num_SHIFT)) & USB3_XECP_UPORTS_PON_RST_REG_usb_phy_port_num_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_TRM_REG3 - Host Control Transfer Manager (TRM) */
/*! @{ */
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache_MASK (0x1U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_cache_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead_MASK (0x2U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead_SHIFT (1U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_lookahead_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid_MASK (0x4U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid_SHIFT (2U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_hit_invalid_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug_MASK (0x8U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug_SHIFT (3U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_cache_debug_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos_MASK (0x30U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos_SHIFT (4U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_look_pos_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc_MASK (0x40U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc_SHIFT (6U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_defer_bc_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double_MASK (0x80U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double_SHIFT (7U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cfg_en_miss_double_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en_MASK (0x100U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en_SHIFT (8U)
#define USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG3_cpl_extra_db_rang_en_MASK)
/*! @} */

/*! @name XECP_AUX_CTRL_REG1 - AUX Power Management Control 1 */
/*! @{ */
#define USB3_XECP_AUX_CTRL_REG1_force_pm_state_MASK (0x1U)
#define USB3_XECP_AUX_CTRL_REG1_force_pm_state_SHIFT (0U)
#define USB3_XECP_AUX_CTRL_REG1_force_pm_state(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_force_pm_state_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_force_pm_state_MASK)
#define USB3_XECP_AUX_CTRL_REG1_pm_state_MASK    (0x1EU)
#define USB3_XECP_AUX_CTRL_REG1_pm_state_SHIFT   (1U)
#define USB3_XECP_AUX_CTRL_REG1_pm_state(x)      (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_pm_state_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_pm_state_MASK)
#define USB3_XECP_AUX_CTRL_REG1_enable_p2_enter_MASK (0x20U)
#define USB3_XECP_AUX_CTRL_REG1_enable_p2_enter_SHIFT (5U)
#define USB3_XECP_AUX_CTRL_REG1_enable_p2_enter(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_enable_p2_enter_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_enable_p2_enter_MASK)
#define USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en_MASK (0x40U)
#define USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en_SHIFT (6U)
#define USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_p2_overwrite_p1_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en_MASK (0x80U)
#define USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en_SHIFT (7U)
#define USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_ignore_aux_pme_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en_MASK (0x100U)
#define USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en_SHIFT (8U)
#define USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_phystatus_fall_timeout_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable_MASK (0x200U)
#define USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable_SHIFT (9U)
#define USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cclk_gate_disable_MASK)
#define USB3_XECP_AUX_CTRL_REG1_new_ow_en_MASK   (0x400U)
#define USB3_XECP_AUX_CTRL_REG1_new_ow_en_SHIFT  (10U)
#define USB3_XECP_AUX_CTRL_REG1_new_ow_en(x)     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_new_ow_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_new_ow_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_isolation_en_MASK (0x800U)
#define USB3_XECP_AUX_CTRL_REG1_isolation_en_SHIFT (11U)
#define USB3_XECP_AUX_CTRL_REG1_isolation_en(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_isolation_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_isolation_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_pme_status_en_MASK (0x1000U)
#define USB3_XECP_AUX_CTRL_REG1_pme_status_en_SHIFT (12U)
#define USB3_XECP_AUX_CTRL_REG1_pme_status_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_pme_status_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_pme_status_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en_MASK (0x2000U)
#define USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en_SHIFT (13U)
#define USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_elecidle_mask_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en_MASK (0x4000U)
#define USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en_SHIFT (14U)
#define USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_pipe_rst_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en_MASK (0x8000U)
#define USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en_SHIFT (15U)
#define USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_rxdet_p3_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis_MASK (0x10000U)
#define USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis_SHIFT (16U)
#define USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_clk_gate_dis_MASK)
#define USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en_MASK (0x20000U)
#define USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en_SHIFT (17U)
#define USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_usb_p2_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength_MASK (0xC0000U)
#define USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength_SHIFT (18U)
#define USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_iob_drivestrength_MASK)
#define USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd_MASK (0x100000U)
#define USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd_SHIFT (20U)
#define USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_cfg_pcie_txreg_pd_MASK)
#define USB3_XECP_AUX_CTRL_REG1_clr_save_flag_MASK (0x200000U)
#define USB3_XECP_AUX_CTRL_REG1_clr_save_flag_SHIFT (21U)
#define USB3_XECP_AUX_CTRL_REG1_clr_save_flag(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_clr_save_flag_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_clr_save_flag_MASK)
#define USB3_XECP_AUX_CTRL_REG1_reservedrw_MASK  (0x400000U)
#define USB3_XECP_AUX_CTRL_REG1_reservedrw_SHIFT (22U)
#define USB3_XECP_AUX_CTRL_REG1_reservedrw(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_reservedrw_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_reservedrw_MASK)
#define USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en_MASK (0x800000U)
#define USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en_SHIFT (23U)
#define USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_sr_cmd_save_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_clr_ssv_en_MASK  (0x1000000U)
#define USB3_XECP_AUX_CTRL_REG1_clr_ssv_en_SHIFT (24U)
#define USB3_XECP_AUX_CTRL_REG1_clr_ssv_en(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_clr_ssv_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_clr_ssv_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_set_ssv_en_MASK  (0x2000000U)
#define USB3_XECP_AUX_CTRL_REG1_set_ssv_en_SHIFT (25U)
#define USB3_XECP_AUX_CTRL_REG1_set_ssv_en(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_set_ssv_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_set_ssv_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en_MASK (0x4000000U)
#define USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en_SHIFT (26U)
#define USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_powerdown_p1_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst_MASK (0x8000000U)
#define USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst_SHIFT (27U)
#define USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_use_perst_4fd_rst_MASK)
#define USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en_MASK (0x10000000U)
#define USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en_SHIFT (28U)
#define USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_direct_rate_pass_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en_MASK (0x20000000U)
#define USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en_SHIFT (29U)
#define USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_extend_phystatus_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en_MASK (0x40000000U)
#define USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en_SHIFT (30U)
#define USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_low_pwr_cclk_gate_en_MASK)
#define USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en_MASK (0x80000000U)
#define USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en_SHIFT (31U)
#define USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG1_d3_hot_pme_en_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_WATERMARK_REG - Port Watermark */
/*! @{ */
#define USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark_MASK (0xFFFFU)
#define USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark_SHIFT)) & USB3_XECP_HOST_CTRL_WATERMARK_REG_xbuf_water_mark_MASK)
#define USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark_MASK (0xFFFF0000U)
#define USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark_SHIFT (16U)
#define USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark_SHIFT)) & USB3_XECP_HOST_CTRL_WATERMARK_REG_rbuf_water_mark_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_PORT_LINK_REG - SuperSpeed Port Link Control */
/*! @{ */
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp_MASK (0x1U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_comp_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode_MASK (0x2U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode_SHIFT (1U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lpbk_mode_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable_MASK (0x4U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable_SHIFT (2U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u1_enable_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable_MASK (0x8U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable_SHIFT (3U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u2_enable_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en_MASK (0x10U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en_SHIFT (4U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_symbol_err_en_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb_MASK (0x20U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb_SHIFT (5U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_dis_scrmb_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training_MASK (0x40U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training_SHIFT (6U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_fast_training_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery_MASK (0x80U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery_SHIFT (7U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_recovery_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept_MASK (0x100U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept_SHIFT (8U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_force_pm_accept_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val_MASK (0xE00U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val_SHIFT (9U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_u3_recov_val_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val_MASK (0x7000U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val_SHIFT (12U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_norm_recov_val_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency_MASK (0x18000U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency_SHIFT (15U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_cfg_lowpower_latency_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel_MASK (0xE0000U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel_SHIFT (17U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_dbg_mode_sel_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en_MASK (0x100000U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en_SHIFT (20U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_link_err_cnt_slv_en_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern_MASK (0x1E00000U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern_SHIFT (21U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_comp_pattern_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0_MASK (0x2000000U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0_SHIFT (25U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_u0_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_MASK (0x4000000U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_SHIFT (26U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state_MASK (0xF8000000U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state_SHIFT (27U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG_force_ltssm_state_MASK)
/*! @} */

/*! @name XECP_USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control */
/*! @{ */
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM_MASK (0x1U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM_SHIFT (0U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_QUICK_SIM_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST_MASK (0x2U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST_SHIFT (1U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RST_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON_MASK (0x4U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON_SHIFT (2U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_RSTDISCON_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS_MASK (0x8U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS_SHIFT (3U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_CLKGATEDIS_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL_MASK (0x10U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL_SHIFT (4U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_PHY_SUSDISALL_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING_MASK (0x20U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING_SHIFT (5U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_AUTOPING_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING_MASK (0x40U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING_SHIFT (6U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCEPING_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING_MASK (0x80U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING_SHIFT (7U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DROPPING_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME_MASK (0x100U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME_SHIFT (8U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIRECT_RESUME_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK_MASK (0x200U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK_SHIFT (9U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_ISO_PEEK_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR_MASK (0x400U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR_SHIFT (10U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_DIS_PORT_ERR_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN_MASK (0x800U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN_SHIFT (11U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_DISC_WIN_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1_MASK (0x1000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1_SHIFT (12U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST1_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2_MASK (0x2000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2_SHIFT (13U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_UTMIRST2_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON_MASK (0x4000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON_SHIFT (14U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FS_LS_EXT_DISCON_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS_MASK (0x8000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS_SHIFT (15U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SPLIT_192_LIMITDIS_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED_MASK (0x10000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED_SHIFT (16U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_FORCE_FULL_SPEED_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT_MASK (0x20000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT_SHIFT (17U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_EOP_DETECT_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO_MASK (0x40000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO_SHIFT (18U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_ENABLE_FLUSH_TO_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1_MASK (0x80000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1_SHIFT (19U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA1_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA_MASK (0x100000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA_SHIFT (20U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_HW_LPM_ERRATA_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS_MASK (0x200000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS_SHIFT (21U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_RESUME_DEB_DIS_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG_MASK (0x400000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG_SHIFT (22U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_LATENCY_TOL_MSG_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_MASK (0x800000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SHIFT (23U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_USB2_PM_DEBUG_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo_MASK (0xFF000000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo_SHIFT (24U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG1_TIMER_DISCONNECT_DETECT_lo_MASK)
/*! @} */

/*! @name XECP_USB2_LINK_MGR_CTRL_REG2 - USB2 Port Link Control */
/*! @{ */
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi_MASK (0x1FU)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi_SHIFT (0U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_DISCONNECT_DETECT_hi_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT_MASK (0x3FFE0U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT_SHIFT (5U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CONNECT_DETECT_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT_MASK (0x7FFC0000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT_SHIFT (18U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_CHIRP_K_DETECT_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0_MASK (0x80000000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0_SHIFT (31U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG2_TIMER_RESET_0_MASK)
/*! @} */

/*! @name XECP_USB2_LINK_MGR_CTRL_REG3 - USB2 Port Link Control */
/*! @{ */
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET_MASK (0x7FFFU)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET_SHIFT (0U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_RESET_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE_MASK (0xFFF8000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE_SHIFT (15U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U3_SETTLE_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE_MASK (0xF0000000U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE_SHIFT (28U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG3_TIMER_U2_SETTLE_MASK)
/*! @} */

/*! @name XECP_USB2_LINK_MGR_CTRL_REG4 - USB2 Port Link Control */
/*! @{ */
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE_MASK (0x1FFU)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE_SHIFT (0U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_U2_SETTLE_MASK)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT_MASK (0x1FFFE00U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT_SHIFT (9U)
#define USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT_SHIFT)) & USB3_XECP_USB2_LINK_MGR_CTRL_REG4_TIMER_RESUME_U2_REFLECT_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_BW_MAX_REG - USB2 Max Bandwidth Control */
/*! @{ */
#define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw_MASK (0xFFU)
#define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw_SHIFT)) & USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_max_bw_MASK)
#define USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw_MASK (0xFF00U)
#define USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw_SHIFT (8U)
#define USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw_SHIFT)) & USB3_XECP_HOST_CTRL_BW_MAX_REG_hs_max_bw_MASK)
#define USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw_MASK (0xFF0000U)
#define USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw_SHIFT (16U)
#define USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw_SHIFT)) & USB3_XECP_HOST_CTRL_BW_MAX_REG_ss_max_bw_MASK)
#define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw_MASK (0xFF000000U)
#define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw_SHIFT (24U)
#define USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw_SHIFT)) & USB3_XECP_HOST_CTRL_BW_MAX_REG_fsls_bhub_max_bw_MASK)
/*! @} */

/*! @name XECP_FPGA_REVISION_REG - FPGA_REVISION_REG */
/*! @{ */
#define USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT_MASK (0xFFFFFFFFU)
#define USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT_SHIFT (0U)
#define USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT_SHIFT)) & USB3_XECP_FPGA_REVISION_REG_FPGA_REVISION_REG_DEFAULT_MASK)
/*! @} */

/*! @name XECP_HOST_INTF_CTRL_REG - Host interface control */
/*! @{ */
#define USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask_MASK (0x1U)
#define USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask_SHIFT (0U)
#define USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_host_err_mask_MASK)
#define USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en_MASK (0x2U)
#define USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en_SHIFT (1U)
#define USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_hc_halt_timeout_en_MASK)
#define USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl_MASK (0x3CU)
#define USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl_SHIFT (2U)
#define USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_host_intf_ctrl_MASK)
#define USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd_MASK (0xC0U)
#define USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd_SHIFT (6U)
#define USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_cfg_max_num_of_rd_MASK)
#define USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk_MASK (0x100U)
#define USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk_SHIFT (8U)
#define USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk_SHIFT)) & USB3_XECP_HOST_INTF_CTRL_REG_prot_hdr_rbuf_overflow_cclk_MASK)
/*! @} */

/*! @name XECP_BW_OV_SS_BURST_REG - BW_OV_SS_BURST_REG */
/*! @{ */
#define USB3_XECP_BW_OV_SS_BURST_REG_bw_ov_ss_burst_MASK (0xFFFU)
#define USB3_XECP_BW_OV_SS_BURST_REG_bw_ov_ss_burst_SHIFT (0U)
#define USB3_XECP_BW_OV_SS_BURST_REG_bw_ov_ss_burst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_BW_OV_SS_BURST_REG_bw_ov_ss_burst_SHIFT)) & USB3_XECP_BW_OV_SS_BURST_REG_bw_ov_ss_burst_MASK)
#define USB3_XECP_BW_OV_SS_BURST_REG_bw_ov_sys_burst_MASK (0xFFF000U)
#define USB3_XECP_BW_OV_SS_BURST_REG_bw_ov_sys_burst_SHIFT (12U)
#define USB3_XECP_BW_OV_SS_BURST_REG_bw_ov_sys_burst(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_BW_OV_SS_BURST_REG_bw_ov_sys_burst_SHIFT)) & USB3_XECP_BW_OV_SS_BURST_REG_bw_ov_sys_burst_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_TRM_REG2 - Host Control Transfer Manager (TRM) */
/*! @{ */
#define USB3_XECP_HOST_CTRL_TRM_REG2_reserve_trb_en_MASK (0x1U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_reserve_trb_en_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_reserve_trb_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_reserve_trb_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_reserve_trb_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_iso_cnt_2nodma_en_MASK (0x2U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_iso_cnt_2nodma_en_SHIFT (1U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_iso_cnt_2nodma_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_iso_cnt_2nodma_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_iso_cnt_2nodma_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_uport_crd_upd_en_MASK (0x4U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_uport_crd_upd_en_SHIFT (2U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_uport_crd_upd_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_uport_crd_upd_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_uport_crd_upd_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_cntx_1st_td_en_MASK (0x8U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_cntx_1st_td_en_SHIFT (3U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_cntx_1st_td_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_cntx_1st_td_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_cntx_1st_td_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_use_empty_4tte_overlap_MASK (0x10U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_use_empty_4tte_overlap_SHIFT (4U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_use_empty_4tte_overlap(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_use_empty_4tte_overlap_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_use_empty_4tte_overlap_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_setaddr_override_MASK (0x20U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_setaddr_override_SHIFT (5U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_setaddr_override(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_setaddr_override_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_setaddr_override_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_fc_on_2incomplet_en_MASK (0x40U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_fc_on_2incomplet_en_SHIFT (6U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_fc_on_2incomplet_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_fc_on_2incomplet_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_fc_on_2incomplet_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_pkt_bndry_2ignore_ntrb_en_MASK (0x80U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_pkt_bndry_2ignore_ntrb_en_SHIFT (7U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_pkt_bndry_2ignore_ntrb_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_pkt_bndry_2ignore_ntrb_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_pkt_bndry_2ignore_ntrb_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_support_0len_tte_en_MASK (0x100U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_support_0len_tte_en_SHIFT (8U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_support_0len_tte_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_support_0len_tte_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_support_0len_tte_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_trm_adv_detect_en_MASK (0x200U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_trm_adv_detect_en_SHIFT (9U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_trm_adv_detect_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_trm_adv_detect_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_trm_adv_detect_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_stream_id_match_en_MASK (0x400U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_stream_id_match_en_SHIFT (10U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_stream_id_match_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_stream_id_match_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_stream_id_match_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_stream_idle2prime_en_MASK (0x800U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_stream_idle2prime_en_SHIFT (11U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_stream_idle2prime_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_stream_idle2prime_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_stream_idle2prime_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_disable_cpl_sst_ideq0_err_MASK (0x1000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_disable_cpl_sst_ideq0_err_SHIFT (12U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_disable_cpl_sst_ideq0_err(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_disable_cpl_sst_ideq0_err_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_disable_cpl_sst_ideq0_err_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_rport_crd_check_dis_MASK (0x2000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_rport_crd_check_dis_SHIFT (13U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_rport_crd_check_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_rport_crd_check_dis_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_rport_crd_check_dis_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_odma_crd_cal_en_MASK (0x4000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_odma_crd_cal_en_SHIFT (14U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_odma_crd_cal_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_odma_crd_cal_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_odma_crd_cal_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_skip_intr_4resp_en_MASK (0x8000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_skip_intr_4resp_en_SHIFT (15U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_skip_intr_4resp_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_skip_intr_4resp_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_skip_intr_4resp_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_msi_cnt_en_MASK (0x10000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_msi_cnt_en_SHIFT (16U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_msi_cnt_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_msi_cnt_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_msi_cnt_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_ent_at_end_of_td_en_MASK (0x20000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_ent_at_end_of_td_en_SHIFT (17U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_ent_at_end_of_td_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_ent_at_end_of_td_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_ent_at_end_of_td_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_multi_non0_ctrl_ep_en_MASK (0x40000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_multi_non0_ctrl_ep_en_SHIFT (18U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_multi_non0_ctrl_ep_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_multi_non0_ctrl_ep_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_multi_non0_ctrl_ep_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_deadlock_trb_err_en_MASK (0x80000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_deadlock_trb_err_en_SHIFT (19U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_deadlock_trb_err_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_deadlock_trb_err_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_deadlock_trb_err_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_dev_mbs_cap_en_MASK (0x100000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_dev_mbs_cap_en_SHIFT (20U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_dev_mbs_cap_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_dev_mbs_cap_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_dev_mbs_cap_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_second_event_for_ISP_en_MASK (0x200000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_second_event_for_ISP_en_SHIFT (21U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_second_event_for_ISP_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_second_event_for_ISP_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_second_event_for_ISP_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_stop_2ms_4tte_en_MASK (0x400000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_stop_2ms_4tte_en_SHIFT (22U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_stop_2ms_4tte_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_stop_2ms_4tte_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_stop_2ms_4tte_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_double_clr_mask_dis_MASK (0x800000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_double_clr_mask_dis_SHIFT (23U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_double_clr_mask_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_double_clr_mask_dis_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_double_clr_mask_dis_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_ignore_npkt_4prdc_MASK (0x1000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_ignore_npkt_4prdc_SHIFT (24U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_ignore_npkt_4prdc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_ignore_npkt_4prdc_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_ignore_npkt_4prdc_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_tte_in_ep_block_en_MASK (0x2000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_tte_in_ep_block_en_SHIFT (25U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_tte_in_ep_block_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_tte_in_ep_block_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_tte_in_ep_block_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_tte_pkt_bndry_exit_MASK (0x4000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_tte_pkt_bndry_exit_SHIFT (26U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_tte_pkt_bndry_exit(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_tte_pkt_bndry_exit_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_tte_pkt_bndry_exit_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_trm_odma_fifo_disable_MASK (0x8000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_trm_odma_fifo_disable_SHIFT (27U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_trm_odma_fifo_disable(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_trm_odma_fifo_disable_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_trm_odma_fifo_disable_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_err_cpl_code_store_en_MASK (0x10000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_err_cpl_code_store_en_SHIFT (28U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_err_cpl_code_store_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_err_cpl_code_store_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_err_cpl_code_store_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_non_dma_imd_en_MASK (0x20000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_non_dma_imd_en_SHIFT (29U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_non_dma_imd_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_non_dma_imd_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_non_dma_imd_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_pkt_bndry_block_halt_en_MASK (0x40000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_pkt_bndry_block_halt_en_SHIFT (30U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_pkt_bndry_block_halt_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_pkt_bndry_block_halt_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_pkt_bndry_block_halt_en_MASK)
#define USB3_XECP_HOST_CTRL_TRM_REG2_insert_cpl_idma_wait_en_MASK (0x80000000U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_insert_cpl_idma_wait_en_SHIFT (31U)
#define USB3_XECP_HOST_CTRL_TRM_REG2_insert_cpl_idma_wait_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TRM_REG2_insert_cpl_idma_wait_en_SHIFT)) & USB3_XECP_HOST_CTRL_TRM_REG2_insert_cpl_idma_wait_en_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_BW_MAX1_REG - HOST_CTRL_BW_MAX1_REG */
/*! @{ */
#define USB3_XECP_HOST_CTRL_BW_MAX1_REG_bw_max_reg31_0_MASK (0xFFFFFFFFU)
#define USB3_XECP_HOST_CTRL_BW_MAX1_REG_bw_max_reg31_0_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_BW_MAX1_REG_bw_max_reg31_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_BW_MAX1_REG_bw_max_reg31_0_SHIFT)) & USB3_XECP_HOST_CTRL_BW_MAX1_REG_bw_max_reg31_0_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_BW_MAX2_REG - HOST_CTRL_BW_MAX2_REG */
/*! @{ */
#define USB3_XECP_HOST_CTRL_BW_MAX2_REG_bw_max_reg59_32_MASK (0xFFFFFFFU)
#define USB3_XECP_HOST_CTRL_BW_MAX2_REG_bw_max_reg59_32_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_BW_MAX2_REG_bw_max_reg59_32(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_BW_MAX2_REG_bw_max_reg59_32_SHIFT)) & USB3_XECP_HOST_CTRL_BW_MAX2_REG_bw_max_reg59_32_MASK)
/*! @} */

/*! @name XECP_USB2_LINESTATE_REG - USB2_LINESTATE_REG */
/*! @{ */
#define USB3_XECP_USB2_LINESTATE_REG_utmi_linestate_MASK (0xFFU)
#define USB3_XECP_USB2_LINESTATE_REG_utmi_linestate_SHIFT (0U)
#define USB3_XECP_USB2_LINESTATE_REG_utmi_linestate(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINESTATE_REG_utmi_linestate_SHIFT)) & USB3_XECP_USB2_LINESTATE_REG_utmi_linestate_MASK)
#define USB3_XECP_USB2_LINESTATE_REG_pdown_status_MASK (0xFFFF00U)
#define USB3_XECP_USB2_LINESTATE_REG_pdown_status_SHIFT (8U)
#define USB3_XECP_USB2_LINESTATE_REG_pdown_status(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB2_LINESTATE_REG_pdown_status_SHIFT)) & USB3_XECP_USB2_LINESTATE_REG_pdown_status_MASK)
/*! @} */

/*! @name XECP_HOST_PROTO_GAP_TIMER1_REG - HOST_PROTO_GAP_TIMER1_REG */
/*! @{ */
#define USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS_MASK (0xFFU)
#define USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS_SHIFT (0U)
#define USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS_SHIFT)) & USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS_MASK)
#define USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS_SOF_MASK (0xFF00U)
#define USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS_SOF_SHIFT (8U)
#define USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS_SOF(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS_SOF_SHIFT)) & USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS_SOF_MASK)
#define USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS_RX_MASK (0xFF0000U)
#define USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS_RX_SHIFT (16U)
#define USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS_RX(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS_RX_SHIFT)) & USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_HS_RX_MASK)
#define USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_FS_MASK (0xFF000000U)
#define USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_FS_SHIFT (24U)
#define USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_FS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_FS_SHIFT)) & USB3_XECP_HOST_PROTO_GAP_TIMER1_REG_USB2_PROTO_PKT_GAP_FS_MASK)
/*! @} */

/*! @name XECP_HOST_PROTO_GAP_TIMER2_REG - HOST_PROTO_GAP_TIMER2_REG */
/*! @{ */
#define USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS_MASK (0xFFU)
#define USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS_SHIFT (0U)
#define USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS_SHIFT)) & USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS_MASK)
#define USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS_HRX_MASK (0xFF00U)
#define USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS_HRX_SHIFT (8U)
#define USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS_HRX(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS_HRX_SHIFT)) & USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS_HRX_MASK)
#define USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS_HTX_MASK (0xFF0000U)
#define USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS_HTX_SHIFT (16U)
#define USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS_HTX(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS_HTX_SHIFT)) & USB3_XECP_HOST_PROTO_GAP_TIMER2_REG_USB2_PROTO_PKT_GAP_LS_HTX_MASK)
/*! @} */

/*! @name XECP_HOST_PROTO_BTO_TIMER_REG - HOST_PROTO_BTO_TIMER_REG */
/*! @{ */
#define USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_HS_MASK (0x3FFU)
#define USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_HS_SHIFT (0U)
#define USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_HS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_HS_SHIFT)) & USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_HS_MASK)
#define USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_FS_MASK (0x1FFC00U)
#define USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_FS_SHIFT (10U)
#define USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_FS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_FS_SHIFT)) & USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_FS_MASK)
#define USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_LS_MASK (0xFFE00000U)
#define USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_LS_SHIFT (21U)
#define USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_LS(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_LS_SHIFT)) & USB3_XECP_HOST_PROTO_BTO_TIMER_REG_USB2_PROTO_BTO_LS_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_PSCH_REG - HOST_CTRL_PSCH_REG */
/*! @{ */
#define USB3_XECP_HOST_CTRL_PSCH_REG_PSCH_HOST_CTRL_REG_I_31_24_MASK (0xFF000000U)
#define USB3_XECP_HOST_CTRL_PSCH_REG_PSCH_HOST_CTRL_REG_I_31_24_SHIFT (24U)
#define USB3_XECP_HOST_CTRL_PSCH_REG_PSCH_HOST_CTRL_REG_I_31_24(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PSCH_REG_PSCH_HOST_CTRL_REG_I_31_24_SHIFT)) & USB3_XECP_HOST_CTRL_PSCH_REG_PSCH_HOST_CTRL_REG_I_31_24_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_PSCH1_REG - HOST_CTRL_PSCH1_REG */
/*! @{ */
#define USB3_XECP_HOST_CTRL_PSCH1_REG_idle_scale_MASK (0xC00U)
#define USB3_XECP_HOST_CTRL_PSCH1_REG_idle_scale_SHIFT (10U)
#define USB3_XECP_HOST_CTRL_PSCH1_REG_idle_scale(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PSCH1_REG_idle_scale_SHIFT)) & USB3_XECP_HOST_CTRL_PSCH1_REG_idle_scale_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_LTM_REG - HOST_CTRL_LTM_REG */
/*! @{ */
#define USB3_XECP_HOST_CTRL_LTM_REG_belt_selected_MASK (0xFFFU)
#define USB3_XECP_HOST_CTRL_LTM_REG_belt_selected_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_LTM_REG_belt_selected(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_LTM_REG_belt_selected_SHIFT)) & USB3_XECP_HOST_CTRL_LTM_REG_belt_selected_MASK)
/*! @} */

/*! @name XECP_AUX_CTRL_REG2 - AUX Power Management Control 1 */
/*! @{ */
#define USB3_XECP_AUX_CTRL_REG2_auto_p2_ow_en_reg_MASK (0x1U)
#define USB3_XECP_AUX_CTRL_REG2_auto_p2_ow_en_reg_SHIFT (0U)
#define USB3_XECP_AUX_CTRL_REG2_auto_p2_ow_en_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_auto_p2_ow_en_reg_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_auto_p2_ow_en_reg_MASK)
#define USB3_XECP_AUX_CTRL_REG2_cfg_fast_sims_MASK (0x2U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_fast_sims_SHIFT (1U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_fast_sims(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_cfg_fast_sims_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_cfg_fast_sims_MASK)
#define USB3_XECP_AUX_CTRL_REG2_p0_drive_dis_MASK (0x4U)
#define USB3_XECP_AUX_CTRL_REG2_p0_drive_dis_SHIFT (2U)
#define USB3_XECP_AUX_CTRL_REG2_p0_drive_dis(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_p0_drive_dis_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_p0_drive_dis_MASK)
#define USB3_XECP_AUX_CTRL_REG2_idle_wakeup_en_MASK (0x8U)
#define USB3_XECP_AUX_CTRL_REG2_idle_wakeup_en_SHIFT (3U)
#define USB3_XECP_AUX_CTRL_REG2_idle_wakeup_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_idle_wakeup_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_idle_wakeup_en_MASK)
#define USB3_XECP_AUX_CTRL_REG2_cfg_psceg_sel_MASK (0x200U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_psceg_sel_SHIFT (9U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_psceg_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_cfg_psceg_sel_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_cfg_psceg_sel_MASK)
#define USB3_XECP_AUX_CTRL_REG2_prdc_prevent_l1_en_MASK (0x400U)
#define USB3_XECP_AUX_CTRL_REG2_prdc_prevent_l1_en_SHIFT (10U)
#define USB3_XECP_AUX_CTRL_REG2_prdc_prevent_l1_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_prdc_prevent_l1_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_prdc_prevent_l1_en_MASK)
#define USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_en_MASK (0x2000U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_en_SHIFT (13U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_en(x)  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_en_MASK)
#define USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_timeout_MASK (0xC000U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_timeout_SHIFT (14U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_timeout(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_timeout_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_timeout_MASK)
#define USB3_XECP_AUX_CTRL_REG2_wake_exit_use_lvl_en_MASK (0x10000U)
#define USB3_XECP_AUX_CTRL_REG2_wake_exit_use_lvl_en_SHIFT (16U)
#define USB3_XECP_AUX_CTRL_REG2_wake_exit_use_lvl_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_wake_exit_use_lvl_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_wake_exit_use_lvl_en_MASK)
#define USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_lfps_time_MASK (0x20000U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_lfps_time_SHIFT (17U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_lfps_time(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_lfps_time_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_cfg_u2_p3_lfps_time_MASK)
#define USB3_XECP_AUX_CTRL_REG2_u0_wake_timeout_en_MASK (0x40000U)
#define USB3_XECP_AUX_CTRL_REG2_u0_wake_timeout_en_SHIFT (18U)
#define USB3_XECP_AUX_CTRL_REG2_u0_wake_timeout_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_u0_wake_timeout_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_u0_wake_timeout_en_MASK)
#define USB3_XECP_AUX_CTRL_REG2_pdown_2link_rst_en_reg_MASK (0x80000U)
#define USB3_XECP_AUX_CTRL_REG2_pdown_2link_rst_en_reg_SHIFT (19U)
#define USB3_XECP_AUX_CTRL_REG2_pdown_2link_rst_en_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_pdown_2link_rst_en_reg_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_pdown_2link_rst_en_reg_MASK)
#define USB3_XECP_AUX_CTRL_REG2_cfg_u3_auto_MASK (0x100000U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_u3_auto_SHIFT (20U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_u3_auto(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_cfg_u3_auto_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_cfg_u3_auto_MASK)
#define USB3_XECP_AUX_CTRL_REG2_p2_overwrite_whenl1_en_MASK (0x200000U)
#define USB3_XECP_AUX_CTRL_REG2_p2_overwrite_whenl1_en_SHIFT (21U)
#define USB3_XECP_AUX_CTRL_REG2_p2_overwrite_whenl1_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_p2_overwrite_whenl1_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_p2_overwrite_whenl1_en_MASK)
#define USB3_XECP_AUX_CTRL_REG2_cfg_ltssm_idle2ts2_MASK (0x400000U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_ltssm_idle2ts2_SHIFT (22U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_ltssm_idle2ts2(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_cfg_ltssm_idle2ts2_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_cfg_ltssm_idle2ts2_MASK)
#define USB3_XECP_AUX_CTRL_REG2_cfg_psceg_dis_sel_MASK (0x800000U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_psceg_dis_sel_SHIFT (23U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_psceg_dis_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_cfg_psceg_dis_sel_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_cfg_psceg_dis_sel_MASK)
#define USB3_XECP_AUX_CTRL_REG2_auto_pm_exit_l1_en_MASK (0x1000000U)
#define USB3_XECP_AUX_CTRL_REG2_auto_pm_exit_l1_en_SHIFT (24U)
#define USB3_XECP_AUX_CTRL_REG2_auto_pm_exit_l1_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_auto_pm_exit_l1_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_auto_pm_exit_l1_en_MASK)
#define USB3_XECP_AUX_CTRL_REG2_cfg_dbgp_dis_auto_MASK (0x2000000U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_dbgp_dis_auto_SHIFT (25U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_dbgp_dis_auto(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_cfg_dbgp_dis_auto_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_cfg_dbgp_dis_auto_MASK)
#define USB3_XECP_AUX_CTRL_REG2_cfg_debounce_en_MASK (0x4000000U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_debounce_en_SHIFT (26U)
#define USB3_XECP_AUX_CTRL_REG2_cfg_debounce_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_cfg_debounce_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_cfg_debounce_en_MASK)
#define USB3_XECP_AUX_CTRL_REG2_batt_charge_d3_en_MASK (0x8000000U)
#define USB3_XECP_AUX_CTRL_REG2_batt_charge_d3_en_SHIFT (27U)
#define USB3_XECP_AUX_CTRL_REG2_batt_charge_d3_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_batt_charge_d3_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_batt_charge_d3_en_MASK)
#define USB3_XECP_AUX_CTRL_REG2_shadow_decode_dis_MASK (0x10000000U)
#define USB3_XECP_AUX_CTRL_REG2_shadow_decode_dis_SHIFT (28U)
#define USB3_XECP_AUX_CTRL_REG2_shadow_decode_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_shadow_decode_dis_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_shadow_decode_dis_MASK)
#define USB3_XECP_AUX_CTRL_REG2_snps_phystatus_done_l1_dis_MASK (0x20000000U)
#define USB3_XECP_AUX_CTRL_REG2_snps_phystatus_done_l1_dis_SHIFT (29U)
#define USB3_XECP_AUX_CTRL_REG2_snps_phystatus_done_l1_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_snps_phystatus_done_l1_dis_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_snps_phystatus_done_l1_dis_MASK)
#define USB3_XECP_AUX_CTRL_REG2_snps_phystatus_done_l23_dis_MASK (0x40000000U)
#define USB3_XECP_AUX_CTRL_REG2_snps_phystatus_done_l23_dis_SHIFT (30U)
#define USB3_XECP_AUX_CTRL_REG2_snps_phystatus_done_l23_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_snps_phystatus_done_l23_dis_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_snps_phystatus_done_l23_dis_MASK)
#define USB3_XECP_AUX_CTRL_REG2_uports_change_detect_en_MASK (0x80000000U)
#define USB3_XECP_AUX_CTRL_REG2_uports_change_detect_en_SHIFT (31U)
#define USB3_XECP_AUX_CTRL_REG2_uports_change_detect_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG2_uports_change_detect_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG2_uports_change_detect_en_MASK)
/*! @} */

/*! @name XECP_AUX_CTRL_REG3 - Configuration bits for USB2 PHY */
/*! @{ */
#define USB3_XECP_AUX_CTRL_REG3_phy_misc_ctrl_reg_1_0_MASK (0x3U)
#define USB3_XECP_AUX_CTRL_REG3_phy_misc_ctrl_reg_1_0_SHIFT (0U)
#define USB3_XECP_AUX_CTRL_REG3_phy_misc_ctrl_reg_1_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG3_phy_misc_ctrl_reg_1_0_SHIFT)) & USB3_XECP_AUX_CTRL_REG3_phy_misc_ctrl_reg_1_0_MASK)
#define USB3_XECP_AUX_CTRL_REG3_phy_misc_ctrl_reg_4_2_MASK (0x1CU)
#define USB3_XECP_AUX_CTRL_REG3_phy_misc_ctrl_reg_4_2_SHIFT (2U)
#define USB3_XECP_AUX_CTRL_REG3_phy_misc_ctrl_reg_4_2(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG3_phy_misc_ctrl_reg_4_2_SHIFT)) & USB3_XECP_AUX_CTRL_REG3_phy_misc_ctrl_reg_4_2_MASK)
#define USB3_XECP_AUX_CTRL_REG3_STA_MASK         (0xE0U)
#define USB3_XECP_AUX_CTRL_REG3_STA_SHIFT        (5U)
#define USB3_XECP_AUX_CTRL_REG3_STA(x)           (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG3_STA_SHIFT)) & USB3_XECP_AUX_CTRL_REG3_STA_MASK)
#define USB3_XECP_AUX_CTRL_REG3_Trans_HS_cross_adj_MASK (0x300U)
#define USB3_XECP_AUX_CTRL_REG3_Trans_HS_cross_adj_SHIFT (8U)
#define USB3_XECP_AUX_CTRL_REG3_Trans_HS_cross_adj(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG3_Trans_HS_cross_adj_SHIFT)) & USB3_XECP_AUX_CTRL_REG3_Trans_HS_cross_adj_MASK)
#define USB3_XECP_AUX_CTRL_REG3_HS_trans_rs_time_adj_MASK (0x400U)
#define USB3_XECP_AUX_CTRL_REG3_HS_trans_rs_time_adj_SHIFT (10U)
#define USB3_XECP_AUX_CTRL_REG3_HS_trans_rs_time_adj(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG3_HS_trans_rs_time_adj_SHIFT)) & USB3_XECP_AUX_CTRL_REG3_HS_trans_rs_time_adj_MASK)
#define USB3_XECP_AUX_CTRL_REG3_HS_trans_pre_emph_en_MASK (0x800U)
#define USB3_XECP_AUX_CTRL_REG3_HS_trans_pre_emph_en_SHIFT (11U)
#define USB3_XECP_AUX_CTRL_REG3_HS_trans_pre_emph_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG3_HS_trans_pre_emph_en_SHIFT)) & USB3_XECP_AUX_CTRL_REG3_HS_trans_pre_emph_en_MASK)
#define USB3_XECP_AUX_CTRL_REG3_fsls_src_impd_adj_MASK (0xF000U)
#define USB3_XECP_AUX_CTRL_REG3_fsls_src_impd_adj_SHIFT (12U)
#define USB3_XECP_AUX_CTRL_REG3_fsls_src_impd_adj(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG3_fsls_src_impd_adj_SHIFT)) & USB3_XECP_AUX_CTRL_REG3_fsls_src_impd_adj_MASK)
#define USB3_XECP_AUX_CTRL_REG3_hs_dc_v_lvl_adj_MASK (0xF0000U)
#define USB3_XECP_AUX_CTRL_REG3_hs_dc_v_lvl_adj_SHIFT (16U)
#define USB3_XECP_AUX_CTRL_REG3_hs_dc_v_lvl_adj(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_REG3_hs_dc_v_lvl_adj_SHIFT)) & USB3_XECP_AUX_CTRL_REG3_hs_dc_v_lvl_adj_MASK)
/*! @} */

/*! @name XECP_DEBUG_CTRL_REG - DEBUG_CTRL_REG */
/*! @{ */
#define USB3_XECP_DEBUG_CTRL_REG_debug_mode_sel_MASK (0x1FU)
#define USB3_XECP_DEBUG_CTRL_REG_debug_mode_sel_SHIFT (0U)
#define USB3_XECP_DEBUG_CTRL_REG_debug_mode_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DEBUG_CTRL_REG_debug_mode_sel_SHIFT)) & USB3_XECP_DEBUG_CTRL_REG_debug_mode_sel_MASK)
#define USB3_XECP_DEBUG_CTRL_REG_debug_fine_mode_sel_MASK (0x60U)
#define USB3_XECP_DEBUG_CTRL_REG_debug_fine_mode_sel_SHIFT (5U)
#define USB3_XECP_DEBUG_CTRL_REG_debug_fine_mode_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DEBUG_CTRL_REG_debug_fine_mode_sel_SHIFT)) & USB3_XECP_DEBUG_CTRL_REG_debug_fine_mode_sel_MASK)
#define USB3_XECP_DEBUG_CTRL_REG_debug_en_toggle_MASK (0x80U)
#define USB3_XECP_DEBUG_CTRL_REG_debug_en_toggle_SHIFT (7U)
#define USB3_XECP_DEBUG_CTRL_REG_debug_en_toggle(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DEBUG_CTRL_REG_debug_en_toggle_SHIFT)) & USB3_XECP_DEBUG_CTRL_REG_debug_en_toggle_MASK)
#define USB3_XECP_DEBUG_CTRL_REG_port_pwr_ctrl_toggle_MASK (0x100U)
#define USB3_XECP_DEBUG_CTRL_REG_port_pwr_ctrl_toggle_SHIFT (8U)
#define USB3_XECP_DEBUG_CTRL_REG_port_pwr_ctrl_toggle(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DEBUG_CTRL_REG_port_pwr_ctrl_toggle_SHIFT)) & USB3_XECP_DEBUG_CTRL_REG_port_pwr_ctrl_toggle_MASK)
#define USB3_XECP_DEBUG_CTRL_REG_sw_eeprom_en_MASK (0x200U)
#define USB3_XECP_DEBUG_CTRL_REG_sw_eeprom_en_SHIFT (9U)
#define USB3_XECP_DEBUG_CTRL_REG_sw_eeprom_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DEBUG_CTRL_REG_sw_eeprom_en_SHIFT)) & USB3_XECP_DEBUG_CTRL_REG_sw_eeprom_en_MASK)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_resume_timer_en_MASK (0x4000U)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_resume_timer_en_SHIFT (14U)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_resume_timer_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DEBUG_CTRL_REG_cfg_resume_timer_en_SHIFT)) & USB3_XECP_DEBUG_CTRL_REG_cfg_resume_timer_en_MASK)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_resume_wake_dis_MASK (0x8000U)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_resume_wake_dis_SHIFT (15U)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_resume_wake_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DEBUG_CTRL_REG_cfg_resume_wake_dis_SHIFT)) & USB3_XECP_DEBUG_CTRL_REG_cfg_resume_wake_dis_MASK)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_pm_debug_ctrl_MASK (0xF0000U)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_pm_debug_ctrl_SHIFT (16U)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_pm_debug_ctrl(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DEBUG_CTRL_REG_cfg_pm_debug_ctrl_SHIFT)) & USB3_XECP_DEBUG_CTRL_REG_cfg_pm_debug_ctrl_MASK)
#define USB3_XECP_DEBUG_CTRL_REG_new_nb_ctrl_reg_MASK (0x1F00000U)
#define USB3_XECP_DEBUG_CTRL_REG_new_nb_ctrl_reg_SHIFT (20U)
#define USB3_XECP_DEBUG_CTRL_REG_new_nb_ctrl_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DEBUG_CTRL_REG_new_nb_ctrl_reg_SHIFT)) & USB3_XECP_DEBUG_CTRL_REG_new_nb_ctrl_reg_MASK)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_l1_l0s_ctrl_MASK (0x1E000000U)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_l1_l0s_ctrl_SHIFT (25U)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_l1_l0s_ctrl(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DEBUG_CTRL_REG_cfg_l1_l0s_ctrl_SHIFT)) & USB3_XECP_DEBUG_CTRL_REG_cfg_l1_l0s_ctrl_MASK)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_pcie_gasket_ctrl_MASK (0xE0000000U)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_pcie_gasket_ctrl_SHIFT (29U)
#define USB3_XECP_DEBUG_CTRL_REG_cfg_pcie_gasket_ctrl(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DEBUG_CTRL_REG_cfg_pcie_gasket_ctrl_SHIFT)) & USB3_XECP_DEBUG_CTRL_REG_cfg_pcie_gasket_ctrl_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_SCH_REG2 - Host Control Scheduler */
/*! @{ */
#define USB3_XECP_HOST_CTRL_SCH_REG2_sch_prdc_retry_usb2_dis_MASK (0x1U)
#define USB3_XECP_HOST_CTRL_SCH_REG2_sch_prdc_retry_usb2_dis_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_SCH_REG2_sch_prdc_retry_usb2_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG2_sch_prdc_retry_usb2_dis_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG2_sch_prdc_retry_usb2_dis_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG2_sch_poll_reservation_dis_MASK (0x2U)
#define USB3_XECP_HOST_CTRL_SCH_REG2_sch_poll_reservation_dis_SHIFT (1U)
#define USB3_XECP_HOST_CTRL_SCH_REG2_sch_poll_reservation_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG2_sch_poll_reservation_dis_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG2_sch_poll_reservation_dis_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG2_sch_always_reserve_dis_MASK (0x4U)
#define USB3_XECP_HOST_CTRL_SCH_REG2_sch_always_reserve_dis_SHIFT (2U)
#define USB3_XECP_HOST_CTRL_SCH_REG2_sch_always_reserve_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG2_sch_always_reserve_dis_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG2_sch_always_reserve_dis_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG2_sch_poll_dbrang_dis_MASK (0x8U)
#define USB3_XECP_HOST_CTRL_SCH_REG2_sch_poll_dbrang_dis_SHIFT (3U)
#define USB3_XECP_HOST_CTRL_SCH_REG2_sch_poll_dbrang_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG2_sch_poll_dbrang_dis_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG2_sch_poll_dbrang_dis_MASK)
#define USB3_XECP_HOST_CTRL_SCH_REG2_service_time_watermark_MASK (0x7F00U)
#define USB3_XECP_HOST_CTRL_SCH_REG2_service_time_watermark_SHIFT (8U)
#define USB3_XECP_HOST_CTRL_SCH_REG2_service_time_watermark(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_SCH_REG2_service_time_watermark_SHIFT)) & USB3_XECP_HOST_CTRL_SCH_REG2_service_time_watermark_MASK)
/*! @} */

/*! @name XECP_AUX_DEBUG_READ_ONLY - AUX_DEBUG_READ_ONLY */
/*! @{ */
#define USB3_XECP_AUX_DEBUG_READ_ONLY_all_uports_in_u3nc_MASK (0x1U)
#define USB3_XECP_AUX_DEBUG_READ_ONLY_all_uports_in_u3nc_SHIFT (0U)
#define USB3_XECP_AUX_DEBUG_READ_ONLY_all_uports_in_u3nc(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_DEBUG_READ_ONLY_all_uports_in_u3nc_SHIFT)) & USB3_XECP_AUX_DEBUG_READ_ONLY_all_uports_in_u3nc_MASK)
#define USB3_XECP_AUX_DEBUG_READ_ONLY_p2_overwrite_enter_MASK (0x2U)
#define USB3_XECP_AUX_DEBUG_READ_ONLY_p2_overwrite_enter_SHIFT (1U)
#define USB3_XECP_AUX_DEBUG_READ_ONLY_p2_overwrite_enter(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_DEBUG_READ_ONLY_p2_overwrite_enter_SHIFT)) & USB3_XECP_AUX_DEBUG_READ_ONLY_p2_overwrite_enter_MASK)
/*! @} */

/*! @name XECP_AUX_CTRL_PORTNUM_REG - AUX_CTRL_PORTNUM_REG */
/*! @{ */
#define USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_nports_usb2_MASK (0xFFU)
#define USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_nports_usb2_SHIFT (0U)
#define USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_nports_usb2(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_nports_usb2_SHIFT)) & USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_nports_usb2_MASK)
#define USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_nports_usb3_MASK (0xFF00U)
#define USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_nports_usb3_SHIFT (8U)
#define USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_nports_usb3(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_nports_usb3_SHIFT)) & USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_nports_usb3_MASK)
#define USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_max_nports_MASK (0xFF0000U)
#define USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_max_nports_SHIFT (16U)
#define USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_max_nports(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_max_nports_SHIFT)) & USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_max_nports_MASK)
#define USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_max_slots_MASK (0xFF000000U)
#define USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_max_slots_SHIFT (24U)
#define USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_max_slots(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_max_slots_SHIFT)) & USB3_XECP_AUX_CTRL_PORTNUM_REG_limit_max_slots_MASK)
/*! @} */

/*! @name XECP_AUX_CTRL_DEV_REMOVE_REG - Feature #3002 (Device Removable in PORTSC) */
/*! @{ */
#define USB3_XECP_AUX_CTRL_DEV_REMOVE_REG_device_removable_usb2_MASK (0xFFU)
#define USB3_XECP_AUX_CTRL_DEV_REMOVE_REG_device_removable_usb2_SHIFT (0U)
#define USB3_XECP_AUX_CTRL_DEV_REMOVE_REG_device_removable_usb2(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_DEV_REMOVE_REG_device_removable_usb2_SHIFT)) & USB3_XECP_AUX_CTRL_DEV_REMOVE_REG_device_removable_usb2_MASK)
#define USB3_XECP_AUX_CTRL_DEV_REMOVE_REG_device_removable_usb3_MASK (0xFF00U)
#define USB3_XECP_AUX_CTRL_DEV_REMOVE_REG_device_removable_usb3_SHIFT (8U)
#define USB3_XECP_AUX_CTRL_DEV_REMOVE_REG_device_removable_usb3(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_AUX_CTRL_DEV_REMOVE_REG_device_removable_usb3_SHIFT)) & USB3_XECP_AUX_CTRL_DEV_REMOVE_REG_device_removable_usb3_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_DEBUG_PORT_DESC - dbgp_desc_ctrl_reg */
/*! @{ */
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_CAP_U1_EXIT_LAT_MASK (0xFU)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_CAP_U1_EXIT_LAT_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_CAP_U1_EXIT_LAT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_CAP_U1_EXIT_LAT_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_CAP_U1_EXIT_LAT_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_CAP_U2_EXIT_LAT_MASK (0x7FF0U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_CAP_U2_EXIT_LAT_SHIFT (4U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_CAP_U2_EXIT_LAT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_CAP_U2_EXIT_LAT_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_CAP_U2_EXIT_LAT_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_MAX_POWER_MASK (0xFF0000U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_MAX_POWER_SHIFT (16U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_MAX_POWER(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_MAX_POWER_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_DESC_DEBUG_PORT_MAX_POWER_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_DEBUG_PORT_TRM - dbgp_trm_ctrl_reg */
/*! @{ */
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_stall_event_MASK (0x1U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_stall_event_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_stall_event(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_stall_event_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_stall_event_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_enable_type0_is_norm_MASK (0x2U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_enable_type0_is_norm_SHIFT (1U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_enable_type0_is_norm(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_enable_type0_is_norm_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_enable_type0_is_norm_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_tx_buffer_credits_MASK (0x4U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_tx_buffer_credits_SHIFT (2U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_tx_buffer_credits(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_tx_buffer_credits_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_tx_buffer_credits_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_tx_dbg_xfer_st_MASK (0x8U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_tx_dbg_xfer_st_SHIFT (3U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_tx_dbg_xfer_st(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_tx_dbg_xfer_st_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_tx_dbg_xfer_st_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_rx_dbg_xfer_st_MASK (0x10U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_rx_dbg_xfer_st_SHIFT (4U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_rx_dbg_xfer_st(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_rx_dbg_xfer_st_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_reset_rx_dbg_xfer_st_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_timeout_timer_MASK (0x20U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_timeout_timer_SHIFT (5U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_timeout_timer(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_timeout_timer_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_timeout_timer_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_ack_eq_db_MASK (0x40U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_ack_eq_db_SHIFT (6U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_ack_eq_db(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_ack_eq_db_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_ack_eq_db_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_reread_trb_on_nonidle_db_MASK (0x80U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_reread_trb_on_nonidle_db_SHIFT (7U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_reread_trb_on_nonidle_db(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_reread_trb_on_nonidle_db_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_reread_trb_on_nonidle_db_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_stop_req_done_clr_ep_active_MASK (0x100U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_stop_req_done_clr_ep_active_SHIFT (8U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_stop_req_done_clr_ep_active(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_stop_req_done_clr_ep_active_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_stop_req_done_clr_ep_active_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_clear_pending_on_dqptr_load_MASK (0x200U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_clear_pending_on_dqptr_load_SHIFT (9U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_clear_pending_on_dqptr_load(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_clear_pending_on_dqptr_load_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_clear_pending_on_dqptr_load_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_mask_stop_on_pkt_bndry_MASK (0x400U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_mask_stop_on_pkt_bndry_SHIFT (10U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_mask_stop_on_pkt_bndry(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_mask_stop_on_pkt_bndry_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_mask_stop_on_pkt_bndry_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_adv_dqptr_on_stall_MASK (0x800U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_adv_dqptr_on_stall_SHIFT (11U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_adv_dqptr_on_stall(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_adv_dqptr_on_stall_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_adv_dqptr_on_stall_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_mask_extra_event_MASK (0x1000U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_mask_extra_event_SHIFT (12U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_mask_extra_event(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_mask_extra_event_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_disable_mask_extra_event_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_int_dbgp_trm_ctrl_reg_MASK (0xFFFFE000U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_int_dbgp_trm_ctrl_reg_SHIFT (13U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_int_dbgp_trm_ctrl_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_int_dbgp_trm_ctrl_reg_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_TRM_int_dbgp_trm_ctrl_reg_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_DEBUG_PORT_IDMA - dbgp_idma_ctrl_reg */
/*! @{ */
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_IDMA_int_dbgp_idma_ctrl_reg_MASK (0xFFFFFFFFU)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_IDMA_int_dbgp_idma_ctrl_reg_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_IDMA_int_dbgp_idma_ctrl_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_IDMA_int_dbgp_idma_ctrl_reg_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_IDMA_int_dbgp_idma_ctrl_reg_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_DEBUG_PORT_ODMA - dbgp_odma_ctrl_reg */
/*! @{ */
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_ODMA_int_dbgp_odma_ctrl_reg_MASK (0xFFFFFFFFU)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_ODMA_int_dbgp_odma_ctrl_reg_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_ODMA_int_dbgp_odma_ctrl_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_ODMA_int_dbgp_odma_ctrl_reg_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_ODMA_int_dbgp_odma_ctrl_reg_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_DEBUG_PORT_MISC - dbgp_misc_ctrl_reg */
/*! @{ */
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_clk_gate_dis_MASK (0x1U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_clk_gate_dis_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_clk_gate_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_clk_gate_dis_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_clk_gate_dis_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_string_dis_MASK (0x2U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_string_dis_SHIFT (1U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_string_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_string_dis_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_string_dis_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_ackzero_dis_MASK (0x4U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_ackzero_dis_SHIFT (2U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_ackzero_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_ackzero_dis_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_ackzero_dis_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_intr_en_MASK (0x8U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_intr_en_SHIFT (3U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_intr_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_intr_en_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_intr_en_MASK)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_intr_trgt_MASK (0x70U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_intr_trgt_SHIFT (4U)
#define USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_intr_trgt(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_intr_trgt_SHIFT)) & USB3_XECP_HOST_CTRL_DEBUG_PORT_MISC_dbgp_intr_trgt_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_TTE_REG1 - Specific control register for SCH */
/*! @{ */
#define USB3_XECP_HOST_CTRL_TTE_REG1_eob_iso_dis_MASK (0x1U)
#define USB3_XECP_HOST_CTRL_TTE_REG1_eob_iso_dis_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_TTE_REG1_eob_iso_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TTE_REG1_eob_iso_dis_SHIFT)) & USB3_XECP_HOST_CTRL_TTE_REG1_eob_iso_dis_MASK)
#define USB3_XECP_HOST_CTRL_TTE_REG1_eob_int_dis_MASK (0x2U)
#define USB3_XECP_HOST_CTRL_TTE_REG1_eob_int_dis_SHIFT (1U)
#define USB3_XECP_HOST_CTRL_TTE_REG1_eob_int_dis(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_TTE_REG1_eob_int_dis_SHIFT)) & USB3_XECP_HOST_CTRL_TTE_REG1_eob_int_dis_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_LTM_REG1 - HOST_CTRL_LTM_REG1 */
/*! @{ */
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_slot_select_MASK (0xFFFFU)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_slot_select_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_slot_select(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_LTM_REG1_belt_slot_select_SHIFT)) & USB3_XECP_HOST_CTRL_LTM_REG1_belt_slot_select_MASK)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_port_select_MASK (0xFF0000U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_port_select_SHIFT (16U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_port_select(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_LTM_REG1_belt_port_select_SHIFT)) & USB3_XECP_HOST_CTRL_LTM_REG1_belt_port_select_MASK)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_disableslot_MASK (0x1000000U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_disableslot_SHIFT (24U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_disableslot(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_disableslot_SHIFT)) & USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_disableslot_MASK)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_disableall_MASK (0x2000000U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_disableall_SHIFT (25U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_disableall(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_disableall_SHIFT)) & USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_disableall_MASK)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_recompute_MASK (0x4000000U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_recompute_SHIFT (26U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_recompute(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_recompute_SHIFT)) & USB3_XECP_HOST_CTRL_LTM_REG1_belt_force_recompute_MASK)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_pcie_en_MASK (0x8000000U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_pcie_en_SHIFT (27U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_pcie_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_LTM_REG1_belt_pcie_en_SHIFT)) & USB3_XECP_HOST_CTRL_LTM_REG1_belt_pcie_en_MASK)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_usb3_en_MASK (0x10000000U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_usb3_en_SHIFT (28U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_usb3_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_LTM_REG1_belt_usb3_en_SHIFT)) & USB3_XECP_HOST_CTRL_LTM_REG1_belt_usb3_en_MASK)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_usb2_en_MASK (0x20000000U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_usb2_en_SHIFT (29U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_usb2_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_LTM_REG1_belt_usb2_en_SHIFT)) & USB3_XECP_HOST_CTRL_LTM_REG1_belt_usb2_en_MASK)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_select_MASK (0xC0000000U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_select_SHIFT (30U)
#define USB3_XECP_HOST_CTRL_LTM_REG1_belt_select(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_LTM_REG1_belt_select_SHIFT)) & USB3_XECP_HOST_CTRL_LTM_REG1_belt_select_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_LTM_REG2 - HOST_CTRL_LTM_REG2 */
/*! @{ */
#define USB3_XECP_HOST_CTRL_LTM_REG2_DEFAULT_PCIE_LTM_MASK (0xFFFU)
#define USB3_XECP_HOST_CTRL_LTM_REG2_DEFAULT_PCIE_LTM_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_LTM_REG2_DEFAULT_PCIE_LTM(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_LTM_REG2_DEFAULT_PCIE_LTM_SHIFT)) & USB3_XECP_HOST_CTRL_LTM_REG2_DEFAULT_PCIE_LTM_MASK)
/*! @} */

/*! @name XECP_BATTERY_CHARGE_REG - Battery charge mode and enable */
/*! @{ */
#define USB3_XECP_BATTERY_CHARGE_REG_battery_charge_mode_reg_MASK (0x1U)
#define USB3_XECP_BATTERY_CHARGE_REG_battery_charge_mode_reg_SHIFT (0U)
#define USB3_XECP_BATTERY_CHARGE_REG_battery_charge_mode_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_BATTERY_CHARGE_REG_battery_charge_mode_reg_SHIFT)) & USB3_XECP_BATTERY_CHARGE_REG_battery_charge_mode_reg_MASK)
#define USB3_XECP_BATTERY_CHARGE_REG_reservedr_MASK (0x1FFFFFEU)
#define USB3_XECP_BATTERY_CHARGE_REG_reservedr_SHIFT (1U)
#define USB3_XECP_BATTERY_CHARGE_REG_reservedr(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_BATTERY_CHARGE_REG_reservedr_SHIFT)) & USB3_XECP_BATTERY_CHARGE_REG_reservedr_MASK)
#define USB3_XECP_BATTERY_CHARGE_REG_battery_charge_mode_en_reg_MASK (0xFE000000U)
#define USB3_XECP_BATTERY_CHARGE_REG_battery_charge_mode_en_reg_SHIFT (25U)
#define USB3_XECP_BATTERY_CHARGE_REG_battery_charge_mode_en_reg(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_BATTERY_CHARGE_REG_battery_charge_mode_en_reg_SHIFT)) & USB3_XECP_BATTERY_CHARGE_REG_battery_charge_mode_en_reg_MASK)
/*! @} */

/*! @name XECP_BATTERY_CHARGE_REG1 - Battery charge control register 1 */
/*! @{ */
#define USB3_XECP_BATTERY_CHARGE_REG1_BATTERY_CHARGE_CTRL_REG1_DEFAULT_MASK (0x7FFFFFFFU)
#define USB3_XECP_BATTERY_CHARGE_REG1_BATTERY_CHARGE_CTRL_REG1_DEFAULT_SHIFT (0U)
#define USB3_XECP_BATTERY_CHARGE_REG1_BATTERY_CHARGE_CTRL_REG1_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_BATTERY_CHARGE_REG1_BATTERY_CHARGE_CTRL_REG1_DEFAULT_SHIFT)) & USB3_XECP_BATTERY_CHARGE_REG1_BATTERY_CHARGE_CTRL_REG1_DEFAULT_MASK)
/*! @} */

/*! @name XECP_BATTERY_CHARGE_REG2 - Battery charge control register 2 */
/*! @{ */
#define USB3_XECP_BATTERY_CHARGE_REG2_BATTERY_CHARGE_CTRL_REG2_DEFAULT_MASK (0xFFFFFFU)
#define USB3_XECP_BATTERY_CHARGE_REG2_BATTERY_CHARGE_CTRL_REG2_DEFAULT_SHIFT (0U)
#define USB3_XECP_BATTERY_CHARGE_REG2_BATTERY_CHARGE_CTRL_REG2_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_BATTERY_CHARGE_REG2_BATTERY_CHARGE_CTRL_REG2_DEFAULT_SHIFT)) & USB3_XECP_BATTERY_CHARGE_REG2_BATTERY_CHARGE_CTRL_REG2_DEFAULT_MASK)
/*! @} */

/*! @name XECP_BATTERY_CHARGE_REG3 - Battery charge debug */
/*! @{ */
#define USB3_XECP_BATTERY_CHARGE_REG3_battery_charge_debug_MASK (0xFFFFFFU)
#define USB3_XECP_BATTERY_CHARGE_REG3_battery_charge_debug_SHIFT (0U)
#define USB3_XECP_BATTERY_CHARGE_REG3_battery_charge_debug(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_BATTERY_CHARGE_REG3_battery_charge_debug_SHIFT)) & USB3_XECP_BATTERY_CHARGE_REG3_battery_charge_debug_MASK)
/*! @} */

/*! @name XECP_HOST_CTRL_PORT_LINK_REG1 - Feature #581 */
/*! @{ */
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG1_link_8b_debug_ctrl_MASK (0x3U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG1_link_8b_debug_ctrl_SHIFT (0U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG1_link_8b_debug_ctrl(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG1_link_8b_debug_ctrl_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG1_link_8b_debug_ctrl_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG1_link_ltssm_debug_ctrl_MASK (0xFCU)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG1_link_ltssm_debug_ctrl_SHIFT (2U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG1_link_ltssm_debug_ctrl(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG1_link_ltssm_debug_ctrl_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG1_link_ltssm_debug_ctrl_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG1_cfg_tiebreak_val_MASK (0xF00U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG1_cfg_tiebreak_val_SHIFT (8U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG1_cfg_tiebreak_val(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG1_cfg_tiebreak_val_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG1_cfg_tiebreak_val_MASK)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG1_cfg_tiebreak_mode_MASK (0x3000U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG1_cfg_tiebreak_mode_SHIFT (12U)
#define USB3_XECP_HOST_CTRL_PORT_LINK_REG1_cfg_tiebreak_mode(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_HOST_CTRL_PORT_LINK_REG1_cfg_tiebreak_mode_SHIFT)) & USB3_XECP_HOST_CTRL_PORT_LINK_REG1_cfg_tiebreak_mode_MASK)
/*! @} */

/*! @name XECP_USBLEGSUP - USB Legacy Support Capability */
/*! @{ */
#define USB3_XECP_USBLEGSUP_CID_MASK             (0xFFU)
#define USB3_XECP_USBLEGSUP_CID_SHIFT            (0U)
#define USB3_XECP_USBLEGSUP_CID(x)               (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGSUP_CID_SHIFT)) & USB3_XECP_USBLEGSUP_CID_MASK)
#define USB3_XECP_USBLEGSUP_NextCP_MASK          (0xFF00U)
#define USB3_XECP_USBLEGSUP_NextCP_SHIFT         (8U)
#define USB3_XECP_USBLEGSUP_NextCP(x)            (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGSUP_NextCP_SHIFT)) & USB3_XECP_USBLEGSUP_NextCP_MASK)
#define USB3_XECP_USBLEGSUP_HCBIOSOS_MASK        (0x10000U)
#define USB3_XECP_USBLEGSUP_HCBIOSOS_SHIFT       (16U)
#define USB3_XECP_USBLEGSUP_HCBIOSOS(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGSUP_HCBIOSOS_SHIFT)) & USB3_XECP_USBLEGSUP_HCBIOSOS_MASK)
#define USB3_XECP_USBLEGSUP_HCOSOS_MASK          (0x1000000U)
#define USB3_XECP_USBLEGSUP_HCOSOS_SHIFT         (24U)
#define USB3_XECP_USBLEGSUP_HCOSOS(x)            (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGSUP_HCOSOS_SHIFT)) & USB3_XECP_USBLEGSUP_HCOSOS_MASK)
/*! @} */

/*! @name XECP_USBLEGCTLSTS - USB Legacy Support Control Status */
/*! @{ */
#define USB3_XECP_USBLEGCTLSTS_USBSMIE_MASK      (0x1U)
#define USB3_XECP_USBLEGCTLSTS_USBSMIE_SHIFT     (0U)
#define USB3_XECP_USBLEGCTLSTS_USBSMIE(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_USBSMIE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_USBSMIE_MASK)
#define USB3_XECP_USBLEGCTLSTS_SMIHSEE_MASK      (0x10U)
#define USB3_XECP_USBLEGCTLSTS_SMIHSEE_SHIFT     (4U)
#define USB3_XECP_USBLEGCTLSTS_SMIHSEE(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIHSEE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIHSEE_MASK)
#define USB3_XECP_USBLEGCTLSTS_SMIOSOE_MASK      (0x2000U)
#define USB3_XECP_USBLEGCTLSTS_SMIOSOE_SHIFT     (13U)
#define USB3_XECP_USBLEGCTLSTS_SMIOSOE(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIOSOE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIOSOE_MASK)
#define USB3_XECP_USBLEGCTLSTS_SMIPCICE_MASK     (0x4000U)
#define USB3_XECP_USBLEGCTLSTS_SMIPCICE_SHIFT    (14U)
#define USB3_XECP_USBLEGCTLSTS_SMIPCICE(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIPCICE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIPCICE_MASK)
#define USB3_XECP_USBLEGCTLSTS_SMIBARE_MASK      (0x8000U)
#define USB3_XECP_USBLEGCTLSTS_SMIBARE_SHIFT     (15U)
#define USB3_XECP_USBLEGCTLSTS_SMIBARE(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIBARE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIBARE_MASK)
#define USB3_XECP_USBLEGCTLSTS_SMIEI_MASK        (0x10000U)
#define USB3_XECP_USBLEGCTLSTS_SMIEI_SHIFT       (16U)
#define USB3_XECP_USBLEGCTLSTS_SMIEI(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIEI_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIEI_MASK)
#define USB3_XECP_USBLEGCTLSTS_SMIHSE_MASK       (0x100000U)
#define USB3_XECP_USBLEGCTLSTS_SMIHSE_SHIFT      (20U)
#define USB3_XECP_USBLEGCTLSTS_SMIHSE(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIHSE_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIHSE_MASK)
#define USB3_XECP_USBLEGCTLSTS_SMIOSOC_MASK      (0x20000000U)
#define USB3_XECP_USBLEGCTLSTS_SMIOSOC_SHIFT     (29U)
#define USB3_XECP_USBLEGCTLSTS_SMIOSOC(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIOSOC_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIOSOC_MASK)
#define USB3_XECP_USBLEGCTLSTS_SMIPCIC_MASK      (0x40000000U)
#define USB3_XECP_USBLEGCTLSTS_SMIPCIC_SHIFT     (30U)
#define USB3_XECP_USBLEGCTLSTS_SMIPCIC(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIPCIC_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIPCIC_MASK)
#define USB3_XECP_USBLEGCTLSTS_SMIBAR_MASK       (0x80000000U)
#define USB3_XECP_USBLEGCTLSTS_SMIBAR_SHIFT      (31U)
#define USB3_XECP_USBLEGCTLSTS_SMIBAR(x)         (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USBLEGCTLSTS_SMIBAR_SHIFT)) & USB3_XECP_USBLEGCTLSTS_SMIBAR_MASK)
/*! @} */

/*! @name XECP_DCID - Debug Capability ID */
/*! @{ */
#define USB3_XECP_DCID_CapID_MASK                (0xFFU)
#define USB3_XECP_DCID_CapID_SHIFT               (0U)
#define USB3_XECP_DCID_CapID(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCID_CapID_SHIFT)) & USB3_XECP_DCID_CapID_MASK)
#define USB3_XECP_DCID_NextCapID_MASK            (0xFF00U)
#define USB3_XECP_DCID_NextCapID_SHIFT           (8U)
#define USB3_XECP_DCID_NextCapID(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCID_NextCapID_SHIFT)) & USB3_XECP_DCID_NextCapID_MASK)
#define USB3_XECP_DCID_DCERST_Max_MASK           (0x1F0000U)
#define USB3_XECP_DCID_DCERST_Max_SHIFT          (16U)
#define USB3_XECP_DCID_DCERST_Max(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCID_DCERST_Max_SHIFT)) & USB3_XECP_DCID_DCERST_Max_MASK)
/*! @} */

/*! @name XECP_DCDB - Debug Capability Doorbell */
/*! @{ */
#define USB3_XECP_DCDB_DB_target_MASK            (0xFF00U)
#define USB3_XECP_DCDB_DB_target_SHIFT           (8U)
#define USB3_XECP_DCDB_DB_target(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDB_DB_target_SHIFT)) & USB3_XECP_DCDB_DB_target_MASK)
/*! @} */

/*! @name XECP_DCERSTSZ - Debug Capability Event Ring Segment Table Size */
/*! @{ */
#define USB3_XECP_DCERSTSZ_ERSTSZ_MASK           (0xFFFFU)
#define USB3_XECP_DCERSTSZ_ERSTSZ_SHIFT          (0U)
#define USB3_XECP_DCERSTSZ_ERSTSZ(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERSTSZ_ERSTSZ_SHIFT)) & USB3_XECP_DCERSTSZ_ERSTSZ_MASK)
/*! @} */

/*! @name XECP_DCERSTBA_LOW - Debug Capability Event Ring Segment Table Base Address */
/*! @{ */
#define USB3_XECP_DCERSTBA_LOW_ERSTBA_L_MASK     (0xFFFFFFF0U)
#define USB3_XECP_DCERSTBA_LOW_ERSTBA_L_SHIFT    (4U)
#define USB3_XECP_DCERSTBA_LOW_ERSTBA_L(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERSTBA_LOW_ERSTBA_L_SHIFT)) & USB3_XECP_DCERSTBA_LOW_ERSTBA_L_MASK)
/*! @} */

/*! @name XECP_DCERSTBA_HIGH - Debug Capability Event Ring Segment Table Base Address */
/*! @{ */
#define USB3_XECP_DCERSTBA_HIGH_ERSTBA_H_MASK    (0xFFFFFFFFU)
#define USB3_XECP_DCERSTBA_HIGH_ERSTBA_H_SHIFT   (0U)
#define USB3_XECP_DCERSTBA_HIGH_ERSTBA_H(x)      (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERSTBA_HIGH_ERSTBA_H_SHIFT)) & USB3_XECP_DCERSTBA_HIGH_ERSTBA_H_MASK)
/*! @} */

/*! @name XECP_DCERDP_LOW - Debug Capability Event Ring Dequeue Pointer */
/*! @{ */
#define USB3_XECP_DCERDP_LOW_DESI_MASK           (0x7U)
#define USB3_XECP_DCERDP_LOW_DESI_SHIFT          (0U)
#define USB3_XECP_DCERDP_LOW_DESI(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERDP_LOW_DESI_SHIFT)) & USB3_XECP_DCERDP_LOW_DESI_MASK)
#define USB3_XECP_DCERDP_LOW_Deq_Ptr_L_MASK      (0xFFFFFFF0U)
#define USB3_XECP_DCERDP_LOW_Deq_Ptr_L_SHIFT     (4U)
#define USB3_XECP_DCERDP_LOW_Deq_Ptr_L(x)        (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERDP_LOW_Deq_Ptr_L_SHIFT)) & USB3_XECP_DCERDP_LOW_Deq_Ptr_L_MASK)
/*! @} */

/*! @name XECP_DCERDP_HIGH - Debug Capability Event Ring Dequeue Pointer */
/*! @{ */
#define USB3_XECP_DCERDP_HIGH_Deq_Ptr_H_MASK     (0xFFFFFFFFU)
#define USB3_XECP_DCERDP_HIGH_Deq_Ptr_H_SHIFT    (0U)
#define USB3_XECP_DCERDP_HIGH_Deq_Ptr_H(x)       (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCERDP_HIGH_Deq_Ptr_H_SHIFT)) & USB3_XECP_DCERDP_HIGH_Deq_Ptr_H_MASK)
/*! @} */

/*! @name XECP_DCCTRL - Debug Capability Control */
/*! @{ */
#define USB3_XECP_DCCTRL_DCR_MASK                (0x1U)
#define USB3_XECP_DCCTRL_DCR_SHIFT               (0U)
#define USB3_XECP_DCCTRL_DCR(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_DCR_SHIFT)) & USB3_XECP_DCCTRL_DCR_MASK)
#define USB3_XECP_DCCTRL_LSE_MASK                (0x2U)
#define USB3_XECP_DCCTRL_LSE_SHIFT               (1U)
#define USB3_XECP_DCCTRL_LSE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_LSE_SHIFT)) & USB3_XECP_DCCTRL_LSE_MASK)
#define USB3_XECP_DCCTRL_HOT_MASK                (0x4U)
#define USB3_XECP_DCCTRL_HOT_SHIFT               (2U)
#define USB3_XECP_DCCTRL_HOT(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_HOT_SHIFT)) & USB3_XECP_DCCTRL_HOT_MASK)
#define USB3_XECP_DCCTRL_HIT_MASK                (0x8U)
#define USB3_XECP_DCCTRL_HIT_SHIFT               (3U)
#define USB3_XECP_DCCTRL_HIT(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_HIT_SHIFT)) & USB3_XECP_DCCTRL_HIT_MASK)
#define USB3_XECP_DCCTRL_DRC_MASK                (0x10U)
#define USB3_XECP_DCCTRL_DRC_SHIFT               (4U)
#define USB3_XECP_DCCTRL_DRC(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_DRC_SHIFT)) & USB3_XECP_DCCTRL_DRC_MASK)
#define USB3_XECP_DCCTRL_DMaxBSize_MASK          (0xFF0000U)
#define USB3_XECP_DCCTRL_DMaxBSize_SHIFT         (16U)
#define USB3_XECP_DCCTRL_DMaxBSize(x)            (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_DMaxBSize_SHIFT)) & USB3_XECP_DCCTRL_DMaxBSize_MASK)
#define USB3_XECP_DCCTRL_Dev_addr_MASK           (0x7F000000U)
#define USB3_XECP_DCCTRL_Dev_addr_SHIFT          (24U)
#define USB3_XECP_DCCTRL_Dev_addr(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_Dev_addr_SHIFT)) & USB3_XECP_DCCTRL_Dev_addr_MASK)
#define USB3_XECP_DCCTRL_DCE_MASK                (0x80000000U)
#define USB3_XECP_DCCTRL_DCE_SHIFT               (31U)
#define USB3_XECP_DCCTRL_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCTRL_DCE_SHIFT)) & USB3_XECP_DCCTRL_DCE_MASK)
/*! @} */

/*! @name XECP_DCST - Debug Capability Status */
/*! @{ */
#define USB3_XECP_DCST_ER_MASK                   (0x1U)
#define USB3_XECP_DCST_ER_SHIFT                  (0U)
#define USB3_XECP_DCST_ER(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCST_ER_SHIFT)) & USB3_XECP_DCST_ER_MASK)
#define USB3_XECP_DCST_Dbgp_num_MASK             (0xFF000000U)
#define USB3_XECP_DCST_Dbgp_num_SHIFT            (24U)
#define USB3_XECP_DCST_Dbgp_num(x)               (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCST_Dbgp_num_SHIFT)) & USB3_XECP_DCST_Dbgp_num_MASK)
/*! @} */

/*! @name XECP_DCPORTSC - Debug Capability Port Status and Control */
/*! @{ */
#define USB3_XECP_DCPORTSC_CCS_MASK              (0x1U)
#define USB3_XECP_DCPORTSC_CCS_SHIFT             (0U)
#define USB3_XECP_DCPORTSC_CCS(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_CCS_SHIFT)) & USB3_XECP_DCPORTSC_CCS_MASK)
#define USB3_XECP_DCPORTSC_PED_MASK              (0x2U)
#define USB3_XECP_DCPORTSC_PED_SHIFT             (1U)
#define USB3_XECP_DCPORTSC_PED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PED_SHIFT)) & USB3_XECP_DCPORTSC_PED_MASK)
#define USB3_XECP_DCPORTSC_PR_MASK               (0x10U)
#define USB3_XECP_DCPORTSC_PR_SHIFT              (4U)
#define USB3_XECP_DCPORTSC_PR(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PR_SHIFT)) & USB3_XECP_DCPORTSC_PR_MASK)
#define USB3_XECP_DCPORTSC_PLS_MASK              (0x1E0U)
#define USB3_XECP_DCPORTSC_PLS_SHIFT             (5U)
#define USB3_XECP_DCPORTSC_PLS(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PLS_SHIFT)) & USB3_XECP_DCPORTSC_PLS_MASK)
#define USB3_XECP_DCPORTSC_PortSpeed_MASK        (0x3C00U)
#define USB3_XECP_DCPORTSC_PortSpeed_SHIFT       (10U)
#define USB3_XECP_DCPORTSC_PortSpeed(x)          (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PortSpeed_SHIFT)) & USB3_XECP_DCPORTSC_PortSpeed_MASK)
#define USB3_XECP_DCPORTSC_CSC_MASK              (0x20000U)
#define USB3_XECP_DCPORTSC_CSC_SHIFT             (17U)
#define USB3_XECP_DCPORTSC_CSC(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_CSC_SHIFT)) & USB3_XECP_DCPORTSC_CSC_MASK)
#define USB3_XECP_DCPORTSC_PRC_MASK              (0x200000U)
#define USB3_XECP_DCPORTSC_PRC_SHIFT             (21U)
#define USB3_XECP_DCPORTSC_PRC(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PRC_SHIFT)) & USB3_XECP_DCPORTSC_PRC_MASK)
#define USB3_XECP_DCPORTSC_PLC_MASK              (0x400000U)
#define USB3_XECP_DCPORTSC_PLC_SHIFT             (22U)
#define USB3_XECP_DCPORTSC_PLC(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_PLC_SHIFT)) & USB3_XECP_DCPORTSC_PLC_MASK)
#define USB3_XECP_DCPORTSC_CEC_MASK              (0x800000U)
#define USB3_XECP_DCPORTSC_CEC_SHIFT             (23U)
#define USB3_XECP_DCPORTSC_CEC(x)                (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCPORTSC_CEC_SHIFT)) & USB3_XECP_DCPORTSC_CEC_MASK)
/*! @} */

/*! @name XECP_DCCP_LOW - Debug Capability Context Pointer */
/*! @{ */
#define USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L_MASK  (0xFFFFFFF0U)
#define USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L_SHIFT (4U)
#define USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L(x)    (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L_SHIFT)) & USB3_XECP_DCCP_LOW_DBGP_CNTX_PTR_L_MASK)
/*! @} */

/*! @name XECP_DCCP_HIGH - Debug Capability Context Pointer */
/*! @{ */
#define USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H_MASK (0xFFFFFFFFU)
#define USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H_SHIFT (0U)
#define USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H(x)   (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H_SHIFT)) & USB3_XECP_DCCP_HIGH_DBGP_CNTX_PTR_H_MASK)
/*! @} */

/*! @name XECP_DCDDI1 - Debug Capability Device Descriptor Info */
/*! @{ */
#define USB3_XECP_DCDDI1_DbC_PROT_MASK           (0xFFU)
#define USB3_XECP_DCDDI1_DbC_PROT_SHIFT          (0U)
#define USB3_XECP_DCDDI1_DbC_PROT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDDI1_DbC_PROT_SHIFT)) & USB3_XECP_DCDDI1_DbC_PROT_MASK)
#define USB3_XECP_DCDDI1_VID_MASK                (0xFFFF0000U)
#define USB3_XECP_DCDDI1_VID_SHIFT               (16U)
#define USB3_XECP_DCDDI1_VID(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDDI1_VID_SHIFT)) & USB3_XECP_DCDDI1_VID_MASK)
/*! @} */

/*! @name XECP_DCDDI2 - The Debug Capability Device Descriptor */
/*! @{ */
#define USB3_XECP_DCDDI2_PROD_ID_MASK            (0xFFFFU)
#define USB3_XECP_DCDDI2_PROD_ID_SHIFT           (0U)
#define USB3_XECP_DCDDI2_PROD_ID(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDDI2_PROD_ID_SHIFT)) & USB3_XECP_DCDDI2_PROD_ID_MASK)
#define USB3_XECP_DCDDI2_DEV_REV_MASK            (0xFFFF0000U)
#define USB3_XECP_DCDDI2_DEV_REV_SHIFT           (16U)
#define USB3_XECP_DCDDI2_DEV_REV(x)              (((uint32_t)(((uint32_t)(x)) << USB3_XECP_DCDDI2_DEV_REV_SHIFT)) & USB3_XECP_DCDDI2_DEV_REV_MASK)
/*! @} */

/*! @name XECP_USB3_TEST_PORT0_REG - USB3_TEST_PORT_REG */
/*! @{ */
#define USB3_XECP_USB3_TEST_PORT0_REG_USB3_test_ctrl_MASK (0x1U)
#define USB3_XECP_USB3_TEST_PORT0_REG_USB3_test_ctrl_SHIFT (0U)
#define USB3_XECP_USB3_TEST_PORT0_REG_USB3_test_ctrl(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB3_TEST_PORT0_REG_USB3_test_ctrl_SHIFT)) & USB3_XECP_USB3_TEST_PORT0_REG_USB3_test_ctrl_MASK)
#define USB3_XECP_USB3_TEST_PORT0_REG_USB3_test_loop_num_MASK (0xFFFEU)
#define USB3_XECP_USB3_TEST_PORT0_REG_USB3_test_loop_num_SHIFT (1U)
#define USB3_XECP_USB3_TEST_PORT0_REG_USB3_test_loop_num(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB3_TEST_PORT0_REG_USB3_test_loop_num_SHIFT)) & USB3_XECP_USB3_TEST_PORT0_REG_USB3_test_loop_num_MASK)
#define USB3_XECP_USB3_TEST_PORT0_REG_link_test_done_MASK (0x10000U)
#define USB3_XECP_USB3_TEST_PORT0_REG_link_test_done_SHIFT (16U)
#define USB3_XECP_USB3_TEST_PORT0_REG_link_test_done(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB3_TEST_PORT0_REG_link_test_done_SHIFT)) & USB3_XECP_USB3_TEST_PORT0_REG_link_test_done_MASK)
#define USB3_XECP_USB3_TEST_PORT0_REG_link_test_loop_pass_MASK (0xFFFE0000U)
#define USB3_XECP_USB3_TEST_PORT0_REG_link_test_loop_pass_SHIFT (17U)
#define USB3_XECP_USB3_TEST_PORT0_REG_link_test_loop_pass(x) (((uint32_t)(((uint32_t)(x)) << USB3_XECP_USB3_TEST_PORT0_REG_link_test_loop_pass_SHIFT)) & USB3_XECP_USB3_TEST_PORT0_REG_link_test_loop_pass_MASK)
/*! @} */

/*! @name USB_CONF - Global Configuration */
/*! @{ */
#define USB3_USB_CONF_CFGRST_MASK                (0x1U)
#define USB3_USB_CONF_CFGRST_SHIFT               (0U)
#define USB3_USB_CONF_CFGRST(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CFGRST_SHIFT)) & USB3_USB_CONF_CFGRST_MASK)
#define USB3_USB_CONF_CFGSET_MASK                (0x2U)
#define USB3_USB_CONF_CFGSET_SHIFT               (1U)
#define USB3_USB_CONF_CFGSET(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CFGSET_SHIFT)) & USB3_USB_CONF_CFGSET_MASK)
#define USB3_USB_CONF_RESERVED0_MASK             (0x4U)
#define USB3_USB_CONF_RESERVED0_SHIFT            (2U)
#define USB3_USB_CONF_RESERVED0(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_RESERVED0_SHIFT)) & USB3_USB_CONF_RESERVED0_MASK)
#define USB3_USB_CONF_USB3DIS_MASK               (0x8U)
#define USB3_USB_CONF_USB3DIS_SHIFT              (3U)
#define USB3_USB_CONF_USB3DIS(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_USB3DIS_SHIFT)) & USB3_USB_CONF_USB3DIS_MASK)
#define USB3_USB_CONF_USB2DIS_MASK               (0x10U)
#define USB3_USB_CONF_USB2DIS_SHIFT              (4U)
#define USB3_USB_CONF_USB2DIS(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_USB2DIS_SHIFT)) & USB3_USB_CONF_USB2DIS_MASK)
#define USB3_USB_CONF_LENDIAN_MASK               (0x20U)
#define USB3_USB_CONF_LENDIAN_SHIFT              (5U)
#define USB3_USB_CONF_LENDIAN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LENDIAN_SHIFT)) & USB3_USB_CONF_LENDIAN_MASK)
#define USB3_USB_CONF_BENDIAN_MASK               (0x40U)
#define USB3_USB_CONF_BENDIAN_SHIFT              (6U)
#define USB3_USB_CONF_BENDIAN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_BENDIAN_SHIFT)) & USB3_USB_CONF_BENDIAN_MASK)
#define USB3_USB_CONF_SWRST_MASK                 (0x80U)
#define USB3_USB_CONF_SWRST_SHIFT                (7U)
#define USB3_USB_CONF_SWRST(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_SWRST_SHIFT)) & USB3_USB_CONF_SWRST_MASK)
#define USB3_USB_CONF_DSING_MASK                 (0x100U)
#define USB3_USB_CONF_DSING_SHIFT                (8U)
#define USB3_USB_CONF_DSING(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DSING_SHIFT)) & USB3_USB_CONF_DSING_MASK)
#define USB3_USB_CONF_DMULT_MASK                 (0x200U)
#define USB3_USB_CONF_DMULT_SHIFT                (9U)
#define USB3_USB_CONF_DMULT(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DMULT_SHIFT)) & USB3_USB_CONF_DMULT_MASK)
#define USB3_USB_CONF_DMAOFFEN_MASK              (0x400U)
#define USB3_USB_CONF_DMAOFFEN_SHIFT             (10U)
#define USB3_USB_CONF_DMAOFFEN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DMAOFFEN_SHIFT)) & USB3_USB_CONF_DMAOFFEN_MASK)
#define USB3_USB_CONF_DMAOFFDS_MASK              (0x800U)
#define USB3_USB_CONF_DMAOFFDS_SHIFT             (11U)
#define USB3_USB_CONF_DMAOFFDS(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DMAOFFDS_SHIFT)) & USB3_USB_CONF_DMAOFFDS_MASK)
#define USB3_USB_CONF_CFORCE_FS_MASK             (0x1000U)
#define USB3_USB_CONF_CFORCE_FS_SHIFT            (12U)
#define USB3_USB_CONF_CFORCE_FS(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CFORCE_FS_SHIFT)) & USB3_USB_CONF_CFORCE_FS_MASK)
#define USB3_USB_CONF_SFORCE_FS_MASK             (0x2000U)
#define USB3_USB_CONF_SFORCE_FS_SHIFT            (13U)
#define USB3_USB_CONF_SFORCE_FS(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_SFORCE_FS_SHIFT)) & USB3_USB_CONF_SFORCE_FS_MASK)
#define USB3_USB_CONF_DEVEN_MASK                 (0x4000U)
#define USB3_USB_CONF_DEVEN_SHIFT                (14U)
#define USB3_USB_CONF_DEVEN(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DEVEN_SHIFT)) & USB3_USB_CONF_DEVEN_MASK)
#define USB3_USB_CONF_DEVDS_MASK                 (0x8000U)
#define USB3_USB_CONF_DEVDS_SHIFT                (15U)
#define USB3_USB_CONF_DEVDS(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_DEVDS_SHIFT)) & USB3_USB_CONF_DEVDS_MASK)
#define USB3_USB_CONF_L1EN_MASK                  (0x10000U)
#define USB3_USB_CONF_L1EN_SHIFT                 (16U)
#define USB3_USB_CONF_L1EN(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_L1EN_SHIFT)) & USB3_USB_CONF_L1EN_MASK)
#define USB3_USB_CONF_L1DS_MASK                  (0x20000U)
#define USB3_USB_CONF_L1DS_SHIFT                 (17U)
#define USB3_USB_CONF_L1DS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_L1DS_SHIFT)) & USB3_USB_CONF_L1DS_MASK)
#define USB3_USB_CONF_CLK2OFFEN_MASK             (0x40000U)
#define USB3_USB_CONF_CLK2OFFEN_SHIFT            (18U)
#define USB3_USB_CONF_CLK2OFFEN(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CLK2OFFEN_SHIFT)) & USB3_USB_CONF_CLK2OFFEN_MASK)
#define USB3_USB_CONF_CLK2OFFDS_MASK             (0x80000U)
#define USB3_USB_CONF_CLK2OFFDS_SHIFT            (19U)
#define USB3_USB_CONF_CLK2OFFDS(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CLK2OFFDS_SHIFT)) & USB3_USB_CONF_CLK2OFFDS_MASK)
#define USB3_USB_CONF_LGO_L0_MASK                (0x100000U)
#define USB3_USB_CONF_LGO_L0_SHIFT               (20U)
#define USB3_USB_CONF_LGO_L0(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_L0_SHIFT)) & USB3_USB_CONF_LGO_L0_MASK)
#define USB3_USB_CONF_CLK3OFFEN_MASK             (0x200000U)
#define USB3_USB_CONF_CLK3OFFEN_SHIFT            (21U)
#define USB3_USB_CONF_CLK3OFFEN(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CLK3OFFEN_SHIFT)) & USB3_USB_CONF_CLK3OFFEN_MASK)
#define USB3_USB_CONF_CLK3OFFDS_MASK             (0x400000U)
#define USB3_USB_CONF_CLK3OFFDS_SHIFT            (22U)
#define USB3_USB_CONF_CLK3OFFDS(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_CLK3OFFDS_SHIFT)) & USB3_USB_CONF_CLK3OFFDS_MASK)
#define USB3_USB_CONF_RESERVED1_MASK             (0x800000U)
#define USB3_USB_CONF_RESERVED1_SHIFT            (23U)
#define USB3_USB_CONF_RESERVED1(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_RESERVED1_SHIFT)) & USB3_USB_CONF_RESERVED1_MASK)
#define USB3_USB_CONF_U1EN_MASK                  (0x1000000U)
#define USB3_USB_CONF_U1EN_SHIFT                 (24U)
#define USB3_USB_CONF_U1EN(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_U1EN_SHIFT)) & USB3_USB_CONF_U1EN_MASK)
#define USB3_USB_CONF_U1DS_MASK                  (0x2000000U)
#define USB3_USB_CONF_U1DS_SHIFT                 (25U)
#define USB3_USB_CONF_U1DS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_U1DS_SHIFT)) & USB3_USB_CONF_U1DS_MASK)
#define USB3_USB_CONF_U2EN_MASK                  (0x4000000U)
#define USB3_USB_CONF_U2EN_SHIFT                 (26U)
#define USB3_USB_CONF_U2EN(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_U2EN_SHIFT)) & USB3_USB_CONF_U2EN_MASK)
#define USB3_USB_CONF_U2DS_MASK                  (0x8000000U)
#define USB3_USB_CONF_U2DS_SHIFT                 (27U)
#define USB3_USB_CONF_U2DS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_U2DS_SHIFT)) & USB3_USB_CONF_U2DS_MASK)
#define USB3_USB_CONF_LGO_U0_MASK                (0x10000000U)
#define USB3_USB_CONF_LGO_U0_SHIFT               (28U)
#define USB3_USB_CONF_LGO_U0(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_U0_SHIFT)) & USB3_USB_CONF_LGO_U0_MASK)
#define USB3_USB_CONF_LGO_U1_MASK                (0x20000000U)
#define USB3_USB_CONF_LGO_U1_SHIFT               (29U)
#define USB3_USB_CONF_LGO_U1(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_U1_SHIFT)) & USB3_USB_CONF_LGO_U1_MASK)
#define USB3_USB_CONF_LGO_U2_MASK                (0x40000000U)
#define USB3_USB_CONF_LGO_U2_SHIFT               (30U)
#define USB3_USB_CONF_LGO_U2(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_U2_SHIFT)) & USB3_USB_CONF_LGO_U2_MASK)
#define USB3_USB_CONF_LGO_SSINACT_MASK           (0x80000000U)
#define USB3_USB_CONF_LGO_SSINACT_SHIFT          (31U)
#define USB3_USB_CONF_LGO_SSINACT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF_LGO_SSINACT_SHIFT)) & USB3_USB_CONF_LGO_SSINACT_MASK)
/*! @} */

/*! @name USB_STS - Global Status */
/*! @{ */
#define USB3_USB_STS_CFGSTS_MASK                 (0x1U)
#define USB3_USB_STS_CFGSTS_SHIFT                (0U)
#define USB3_USB_STS_CFGSTS(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_CFGSTS_SHIFT)) & USB3_USB_STS_CFGSTS_MASK)
#define USB3_USB_STS_MEM_OV_MASK                 (0x2U)
#define USB3_USB_STS_MEM_OV_SHIFT                (1U)
#define USB3_USB_STS_MEM_OV(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_MEM_OV_SHIFT)) & USB3_USB_STS_MEM_OV_MASK)
#define USB3_USB_STS_USB3CONS_MASK               (0x4U)
#define USB3_USB_STS_USB3CONS_SHIFT              (2U)
#define USB3_USB_STS_USB3CONS(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_USB3CONS_SHIFT)) & USB3_USB_STS_USB3CONS_MASK)
#define USB3_USB_STS_DTRANS_MASK                 (0x8U)
#define USB3_USB_STS_DTRANS_SHIFT                (3U)
#define USB3_USB_STS_DTRANS(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_DTRANS_SHIFT)) & USB3_USB_STS_DTRANS_MASK)
#define USB3_USB_STS_USBSPEED_MASK               (0x70U)
#define USB3_USB_STS_USBSPEED_SHIFT              (4U)
#define USB3_USB_STS_USBSPEED(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_USBSPEED_SHIFT)) & USB3_USB_STS_USBSPEED_MASK)
#define USB3_USB_STS_ENDIAN_MIRROR_MASK          (0x80U)
#define USB3_USB_STS_ENDIAN_MIRROR_SHIFT         (7U)
#define USB3_USB_STS_ENDIAN_MIRROR(x)            (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_ENDIAN_MIRROR_SHIFT)) & USB3_USB_STS_ENDIAN_MIRROR_MASK)
#define USB3_USB_STS_CLK2OFF_MASK                (0x100U)
#define USB3_USB_STS_CLK2OFF_SHIFT               (8U)
#define USB3_USB_STS_CLK2OFF(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_CLK2OFF_SHIFT)) & USB3_USB_STS_CLK2OFF_MASK)
#define USB3_USB_STS_CLK3OFF_MASK                (0x200U)
#define USB3_USB_STS_CLK3OFF_SHIFT               (9U)
#define USB3_USB_STS_CLK3OFF(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_CLK3OFF_SHIFT)) & USB3_USB_STS_CLK3OFF_MASK)
#define USB3_USB_STS_IN_RST_MASK                 (0x400U)
#define USB3_USB_STS_IN_RST_SHIFT                (10U)
#define USB3_USB_STS_IN_RST(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_IN_RST_SHIFT)) & USB3_USB_STS_IN_RST_MASK)
#define USB3_USB_STS_RESERVED0_MASK              (0x3800U)
#define USB3_USB_STS_RESERVED0_SHIFT             (11U)
#define USB3_USB_STS_RESERVED0(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_RESERVED0_SHIFT)) & USB3_USB_STS_RESERVED0_MASK)
#define USB3_USB_STS_DEVS_MASK                   (0x4000U)
#define USB3_USB_STS_DEVS_SHIFT                  (14U)
#define USB3_USB_STS_DEVS(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_DEVS_SHIFT)) & USB3_USB_STS_DEVS_MASK)
#define USB3_USB_STS_ADDRESSED_MASK              (0x8000U)
#define USB3_USB_STS_ADDRESSED_SHIFT             (15U)
#define USB3_USB_STS_ADDRESSED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_ADDRESSED_SHIFT)) & USB3_USB_STS_ADDRESSED_MASK)
#define USB3_USB_STS_L1ENS_MASK                  (0x10000U)
#define USB3_USB_STS_L1ENS_SHIFT                 (16U)
#define USB3_USB_STS_L1ENS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_L1ENS_SHIFT)) & USB3_USB_STS_L1ENS_MASK)
#define USB3_USB_STS_VBUSS_MASK                  (0x20000U)
#define USB3_USB_STS_VBUSS_SHIFT                 (17U)
#define USB3_USB_STS_VBUSS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_VBUSS_SHIFT)) & USB3_USB_STS_VBUSS_MASK)
#define USB3_USB_STS_LPMST_MASK                  (0xC0000U)
#define USB3_USB_STS_LPMST_SHIFT                 (18U)
#define USB3_USB_STS_LPMST(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_LPMST_SHIFT)) & USB3_USB_STS_LPMST_MASK)
#define USB3_USB_STS_USB2CONS_MASK               (0x100000U)
#define USB3_USB_STS_USB2CONS_SHIFT              (20U)
#define USB3_USB_STS_USB2CONS(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_USB2CONS_SHIFT)) & USB3_USB_STS_USB2CONS_MASK)
#define USB3_USB_STS_DISABLE_HS_MASK             (0x200000U)
#define USB3_USB_STS_DISABLE_HS_SHIFT            (21U)
#define USB3_USB_STS_DISABLE_HS(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_DISABLE_HS_SHIFT)) & USB3_USB_STS_DISABLE_HS_MASK)
#define USB3_USB_STS_RESERVED1_MASK              (0xC00000U)
#define USB3_USB_STS_RESERVED1_SHIFT             (22U)
#define USB3_USB_STS_RESERVED1(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_RESERVED1_SHIFT)) & USB3_USB_STS_RESERVED1_MASK)
#define USB3_USB_STS_U1ENS_MASK                  (0x1000000U)
#define USB3_USB_STS_U1ENS_SHIFT                 (24U)
#define USB3_USB_STS_U1ENS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_U1ENS_SHIFT)) & USB3_USB_STS_U1ENS_MASK)
#define USB3_USB_STS_U2ENS_MASK                  (0x2000000U)
#define USB3_USB_STS_U2ENS_SHIFT                 (25U)
#define USB3_USB_STS_U2ENS(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_U2ENS_SHIFT)) & USB3_USB_STS_U2ENS_MASK)
#define USB3_USB_STS_LST_MASK                    (0x3C000000U)
#define USB3_USB_STS_LST_SHIFT                   (26U)
#define USB3_USB_STS_LST(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_LST_SHIFT)) & USB3_USB_STS_LST_MASK)
#define USB3_USB_STS_DMAOFF_MASK                 (0x40000000U)
#define USB3_USB_STS_DMAOFF_SHIFT                (30U)
#define USB3_USB_STS_DMAOFF(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_DMAOFF_SHIFT)) & USB3_USB_STS_DMAOFF_MASK)
#define USB3_USB_STS_ENDIAN_MASK                 (0x80000000U)
#define USB3_USB_STS_ENDIAN_SHIFT                (31U)
#define USB3_USB_STS_ENDIAN(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_STS_ENDIAN_SHIFT)) & USB3_USB_STS_ENDIAN_MASK)
/*! @} */

/*! @name USB_CMD - Global Command */
/*! @{ */
#define USB3_USB_CMD_SET_ADDR_MASK               (0x1U)
#define USB3_USB_CMD_SET_ADDR_SHIFT              (0U)
#define USB3_USB_CMD_SET_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_SET_ADDR_SHIFT)) & USB3_USB_CMD_SET_ADDR_MASK)
#define USB3_USB_CMD_FADDR_MASK                  (0xFEU)
#define USB3_USB_CMD_FADDR_SHIFT                 (1U)
#define USB3_USB_CMD_FADDR(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_FADDR_SHIFT)) & USB3_USB_CMD_FADDR_MASK)
#define USB3_USB_CMD_SDNFW_MASK                  (0x100U)
#define USB3_USB_CMD_SDNFW_SHIFT                 (8U)
#define USB3_USB_CMD_SDNFW(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_SDNFW_SHIFT)) & USB3_USB_CMD_SDNFW_MASK)
#define USB3_USB_CMD_STMODE_MASK                 (0x200U)
#define USB3_USB_CMD_STMODE_SHIFT                (9U)
#define USB3_USB_CMD_STMODE(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_STMODE_SHIFT)) & USB3_USB_CMD_STMODE_MASK)
#define USB3_USB_CMD_TMODE_SEL_MASK              (0xC00U)
#define USB3_USB_CMD_TMODE_SEL_SHIFT             (10U)
#define USB3_USB_CMD_TMODE_SEL(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_TMODE_SEL_SHIFT)) & USB3_USB_CMD_TMODE_SEL_MASK)
#define USB3_USB_CMD_SDNLTM_MASK                 (0x1000U)
#define USB3_USB_CMD_SDNLTM_SHIFT                (12U)
#define USB3_USB_CMD_SDNLTM(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_SDNLTM_SHIFT)) & USB3_USB_CMD_SDNLTM_MASK)
#define USB3_USB_CMD_SPKT_MASK                   (0x2000U)
#define USB3_USB_CMD_SPKT_SHIFT                  (13U)
#define USB3_USB_CMD_SPKT(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_SPKT_SHIFT)) & USB3_USB_CMD_SPKT_MASK)
#define USB3_USB_CMD_RESERVED0_MASK              (0xC000U)
#define USB3_USB_CMD_RESERVED0_SHIFT             (14U)
#define USB3_USB_CMD_RESERVED0(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_RESERVED0_SHIFT)) & USB3_USB_CMD_RESERVED0_MASK)
#define USB3_USB_CMD_DNLTM_BELT_7_0_MASK         (0xFF0000U)
#define USB3_USB_CMD_DNLTM_BELT_7_0_SHIFT        (16U)
#define USB3_USB_CMD_DNLTM_BELT_7_0(x)           (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_DNLTM_BELT_7_0_SHIFT)) & USB3_USB_CMD_DNLTM_BELT_7_0_MASK)
#define USB3_USB_CMD_DNLTM_BELT_11_8_MASK        (0xF000000U)
#define USB3_USB_CMD_DNLTM_BELT_11_8_SHIFT       (24U)
#define USB3_USB_CMD_DNLTM_BELT_11_8(x)          (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_DNLTM_BELT_11_8_SHIFT)) & USB3_USB_CMD_DNLTM_BELT_11_8_MASK)
#define USB3_USB_CMD_RESERVED1_MASK              (0xF0000000U)
#define USB3_USB_CMD_RESERVED1_SHIFT             (28U)
#define USB3_USB_CMD_RESERVED1(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CMD_RESERVED1_SHIFT)) & USB3_USB_CMD_RESERVED1_MASK)
/*! @} */

/*! @name USB_IPTN - ITP Number */
/*! @{ */
#define USB3_USB_IPTN_ITPN_MASK                  (0x3FFFU)
#define USB3_USB_IPTN_ITPN_SHIFT                 (0U)
#define USB3_USB_IPTN_ITPN(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_IPTN_ITPN_SHIFT)) & USB3_USB_IPTN_ITPN_MASK)
#define USB3_USB_IPTN_RESERVED_MASK              (0xFFFFC000U)
#define USB3_USB_IPTN_RESERVED_SHIFT             (14U)
#define USB3_USB_IPTN_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IPTN_RESERVED_SHIFT)) & USB3_USB_IPTN_RESERVED_MASK)
/*! @} */

/*! @name USB_LPM - Link Power Management */
/*! @{ */
#define USB3_USB_LPM_HIRD_MASK                   (0xFU)
#define USB3_USB_LPM_HIRD_SHIFT                  (0U)
#define USB3_USB_LPM_HIRD(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_USB_LPM_HIRD_SHIFT)) & USB3_USB_LPM_HIRD_MASK)
#define USB3_USB_LPM_BRW_MASK                    (0x10U)
#define USB3_USB_LPM_BRW_SHIFT                   (4U)
#define USB3_USB_LPM_BRW(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_USB_LPM_BRW_SHIFT)) & USB3_USB_LPM_BRW_MASK)
#define USB3_USB_LPM_RESERVED_MASK               (0xFFFFFFE0U)
#define USB3_USB_LPM_RESERVED_SHIFT              (5U)
#define USB3_USB_LPM_RESERVED(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_LPM_RESERVED_SHIFT)) & USB3_USB_LPM_RESERVED_MASK)
/*! @} */

/*! @name USB_IEN - Interrupt Enable */
/*! @{ */
#define USB3_USB_IEN_CONIEN_MASK                 (0x1U)
#define USB3_USB_IEN_CONIEN_SHIFT                (0U)
#define USB3_USB_IEN_CONIEN(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_CONIEN_SHIFT)) & USB3_USB_IEN_CONIEN_MASK)
#define USB3_USB_IEN_DISIEN_MASK                 (0x2U)
#define USB3_USB_IEN_DISIEN_SHIFT                (1U)
#define USB3_USB_IEN_DISIEN(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_DISIEN_SHIFT)) & USB3_USB_IEN_DISIEN_MASK)
#define USB3_USB_IEN_UWRESIEN_MASK               (0x4U)
#define USB3_USB_IEN_UWRESIEN_SHIFT              (2U)
#define USB3_USB_IEN_UWRESIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_UWRESIEN_SHIFT)) & USB3_USB_IEN_UWRESIEN_MASK)
#define USB3_USB_IEN_UHRESIEN_MASK               (0x8U)
#define USB3_USB_IEN_UHRESIEN_SHIFT              (3U)
#define USB3_USB_IEN_UHRESIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_UHRESIEN_SHIFT)) & USB3_USB_IEN_UHRESIEN_MASK)
#define USB3_USB_IEN_U3ENTIEN_MASK               (0x10U)
#define USB3_USB_IEN_U3ENTIEN_SHIFT              (4U)
#define USB3_USB_IEN_U3ENTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U3ENTIEN_SHIFT)) & USB3_USB_IEN_U3ENTIEN_MASK)
#define USB3_USB_IEN_U3EXTIEN_MASK               (0x20U)
#define USB3_USB_IEN_U3EXTIEN_SHIFT              (5U)
#define USB3_USB_IEN_U3EXTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U3EXTIEN_SHIFT)) & USB3_USB_IEN_U3EXTIEN_MASK)
#define USB3_USB_IEN_U2ENTIEN_MASK               (0x40U)
#define USB3_USB_IEN_U2ENTIEN_SHIFT              (6U)
#define USB3_USB_IEN_U2ENTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U2ENTIEN_SHIFT)) & USB3_USB_IEN_U2ENTIEN_MASK)
#define USB3_USB_IEN_U2EXTIEN_MASK               (0x80U)
#define USB3_USB_IEN_U2EXTIEN_SHIFT              (7U)
#define USB3_USB_IEN_U2EXTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U2EXTIEN_SHIFT)) & USB3_USB_IEN_U2EXTIEN_MASK)
#define USB3_USB_IEN_U1ENTIEN_MASK               (0x100U)
#define USB3_USB_IEN_U1ENTIEN_SHIFT              (8U)
#define USB3_USB_IEN_U1ENTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U1ENTIEN_SHIFT)) & USB3_USB_IEN_U1ENTIEN_MASK)
#define USB3_USB_IEN_U1EXTIEN_MASK               (0x200U)
#define USB3_USB_IEN_U1EXTIEN_SHIFT              (9U)
#define USB3_USB_IEN_U1EXTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U1EXTIEN_SHIFT)) & USB3_USB_IEN_U1EXTIEN_MASK)
#define USB3_USB_IEN_ITPIEN_MASK                 (0x400U)
#define USB3_USB_IEN_ITPIEN_SHIFT                (10U)
#define USB3_USB_IEN_ITPIEN(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_ITPIEN_SHIFT)) & USB3_USB_IEN_ITPIEN_MASK)
#define USB3_USB_IEN_WAKEIEN_MASK                (0x800U)
#define USB3_USB_IEN_WAKEIEN_SHIFT               (11U)
#define USB3_USB_IEN_WAKEIEN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_WAKEIEN_SHIFT)) & USB3_USB_IEN_WAKEIEN_MASK)
#define USB3_USB_IEN_SPKTIEN_MASK                (0x1000U)
#define USB3_USB_IEN_SPKTIEN_SHIFT               (12U)
#define USB3_USB_IEN_SPKTIEN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_SPKTIEN_SHIFT)) & USB3_USB_IEN_SPKTIEN_MASK)
#define USB3_USB_IEN_RESERVED0_MASK              (0xE000U)
#define USB3_USB_IEN_RESERVED0_SHIFT             (13U)
#define USB3_USB_IEN_RESERVED0(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED0_SHIFT)) & USB3_USB_IEN_RESERVED0_MASK)
#define USB3_USB_IEN_CON2IEN_MASK                (0x10000U)
#define USB3_USB_IEN_CON2IEN_SHIFT               (16U)
#define USB3_USB_IEN_CON2IEN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_CON2IEN_SHIFT)) & USB3_USB_IEN_CON2IEN_MASK)
#define USB3_USB_IEN_DIS2IEN_MASK                (0x20000U)
#define USB3_USB_IEN_DIS2IEN_SHIFT               (17U)
#define USB3_USB_IEN_DIS2IEN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_DIS2IEN_SHIFT)) & USB3_USB_IEN_DIS2IEN_MASK)
#define USB3_USB_IEN_U2RESIEN_MASK               (0x40000U)
#define USB3_USB_IEN_U2RESIEN_SHIFT              (18U)
#define USB3_USB_IEN_U2RESIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_U2RESIEN_SHIFT)) & USB3_USB_IEN_U2RESIEN_MASK)
#define USB3_USB_IEN_RESERVED1_MASK              (0x80000U)
#define USB3_USB_IEN_RESERVED1_SHIFT             (19U)
#define USB3_USB_IEN_RESERVED1(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED1_SHIFT)) & USB3_USB_IEN_RESERVED1_MASK)
#define USB3_USB_IEN_L2ENTIEN_MASK               (0x100000U)
#define USB3_USB_IEN_L2ENTIEN_SHIFT              (20U)
#define USB3_USB_IEN_L2ENTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_L2ENTIEN_SHIFT)) & USB3_USB_IEN_L2ENTIEN_MASK)
#define USB3_USB_IEN_L2EXTIEN_MASK               (0x200000U)
#define USB3_USB_IEN_L2EXTIEN_SHIFT              (21U)
#define USB3_USB_IEN_L2EXTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_L2EXTIEN_SHIFT)) & USB3_USB_IEN_L2EXTIEN_MASK)
#define USB3_USB_IEN_RESERVED2_MASK              (0xC00000U)
#define USB3_USB_IEN_RESERVED2_SHIFT             (22U)
#define USB3_USB_IEN_RESERVED2(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED2_SHIFT)) & USB3_USB_IEN_RESERVED2_MASK)
#define USB3_USB_IEN_L1ENTIEN_MASK               (0x1000000U)
#define USB3_USB_IEN_L1ENTIEN_SHIFT              (24U)
#define USB3_USB_IEN_L1ENTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_L1ENTIEN_SHIFT)) & USB3_USB_IEN_L1ENTIEN_MASK)
#define USB3_USB_IEN_L1EXTIEN_MASK               (0x2000000U)
#define USB3_USB_IEN_L1EXTIEN_SHIFT              (25U)
#define USB3_USB_IEN_L1EXTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_L1EXTIEN_SHIFT)) & USB3_USB_IEN_L1EXTIEN_MASK)
#define USB3_USB_IEN_CFGRESIEN_MASK              (0x4000000U)
#define USB3_USB_IEN_CFGRESIEN_SHIFT             (26U)
#define USB3_USB_IEN_CFGRESIEN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_CFGRESIEN_SHIFT)) & USB3_USB_IEN_CFGRESIEN_MASK)
#define USB3_USB_IEN_RESERVED3_MASK              (0x8000000U)
#define USB3_USB_IEN_RESERVED3_SHIFT             (27U)
#define USB3_USB_IEN_RESERVED3(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED3_SHIFT)) & USB3_USB_IEN_RESERVED3_MASK)
#define USB3_USB_IEN_UWRESSIEN_MASK              (0x10000000U)
#define USB3_USB_IEN_UWRESSIEN_SHIFT             (28U)
#define USB3_USB_IEN_UWRESSIEN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_UWRESSIEN_SHIFT)) & USB3_USB_IEN_UWRESSIEN_MASK)
#define USB3_USB_IEN_UWRESEIEN_MASK              (0x20000000U)
#define USB3_USB_IEN_UWRESEIEN_SHIFT             (29U)
#define USB3_USB_IEN_UWRESEIEN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_UWRESEIEN_SHIFT)) & USB3_USB_IEN_UWRESEIEN_MASK)
#define USB3_USB_IEN_RESERVED4_MASK              (0xC0000000U)
#define USB3_USB_IEN_RESERVED4_SHIFT             (30U)
#define USB3_USB_IEN_RESERVED4(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_IEN_RESERVED4_SHIFT)) & USB3_USB_IEN_RESERVED4_MASK)
/*! @} */

/*! @name USB_ISTS - Interrupt Status */
/*! @{ */
#define USB3_USB_ISTS_CONI_MASK                  (0x1U)
#define USB3_USB_ISTS_CONI_SHIFT                 (0U)
#define USB3_USB_ISTS_CONI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_CONI_SHIFT)) & USB3_USB_ISTS_CONI_MASK)
#define USB3_USB_ISTS_DISI_MASK                  (0x2U)
#define USB3_USB_ISTS_DISI_SHIFT                 (1U)
#define USB3_USB_ISTS_DISI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_DISI_SHIFT)) & USB3_USB_ISTS_DISI_MASK)
#define USB3_USB_ISTS_UWRESI_MASK                (0x4U)
#define USB3_USB_ISTS_UWRESI_SHIFT               (2U)
#define USB3_USB_ISTS_UWRESI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_UWRESI_SHIFT)) & USB3_USB_ISTS_UWRESI_MASK)
#define USB3_USB_ISTS_UHRESI_MASK                (0x8U)
#define USB3_USB_ISTS_UHRESI_SHIFT               (3U)
#define USB3_USB_ISTS_UHRESI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_UHRESI_SHIFT)) & USB3_USB_ISTS_UHRESI_MASK)
#define USB3_USB_ISTS_U3ENTI_MASK                (0x10U)
#define USB3_USB_ISTS_U3ENTI_SHIFT               (4U)
#define USB3_USB_ISTS_U3ENTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U3ENTI_SHIFT)) & USB3_USB_ISTS_U3ENTI_MASK)
#define USB3_USB_ISTS_U3EXTI_MASK                (0x20U)
#define USB3_USB_ISTS_U3EXTI_SHIFT               (5U)
#define USB3_USB_ISTS_U3EXTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U3EXTI_SHIFT)) & USB3_USB_ISTS_U3EXTI_MASK)
#define USB3_USB_ISTS_U2ENTI_MASK                (0x40U)
#define USB3_USB_ISTS_U2ENTI_SHIFT               (6U)
#define USB3_USB_ISTS_U2ENTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U2ENTI_SHIFT)) & USB3_USB_ISTS_U2ENTI_MASK)
#define USB3_USB_ISTS_U2EXTI_MASK                (0x80U)
#define USB3_USB_ISTS_U2EXTI_SHIFT               (7U)
#define USB3_USB_ISTS_U2EXTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U2EXTI_SHIFT)) & USB3_USB_ISTS_U2EXTI_MASK)
#define USB3_USB_ISTS_U1ENTI_MASK                (0x100U)
#define USB3_USB_ISTS_U1ENTI_SHIFT               (8U)
#define USB3_USB_ISTS_U1ENTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U1ENTI_SHIFT)) & USB3_USB_ISTS_U1ENTI_MASK)
#define USB3_USB_ISTS_U1EXTI_MASK                (0x200U)
#define USB3_USB_ISTS_U1EXTI_SHIFT               (9U)
#define USB3_USB_ISTS_U1EXTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U1EXTI_SHIFT)) & USB3_USB_ISTS_U1EXTI_MASK)
#define USB3_USB_ISTS_ITPI_MASK                  (0x400U)
#define USB3_USB_ISTS_ITPI_SHIFT                 (10U)
#define USB3_USB_ISTS_ITPI(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_ITPI_SHIFT)) & USB3_USB_ISTS_ITPI_MASK)
#define USB3_USB_ISTS_WAKEI_MASK                 (0x800U)
#define USB3_USB_ISTS_WAKEI_SHIFT                (11U)
#define USB3_USB_ISTS_WAKEI(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_WAKEI_SHIFT)) & USB3_USB_ISTS_WAKEI_MASK)
#define USB3_USB_ISTS_SPKTI_MASK                 (0x1000U)
#define USB3_USB_ISTS_SPKTI_SHIFT                (12U)
#define USB3_USB_ISTS_SPKTI(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_SPKTI_SHIFT)) & USB3_USB_ISTS_SPKTI_MASK)
#define USB3_USB_ISTS_RESERVED0_MASK             (0xE000U)
#define USB3_USB_ISTS_RESERVED0_SHIFT            (13U)
#define USB3_USB_ISTS_RESERVED0(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED0_SHIFT)) & USB3_USB_ISTS_RESERVED0_MASK)
#define USB3_USB_ISTS_CON2I_MASK                 (0x10000U)
#define USB3_USB_ISTS_CON2I_SHIFT                (16U)
#define USB3_USB_ISTS_CON2I(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_CON2I_SHIFT)) & USB3_USB_ISTS_CON2I_MASK)
#define USB3_USB_ISTS_DIS2I_MASK                 (0x20000U)
#define USB3_USB_ISTS_DIS2I_SHIFT                (17U)
#define USB3_USB_ISTS_DIS2I(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_DIS2I_SHIFT)) & USB3_USB_ISTS_DIS2I_MASK)
#define USB3_USB_ISTS_U2RESI_MASK                (0x40000U)
#define USB3_USB_ISTS_U2RESI_SHIFT               (18U)
#define USB3_USB_ISTS_U2RESI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_U2RESI_SHIFT)) & USB3_USB_ISTS_U2RESI_MASK)
#define USB3_USB_ISTS_RESERVED1_MASK             (0x80000U)
#define USB3_USB_ISTS_RESERVED1_SHIFT            (19U)
#define USB3_USB_ISTS_RESERVED1(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED1_SHIFT)) & USB3_USB_ISTS_RESERVED1_MASK)
#define USB3_USB_ISTS_L2ENTI_MASK                (0x100000U)
#define USB3_USB_ISTS_L2ENTI_SHIFT               (20U)
#define USB3_USB_ISTS_L2ENTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_L2ENTI_SHIFT)) & USB3_USB_ISTS_L2ENTI_MASK)
#define USB3_USB_ISTS_L2EXTI_MASK                (0x200000U)
#define USB3_USB_ISTS_L2EXTI_SHIFT               (21U)
#define USB3_USB_ISTS_L2EXTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_L2EXTI_SHIFT)) & USB3_USB_ISTS_L2EXTI_MASK)
#define USB3_USB_ISTS_RESERVED2_MASK             (0xC00000U)
#define USB3_USB_ISTS_RESERVED2_SHIFT            (22U)
#define USB3_USB_ISTS_RESERVED2(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED2_SHIFT)) & USB3_USB_ISTS_RESERVED2_MASK)
#define USB3_USB_ISTS_L1ENTI_MASK                (0x1000000U)
#define USB3_USB_ISTS_L1ENTI_SHIFT               (24U)
#define USB3_USB_ISTS_L1ENTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_L1ENTI_SHIFT)) & USB3_USB_ISTS_L1ENTI_MASK)
#define USB3_USB_ISTS_L1EXTI_MASK                (0x2000000U)
#define USB3_USB_ISTS_L1EXTI_SHIFT               (25U)
#define USB3_USB_ISTS_L1EXTI(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_L1EXTI_SHIFT)) & USB3_USB_ISTS_L1EXTI_MASK)
#define USB3_USB_ISTS_CFGRESI_MASK               (0x4000000U)
#define USB3_USB_ISTS_CFGRESI_SHIFT              (26U)
#define USB3_USB_ISTS_CFGRESI(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_CFGRESI_SHIFT)) & USB3_USB_ISTS_CFGRESI_MASK)
#define USB3_USB_ISTS_RESERVED3_MASK             (0x8000000U)
#define USB3_USB_ISTS_RESERVED3_SHIFT            (27U)
#define USB3_USB_ISTS_RESERVED3(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED3_SHIFT)) & USB3_USB_ISTS_RESERVED3_MASK)
#define USB3_USB_ISTS_UWRESSI_MASK               (0x10000000U)
#define USB3_USB_ISTS_UWRESSI_SHIFT              (28U)
#define USB3_USB_ISTS_UWRESSI(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_UWRESSI_SHIFT)) & USB3_USB_ISTS_UWRESSI_MASK)
#define USB3_USB_ISTS_UWRESEI_MASK               (0x20000000U)
#define USB3_USB_ISTS_UWRESEI_SHIFT              (29U)
#define USB3_USB_ISTS_UWRESEI(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_UWRESEI_SHIFT)) & USB3_USB_ISTS_UWRESEI_MASK)
#define USB3_USB_ISTS_RESERVED4_MASK             (0xC0000000U)
#define USB3_USB_ISTS_RESERVED4_SHIFT            (30U)
#define USB3_USB_ISTS_RESERVED4(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_ISTS_RESERVED4_SHIFT)) & USB3_USB_ISTS_RESERVED4_MASK)
/*! @} */

/*! @name EP_SEL - Endpoint Select */
/*! @{ */
#define USB3_EP_SEL_EPNO_MASK                    (0xFU)
#define USB3_EP_SEL_EPNO_SHIFT                   (0U)
#define USB3_EP_SEL_EPNO(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_EP_SEL_EPNO_SHIFT)) & USB3_EP_SEL_EPNO_MASK)
#define USB3_EP_SEL_RESERVED0_MASK               (0x70U)
#define USB3_EP_SEL_RESERVED0_SHIFT              (4U)
#define USB3_EP_SEL_RESERVED0(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_SEL_RESERVED0_SHIFT)) & USB3_EP_SEL_RESERVED0_MASK)
#define USB3_EP_SEL_DIR_MASK                     (0x80U)
#define USB3_EP_SEL_DIR_SHIFT                    (7U)
#define USB3_EP_SEL_DIR(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_EP_SEL_DIR_SHIFT)) & USB3_EP_SEL_DIR_MASK)
#define USB3_EP_SEL_RESERVED1_MASK               (0xFFFFFF00U)
#define USB3_EP_SEL_RESERVED1_SHIFT              (8U)
#define USB3_EP_SEL_RESERVED1(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_SEL_RESERVED1_SHIFT)) & USB3_EP_SEL_RESERVED1_MASK)
/*! @} */

/*! @name EP_TRADDR - Endpoint Transfer Ring Address */
/*! @{ */
#define USB3_EP_TRADDR_TRADDR_MASK               (0xFFFFFFFFU)
#define USB3_EP_TRADDR_TRADDR_SHIFT              (0U)
#define USB3_EP_TRADDR_TRADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_TRADDR_TRADDR_SHIFT)) & USB3_EP_TRADDR_TRADDR_MASK)
/*! @} */

/*! @name EP_CFG - Endpoint Configuration */
/*! @{ */
#define USB3_EP_CFG_ENABLE_MASK                  (0x1U)
#define USB3_EP_CFG_ENABLE_SHIFT                 (0U)
#define USB3_EP_CFG_ENABLE(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_ENABLE_SHIFT)) & USB3_EP_CFG_ENABLE_MASK)
#define USB3_EP_CFG_EPTYPE_MASK                  (0x6U)
#define USB3_EP_CFG_EPTYPE_SHIFT                 (1U)
#define USB3_EP_CFG_EPTYPE(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_EPTYPE_SHIFT)) & USB3_EP_CFG_EPTYPE_MASK)
#define USB3_EP_CFG_STREAM_EN_MASK               (0x8U)
#define USB3_EP_CFG_STREAM_EN_SHIFT              (3U)
#define USB3_EP_CFG_STREAM_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_STREAM_EN_SHIFT)) & USB3_EP_CFG_STREAM_EN_MASK)
#define USB3_EP_CFG_TDL_CHK_MASK                 (0x10U)
#define USB3_EP_CFG_TDL_CHK_SHIFT                (4U)
#define USB3_EP_CFG_TDL_CHK(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_TDL_CHK_SHIFT)) & USB3_EP_CFG_TDL_CHK_MASK)
#define USB3_EP_CFG_SID_CHK_MASK                 (0x20U)
#define USB3_EP_CFG_SID_CHK_SHIFT                (5U)
#define USB3_EP_CFG_SID_CHK(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_SID_CHK_SHIFT)) & USB3_EP_CFG_SID_CHK_MASK)
#define USB3_EP_CFG_RESERVED0_MASK               (0x40U)
#define USB3_EP_CFG_RESERVED0_SHIFT              (6U)
#define USB3_EP_CFG_RESERVED0(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_RESERVED0_SHIFT)) & USB3_EP_CFG_RESERVED0_MASK)
#define USB3_EP_CFG_EPENDIAN_MASK                (0x80U)
#define USB3_EP_CFG_EPENDIAN_SHIFT               (7U)
#define USB3_EP_CFG_EPENDIAN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_EPENDIAN_SHIFT)) & USB3_EP_CFG_EPENDIAN_MASK)
#define USB3_EP_CFG_MAXBURST_MASK                (0xF00U)
#define USB3_EP_CFG_MAXBURST_SHIFT               (8U)
#define USB3_EP_CFG_MAXBURST(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_MAXBURST_SHIFT)) & USB3_EP_CFG_MAXBURST_MASK)
#define USB3_EP_CFG_RESERVED1_MASK               (0x3000U)
#define USB3_EP_CFG_RESERVED1_SHIFT              (12U)
#define USB3_EP_CFG_RESERVED1(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_RESERVED1_SHIFT)) & USB3_EP_CFG_RESERVED1_MASK)
#define USB3_EP_CFG_MULT_MASK                    (0xC000U)
#define USB3_EP_CFG_MULT_SHIFT                   (14U)
#define USB3_EP_CFG_MULT(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_MULT_SHIFT)) & USB3_EP_CFG_MULT_MASK)
#define USB3_EP_CFG_MAXPKTSIZE_MASK              (0x7FF0000U)
#define USB3_EP_CFG_MAXPKTSIZE_SHIFT             (16U)
#define USB3_EP_CFG_MAXPKTSIZE(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_MAXPKTSIZE_SHIFT)) & USB3_EP_CFG_MAXPKTSIZE_MASK)
#define USB3_EP_CFG_BUFFERING_MASK               (0xF8000000U)
#define USB3_EP_CFG_BUFFERING_SHIFT              (27U)
#define USB3_EP_CFG_BUFFERING(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_CFG_BUFFERING_SHIFT)) & USB3_EP_CFG_BUFFERING_MASK)
/*! @} */

/*! @name EP_CMD - Endpoint Command */
/*! @{ */
#define USB3_EP_CMD_EPRST_MASK                   (0x1U)
#define USB3_EP_CMD_EPRST_SHIFT                  (0U)
#define USB3_EP_CMD_EPRST(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_EPRST_SHIFT)) & USB3_EP_CMD_EPRST_MASK)
#define USB3_EP_CMD_SSTALL_MASK                  (0x2U)
#define USB3_EP_CMD_SSTALL_SHIFT                 (1U)
#define USB3_EP_CMD_SSTALL(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_SSTALL_SHIFT)) & USB3_EP_CMD_SSTALL_MASK)
#define USB3_EP_CMD_CSTALL_MASK                  (0x4U)
#define USB3_EP_CMD_CSTALL_SHIFT                 (2U)
#define USB3_EP_CMD_CSTALL(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_CSTALL_SHIFT)) & USB3_EP_CMD_CSTALL_MASK)
#define USB3_EP_CMD_ERDY_MASK                    (0x8U)
#define USB3_EP_CMD_ERDY_SHIFT                   (3U)
#define USB3_EP_CMD_ERDY(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_ERDY_SHIFT)) & USB3_EP_CMD_ERDY_MASK)
#define USB3_EP_CMD_RESERVED_MASK                (0x10U)
#define USB3_EP_CMD_RESERVED_SHIFT               (4U)
#define USB3_EP_CMD_RESERVED(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_RESERVED_SHIFT)) & USB3_EP_CMD_RESERVED_MASK)
#define USB3_EP_CMD_REQ_CMPL_MASK                (0x20U)
#define USB3_EP_CMD_REQ_CMPL_SHIFT               (5U)
#define USB3_EP_CMD_REQ_CMPL(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_REQ_CMPL_SHIFT)) & USB3_EP_CMD_REQ_CMPL_MASK)
#define USB3_EP_CMD_DRDY_MASK                    (0x40U)
#define USB3_EP_CMD_DRDY_SHIFT                   (6U)
#define USB3_EP_CMD_DRDY(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_DRDY_SHIFT)) & USB3_EP_CMD_DRDY_MASK)
#define USB3_EP_CMD_DFLUSH_MASK                  (0x80U)
#define USB3_EP_CMD_DFLUSH_SHIFT                 (7U)
#define USB3_EP_CMD_DFLUSH(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_DFLUSH_SHIFT)) & USB3_EP_CMD_DFLUSH_MASK)
#define USB3_EP_CMD_STDL_MASK                    (0x100U)
#define USB3_EP_CMD_STDL_SHIFT                   (8U)
#define USB3_EP_CMD_STDL(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_STDL_SHIFT)) & USB3_EP_CMD_STDL_MASK)
#define USB3_EP_CMD_TDL_MASK                     (0xFE00U)
#define USB3_EP_CMD_TDL_SHIFT                    (9U)
#define USB3_EP_CMD_TDL(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_TDL_SHIFT)) & USB3_EP_CMD_TDL_MASK)
#define USB3_EP_CMD_ERDY_SID_MASK                (0xFFFF0000U)
#define USB3_EP_CMD_ERDY_SID_SHIFT               (16U)
#define USB3_EP_CMD_ERDY_SID(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_EP_CMD_ERDY_SID_SHIFT)) & USB3_EP_CMD_ERDY_SID_MASK)
/*! @} */

/*! @name EP_STS - Endpoint Status */
/*! @{ */
#define USB3_EP_STS_SETUP_MASK                   (0x1U)
#define USB3_EP_STS_SETUP_SHIFT                  (0U)
#define USB3_EP_STS_SETUP(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SETUP_SHIFT)) & USB3_EP_STS_SETUP_MASK)
#define USB3_EP_STS_STALL_MASK                   (0x2U)
#define USB3_EP_STS_STALL_SHIFT                  (1U)
#define USB3_EP_STS_STALL(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_STALL_SHIFT)) & USB3_EP_STS_STALL_MASK)
#define USB3_EP_STS_IOC_MASK                     (0x4U)
#define USB3_EP_STS_IOC_SHIFT                    (2U)
#define USB3_EP_STS_IOC(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_IOC_SHIFT)) & USB3_EP_STS_IOC_MASK)
#define USB3_EP_STS_ISP_MASK                     (0x8U)
#define USB3_EP_STS_ISP_SHIFT                    (3U)
#define USB3_EP_STS_ISP(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_ISP_SHIFT)) & USB3_EP_STS_ISP_MASK)
#define USB3_EP_STS_DESCMIS_MASK                 (0x10U)
#define USB3_EP_STS_DESCMIS_SHIFT                (4U)
#define USB3_EP_STS_DESCMIS(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_DESCMIS_SHIFT)) & USB3_EP_STS_DESCMIS_MASK)
#define USB3_EP_STS_STREAMR_MASK                 (0x20U)
#define USB3_EP_STS_STREAMR_SHIFT                (5U)
#define USB3_EP_STS_STREAMR(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_STREAMR_SHIFT)) & USB3_EP_STS_STREAMR_MASK)
#define USB3_EP_STS_MD_EXIT_MASK                 (0x40U)
#define USB3_EP_STS_MD_EXIT_SHIFT                (6U)
#define USB3_EP_STS_MD_EXIT(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_MD_EXIT_SHIFT)) & USB3_EP_STS_MD_EXIT_MASK)
#define USB3_EP_STS_TRBERR_MASK                  (0x80U)
#define USB3_EP_STS_TRBERR_SHIFT                 (7U)
#define USB3_EP_STS_TRBERR(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_TRBERR_SHIFT)) & USB3_EP_STS_TRBERR_MASK)
#define USB3_EP_STS_NRDY_MASK                    (0x100U)
#define USB3_EP_STS_NRDY_SHIFT                   (8U)
#define USB3_EP_STS_NRDY(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_NRDY_SHIFT)) & USB3_EP_STS_NRDY_MASK)
#define USB3_EP_STS_DBUSY_MASK                   (0x200U)
#define USB3_EP_STS_DBUSY_SHIFT                  (9U)
#define USB3_EP_STS_DBUSY(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_DBUSY_SHIFT)) & USB3_EP_STS_DBUSY_MASK)
#define USB3_EP_STS_BUFFEMPTY_MASK               (0x400U)
#define USB3_EP_STS_BUFFEMPTY_SHIFT              (10U)
#define USB3_EP_STS_BUFFEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_BUFFEMPTY_SHIFT)) & USB3_EP_STS_BUFFEMPTY_MASK)
#define USB3_EP_STS_CCS_MASK                     (0x800U)
#define USB3_EP_STS_CCS_SHIFT                    (11U)
#define USB3_EP_STS_CCS(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_CCS_SHIFT)) & USB3_EP_STS_CCS_MASK)
#define USB3_EP_STS_PRIME_MASK                   (0x1000U)
#define USB3_EP_STS_PRIME_SHIFT                  (12U)
#define USB3_EP_STS_PRIME(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_PRIME_SHIFT)) & USB3_EP_STS_PRIME_MASK)
#define USB3_EP_STS_SIDERR_MASK                  (0x2000U)
#define USB3_EP_STS_SIDERR_SHIFT                 (13U)
#define USB3_EP_STS_SIDERR(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SIDERR_SHIFT)) & USB3_EP_STS_SIDERR_MASK)
#define USB3_EP_STS_OUTSMM_MASK                  (0x4000U)
#define USB3_EP_STS_OUTSMM_SHIFT                 (14U)
#define USB3_EP_STS_OUTSMM(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_OUTSMM_SHIFT)) & USB3_EP_STS_OUTSMM_MASK)
#define USB3_EP_STS_ISOERR_MASK                  (0x8000U)
#define USB3_EP_STS_ISOERR_SHIFT                 (15U)
#define USB3_EP_STS_ISOERR(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_ISOERR_SHIFT)) & USB3_EP_STS_ISOERR_MASK)
#define USB3_EP_STS_HOSTPP_MASK                  (0x10000U)
#define USB3_EP_STS_HOSTPP_SHIFT                 (16U)
#define USB3_EP_STS_HOSTPP(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_HOSTPP_SHIFT)) & USB3_EP_STS_HOSTPP_MASK)
#define USB3_EP_STS_SPSMST_MASK                  (0x60000U)
#define USB3_EP_STS_SPSMST_SHIFT                 (17U)
#define USB3_EP_STS_SPSMST(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SPSMST_SHIFT)) & USB3_EP_STS_SPSMST_MASK)
#define USB3_EP_STS_IOT_MASK                     (0x80000U)
#define USB3_EP_STS_IOT_SHIFT                    (19U)
#define USB3_EP_STS_IOT(x)                       (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_IOT_SHIFT)) & USB3_EP_STS_IOT_MASK)
#define USB3_EP_STS_RESERVED0_MASK               (0xF00000U)
#define USB3_EP_STS_RESERVED0_SHIFT              (20U)
#define USB3_EP_STS_RESERVED0(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_RESERVED0_SHIFT)) & USB3_EP_STS_RESERVED0_MASK)
#define USB3_EP_STS_OUTQ_NO_MASK                 (0xF000000U)
#define USB3_EP_STS_OUTQ_NO_SHIFT                (24U)
#define USB3_EP_STS_OUTQ_NO(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_OUTQ_NO_SHIFT)) & USB3_EP_STS_OUTQ_NO_MASK)
#define USB3_EP_STS_OUTQ_VAL_MASK                (0x10000000U)
#define USB3_EP_STS_OUTQ_VAL_SHIFT               (28U)
#define USB3_EP_STS_OUTQ_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_OUTQ_VAL_SHIFT)) & USB3_EP_STS_OUTQ_VAL_MASK)
#define USB3_EP_STS_RESERVED1_MASK               (0x60000000U)
#define USB3_EP_STS_RESERVED1_SHIFT              (29U)
#define USB3_EP_STS_RESERVED1(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_RESERVED1_SHIFT)) & USB3_EP_STS_RESERVED1_MASK)
#define USB3_EP_STS_STPWAIT_MASK                 (0x80000000U)
#define USB3_EP_STS_STPWAIT_SHIFT                (31U)
#define USB3_EP_STS_STPWAIT(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_STPWAIT_SHIFT)) & USB3_EP_STS_STPWAIT_MASK)
/*! @} */

/*! @name EP_STS_SID - Endpoint Status */
/*! @{ */
#define USB3_EP_STS_SID_SID_MASK                 (0xFFFFU)
#define USB3_EP_STS_SID_SID_SHIFT                (0U)
#define USB3_EP_STS_SID_SID(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SID_SID_SHIFT)) & USB3_EP_STS_SID_SID_MASK)
#define USB3_EP_STS_SID_RESERVED_MASK            (0xFFFF0000U)
#define USB3_EP_STS_SID_RESERVED_SHIFT           (16U)
#define USB3_EP_STS_SID_RESERVED(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_SID_RESERVED_SHIFT)) & USB3_EP_STS_SID_RESERVED_MASK)
/*! @} */

/*! @name EP_STS_EN - Endpoint Status Register Enable */
/*! @{ */
#define USB3_EP_STS_EN_SETUPEN_MASK              (0x1U)
#define USB3_EP_STS_EN_SETUPEN_SHIFT             (0U)
#define USB3_EP_STS_EN_SETUPEN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_SETUPEN_SHIFT)) & USB3_EP_STS_EN_SETUPEN_MASK)
#define USB3_EP_STS_EN_RESERVED0_MASK            (0xEU)
#define USB3_EP_STS_EN_RESERVED0_SHIFT           (1U)
#define USB3_EP_STS_EN_RESERVED0(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_RESERVED0_SHIFT)) & USB3_EP_STS_EN_RESERVED0_MASK)
#define USB3_EP_STS_EN_DESCMISEN_MASK            (0x10U)
#define USB3_EP_STS_EN_DESCMISEN_SHIFT           (4U)
#define USB3_EP_STS_EN_DESCMISEN(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_DESCMISEN_SHIFT)) & USB3_EP_STS_EN_DESCMISEN_MASK)
#define USB3_EP_STS_EN_STREAMREN_MASK            (0x20U)
#define USB3_EP_STS_EN_STREAMREN_SHIFT           (5U)
#define USB3_EP_STS_EN_STREAMREN(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_STREAMREN_SHIFT)) & USB3_EP_STS_EN_STREAMREN_MASK)
#define USB3_EP_STS_EN_MD_EXITEN_MASK            (0x40U)
#define USB3_EP_STS_EN_MD_EXITEN_SHIFT           (6U)
#define USB3_EP_STS_EN_MD_EXITEN(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_MD_EXITEN_SHIFT)) & USB3_EP_STS_EN_MD_EXITEN_MASK)
#define USB3_EP_STS_EN_TRBERREN_MASK             (0x80U)
#define USB3_EP_STS_EN_TRBERREN_SHIFT            (7U)
#define USB3_EP_STS_EN_TRBERREN(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_TRBERREN_SHIFT)) & USB3_EP_STS_EN_TRBERREN_MASK)
#define USB3_EP_STS_EN_NRDYEN_MASK               (0x100U)
#define USB3_EP_STS_EN_NRDYEN_SHIFT              (8U)
#define USB3_EP_STS_EN_NRDYEN(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_NRDYEN_SHIFT)) & USB3_EP_STS_EN_NRDYEN_MASK)
#define USB3_EP_STS_EN_RESERVED1_MASK            (0xE00U)
#define USB3_EP_STS_EN_RESERVED1_SHIFT           (9U)
#define USB3_EP_STS_EN_RESERVED1(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_RESERVED1_SHIFT)) & USB3_EP_STS_EN_RESERVED1_MASK)
#define USB3_EP_STS_EN_PRIMEEN_MASK              (0x1000U)
#define USB3_EP_STS_EN_PRIMEEN_SHIFT             (12U)
#define USB3_EP_STS_EN_PRIMEEN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_PRIMEEN_SHIFT)) & USB3_EP_STS_EN_PRIMEEN_MASK)
#define USB3_EP_STS_EN_SIDERREN_MASK             (0x2000U)
#define USB3_EP_STS_EN_SIDERREN_SHIFT            (13U)
#define USB3_EP_STS_EN_SIDERREN(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_SIDERREN_SHIFT)) & USB3_EP_STS_EN_SIDERREN_MASK)
#define USB3_EP_STS_EN_OUTSMMEN_MASK             (0x4000U)
#define USB3_EP_STS_EN_OUTSMMEN_SHIFT            (14U)
#define USB3_EP_STS_EN_OUTSMMEN(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_OUTSMMEN_SHIFT)) & USB3_EP_STS_EN_OUTSMMEN_MASK)
#define USB3_EP_STS_EN_ISOERREN_MASK             (0x8000U)
#define USB3_EP_STS_EN_ISOERREN_SHIFT            (15U)
#define USB3_EP_STS_EN_ISOERREN(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_ISOERREN_SHIFT)) & USB3_EP_STS_EN_ISOERREN_MASK)
#define USB3_EP_STS_EN_RESERVED2_MASK            (0x70000U)
#define USB3_EP_STS_EN_RESERVED2_SHIFT           (16U)
#define USB3_EP_STS_EN_RESERVED2(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_RESERVED2_SHIFT)) & USB3_EP_STS_EN_RESERVED2_MASK)
#define USB3_EP_STS_EN_IOTEN_MASK                (0x80000U)
#define USB3_EP_STS_EN_IOTEN_SHIFT               (19U)
#define USB3_EP_STS_EN_IOTEN(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_IOTEN_SHIFT)) & USB3_EP_STS_EN_IOTEN_MASK)
#define USB3_EP_STS_EN_RESERVED3_MASK            (0x7FF00000U)
#define USB3_EP_STS_EN_RESERVED3_SHIFT           (20U)
#define USB3_EP_STS_EN_RESERVED3(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_RESERVED3_SHIFT)) & USB3_EP_STS_EN_RESERVED3_MASK)
#define USB3_EP_STS_EN_STPWAITEN_MASK            (0x80000000U)
#define USB3_EP_STS_EN_STPWAITEN_SHIFT           (31U)
#define USB3_EP_STS_EN_STPWAITEN(x)              (((uint32_t)(((uint32_t)(x)) << USB3_EP_STS_EN_STPWAITEN_SHIFT)) & USB3_EP_STS_EN_STPWAITEN_MASK)
/*! @} */

/*! @name DRBL - Doorbell Register */
/*! @{ */
#define USB3_DRBL_DRBL0O_MASK                    (0x1U)
#define USB3_DRBL_DRBL0O_SHIFT                   (0U)
#define USB3_DRBL_DRBL0O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL0O_SHIFT)) & USB3_DRBL_DRBL0O_MASK)
#define USB3_DRBL_DRBL1O_MASK                    (0x2U)
#define USB3_DRBL_DRBL1O_SHIFT                   (1U)
#define USB3_DRBL_DRBL1O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL1O_SHIFT)) & USB3_DRBL_DRBL1O_MASK)
#define USB3_DRBL_DRBL2O_MASK                    (0x4U)
#define USB3_DRBL_DRBL2O_SHIFT                   (2U)
#define USB3_DRBL_DRBL2O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL2O_SHIFT)) & USB3_DRBL_DRBL2O_MASK)
#define USB3_DRBL_DRBL3O_MASK                    (0x8U)
#define USB3_DRBL_DRBL3O_SHIFT                   (3U)
#define USB3_DRBL_DRBL3O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL3O_SHIFT)) & USB3_DRBL_DRBL3O_MASK)
#define USB3_DRBL_DRBL4O_MASK                    (0x10U)
#define USB3_DRBL_DRBL4O_SHIFT                   (4U)
#define USB3_DRBL_DRBL4O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL4O_SHIFT)) & USB3_DRBL_DRBL4O_MASK)
#define USB3_DRBL_DRBL5O_MASK                    (0x20U)
#define USB3_DRBL_DRBL5O_SHIFT                   (5U)
#define USB3_DRBL_DRBL5O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL5O_SHIFT)) & USB3_DRBL_DRBL5O_MASK)
#define USB3_DRBL_DRBL6O_MASK                    (0x40U)
#define USB3_DRBL_DRBL6O_SHIFT                   (6U)
#define USB3_DRBL_DRBL6O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL6O_SHIFT)) & USB3_DRBL_DRBL6O_MASK)
#define USB3_DRBL_DRBL7O_MASK                    (0x80U)
#define USB3_DRBL_DRBL7O_SHIFT                   (7U)
#define USB3_DRBL_DRBL7O(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL7O_SHIFT)) & USB3_DRBL_DRBL7O_MASK)
#define USB3_DRBL_reserved8_MASK                 (0x100U)
#define USB3_DRBL_reserved8_SHIFT                (8U)
#define USB3_DRBL_reserved8(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved8_SHIFT)) & USB3_DRBL_reserved8_MASK)
#define USB3_DRBL_reserved9_MASK                 (0x200U)
#define USB3_DRBL_reserved9_SHIFT                (9U)
#define USB3_DRBL_reserved9(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved9_SHIFT)) & USB3_DRBL_reserved9_MASK)
#define USB3_DRBL_reserved10_MASK                (0x400U)
#define USB3_DRBL_reserved10_SHIFT               (10U)
#define USB3_DRBL_reserved10(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved10_SHIFT)) & USB3_DRBL_reserved10_MASK)
#define USB3_DRBL_reserved11_MASK                (0x800U)
#define USB3_DRBL_reserved11_SHIFT               (11U)
#define USB3_DRBL_reserved11(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved11_SHIFT)) & USB3_DRBL_reserved11_MASK)
#define USB3_DRBL_reserved12_MASK                (0x1000U)
#define USB3_DRBL_reserved12_SHIFT               (12U)
#define USB3_DRBL_reserved12(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved12_SHIFT)) & USB3_DRBL_reserved12_MASK)
#define USB3_DRBL_reserved13_MASK                (0x2000U)
#define USB3_DRBL_reserved13_SHIFT               (13U)
#define USB3_DRBL_reserved13(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved13_SHIFT)) & USB3_DRBL_reserved13_MASK)
#define USB3_DRBL_reserved14_MASK                (0x4000U)
#define USB3_DRBL_reserved14_SHIFT               (14U)
#define USB3_DRBL_reserved14(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved14_SHIFT)) & USB3_DRBL_reserved14_MASK)
#define USB3_DRBL_reserved15_MASK                (0x8000U)
#define USB3_DRBL_reserved15_SHIFT               (15U)
#define USB3_DRBL_reserved15(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved15_SHIFT)) & USB3_DRBL_reserved15_MASK)
#define USB3_DRBL_DRBL0I_MASK                    (0x10000U)
#define USB3_DRBL_DRBL0I_SHIFT                   (16U)
#define USB3_DRBL_DRBL0I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL0I_SHIFT)) & USB3_DRBL_DRBL0I_MASK)
#define USB3_DRBL_DRBL1I_MASK                    (0x20000U)
#define USB3_DRBL_DRBL1I_SHIFT                   (17U)
#define USB3_DRBL_DRBL1I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL1I_SHIFT)) & USB3_DRBL_DRBL1I_MASK)
#define USB3_DRBL_DRBL2I_MASK                    (0x40000U)
#define USB3_DRBL_DRBL2I_SHIFT                   (18U)
#define USB3_DRBL_DRBL2I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL2I_SHIFT)) & USB3_DRBL_DRBL2I_MASK)
#define USB3_DRBL_DRBL3I_MASK                    (0x80000U)
#define USB3_DRBL_DRBL3I_SHIFT                   (19U)
#define USB3_DRBL_DRBL3I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL3I_SHIFT)) & USB3_DRBL_DRBL3I_MASK)
#define USB3_DRBL_DRBL4I_MASK                    (0x100000U)
#define USB3_DRBL_DRBL4I_SHIFT                   (20U)
#define USB3_DRBL_DRBL4I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL4I_SHIFT)) & USB3_DRBL_DRBL4I_MASK)
#define USB3_DRBL_DRBL5I_MASK                    (0x200000U)
#define USB3_DRBL_DRBL5I_SHIFT                   (21U)
#define USB3_DRBL_DRBL5I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL5I_SHIFT)) & USB3_DRBL_DRBL5I_MASK)
#define USB3_DRBL_DRBL6I_MASK                    (0x400000U)
#define USB3_DRBL_DRBL6I_SHIFT                   (22U)
#define USB3_DRBL_DRBL6I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL6I_SHIFT)) & USB3_DRBL_DRBL6I_MASK)
#define USB3_DRBL_DRBL7I_MASK                    (0x800000U)
#define USB3_DRBL_DRBL7I_SHIFT                   (23U)
#define USB3_DRBL_DRBL7I(x)                      (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_DRBL7I_SHIFT)) & USB3_DRBL_DRBL7I_MASK)
#define USB3_DRBL_reserved24_MASK                (0x1000000U)
#define USB3_DRBL_reserved24_SHIFT               (24U)
#define USB3_DRBL_reserved24(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved24_SHIFT)) & USB3_DRBL_reserved24_MASK)
#define USB3_DRBL_reserved25_MASK                (0x2000000U)
#define USB3_DRBL_reserved25_SHIFT               (25U)
#define USB3_DRBL_reserved25(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved25_SHIFT)) & USB3_DRBL_reserved25_MASK)
#define USB3_DRBL_reserved26_MASK                (0x4000000U)
#define USB3_DRBL_reserved26_SHIFT               (26U)
#define USB3_DRBL_reserved26(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved26_SHIFT)) & USB3_DRBL_reserved26_MASK)
#define USB3_DRBL_reserved27_MASK                (0x8000000U)
#define USB3_DRBL_reserved27_SHIFT               (27U)
#define USB3_DRBL_reserved27(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved27_SHIFT)) & USB3_DRBL_reserved27_MASK)
#define USB3_DRBL_reserved28_MASK                (0x10000000U)
#define USB3_DRBL_reserved28_SHIFT               (28U)
#define USB3_DRBL_reserved28(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved28_SHIFT)) & USB3_DRBL_reserved28_MASK)
#define USB3_DRBL_reserved29_MASK                (0x20000000U)
#define USB3_DRBL_reserved29_SHIFT               (29U)
#define USB3_DRBL_reserved29(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved29_SHIFT)) & USB3_DRBL_reserved29_MASK)
#define USB3_DRBL_reserved30_MASK                (0x40000000U)
#define USB3_DRBL_reserved30_SHIFT               (30U)
#define USB3_DRBL_reserved30(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved30_SHIFT)) & USB3_DRBL_reserved30_MASK)
#define USB3_DRBL_reserved31_MASK                (0x80000000U)
#define USB3_DRBL_reserved31_SHIFT               (31U)
#define USB3_DRBL_reserved31(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_DRBL_reserved31_SHIFT)) & USB3_DRBL_reserved31_MASK)
/*! @} */

/*! @name EP_IEN - Endpoints Interrupt Enable) */
/*! @{ */
#define USB3_EP_IEN_EOUTEN0_MASK                 (0x1U)
#define USB3_EP_IEN_EOUTEN0_SHIFT                (0U)
#define USB3_EP_IEN_EOUTEN0(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN0_SHIFT)) & USB3_EP_IEN_EOUTEN0_MASK)
#define USB3_EP_IEN_EOUTEN1_MASK                 (0x2U)
#define USB3_EP_IEN_EOUTEN1_SHIFT                (1U)
#define USB3_EP_IEN_EOUTEN1(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN1_SHIFT)) & USB3_EP_IEN_EOUTEN1_MASK)
#define USB3_EP_IEN_EOUTEN2_MASK                 (0x4U)
#define USB3_EP_IEN_EOUTEN2_SHIFT                (2U)
#define USB3_EP_IEN_EOUTEN2(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN2_SHIFT)) & USB3_EP_IEN_EOUTEN2_MASK)
#define USB3_EP_IEN_EOUTEN3_MASK                 (0x8U)
#define USB3_EP_IEN_EOUTEN3_SHIFT                (3U)
#define USB3_EP_IEN_EOUTEN3(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN3_SHIFT)) & USB3_EP_IEN_EOUTEN3_MASK)
#define USB3_EP_IEN_EOUTEN4_MASK                 (0x10U)
#define USB3_EP_IEN_EOUTEN4_SHIFT                (4U)
#define USB3_EP_IEN_EOUTEN4(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN4_SHIFT)) & USB3_EP_IEN_EOUTEN4_MASK)
#define USB3_EP_IEN_EOUTEN5_MASK                 (0x20U)
#define USB3_EP_IEN_EOUTEN5_SHIFT                (5U)
#define USB3_EP_IEN_EOUTEN5(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN5_SHIFT)) & USB3_EP_IEN_EOUTEN5_MASK)
#define USB3_EP_IEN_EOUTEN6_MASK                 (0x40U)
#define USB3_EP_IEN_EOUTEN6_SHIFT                (6U)
#define USB3_EP_IEN_EOUTEN6(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN6_SHIFT)) & USB3_EP_IEN_EOUTEN6_MASK)
#define USB3_EP_IEN_EOUTEN7_MASK                 (0x80U)
#define USB3_EP_IEN_EOUTEN7_SHIFT                (7U)
#define USB3_EP_IEN_EOUTEN7(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EOUTEN7_SHIFT)) & USB3_EP_IEN_EOUTEN7_MASK)
#define USB3_EP_IEN_reserved8_MASK               (0x100U)
#define USB3_EP_IEN_reserved8_SHIFT              (8U)
#define USB3_EP_IEN_reserved8(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved8_SHIFT)) & USB3_EP_IEN_reserved8_MASK)
#define USB3_EP_IEN_reserved9_MASK               (0x200U)
#define USB3_EP_IEN_reserved9_SHIFT              (9U)
#define USB3_EP_IEN_reserved9(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved9_SHIFT)) & USB3_EP_IEN_reserved9_MASK)
#define USB3_EP_IEN_reserved10_MASK              (0x400U)
#define USB3_EP_IEN_reserved10_SHIFT             (10U)
#define USB3_EP_IEN_reserved10(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved10_SHIFT)) & USB3_EP_IEN_reserved10_MASK)
#define USB3_EP_IEN_reserved11_MASK              (0x800U)
#define USB3_EP_IEN_reserved11_SHIFT             (11U)
#define USB3_EP_IEN_reserved11(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved11_SHIFT)) & USB3_EP_IEN_reserved11_MASK)
#define USB3_EP_IEN_reserved12_MASK              (0x1000U)
#define USB3_EP_IEN_reserved12_SHIFT             (12U)
#define USB3_EP_IEN_reserved12(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved12_SHIFT)) & USB3_EP_IEN_reserved12_MASK)
#define USB3_EP_IEN_reserved13_MASK              (0x2000U)
#define USB3_EP_IEN_reserved13_SHIFT             (13U)
#define USB3_EP_IEN_reserved13(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved13_SHIFT)) & USB3_EP_IEN_reserved13_MASK)
#define USB3_EP_IEN_reserved14_MASK              (0x4000U)
#define USB3_EP_IEN_reserved14_SHIFT             (14U)
#define USB3_EP_IEN_reserved14(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved14_SHIFT)) & USB3_EP_IEN_reserved14_MASK)
#define USB3_EP_IEN_reserved15_MASK              (0x8000U)
#define USB3_EP_IEN_reserved15_SHIFT             (15U)
#define USB3_EP_IEN_reserved15(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved15_SHIFT)) & USB3_EP_IEN_reserved15_MASK)
#define USB3_EP_IEN_EINEN0_MASK                  (0x10000U)
#define USB3_EP_IEN_EINEN0_SHIFT                 (16U)
#define USB3_EP_IEN_EINEN0(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN0_SHIFT)) & USB3_EP_IEN_EINEN0_MASK)
#define USB3_EP_IEN_EINEN1_MASK                  (0x20000U)
#define USB3_EP_IEN_EINEN1_SHIFT                 (17U)
#define USB3_EP_IEN_EINEN1(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN1_SHIFT)) & USB3_EP_IEN_EINEN1_MASK)
#define USB3_EP_IEN_EINEN2_MASK                  (0x40000U)
#define USB3_EP_IEN_EINEN2_SHIFT                 (18U)
#define USB3_EP_IEN_EINEN2(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN2_SHIFT)) & USB3_EP_IEN_EINEN2_MASK)
#define USB3_EP_IEN_EINEN3_MASK                  (0x80000U)
#define USB3_EP_IEN_EINEN3_SHIFT                 (19U)
#define USB3_EP_IEN_EINEN3(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN3_SHIFT)) & USB3_EP_IEN_EINEN3_MASK)
#define USB3_EP_IEN_EINEN4_MASK                  (0x100000U)
#define USB3_EP_IEN_EINEN4_SHIFT                 (20U)
#define USB3_EP_IEN_EINEN4(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN4_SHIFT)) & USB3_EP_IEN_EINEN4_MASK)
#define USB3_EP_IEN_EINEN5_MASK                  (0x200000U)
#define USB3_EP_IEN_EINEN5_SHIFT                 (21U)
#define USB3_EP_IEN_EINEN5(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN5_SHIFT)) & USB3_EP_IEN_EINEN5_MASK)
#define USB3_EP_IEN_EINEN6_MASK                  (0x400000U)
#define USB3_EP_IEN_EINEN6_SHIFT                 (22U)
#define USB3_EP_IEN_EINEN6(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN6_SHIFT)) & USB3_EP_IEN_EINEN6_MASK)
#define USB3_EP_IEN_EINEN7_MASK                  (0x800000U)
#define USB3_EP_IEN_EINEN7_SHIFT                 (23U)
#define USB3_EP_IEN_EINEN7(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_EINEN7_SHIFT)) & USB3_EP_IEN_EINEN7_MASK)
#define USB3_EP_IEN_reserved24_MASK              (0x1000000U)
#define USB3_EP_IEN_reserved24_SHIFT             (24U)
#define USB3_EP_IEN_reserved24(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved24_SHIFT)) & USB3_EP_IEN_reserved24_MASK)
#define USB3_EP_IEN_reserved25_MASK              (0x2000000U)
#define USB3_EP_IEN_reserved25_SHIFT             (25U)
#define USB3_EP_IEN_reserved25(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved25_SHIFT)) & USB3_EP_IEN_reserved25_MASK)
#define USB3_EP_IEN_reserved26_MASK              (0x4000000U)
#define USB3_EP_IEN_reserved26_SHIFT             (26U)
#define USB3_EP_IEN_reserved26(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved26_SHIFT)) & USB3_EP_IEN_reserved26_MASK)
#define USB3_EP_IEN_reserved27_MASK              (0x8000000U)
#define USB3_EP_IEN_reserved27_SHIFT             (27U)
#define USB3_EP_IEN_reserved27(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved27_SHIFT)) & USB3_EP_IEN_reserved27_MASK)
#define USB3_EP_IEN_reserved28_MASK              (0x10000000U)
#define USB3_EP_IEN_reserved28_SHIFT             (28U)
#define USB3_EP_IEN_reserved28(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved28_SHIFT)) & USB3_EP_IEN_reserved28_MASK)
#define USB3_EP_IEN_reserved29_MASK              (0x20000000U)
#define USB3_EP_IEN_reserved29_SHIFT             (29U)
#define USB3_EP_IEN_reserved29(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved29_SHIFT)) & USB3_EP_IEN_reserved29_MASK)
#define USB3_EP_IEN_reserved30_MASK              (0x40000000U)
#define USB3_EP_IEN_reserved30_SHIFT             (30U)
#define USB3_EP_IEN_reserved30(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved30_SHIFT)) & USB3_EP_IEN_reserved30_MASK)
#define USB3_EP_IEN_reserved31_MASK              (0x80000000U)
#define USB3_EP_IEN_reserved31_SHIFT             (31U)
#define USB3_EP_IEN_reserved31(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_IEN_reserved31_SHIFT)) & USB3_EP_IEN_reserved31_MASK)
/*! @} */

/*! @name EP_ISTS - Endpoints Interrupt Status */
/*! @{ */
#define USB3_EP_ISTS_EOUT0_MASK                  (0x1U)
#define USB3_EP_ISTS_EOUT0_SHIFT                 (0U)
#define USB3_EP_ISTS_EOUT0(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT0_SHIFT)) & USB3_EP_ISTS_EOUT0_MASK)
#define USB3_EP_ISTS_EOUT1_MASK                  (0x2U)
#define USB3_EP_ISTS_EOUT1_SHIFT                 (1U)
#define USB3_EP_ISTS_EOUT1(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT1_SHIFT)) & USB3_EP_ISTS_EOUT1_MASK)
#define USB3_EP_ISTS_EOUT2_MASK                  (0x4U)
#define USB3_EP_ISTS_EOUT2_SHIFT                 (2U)
#define USB3_EP_ISTS_EOUT2(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT2_SHIFT)) & USB3_EP_ISTS_EOUT2_MASK)
#define USB3_EP_ISTS_EOUT3_MASK                  (0x8U)
#define USB3_EP_ISTS_EOUT3_SHIFT                 (3U)
#define USB3_EP_ISTS_EOUT3(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT3_SHIFT)) & USB3_EP_ISTS_EOUT3_MASK)
#define USB3_EP_ISTS_EOUT4_MASK                  (0x10U)
#define USB3_EP_ISTS_EOUT4_SHIFT                 (4U)
#define USB3_EP_ISTS_EOUT4(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT4_SHIFT)) & USB3_EP_ISTS_EOUT4_MASK)
#define USB3_EP_ISTS_EOUT5_MASK                  (0x20U)
#define USB3_EP_ISTS_EOUT5_SHIFT                 (5U)
#define USB3_EP_ISTS_EOUT5(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT5_SHIFT)) & USB3_EP_ISTS_EOUT5_MASK)
#define USB3_EP_ISTS_EOUT6_MASK                  (0x40U)
#define USB3_EP_ISTS_EOUT6_SHIFT                 (6U)
#define USB3_EP_ISTS_EOUT6(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT6_SHIFT)) & USB3_EP_ISTS_EOUT6_MASK)
#define USB3_EP_ISTS_EOUT7_MASK                  (0x80U)
#define USB3_EP_ISTS_EOUT7_SHIFT                 (7U)
#define USB3_EP_ISTS_EOUT7(x)                    (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EOUT7_SHIFT)) & USB3_EP_ISTS_EOUT7_MASK)
#define USB3_EP_ISTS_reserved8_MASK              (0x100U)
#define USB3_EP_ISTS_reserved8_SHIFT             (8U)
#define USB3_EP_ISTS_reserved8(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved8_SHIFT)) & USB3_EP_ISTS_reserved8_MASK)
#define USB3_EP_ISTS_reserved9_MASK              (0x200U)
#define USB3_EP_ISTS_reserved9_SHIFT             (9U)
#define USB3_EP_ISTS_reserved9(x)                (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved9_SHIFT)) & USB3_EP_ISTS_reserved9_MASK)
#define USB3_EP_ISTS_reserved10_MASK             (0x400U)
#define USB3_EP_ISTS_reserved10_SHIFT            (10U)
#define USB3_EP_ISTS_reserved10(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved10_SHIFT)) & USB3_EP_ISTS_reserved10_MASK)
#define USB3_EP_ISTS_reserved11_MASK             (0x800U)
#define USB3_EP_ISTS_reserved11_SHIFT            (11U)
#define USB3_EP_ISTS_reserved11(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved11_SHIFT)) & USB3_EP_ISTS_reserved11_MASK)
#define USB3_EP_ISTS_reserved12_MASK             (0x1000U)
#define USB3_EP_ISTS_reserved12_SHIFT            (12U)
#define USB3_EP_ISTS_reserved12(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved12_SHIFT)) & USB3_EP_ISTS_reserved12_MASK)
#define USB3_EP_ISTS_reserved13_MASK             (0x2000U)
#define USB3_EP_ISTS_reserved13_SHIFT            (13U)
#define USB3_EP_ISTS_reserved13(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved13_SHIFT)) & USB3_EP_ISTS_reserved13_MASK)
#define USB3_EP_ISTS_reserved14_MASK             (0x4000U)
#define USB3_EP_ISTS_reserved14_SHIFT            (14U)
#define USB3_EP_ISTS_reserved14(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved14_SHIFT)) & USB3_EP_ISTS_reserved14_MASK)
#define USB3_EP_ISTS_reserved15_MASK             (0x8000U)
#define USB3_EP_ISTS_reserved15_SHIFT            (15U)
#define USB3_EP_ISTS_reserved15(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved15_SHIFT)) & USB3_EP_ISTS_reserved15_MASK)
#define USB3_EP_ISTS_EIN0_MASK                   (0x10000U)
#define USB3_EP_ISTS_EIN0_SHIFT                  (16U)
#define USB3_EP_ISTS_EIN0(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN0_SHIFT)) & USB3_EP_ISTS_EIN0_MASK)
#define USB3_EP_ISTS_EIN1_MASK                   (0x20000U)
#define USB3_EP_ISTS_EIN1_SHIFT                  (17U)
#define USB3_EP_ISTS_EIN1(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN1_SHIFT)) & USB3_EP_ISTS_EIN1_MASK)
#define USB3_EP_ISTS_EIN2_MASK                   (0x40000U)
#define USB3_EP_ISTS_EIN2_SHIFT                  (18U)
#define USB3_EP_ISTS_EIN2(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN2_SHIFT)) & USB3_EP_ISTS_EIN2_MASK)
#define USB3_EP_ISTS_EIN3_MASK                   (0x80000U)
#define USB3_EP_ISTS_EIN3_SHIFT                  (19U)
#define USB3_EP_ISTS_EIN3(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN3_SHIFT)) & USB3_EP_ISTS_EIN3_MASK)
#define USB3_EP_ISTS_EIN4_MASK                   (0x100000U)
#define USB3_EP_ISTS_EIN4_SHIFT                  (20U)
#define USB3_EP_ISTS_EIN4(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN4_SHIFT)) & USB3_EP_ISTS_EIN4_MASK)
#define USB3_EP_ISTS_EIN5_MASK                   (0x200000U)
#define USB3_EP_ISTS_EIN5_SHIFT                  (21U)
#define USB3_EP_ISTS_EIN5(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN5_SHIFT)) & USB3_EP_ISTS_EIN5_MASK)
#define USB3_EP_ISTS_EIN6_MASK                   (0x400000U)
#define USB3_EP_ISTS_EIN6_SHIFT                  (22U)
#define USB3_EP_ISTS_EIN6(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN6_SHIFT)) & USB3_EP_ISTS_EIN6_MASK)
#define USB3_EP_ISTS_EIN7_MASK                   (0x800000U)
#define USB3_EP_ISTS_EIN7_SHIFT                  (23U)
#define USB3_EP_ISTS_EIN7(x)                     (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_EIN7_SHIFT)) & USB3_EP_ISTS_EIN7_MASK)
#define USB3_EP_ISTS_reserved24_MASK             (0x1000000U)
#define USB3_EP_ISTS_reserved24_SHIFT            (24U)
#define USB3_EP_ISTS_reserved24(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved24_SHIFT)) & USB3_EP_ISTS_reserved24_MASK)
#define USB3_EP_ISTS_reserved25_MASK             (0x2000000U)
#define USB3_EP_ISTS_reserved25_SHIFT            (25U)
#define USB3_EP_ISTS_reserved25(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved25_SHIFT)) & USB3_EP_ISTS_reserved25_MASK)
#define USB3_EP_ISTS_reserved26_MASK             (0x4000000U)
#define USB3_EP_ISTS_reserved26_SHIFT            (26U)
#define USB3_EP_ISTS_reserved26(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved26_SHIFT)) & USB3_EP_ISTS_reserved26_MASK)
#define USB3_EP_ISTS_reserved27_MASK             (0x8000000U)
#define USB3_EP_ISTS_reserved27_SHIFT            (27U)
#define USB3_EP_ISTS_reserved27(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved27_SHIFT)) & USB3_EP_ISTS_reserved27_MASK)
#define USB3_EP_ISTS_reserved28_MASK             (0x10000000U)
#define USB3_EP_ISTS_reserved28_SHIFT            (28U)
#define USB3_EP_ISTS_reserved28(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved28_SHIFT)) & USB3_EP_ISTS_reserved28_MASK)
#define USB3_EP_ISTS_reserved29_MASK             (0x20000000U)
#define USB3_EP_ISTS_reserved29_SHIFT            (29U)
#define USB3_EP_ISTS_reserved29(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved29_SHIFT)) & USB3_EP_ISTS_reserved29_MASK)
#define USB3_EP_ISTS_reserved30_MASK             (0x40000000U)
#define USB3_EP_ISTS_reserved30_SHIFT            (30U)
#define USB3_EP_ISTS_reserved30(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved30_SHIFT)) & USB3_EP_ISTS_reserved30_MASK)
#define USB3_EP_ISTS_reserved31_MASK             (0x80000000U)
#define USB3_EP_ISTS_reserved31_SHIFT            (31U)
#define USB3_EP_ISTS_reserved31(x)               (((uint32_t)(((uint32_t)(x)) << USB3_EP_ISTS_reserved31_SHIFT)) & USB3_EP_ISTS_reserved31_MASK)
/*! @} */

/*! @name USB_PWR - Global power configuration */
/*! @{ */
#define USB3_USB_PWR_PSO_EN_MASK                 (0x1U)
#define USB3_USB_PWR_PSO_EN_SHIFT                (0U)
#define USB3_USB_PWR_PSO_EN(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_PSO_EN_SHIFT)) & USB3_USB_PWR_PSO_EN_MASK)
#define USB3_USB_PWR_PSO_DS_MASK                 (0x2U)
#define USB3_USB_PWR_PSO_DS_SHIFT                (1U)
#define USB3_USB_PWR_PSO_DS(x)                   (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_PSO_DS_SHIFT)) & USB3_USB_PWR_PSO_DS_MASK)
#define USB3_USB_PWR_RESERVED0_MASK              (0xFCU)
#define USB3_USB_PWR_RESERVED0_SHIFT             (2U)
#define USB3_USB_PWR_RESERVED0(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_RESERVED0_SHIFT)) & USB3_USB_PWR_RESERVED0_MASK)
#define USB3_USB_PWR_STB_CLK_SWITCH_EN_MASK      (0x100U)
#define USB3_USB_PWR_STB_CLK_SWITCH_EN_SHIFT     (8U)
#define USB3_USB_PWR_STB_CLK_SWITCH_EN(x)        (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_STB_CLK_SWITCH_EN_SHIFT)) & USB3_USB_PWR_STB_CLK_SWITCH_EN_MASK)
#define USB3_USB_PWR_STB_CLK_SWITCH_DONE_MASK    (0x200U)
#define USB3_USB_PWR_STB_CLK_SWITCH_DONE_SHIFT   (9U)
#define USB3_USB_PWR_STB_CLK_SWITCH_DONE(x)      (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_STB_CLK_SWITCH_DONE_SHIFT)) & USB3_USB_PWR_STB_CLK_SWITCH_DONE_MASK)
#define USB3_USB_PWR_RESERVED1_MASK              (0x3FFFFC00U)
#define USB3_USB_PWR_RESERVED1_SHIFT             (10U)
#define USB3_USB_PWR_RESERVED1(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_RESERVED1_SHIFT)) & USB3_USB_PWR_RESERVED1_MASK)
#define USB3_USB_PWR_FAST_REG_ACCESS_STAT_MASK   (0x40000000U)
#define USB3_USB_PWR_FAST_REG_ACCESS_STAT_SHIFT  (30U)
#define USB3_USB_PWR_FAST_REG_ACCESS_STAT(x)     (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_FAST_REG_ACCESS_STAT_SHIFT)) & USB3_USB_PWR_FAST_REG_ACCESS_STAT_MASK)
#define USB3_USB_PWR_FAST_REG_ACCESS_MASK        (0x80000000U)
#define USB3_USB_PWR_FAST_REG_ACCESS_SHIFT       (31U)
#define USB3_USB_PWR_FAST_REG_ACCESS(x)          (((uint32_t)(((uint32_t)(x)) << USB3_USB_PWR_FAST_REG_ACCESS_SHIFT)) & USB3_USB_PWR_FAST_REG_ACCESS_MASK)
/*! @} */

/*! @name USB_CONF2 - USB configuration */
/*! @{ */
#define USB3_USB_CONF2_AHB_RETRY_EN_MASK         (0x1U)
#define USB3_USB_CONF2_AHB_RETRY_EN_SHIFT        (0U)
#define USB3_USB_CONF2_AHB_RETRY_EN(x)           (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF2_AHB_RETRY_EN_SHIFT)) & USB3_USB_CONF2_AHB_RETRY_EN_MASK)
#define USB3_USB_CONF2_RESERVED_MASK             (0xFFFFFFFEU)
#define USB3_USB_CONF2_RESERVED_SHIFT            (1U)
#define USB3_USB_CONF2_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CONF2_RESERVED_SHIFT)) & USB3_USB_CONF2_RESERVED_MASK)
/*! @} */

/*! @name USB_CAP1 - USB Capability */
/*! @{ */
#define USB3_USB_CAP1_SFR_TYPE_MASK              (0xFU)
#define USB3_USB_CAP1_SFR_TYPE_SHIFT             (0U)
#define USB3_USB_CAP1_SFR_TYPE(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_SFR_TYPE_SHIFT)) & USB3_USB_CAP1_SFR_TYPE_MASK)
#define USB3_USB_CAP1_SFR_WIDTH_MASK             (0xF0U)
#define USB3_USB_CAP1_SFR_WIDTH_SHIFT            (4U)
#define USB3_USB_CAP1_SFR_WIDTH(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_SFR_WIDTH_SHIFT)) & USB3_USB_CAP1_SFR_WIDTH_MASK)
#define USB3_USB_CAP1_DMA_TYPE_MASK              (0xF00U)
#define USB3_USB_CAP1_DMA_TYPE_SHIFT             (8U)
#define USB3_USB_CAP1_DMA_TYPE(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_DMA_TYPE_SHIFT)) & USB3_USB_CAP1_DMA_TYPE_MASK)
#define USB3_USB_CAP1_DMA_WIDTH_MASK             (0xF000U)
#define USB3_USB_CAP1_DMA_WIDTH_SHIFT            (12U)
#define USB3_USB_CAP1_DMA_WIDTH(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_DMA_WIDTH_SHIFT)) & USB3_USB_CAP1_DMA_WIDTH_MASK)
#define USB3_USB_CAP1_U3PHY_TYPE_MASK            (0xF0000U)
#define USB3_USB_CAP1_U3PHY_TYPE_SHIFT           (16U)
#define USB3_USB_CAP1_U3PHY_TYPE(x)              (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U3PHY_TYPE_SHIFT)) & USB3_USB_CAP1_U3PHY_TYPE_MASK)
#define USB3_USB_CAP1_U3PHY_WIDTH_MASK           (0xF00000U)
#define USB3_USB_CAP1_U3PHY_WIDTH_SHIFT          (20U)
#define USB3_USB_CAP1_U3PHY_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U3PHY_WIDTH_SHIFT)) & USB3_USB_CAP1_U3PHY_WIDTH_MASK)
#define USB3_USB_CAP1_U2PHY_EN_MASK              (0x1000000U)
#define USB3_USB_CAP1_U2PHY_EN_SHIFT             (24U)
#define USB3_USB_CAP1_U2PHY_EN(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U2PHY_EN_SHIFT)) & USB3_USB_CAP1_U2PHY_EN_MASK)
#define USB3_USB_CAP1_U2PHY_TYPE_MASK            (0x2000000U)
#define USB3_USB_CAP1_U2PHY_TYPE_SHIFT           (25U)
#define USB3_USB_CAP1_U2PHY_TYPE(x)              (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U2PHY_TYPE_SHIFT)) & USB3_USB_CAP1_U2PHY_TYPE_MASK)
#define USB3_USB_CAP1_U2PHY_WIDTH_MASK           (0x4000000U)
#define USB3_USB_CAP1_U2PHY_WIDTH_SHIFT          (26U)
#define USB3_USB_CAP1_U2PHY_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_U2PHY_WIDTH_SHIFT)) & USB3_USB_CAP1_U2PHY_WIDTH_MASK)
#define USB3_USB_CAP1_OTG_READY_MASK             (0x8000000U)
#define USB3_USB_CAP1_OTG_READY_SHIFT            (27U)
#define USB3_USB_CAP1_OTG_READY(x)               (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_OTG_READY_SHIFT)) & USB3_USB_CAP1_OTG_READY_MASK)
#define USB3_USB_CAP1_RESERVED_MASK              (0xF0000000U)
#define USB3_USB_CAP1_RESERVED_SHIFT             (28U)
#define USB3_USB_CAP1_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP1_RESERVED_SHIFT)) & USB3_USB_CAP1_RESERVED_MASK)
/*! @} */

/*! @name USB_CAP2 - USB Capability */
/*! @{ */
#define USB3_USB_CAP2_ACTUAL_MEM_SIZE_MASK       (0xFFU)
#define USB3_USB_CAP2_ACTUAL_MEM_SIZE_SHIFT      (0U)
#define USB3_USB_CAP2_ACTUAL_MEM_SIZE(x)         (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP2_ACTUAL_MEM_SIZE_SHIFT)) & USB3_USB_CAP2_ACTUAL_MEM_SIZE_MASK)
#define USB3_USB_CAP2_MAX_MEM_SIZE_MASK          (0x1F00U)
#define USB3_USB_CAP2_MAX_MEM_SIZE_SHIFT         (8U)
#define USB3_USB_CAP2_MAX_MEM_SIZE(x)            (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP2_MAX_MEM_SIZE_SHIFT)) & USB3_USB_CAP2_MAX_MEM_SIZE_MASK)
#define USB3_USB_CAP2_RESERVED_MASK              (0xFFFFE000U)
#define USB3_USB_CAP2_RESERVED_SHIFT             (13U)
#define USB3_USB_CAP2_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP2_RESERVED_SHIFT)) & USB3_USB_CAP2_RESERVED_MASK)
/*! @} */

/*! @name USB_CAP3 - USB Capability */
/*! @{ */
#define USB3_USB_CAP3_EPOUT_N_MASK               (0xFFFFU)
#define USB3_USB_CAP3_EPOUT_N_SHIFT              (0U)
#define USB3_USB_CAP3_EPOUT_N(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP3_EPOUT_N_SHIFT)) & USB3_USB_CAP3_EPOUT_N_MASK)
#define USB3_USB_CAP3_EPIN_N_MASK                (0xFFFF0000U)
#define USB3_USB_CAP3_EPIN_N_SHIFT               (16U)
#define USB3_USB_CAP3_EPIN_N(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP3_EPIN_N_SHIFT)) & USB3_USB_CAP3_EPIN_N_MASK)
/*! @} */

/*! @name USB_CAP4 - ISO HW support */
/*! @{ */
#define USB3_USB_CAP4_EPOUTI_N_MASK              (0xFFFFU)
#define USB3_USB_CAP4_EPOUTI_N_SHIFT             (0U)
#define USB3_USB_CAP4_EPOUTI_N(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP4_EPOUTI_N_SHIFT)) & USB3_USB_CAP4_EPOUTI_N_MASK)
#define USB3_USB_CAP4_EPINI_N_MASK               (0xFFFF0000U)
#define USB3_USB_CAP4_EPINI_N_SHIFT              (16U)
#define USB3_USB_CAP4_EPINI_N(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP4_EPINI_N_SHIFT)) & USB3_USB_CAP4_EPINI_N_MASK)
/*! @} */

/*! @name USB_CAP5 - Bulk Stream HW */
/*! @{ */
#define USB3_USB_CAP5_EPOUTI_N_MASK              (0xFFFFU)
#define USB3_USB_CAP5_EPOUTI_N_SHIFT             (0U)
#define USB3_USB_CAP5_EPOUTI_N(x)                (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP5_EPOUTI_N_SHIFT)) & USB3_USB_CAP5_EPOUTI_N_MASK)
#define USB3_USB_CAP5_EPINI_N_MASK               (0xFFFF0000U)
#define USB3_USB_CAP5_EPINI_N_SHIFT              (16U)
#define USB3_USB_CAP5_EPINI_N(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP5_EPINI_N_SHIFT)) & USB3_USB_CAP5_EPINI_N_MASK)
/*! @} */

/*! @name USB_CAP6 - Device controller version */
/*! @{ */
#define USB3_USB_CAP6_VERSION_MASK               (0xFFFFFFFFU)
#define USB3_USB_CAP6_VERSION_SHIFT              (0U)
#define USB3_USB_CAP6_VERSION(x)                 (((uint32_t)(((uint32_t)(x)) << USB3_USB_CAP6_VERSION_SHIFT)) & USB3_USB_CAP6_VERSION_MASK)
/*! @} */

/*! @name USB_CPKT1 - Custom Packet value */
/*! @{ */
#define USB3_USB_CPKT1_CPKT1_MASK                (0xFFFFFFFFU)
#define USB3_USB_CPKT1_CPKT1_SHIFT               (0U)
#define USB3_USB_CPKT1_CPKT1(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CPKT1_CPKT1_SHIFT)) & USB3_USB_CPKT1_CPKT1_MASK)
/*! @} */

/*! @name USB_CPKT2 - Custom Packet value */
/*! @{ */
#define USB3_USB_CPKT2_CPKT2_MASK                (0xFFFFFFFFU)
#define USB3_USB_CPKT2_CPKT2_SHIFT               (0U)
#define USB3_USB_CPKT2_CPKT2(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CPKT2_CPKT2_SHIFT)) & USB3_USB_CPKT2_CPKT2_MASK)
/*! @} */

/*! @name USB_CPKT3 - Custom Packet value */
/*! @{ */
#define USB3_USB_CPKT3_CPKT3_MASK                (0xFFFFFFFFU)
#define USB3_USB_CPKT3_CPKT3_SHIFT               (0U)
#define USB3_USB_CPKT3_CPKT3(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_USB_CPKT3_CPKT3_SHIFT)) & USB3_USB_CPKT3_CPKT3_MASK)
/*! @} */

/*! @name CFG_REG1 - VBUS debouncer Configuration */
/*! @{ */
#define USB3_CFG_REG1_DEBOUNCER_CNT_MASK         (0x3FFFFU)
#define USB3_CFG_REG1_DEBOUNCER_CNT_SHIFT        (0U)
#define USB3_CFG_REG1_DEBOUNCER_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG1_DEBOUNCER_CNT_SHIFT)) & USB3_CFG_REG1_DEBOUNCER_CNT_MASK)
#define USB3_CFG_REG1_RESERVED_MASK              (0xFFFC0000U)
#define USB3_CFG_REG1_RESERVED_SHIFT             (18U)
#define USB3_CFG_REG1_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG1_RESERVED_SHIFT)) & USB3_CFG_REG1_RESERVED_MASK)
/*! @} */

/*! @name DBG_LINK1 - Link */
/*! @{ */
#define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_MASK (0xFFU)
#define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SHIFT (0U)
#define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT(x)   (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SHIFT)) & USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_MASK)
#define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK (0xFF00U)
#define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SHIFT (8U)
#define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(x)   (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SHIFT)) & USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK)
#define USB3_DBG_LINK1_RXDET_BREAK_DIS_MASK      (0x10000U)
#define USB3_DBG_LINK1_RXDET_BREAK_DIS_SHIFT     (16U)
#define USB3_DBG_LINK1_RXDET_BREAK_DIS(x)        (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_RXDET_BREAK_DIS_SHIFT)) & USB3_DBG_LINK1_RXDET_BREAK_DIS_MASK)
#define USB3_DBG_LINK1_LFPS_GEN_PING_MASK        (0x3E0000U)
#define USB3_DBG_LINK1_LFPS_GEN_PING_SHIFT       (17U)
#define USB3_DBG_LINK1_LFPS_GEN_PING(x)          (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_GEN_PING_SHIFT)) & USB3_DBG_LINK1_LFPS_GEN_PING_MASK)
#define USB3_DBG_LINK1_RESERVED0_MASK            (0xC00000U)
#define USB3_DBG_LINK1_RESERVED0_SHIFT           (22U)
#define USB3_DBG_LINK1_RESERVED0(x)              (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_RESERVED0_SHIFT)) & USB3_DBG_LINK1_RESERVED0_MASK)
#define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET_MASK (0x1000000U)
#define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET_SHIFT (24U)
#define USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET_SHIFT)) & USB3_DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET_MASK)
#define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET_MASK (0x2000000U)
#define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET_SHIFT (25U)
#define USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET(x) (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET_SHIFT)) & USB3_DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET_MASK)
#define USB3_DBG_LINK1_RXDET_BREAK_DIS_SET_MASK  (0x4000000U)
#define USB3_DBG_LINK1_RXDET_BREAK_DIS_SET_SHIFT (26U)
#define USB3_DBG_LINK1_RXDET_BREAK_DIS_SET(x)    (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_RXDET_BREAK_DIS_SET_SHIFT)) & USB3_DBG_LINK1_RXDET_BREAK_DIS_SET_MASK)
#define USB3_DBG_LINK1_LFPS_GEN_PING_SET_MASK    (0x8000000U)
#define USB3_DBG_LINK1_LFPS_GEN_PING_SET_SHIFT   (27U)
#define USB3_DBG_LINK1_LFPS_GEN_PING_SET(x)      (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_LFPS_GEN_PING_SET_SHIFT)) & USB3_DBG_LINK1_LFPS_GEN_PING_SET_MASK)
#define USB3_DBG_LINK1_RESERVED1_MASK            (0xF0000000U)
#define USB3_DBG_LINK1_RESERVED1_SHIFT           (28U)
#define USB3_DBG_LINK1_RESERVED1(x)              (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK1_RESERVED1_SHIFT)) & USB3_DBG_LINK1_RESERVED1_MASK)
/*! @} */

/*! @name DBG_LINK2 - Link */
/*! @{ */
#define USB3_DBG_LINK2_RXEQTR_AVAL_MASK          (0xFFU)
#define USB3_DBG_LINK2_RXEQTR_AVAL_SHIFT         (0U)
#define USB3_DBG_LINK2_RXEQTR_AVAL(x)            (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RXEQTR_AVAL_SHIFT)) & USB3_DBG_LINK2_RXEQTR_AVAL_MASK)
#define USB3_DBG_LINK2_RXEQTR_DVAL_MASK          (0xFF00U)
#define USB3_DBG_LINK2_RXEQTR_DVAL_SHIFT         (8U)
#define USB3_DBG_LINK2_RXEQTR_DVAL(x)            (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RXEQTR_DVAL_SHIFT)) & USB3_DBG_LINK2_RXEQTR_DVAL_MASK)
#define USB3_DBG_LINK2_PHYRXVAL_DVAL_MASK        (0xFF0000U)
#define USB3_DBG_LINK2_PHYRXVAL_DVAL_SHIFT       (16U)
#define USB3_DBG_LINK2_PHYRXVAL_DVAL(x)          (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_PHYRXVAL_DVAL_SHIFT)) & USB3_DBG_LINK2_PHYRXVAL_DVAL_MASK)
#define USB3_DBG_LINK2_TXDET_DVAL_MASK           (0x7000000U)
#define USB3_DBG_LINK2_TXDET_DVAL_SHIFT          (24U)
#define USB3_DBG_LINK2_TXDET_DVAL(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_TXDET_DVAL_SHIFT)) & USB3_DBG_LINK2_TXDET_DVAL_MASK)
#define USB3_DBG_LINK2_RESERVED_MASK             (0x8000000U)
#define USB3_DBG_LINK2_RESERVED_SHIFT            (27U)
#define USB3_DBG_LINK2_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RESERVED_SHIFT)) & USB3_DBG_LINK2_RESERVED_MASK)
#define USB3_DBG_LINK2_RXEQTR_AVAL_SET_MASK      (0x10000000U)
#define USB3_DBG_LINK2_RXEQTR_AVAL_SET_SHIFT     (28U)
#define USB3_DBG_LINK2_RXEQTR_AVAL_SET(x)        (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RXEQTR_AVAL_SET_SHIFT)) & USB3_DBG_LINK2_RXEQTR_AVAL_SET_MASK)
#define USB3_DBG_LINK2_RXEQTR_DVAL_SET_MASK      (0x20000000U)
#define USB3_DBG_LINK2_RXEQTR_DVAL_SET_SHIFT     (29U)
#define USB3_DBG_LINK2_RXEQTR_DVAL_SET(x)        (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_RXEQTR_DVAL_SET_SHIFT)) & USB3_DBG_LINK2_RXEQTR_DVAL_SET_MASK)
#define USB3_DBG_LINK2_PHYRXVAL_DVAL_SET_MASK    (0x40000000U)
#define USB3_DBG_LINK2_PHYRXVAL_DVAL_SET_SHIFT   (30U)
#define USB3_DBG_LINK2_PHYRXVAL_DVAL_SET(x)      (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_PHYRXVAL_DVAL_SET_SHIFT)) & USB3_DBG_LINK2_PHYRXVAL_DVAL_SET_MASK)
#define USB3_DBG_LINK2_TXDET_DVAL_SET_MASK       (0x80000000U)
#define USB3_DBG_LINK2_TXDET_DVAL_SET_SHIFT      (31U)
#define USB3_DBG_LINK2_TXDET_DVAL_SET(x)         (((uint32_t)(((uint32_t)(x)) << USB3_DBG_LINK2_TXDET_DVAL_SET_SHIFT)) & USB3_DBG_LINK2_TXDET_DVAL_SET_MASK)
/*! @} */

/*! @name CFG_REG4 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_MASK (0xFFU)
#define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_SHIFT (0U)
#define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_SHIFT)) & USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_MASK)
#define USB3_CFG_REG4_RESERVED_MASK              (0x3FFFFF00U)
#define USB3_CFG_REG4_RESERVED_SHIFT             (8U)
#define USB3_CFG_REG4_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG4_RESERVED_SHIFT)) & USB3_CFG_REG4_RESERVED_MASK)
#define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG4_RXDETECT_QUIET_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG5 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_MASK  (0x7FFU)
#define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_SHIFT (0U)
#define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_SHIFT)) & USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_MASK)
#define USB3_CFG_REG5_RESERVED_MASK              (0x3FFFF800U)
#define USB3_CFG_REG5_RESERVED_SHIFT             (11U)
#define USB3_CFG_REG5_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG5_RESERVED_SHIFT)) & USB3_CFG_REG5_RESERVED_MASK)
#define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG5_U3_HDSK_FAIL_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG6 - Configuration Register 6 */
/*! @{ */
#define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_MASK (0xFFU)
#define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_SHIFT (0U)
#define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_SHIFT)) & USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_MASK)
#define USB3_CFG_REG6_RESERVED_MASK              (0x3FFFFF00U)
#define USB3_CFG_REG6_RESERVED_SHIFT             (8U)
#define USB3_CFG_REG6_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG6_RESERVED_SHIFT)) & USB3_CFG_REG6_RESERVED_MASK)
#define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG6_SSINACTIVE_QUIET_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG7 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_MASK  (0x1FFFU)
#define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_SHIFT (0U)
#define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_SHIFT)) & USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_MASK)
#define USB3_CFG_REG7_RESERVED_MASK              (0x3FFFE000U)
#define USB3_CFG_REG7_RESERVED_SHIFT             (13U)
#define USB3_CFG_REG7_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG7_RESERVED_SHIFT)) & USB3_CFG_REG7_RESERVED_MASK)
#define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG7_POLLING_LFPS_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG8 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_MASK (0x3FFU)
#define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_SHIFT (0U)
#define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_SHIFT)) & USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_MASK)
#define USB3_CFG_REG8_RESERVED_MASK              (0x3FFFFC00U)
#define USB3_CFG_REG8_RESERVED_SHIFT             (10U)
#define USB3_CFG_REG8_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG8_RESERVED_SHIFT)) & USB3_CFG_REG8_RESERVED_MASK)
#define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG8_POLLING_ACTIVE_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG9 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_MASK  (0x1FU)
#define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_SHIFT (0U)
#define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_SHIFT)) & USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_MASK)
#define USB3_CFG_REG9_RESERVED_MASK              (0x3FFFFFE0U)
#define USB3_CFG_REG9_RESERVED_SHIFT             (5U)
#define USB3_CFG_REG9_RESERVED(x)                (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG9_RESERVED_SHIFT)) & USB3_CFG_REG9_RESERVED_MASK)
#define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG9_POLLING_IDLE_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG10 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_MASK (0xFFU)
#define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_SHIFT (0U)
#define USB3_CFG_REG10_POLLING_CONF_TIMEOUT(x)   (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG10_POLLING_CONF_TIMEOUT_SHIFT)) & USB3_CFG_REG10_POLLING_CONF_TIMEOUT_MASK)
#define USB3_CFG_REG10_RESERVED_MASK             (0x3FFFFF00U)
#define USB3_CFG_REG10_RESERVED_SHIFT            (8U)
#define USB3_CFG_REG10_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG10_RESERVED_SHIFT)) & USB3_CFG_REG10_RESERVED_MASK)
#define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG10_POLLING_CONF_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG11 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_MASK (0xFFU)
#define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_SHIFT (0U)
#define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_SHIFT)) & USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_MASK)
#define USB3_CFG_REG11_RESERVED_MASK             (0x3FFFFF00U)
#define USB3_CFG_REG11_RESERVED_SHIFT            (8U)
#define USB3_CFG_REG11_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG11_RESERVED_SHIFT)) & USB3_CFG_REG11_RESERVED_MASK)
#define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG11_RECOVERY_ACTIVE_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG12 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_MASK (0xFFU)
#define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_SHIFT (0U)
#define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_SHIFT)) & USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_MASK)
#define USB3_CFG_REG12_RESERVED_MASK             (0x3FFFFF00U)
#define USB3_CFG_REG12_RESERVED_SHIFT            (8U)
#define USB3_CFG_REG12_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG12_RESERVED_SHIFT)) & USB3_CFG_REG12_RESERVED_MASK)
#define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG12_RECOVERY_CONF_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG13 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_MASK (0x1FU)
#define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_SHIFT (0U)
#define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_SHIFT)) & USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_MASK)
#define USB3_CFG_REG13_RESERVED_MASK             (0xFFFFFE0U)
#define USB3_CFG_REG13_RESERVED_SHIFT            (5U)
#define USB3_CFG_REG13_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG13_RESERVED_SHIFT)) & USB3_CFG_REG13_RESERVED_MASK)
#define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG13_RECOVERY_IDLE_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG14 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_MASK (0xFFU)
#define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_SHIFT (0U)
#define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_SHIFT)) & USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_MASK)
#define USB3_CFG_REG14_RESERVED_MASK             (0x3FFFFF00U)
#define USB3_CFG_REG14_RESERVED_SHIFT            (8U)
#define USB3_CFG_REG14_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG14_RESERVED_SHIFT)) & USB3_CFG_REG14_RESERVED_MASK)
#define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG14_HOTRESET_ACTIVE_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG15 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_MASK (0x1FU)
#define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_SHIFT (0U)
#define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT(x)  (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_SHIFT)) & USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_MASK)
#define USB3_CFG_REG15_RESERVED_MASK             (0x3FFFFFE0U)
#define USB3_CFG_REG15_RESERVED_SHIFT            (5U)
#define USB3_CFG_REG15_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG15_RESERVED_SHIFT)) & USB3_CFG_REG15_RESERVED_MASK)
#define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG15_HOTRESET_EXIT_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG16 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG16_LFPS_PING_REPEAT_MASK     (0xFFFU)
#define USB3_CFG_REG16_LFPS_PING_REPEAT_SHIFT    (0U)
#define USB3_CFG_REG16_LFPS_PING_REPEAT(x)       (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG16_LFPS_PING_REPEAT_SHIFT)) & USB3_CFG_REG16_LFPS_PING_REPEAT_MASK)
#define USB3_CFG_REG16_RESERVED_MASK             (0x3FFFF000U)
#define USB3_CFG_REG16_RESERVED_SHIFT            (12U)
#define USB3_CFG_REG16_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG16_RESERVED_SHIFT)) & USB3_CFG_REG16_RESERVED_MASK)
#define USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE_SHIFT)) & USB3_CFG_REG16_LFPS_PING_REPEAT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG17 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG17_PENDING_HP_TIMEOUT_MASK   (0x3FFU)
#define USB3_CFG_REG17_PENDING_HP_TIMEOUT_SHIFT  (0U)
#define USB3_CFG_REG17_PENDING_HP_TIMEOUT(x)     (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG17_PENDING_HP_TIMEOUT_SHIFT)) & USB3_CFG_REG17_PENDING_HP_TIMEOUT_MASK)
#define USB3_CFG_REG17_RESERVED_MASK             (0x3FFFFC00U)
#define USB3_CFG_REG17_RESERVED_SHIFT            (10U)
#define USB3_CFG_REG17_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG17_RESERVED_SHIFT)) & USB3_CFG_REG17_RESERVED_MASK)
#define USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG17_PENDING_HP_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG18 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_MASK    (0x7FU)
#define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_SHIFT   (0U)
#define USB3_CFG_REG18_CREDIT_HP_TIMEOUT(x)      (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG18_CREDIT_HP_TIMEOUT_SHIFT)) & USB3_CFG_REG18_CREDIT_HP_TIMEOUT_MASK)
#define USB3_CFG_REG18_RESERVED_MASK             (0x3FFFFF80U)
#define USB3_CFG_REG18_RESERVED_SHIFT            (7U)
#define USB3_CFG_REG18_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG18_RESERVED_SHIFT)) & USB3_CFG_REG18_RESERVED_MASK)
#define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG18_CREDIT_HP_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG19 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG19_LUP_TIMEOUT_MASK          (0x3FFU)
#define USB3_CFG_REG19_LUP_TIMEOUT_SHIFT         (0U)
#define USB3_CFG_REG19_LUP_TIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG19_LUP_TIMEOUT_SHIFT)) & USB3_CFG_REG19_LUP_TIMEOUT_MASK)
#define USB3_CFG_REG19_RESERVED_MASK             (0x3FFFFC00U)
#define USB3_CFG_REG19_RESERVED_SHIFT            (10U)
#define USB3_CFG_REG19_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG19_RESERVED_SHIFT)) & USB3_CFG_REG19_RESERVED_MASK)
#define USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE(x)   (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG19_LUP_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG20 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG20_LDN_TIMEOUT_MASK          (0xFFU)
#define USB3_CFG_REG20_LDN_TIMEOUT_SHIFT         (0U)
#define USB3_CFG_REG20_LDN_TIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG20_LDN_TIMEOUT_SHIFT)) & USB3_CFG_REG20_LDN_TIMEOUT_MASK)
#define USB3_CFG_REG20_RESERVED_MASK             (0x3FFFFF00U)
#define USB3_CFG_REG20_RESERVED_SHIFT            (8U)
#define USB3_CFG_REG20_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG20_RESERVED_SHIFT)) & USB3_CFG_REG20_RESERVED_MASK)
#define USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE(x)   (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG20_LDN_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG21 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG21_PM_LC_TIMEOUT_MASK        (0x3FFU)
#define USB3_CFG_REG21_PM_LC_TIMEOUT_SHIFT       (0U)
#define USB3_CFG_REG21_PM_LC_TIMEOUT(x)          (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG21_PM_LC_TIMEOUT_SHIFT)) & USB3_CFG_REG21_PM_LC_TIMEOUT_MASK)
#define USB3_CFG_REG21_RESERVED_MASK             (0x3FFFFC00U)
#define USB3_CFG_REG21_RESERVED_SHIFT            (10U)
#define USB3_CFG_REG21_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG21_RESERVED_SHIFT)) & USB3_CFG_REG21_RESERVED_MASK)
#define USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG21_PM_LC_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG22 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_MASK     (0x7FFU)
#define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_SHIFT    (0U)
#define USB3_CFG_REG22_PM_ENTRY_TIMEOUT(x)       (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG22_PM_ENTRY_TIMEOUT_SHIFT)) & USB3_CFG_REG22_PM_ENTRY_TIMEOUT_MASK)
#define USB3_CFG_REG22_RESERVED_MASK             (0x3FFFF800U)
#define USB3_CFG_REG22_RESERVED_SHIFT            (11U)
#define USB3_CFG_REG22_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG22_RESERVED_SHIFT)) & USB3_CFG_REG22_RESERVED_MASK)
#define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG22_PM_ENTRY_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG23 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG23_UX_EXIT_TIMEOUT_MASK      (0x7FU)
#define USB3_CFG_REG23_UX_EXIT_TIMEOUT_SHIFT     (0U)
#define USB3_CFG_REG23_UX_EXIT_TIMEOUT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG23_UX_EXIT_TIMEOUT_SHIFT)) & USB3_CFG_REG23_UX_EXIT_TIMEOUT_MASK)
#define USB3_CFG_REG23_RESERVED_MASK             (0x3FFFFF80U)
#define USB3_CFG_REG23_RESERVED_SHIFT            (7U)
#define USB3_CFG_REG23_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG23_RESERVED_SHIFT)) & USB3_CFG_REG23_RESERVED_MASK)
#define USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG23_UX_EXIT_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG24 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG24_LFPS_DET_RESET_MIN_MASK   (0x7FFFFFU)
#define USB3_CFG_REG24_LFPS_DET_RESET_MIN_SHIFT  (0U)
#define USB3_CFG_REG24_LFPS_DET_RESET_MIN(x)     (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG24_LFPS_DET_RESET_MIN_SHIFT)) & USB3_CFG_REG24_LFPS_DET_RESET_MIN_MASK)
#define USB3_CFG_REG24_RESERVED_MASK             (0xFF800000U)
#define USB3_CFG_REG24_RESERVED_SHIFT            (23U)
#define USB3_CFG_REG24_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG24_RESERVED_SHIFT)) & USB3_CFG_REG24_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG25 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG25_LFPS_DET_RESET_MAX_MASK   (0xFFFFFFU)
#define USB3_CFG_REG25_LFPS_DET_RESET_MAX_SHIFT  (0U)
#define USB3_CFG_REG25_LFPS_DET_RESET_MAX(x)     (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG25_LFPS_DET_RESET_MAX_SHIFT)) & USB3_CFG_REG25_LFPS_DET_RESET_MAX_MASK)
#define USB3_CFG_REG25_RESERVED_MASK             (0xFF000000U)
#define USB3_CFG_REG25_RESERVED_SHIFT            (24U)
#define USB3_CFG_REG25_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG25_RESERVED_SHIFT)) & USB3_CFG_REG25_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG26 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG26_LFPS_DET_POLLING_MIN_MASK (0x7FU)
#define USB3_CFG_REG26_LFPS_DET_POLLING_MIN_SHIFT (0U)
#define USB3_CFG_REG26_LFPS_DET_POLLING_MIN(x)   (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG26_LFPS_DET_POLLING_MIN_SHIFT)) & USB3_CFG_REG26_LFPS_DET_POLLING_MIN_MASK)
#define USB3_CFG_REG26_RESERVED_MASK             (0xFFFFFF80U)
#define USB3_CFG_REG26_RESERVED_SHIFT            (7U)
#define USB3_CFG_REG26_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG26_RESERVED_SHIFT)) & USB3_CFG_REG26_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG27 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG27_LFPS_DET_POLLING_MAX_MASK (0xFFU)
#define USB3_CFG_REG27_LFPS_DET_POLLING_MAX_SHIFT (0U)
#define USB3_CFG_REG27_LFPS_DET_POLLING_MAX(x)   (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG27_LFPS_DET_POLLING_MAX_SHIFT)) & USB3_CFG_REG27_LFPS_DET_POLLING_MAX_MASK)
#define USB3_CFG_REG27_RESERVED_MASK             (0xFFFFFF00U)
#define USB3_CFG_REG27_RESERVED_SHIFT            (8U)
#define USB3_CFG_REG27_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG27_RESERVED_SHIFT)) & USB3_CFG_REG27_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG28 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG28_LFPS_DET_PING_MIN_MASK    (0x7U)
#define USB3_CFG_REG28_LFPS_DET_PING_MIN_SHIFT   (0U)
#define USB3_CFG_REG28_LFPS_DET_PING_MIN(x)      (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG28_LFPS_DET_PING_MIN_SHIFT)) & USB3_CFG_REG28_LFPS_DET_PING_MIN_MASK)
#define USB3_CFG_REG28_RESERVED_MASK             (0xFFFFFFF8U)
#define USB3_CFG_REG28_RESERVED_SHIFT            (3U)
#define USB3_CFG_REG28_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG28_RESERVED_SHIFT)) & USB3_CFG_REG28_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG29 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG29_LFPS_DET_PING_MAX_MASK    (0x1FU)
#define USB3_CFG_REG29_LFPS_DET_PING_MAX_SHIFT   (0U)
#define USB3_CFG_REG29_LFPS_DET_PING_MAX(x)      (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG29_LFPS_DET_PING_MAX_SHIFT)) & USB3_CFG_REG29_LFPS_DET_PING_MAX_MASK)
#define USB3_CFG_REG29_RESERVED_MASK             (0xFFFFFFE0U)
#define USB3_CFG_REG29_RESERVED_SHIFT            (5U)
#define USB3_CFG_REG29_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG29_RESERVED_SHIFT)) & USB3_CFG_REG29_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG30 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN_MASK  (0x3FU)
#define USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN_SHIFT (0U)
#define USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN_SHIFT)) & USB3_CFG_REG30_LFPS_DET_U1EXIT_MIN_MASK)
#define USB3_CFG_REG30_RESERVED_MASK             (0xFFFFFFC0U)
#define USB3_CFG_REG30_RESERVED_SHIFT            (6U)
#define USB3_CFG_REG30_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG30_RESERVED_SHIFT)) & USB3_CFG_REG30_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG31 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX_MASK  (0x7FU)
#define USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX_SHIFT (0U)
#define USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX_SHIFT)) & USB3_CFG_REG31_LFPS_DET_U1EXIT_MAX_MASK)
#define USB3_CFG_REG31_RESERVED_MASK             (0xFFFFFF80U)
#define USB3_CFG_REG31_RESERVED_SHIFT            (7U)
#define USB3_CFG_REG31_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG31_RESERVED_SHIFT)) & USB3_CFG_REG31_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG32 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN_MASK  (0x3FU)
#define USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN_SHIFT (0U)
#define USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN_SHIFT)) & USB3_CFG_REG32_LFPS_DET_U2EXIT_MIN_MASK)
#define USB3_CFG_REG32_RESERVED_MASK             (0xFFFFFFC0U)
#define USB3_CFG_REG32_RESERVED_SHIFT            (6U)
#define USB3_CFG_REG32_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG32_RESERVED_SHIFT)) & USB3_CFG_REG32_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG33 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX_MASK  (0x3FFFFU)
#define USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX_SHIFT (0U)
#define USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX_SHIFT)) & USB3_CFG_REG33_LFPS_DET_U2EXIT_MAX_MASK)
#define USB3_CFG_REG33_RESERVED_MASK             (0xFFFC0000U)
#define USB3_CFG_REG33_RESERVED_SHIFT            (18U)
#define USB3_CFG_REG33_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG33_RESERVED_SHIFT)) & USB3_CFG_REG33_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG34 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN_MASK  (0x3FU)
#define USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN_SHIFT (0U)
#define USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN_SHIFT)) & USB3_CFG_REG34_LFPS_DET_U3EXIT_MIN_MASK)
#define USB3_CFG_REG34_RESERVED_MASK             (0xFFFFFFC0U)
#define USB3_CFG_REG34_RESERVED_SHIFT            (6U)
#define USB3_CFG_REG34_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG34_RESERVED_SHIFT)) & USB3_CFG_REG34_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG35 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX_MASK  (0x1FFFFFU)
#define USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX_SHIFT (0U)
#define USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX_SHIFT)) & USB3_CFG_REG35_LFPS_DET_U3EXIT_MAX_MASK)
#define USB3_CFG_REG35_RESERVED_MASK             (0xFFE00000U)
#define USB3_CFG_REG35_RESERVED_SHIFT            (21U)
#define USB3_CFG_REG35_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG35_RESERVED_SHIFT)) & USB3_CFG_REG35_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG36 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG36_LFPS_GEN_PING_MASK        (0x1FU)
#define USB3_CFG_REG36_LFPS_GEN_PING_SHIFT       (0U)
#define USB3_CFG_REG36_LFPS_GEN_PING(x)          (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG36_LFPS_GEN_PING_SHIFT)) & USB3_CFG_REG36_LFPS_GEN_PING_MASK)
#define USB3_CFG_REG36_RESERVED_MASK             (0xFFFFFFE0U)
#define USB3_CFG_REG36_RESERVED_SHIFT            (5U)
#define USB3_CFG_REG36_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG36_RESERVED_SHIFT)) & USB3_CFG_REG36_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG37 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG37_LFPS_GEN_POLLING_MASK     (0xFFU)
#define USB3_CFG_REG37_LFPS_GEN_POLLING_SHIFT    (0U)
#define USB3_CFG_REG37_LFPS_GEN_POLLING(x)       (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG37_LFPS_GEN_POLLING_SHIFT)) & USB3_CFG_REG37_LFPS_GEN_POLLING_MASK)
#define USB3_CFG_REG37_RESERVED_MASK             (0xFFFFFF00U)
#define USB3_CFG_REG37_RESERVED_SHIFT            (8U)
#define USB3_CFG_REG37_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG37_RESERVED_SHIFT)) & USB3_CFG_REG37_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG38 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG38_LFPS_GEN_U1EXIT_MASK      (0x3FFFFU)
#define USB3_CFG_REG38_LFPS_GEN_U1EXIT_SHIFT     (0U)
#define USB3_CFG_REG38_LFPS_GEN_U1EXIT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG38_LFPS_GEN_U1EXIT_SHIFT)) & USB3_CFG_REG38_LFPS_GEN_U1EXIT_MASK)
#define USB3_CFG_REG38_RESERVED_MASK             (0xFFFC0000U)
#define USB3_CFG_REG38_RESERVED_SHIFT            (18U)
#define USB3_CFG_REG38_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG38_RESERVED_SHIFT)) & USB3_CFG_REG38_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG39 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG39_LFPS_GEN_U3EXIT_MASK      (0x1FFFFFU)
#define USB3_CFG_REG39_LFPS_GEN_U3EXIT_SHIFT     (0U)
#define USB3_CFG_REG39_LFPS_GEN_U3EXIT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG39_LFPS_GEN_U3EXIT_SHIFT)) & USB3_CFG_REG39_LFPS_GEN_U3EXIT_MASK)
#define USB3_CFG_REG39_RESERVED_MASK             (0xFFE00000U)
#define USB3_CFG_REG39_RESERVED_SHIFT            (21U)
#define USB3_CFG_REG39_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG39_RESERVED_SHIFT)) & USB3_CFG_REG39_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG40 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT_MASK  (0x7FU)
#define USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT_SHIFT (0U)
#define USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT_SHIFT)) & USB3_CFG_REG40_LFPS_MIN_GEN_U1EXIT_MASK)
#define USB3_CFG_REG40_RESERVED_MASK             (0xFFFFFF80U)
#define USB3_CFG_REG40_RESERVED_SHIFT            (7U)
#define USB3_CFG_REG40_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG40_RESERVED_SHIFT)) & USB3_CFG_REG40_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG41 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT_MASK  (0x7FFFU)
#define USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT_SHIFT (0U)
#define USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT_SHIFT)) & USB3_CFG_REG41_LFPS_MIN_GEN_U2EXIT_MASK)
#define USB3_CFG_REG41_RESERVED_MASK             (0xFFFF8000U)
#define USB3_CFG_REG41_RESERVED_SHIFT            (15U)
#define USB3_CFG_REG41_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG41_RESERVED_SHIFT)) & USB3_CFG_REG41_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG42 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG42_LFPS_POLLING_REPEAT_MASK  (0x7FFU)
#define USB3_CFG_REG42_LFPS_POLLING_REPEAT_SHIFT (0U)
#define USB3_CFG_REG42_LFPS_POLLING_REPEAT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG42_LFPS_POLLING_REPEAT_SHIFT)) & USB3_CFG_REG42_LFPS_POLLING_REPEAT_MASK)
#define USB3_CFG_REG42_RESERVED_MASK             (0xFFFFF800U)
#define USB3_CFG_REG42_RESERVED_SHIFT            (11U)
#define USB3_CFG_REG42_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG42_RESERVED_SHIFT)) & USB3_CFG_REG42_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG43 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT_MASK (0x7FFU)
#define USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT_SHIFT (0U)
#define USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT_SHIFT)) & USB3_CFG_REG43_LFPS_POLLING_MAX_TREPEAT_MASK)
#define USB3_CFG_REG43_RESERVED_MASK             (0xFFFFF800U)
#define USB3_CFG_REG43_RESERVED_SHIFT            (11U)
#define USB3_CFG_REG43_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG43_RESERVED_SHIFT)) & USB3_CFG_REG43_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG44 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT_MASK (0x7FFU)
#define USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT_SHIFT (0U)
#define USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT_SHIFT)) & USB3_CFG_REG44_LFPS_POLLING_MIN_TREPEAT_MASK)
#define USB3_CFG_REG44_RESERVED_MASK             (0xFFFFF800U)
#define USB3_CFG_REG44_RESERVED_SHIFT            (11U)
#define USB3_CFG_REG44_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG44_RESERVED_SHIFT)) & USB3_CFG_REG44_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG45 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_MASK   (0x7FU)
#define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_SHIFT  (0U)
#define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT(x)     (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_SHIFT)) & USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_MASK)
#define USB3_CFG_REG45_RESERVED_MASK             (0x3FFFFF80U)
#define USB3_CFG_REG45_RESERVED_SHIFT            (7U)
#define USB3_CFG_REG45_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG45_RESERVED_SHIFT)) & USB3_CFG_REG45_RESERVED_MASK)
#define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE_SHIFT)) & USB3_CFG_REG45_ITP_WAKEUP_TIMEOUT_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG46 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG46_TSEQ_QUANTITY_MASK        (0xFFFFU)
#define USB3_CFG_REG46_TSEQ_QUANTITY_SHIFT       (0U)
#define USB3_CFG_REG46_TSEQ_QUANTITY(x)          (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG46_TSEQ_QUANTITY_SHIFT)) & USB3_CFG_REG46_TSEQ_QUANTITY_MASK)
#define USB3_CFG_REG46_RESERVED_MASK             (0xFFFF0000U)
#define USB3_CFG_REG46_RESERVED_SHIFT            (16U)
#define USB3_CFG_REG46_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG46_RESERVED_SHIFT)) & USB3_CFG_REG46_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG47 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG47_ERDY_TIMEOUT_CNT_MASK     (0xFFFFFU)
#define USB3_CFG_REG47_ERDY_TIMEOUT_CNT_SHIFT    (0U)
#define USB3_CFG_REG47_ERDY_TIMEOUT_CNT(x)       (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG47_ERDY_TIMEOUT_CNT_SHIFT)) & USB3_CFG_REG47_ERDY_TIMEOUT_CNT_MASK)
#define USB3_CFG_REG47_RESERVED_MASK             (0xFFF00000U)
#define USB3_CFG_REG47_RESERVED_SHIFT            (20U)
#define USB3_CFG_REG47_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG47_RESERVED_SHIFT)) & USB3_CFG_REG47_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG48 - USB2 Configuration */
/*! @{ */
#define USB3_CFG_REG48_TWTRSTFS_J_CNT_MASK       (0x3FFFFU)
#define USB3_CFG_REG48_TWTRSTFS_J_CNT_SHIFT      (0U)
#define USB3_CFG_REG48_TWTRSTFS_J_CNT(x)         (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG48_TWTRSTFS_J_CNT_SHIFT)) & USB3_CFG_REG48_TWTRSTFS_J_CNT_MASK)
#define USB3_CFG_REG48_RESERVED_MASK             (0xFFFC0000U)
#define USB3_CFG_REG48_RESERVED_SHIFT            (18U)
#define USB3_CFG_REG48_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG48_RESERVED_SHIFT)) & USB3_CFG_REG48_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG49 - USB2 Configuration */
/*! @{ */
#define USB3_CFG_REG49_TUCH_CNT_MASK             (0xFFFFU)
#define USB3_CFG_REG49_TUCH_CNT_SHIFT            (0U)
#define USB3_CFG_REG49_TUCH_CNT(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG49_TUCH_CNT_SHIFT)) & USB3_CFG_REG49_TUCH_CNT_MASK)
#define USB3_CFG_REG49_RESERVED_MASK             (0xFFFF0000U)
#define USB3_CFG_REG49_RESERVED_SHIFT            (16U)
#define USB3_CFG_REG49_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG49_RESERVED_SHIFT)) & USB3_CFG_REG49_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG50 - USB2 Configuration */
/*! @{ */
#define USB3_CFG_REG50_TWAITCHK_CNT_MASK         (0xFFFU)
#define USB3_CFG_REG50_TWAITCHK_CNT_SHIFT        (0U)
#define USB3_CFG_REG50_TWAITCHK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG50_TWAITCHK_CNT_SHIFT)) & USB3_CFG_REG50_TWAITCHK_CNT_MASK)
#define USB3_CFG_REG50_RESERVED_MASK             (0xFFFFF000U)
#define USB3_CFG_REG50_RESERVED_SHIFT            (12U)
#define USB3_CFG_REG50_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG50_RESERVED_SHIFT)) & USB3_CFG_REG50_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG51 - USB2 Configuration */
/*! @{ */
#define USB3_CFG_REG51_TWTFS_CNT_MASK            (0x1FFFFU)
#define USB3_CFG_REG51_TWTFS_CNT_SHIFT           (0U)
#define USB3_CFG_REG51_TWTFS_CNT(x)              (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG51_TWTFS_CNT_SHIFT)) & USB3_CFG_REG51_TWTFS_CNT_MASK)
#define USB3_CFG_REG51_RESERVED_MASK             (0xFFFE0000U)
#define USB3_CFG_REG51_RESERVED_SHIFT            (17U)
#define USB3_CFG_REG51_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG51_RESERVED_SHIFT)) & USB3_CFG_REG51_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG52 - USB2 Configuration */
/*! @{ */
#define USB3_CFG_REG52_TWTREV_CNT_MASK           (0x1FFFFU)
#define USB3_CFG_REG52_TWTREV_CNT_SHIFT          (0U)
#define USB3_CFG_REG52_TWTREV_CNT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG52_TWTREV_CNT_SHIFT)) & USB3_CFG_REG52_TWTREV_CNT_MASK)
#define USB3_CFG_REG52_RESERVED_MASK             (0xFFFE0000U)
#define USB3_CFG_REG52_RESERVED_SHIFT            (17U)
#define USB3_CFG_REG52_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG52_RESERVED_SHIFT)) & USB3_CFG_REG52_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG53 - USB2 Configuration */
/*! @{ */
#define USB3_CFG_REG53_TWTRSTHS_CNT_MASK         (0x7FFFU)
#define USB3_CFG_REG53_TWTRSTHS_CNT_SHIFT        (0U)
#define USB3_CFG_REG53_TWTRSTHS_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG53_TWTRSTHS_CNT_SHIFT)) & USB3_CFG_REG53_TWTRSTHS_CNT_MASK)
#define USB3_CFG_REG53_RESERVED_MASK             (0xFFFF8000U)
#define USB3_CFG_REG53_RESERVED_SHIFT            (15U)
#define USB3_CFG_REG53_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG53_RESERVED_SHIFT)) & USB3_CFG_REG53_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG54 - USB2 Configuration */
/*! @{ */
#define USB3_CFG_REG54_TWTRSM_CNT_MASK           (0x3FFFFU)
#define USB3_CFG_REG54_TWTRSM_CNT_SHIFT          (0U)
#define USB3_CFG_REG54_TWTRSM_CNT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG54_TWTRSM_CNT_SHIFT)) & USB3_CFG_REG54_TWTRSM_CNT_MASK)
#define USB3_CFG_REG54_RESERVED_MASK             (0xFFFC0000U)
#define USB3_CFG_REG54_RESERVED_SHIFT            (18U)
#define USB3_CFG_REG54_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG54_RESERVED_SHIFT)) & USB3_CFG_REG54_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG55 - USB2 Configuration */
/*! @{ */
#define USB3_CFG_REG55_TDRSMUP_CNT_MASK          (0xFFFFU)
#define USB3_CFG_REG55_TDRSMUP_CNT_SHIFT         (0U)
#define USB3_CFG_REG55_TDRSMUP_CNT(x)            (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG55_TDRSMUP_CNT_SHIFT)) & USB3_CFG_REG55_TDRSMUP_CNT_MASK)
#define USB3_CFG_REG55_RESERVED_MASK             (0xFFFF0000U)
#define USB3_CFG_REG55_RESERVED_SHIFT            (16U)
#define USB3_CFG_REG55_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG55_RESERVED_SHIFT)) & USB3_CFG_REG55_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG56 - USB2 Configuration */
/*! @{ */
#define USB3_CFG_REG56_TOUTHS_CNT_MASK           (0x3FU)
#define USB3_CFG_REG56_TOUTHS_CNT_SHIFT          (0U)
#define USB3_CFG_REG56_TOUTHS_CNT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG56_TOUTHS_CNT_SHIFT)) & USB3_CFG_REG56_TOUTHS_CNT_MASK)
#define USB3_CFG_REG56_RESERVED_MASK             (0xFFFFFFC0U)
#define USB3_CFG_REG56_RESERVED_SHIFT            (6U)
#define USB3_CFG_REG56_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG56_RESERVED_SHIFT)) & USB3_CFG_REG56_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG57 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG57_LFPS_DEB_WIDTH_MASK       (0x3U)
#define USB3_CFG_REG57_LFPS_DEB_WIDTH_SHIFT      (0U)
#define USB3_CFG_REG57_LFPS_DEB_WIDTH(x)         (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG57_LFPS_DEB_WIDTH_SHIFT)) & USB3_CFG_REG57_LFPS_DEB_WIDTH_MASK)
#define USB3_CFG_REG57_RESERVED_MASK             (0xFFFFFFFCU)
#define USB3_CFG_REG57_RESERVED_SHIFT            (2U)
#define USB3_CFG_REG57_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG57_RESERVED_SHIFT)) & USB3_CFG_REG57_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG58 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG58_LFPS_GEN_U2EXIT_MASK      (0x3FFFFU)
#define USB3_CFG_REG58_LFPS_GEN_U2EXIT_SHIFT     (0U)
#define USB3_CFG_REG58_LFPS_GEN_U2EXIT(x)        (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG58_LFPS_GEN_U2EXIT_SHIFT)) & USB3_CFG_REG58_LFPS_GEN_U2EXIT_MASK)
#define USB3_CFG_REG58_RESERVED_MASK             (0xFFFC0000U)
#define USB3_CFG_REG58_RESERVED_SHIFT            (18U)
#define USB3_CFG_REG58_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG58_RESERVED_SHIFT)) & USB3_CFG_REG58_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG59 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT_MASK  (0xFFFFU)
#define USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT_SHIFT (0U)
#define USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT_SHIFT)) & USB3_CFG_REG59_LFPS_MIN_GEN_U3EXIT_MASK)
#define USB3_CFG_REG59_RESERVED_MASK             (0xFFFF0000U)
#define USB3_CFG_REG59_RESERVED_SHIFT            (16U)
#define USB3_CFG_REG59_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG59_RESERVED_SHIFT)) & USB3_CFG_REG59_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG60 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG60_PORT_CONFIG_TIMEOUT_MASK  (0x7FU)
#define USB3_CFG_REG60_PORT_CONFIG_TIMEOUT_SHIFT (0U)
#define USB3_CFG_REG60_PORT_CONFIG_TIMEOUT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG60_PORT_CONFIG_TIMEOUT_SHIFT)) & USB3_CFG_REG60_PORT_CONFIG_TIMEOUT_MASK)
#define USB3_CFG_REG60_RESERVED_MASK             (0xFFFFFF80U)
#define USB3_CFG_REG60_RESERVED_SHIFT            (7U)
#define USB3_CFG_REG60_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG60_RESERVED_SHIFT)) & USB3_CFG_REG60_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG61 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ_MASK (0x7FFU)
#define USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ_SHIFT (0U)
#define USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ(x)  (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ_SHIFT)) & USB3_CFG_REG61_LFPS_POL_LFPS_TO_RXEQ_MASK)
#define USB3_CFG_REG61_RESERVED_MASK             (0xFFFFF800U)
#define USB3_CFG_REG61_RESERVED_SHIFT            (11U)
#define USB3_CFG_REG61_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG61_RESERVED_SHIFT)) & USB3_CFG_REG61_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG62 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG62_PHY_TX_LATENCY_MASK       (0x3FU)
#define USB3_CFG_REG62_PHY_TX_LATENCY_SHIFT      (0U)
#define USB3_CFG_REG62_PHY_TX_LATENCY(x)         (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG62_PHY_TX_LATENCY_SHIFT)) & USB3_CFG_REG62_PHY_TX_LATENCY_MASK)
#define USB3_CFG_REG62_RESERVED_MASK             (0x3FFFFFC0U)
#define USB3_CFG_REG62_RESERVED_SHIFT            (6U)
#define USB3_CFG_REG62_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG62_RESERVED_SHIFT)) & USB3_CFG_REG62_RESERVED_MASK)
#define USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE_MASK (0xC0000000U)
#define USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE_SHIFT (30U)
#define USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE_SHIFT)) & USB3_CFG_REG62_PHY_TX_LATENCY_PRESCALE_MASK)
/*! @} */

/*! @name CFG_REG63 - USB3 Configuration */
/*! @{ */
#define USB3_CFG_REG63_U2_INACTIVITY_TMOUT_MASK  (0x7FFFU)
#define USB3_CFG_REG63_U2_INACTIVITY_TMOUT_SHIFT (0U)
#define USB3_CFG_REG63_U2_INACTIVITY_TMOUT(x)    (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG63_U2_INACTIVITY_TMOUT_SHIFT)) & USB3_CFG_REG63_U2_INACTIVITY_TMOUT_MASK)
#define USB3_CFG_REG63_RESERVED_MASK             (0xFFFF8000U)
#define USB3_CFG_REG63_RESERVED_SHIFT            (15U)
#define USB3_CFG_REG63_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG63_RESERVED_SHIFT)) & USB3_CFG_REG63_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG64 - USB2 Configuration */
/*! @{ */
#define USB3_CFG_REG64_TFILTSE0_MASK             (0x7FU)
#define USB3_CFG_REG64_TFILTSE0_SHIFT            (0U)
#define USB3_CFG_REG64_TFILTSE0(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG64_TFILTSE0_SHIFT)) & USB3_CFG_REG64_TFILTSE0_MASK)
#define USB3_CFG_REG64_RESERVED_MASK             (0xFFFFFF80U)
#define USB3_CFG_REG64_RESERVED_SHIFT            (7U)
#define USB3_CFG_REG64_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG64_RESERVED_SHIFT)) & USB3_CFG_REG64_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG65 - USB2 Configuration */
/*! @{ */
#define USB3_CFG_REG65_TFILT_MASK                (0x7FU)
#define USB3_CFG_REG65_TFILT_SHIFT               (0U)
#define USB3_CFG_REG65_TFILT(x)                  (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG65_TFILT_SHIFT)) & USB3_CFG_REG65_TFILT_MASK)
#define USB3_CFG_REG65_RESERVED_MASK             (0xFFFF8000U)
#define USB3_CFG_REG65_RESERVED_SHIFT            (15U)
#define USB3_CFG_REG65_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG65_RESERVED_SHIFT)) & USB3_CFG_REG65_RESERVED_MASK)
/*! @} */

/*! @name CFG_REG66 - USB2 Configuration */
/*! @{ */
#define USB3_CFG_REG66_TWTRSTFS_SE0_MASK         (0x7FU)
#define USB3_CFG_REG66_TWTRSTFS_SE0_SHIFT        (0U)
#define USB3_CFG_REG66_TWTRSTFS_SE0(x)           (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG66_TWTRSTFS_SE0_SHIFT)) & USB3_CFG_REG66_TWTRSTFS_SE0_MASK)
#define USB3_CFG_REG66_RESERVED_MASK             (0xFFFF8000U)
#define USB3_CFG_REG66_RESERVED_SHIFT            (15U)
#define USB3_CFG_REG66_RESERVED(x)               (((uint32_t)(((uint32_t)(x)) << USB3_CFG_REG66_RESERVED_SHIFT)) & USB3_CFG_REG66_RESERVED_MASK)
/*! @} */

/*! @name DMA_AXI_CTRL - DMA AXI Master Control */
/*! @{ */
#define USB3_DMA_AXI_CTRL_MARPROT_MASK           (0x7U)
#define USB3_DMA_AXI_CTRL_MARPROT_SHIFT          (0U)
#define USB3_DMA_AXI_CTRL_MARPROT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MARPROT_SHIFT)) & USB3_DMA_AXI_CTRL_MARPROT_MASK)
#define USB3_DMA_AXI_CTRL_RESERVED0_MASK         (0x8U)
#define USB3_DMA_AXI_CTRL_RESERVED0_SHIFT        (3U)
#define USB3_DMA_AXI_CTRL_RESERVED0(x)           (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_RESERVED0_SHIFT)) & USB3_DMA_AXI_CTRL_RESERVED0_MASK)
#define USB3_DMA_AXI_CTRL_MARCACHE_MASK          (0xF0U)
#define USB3_DMA_AXI_CTRL_MARCACHE_SHIFT         (4U)
#define USB3_DMA_AXI_CTRL_MARCACHE(x)            (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MARCACHE_SHIFT)) & USB3_DMA_AXI_CTRL_MARCACHE_MASK)
#define USB3_DMA_AXI_CTRL_MARLOCK_MASK           (0x300U)
#define USB3_DMA_AXI_CTRL_MARLOCK_SHIFT          (8U)
#define USB3_DMA_AXI_CTRL_MARLOCK(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MARLOCK_SHIFT)) & USB3_DMA_AXI_CTRL_MARLOCK_MASK)
#define USB3_DMA_AXI_CTRL_RESERVED1_MASK         (0xFC00U)
#define USB3_DMA_AXI_CTRL_RESERVED1_SHIFT        (10U)
#define USB3_DMA_AXI_CTRL_RESERVED1(x)           (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_RESERVED1_SHIFT)) & USB3_DMA_AXI_CTRL_RESERVED1_MASK)
#define USB3_DMA_AXI_CTRL_MAWPROT_MASK           (0x70000U)
#define USB3_DMA_AXI_CTRL_MAWPROT_SHIFT          (16U)
#define USB3_DMA_AXI_CTRL_MAWPROT(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MAWPROT_SHIFT)) & USB3_DMA_AXI_CTRL_MAWPROT_MASK)
#define USB3_DMA_AXI_CTRL_RESERVED2_MASK         (0x80000U)
#define USB3_DMA_AXI_CTRL_RESERVED2_SHIFT        (19U)
#define USB3_DMA_AXI_CTRL_RESERVED2(x)           (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_RESERVED2_SHIFT)) & USB3_DMA_AXI_CTRL_RESERVED2_MASK)
#define USB3_DMA_AXI_CTRL_MAWCACHE_MASK          (0xF00000U)
#define USB3_DMA_AXI_CTRL_MAWCACHE_SHIFT         (20U)
#define USB3_DMA_AXI_CTRL_MAWCACHE(x)            (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MAWCACHE_SHIFT)) & USB3_DMA_AXI_CTRL_MAWCACHE_MASK)
#define USB3_DMA_AXI_CTRL_MAWLOCK_MASK           (0x3000000U)
#define USB3_DMA_AXI_CTRL_MAWLOCK_SHIFT          (24U)
#define USB3_DMA_AXI_CTRL_MAWLOCK(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_MAWLOCK_SHIFT)) & USB3_DMA_AXI_CTRL_MAWLOCK_MASK)
#define USB3_DMA_AXI_CTRL_RESERVED3_MASK         (0xFC000000U)
#define USB3_DMA_AXI_CTRL_RESERVED3_SHIFT        (26U)
#define USB3_DMA_AXI_CTRL_RESERVED3(x)           (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL_RESERVED3_SHIFT)) & USB3_DMA_AXI_CTRL_RESERVED3_MASK)
/*! @} */

/*! @name DMA_AXI_ID - DMA AXI Master ID */
/*! @{ */
#define USB3_DMA_AXI_ID_MAW_ID_MASK              (0x1FU)
#define USB3_DMA_AXI_ID_MAW_ID_SHIFT             (0U)
#define USB3_DMA_AXI_ID_MAW_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_ID_MAW_ID_SHIFT)) & USB3_DMA_AXI_ID_MAW_ID_MASK)
#define USB3_DMA_AXI_ID_RESERVED0_MASK           (0xFFE0U)
#define USB3_DMA_AXI_ID_RESERVED0_SHIFT          (5U)
#define USB3_DMA_AXI_ID_RESERVED0(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_ID_RESERVED0_SHIFT)) & USB3_DMA_AXI_ID_RESERVED0_MASK)
#define USB3_DMA_AXI_ID_MAR_ID_MASK              (0x1F0000U)
#define USB3_DMA_AXI_ID_MAR_ID_SHIFT             (16U)
#define USB3_DMA_AXI_ID_MAR_ID(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_ID_MAR_ID_SHIFT)) & USB3_DMA_AXI_ID_MAR_ID_MASK)
#define USB3_DMA_AXI_ID_RESERVED1_MASK           (0xFFE00000U)
#define USB3_DMA_AXI_ID_RESERVED1_SHIFT          (21U)
#define USB3_DMA_AXI_ID_RESERVED1(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_ID_RESERVED1_SHIFT)) & USB3_DMA_AXI_ID_RESERVED1_MASK)
/*! @} */

/*! @name DMA_AXI_CAP - DMA AXI Master Extended Capability */
/*! @{ */
#define USB3_DMA_AXI_CAP_RESERVED0_MASK          (0xFFFFFU)
#define USB3_DMA_AXI_CAP_RESERVED0_SHIFT         (0U)
#define USB3_DMA_AXI_CAP_RESERVED0(x)            (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_RESERVED0_SHIFT)) & USB3_DMA_AXI_CAP_RESERVED0_MASK)
#define USB3_DMA_AXI_CAP_AXI_DECERR_EN_MASK      (0x100000U)
#define USB3_DMA_AXI_CAP_AXI_DECERR_EN_SHIFT     (20U)
#define USB3_DMA_AXI_CAP_AXI_DECERR_EN(x)        (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_DECERR_EN_SHIFT)) & USB3_DMA_AXI_CAP_AXI_DECERR_EN_MASK)
#define USB3_DMA_AXI_CAP_AXI_SLVERR_EN_MASK      (0x200000U)
#define USB3_DMA_AXI_CAP_AXI_SLVERR_EN_SHIFT     (21U)
#define USB3_DMA_AXI_CAP_AXI_SLVERR_EN(x)        (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_SLVERR_EN_SHIFT)) & USB3_DMA_AXI_CAP_AXI_SLVERR_EN_MASK)
#define USB3_DMA_AXI_CAP_RESERVED1_MASK          (0xFC00000U)
#define USB3_DMA_AXI_CAP_RESERVED1_SHIFT         (22U)
#define USB3_DMA_AXI_CAP_RESERVED1(x)            (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_RESERVED1_SHIFT)) & USB3_DMA_AXI_CAP_RESERVED1_MASK)
#define USB3_DMA_AXI_CAP_AXI_DECERR_MASK         (0x10000000U)
#define USB3_DMA_AXI_CAP_AXI_DECERR_SHIFT        (28U)
#define USB3_DMA_AXI_CAP_AXI_DECERR(x)           (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_DECERR_SHIFT)) & USB3_DMA_AXI_CAP_AXI_DECERR_MASK)
#define USB3_DMA_AXI_CAP_AXI_SLVERR_MASK         (0x20000000U)
#define USB3_DMA_AXI_CAP_AXI_SLVERR_SHIFT        (29U)
#define USB3_DMA_AXI_CAP_AXI_SLVERR(x)           (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_SLVERR_SHIFT)) & USB3_DMA_AXI_CAP_AXI_SLVERR_MASK)
#define USB3_DMA_AXI_CAP_AXI_IDLE_MASK           (0x40000000U)
#define USB3_DMA_AXI_CAP_AXI_IDLE_SHIFT          (30U)
#define USB3_DMA_AXI_CAP_AXI_IDLE(x)             (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_AXI_IDLE_SHIFT)) & USB3_DMA_AXI_CAP_AXI_IDLE_MASK)
#define USB3_DMA_AXI_CAP_RESERVED2_MASK          (0x80000000U)
#define USB3_DMA_AXI_CAP_RESERVED2_SHIFT         (31U)
#define USB3_DMA_AXI_CAP_RESERVED2(x)            (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CAP_RESERVED2_SHIFT)) & USB3_DMA_AXI_CAP_RESERVED2_MASK)
/*! @} */

/*! @name DMA_AXI_CTRL0 - DMA AXI Master Control */
/*! @{ */
#define USB3_DMA_AXI_CTRL0_B_MAX_MASK            (0xFU)
#define USB3_DMA_AXI_CTRL0_B_MAX_SHIFT           (0U)
#define USB3_DMA_AXI_CTRL0_B_MAX(x)              (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL0_B_MAX_SHIFT)) & USB3_DMA_AXI_CTRL0_B_MAX_MASK)
#define USB3_DMA_AXI_CTRL0_RESERVED_MASK         (0xFFFFFFF0U)
#define USB3_DMA_AXI_CTRL0_RESERVED_SHIFT        (4U)
#define USB3_DMA_AXI_CTRL0_RESERVED(x)           (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL0_RESERVED_SHIFT)) & USB3_DMA_AXI_CTRL0_RESERVED_MASK)
/*! @} */

/*! @name DMA_AXI_CTRL1 - DMA AXI Master Control */
/*! @{ */
#define USB3_DMA_AXI_CTRL1_ROT_MASK              (0x1FU)
#define USB3_DMA_AXI_CTRL1_ROT_SHIFT             (0U)
#define USB3_DMA_AXI_CTRL1_ROT(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL1_ROT_SHIFT)) & USB3_DMA_AXI_CTRL1_ROT_MASK)
#define USB3_DMA_AXI_CTRL1_RESERVED0_MASK        (0xFFE0U)
#define USB3_DMA_AXI_CTRL1_RESERVED0_SHIFT       (5U)
#define USB3_DMA_AXI_CTRL1_RESERVED0(x)          (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL1_RESERVED0_SHIFT)) & USB3_DMA_AXI_CTRL1_RESERVED0_MASK)
#define USB3_DMA_AXI_CTRL1_WOT_MASK              (0x1F0000U)
#define USB3_DMA_AXI_CTRL1_WOT_SHIFT             (16U)
#define USB3_DMA_AXI_CTRL1_WOT(x)                (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL1_WOT_SHIFT)) & USB3_DMA_AXI_CTRL1_WOT_MASK)
#define USB3_DMA_AXI_CTRL1_RESERVED1_MASK        (0xFFE00000U)
#define USB3_DMA_AXI_CTRL1_RESERVED1_SHIFT       (21U)
#define USB3_DMA_AXI_CTRL1_RESERVED1(x)          (((uint32_t)(((uint32_t)(x)) << USB3_DMA_AXI_CTRL1_RESERVED1_SHIFT)) & USB3_DMA_AXI_CTRL1_RESERVED1_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USB3_Register_Masks */


/* USB3 - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__USB3 base address */
#define CONNECTIVITY__USB3_BASE                  (0x5B110000u)
/** Peripheral CONNECTIVITY__USB3 base pointer */
#define CONNECTIVITY__USB3                       ((USB3_Type *)CONNECTIVITY__USB3_BASE)
/** Array initializer of USB3 peripheral base addresses */
#define USB3_BASE_ADDRS                          { CONNECTIVITY__USB3_BASE }
/** Array initializer of USB3 peripheral base pointers */
#define USB3_BASE_PTRS                           { CONNECTIVITY__USB3 }
/** Interrupt vectors for the USB3 peripheral type */
#define USB3_IRQS                                { CONNECTIVITY_USB3_INT_IRQn }

/*!
 * @}
 */ /* end of group USB3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USBDCD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
 * @{
 */

/** USBDCD - Register Layout Typedef */
typedef struct {
  __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
  __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
  __IO uint32_t STATUS;                            /**< Status register, offset: 0x8 */
  __IO uint32_t SIGNAL_OVERRIDE;                   /**< Signal Override Register, offset: 0xC */
  __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
  __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
  union {                                          /* offset: 0x18 */
    __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
    __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
  };
} USBDCD_Type;

/* ----------------------------------------------------------------------------
   -- USBDCD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
 * @{
 */

/*! @name CONTROL - Control register */
/*! @{ */
#define USBDCD_CONTROL_IACK_MASK                 (0x1U)
#define USBDCD_CONTROL_IACK_SHIFT                (0U)
/*! IACK - Interrupt Acknowledge
 *  0b0..Do not clear the interrupt.
 *  0b1..Clear the IF bit (interrupt flag).
 */
#define USBDCD_CONTROL_IACK(x)                   (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
#define USBDCD_CONTROL_IF_MASK                   (0x100U)
#define USBDCD_CONTROL_IF_SHIFT                  (8U)
/*! IF - Interrupt Flag
 *  0b0..No interrupt is pending.
 *  0b1..An interrupt is pending.
 */
#define USBDCD_CONTROL_IF(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
#define USBDCD_CONTROL_IE_MASK                   (0x10000U)
#define USBDCD_CONTROL_IE_SHIFT                  (16U)
/*! IE - Interrupt Enable
 *  0b0..Disable interrupts to the system.
 *  0b1..Enable interrupts to the system.
 */
#define USBDCD_CONTROL_IE(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
#define USBDCD_CONTROL_BC12_MASK                 (0x20000U)
#define USBDCD_CONTROL_BC12_SHIFT                (17U)
/*! BC12 - BC12
 *  0b0..Compatible with BC1.1 (default)
 *  0b1..Compatible with BC1.2
 */
#define USBDCD_CONTROL_BC12(x)                   (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
#define USBDCD_CONTROL_START_MASK                (0x1000000U)
#define USBDCD_CONTROL_START_SHIFT               (24U)
/*! START - Start Change Detection Sequence
 *  0b0..Do not start the sequence. Writes of this value have no effect.
 *  0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
 */
#define USBDCD_CONTROL_START(x)                  (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
#define USBDCD_CONTROL_SR_MASK                   (0x2000000U)
#define USBDCD_CONTROL_SR_SHIFT                  (25U)
/*! SR - Software Reset
 *  0b0..Do not perform a software reset.
 *  0b1..Perform a software reset.
 */
#define USBDCD_CONTROL_SR(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
/*! @} */

/*! @name CLOCK - Clock register */
/*! @{ */
#define USBDCD_CLOCK_CLOCK_UNIT_MASK             (0x1U)
#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            (0U)
/*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
 *  0b0..kHz Speed (between 1 kHz and 1023 kHz)
 *  0b1..MHz Speed (between 1 MHz and 1023 MHz)
 */
#define USBDCD_CLOCK_CLOCK_UNIT(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
#define USBDCD_CLOCK_CLOCK_SPEED_MASK            (0xFFCU)
#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           (2U)
#define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
/*! @} */

/*! @name STATUS - Status register */
/*! @{ */
#define USBDCD_STATUS_DP_STATE_MACHINE_MASK      (0xFU)
#define USBDCD_STATUS_DP_STATE_MACHINE_SHIFT     (0U)
/*! DP_STATE_MACHINE - Data Pin State Machine
 *  0b0000..IDLE
 *  0b0001..CHECK_DP_LOW
 *  0b0010..DEBOUNCE_DP
 *  0b0011..WAIT_FOR_ONE_MS
 *  0b0100..Not used
 *  0b0101..CHECK_CP
 *  0b0110..CHECK_DM
 *  0b0111..TIMER_DONE_SM
 *  0b1000..WAIT_FOR_PULLUP
 *  0b1001..WAIT_FOR_CLOCKS
 *  0b1010..Not used
 *  0b1110..Not used
 *  0b1111..DONE
 */
#define USBDCD_STATUS_DP_STATE_MACHINE(x)        (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_DP_STATE_MACHINE_SHIFT)) & USBDCD_STATUS_DP_STATE_MACHINE_MASK)
#define USBDCD_STATUS_TIM_ACT_MASK               (0x3F00U)
#define USBDCD_STATUS_TIM_ACT_SHIFT              (8U)
#define USBDCD_STATUS_TIM_ACT(x)                 (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TIM_ACT_SHIFT)) & USBDCD_STATUS_TIM_ACT_MASK)
#define USBDCD_STATUS_SEQ_RES_MASK               (0x30000U)
#define USBDCD_STATUS_SEQ_RES_SHIFT              (16U)
/*! SEQ_RES - Charger Detection Sequence Results
 *  0b00..No results to report.
 *  0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
 *  0b11..Attached to a DCP.
 */
#define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
#define USBDCD_STATUS_SEQ_STAT_MASK              (0xC0000U)
#define USBDCD_STATUS_SEQ_STAT_SHIFT             (18U)
/*! SEQ_STAT - Charger Detection Sequence Status
 *  0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
 *  0b01..Data pin contact detection is complete.
 *  0b10..Charging port detection is complete.
 *  0b11..Charger type detection is complete.
 */
#define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
#define USBDCD_STATUS_ERR_MASK                   (0x100000U)
#define USBDCD_STATUS_ERR_SHIFT                  (20U)
/*! ERR - Error Flag
 *  0b0..No sequence errors.
 *  0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.
 */
#define USBDCD_STATUS_ERR(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
#define USBDCD_STATUS_TO_MASK                    (0x200000U)
#define USBDCD_STATUS_TO_SHIFT                   (21U)
/*! TO - Timeout Flag
 *  0b0..The detection sequence has not been running for over 1 s.
 *  0b1..It has been over 1 s since the data pin contact was detected and debounced.
 */
#define USBDCD_STATUS_TO(x)                      (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
#define USBDCD_STATUS_ACTIVE_MASK                (0x400000U)
#define USBDCD_STATUS_ACTIVE_SHIFT               (22U)
/*! ACTIVE - Active Status Indicator
 *  0b0..The sequence is not running.
 *  0b1..The sequence is running.
 */
#define USBDCD_STATUS_ACTIVE(x)                  (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
/*! @} */

/*! @name SIGNAL_OVERRIDE - Signal Override Register */
/*! @{ */
#define USBDCD_SIGNAL_OVERRIDE_PS_MASK           (0x3U)
#define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT          (0U)
/*! PS - Phase Selection
 *  0b00..No overrides. Same behavior as functional mode.
 *  0b01..usbdcd_en and usbdcd_data_cont_det_en signals to analog block are forced high. Enables IDP_SRC and RDM_DWN.
 *  0b10..usbdcd_en and usbdcd_chg_det_en signals to analog block are forced high. Enables VDP_SRC and IDM_SINK.
 */
#define USBDCD_SIGNAL_OVERRIDE_PS(x)             (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK)
#define USBDCD_SIGNAL_OVERRIDE_DMIR_MASK         (0x100U)
#define USBDCD_SIGNAL_OVERRIDE_DMIR_SHIFT        (8U)
/*! DMIR - usbdcd_dm_in_range (DMIR) status in selected phase
 *  0b0..D- voltage is not within the defined range.
 *  0b1..D- voltage is within the defined range.
 */
#define USBDCD_SIGNAL_OVERRIDE_DMIR(x)           (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_DMIR_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_DMIR_MASK)
#define USBDCD_SIGNAL_OVERRIDE_DPIR_MASK         (0x200U)
#define USBDCD_SIGNAL_OVERRIDE_DPIR_SHIFT        (9U)
/*! DPIR - usbdcd_dp_in_range (DPIR) status in selected phase
 *  0b0..D+ voltage is not within the defined range.
 *  0b1..D+ voltage is within the defined range.
 */
#define USBDCD_SIGNAL_OVERRIDE_DPIR(x)           (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_DPIR_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_DPIR_MASK)
/*! @} */

/*! @name TIMER0 - TIMER0 register */
/*! @{ */
#define USBDCD_TIMER0_TUNITCON_MASK              (0xFFFU)
#define USBDCD_TIMER0_TUNITCON_SHIFT             (0U)
#define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
#define USBDCD_TIMER0_TSEQ_INIT_MASK             (0x3FF0000U)
#define USBDCD_TIMER0_TSEQ_INIT_SHIFT            (16U)
#define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
/*! @} */

/*! @name TIMER1 - TIMER1 register */
/*! @{ */
#define USBDCD_TIMER1_TVDPSRC_ON_MASK            (0x3FFU)
#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           (0U)
#define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
#define USBDCD_TIMER1_TDCD_DBNC_MASK             (0x3FF0000U)
#define USBDCD_TIMER1_TDCD_DBNC_SHIFT            (16U)
#define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
/*! @} */

/*! @name TIMER2_BC11 - TIMER2_BC11 register */
/*! @{ */
#define USBDCD_TIMER2_BC11_CHECK_DM_MASK         (0xFU)
#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT        (0U)
#define USBDCD_TIMER2_BC11_CHECK_DM(x)           (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK      (0x3FF0000U)
#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT     (16U)
#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x)        (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
/*! @} */

/*! @name TIMER2_BC12 - TIMER2_BC12 register */
/*! @{ */
#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK       (0x3FFU)
#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT      (0U)
#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x)         (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK  (0x3FF0000U)
#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)    (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USBDCD_Register_Masks */


/* USBDCD - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__USBDCD base address */
#define CONNECTIVITY__USBDCD_BASE                (0x5B100000u)
/** Peripheral CONNECTIVITY__USBDCD base pointer */
#define CONNECTIVITY__USBDCD                     ((USBDCD_Type *)CONNECTIVITY__USBDCD_BASE)
/** Array initializer of USBDCD peripheral base addresses */
#define USBDCD_BASE_ADDRS                        { CONNECTIVITY__USBDCD_BASE }
/** Array initializer of USBDCD peripheral base pointers */
#define USBDCD_BASE_PTRS                         { CONNECTIVITY__USBDCD }

/*!
 * @}
 */ /* end of group USBDCD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USDHC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
 * @{
 */

/** USDHC - Register Layout Typedef */
typedef struct {
  __IO uint32_t DS_ADDR;                           /**< DMA System Address, offset: 0x0 */
  __IO uint32_t BLK_ATT;                           /**< Block Attributes, offset: 0x4 */
  __IO uint32_t CMD_ARG;                           /**< Command Argument, offset: 0x8 */
  __IO uint32_t CMD_XFR_TYP;                       /**< Command Transfer Type, offset: 0xC */
  __I  uint32_t CMD_RSP0;                          /**< Command Response0, offset: 0x10 */
  __I  uint32_t CMD_RSP1;                          /**< Command Response1, offset: 0x14 */
  __I  uint32_t CMD_RSP2;                          /**< Command Response2, offset: 0x18 */
  __I  uint32_t CMD_RSP3;                          /**< Command Response3, offset: 0x1C */
  __IO uint32_t DATA_BUFF_ACC_PORT;                /**< Data Buffer Access Port, offset: 0x20 */
  __I  uint32_t PRES_STATE;                        /**< Present State, offset: 0x24 */
  __IO uint32_t PROT_CTRL;                         /**< Protocol Control, offset: 0x28 */
  __IO uint32_t SYS_CTRL;                          /**< System Control, offset: 0x2C */
  __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x30 */
  __IO uint32_t INT_STATUS_EN;                     /**< Interrupt Status Enable, offset: 0x34 */
  __IO uint32_t INT_SIGNAL_EN;                     /**< Interrupt Signal Enable, offset: 0x38 */
  __I  uint32_t AUTOCMD12_ERR_STATUS;              /**< Auto CMD12 Error Status, offset: 0x3C */
  __I  uint32_t HOST_CTRL_CAP;                     /**< Host Controller Capabilities, offset: 0x40 */
  __IO uint32_t WTMK_LVL;                          /**< Watermark Level, offset: 0x44 */
  __IO uint32_t MIX_CTRL;                          /**< Mixer Control, offset: 0x48 */
       uint8_t RESERVED_0[4];
  __O  uint32_t FORCE_EVENT;                       /**< Force Event, offset: 0x50 */
  __I  uint32_t ADMA_ERR_STATUS;                   /**< ADMA Error Status Register, offset: 0x54 */
  __IO uint32_t ADMA_SYS_ADDR;                     /**< ADMA System Address, offset: 0x58 */
       uint8_t RESERVED_1[20];
  __IO uint32_t STROBE_DLL_CTRL;                   /**< Strobe DLL Control, offset: 0x70 */
  __I  uint32_t STROBE_DLL_STATUS;                 /**< Strobe DLL Status, offset: 0x74 */
       uint8_t RESERVED_2[72];
  __IO uint32_t VEND_SPEC;                         /**< Vendor Specific Register, offset: 0xC0 */
  __IO uint32_t MMC_BOOT;                          /**< MMC Boot Register, offset: 0xC4 */
  __IO uint32_t VEND_SPEC2;                        /**< Vendor Specific 2 Register, offset: 0xC8 */
       uint8_t RESERVED_3[48];
  __I  uint32_t HOST_CTRL_VER;                     /**< Host Controller Version, offset: 0xFC */
} USDHC_Type;

/* ----------------------------------------------------------------------------
   -- USDHC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USDHC_Register_Masks USDHC Register Masks
 * @{
 */

/*! @name DS_ADDR - DMA System Address */
/*! @{ */
#define USDHC_DS_ADDR_DS_ADDR_MASK               (0xFFFFFFFCU)
#define USDHC_DS_ADDR_DS_ADDR_SHIFT              (2U)
#define USDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
/*! @} */

/*! @name BLK_ATT - Block Attributes */
/*! @{ */
#define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
#define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
/*! BLKSIZE - Block Size
 *  0b1000000000000..4096 Bytes
 *  0b0100000000000..2048 Bytes
 *  0b0001000000000..512 Bytes
 *  0b0000111111111..511 Bytes
 *  0b0000000000100..4 Bytes
 *  0b0000000000011..3 Bytes
 *  0b0000000000010..2 Bytes
 *  0b0000000000001..1 Byte
 *  0b0000000000000..No data transfer
 */
#define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
#define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
#define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
/*! BLKCNT - Block Count
 *  0b1111111111111111..65535 blocks
 *  0b0000000000000010..2 blocks
 *  0b0000000000000001..1 block
 *  0b0000000000000000..Stop Count
 */
#define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
/*! @} */

/*! @name CMD_ARG - Command Argument */
/*! @{ */
#define USDHC_CMD_ARG_CMDARG_MASK                (0xFFFFFFFFU)
#define USDHC_CMD_ARG_CMDARG_SHIFT               (0U)
#define USDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
/*! @} */

/*! @name CMD_XFR_TYP - Command Transfer Type */
/*! @{ */
#define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
/*! RSPTYP - Response Type Select
 *  0b00..No Response
 *  0b01..Response Length 136
 *  0b10..Response Length 48
 *  0b11..Response Length 48, check Busy after response
 */
#define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
#define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
/*! CCCEN - Command CRC Check Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
#define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
#define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
/*! CICEN - Command Index Check Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
#define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
/*! DPSEL - Data Present Select
 *  0b1..Data Present
 *  0b0..No Data Present
 */
#define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
#define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
/*! CMDTYP - Command Type
 *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
 *  0b10..Resume CMD52 for writing Function Select in CCCR
 *  0b01..Suspend CMD52 for writing Bus Suspend in CCCR
 *  0b00..Normal Other commands
 */
#define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
#define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
#define USDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
/*! @} */

/*! @name CMD_RSP0 - Command Response0 */
/*! @{ */
#define USDHC_CMD_RSP0_CMDRSP0_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP0_CMDRSP0_SHIFT             (0U)
#define USDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
/*! @} */

/*! @name CMD_RSP1 - Command Response1 */
/*! @{ */
#define USDHC_CMD_RSP1_CMDRSP1_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP1_CMDRSP1_SHIFT             (0U)
#define USDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/*! @} */

/*! @name CMD_RSP2 - Command Response2 */
/*! @{ */
#define USDHC_CMD_RSP2_CMDRSP2_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP2_CMDRSP2_SHIFT             (0U)
#define USDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/*! @} */

/*! @name CMD_RSP3 - Command Response3 */
/*! @{ */
#define USDHC_CMD_RSP3_CMDRSP3_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP3_CMDRSP3_SHIFT             (0U)
#define USDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
/*! @} */

/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
/*! @{ */
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    (0xFFFFFFFFU)
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
/*! @} */

/*! @name PRES_STATE - Present State */
/*! @{ */
#define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
#define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
/*! CIHB - Command Inhibit (CMD)
 *  0b1..Cannot issue command
 *  0b0..Can issue command using only CMD line
 */
#define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
#define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
#define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
/*! CDIHB - Command Inhibit (DATA)
 *  0b1..Cannot issue command which uses the DATA line
 *  0b0..Can issue command which uses the DATA line
 */
#define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
#define USDHC_PRES_STATE_DLA_MASK                (0x4U)
#define USDHC_PRES_STATE_DLA_SHIFT               (2U)
/*! DLA - Data Line Active
 *  0b1..DATA Line Active
 *  0b0..DATA Line Inactive
 */
#define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
#define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
#define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
/*! SDSTB - SD Clock Stable
 *  0b1..Clock is stable.
 *  0b0..Clock is changing frequency and not stable.
 */
#define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
#define USDHC_PRES_STATE_IPGOFF_MASK             (0x10U)
#define USDHC_PRES_STATE_IPGOFF_SHIFT            (4U)
/*! IPGOFF - IPG_CLK Gated Off Internally
 *  0b1..IPG_CLK is gated off.
 *  0b0..IPG_CLK is active.
 */
#define USDHC_PRES_STATE_IPGOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
#define USDHC_PRES_STATE_HCKOFF_MASK             (0x20U)
#define USDHC_PRES_STATE_HCKOFF_SHIFT            (5U)
/*! HCKOFF - HCLK Gated Off Internally
 *  0b1..HCLK is gated off.
 *  0b0..HCLK is active.
 */
#define USDHC_PRES_STATE_HCKOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
#define USDHC_PRES_STATE_PEROFF_MASK             (0x40U)
#define USDHC_PRES_STATE_PEROFF_SHIFT            (6U)
/*! PEROFF - IPG_PERCLK Gated Off Internally
 *  0b1..IPG_PERCLK is gated off.
 *  0b0..IPG_PERCLK is active.
 */
#define USDHC_PRES_STATE_PEROFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
#define USDHC_PRES_STATE_SDOFF_MASK              (0x80U)
#define USDHC_PRES_STATE_SDOFF_SHIFT             (7U)
/*! SDOFF - SD Clock Gated Off Internally
 *  0b1..SD Clock is gated off.
 *  0b0..SD Clock is active.
 */
#define USDHC_PRES_STATE_SDOFF(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
#define USDHC_PRES_STATE_WTA_MASK                (0x100U)
#define USDHC_PRES_STATE_WTA_SHIFT               (8U)
/*! WTA - Write Transfer Active
 *  0b1..Transferring data
 *  0b0..No valid data
 */
#define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
#define USDHC_PRES_STATE_RTA_MASK                (0x200U)
#define USDHC_PRES_STATE_RTA_SHIFT               (9U)
/*! RTA - Read Transfer Active
 *  0b1..Transferring data
 *  0b0..No valid data
 */
#define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
#define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
#define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
/*! BWEN - Buffer Write Enable
 *  0b1..Write enable
 *  0b0..Write disable
 */
#define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
#define USDHC_PRES_STATE_BREN_MASK               (0x800U)
#define USDHC_PRES_STATE_BREN_SHIFT              (11U)
/*! BREN - Buffer Read Enable
 *  0b1..Read enable
 *  0b0..Read disable
 */
#define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
#define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
#define USDHC_PRES_STATE_CINST_SHIFT             (16U)
/*! CINST - Card Inserted
 *  0b1..Card Inserted
 *  0b0..Power on Reset or No Card
 */
#define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
#define USDHC_PRES_STATE_CDPL_MASK               (0x40000U)
#define USDHC_PRES_STATE_CDPL_SHIFT              (18U)
/*! CDPL - Card Detect Pin Level
 *  0b1..Card present (CD_B = 0)
 *  0b0..No card present (CD_B = 1)
 */
#define USDHC_PRES_STATE_CDPL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
#define USDHC_PRES_STATE_WPSPL_MASK              (0x80000U)
#define USDHC_PRES_STATE_WPSPL_SHIFT             (19U)
/*! WPSPL - Write Protect Switch Pin Level
 *  0b1..Write enabled (WP = 0)
 *  0b0..Write protected (WP = 1)
 */
#define USDHC_PRES_STATE_WPSPL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
#define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
#define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
#define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
#define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
#define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
/*! DLSL - DATA[7:0] Line Signal Level
 *  0b00000111..Data 7 line signal level
 *  0b00000110..Data 6 line signal level
 *  0b00000101..Data 5 line signal level
 *  0b00000100..Data 4 line signal level
 *  0b00000011..Data 3 line signal level
 *  0b00000010..Data 2 line signal level
 *  0b00000001..Data 1 line signal level
 *  0b00000000..Data 0 line signal level
 */
#define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
/*! @} */

/*! @name PROT_CTRL - Protocol Control */
/*! @{ */
#define USDHC_PROT_CTRL_LCTL_MASK                (0x1U)
#define USDHC_PROT_CTRL_LCTL_SHIFT               (0U)
/*! LCTL - LED Control
 *  0b1..LED on
 *  0b0..LED off
 */
#define USDHC_PROT_CTRL_LCTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
#define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
#define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
/*! DTW - Data Transfer Width
 *  0b10..8-bit mode
 *  0b01..4-bit mode
 *  0b00..1-bit mode
 *  0b11..Reserved
 */
#define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
#define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
#define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
/*! D3CD - DATA3 as Card Detection Pin
 *  0b1..DATA3 as Card Detection Pin
 *  0b0..DATA3 does not monitor Card Insertion
 */
#define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
#define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
#define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
/*! EMODE - Endian Mode
 *  0b00..Big Endian Mode
 *  0b01..Half Word Big Endian Mode
 *  0b10..Little Endian Mode
 *  0b11..Reserved
 */
#define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
#define USDHC_PROT_CTRL_CDTL_MASK                (0x40U)
#define USDHC_PROT_CTRL_CDTL_SHIFT               (6U)
/*! CDTL - Card Detect Test Level
 *  0b1..Card Detect Test Level is 1, card inserted
 *  0b0..Card Detect Test Level is 0, no card inserted
 */
#define USDHC_PROT_CTRL_CDTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
#define USDHC_PROT_CTRL_CDSS_MASK                (0x80U)
#define USDHC_PROT_CTRL_CDSS_SHIFT               (7U)
/*! CDSS - Card Detect Signal Selection
 *  0b1..Card Detection Test Level is selected (for test purpose).
 *  0b0..Card Detection Level is selected (for normal purpose).
 */
#define USDHC_PROT_CTRL_CDSS(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
#define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
#define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
/*! DMASEL - DMA Select
 *  0b00..No DMA or Simple DMA is selected
 *  0b01..ADMA1 is selected
 *  0b10..ADMA2 is selected
 *  0b11..reserved
 */
#define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
#define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
#define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
/*! SABGREQ - Stop At Block Gap Request
 *  0b1..Stop
 *  0b0..Transfer
 */
#define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
#define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
#define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
/*! CREQ - Continue Request
 *  0b1..Restart
 *  0b0..No effect
 */
#define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
#define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
#define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
/*! RWCTL - Read Wait Control
 *  0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set
 *  0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set
 */
#define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
#define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
#define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
/*! IABG - Interrupt At Block Gap
 *  0b1..Enabled
 *  0b0..Disabled
 */
#define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
#define USDHC_PROT_CTRL_RD_WAIT_POINT_MASK       (0xE00000U)
#define USDHC_PROT_CTRL_RD_WAIT_POINT_SHIFT      (21U)
#define USDHC_PROT_CTRL_RD_WAIT_POINT(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_WAIT_POINT_SHIFT)) & USDHC_PROT_CTRL_RD_WAIT_POINT_MASK)
#define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
#define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
/*! WECINT - Wakeup Event Enable On Card Interrupt
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
#define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
#define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
/*! WECINS - Wakeup Event Enable On SD Card Insertion
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
#define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
#define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
/*! WECRM - Wakeup Event Enable On SD Card Removal
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
/*! NON_EXACT_BLK_RD - NON_EXACT_BLK_RD
 *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
 *  0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read.
 */
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
#define USDHC_PROT_CTRL_RD_NO8CLK_EN_MASK        (0x80000000U)
#define USDHC_PROT_CTRL_RD_NO8CLK_EN_SHIFT       (31U)
/*! RD_NO8CLK_EN - RD_NO8CLK_EN
 *  0b1..S/W RD_DONE_NO_8CLK is enabled.
 *  0b0..Disable S/W RD_DONE_NO_8CLK, uSHDC determines if 8 clocks are needed automatically.
 */
#define USDHC_PROT_CTRL_RD_NO8CLK_EN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_NO8CLK_EN_SHIFT)) & USDHC_PROT_CTRL_RD_NO8CLK_EN_MASK)
/*! @} */

/*! @name SYS_CTRL - System Control */
/*! @{ */
#define USDHC_SYS_CTRL_IPGEN_MASK                (0x1U)
#define USDHC_SYS_CTRL_IPGEN_SHIFT               (0U)
#define USDHC_SYS_CTRL_IPGEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPGEN_SHIFT)) & USDHC_SYS_CTRL_IPGEN_MASK)
#define USDHC_SYS_CTRL_HCKEN_MASK                (0x2U)
#define USDHC_SYS_CTRL_HCKEN_SHIFT               (1U)
#define USDHC_SYS_CTRL_HCKEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_HCKEN_SHIFT)) & USDHC_SYS_CTRL_HCKEN_MASK)
#define USDHC_SYS_CTRL_PEREN_MASK                (0x4U)
#define USDHC_SYS_CTRL_PEREN_SHIFT               (2U)
#define USDHC_SYS_CTRL_PEREN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_PEREN_SHIFT)) & USDHC_SYS_CTRL_PEREN_MASK)
#define USDHC_SYS_CTRL_SDCLKEN_MASK              (0x8U)
#define USDHC_SYS_CTRL_SDCLKEN_SHIFT             (3U)
#define USDHC_SYS_CTRL_SDCLKEN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKEN_SHIFT)) & USDHC_SYS_CTRL_SDCLKEN_MASK)
#define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
#define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
/*! DVS - Divisor
 *  0b0000..Divide-by-1
 *  0b0001..Divide-by-2
 *  0b1110..Divide-by-15
 *  0b1111..Divide-by-16
 */
#define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
#define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
#define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
#define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
#define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
#define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
#define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
#define USDHC_SYS_CTRL_RST_STROBE_FIFO_MASK      (0x200000U)
#define USDHC_SYS_CTRL_RST_STROBE_FIFO_SHIFT     (21U)
#define USDHC_SYS_CTRL_RST_STROBE_FIFO(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RST_STROBE_FIFO_SHIFT)) & USDHC_SYS_CTRL_RST_STROBE_FIFO_MASK)
#define USDHC_SYS_CTRL_RST_FIFO_MASK             (0x400000U)
#define USDHC_SYS_CTRL_RST_FIFO_SHIFT            (22U)
#define USDHC_SYS_CTRL_RST_FIFO(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RST_FIFO_SHIFT)) & USDHC_SYS_CTRL_RST_FIFO_MASK)
#define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
#define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
#define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
#define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
/*! RSTA - Software Reset For ALL
 *  0b1..Reset
 *  0b0..No Reset
 */
#define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
#define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
#define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
/*! RSTC - Software Reset For CMD Line
 *  0b1..Reset
 *  0b0..No Reset
 */
#define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
#define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
#define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
/*! RSTD - Software Reset For DATA Line
 *  0b1..Reset
 *  0b0..No Reset
 */
#define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
#define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
#define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
#define USDHC_SYS_CTRL_INITA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
/*! @} */

/*! @name INT_STATUS - Interrupt Status */
/*! @{ */
#define USDHC_INT_STATUS_CC_MASK                 (0x1U)
#define USDHC_INT_STATUS_CC_SHIFT                (0U)
/*! CC - Command Complete
 *  0b1..Command complete
 *  0b0..Command not complete
 */
#define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
#define USDHC_INT_STATUS_TC_MASK                 (0x2U)
#define USDHC_INT_STATUS_TC_SHIFT                (1U)
/*! TC - Transfer Complete
 *  0b1..Transfer complete
 *  0b0..Transfer not complete
 */
#define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
#define USDHC_INT_STATUS_BGE_MASK                (0x4U)
#define USDHC_INT_STATUS_BGE_SHIFT               (2U)
/*! BGE - Block Gap Event
 *  0b1..Transaction stopped at block gap
 *  0b0..No block gap event
 */
#define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
#define USDHC_INT_STATUS_DINT_MASK               (0x8U)
#define USDHC_INT_STATUS_DINT_SHIFT              (3U)
/*! DINT - DMA Interrupt
 *  0b1..DMA Interrupt is generated
 *  0b0..No DMA Interrupt
 */
#define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
#define USDHC_INT_STATUS_BWR_MASK                (0x10U)
#define USDHC_INT_STATUS_BWR_SHIFT               (4U)
/*! BWR - Buffer Write Ready
 *  0b1..Ready to write buffer:
 *  0b0..Not ready to write buffer
 */
#define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
#define USDHC_INT_STATUS_BRR_MASK                (0x20U)
#define USDHC_INT_STATUS_BRR_SHIFT               (5U)
/*! BRR - Buffer Read Ready
 *  0b1..Ready to read buffer
 *  0b0..Not ready to read buffer
 */
#define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
#define USDHC_INT_STATUS_CINS_MASK               (0x40U)
#define USDHC_INT_STATUS_CINS_SHIFT              (6U)
/*! CINS - Card Insertion
 *  0b1..Card inserted
 *  0b0..Card state unstable or removed
 */
#define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
#define USDHC_INT_STATUS_CRM_MASK                (0x80U)
#define USDHC_INT_STATUS_CRM_SHIFT               (7U)
/*! CRM - Card Removal
 *  0b1..Card removed
 *  0b0..Card state unstable or inserted
 */
#define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
#define USDHC_INT_STATUS_CINT_MASK               (0x100U)
#define USDHC_INT_STATUS_CINT_SHIFT              (8U)
/*! CINT - Card Interrupt
 *  0b1..Generate Card Interrupt
 *  0b0..No Card Interrupt
 */
#define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
#define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
#define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
/*! CTOE - Command Timeout Error
 *  0b1..Time out
 *  0b0..No Error
 */
#define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
#define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
#define USDHC_INT_STATUS_CCE_SHIFT               (17U)
/*! CCE - Command CRC Error
 *  0b1..CRC Error Generated.
 *  0b0..No Error
 */
#define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
#define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
#define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
/*! CEBE - Command End Bit Error
 *  0b1..End Bit Error Generated
 *  0b0..No Error
 */
#define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
#define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
#define USDHC_INT_STATUS_CIE_SHIFT               (19U)
/*! CIE - Command Index Error
 *  0b1..Error
 *  0b0..No Error
 */
#define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
#define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
#define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
/*! DTOE - Data Timeout Error
 *  0b1..Time out
 *  0b0..No Error
 */
#define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
#define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
#define USDHC_INT_STATUS_DCE_SHIFT               (21U)
/*! DCE - Data CRC Error
 *  0b1..Error
 *  0b0..No Error
 */
#define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
#define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
#define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
/*! DEBE - Data End Bit Error
 *  0b1..Error
 *  0b0..No Error
 */
#define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
#define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
#define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
/*! AC12E - Auto CMD12 Error
 *  0b1..Error
 *  0b0..No Error
 */
#define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
#define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
#define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
/*! DMAE - DMA Error
 *  0b1..Error
 *  0b0..No Error
 */
#define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
/*! @} */

/*! @name INT_STATUS_EN - Interrupt Status Enable */
/*! @{ */
#define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
#define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
/*! CCSEN - Command Complete Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
#define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
#define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
/*! TCSEN - Transfer Complete Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
#define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
#define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
/*! BGESEN - Block Gap Event Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
#define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
/*! DINTSEN - DMA Interrupt Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
#define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
/*! BWRSEN - Buffer Write Ready Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
#define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
/*! BRRSEN - Buffer Read Ready Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
#define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
/*! CINSSEN - Card Insertion Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
#define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
/*! CRMSEN - Card Removal Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
#define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
/*! CINTSEN - Card Interrupt Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
#define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
/*! CTOESEN - Command Timeout Error Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
#define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
#define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
/*! CCESEN - Command CRC Error Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
#define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
/*! CEBESEN - Command End Bit Error Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
#define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
#define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
/*! CIESEN - Command Index Error Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
#define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
/*! DTOESEN - Data Timeout Error Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
#define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
#define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
/*! DCESEN - Data CRC Error Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
#define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
/*! DEBESEN - Data End Bit Error Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
#define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
/*! AC12ESEN - Auto CMD12 Error Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
#define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
/*! DMAESEN - DMA Error Status Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
/*! @} */

/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
/*! @{ */
#define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
/*! CCIEN - Command Complete Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
#define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
/*! TCIEN - Transfer Complete Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
/*! BGEIEN - Block Gap Event Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
/*! DINTIEN - DMA Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
/*! BWRIEN - Buffer Write Ready Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
/*! BRRIEN - Buffer Read Ready Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
/*! CINSIEN - Card Insertion Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
/*! CRMIEN - Card Removal Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
/*! CINTIEN - Card Interrupt Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
/*! CTOEIEN - Command Timeout Error Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
/*! CCEIEN - Command CRC Error Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
/*! CEBEIEN - Command End Bit Error Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
/*! CIEIEN - Command Index Error Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
/*! DTOEIEN - Data Timeout Error Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
/*! DCEIEN - Data CRC Error Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
/*! DEBEIEN - Data End Bit Error Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
/*! AC12EIEN - Auto CMD12 Error Interrupt Enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
/*! DMAEIEN - DMA Error Interrupt Enable
 *  0b1..Enable
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
/*! @} */

/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
/*! @{ */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
/*! AC12NE - Auto CMD12 Not Executed
 *  0b1..Not executed
 *  0b0..Executed
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
/*! AC12TOE - Auto CMD12 / 23 Timeout Error
 *  0b1..Time out
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x4U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
/*! AC12EBE - Auto CMD12 / 23 End Bit Error
 *  0b1..End Bit Error Generated
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x8U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (3U)
/*! AC12CE - Auto CMD12 / 23 CRC Error
 *  0b1..CRC Error Met in Auto CMD12/23 Response
 *  0b0..No CRC error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
/*! AC12IE - Auto CMD12 / 23 Index Error
 *  0b1..Error, the CMD index in response is not CMD12/23
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error
 *  0b1..Not Issued
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
/*! @} */

/*! @name HOST_CTRL_CAP - Host Controller Capabilities */
/*! @{ */
#define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
#define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
/*! MBL - Max Block Length
 *  0b000..512 bytes
 *  0b001..1024 bytes
 *  0b010..2048 bytes
 *  0b011..4096 bytes
 */
#define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
#define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
/*! ADMAS - ADMA Support
 *  0b1..Advanced DMA Supported
 *  0b0..Advanced DMA Not supported
 */
#define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
#define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
#define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
/*! HSS - High Speed Support
 *  0b1..High Speed Supported
 *  0b0..High Speed Not Supported
 */
#define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
#define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
/*! DMAS - DMA Support
 *  0b1..DMA Supported
 *  0b0..DMA not supported
 */
#define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
#define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
#define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
/*! SRS - Suspend / Resume Support
 *  0b1..Supported
 *  0b0..Not supported
 */
#define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
#define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
#define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
/*! VS33 - Voltage Support 3.3V
 *  0b1..3.3V supported
 *  0b0..3.3V not supported
 */
#define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
#define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
#define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
/*! VS30 - Voltage Support 3.0 V
 *  0b1..3.0V supported
 *  0b0..3.0V not supported
 */
#define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
#define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
#define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
/*! VS18 - Voltage Support 1.8 V
 *  0b1..1.8V supported
 *  0b0..1.8V not supported
 */
#define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
/*! @} */

/*! @name WTMK_LVL - Watermark Level */
/*! @{ */
#define USDHC_WTMK_LVL_RD_WML_MASK               (0xFFU)
#define USDHC_WTMK_LVL_RD_WML_SHIFT              (0U)
#define USDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
#define USDHC_WTMK_LVL_WR_WML_MASK               (0xFF0000U)
#define USDHC_WTMK_LVL_WR_WML_SHIFT              (16U)
#define USDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
/*! @} */

/*! @name MIX_CTRL - Mixer Control */
/*! @{ */
#define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
#define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
/*! DMAEN - DMA Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
#define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
#define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
/*! BCEN - Block Count Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
#define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
#define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
/*! AC12EN - Auto CMD12 Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
#define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
#define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
#define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
#define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
#define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
/*! DTDSEL - Data Transfer Direction Select
 *  0b1..Read (Card to Host)
 *  0b0..Write (Host to Card)
 */
#define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
#define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
#define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
/*! MSBSEL - Multi / Single Block Select
 *  0b1..Multiple Blocks
 *  0b0..Single Block
 */
#define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
#define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
#define USDHC_MIX_CTRL_NIBBLE_POS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
#define USDHC_MIX_CTRL_AC23EN_MASK               (0x80U)
#define USDHC_MIX_CTRL_AC23EN_SHIFT              (7U)
#define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
#define USDHC_MIX_CTRL_HS400_MODE_MASK           (0x4000000U)
#define USDHC_MIX_CTRL_HS400_MODE_SHIFT          (26U)
#define USDHC_MIX_CTRL_HS400_MODE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)
#define USDHC_MIX_CTRL_AC12_RD_POINT_MASK        (0x20000000U)
#define USDHC_MIX_CTRL_AC12_RD_POINT_SHIFT       (29U)
/*! AC12_RD_POINT - AC12_RD_POINT
 *  0b1..Send Auto CMD12 8 cycles after CRC is checked successfully
 *  0b0..Send Auto CMD12 right after CRC is checked successfully
 */
#define USDHC_MIX_CTRL_AC12_RD_POINT(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12_RD_POINT_SHIFT)) & USDHC_MIX_CTRL_AC12_RD_POINT_MASK)
#define USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG_MASK     (0x40000000U)
#define USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG_SHIFT    (30U)
#define USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG_SHIFT)) & USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG_MASK)
#define USDHC_MIX_CTRL_CMD_DMY_EN_MASK           (0x80000000U)
#define USDHC_MIX_CTRL_CMD_DMY_EN_SHIFT          (31U)
#define USDHC_MIX_CTRL_CMD_DMY_EN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_CMD_DMY_EN_SHIFT)) & USDHC_MIX_CTRL_CMD_DMY_EN_MASK)
/*! @} */

/*! @name FORCE_EVENT - Force Event */
/*! @{ */
#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK        (0x1U)
#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       (0U)
#define USDHC_FORCE_EVENT_FEVTAC12NE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK       (0x2U)
#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      (1U)
#define USDHC_FORCE_EVENT_FEVTAC12TOE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK        (0x4U)
#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       (2U)
#define USDHC_FORCE_EVENT_FEVTAC12CE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK       (0x8U)
#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      (3U)
#define USDHC_FORCE_EVENT_FEVTAC12EBE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK        (0x10U)
#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       (4U)
#define USDHC_FORCE_EVENT_FEVTAC12IE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     (0x80U)
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    (7U)
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
#define USDHC_FORCE_EVENT_FEVTCTOE_MASK          (0x10000U)
#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT         (16U)
#define USDHC_FORCE_EVENT_FEVTCTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
#define USDHC_FORCE_EVENT_FEVTCCE_MASK           (0x20000U)
#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT          (17U)
#define USDHC_FORCE_EVENT_FEVTCCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
#define USDHC_FORCE_EVENT_FEVTCEBE_MASK          (0x40000U)
#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT         (18U)
#define USDHC_FORCE_EVENT_FEVTCEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
#define USDHC_FORCE_EVENT_FEVTCIE_MASK           (0x80000U)
#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT          (19U)
#define USDHC_FORCE_EVENT_FEVTCIE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
#define USDHC_FORCE_EVENT_FEVTDTOE_MASK          (0x100000U)
#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT         (20U)
#define USDHC_FORCE_EVENT_FEVTDTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
#define USDHC_FORCE_EVENT_FEVTDCE_MASK           (0x200000U)
#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT          (21U)
#define USDHC_FORCE_EVENT_FEVTDCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
#define USDHC_FORCE_EVENT_FEVTDEBE_MASK          (0x400000U)
#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT         (22U)
#define USDHC_FORCE_EVENT_FEVTDEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12E_MASK         (0x1000000U)
#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT        (24U)
#define USDHC_FORCE_EVENT_FEVTAC12E(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
#define USDHC_FORCE_EVENT_FEVTDMAE_MASK          (0x10000000U)
#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT         (28U)
#define USDHC_FORCE_EVENT_FEVTDMAE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
#define USDHC_FORCE_EVENT_FEVTCINT_MASK          (0x80000000U)
#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT         (31U)
#define USDHC_FORCE_EVENT_FEVTCINT(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
/*! @} */

/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */
/*! @{ */
#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK        (0x3U)
#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       (0U)
#define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
/*! ADMALME - ADMA Length Mismatch Error
 *  0b1..Error
 *  0b0..No Error
 */
#define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
/*! ADMADCE - ADMA Descriptor Error
 *  0b1..Error
 *  0b0..No Error
 */
#define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
/*! @} */

/*! @name ADMA_SYS_ADDR - ADMA System Address */
/*! @{ */
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        (0xFFFFFFFCU)
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       (2U)
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
/*! @} */

/*! @name STROBE_DLL_CTRL - Strobe DLL Control */
/*! @{ */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x38U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK (0x40U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT (6U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK (0x80U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT (7U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */

/*! @name STROBE_DLL_STATUS - Strobe DLL Status */
/*! @{ */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
/*! @} */

/*! @name VEND_SPEC - Vendor Specific Register */
/*! @{ */
#define USDHC_VEND_SPEC_VSELECT_MASK             (0x2U)
#define USDHC_VEND_SPEC_VSELECT_SHIFT            (1U)
/*! VSELECT - Voltage Selection
 *  0b1..Change the voltage to low voltage range, around 1.8 V
 *  0b0..Change the voltage to high voltage range, around 3.0 V
 */
#define USDHC_VEND_SPEC_VSELECT(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK     (0x4U)
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT    (2U)
/*! CONFLICT_CHK_EN - Conflict check enable.
 *  0b0..Conflict check disable
 *  0b1..Conflict check enable
 */
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
/*! AC12_WR_CHKBUSY_EN - AC12_WR_CHKBUSY_EN
 *  0b0..Do not check busy after auto CMD12 for write data packet
 *  0b1..Check busy after auto CMD12 for write data packet
 */
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
#define USDHC_VEND_SPEC_DAT3_CD_POL_MASK         (0x10U)
#define USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT        (4U)
/*! DAT3_CD_POL - DAT3_CD_POL
 *  0b0..Card detected when DATA3 is high.
 *  0b1..Card detected when DATA3 is low.
 */
#define USDHC_VEND_SPEC_DAT3_CD_POL(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT)) & USDHC_VEND_SPEC_DAT3_CD_POL_MASK)
#define USDHC_VEND_SPEC_CD_POL_MASK              (0x20U)
#define USDHC_VEND_SPEC_CD_POL_SHIFT             (5U)
/*! CD_POL - CD_POL
 *  0b0..CD_B pin is low active.
 *  0b1..CD_B pin is high active.
 */
#define USDHC_VEND_SPEC_CD_POL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CD_POL_SHIFT)) & USDHC_VEND_SPEC_CD_POL_MASK)
#define USDHC_VEND_SPEC_WP_POL_MASK              (0x40U)
#define USDHC_VEND_SPEC_WP_POL_SHIFT             (6U)
/*! WP_POL - WP_POL
 *  0b0..WP pin is high active.
 *  0b1..WP pin is low active.
 */
#define USDHC_VEND_SPEC_WP_POL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_WP_POL_SHIFT)) & USDHC_VEND_SPEC_WP_POL_MASK)
#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK     (0x80U)
#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT    (7U)
/*! CLKONJ_IN_ABORT - CLKONJ_IN_ABORT
 *  0b0..The CLK output is active when sending abort command while data is transmitting even if the internal FIFO is full (for read) or empty (for write).
 *  0b1..The CLK output is inactive when sending abort command while data is transmitting if the internal FIFO is full (for read) or empty (for write).
 */
#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT)) & USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK)
#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
/*! FRC_SDCLK_ON - FRC_SDCLK_ON
 *  0b0..CLK active or inactive is fully controlled by the hardware.
 *  0b1..Force CLK active.
 */
#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
#define USDHC_VEND_SPEC_AC12_ISNOT_ABORT_MASK    (0x200U)
#define USDHC_VEND_SPEC_AC12_ISNOT_ABORT_SHIFT   (9U)
/*! AC12_ISNOT_ABORT - AC12_ISNOT_ABORT
 *  0b0..Hardware treats the Auto CMD12 as abort command.
 *  0b1..Hardwae does not treat the Auto CMD12 as abort command.
 */
#define USDHC_VEND_SPEC_AC12_ISNOT_ABORT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_ISNOT_ABORT_SHIFT)) & USDHC_VEND_SPEC_AC12_ISNOT_ABORT_MASK)
#define USDHC_VEND_SPEC_DDREN_ACT_ATONCE_MASK    (0x400U)
#define USDHC_VEND_SPEC_DDREN_ACT_ATONCE_SHIFT   (10U)
/*! DDREN_ACT_ATONCE - DDREN_ACT_ATONCE
 *  0b0..DDR_EN setting becomes active only when the DATA and CMD line are idle.
 *  0b1..DDR_EN setting becomes active at once no matter what the state of the DATA and CMD line are.
 */
#define USDHC_VEND_SPEC_DDREN_ACT_ATONCE(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DDREN_ACT_ATONCE_SHIFT)) & USDHC_VEND_SPEC_DDREN_ACT_ATONCE_MASK)
#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK     (0x800U)
#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT    (11U)
/*! IPG_CLK_SOFT_EN - IPG_CLK Software Enable
 *  0b0..Gate off the IPG_CLK
 *  0b1..Enable the IPG_CLK
 */
#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK)
#define USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK        (0x1000U)
#define USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT       (12U)
/*! HCLK_SOFT_EN - AXI Clock Software Enable
 *  0b0..Gate off the AXI clock.
 *  0b1..Enable the AXI clock.
 */
#define USDHC_VEND_SPEC_HCLK_SOFT_EN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK)
#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK  (0x2000U)
#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT (13U)
/*! IPG_PERCLK_SOFT_EN - IPG_PERCLK Software Enable
 *  0b0..Gate off the IPG_PERCLK
 *  0b1..Enable the IPG_PERCLK
 */
#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK)
#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK    (0x4000U)
#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT   (14U)
/*! CARD_CLK_SOFT_EN - Card Clock Software Enable
 *  0b0..Gate off the sd_clk
 *  0b1..Enable the sd_clk
 */
#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK)
#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
/*! CRC_CHK_DIS - CRC Check Disable
 *  0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet
 *  0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet
 */
#define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
#define USDHC_VEND_SPEC_INT_ST_VAL_MASK          (0xFF0000U)
#define USDHC_VEND_SPEC_INT_ST_VAL_SHIFT         (16U)
#define USDHC_VEND_SPEC_INT_ST_VAL(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_INT_ST_VAL_SHIFT)) & USDHC_VEND_SPEC_INT_ST_VAL_MASK)
#define USDHC_VEND_SPEC_DBG_SEL_MASK             (0xF000000U)
#define USDHC_VEND_SPEC_DBG_SEL_SHIFT            (24U)
#define USDHC_VEND_SPEC_DBG_SEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DBG_SEL_SHIFT)) & USDHC_VEND_SPEC_DBG_SEL_MASK)
#define USDHC_VEND_SPEC_CMD_OE_PRE_EN_MASK       (0x10000000U)
#define USDHC_VEND_SPEC_CMD_OE_PRE_EN_SHIFT      (28U)
/*! CMD_OE_PRE_EN - CMD_OE_PRE_EN
 *  0b1..CMD_OE asserts one clock cycle before CMD_O
 *  0b0..CMD_OE and CMD_O assert at the same time
 */
#define USDHC_VEND_SPEC_CMD_OE_PRE_EN(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_OE_PRE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_OE_PRE_EN_MASK)
#define USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN_MASK  (0x20000000U)
#define USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN_SHIFT (29U)
/*! AC12_RD_CHKBUSY_EN - AC12_RD_CHKBUSY_EN
 *  0b1..Auto CMD12 to terminate multi-block read needs to check busy
 *  0b0..Auto CMD12 to terminate multi-block read doesn't need to check busy
 */
#define USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN_MASK)
#define USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ_MASK (0x40000000U)
#define USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ_SHIFT (30U)
#define USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ_SHIFT)) & USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ_MASK)
#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
/*! CMD_BYTE_EN - CMD_BYTE_EN
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
/*! @} */

/*! @name MMC_BOOT - MMC Boot Register */
/*! @{ */
#define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
/*! DTOCV_ACK - DTOCV_ACK
 *  0b0000..SDCLK x 2^14
 *  0b0001..SDCLK x 2^15
 *  0b0010..SDCLK x 2^16
 *  0b0011..SDCLK x 2^17
 *  0b0100..SDCLK x 2^18
 *  0b0101..SDCLK x 2^19
 *  0b0110..SDCLK x 2^20
 *  0b0111..SDCLK x 2^21
 *  0b1110..SDCLK x 2^28
 *  0b1111..SDCLK x 2^29
 */
#define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
#define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
/*! BOOT_ACK - BOOT_ACK
 *  0b0..No ack
 *  0b1..Ack
 */
#define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
#define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
/*! BOOT_MODE - BOOT_MODE
 *  0b0..Normal boot
 *  0b1..Alternative boot
 */
#define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
#define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
#define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
/*! BOOT_EN - BOOT_EN
 *  0b0..Fast boot disable
 *  0b1..Fast boot enable
 */
#define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
#define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
/*! DISABLE_TIME_OUT - Disable Time Out
 *  0b0..Enable time out
 *  0b1..Disable time out
 */
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
/*! @} */

/*! @name VEND_SPEC2 - Vendor Specific 2 Register */
/*! @{ */
#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK  (0x1U)
#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT (0U)
/*! SDR104_TIMING_DIS - SDR104_TIMING_DIS
 *  0b0..The timeout counter for Ncr changes to 80, Ncrc changes to 21.
 *  0b1..The timeout counter for Ncr changes to 72, Ncrc changes to 15.
 */
#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK)
#define USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK      (0x2U)
#define USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT     (1U)
/*! SDR104_OE_DIS - SDR104_OE_DIS
 *  0b0..Drive the CMD_OE / DATA_OE for one more clock cycle after the end bit.
 *  0b1..Stop to drive the CMD_OE / DATA_OE at once after driving the end bit.
 */
#define USDHC_VEND_SPEC2_SDR104_OE_DIS(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK)
#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK     (0x4U)
#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT    (2U)
/*! SDR104_NSD_DIS - SDR104_NSD_DIS
 *  0b0..Enable the interrupt window 9 cycles later after the end of the I/O abort command (or CMD12) is sent.
 *  0b1..Enable the interrupt window 5 cycles later after the end of the I/O abort command (or CMD12) is sent.
 */
#define USDHC_VEND_SPEC2_SDR104_NSD_DIS(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK)
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
/*! CARD_INT_D3_TEST - Card Interrupt Detection Test
 *  0b0..Check the card interrupt only when DATA3 is high.
 *  0b1..Check the card interrupt by ignoring the status of DATA3.
 */
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK (0x80U)
#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT (7U)
/*! CARD_INT_AUTO_CLR_DIS - CARD_INT_AUTO_CLR_DIS
 *  0b0..Card interrupt status bit (CINT) can be cleared when Card Interrupt status enable bit is 0.
 *  0b1..Card interrupt status bit (CINT) can only be cleared by writting a 1 to CINT bit.
 */
#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK)
#define USDHC_VEND_SPEC2_CMD_BUSY_TRAN_CPL_EN_MASK (0x100U)
#define USDHC_VEND_SPEC2_CMD_BUSY_TRAN_CPL_EN_SHIFT (8U)
/*! CMD_BUSY_TRAN_CPL_EN - CMD_BUSY_TRAN_CPL_EN
 *  0b0..Disable fix
 *  0b1..Enable fix
 */
#define USDHC_VEND_SPEC2_CMD_BUSY_TRAN_CPL_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CMD_BUSY_TRAN_CPL_EN_SHIFT)) & USDHC_VEND_SPEC2_CMD_BUSY_TRAN_CPL_EN_MASK)
#define USDHC_VEND_SPEC2_TEST_SYNC_EN_MASK       (0x200U)
#define USDHC_VEND_SPEC2_TEST_SYNC_EN_SHIFT      (9U)
#define USDHC_VEND_SPEC2_TEST_SYNC_EN(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TEST_SYNC_EN_SHIFT)) & USDHC_VEND_SPEC2_TEST_SYNC_EN_MASK)
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)
#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK     (0x2000U)
#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT    (13U)
#define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK)
#define USDHC_VEND_SPEC2_BUS_RST_MASK            (0x4000U)
#define USDHC_VEND_SPEC2_BUS_RST_SHIFT           (14U)
#define USDHC_VEND_SPEC2_BUS_RST(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK)
/*! @} */

/*! @name HOST_CTRL_VER - Host Controller Version */
/*! @{ */
#define USDHC_HOST_CTRL_VER_SVN_MASK             (0xFFU)
#define USDHC_HOST_CTRL_VER_SVN_SHIFT            (0U)
/*! SVN - Specification Version Number
 *  0b00000000..SD Host Specification Version 1.0.
 *  0b00000010..SD Host Specification Version 3.0, supports Test Event Register and ADMA.
 *  0b00000011-0b11111111..Reserved
 */
#define USDHC_HOST_CTRL_VER_SVN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_VER_SVN_SHIFT)) & USDHC_HOST_CTRL_VER_SVN_MASK)
#define USDHC_HOST_CTRL_VER_VVN_MASK             (0xFF00U)
#define USDHC_HOST_CTRL_VER_VVN_SHIFT            (8U)
/*! VVN - Vendor Version Number
 *  0b00000001..NXP uSDHC Version 1.1
 *  0b00000010..NXP uSDHC Version 2.0
 *  0b00000011..NXP uSDHC Version 3.0
 *  0b00000100..NXP uSDHC Version 4.0
 *  0b00000101..NXP uSDHC Version 5.0
 */
#define USDHC_HOST_CTRL_VER_VVN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_VER_VVN_SHIFT)) & USDHC_HOST_CTRL_VER_VVN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USDHC_Register_Masks */


/* USDHC - Peripheral instance base addresses */
/** Peripheral CONNECTIVITY__USDHC0 base address */
#define CONNECTIVITY__USDHC0_BASE                (0x5B010000u)
/** Peripheral CONNECTIVITY__USDHC0 base pointer */
#define CONNECTIVITY__USDHC0                     ((USDHC_Type *)CONNECTIVITY__USDHC0_BASE)
/** Peripheral CONNECTIVITY__USDHC1 base address */
#define CONNECTIVITY__USDHC1_BASE                (0x5B020000u)
/** Peripheral CONNECTIVITY__USDHC1 base pointer */
#define CONNECTIVITY__USDHC1                     ((USDHC_Type *)CONNECTIVITY__USDHC1_BASE)
/** Peripheral CONNECTIVITY__USDHC2 base address */
#define CONNECTIVITY__USDHC2_BASE                (0x5B030000u)
/** Peripheral CONNECTIVITY__USDHC2 base pointer */
#define CONNECTIVITY__USDHC2                     ((USDHC_Type *)CONNECTIVITY__USDHC2_BASE)
/** Array initializer of USDHC peripheral base addresses */
#define USDHC_BASE_ADDRS                         { CONNECTIVITY__USDHC0_BASE, CONNECTIVITY__USDHC1_BASE, CONNECTIVITY__USDHC2_BASE }
/** Array initializer of USDHC peripheral base pointers */
#define USDHC_BASE_PTRS                          { CONNECTIVITY__USDHC0, CONNECTIVITY__USDHC1, CONNECTIVITY__USDHC2 }
/** Interrupt vectors for the USDHC peripheral type */
#define USDHC_IRQS                               { NotAvail_IRQn, CONNECTIVITY_USDHC0_INT_IRQn, CONNECTIVITY_USDHC1_INT_IRQn }

/*!
 * @}
 */ /* end of group USDHC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VPU_LPCG_AVSD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_AVSD_Peripheral_Access_Layer VPU_LPCG_AVSD Peripheral Access Layer
 * @{
 */

/** VPU_LPCG_AVSD - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_AVSD_0;                       /**< na, offset: 0x0 */
} VPU_LPCG_AVSD_Type;

/* ----------------------------------------------------------------------------
   -- VPU_LPCG_AVSD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_AVSD_Register_Masks VPU_LPCG_AVSD Register Masks
 * @{
 */

/*! @name LPCG_AVSD_0 - na */
/*! @{ */
#define VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_16_MASK (0x1FFFFU)
#define VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_16_SHIFT (0U)
#define VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_16_SHIFT)) & VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_0_16_MASK)
#define VPU_LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN_MASK (0x20000U)
#define VPU_LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN_SHIFT (17U)
#define VPU_LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN_SHIFT)) & VPU_LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_SWEN_MASK)
#define VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_18_18_MASK (0x40000U)
#define VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_18_18_SHIFT (18U)
#define VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_18_18_SHIFT)) & VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_18_18_MASK)
#define VPU_LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP_MASK (0x80000U)
#define VPU_LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP_SHIFT (19U)
#define VPU_LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP_SHIFT)) & VPU_LPCG_AVSD_LPCG_AVSD_0_med_dec_mfd_avsd_clk_gated_STOP_MASK)
#define VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_20_31_MASK (0xFFF00000U)
#define VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_20_31_SHIFT (20U)
#define VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_20_31_SHIFT)) & VPU_LPCG_AVSD_LPCG_AVSD_0_LPCG_AVSD_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group VPU_LPCG_AVSD_Register_Masks */


/* VPU_LPCG_AVSD - Peripheral instance base addresses */
/** Peripheral VPU__LPCG_AVSD base address */
#define VPU__LPCG_AVSD_BASE                      (0x2D130000u)
/** Peripheral VPU__LPCG_AVSD base pointer */
#define VPU__LPCG_AVSD                           ((VPU_LPCG_AVSD_Type *)VPU__LPCG_AVSD_BASE)
/** Array initializer of VPU_LPCG_AVSD peripheral base addresses */
#define VPU_LPCG_AVSD_BASE_ADDRS                 { VPU__LPCG_AVSD_BASE }
/** Array initializer of VPU_LPCG_AVSD peripheral base pointers */
#define VPU_LPCG_AVSD_BASE_PTRS                  { VPU__LPCG_AVSD }

/*!
 * @}
 */ /* end of group VPU_LPCG_AVSD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VPU_LPCG_ENC0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_ENC0_Peripheral_Access_Layer VPU_LPCG_ENC0 Peripheral Access Layer
 * @{
 */

/** VPU_LPCG_ENC0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_ENC0_0;                       /**< na, offset: 0x0 */
} VPU_LPCG_ENC0_Type;

/* ----------------------------------------------------------------------------
   -- VPU_LPCG_ENC0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_ENC0_Register_Masks VPU_LPCG_ENC0 Register Masks
 * @{
 */

/*! @name LPCG_ENC0_0 - na */
/*! @{ */
#define VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_0_16_MASK (0x1FFFFU)
#define VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_0_16_SHIFT (0U)
#define VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_0_16_SHIFT)) & VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_0_16_MASK)
#define VPU_LPCG_ENC0_LPCG_ENC0_0_avehd_xbus_top_wrapper_sys_clk_SWEN_MASK (0x20000U)
#define VPU_LPCG_ENC0_LPCG_ENC0_0_avehd_xbus_top_wrapper_sys_clk_SWEN_SHIFT (17U)
#define VPU_LPCG_ENC0_LPCG_ENC0_0_avehd_xbus_top_wrapper_sys_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_ENC0_LPCG_ENC0_0_avehd_xbus_top_wrapper_sys_clk_SWEN_SHIFT)) & VPU_LPCG_ENC0_LPCG_ENC0_0_avehd_xbus_top_wrapper_sys_clk_SWEN_MASK)
#define VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_18_18_MASK (0x40000U)
#define VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_18_18_SHIFT (18U)
#define VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_18_18_SHIFT)) & VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_18_18_MASK)
#define VPU_LPCG_ENC0_LPCG_ENC0_0_avehd_xbus_top_wrapper_sys_clk_STOP_MASK (0x80000U)
#define VPU_LPCG_ENC0_LPCG_ENC0_0_avehd_xbus_top_wrapper_sys_clk_STOP_SHIFT (19U)
#define VPU_LPCG_ENC0_LPCG_ENC0_0_avehd_xbus_top_wrapper_sys_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_ENC0_LPCG_ENC0_0_avehd_xbus_top_wrapper_sys_clk_STOP_SHIFT)) & VPU_LPCG_ENC0_LPCG_ENC0_0_avehd_xbus_top_wrapper_sys_clk_STOP_MASK)
#define VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_20_31_MASK (0xFFF00000U)
#define VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_20_31_SHIFT (20U)
#define VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_20_31_SHIFT)) & VPU_LPCG_ENC0_LPCG_ENC0_0_LPCG_ENC0_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group VPU_LPCG_ENC0_Register_Masks */


/* VPU_LPCG_ENC0 - Peripheral instance base addresses */
/** Peripheral VPU__LPCG_ENC0 base address */
#define VPU__LPCG_ENC0_BASE                      (0x2D0D0000u)
/** Peripheral VPU__LPCG_ENC0 base pointer */
#define VPU__LPCG_ENC0                           ((VPU_LPCG_ENC0_Type *)VPU__LPCG_ENC0_BASE)
/** Array initializer of VPU_LPCG_ENC0 peripheral base addresses */
#define VPU_LPCG_ENC0_BASE_ADDRS                 { VPU__LPCG_ENC0_BASE }
/** Array initializer of VPU_LPCG_ENC0 peripheral base pointers */
#define VPU_LPCG_ENC0_BASE_PTRS                  { VPU__LPCG_ENC0 }

/*!
 * @}
 */ /* end of group VPU_LPCG_ENC0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VPU_LPCG_ENC1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_ENC1_Peripheral_Access_Layer VPU_LPCG_ENC1 Peripheral Access Layer
 * @{
 */

/** VPU_LPCG_ENC1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_ENC1_0;                       /**< na, offset: 0x0 */
} VPU_LPCG_ENC1_Type;

/* ----------------------------------------------------------------------------
   -- VPU_LPCG_ENC1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_ENC1_Register_Masks VPU_LPCG_ENC1 Register Masks
 * @{
 */

/*! @name LPCG_ENC1_0 - na */
/*! @{ */
#define VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_0_16_MASK (0x1FFFFU)
#define VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_0_16_SHIFT (0U)
#define VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_0_16_SHIFT)) & VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_0_16_MASK)
#define VPU_LPCG_ENC1_LPCG_ENC1_0_avehd_xbus_top_wrapper1_sys_clk_SWEN_MASK (0x20000U)
#define VPU_LPCG_ENC1_LPCG_ENC1_0_avehd_xbus_top_wrapper1_sys_clk_SWEN_SHIFT (17U)
#define VPU_LPCG_ENC1_LPCG_ENC1_0_avehd_xbus_top_wrapper1_sys_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_ENC1_LPCG_ENC1_0_avehd_xbus_top_wrapper1_sys_clk_SWEN_SHIFT)) & VPU_LPCG_ENC1_LPCG_ENC1_0_avehd_xbus_top_wrapper1_sys_clk_SWEN_MASK)
#define VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_18_18_MASK (0x40000U)
#define VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_18_18_SHIFT (18U)
#define VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_18_18_SHIFT)) & VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_18_18_MASK)
#define VPU_LPCG_ENC1_LPCG_ENC1_0_avehd_xbus_top_wrapper1_sys_clk_STOP_MASK (0x80000U)
#define VPU_LPCG_ENC1_LPCG_ENC1_0_avehd_xbus_top_wrapper1_sys_clk_STOP_SHIFT (19U)
#define VPU_LPCG_ENC1_LPCG_ENC1_0_avehd_xbus_top_wrapper1_sys_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_ENC1_LPCG_ENC1_0_avehd_xbus_top_wrapper1_sys_clk_STOP_SHIFT)) & VPU_LPCG_ENC1_LPCG_ENC1_0_avehd_xbus_top_wrapper1_sys_clk_STOP_MASK)
#define VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_20_31_MASK (0xFFF00000U)
#define VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_20_31_SHIFT (20U)
#define VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_20_31_SHIFT)) & VPU_LPCG_ENC1_LPCG_ENC1_0_LPCG_ENC1_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group VPU_LPCG_ENC1_Register_Masks */


/* VPU_LPCG_ENC1 - Peripheral instance base addresses */
/** Peripheral VPU__LPCG_ENC1 base address */
#define VPU__LPCG_ENC1_BASE                      (0x2D0E0000u)
/** Peripheral VPU__LPCG_ENC1 base pointer */
#define VPU__LPCG_ENC1                           ((VPU_LPCG_ENC1_Type *)VPU__LPCG_ENC1_BASE)
/** Array initializer of VPU_LPCG_ENC1 peripheral base addresses */
#define VPU_LPCG_ENC1_BASE_ADDRS                 { VPU__LPCG_ENC1_BASE }
/** Array initializer of VPU_LPCG_ENC1 peripheral base pointers */
#define VPU_LPCG_ENC1_BASE_PTRS                  { VPU__LPCG_ENC1 }

/*!
 * @}
 */ /* end of group VPU_LPCG_ENC1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VPU_LPCG_H264 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_H264_Peripheral_Access_Layer VPU_LPCG_H264 Peripheral Access Layer
 * @{
 */

/** VPU_LPCG_H264 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_H264_0;                       /**< na, offset: 0x0 */
} VPU_LPCG_H264_Type;

/* ----------------------------------------------------------------------------
   -- VPU_LPCG_H264 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_H264_Register_Masks VPU_LPCG_H264 Register Masks
 * @{
 */

/*! @name LPCG_H264_0 - na */
/*! @{ */
#define VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_16_MASK (0x1FFFFU)
#define VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_16_SHIFT (0U)
#define VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_16_SHIFT)) & VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_0_16_MASK)
#define VPU_LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN_MASK (0x20000U)
#define VPU_LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN_SHIFT (17U)
#define VPU_LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN_SHIFT)) & VPU_LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_SWEN_MASK)
#define VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_18_18_MASK (0x40000U)
#define VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_18_18_SHIFT (18U)
#define VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_18_18_SHIFT)) & VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_18_18_MASK)
#define VPU_LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP_MASK (0x80000U)
#define VPU_LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP_SHIFT (19U)
#define VPU_LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP_SHIFT)) & VPU_LPCG_H264_LPCG_H264_0_med_dec_mfd_h264_clk_gated_STOP_MASK)
#define VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_20_31_MASK (0xFFF00000U)
#define VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_20_31_SHIFT (20U)
#define VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_20_31_SHIFT)) & VPU_LPCG_H264_LPCG_H264_0_LPCG_H264_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group VPU_LPCG_H264_Register_Masks */


/* VPU_LPCG_H264 - Peripheral instance base addresses */
/** Peripheral VPU__LPCG_H264 base address */
#define VPU__LPCG_H264_BASE                      (0x2D100000u)
/** Peripheral VPU__LPCG_H264 base pointer */
#define VPU__LPCG_H264                           ((VPU_LPCG_H264_Type *)VPU__LPCG_H264_BASE)
/** Array initializer of VPU_LPCG_H264 peripheral base addresses */
#define VPU_LPCG_H264_BASE_ADDRS                 { VPU__LPCG_H264_BASE }
/** Array initializer of VPU_LPCG_H264 peripheral base pointers */
#define VPU_LPCG_H264_BASE_PTRS                  { VPU__LPCG_H264 }

/*!
 * @}
 */ /* end of group VPU_LPCG_H264_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VPU_LPCG_HIFI4 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_HIFI4_Peripheral_Access_Layer VPU_LPCG_HIFI4 Peripheral Access Layer
 * @{
 */

/** VPU_LPCG_HIFI4 - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_HIFI4_0;                      /**< na, offset: 0x0 */
} VPU_LPCG_HIFI4_Type;

/* ----------------------------------------------------------------------------
   -- VPU_LPCG_HIFI4 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_HIFI4_Register_Masks VPU_LPCG_HIFI4 Register Masks
 * @{
 */

/*! @name LPCG_HIFI4_0 - na */
/*! @{ */
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_0_16_MASK (0x1FFFFU)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_0_16_SHIFT (0U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_0_16_SHIFT)) & VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_0_16_MASK)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_adb_nic0nic1_mst_aclk_SWEN_AND_hifi_cluster_CLK_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN_MASK (0x20000U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_adb_nic0nic1_mst_aclk_SWEN_AND_hifi_cluster_CLK_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN_SHIFT (17U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_adb_nic0nic1_mst_aclk_SWEN_AND_hifi_cluster_CLK_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_adb_nic0nic1_mst_aclk_SWEN_AND_hifi_cluster_CLK_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN_SHIFT)) & VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_adb_nic0nic1_mst_aclk_SWEN_AND_hifi_cluster_CLK_adb_nic1nic0_slv_aclk_SWEN_AND_adb_nic0nic1_slv_aclk_SWEN_AND_adb_nic1nic0_mst_aclk_SWEN_MASK)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_18_18_MASK (0x40000U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_18_18_SHIFT (18U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_18_18_SHIFT)) & VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_18_18_MASK)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_adb_nic0nic1_mst_aclk_STOP_AND_hifi_cluster_CLK_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP_MASK (0x80000U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_adb_nic0nic1_mst_aclk_STOP_AND_hifi_cluster_CLK_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP_SHIFT (19U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_adb_nic0nic1_mst_aclk_STOP_AND_hifi_cluster_CLK_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_adb_nic0nic1_mst_aclk_STOP_AND_hifi_cluster_CLK_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP_SHIFT)) & VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_adb_nic0nic1_mst_aclk_STOP_AND_hifi_cluster_CLK_adb_nic1nic0_slv_aclk_STOP_AND_adb_nic0nic1_slv_aclk_STOP_AND_adb_nic1nic0_mst_aclk_STOP_MASK)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_20_20_MASK (0x100000U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_20_20_SHIFT (20U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_20_20_SHIFT)) & VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_20_20_MASK)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_CLK_SWEN_AND_hifi_cluster_CLK_hifi_mem_CLK_SWEN_MASK (0x200000U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_CLK_SWEN_AND_hifi_cluster_CLK_hifi_mem_CLK_SWEN_SHIFT (21U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_CLK_SWEN_AND_hifi_cluster_CLK_hifi_mem_CLK_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_CLK_SWEN_AND_hifi_cluster_CLK_hifi_mem_CLK_SWEN_SHIFT)) & VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_CLK_SWEN_AND_hifi_cluster_CLK_hifi_mem_CLK_SWEN_MASK)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_22_22_MASK (0x400000U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_22_22_SHIFT (22U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_22_22_SHIFT)) & VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_22_22_MASK)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_CLK_STOP_AND_hifi_cluster_CLK_hifi_mem_CLK_STOP_MASK (0x800000U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_CLK_STOP_AND_hifi_cluster_CLK_hifi_mem_CLK_STOP_SHIFT (23U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_CLK_STOP_AND_hifi_cluster_CLK_hifi_mem_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_CLK_STOP_AND_hifi_cluster_CLK_hifi_mem_CLK_STOP_SHIFT)) & VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_CLK_STOP_AND_hifi_cluster_CLK_hifi_mem_CLK_STOP_MASK)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_24_24_MASK (0x1000000U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_24_24_SHIFT (24U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_24_24_SHIFT)) & VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_24_24_MASK)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_PBCLK_SWEN_AND_hifi_cluster_CLK_hifi_core_ATCLK_SWEN_AND_hifi_cluster_CLK_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_cluster_CLK_hifi_dbg_atbm_clks_SWEN_AND_hifi_cluster_CLK_hifi_dbg_cti_cticlk_SWEN_AND_hifi_cluster_CLK_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_cluster_CLK_hifi_dbg_romtable_apb_clk_SWEN_MASK (0x2000000U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_PBCLK_SWEN_AND_hifi_cluster_CLK_hifi_core_ATCLK_SWEN_AND_hifi_cluster_CLK_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_cluster_CLK_hifi_dbg_atbm_clks_SWEN_AND_hifi_cluster_CLK_hifi_dbg_cti_cticlk_SWEN_AND_hifi_cluster_CLK_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_cluster_CLK_hifi_dbg_romtable_apb_clk_SWEN_SHIFT (25U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_PBCLK_SWEN_AND_hifi_cluster_CLK_hifi_core_ATCLK_SWEN_AND_hifi_cluster_CLK_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_cluster_CLK_hifi_dbg_atbm_clks_SWEN_AND_hifi_cluster_CLK_hifi_dbg_cti_cticlk_SWEN_AND_hifi_cluster_CLK_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_cluster_CLK_hifi_dbg_romtable_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_PBCLK_SWEN_AND_hifi_cluster_CLK_hifi_core_ATCLK_SWEN_AND_hifi_cluster_CLK_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_cluster_CLK_hifi_dbg_atbm_clks_SWEN_AND_hifi_cluster_CLK_hifi_dbg_cti_cticlk_SWEN_AND_hifi_cluster_CLK_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_cluster_CLK_hifi_dbg_romtable_apb_clk_SWEN_SHIFT)) & VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_PBCLK_SWEN_AND_hifi_cluster_CLK_hifi_core_ATCLK_SWEN_AND_hifi_cluster_CLK_hifi_dbg_apbs_pclkm_SWEN_AND_hifi_cluster_CLK_hifi_dbg_atbm_clks_SWEN_AND_hifi_cluster_CLK_hifi_dbg_cti_cticlk_SWEN_AND_hifi_cluster_CLK_hifi_dbg_cti_pclkdbg_SWEN_AND_hifi_cluster_CLK_hifi_dbg_romtable_apb_clk_SWEN_MASK)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_26_26_MASK (0x4000000U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_26_26_SHIFT (26U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_26_26_SHIFT)) & VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_26_26_MASK)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_PBCLK_STOP_AND_hifi_cluster_CLK_hifi_core_ATCLK_STOP_AND_hifi_cluster_CLK_hifi_dbg_apbs_pclkm_STOP_AND_hifi_cluster_CLK_hifi_dbg_atbm_clks_STOP_AND_hifi_cluster_CLK_hifi_dbg_cti_cticlk_STOP_AND_hifi_cluster_CLK_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_cluster_CLK_hifi_dbg_romtable_apb_clk_STOP_MASK (0x8000000U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_PBCLK_STOP_AND_hifi_cluster_CLK_hifi_core_ATCLK_STOP_AND_hifi_cluster_CLK_hifi_dbg_apbs_pclkm_STOP_AND_hifi_cluster_CLK_hifi_dbg_atbm_clks_STOP_AND_hifi_cluster_CLK_hifi_dbg_cti_cticlk_STOP_AND_hifi_cluster_CLK_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_cluster_CLK_hifi_dbg_romtable_apb_clk_STOP_SHIFT (27U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_PBCLK_STOP_AND_hifi_cluster_CLK_hifi_core_ATCLK_STOP_AND_hifi_cluster_CLK_hifi_dbg_apbs_pclkm_STOP_AND_hifi_cluster_CLK_hifi_dbg_atbm_clks_STOP_AND_hifi_cluster_CLK_hifi_dbg_cti_cticlk_STOP_AND_hifi_cluster_CLK_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_cluster_CLK_hifi_dbg_romtable_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_PBCLK_STOP_AND_hifi_cluster_CLK_hifi_core_ATCLK_STOP_AND_hifi_cluster_CLK_hifi_dbg_apbs_pclkm_STOP_AND_hifi_cluster_CLK_hifi_dbg_atbm_clks_STOP_AND_hifi_cluster_CLK_hifi_dbg_cti_cticlk_STOP_AND_hifi_cluster_CLK_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_cluster_CLK_hifi_dbg_romtable_apb_clk_STOP_SHIFT)) & VPU_LPCG_HIFI4_LPCG_HIFI4_0_hifi_cluster_CLK_hifi_core_PBCLK_STOP_AND_hifi_cluster_CLK_hifi_core_ATCLK_STOP_AND_hifi_cluster_CLK_hifi_dbg_apbs_pclkm_STOP_AND_hifi_cluster_CLK_hifi_dbg_atbm_clks_STOP_AND_hifi_cluster_CLK_hifi_dbg_cti_cticlk_STOP_AND_hifi_cluster_CLK_hifi_dbg_cti_pclkdbg_STOP_AND_hifi_cluster_CLK_hifi_dbg_romtable_apb_clk_STOP_MASK)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_28_31_MASK (0xF0000000U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_28_31_SHIFT (28U)
#define VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_28_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_28_31_SHIFT)) & VPU_LPCG_HIFI4_LPCG_HIFI4_0_LPCG_HIFI4_0_reserved_28_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group VPU_LPCG_HIFI4_Register_Masks */


/* VPU_LPCG_HIFI4 - Peripheral instance base addresses */
/** Peripheral VPU__LPCG_HIFI4 base address */
#define VPU__LPCG_HIFI4_BASE                     (0x2D150000u)
/** Peripheral VPU__LPCG_HIFI4 base pointer */
#define VPU__LPCG_HIFI4                          ((VPU_LPCG_HIFI4_Type *)VPU__LPCG_HIFI4_BASE)
/** Array initializer of VPU_LPCG_HIFI4 peripheral base addresses */
#define VPU_LPCG_HIFI4_BASE_ADDRS                { VPU__LPCG_HIFI4_BASE }
/** Array initializer of VPU_LPCG_HIFI4 peripheral base pointers */
#define VPU_LPCG_HIFI4_BASE_PTRS                 { VPU__LPCG_HIFI4 }

/*!
 * @}
 */ /* end of group VPU_LPCG_HIFI4_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VPU_LPCG_MFD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_MFD_Peripheral_Access_Layer VPU_LPCG_MFD Peripheral Access Layer
 * @{
 */

/** VPU_LPCG_MFD - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MFD_0;                        /**< na, offset: 0x0 */
} VPU_LPCG_MFD_Type;

/* ----------------------------------------------------------------------------
   -- VPU_LPCG_MFD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_MFD_Register_Masks VPU_LPCG_MFD Register Masks
 * @{
 */

/*! @name LPCG_MFD_0 - na */
/*! @{ */
#define VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_16_MASK (0x1FFFFU)
#define VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_16_SHIFT (0U)
#define VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_16_SHIFT)) & VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_0_16_MASK)
#define VPU_LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_SWEN_AND_med_dec_mfd_sys_clk_gated_SWEN_MASK (0x20000U)
#define VPU_LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_SWEN_AND_med_dec_mfd_sys_clk_gated_SWEN_SHIFT (17U)
#define VPU_LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_SWEN_AND_med_dec_mfd_sys_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_SWEN_AND_med_dec_mfd_sys_clk_gated_SWEN_SHIFT)) & VPU_LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_SWEN_AND_med_dec_mfd_sys_clk_gated_SWEN_MASK)
#define VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_18_18_MASK (0x40000U)
#define VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_18_18_SHIFT (18U)
#define VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_18_18_SHIFT)) & VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_18_18_MASK)
#define VPU_LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_STOP_AND_med_dec_mfd_sys_clk_gated_STOP_MASK (0x80000U)
#define VPU_LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_STOP_AND_med_dec_mfd_sys_clk_gated_STOP_SHIFT (19U)
#define VPU_LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_STOP_AND_med_dec_mfd_sys_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_STOP_AND_med_dec_mfd_sys_clk_gated_STOP_SHIFT)) & VPU_LPCG_MFD_LPCG_MFD_0_med_dec_mfd_sys_clk_STOP_AND_med_dec_mfd_sys_clk_gated_STOP_MASK)
#define VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_20_31_MASK (0xFFF00000U)
#define VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_20_31_SHIFT (20U)
#define VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_20_31_SHIFT)) & VPU_LPCG_MFD_LPCG_MFD_0_LPCG_MFD_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group VPU_LPCG_MFD_Register_Masks */


/* VPU_LPCG_MFD - Peripheral instance base addresses */
/** Peripheral VPU__LPCG_MFD base address */
#define VPU__LPCG_MFD_BASE                       (0x2D0F0000u)
/** Peripheral VPU__LPCG_MFD base pointer */
#define VPU__LPCG_MFD                            ((VPU_LPCG_MFD_Type *)VPU__LPCG_MFD_BASE)
/** Array initializer of VPU_LPCG_MFD peripheral base addresses */
#define VPU_LPCG_MFD_BASE_ADDRS                  { VPU__LPCG_MFD_BASE }
/** Array initializer of VPU_LPCG_MFD peripheral base pointers */
#define VPU_LPCG_MFD_BASE_PTRS                   { VPU__LPCG_MFD }

/*!
 * @}
 */ /* end of group VPU_LPCG_MFD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VPU_LPCG_MPGD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_MPGD_Peripheral_Access_Layer VPU_LPCG_MPGD Peripheral Access Layer
 * @{
 */

/** VPU_LPCG_MPGD - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_MPGD_0;                       /**< na, offset: 0x0 */
} VPU_LPCG_MPGD_Type;

/* ----------------------------------------------------------------------------
   -- VPU_LPCG_MPGD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_MPGD_Register_Masks VPU_LPCG_MPGD Register Masks
 * @{
 */

/*! @name LPCG_MPGD_0 - na */
/*! @{ */
#define VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_16_MASK (0x1FFFFU)
#define VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_16_SHIFT (0U)
#define VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_16_SHIFT)) & VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_0_16_MASK)
#define VPU_LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN_MASK (0x20000U)
#define VPU_LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN_SHIFT (17U)
#define VPU_LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN_SHIFT)) & VPU_LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_SWEN_MASK)
#define VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_18_18_MASK (0x40000U)
#define VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_18_18_SHIFT (18U)
#define VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_18_18_SHIFT)) & VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_18_18_MASK)
#define VPU_LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP_MASK (0x80000U)
#define VPU_LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP_SHIFT (19U)
#define VPU_LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP_SHIFT)) & VPU_LPCG_MPGD_LPCG_MPGD_0_med_dec_mfd_mpgd_clk_gated_STOP_MASK)
#define VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_20_31_MASK (0xFFF00000U)
#define VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_20_31_SHIFT (20U)
#define VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_20_31_SHIFT)) & VPU_LPCG_MPGD_LPCG_MPGD_0_LPCG_MPGD_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group VPU_LPCG_MPGD_Register_Masks */


/* VPU_LPCG_MPGD - Peripheral instance base addresses */
/** Peripheral VPU__LPCG_MPGD base address */
#define VPU__LPCG_MPGD_BASE                      (0x2D120000u)
/** Peripheral VPU__LPCG_MPGD base pointer */
#define VPU__LPCG_MPGD                           ((VPU_LPCG_MPGD_Type *)VPU__LPCG_MPGD_BASE)
/** Array initializer of VPU_LPCG_MPGD peripheral base addresses */
#define VPU_LPCG_MPGD_BASE_ADDRS                 { VPU__LPCG_MPGD_BASE }
/** Array initializer of VPU_LPCG_MPGD peripheral base pointers */
#define VPU_LPCG_MPGD_BASE_PTRS                  { VPU__LPCG_MPGD }

/*!
 * @}
 */ /* end of group VPU_LPCG_MPGD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VPU_LPCG_OCRAM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_OCRAM_Peripheral_Access_Layer VPU_LPCG_OCRAM Peripheral Access Layer
 * @{
 */

/** VPU_LPCG_OCRAM - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_OCRAM_0;                      /**< na, offset: 0x0 */
} VPU_LPCG_OCRAM_Type;

/* ----------------------------------------------------------------------------
   -- VPU_LPCG_OCRAM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_OCRAM_Register_Masks VPU_LPCG_OCRAM Register Masks
 * @{
 */

/*! @name LPCG_OCRAM_0 - na */
/*! @{ */
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_16_MASK (0x1FFFFU)
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_16_SHIFT (0U)
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_16_SHIFT)) & VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_0_16_MASK)
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_hifi_cluster_CLK_ocram_ctrl_clk_SWEN_AND_hifi_cluster_CLK_ocram_mem_clk_SWEN_MASK (0x20000U)
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_hifi_cluster_CLK_ocram_ctrl_clk_SWEN_AND_hifi_cluster_CLK_ocram_mem_clk_SWEN_SHIFT (17U)
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_hifi_cluster_CLK_ocram_ctrl_clk_SWEN_AND_hifi_cluster_CLK_ocram_mem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_OCRAM_LPCG_OCRAM_0_hifi_cluster_CLK_ocram_ctrl_clk_SWEN_AND_hifi_cluster_CLK_ocram_mem_clk_SWEN_SHIFT)) & VPU_LPCG_OCRAM_LPCG_OCRAM_0_hifi_cluster_CLK_ocram_ctrl_clk_SWEN_AND_hifi_cluster_CLK_ocram_mem_clk_SWEN_MASK)
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_18_18_MASK (0x40000U)
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_18_18_SHIFT (18U)
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_18_18_SHIFT)) & VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_18_18_MASK)
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_hifi_cluster_CLK_ocram_ctrl_clk_STOP_AND_hifi_cluster_CLK_ocram_mem_clk_STOP_MASK (0x80000U)
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_hifi_cluster_CLK_ocram_ctrl_clk_STOP_AND_hifi_cluster_CLK_ocram_mem_clk_STOP_SHIFT (19U)
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_hifi_cluster_CLK_ocram_ctrl_clk_STOP_AND_hifi_cluster_CLK_ocram_mem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_OCRAM_LPCG_OCRAM_0_hifi_cluster_CLK_ocram_ctrl_clk_STOP_AND_hifi_cluster_CLK_ocram_mem_clk_STOP_SHIFT)) & VPU_LPCG_OCRAM_LPCG_OCRAM_0_hifi_cluster_CLK_ocram_ctrl_clk_STOP_AND_hifi_cluster_CLK_ocram_mem_clk_STOP_MASK)
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_20_31_MASK (0xFFF00000U)
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_20_31_SHIFT (20U)
#define VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_20_31_SHIFT)) & VPU_LPCG_OCRAM_LPCG_OCRAM_0_LPCG_OCRAM_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group VPU_LPCG_OCRAM_Register_Masks */


/* VPU_LPCG_OCRAM - Peripheral instance base addresses */
/** Peripheral VPU__LPCG_OCRAM base address */
#define VPU__LPCG_OCRAM_BASE                     (0x2D160000u)
/** Peripheral VPU__LPCG_OCRAM base pointer */
#define VPU__LPCG_OCRAM                          ((VPU_LPCG_OCRAM_Type *)VPU__LPCG_OCRAM_BASE)
/** Array initializer of VPU_LPCG_OCRAM peripheral base addresses */
#define VPU_LPCG_OCRAM_BASE_ADDRS                { VPU__LPCG_OCRAM_BASE }
/** Array initializer of VPU_LPCG_OCRAM peripheral base pointers */
#define VPU_LPCG_OCRAM_BASE_PTRS                 { VPU__LPCG_OCRAM }

/*!
 * @}
 */ /* end of group VPU_LPCG_OCRAM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VPU_LPCG_VC1D Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_VC1D_Peripheral_Access_Layer VPU_LPCG_VC1D Peripheral Access Layer
 * @{
 */

/** VPU_LPCG_VC1D - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_VC1D_0;                       /**< na, offset: 0x0 */
} VPU_LPCG_VC1D_Type;

/* ----------------------------------------------------------------------------
   -- VPU_LPCG_VC1D Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_VC1D_Register_Masks VPU_LPCG_VC1D Register Masks
 * @{
 */

/*! @name LPCG_VC1D_0 - na */
/*! @{ */
#define VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_16_MASK (0x1FFFFU)
#define VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_16_SHIFT (0U)
#define VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_16_SHIFT)) & VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_0_16_MASK)
#define VPU_LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN_MASK (0x20000U)
#define VPU_LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN_SHIFT (17U)
#define VPU_LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN_SHIFT)) & VPU_LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_SWEN_MASK)
#define VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_18_18_MASK (0x40000U)
#define VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_18_18_SHIFT (18U)
#define VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_18_18_SHIFT)) & VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_18_18_MASK)
#define VPU_LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP_MASK (0x80000U)
#define VPU_LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP_SHIFT (19U)
#define VPU_LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP_SHIFT)) & VPU_LPCG_VC1D_LPCG_VC1D_0_med_dec_mfd_vc1d_clk_gated_STOP_MASK)
#define VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_20_31_MASK (0xFFF00000U)
#define VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_20_31_SHIFT (20U)
#define VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_20_31_SHIFT)) & VPU_LPCG_VC1D_LPCG_VC1D_0_LPCG_VC1D_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group VPU_LPCG_VC1D_Register_Masks */


/* VPU_LPCG_VC1D - Peripheral instance base addresses */
/** Peripheral VPU__LPCG_VC1D base address */
#define VPU__LPCG_VC1D_BASE                      (0x2D110000u)
/** Peripheral VPU__LPCG_VC1D base pointer */
#define VPU__LPCG_VC1D                           ((VPU_LPCG_VC1D_Type *)VPU__LPCG_VC1D_BASE)
/** Array initializer of VPU_LPCG_VC1D peripheral base addresses */
#define VPU_LPCG_VC1D_BASE_ADDRS                 { VPU__LPCG_VC1D_BASE }
/** Array initializer of VPU_LPCG_VC1D peripheral base pointers */
#define VPU_LPCG_VC1D_BASE_PTRS                  { VPU__LPCG_VC1D }

/*!
 * @}
 */ /* end of group VPU_LPCG_VC1D_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VPU_LPCG_XUVI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_XUVI_Peripheral_Access_Layer VPU_LPCG_XUVI Peripheral Access Layer
 * @{
 */

/** VPU_LPCG_XUVI - Register Layout Typedef */
typedef struct {
  __IO uint32_t LPCG_XUVI_0;                       /**< na, offset: 0x0 */
} VPU_LPCG_XUVI_Type;

/* ----------------------------------------------------------------------------
   -- VPU_LPCG_XUVI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VPU_LPCG_XUVI_Register_Masks VPU_LPCG_XUVI Register Masks
 * @{
 */

/*! @name LPCG_XUVI_0 - na */
/*! @{ */
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_0_0_MASK (0x1U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_0_0_SHIFT (0U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_0_0_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_0_0_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_stc0_clk_SWEN_AND_xuvi_top_stc1_clk_SWEN_AND_xuvi_top_stc2_clk_SWEN_MASK (0x2U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_stc0_clk_SWEN_AND_xuvi_top_stc1_clk_SWEN_AND_xuvi_top_stc2_clk_SWEN_SHIFT (1U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_stc0_clk_SWEN_AND_xuvi_top_stc1_clk_SWEN_AND_xuvi_top_stc2_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_stc0_clk_SWEN_AND_xuvi_top_stc1_clk_SWEN_AND_xuvi_top_stc2_clk_SWEN_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_stc0_clk_SWEN_AND_xuvi_top_stc1_clk_SWEN_AND_xuvi_top_stc2_clk_SWEN_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_2_2_MASK (0x4U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_2_2_SHIFT (2U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_2_2_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_2_2_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_stc0_clk_STOP_AND_xuvi_top_stc1_clk_STOP_AND_xuvi_top_stc2_clk_STOP_MASK (0x8U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_stc0_clk_STOP_AND_xuvi_top_stc1_clk_STOP_AND_xuvi_top_stc2_clk_STOP_SHIFT (3U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_stc0_clk_STOP_AND_xuvi_top_stc1_clk_STOP_AND_xuvi_top_stc2_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_stc0_clk_STOP_AND_xuvi_top_stc1_clk_STOP_AND_xuvi_top_stc2_clk_STOP_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_stc0_clk_STOP_AND_xuvi_top_stc1_clk_STOP_AND_xuvi_top_stc2_clk_STOP_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_4_4_MASK (0x10U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_4_4_SHIFT (4U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_4_4_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_4_4_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_video_clk_SWEN_MASK (0x20U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_video_clk_SWEN_SHIFT (5U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_video_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_video_clk_SWEN_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_video_clk_SWEN_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_6_6_MASK (0x40U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_6_6_SHIFT (6U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_6_6_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_6_6_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_video_clk_STOP_MASK (0x80U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_video_clk_STOP_SHIFT (7U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_video_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_video_clk_STOP_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_video_clk_STOP_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_8_8_MASK (0x100U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_8_8_SHIFT (8U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_8_8_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_8_8_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_audio_clk_SWEN_MASK (0x200U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_audio_clk_SWEN_SHIFT (9U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_audio_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_audio_clk_SWEN_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_audio_clk_SWEN_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_10_10_MASK (0x400U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_10_10_SHIFT (10U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_10_10_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_10_10_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_audio_clk_STOP_MASK (0x800U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_audio_clk_STOP_SHIFT (11U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_audio_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_audio_clk_STOP_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_audio_clk_STOP_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_12_16_MASK (0x1F000U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_12_16_SHIFT (12U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_12_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_12_16_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_12_16_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_sys_clk_SWEN_MASK (0x20000U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_sys_clk_SWEN_SHIFT (17U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_sys_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_sys_clk_SWEN_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_sys_clk_SWEN_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_18_18_MASK (0x40000U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_18_18_SHIFT (18U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_18_18_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_18_18_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_sys_clk_STOP_MASK (0x80000U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_sys_clk_STOP_SHIFT (19U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_sys_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_sys_clk_STOP_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_xuvi_top_sys_clk_STOP_MASK)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_20_31_MASK (0xFFF00000U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_20_31_SHIFT (20U)
#define VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_20_31_SHIFT)) & VPU_LPCG_XUVI_LPCG_XUVI_0_LPCG_XUVI_0_reserved_20_31_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group VPU_LPCG_XUVI_Register_Masks */


/* VPU_LPCG_XUVI - Peripheral instance base addresses */
/** Peripheral VPU__LPCG_XUVI base address */
#define VPU__LPCG_XUVI_BASE                      (0x2D140000u)
/** Peripheral VPU__LPCG_XUVI base pointer */
#define VPU__LPCG_XUVI                           ((VPU_LPCG_XUVI_Type *)VPU__LPCG_XUVI_BASE)
/** Array initializer of VPU_LPCG_XUVI peripheral base addresses */
#define VPU_LPCG_XUVI_BASE_ADDRS                 { VPU__LPCG_XUVI_BASE }
/** Array initializer of VPU_LPCG_XUVI peripheral base pointers */
#define VPU_LPCG_XUVI_BASE_PTRS                  { VPU__LPCG_XUVI }

/*!
 * @}
 */ /* end of group VPU_LPCG_XUVI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- WDOG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
 * @{
 */

/** WDOG - Register Layout Typedef */
typedef struct {
  __IO uint32_t CS;                                /**< Watchdog Control and Status Register, offset: 0x0 */
  __IO uint32_t CNT;                               /**< Watchdog Counter Register, offset: 0x4 */
  __IO uint32_t TOVAL;                             /**< Watchdog Timeout Value Register, offset: 0x8 */
  __IO uint32_t WIN;                               /**< Watchdog Window Register, offset: 0xC */
} WDOG_Type;

/* ----------------------------------------------------------------------------
   -- WDOG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WDOG_Register_Masks WDOG Register Masks
 * @{
 */

/*! @name CS - Watchdog Control and Status Register */
/*! @{ */
#define WDOG_CS_STOP_MASK                        (0x1U)
#define WDOG_CS_STOP_SHIFT                       (0U)
/*! STOP - Stop Enable
 *  0b0..Watchdog disabled in chip stop mode.
 *  0b1..Watchdog enabled in chip stop mode.
 */
#define WDOG_CS_STOP(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK)
#define WDOG_CS_WAIT_MASK                        (0x2U)
#define WDOG_CS_WAIT_SHIFT                       (1U)
/*! WAIT - Wait Enable
 *  0b0..Watchdog disabled in chip wait mode.
 *  0b1..Watchdog enabled in chip wait mode.
 */
#define WDOG_CS_WAIT(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK)
#define WDOG_CS_DBG_MASK                         (0x4U)
#define WDOG_CS_DBG_SHIFT                        (2U)
/*! DBG - Debug Enable
 *  0b0..Watchdog disabled in chip debug mode.
 *  0b1..Watchdog enabled in chip debug mode.
 */
#define WDOG_CS_DBG(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK)
#define WDOG_CS_TST_MASK                         (0x18U)
#define WDOG_CS_TST_SHIFT                        (3U)
/*! TST - Watchdog Test
 *  0b00..Watchdog test mode disabled.
 *  0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode.
 *  0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
 *  0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
 */
#define WDOG_CS_TST(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK)
#define WDOG_CS_UPDATE_MASK                      (0x20U)
#define WDOG_CS_UPDATE_SHIFT                     (5U)
/*! UPDATE - Allow updates
 *  0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
 *  0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.
 */
#define WDOG_CS_UPDATE(x)                        (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK)
#define WDOG_CS_INT_MASK                         (0x40U)
#define WDOG_CS_INT_SHIFT                        (6U)
/*! INT - Watchdog Interrupt
 *  0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
 *  0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch.
 */
#define WDOG_CS_INT(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK)
#define WDOG_CS_EN_MASK                          (0x80U)
#define WDOG_CS_EN_SHIFT                         (7U)
/*! EN - Watchdog Enable
 *  0b0..Watchdog disabled.
 *  0b1..Watchdog enabled.
 */
#define WDOG_CS_EN(x)                            (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK)
#define WDOG_CS_CLK_MASK                         (0x300U)
#define WDOG_CS_CLK_SHIFT                        (8U)
/*! CLK - Watchdog Clock
 *  0b00..Bus clock
 *  0b01..LPO clock
 *  0b10..INTCLK (internal clock)
 *  0b11..ERCLK (external reference clock)
 */
#define WDOG_CS_CLK(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK)
#define WDOG_CS_RCS_MASK                         (0x400U)
#define WDOG_CS_RCS_SHIFT                        (10U)
/*! RCS - Reconfiguration Success
 *  0b0..Reconfiguring WDOG.
 *  0b1..Reconfiguration is successful.
 */
#define WDOG_CS_RCS(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK)
#define WDOG_CS_ULK_MASK                         (0x800U)
#define WDOG_CS_ULK_SHIFT                        (11U)
/*! ULK - Unlock status
 *  0b0..WDOG is locked.
 *  0b1..WDOG is unlocked.
 */
#define WDOG_CS_ULK(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK)
#define WDOG_CS_PRES_MASK                        (0x1000U)
#define WDOG_CS_PRES_SHIFT                       (12U)
/*! PRES - Watchdog prescaler
 *  0b0..256 prescaler disabled.
 *  0b1..256 prescaler enabled.
 */
#define WDOG_CS_PRES(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK)
#define WDOG_CS_CMD32EN_MASK                     (0x2000U)
#define WDOG_CS_CMD32EN_SHIFT                    (13U)
/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
 *  0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
 *  0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
 */
#define WDOG_CS_CMD32EN(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK)
#define WDOG_CS_FLG_MASK                         (0x4000U)
#define WDOG_CS_FLG_SHIFT                        (14U)
/*! FLG - Watchdog Interrupt Flag
 *  0b0..No interrupt occurred.
 *  0b1..An interrupt occurred.
 */
#define WDOG_CS_FLG(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK)
#define WDOG_CS_WIN_MASK                         (0x8000U)
#define WDOG_CS_WIN_SHIFT                        (15U)
/*! WIN - Watchdog Window
 *  0b0..Window mode disabled.
 *  0b1..Window mode enabled.
 */
#define WDOG_CS_WIN(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK)
/*! @} */

/*! @name CNT - Watchdog Counter Register */
/*! @{ */
#define WDOG_CNT_CNTLOW_MASK                     (0xFFU)
#define WDOG_CNT_CNTLOW_SHIFT                    (0U)
#define WDOG_CNT_CNTLOW(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK)
#define WDOG_CNT_CNTHIGH_MASK                    (0xFF00U)
#define WDOG_CNT_CNTHIGH_SHIFT                   (8U)
#define WDOG_CNT_CNTHIGH(x)                      (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK)
/*! @} */

/*! @name TOVAL - Watchdog Timeout Value Register */
/*! @{ */
#define WDOG_TOVAL_TOVALLOW_MASK                 (0xFFU)
#define WDOG_TOVAL_TOVALLOW_SHIFT                (0U)
#define WDOG_TOVAL_TOVALLOW(x)                   (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK)
#define WDOG_TOVAL_TOVALHIGH_MASK                (0xFF00U)
#define WDOG_TOVAL_TOVALHIGH_SHIFT               (8U)
#define WDOG_TOVAL_TOVALHIGH(x)                  (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK)
/*! @} */

/*! @name WIN - Watchdog Window Register */
/*! @{ */
#define WDOG_WIN_WINLOW_MASK                     (0xFFU)
#define WDOG_WIN_WINLOW_SHIFT                    (0U)
#define WDOG_WIN_WINLOW(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK)
#define WDOG_WIN_WINHIGH_MASK                    (0xFF00U)
#define WDOG_WIN_WINHIGH_SHIFT                   (8U)
#define WDOG_WIN_WINHIGH(x)                      (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group WDOG_Register_Masks */


/* WDOG - Peripheral instance base addresses */
/** Peripheral CM4_0__WDOG base address */
#define CM4_0__WDOG_BASE                         (0x37420000u)
/** Peripheral CM4_0__WDOG base pointer */
#define CM4_0__WDOG                              ((WDOG_Type *)CM4_0__WDOG_BASE)
/** Peripheral CM4_1__WDOG base address */
#define CM4_1__WDOG_BASE                         (0x41420000u)
/** Peripheral CM4_1__WDOG base pointer */
#define CM4_1__WDOG                              ((WDOG_Type *)CM4_1__WDOG_BASE)
/** Peripheral SCU__WDOG base address */
#define SCU__WDOG_BASE                           (0x33420000u)
/** Peripheral SCU__WDOG base pointer */
#define SCU__WDOG                                ((WDOG_Type *)SCU__WDOG_BASE)
/** Array initializer of WDOG peripheral base addresses */
#define WDOG_BASE_ADDRS                          { CM4_0__WDOG_BASE, CM4_1__WDOG_BASE, SCU__WDOG_BASE }
/** Array initializer of WDOG peripheral base pointers */
#define WDOG_BASE_PTRS                           { CM4_0__WDOG, CM4_1__WDOG, SCU__WDOG }
/* Extra definition */
#define WDOG_UPDATE_KEY                          (0xD928C520U)
#define WDOG_REFRESH_KEY                         (0xB480A602U)


/*!
 * @}
 */ /* end of group WDOG_Peripheral_Access_Layer */


/*
** End of section using anonymous unions
*/

#if defined(__ARMCC_VERSION)
  #pragma pop
#elif defined(__GNUC__)
  /* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma language=default
#else
  #error Not supported compiler type
#endif

/*!
 * @}
 */ /* end of group Peripheral_access_layer */


/* ----------------------------------------------------------------------------
   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
 * @{
 */

#if defined(__ARMCC_VERSION)
  #if (__ARMCC_VERSION >= 6010050)
    #pragma clang system_header
  #endif
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma system_include
#endif

/**
 * @brief Mask and left-shift a bit field value for use in a register bit range.
 * @param field Name of the register bit field.
 * @param value Value of the bit field.
 * @return Masked and shifted value.
 */
#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
/**
 * @brief Mask and right-shift a register value to extract a bit field value.
 * @param field Name of the register bit field.
 * @param value Value of the register.
 * @return Masked and shifted bit field value.
 */
#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))

/*!
 * @}
 */ /* end of group Bit_Field_Generic_Macros */


/* ----------------------------------------------------------------------------
   -- SDK Compatibility
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
 * @{
 */

/* No SDK compatibility issues. */

/*!
 * @}
 */ /* end of group SDK_Compatibility_Symbols */


#endif  /* _MIMX8QM6_CM4_CORE1_H_ */

